From bce22974180e05a30122bc3e0fcf264be943323d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 14 Nov 2021 09:02:53 +0100 Subject: [PATCH] cpu/eos_s3: Put wishbone bus in periph_buses and avoid specific integration. --- litex/soc/cores/cpu/eos_s3/core.py | 24 +++++++++++------------- litex/soc/integration/soc.py | 16 +++++----------- 2 files changed, 16 insertions(+), 24 deletions(-) diff --git a/litex/soc/cores/cpu/eos_s3/core.py b/litex/soc/cores/cpu/eos_s3/core.py index f00efd068f..d0ab228853 100644 --- a/litex/soc/cores/cpu/eos_s3/core.py +++ b/litex/soc/cores/cpu/eos_s3/core.py @@ -37,13 +37,11 @@ def __init__(self, platform, variant): self.platform = platform self.reset = Signal() self.interrupt = Signal(4) - self.periph_buses = [] # Peripheral buses (Connected to main SoC's bus). - self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). - - self.wishbone_master = [] # General Purpose Wishbone Masters. + self.pbus = wishbone.Interface(data_width=32, adr_width=15) + self.periph_buses = [self.pbus] + self.memory_buses = [] # # # - self.wb = wishbone.Interface(data_width=32, adr_width=15) # EOS-S3 Clocking. self.clock_domains.cd_Sys_Clk0 = ClockDomain() @@ -58,15 +56,15 @@ def __init__(self, platform, variant): # AHB-To-FPGA Bridge i_WB_CLK = ClockSignal("Sys_Clk0"), o_WB_RST = WB_RST, - o_WBs_ADR = Cat(Signal(2), self.wb.adr), - o_WBs_CYC = self.wb.cyc, - o_WBs_BYTE_STB = self.wb.sel, - o_WBs_WE = self.wb.we, - o_WBs_STB = self.wb.stb, + o_WBs_ADR = Cat(Signal(2), self.pbus.adr), + o_WBs_CYC = self.pbus.cyc, + o_WBs_BYTE_STB = self.pbus.sel, + o_WBs_WE = self.pbus.we, + o_WBs_STB = self.pbus.stb, #o_WBs_RD"(), = // output | Read Enable to FPGA - o_WBs_WR_DAT = self.wb.dat_w, - i_WBs_RD_DAT = self.wb.dat_r, - i_WBs_ACK = self.wb.ack, + o_WBs_WR_DAT = self.pbus.dat_w, + i_WBs_RD_DAT = self.pbus.dat_r, + i_WBs_ACK = self.pbus.ack, # SDMA Signals #SDMA_Req(4'b0000), #SDMA_Sreq(4'b0000), diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 8c9d6fcb73..55fca921ee 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -924,17 +924,11 @@ def add_cpu(self, name="vexriscv", variant="standard", cls=None, reset_address=N self.mem_map.update(self.cpu.mem_map) # Add Bus Masters/CSR/IRQs. - if isinstance(self.cpu, cpu.EOS_S3): - self.bus.add_master(master=self.cpu.wb) - if hasattr(self.cpu, "interrupt"): - self.irq.enable() - for name, loc in self.cpu.interrupts.items(): - self.irq.add(name, loc) - self.add_config("CPU_HAS_INTERRUPT") - if not isinstance(self.cpu, (cpu.CPUNone, cpu.Zynq7000, cpu.EOS_S3)): - if reset_address is None: - reset_address = self.mem_map["rom"] - self.cpu.set_reset_address(reset_address) + if not isinstance(self.cpu, (cpu.CPUNone, cpu.Zynq7000)): + if hasattr(cpu, "set_reset_address"): + if reset_address is None: + reset_address = self.mem_map["rom"] + self.cpu.set_reset_address(reset_address) for n, cpu_bus in enumerate(self.cpu.periph_buses): self.bus.add_master(name="cpu_bus{}".format(n), master=cpu_bus) if hasattr(self.cpu, "interrupt"):