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When 'reset' is active the write signal 'WE' is also active. This means some memory corruption during reset (but confined to the stack page)
These write cycles shouldn't be a problem unless the clock frequency is out of specs (but this can happen during PLL startups), and the boot memory is writable.
I think the real 6502 also modifies the stack pointer during resets but its R/W signal is forced high, disabling writes.
A possible patch is to change the following line...:
/*
Write Enable Generator
*/
always @*
case( state )
BRK0, // writing to stack or memory
BRK1,
BRK2,
JSR0,
JSR1,
PUSH1,
WRITE: WE = ~(reset|res); // (before it was: WE = 1;)
INDX3, // only if doing a STA, STX or STY
INDY3,
ABSX2,
ABS1,
ZPX1,
ZP0: WE = store;
default: WE = 0;
endcase
The text was updated successfully, but these errors were encountered:
When 'reset' is active the write signal 'WE' is also active. This means some memory corruption during reset (but confined to the stack page)
These write cycles shouldn't be a problem unless the clock frequency is out of specs (but this can happen during PLL startups), and the boot memory is writable.
I think the real 6502 also modifies the stack pointer during resets but its R/W signal is forced high, disabling writes.
A possible patch is to change the following line...:
/*
*/
always @*
case( state )
BRK0, // writing to stack or memory
BRK1,
BRK2,
JSR0,
JSR1,
PUSH1,
WRITE: WE = ~(reset|res); // (before it was: WE = 1;)
The text was updated successfully, but these errors were encountered: