-
Notifications
You must be signed in to change notification settings - Fork 4
/
cpuops.cpp
4018 lines (3396 loc) · 116 KB
/
cpuops.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/***********************************************************************************
Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
(c) Copyright 1996 - 2002 Gary Henderson ([email protected]),
Jerremy Koot ([email protected])
(c) Copyright 2002 - 2004 Matthew Kendora
(c) Copyright 2002 - 2005 Peter Bortas ([email protected])
(c) Copyright 2004 - 2005 Joel Yliluoma (http://iki.fi/bisqwit/)
(c) Copyright 2001 - 2006 John Weidman ([email protected])
(c) Copyright 2002 - 2006 funkyass ([email protected]),
Kris Bleakley ([email protected])
(c) Copyright 2002 - 2010 Brad Jorsch ([email protected]),
Nach ([email protected]),
zones ([email protected])
(c) Copyright 2006 - 2007 nitsuja
(c) Copyright 2009 - 2010 BearOso,
OV2
BS-X C emulator code
(c) Copyright 2005 - 2006 Dreamer Nom,
zones
C4 x86 assembler and some C emulation code
(c) Copyright 2000 - 2003 _Demo_ ([email protected]),
Nach,
zsKnight ([email protected])
C4 C++ code
(c) Copyright 2003 - 2006 Brad Jorsch,
Nach
DSP-1 emulator code
(c) Copyright 1998 - 2006 _Demo_,
Andreas Naive ([email protected]),
Gary Henderson,
Ivar ([email protected]),
John Weidman,
Kris Bleakley,
Matthew Kendora,
Nach,
neviksti ([email protected])
DSP-2 emulator code
(c) Copyright 2003 John Weidman,
Kris Bleakley,
Lord Nightmare ([email protected]),
Matthew Kendora,
neviksti
DSP-3 emulator code
(c) Copyright 2003 - 2006 John Weidman,
Kris Bleakley,
Lancer,
z80 gaiden
DSP-4 emulator code
(c) Copyright 2004 - 2006 Dreamer Nom,
John Weidman,
Kris Bleakley,
Nach,
z80 gaiden
OBC1 emulator code
(c) Copyright 2001 - 2004 zsKnight,
pagefault ([email protected]),
Kris Bleakley
Ported from x86 assembler to C by sanmaiwashi
SPC7110 and RTC C++ emulator code used in 1.39-1.51
(c) Copyright 2002 Matthew Kendora with research by
zsKnight,
John Weidman,
Dark Force
SPC7110 and RTC C++ emulator code used in 1.52+
(c) Copyright 2009 byuu,
neviksti
S-DD1 C emulator code
(c) Copyright 2003 Brad Jorsch with research by
Andreas Naive,
John Weidman
S-RTC C emulator code
(c) Copyright 2001 - 2006 byuu,
John Weidman
ST010 C++ emulator code
(c) Copyright 2003 Feather,
John Weidman,
Kris Bleakley,
Matthew Kendora
Super FX x86 assembler emulator code
(c) Copyright 1998 - 2003 _Demo_,
pagefault,
zsKnight
Super FX C emulator code
(c) Copyright 1997 - 1999 Ivar,
Gary Henderson,
John Weidman
Sound emulator code used in 1.5-1.51
(c) Copyright 1998 - 2003 Brad Martin
(c) Copyright 1998 - 2006 Charles Bilyue'
Sound emulator code used in 1.52+
(c) Copyright 2004 - 2007 Shay Green ([email protected])
SH assembler code partly based on x86 assembler code
(c) Copyright 2002 - 2004 Marcus Comstedt ([email protected])
2xSaI filter
(c) Copyright 1999 - 2001 Derek Liauw Kie Fa
HQ2x, HQ3x, HQ4x filters
(c) Copyright 2003 Maxim Stepin ([email protected])
NTSC filter
(c) Copyright 2006 - 2007 Shay Green
GTK+ GUI code
(c) Copyright 2004 - 2010 BearOso
Win32 GUI code
(c) Copyright 2003 - 2006 blip,
funkyass,
Matthew Kendora,
Nach,
nitsuja
(c) Copyright 2009 - 2010 OV2
Mac OS GUI code
(c) Copyright 1998 - 2001 John Stiles
(c) Copyright 2001 - 2010 zones
Specific ports contains the works of other authors. See headers in
individual files.
Snes9x homepage: http://www.snes9x.com/
Permission to use, copy, modify and/or distribute Snes9x in both binary
and source form, for non-commercial purposes, is hereby granted without
fee, providing that this license information and copyright notice appear
with all copies and any derived work.
This software is provided 'as-is', without any express or implied
warranty. In no event shall the authors be held liable for any damages
arising from the use of this software or it's derivatives.
Snes9x is freeware for PERSONAL USE only. Commercial users should
seek permission of the copyright holders first. Commercial use includes,
but is not limited to, charging money for Snes9x or software derived from
Snes9x, including Snes9x or derivatives in commercial game bundles, and/or
using Snes9x as a promotion for your commercial product.
The copyright holders request that bug fixes and improvements to the code
should be forwarded to them so everyone can benefit from the modifications
in future versions.
Super NES and Super Nintendo Entertainment System are trademarks of
Nintendo Co., Limited and its subsidiary companies.
***********************************************************************************/
#include "snes9x.h"
#include "memmap.h"
#include "apu/apu.h"
// for "Magic WDM" features
#ifdef DEBUGGER
#include "snapshot.h"
#include "display.h"
#include "debug.h"
#include "missing.h"
#endif
#ifdef SA1_OPCODES
#define AddCycles(n) { }
#else
#if (S9X_ACCURACY_LEVEL >= 3)
#define AddCycles(n) { CPU.Cycles += (n); while (CPU.Cycles >= CPU.NextEvent) S9xDoHEventProcessing(); }
#else
#define AddCycles(n) { CPU.Cycles += (n); }
#endif
#endif
#include "cpuaddr.h"
#include "cpuops.h"
#include "cpumacro.h"
/* ADC ********************************************************************* */
static void Op69M1 (void)
{
ADC(Immediate8(READ));
}
static void Op69M0 (void)
{
ADC(Immediate16(READ));
}
static void Op69Slow (void)
{
if (CheckMemory())
ADC(Immediate8Slow(READ));
else
ADC(Immediate16Slow(READ));
}
rOP8 (65M1, Direct, WRAP_BANK, ADC)
rOP16(65M0, Direct, WRAP_BANK, ADC)
rOPM (65Slow, DirectSlow, WRAP_BANK, ADC)
rOP8 (75E1, DirectIndexedXE1, WRAP_BANK, ADC)
rOP8 (75E0M1, DirectIndexedXE0, WRAP_BANK, ADC)
rOP16(75E0M0, DirectIndexedXE0, WRAP_BANK, ADC)
rOPM (75Slow, DirectIndexedXSlow, WRAP_BANK, ADC)
rOP8 (72E1, DirectIndirectE1, WRAP_NONE, ADC)
rOP8 (72E0M1, DirectIndirectE0, WRAP_NONE, ADC)
rOP16(72E0M0, DirectIndirectE0, WRAP_NONE, ADC)
rOPM (72Slow, DirectIndirectSlow, WRAP_NONE, ADC)
rOP8 (61E1, DirectIndexedIndirectE1, WRAP_NONE, ADC)
rOP8 (61E0M1, DirectIndexedIndirectE0, WRAP_NONE, ADC)
rOP16(61E0M0, DirectIndexedIndirectE0, WRAP_NONE, ADC)
rOPM (61Slow, DirectIndexedIndirectSlow, WRAP_NONE, ADC)
rOP8 (71E1, DirectIndirectIndexedE1, WRAP_NONE, ADC)
rOP8 (71E0M1X1, DirectIndirectIndexedE0X1, WRAP_NONE, ADC)
rOP16(71E0M0X1, DirectIndirectIndexedE0X1, WRAP_NONE, ADC)
rOP8 (71E0M1X0, DirectIndirectIndexedE0X0, WRAP_NONE, ADC)
rOP16(71E0M0X0, DirectIndirectIndexedE0X0, WRAP_NONE, ADC)
rOPM (71Slow, DirectIndirectIndexedSlow, WRAP_NONE, ADC)
rOP8 (67M1, DirectIndirectLong, WRAP_NONE, ADC)
rOP16(67M0, DirectIndirectLong, WRAP_NONE, ADC)
rOPM (67Slow, DirectIndirectLongSlow, WRAP_NONE, ADC)
rOP8 (77M1, DirectIndirectIndexedLong, WRAP_NONE, ADC)
rOP16(77M0, DirectIndirectIndexedLong, WRAP_NONE, ADC)
rOPM (77Slow, DirectIndirectIndexedLongSlow, WRAP_NONE, ADC)
rOP8 (6DM1, Absolute, WRAP_NONE, ADC)
rOP16(6DM0, Absolute, WRAP_NONE, ADC)
rOPM (6DSlow, AbsoluteSlow, WRAP_NONE, ADC)
rOP8 (7DM1X1, AbsoluteIndexedXX1, WRAP_NONE, ADC)
rOP16(7DM0X1, AbsoluteIndexedXX1, WRAP_NONE, ADC)
rOP8 (7DM1X0, AbsoluteIndexedXX0, WRAP_NONE, ADC)
rOP16(7DM0X0, AbsoluteIndexedXX0, WRAP_NONE, ADC)
rOPM (7DSlow, AbsoluteIndexedXSlow, WRAP_NONE, ADC)
rOP8 (79M1X1, AbsoluteIndexedYX1, WRAP_NONE, ADC)
rOP16(79M0X1, AbsoluteIndexedYX1, WRAP_NONE, ADC)
rOP8 (79M1X0, AbsoluteIndexedYX0, WRAP_NONE, ADC)
rOP16(79M0X0, AbsoluteIndexedYX0, WRAP_NONE, ADC)
rOPM (79Slow, AbsoluteIndexedYSlow, WRAP_NONE, ADC)
rOP8 (6FM1, AbsoluteLong, WRAP_NONE, ADC)
rOP16(6FM0, AbsoluteLong, WRAP_NONE, ADC)
rOPM (6FSlow, AbsoluteLongSlow, WRAP_NONE, ADC)
rOP8 (7FM1, AbsoluteLongIndexedX, WRAP_NONE, ADC)
rOP16(7FM0, AbsoluteLongIndexedX, WRAP_NONE, ADC)
rOPM (7FSlow, AbsoluteLongIndexedXSlow, WRAP_NONE, ADC)
rOP8 (63M1, StackRelative, WRAP_NONE, ADC)
rOP16(63M0, StackRelative, WRAP_NONE, ADC)
rOPM (63Slow, StackRelativeSlow, WRAP_NONE, ADC)
rOP8 (73M1, StackRelativeIndirectIndexed, WRAP_NONE, ADC)
rOP16(73M0, StackRelativeIndirectIndexed, WRAP_NONE, ADC)
rOPM (73Slow, StackRelativeIndirectIndexedSlow, WRAP_NONE, ADC)
/* AND ********************************************************************* */
static void Op29M1 (void)
{
Registers.AL &= Immediate8(READ);
SetZN(Registers.AL);
}
static void Op29M0 (void)
{
Registers.A.W &= Immediate16(READ);
SetZN(Registers.A.W);
}
static void Op29Slow (void)
{
if (CheckMemory())
{
Registers.AL &= Immediate8Slow(READ);
SetZN(Registers.AL);
}
else
{
Registers.A.W &= Immediate16Slow(READ);
SetZN(Registers.A.W);
}
}
rOP8 (25M1, Direct, WRAP_BANK, AND)
rOP16(25M0, Direct, WRAP_BANK, AND)
rOPM (25Slow, DirectSlow, WRAP_BANK, AND)
rOP8 (35E1, DirectIndexedXE1, WRAP_BANK, AND)
rOP8 (35E0M1, DirectIndexedXE0, WRAP_BANK, AND)
rOP16(35E0M0, DirectIndexedXE0, WRAP_BANK, AND)
rOPM (35Slow, DirectIndexedXSlow, WRAP_BANK, AND)
rOP8 (32E1, DirectIndirectE1, WRAP_NONE, AND)
rOP8 (32E0M1, DirectIndirectE0, WRAP_NONE, AND)
rOP16(32E0M0, DirectIndirectE0, WRAP_NONE, AND)
rOPM (32Slow, DirectIndirectSlow, WRAP_NONE, AND)
rOP8 (21E1, DirectIndexedIndirectE1, WRAP_NONE, AND)
rOP8 (21E0M1, DirectIndexedIndirectE0, WRAP_NONE, AND)
rOP16(21E0M0, DirectIndexedIndirectE0, WRAP_NONE, AND)
rOPM (21Slow, DirectIndexedIndirectSlow, WRAP_NONE, AND)
rOP8 (31E1, DirectIndirectIndexedE1, WRAP_NONE, AND)
rOP8 (31E0M1X1, DirectIndirectIndexedE0X1, WRAP_NONE, AND)
rOP16(31E0M0X1, DirectIndirectIndexedE0X1, WRAP_NONE, AND)
rOP8 (31E0M1X0, DirectIndirectIndexedE0X0, WRAP_NONE, AND)
rOP16(31E0M0X0, DirectIndirectIndexedE0X0, WRAP_NONE, AND)
rOPM (31Slow, DirectIndirectIndexedSlow, WRAP_NONE, AND)
rOP8 (27M1, DirectIndirectLong, WRAP_NONE, AND)
rOP16(27M0, DirectIndirectLong, WRAP_NONE, AND)
rOPM (27Slow, DirectIndirectLongSlow, WRAP_NONE, AND)
rOP8 (37M1, DirectIndirectIndexedLong, WRAP_NONE, AND)
rOP16(37M0, DirectIndirectIndexedLong, WRAP_NONE, AND)
rOPM (37Slow, DirectIndirectIndexedLongSlow, WRAP_NONE, AND)
rOP8 (2DM1, Absolute, WRAP_NONE, AND)
rOP16(2DM0, Absolute, WRAP_NONE, AND)
rOPM (2DSlow, AbsoluteSlow, WRAP_NONE, AND)
rOP8 (3DM1X1, AbsoluteIndexedXX1, WRAP_NONE, AND)
rOP16(3DM0X1, AbsoluteIndexedXX1, WRAP_NONE, AND)
rOP8 (3DM1X0, AbsoluteIndexedXX0, WRAP_NONE, AND)
rOP16(3DM0X0, AbsoluteIndexedXX0, WRAP_NONE, AND)
rOPM (3DSlow, AbsoluteIndexedXSlow, WRAP_NONE, AND)
rOP8 (39M1X1, AbsoluteIndexedYX1, WRAP_NONE, AND)
rOP16(39M0X1, AbsoluteIndexedYX1, WRAP_NONE, AND)
rOP8 (39M1X0, AbsoluteIndexedYX0, WRAP_NONE, AND)
rOP16(39M0X0, AbsoluteIndexedYX0, WRAP_NONE, AND)
rOPM (39Slow, AbsoluteIndexedYSlow, WRAP_NONE, AND)
rOP8 (2FM1, AbsoluteLong, WRAP_NONE, AND)
rOP16(2FM0, AbsoluteLong, WRAP_NONE, AND)
rOPM (2FSlow, AbsoluteLongSlow, WRAP_NONE, AND)
rOP8 (3FM1, AbsoluteLongIndexedX, WRAP_NONE, AND)
rOP16(3FM0, AbsoluteLongIndexedX, WRAP_NONE, AND)
rOPM (3FSlow, AbsoluteLongIndexedXSlow, WRAP_NONE, AND)
rOP8 (23M1, StackRelative, WRAP_NONE, AND)
rOP16(23M0, StackRelative, WRAP_NONE, AND)
rOPM (23Slow, StackRelativeSlow, WRAP_NONE, AND)
rOP8 (33M1, StackRelativeIndirectIndexed, WRAP_NONE, AND)
rOP16(33M0, StackRelativeIndirectIndexed, WRAP_NONE, AND)
rOPM (33Slow, StackRelativeIndirectIndexedSlow, WRAP_NONE, AND)
/* ASL ********************************************************************* */
static void Op0AM1 (void)
{
AddCycles(ONE_CYCLE);
ICPU._Carry = (Registers.AL & 0x80) != 0;
Registers.AL <<= 1;
SetZN(Registers.AL);
}
static void Op0AM0 (void)
{
AddCycles(ONE_CYCLE);
ICPU._Carry = (Registers.AH & 0x80) != 0;
Registers.A.W <<= 1;
SetZN(Registers.A.W);
}
static void Op0ASlow (void)
{
AddCycles(ONE_CYCLE);
if (CheckMemory())
{
ICPU._Carry = (Registers.AL & 0x80) != 0;
Registers.AL <<= 1;
SetZN(Registers.AL);
}
else
{
ICPU._Carry = (Registers.AH & 0x80) != 0;
Registers.A.W <<= 1;
SetZN(Registers.A.W);
}
}
mOP8 (06M1, Direct, WRAP_BANK, ASL)
mOP16(06M0, Direct, WRAP_BANK, ASL)
mOPM (06Slow, DirectSlow, WRAP_BANK, ASL)
mOP8 (16E1, DirectIndexedXE1, WRAP_BANK, ASL)
mOP8 (16E0M1, DirectIndexedXE0, WRAP_BANK, ASL)
mOP16(16E0M0, DirectIndexedXE0, WRAP_BANK, ASL)
mOPM (16Slow, DirectIndexedXSlow, WRAP_BANK, ASL)
mOP8 (0EM1, Absolute, WRAP_NONE, ASL)
mOP16(0EM0, Absolute, WRAP_NONE, ASL)
mOPM (0ESlow, AbsoluteSlow, WRAP_NONE, ASL)
mOP8 (1EM1X1, AbsoluteIndexedXX1, WRAP_NONE, ASL)
mOP16(1EM0X1, AbsoluteIndexedXX1, WRAP_NONE, ASL)
mOP8 (1EM1X0, AbsoluteIndexedXX0, WRAP_NONE, ASL)
mOP16(1EM0X0, AbsoluteIndexedXX0, WRAP_NONE, ASL)
mOPM (1ESlow, AbsoluteIndexedXSlow, WRAP_NONE, ASL)
/* BIT ********************************************************************* */
static void Op89M1 (void)
{
ICPU._Zero = Registers.AL & Immediate8(READ);
}
static void Op89M0 (void)
{
ICPU._Zero = (Registers.A.W & Immediate16(READ)) != 0;
}
static void Op89Slow (void)
{
if (CheckMemory())
ICPU._Zero = Registers.AL & Immediate8Slow(READ);
else
ICPU._Zero = (Registers.A.W & Immediate16Slow(READ)) != 0;
}
rOP8 (24M1, Direct, WRAP_BANK, BIT)
rOP16(24M0, Direct, WRAP_BANK, BIT)
rOPM (24Slow, DirectSlow, WRAP_BANK, BIT)
rOP8 (34E1, DirectIndexedXE1, WRAP_BANK, BIT)
rOP8 (34E0M1, DirectIndexedXE0, WRAP_BANK, BIT)
rOP16(34E0M0, DirectIndexedXE0, WRAP_BANK, BIT)
rOPM (34Slow, DirectIndexedXSlow, WRAP_BANK, BIT)
rOP8 (2CM1, Absolute, WRAP_NONE, BIT)
rOP16(2CM0, Absolute, WRAP_NONE, BIT)
rOPM (2CSlow, AbsoluteSlow, WRAP_NONE, BIT)
rOP8 (3CM1X1, AbsoluteIndexedXX1, WRAP_NONE, BIT)
rOP16(3CM0X1, AbsoluteIndexedXX1, WRAP_NONE, BIT)
rOP8 (3CM1X0, AbsoluteIndexedXX0, WRAP_NONE, BIT)
rOP16(3CM0X0, AbsoluteIndexedXX0, WRAP_NONE, BIT)
rOPM (3CSlow, AbsoluteIndexedXSlow, WRAP_NONE, BIT)
/* CMP ********************************************************************* */
static void OpC9M1 (void)
{
int16 Int16 = (int16) Registers.AL - (int16) Immediate8(READ);
ICPU._Carry = Int16 >= 0;
SetZN((uint8) Int16);
}
static void OpC9M0 (void)
{
int32 Int32 = (int32) Registers.A.W - (int32) Immediate16(READ);
ICPU._Carry = Int32 >= 0;
SetZN((uint16) Int32);
}
static void OpC9Slow (void)
{
if (CheckMemory())
{
int16 Int16 = (int16) Registers.AL - (int16) Immediate8Slow(READ);
ICPU._Carry = Int16 >= 0;
SetZN((uint8) Int16);
}
else
{
int32 Int32 = (int32) Registers.A.W - (int32) Immediate16Slow(READ);
ICPU._Carry = Int32 >= 0;
SetZN((uint16) Int32);
}
}
rOP8 (C5M1, Direct, WRAP_BANK, CMP)
rOP16(C5M0, Direct, WRAP_BANK, CMP)
rOPM (C5Slow, DirectSlow, WRAP_BANK, CMP)
rOP8 (D5E1, DirectIndexedXE1, WRAP_BANK, CMP)
rOP8 (D5E0M1, DirectIndexedXE0, WRAP_BANK, CMP)
rOP16(D5E0M0, DirectIndexedXE0, WRAP_BANK, CMP)
rOPM (D5Slow, DirectIndexedXSlow, WRAP_BANK, CMP)
rOP8 (D2E1, DirectIndirectE1, WRAP_NONE, CMP)
rOP8 (D2E0M1, DirectIndirectE0, WRAP_NONE, CMP)
rOP16(D2E0M0, DirectIndirectE0, WRAP_NONE, CMP)
rOPM (D2Slow, DirectIndirectSlow, WRAP_NONE, CMP)
rOP8 (C1E1, DirectIndexedIndirectE1, WRAP_NONE, CMP)
rOP8 (C1E0M1, DirectIndexedIndirectE0, WRAP_NONE, CMP)
rOP16(C1E0M0, DirectIndexedIndirectE0, WRAP_NONE, CMP)
rOPM (C1Slow, DirectIndexedIndirectSlow, WRAP_NONE, CMP)
rOP8 (D1E1, DirectIndirectIndexedE1, WRAP_NONE, CMP)
rOP8 (D1E0M1X1, DirectIndirectIndexedE0X1, WRAP_NONE, CMP)
rOP16(D1E0M0X1, DirectIndirectIndexedE0X1, WRAP_NONE, CMP)
rOP8 (D1E0M1X0, DirectIndirectIndexedE0X0, WRAP_NONE, CMP)
rOP16(D1E0M0X0, DirectIndirectIndexedE0X0, WRAP_NONE, CMP)
rOPM (D1Slow, DirectIndirectIndexedSlow, WRAP_NONE, CMP)
rOP8 (C7M1, DirectIndirectLong, WRAP_NONE, CMP)
rOP16(C7M0, DirectIndirectLong, WRAP_NONE, CMP)
rOPM (C7Slow, DirectIndirectLongSlow, WRAP_NONE, CMP)
rOP8 (D7M1, DirectIndirectIndexedLong, WRAP_NONE, CMP)
rOP16(D7M0, DirectIndirectIndexedLong, WRAP_NONE, CMP)
rOPM (D7Slow, DirectIndirectIndexedLongSlow, WRAP_NONE, CMP)
rOP8 (CDM1, Absolute, WRAP_NONE, CMP)
rOP16(CDM0, Absolute, WRAP_NONE, CMP)
rOPM (CDSlow, AbsoluteSlow, WRAP_NONE, CMP)
rOP8 (DDM1X1, AbsoluteIndexedXX1, WRAP_NONE, CMP)
rOP16(DDM0X1, AbsoluteIndexedXX1, WRAP_NONE, CMP)
rOP8 (DDM1X0, AbsoluteIndexedXX0, WRAP_NONE, CMP)
rOP16(DDM0X0, AbsoluteIndexedXX0, WRAP_NONE, CMP)
rOPM (DDSlow, AbsoluteIndexedXSlow, WRAP_NONE, CMP)
rOP8 (D9M1X1, AbsoluteIndexedYX1, WRAP_NONE, CMP)
rOP16(D9M0X1, AbsoluteIndexedYX1, WRAP_NONE, CMP)
rOP8 (D9M1X0, AbsoluteIndexedYX0, WRAP_NONE, CMP)
rOP16(D9M0X0, AbsoluteIndexedYX0, WRAP_NONE, CMP)
rOPM (D9Slow, AbsoluteIndexedYSlow, WRAP_NONE, CMP)
rOP8 (CFM1, AbsoluteLong, WRAP_NONE, CMP)
rOP16(CFM0, AbsoluteLong, WRAP_NONE, CMP)
rOPM (CFSlow, AbsoluteLongSlow, WRAP_NONE, CMP)
rOP8 (DFM1, AbsoluteLongIndexedX, WRAP_NONE, CMP)
rOP16(DFM0, AbsoluteLongIndexedX, WRAP_NONE, CMP)
rOPM (DFSlow, AbsoluteLongIndexedXSlow, WRAP_NONE, CMP)
rOP8 (C3M1, StackRelative, WRAP_NONE, CMP)
rOP16(C3M0, StackRelative, WRAP_NONE, CMP)
rOPM (C3Slow, StackRelativeSlow, WRAP_NONE, CMP)
rOP8 (D3M1, StackRelativeIndirectIndexed, WRAP_NONE, CMP)
rOP16(D3M0, StackRelativeIndirectIndexed, WRAP_NONE, CMP)
rOPM (D3Slow, StackRelativeIndirectIndexedSlow, WRAP_NONE, CMP)
/* CPX ********************************************************************* */
static void OpE0X1 (void)
{
int16 Int16 = (int16) Registers.XL - (int16) Immediate8(READ);
ICPU._Carry = Int16 >= 0;
SetZN((uint8) Int16);
}
static void OpE0X0 (void)
{
int32 Int32 = (int32) Registers.X.W - (int32) Immediate16(READ);
ICPU._Carry = Int32 >= 0;
SetZN((uint16) Int32);
}
static void OpE0Slow (void)
{
if (CheckIndex())
{
int16 Int16 = (int16) Registers.XL - (int16) Immediate8Slow(READ);
ICPU._Carry = Int16 >= 0;
SetZN((uint8) Int16);
}
else
{
int32 Int32 = (int32) Registers.X.W - (int32) Immediate16Slow(READ);
ICPU._Carry = Int32 >= 0;
SetZN((uint16) Int32);
}
}
rOP8 (E4X1, Direct, WRAP_BANK, CPX)
rOP16(E4X0, Direct, WRAP_BANK, CPX)
rOPX (E4Slow, DirectSlow, WRAP_BANK, CPX)
rOP8 (ECX1, Absolute, WRAP_NONE, CPX)
rOP16(ECX0, Absolute, WRAP_NONE, CPX)
rOPX (ECSlow, AbsoluteSlow, WRAP_NONE, CPX)
/* CPY ********************************************************************* */
static void OpC0X1 (void)
{
int16 Int16 = (int16) Registers.YL - (int16) Immediate8(READ);
ICPU._Carry = Int16 >= 0;
SetZN((uint8) Int16);
}
static void OpC0X0 (void)
{
int32 Int32 = (int32) Registers.Y.W - (int32) Immediate16(READ);
ICPU._Carry = Int32 >= 0;
SetZN((uint16) Int32);
}
static void OpC0Slow (void)
{
if (CheckIndex())
{
int16 Int16 = (int16) Registers.YL - (int16) Immediate8Slow(READ);
ICPU._Carry = Int16 >= 0;
SetZN((uint8) Int16);
}
else
{
int32 Int32 = (int32) Registers.Y.W - (int32) Immediate16Slow(READ);
ICPU._Carry = Int32 >= 0;
SetZN((uint16) Int32);
}
}
rOP8 (C4X1, Direct, WRAP_BANK, CPY)
rOP16(C4X0, Direct, WRAP_BANK, CPY)
rOPX (C4Slow, DirectSlow, WRAP_BANK, CPY)
rOP8 (CCX1, Absolute, WRAP_NONE, CPY)
rOP16(CCX0, Absolute, WRAP_NONE, CPY)
rOPX (CCSlow, AbsoluteSlow, WRAP_NONE, CPY)
/* DEC ********************************************************************* */
static void Op3AM1 (void)
{
AddCycles(ONE_CYCLE);
#ifdef CPU_SHUTDOWN
CPU.WaitAddress = 0xffffffff;
#endif
Registers.AL--;
SetZN(Registers.AL);
}
static void Op3AM0 (void)
{
AddCycles(ONE_CYCLE);
#ifdef CPU_SHUTDOWN
CPU.WaitAddress = 0xffffffff;
#endif
Registers.A.W--;
SetZN(Registers.A.W);
}
static void Op3ASlow (void)
{
AddCycles(ONE_CYCLE);
#ifdef CPU_SHUTDOWN
CPU.WaitAddress = 0xffffffff;
#endif
if (CheckMemory())
{
Registers.AL--;
SetZN(Registers.AL);
}
else
{
Registers.A.W--;
SetZN(Registers.A.W);
}
}
mOP8 (C6M1, Direct, WRAP_BANK, DEC)
mOP16(C6M0, Direct, WRAP_BANK, DEC)
mOPM (C6Slow, DirectSlow, WRAP_BANK, DEC)
mOP8 (D6E1, DirectIndexedXE1, WRAP_BANK, DEC)
mOP8 (D6E0M1, DirectIndexedXE0, WRAP_BANK, DEC)
mOP16(D6E0M0, DirectIndexedXE0, WRAP_BANK, DEC)
mOPM (D6Slow, DirectIndexedXSlow, WRAP_BANK, DEC)
mOP8 (CEM1, Absolute, WRAP_NONE, DEC)
mOP16(CEM0, Absolute, WRAP_NONE, DEC)
mOPM (CESlow, AbsoluteSlow, WRAP_NONE, DEC)
mOP8 (DEM1X1, AbsoluteIndexedXX1, WRAP_NONE, DEC)
mOP16(DEM0X1, AbsoluteIndexedXX1, WRAP_NONE, DEC)
mOP8 (DEM1X0, AbsoluteIndexedXX0, WRAP_NONE, DEC)
mOP16(DEM0X0, AbsoluteIndexedXX0, WRAP_NONE, DEC)
mOPM (DESlow, AbsoluteIndexedXSlow, WRAP_NONE, DEC)
/* EOR ********************************************************************* */
static void Op49M1 (void)
{
Registers.AL ^= Immediate8(READ);
SetZN(Registers.AL);
}
static void Op49M0 (void)
{
Registers.A.W ^= Immediate16(READ);
SetZN(Registers.A.W);
}
static void Op49Slow (void)
{
if (CheckMemory())
{
Registers.AL ^= Immediate8Slow(READ);
SetZN(Registers.AL);
}
else
{
Registers.A.W ^= Immediate16Slow(READ);
SetZN(Registers.A.W);
}
}
rOP8 (45M1, Direct, WRAP_BANK, EOR)
rOP16(45M0, Direct, WRAP_BANK, EOR)
rOPM (45Slow, DirectSlow, WRAP_BANK, EOR)
rOP8 (55E1, DirectIndexedXE1, WRAP_BANK, EOR)
rOP8 (55E0M1, DirectIndexedXE0, WRAP_BANK, EOR)
rOP16(55E0M0, DirectIndexedXE0, WRAP_BANK, EOR)
rOPM (55Slow, DirectIndexedXSlow, WRAP_BANK, EOR)
rOP8 (52E1, DirectIndirectE1, WRAP_NONE, EOR)
rOP8 (52E0M1, DirectIndirectE0, WRAP_NONE, EOR)
rOP16(52E0M0, DirectIndirectE0, WRAP_NONE, EOR)
rOPM (52Slow, DirectIndirectSlow, WRAP_NONE, EOR)
rOP8 (41E1, DirectIndexedIndirectE1, WRAP_NONE, EOR)
rOP8 (41E0M1, DirectIndexedIndirectE0, WRAP_NONE, EOR)
rOP16(41E0M0, DirectIndexedIndirectE0, WRAP_NONE, EOR)
rOPM (41Slow, DirectIndexedIndirectSlow, WRAP_NONE, EOR)
rOP8 (51E1, DirectIndirectIndexedE1, WRAP_NONE, EOR)
rOP8 (51E0M1X1, DirectIndirectIndexedE0X1, WRAP_NONE, EOR)
rOP16(51E0M0X1, DirectIndirectIndexedE0X1, WRAP_NONE, EOR)
rOP8 (51E0M1X0, DirectIndirectIndexedE0X0, WRAP_NONE, EOR)
rOP16(51E0M0X0, DirectIndirectIndexedE0X0, WRAP_NONE, EOR)
rOPM (51Slow, DirectIndirectIndexedSlow, WRAP_NONE, EOR)
rOP8 (47M1, DirectIndirectLong, WRAP_NONE, EOR)
rOP16(47M0, DirectIndirectLong, WRAP_NONE, EOR)
rOPM (47Slow, DirectIndirectLongSlow, WRAP_NONE, EOR)
rOP8 (57M1, DirectIndirectIndexedLong, WRAP_NONE, EOR)
rOP16(57M0, DirectIndirectIndexedLong, WRAP_NONE, EOR)
rOPM (57Slow, DirectIndirectIndexedLongSlow, WRAP_NONE, EOR)
rOP8 (4DM1, Absolute, WRAP_NONE, EOR)
rOP16(4DM0, Absolute, WRAP_NONE, EOR)
rOPM (4DSlow, AbsoluteSlow, WRAP_NONE, EOR)
rOP8 (5DM1X1, AbsoluteIndexedXX1, WRAP_NONE, EOR)
rOP16(5DM0X1, AbsoluteIndexedXX1, WRAP_NONE, EOR)
rOP8 (5DM1X0, AbsoluteIndexedXX0, WRAP_NONE, EOR)
rOP16(5DM0X0, AbsoluteIndexedXX0, WRAP_NONE, EOR)
rOPM (5DSlow, AbsoluteIndexedXSlow, WRAP_NONE, EOR)
rOP8 (59M1X1, AbsoluteIndexedYX1, WRAP_NONE, EOR)
rOP16(59M0X1, AbsoluteIndexedYX1, WRAP_NONE, EOR)
rOP8 (59M1X0, AbsoluteIndexedYX0, WRAP_NONE, EOR)
rOP16(59M0X0, AbsoluteIndexedYX0, WRAP_NONE, EOR)
rOPM (59Slow, AbsoluteIndexedYSlow, WRAP_NONE, EOR)
rOP8 (4FM1, AbsoluteLong, WRAP_NONE, EOR)
rOP16(4FM0, AbsoluteLong, WRAP_NONE, EOR)
rOPM (4FSlow, AbsoluteLongSlow, WRAP_NONE, EOR)
rOP8 (5FM1, AbsoluteLongIndexedX, WRAP_NONE, EOR)
rOP16(5FM0, AbsoluteLongIndexedX, WRAP_NONE, EOR)
rOPM (5FSlow, AbsoluteLongIndexedXSlow, WRAP_NONE, EOR)
rOP8 (43M1, StackRelative, WRAP_NONE, EOR)
rOP16(43M0, StackRelative, WRAP_NONE, EOR)
rOPM (43Slow, StackRelativeSlow, WRAP_NONE, EOR)
rOP8 (53M1, StackRelativeIndirectIndexed, WRAP_NONE, EOR)
rOP16(53M0, StackRelativeIndirectIndexed, WRAP_NONE, EOR)
rOPM (53Slow, StackRelativeIndirectIndexedSlow, WRAP_NONE, EOR)
/* INC ********************************************************************* */
static void Op1AM1 (void)
{
AddCycles(ONE_CYCLE);
#ifdef CPU_SHUTDOWN
CPU.WaitAddress = 0xffffffff;
#endif
Registers.AL++;
SetZN(Registers.AL);
}
static void Op1AM0 (void)
{
AddCycles(ONE_CYCLE);
#ifdef CPU_SHUTDOWN
CPU.WaitAddress = 0xffffffff;
#endif
Registers.A.W++;
SetZN(Registers.A.W);
}
static void Op1ASlow (void)
{
AddCycles(ONE_CYCLE);
#ifdef CPU_SHUTDOWN
CPU.WaitAddress = 0xffffffff;
#endif
if (CheckMemory())
{
Registers.AL++;
SetZN(Registers.AL);
}
else
{
Registers.A.W++;
SetZN(Registers.A.W);
}
}
mOP8 (E6M1, Direct, WRAP_BANK, INC)
mOP16(E6M0, Direct, WRAP_BANK, INC)
mOPM (E6Slow, DirectSlow, WRAP_BANK, INC)
mOP8 (F6E1, DirectIndexedXE1, WRAP_BANK, INC)
mOP8 (F6E0M1, DirectIndexedXE0, WRAP_BANK, INC)
mOP16(F6E0M0, DirectIndexedXE0, WRAP_BANK, INC)
mOPM (F6Slow, DirectIndexedXSlow, WRAP_BANK, INC)
mOP8 (EEM1, Absolute, WRAP_NONE, INC)
mOP16(EEM0, Absolute, WRAP_NONE, INC)
mOPM (EESlow, AbsoluteSlow, WRAP_NONE, INC)
mOP8 (FEM1X1, AbsoluteIndexedXX1, WRAP_NONE, INC)
mOP16(FEM0X1, AbsoluteIndexedXX1, WRAP_NONE, INC)
mOP8 (FEM1X0, AbsoluteIndexedXX0, WRAP_NONE, INC)
mOP16(FEM0X0, AbsoluteIndexedXX0, WRAP_NONE, INC)
mOPM (FESlow, AbsoluteIndexedXSlow, WRAP_NONE, INC)
/* LDA ********************************************************************* */
static void OpA9M1 (void)
{
Registers.AL = Immediate8(READ);
SetZN(Registers.AL);
}
static void OpA9M0 (void)
{
Registers.A.W = Immediate16(READ);
SetZN(Registers.A.W);
}
static void OpA9Slow (void)
{
if (CheckMemory())
{
Registers.AL = Immediate8Slow(READ);
SetZN(Registers.AL);
}
else
{
Registers.A.W = Immediate16Slow(READ);
SetZN(Registers.A.W);
}
}
rOP8 (A5M1, Direct, WRAP_BANK, LDA)
rOP16(A5M0, Direct, WRAP_BANK, LDA)
rOPM (A5Slow, DirectSlow, WRAP_BANK, LDA)
rOP8 (B5E1, DirectIndexedXE1, WRAP_BANK, LDA)
rOP8 (B5E0M1, DirectIndexedXE0, WRAP_BANK, LDA)
rOP16(B5E0M0, DirectIndexedXE0, WRAP_BANK, LDA)
rOPM (B5Slow, DirectIndexedXSlow, WRAP_BANK, LDA)
rOP8 (B2E1, DirectIndirectE1, WRAP_NONE, LDA)
rOP8 (B2E0M1, DirectIndirectE0, WRAP_NONE, LDA)
rOP16(B2E0M0, DirectIndirectE0, WRAP_NONE, LDA)
rOPM (B2Slow, DirectIndirectSlow, WRAP_NONE, LDA)
rOP8 (A1E1, DirectIndexedIndirectE1, WRAP_NONE, LDA)
rOP8 (A1E0M1, DirectIndexedIndirectE0, WRAP_NONE, LDA)
rOP16(A1E0M0, DirectIndexedIndirectE0, WRAP_NONE, LDA)
rOPM (A1Slow, DirectIndexedIndirectSlow, WRAP_NONE, LDA)
rOP8 (B1E1, DirectIndirectIndexedE1, WRAP_NONE, LDA)
rOP8 (B1E0M1X1, DirectIndirectIndexedE0X1, WRAP_NONE, LDA)
rOP16(B1E0M0X1, DirectIndirectIndexedE0X1, WRAP_NONE, LDA)
rOP8 (B1E0M1X0, DirectIndirectIndexedE0X0, WRAP_NONE, LDA)
rOP16(B1E0M0X0, DirectIndirectIndexedE0X0, WRAP_NONE, LDA)
rOPM (B1Slow, DirectIndirectIndexedSlow, WRAP_NONE, LDA)
rOP8 (A7M1, DirectIndirectLong, WRAP_NONE, LDA)
rOP16(A7M0, DirectIndirectLong, WRAP_NONE, LDA)
rOPM (A7Slow, DirectIndirectLongSlow, WRAP_NONE, LDA)
rOP8 (B7M1, DirectIndirectIndexedLong, WRAP_NONE, LDA)
rOP16(B7M0, DirectIndirectIndexedLong, WRAP_NONE, LDA)
rOPM (B7Slow, DirectIndirectIndexedLongSlow, WRAP_NONE, LDA)
rOP8 (ADM1, Absolute, WRAP_NONE, LDA)
rOP16(ADM0, Absolute, WRAP_NONE, LDA)
rOPM (ADSlow, AbsoluteSlow, WRAP_NONE, LDA)
rOP8 (BDM1X1, AbsoluteIndexedXX1, WRAP_NONE, LDA)
rOP16(BDM0X1, AbsoluteIndexedXX1, WRAP_NONE, LDA)
rOP8 (BDM1X0, AbsoluteIndexedXX0, WRAP_NONE, LDA)
rOP16(BDM0X0, AbsoluteIndexedXX0, WRAP_NONE, LDA)
rOPM (BDSlow, AbsoluteIndexedXSlow, WRAP_NONE, LDA)
rOP8 (B9M1X1, AbsoluteIndexedYX1, WRAP_NONE, LDA)
rOP16(B9M0X1, AbsoluteIndexedYX1, WRAP_NONE, LDA)
rOP8 (B9M1X0, AbsoluteIndexedYX0, WRAP_NONE, LDA)
rOP16(B9M0X0, AbsoluteIndexedYX0, WRAP_NONE, LDA)
rOPM (B9Slow, AbsoluteIndexedYSlow, WRAP_NONE, LDA)
rOP8 (AFM1, AbsoluteLong, WRAP_NONE, LDA)
rOP16(AFM0, AbsoluteLong, WRAP_NONE, LDA)
rOPM (AFSlow, AbsoluteLongSlow, WRAP_NONE, LDA)
rOP8 (BFM1, AbsoluteLongIndexedX, WRAP_NONE, LDA)
rOP16(BFM0, AbsoluteLongIndexedX, WRAP_NONE, LDA)
rOPM (BFSlow, AbsoluteLongIndexedXSlow, WRAP_NONE, LDA)
rOP8 (A3M1, StackRelative, WRAP_NONE, LDA)
rOP16(A3M0, StackRelative, WRAP_NONE, LDA)
rOPM (A3Slow, StackRelativeSlow, WRAP_NONE, LDA)
rOP8 (B3M1, StackRelativeIndirectIndexed, WRAP_NONE, LDA)
rOP16(B3M0, StackRelativeIndirectIndexed, WRAP_NONE, LDA)
rOPM (B3Slow, StackRelativeIndirectIndexedSlow, WRAP_NONE, LDA)
/* LDX ********************************************************************* */
static void OpA2X1 (void)
{
Registers.XL = Immediate8(READ);
SetZN(Registers.XL);
}
static void OpA2X0 (void)
{
Registers.X.W = Immediate16(READ);
SetZN(Registers.X.W);
}
static void OpA2Slow (void)
{
if (CheckIndex())
{
Registers.XL = Immediate8Slow(READ);
SetZN(Registers.XL);
}
else
{
Registers.X.W = Immediate16Slow(READ);
SetZN(Registers.X.W);
}
}
rOP8 (A6X1, Direct, WRAP_BANK, LDX)
rOP16(A6X0, Direct, WRAP_BANK, LDX)
rOPX (A6Slow, DirectSlow, WRAP_BANK, LDX)
rOP8 (B6E1, DirectIndexedYE1, WRAP_BANK, LDX)
rOP8 (B6E0X1, DirectIndexedYE0, WRAP_BANK, LDX)
rOP16(B6E0X0, DirectIndexedYE0, WRAP_BANK, LDX)
rOPX (B6Slow, DirectIndexedYSlow, WRAP_BANK, LDX)