Mapping tool's result to circuit design

[GTP95]

Greetings,
I'm playing with your tool to familiarize with it and possibly using it for further research. After running the provided examples and looking at the READMEs, there are still a few important details about results interpretation that I didn't get.

1. At each step, the tool prints a list if exploitable faults. I guess that each number represents a specific fault that was able to modify the CPU's behavior. Where can I find the details of each fault, i.e. the fault's location, effect and time?
2. The tool also prints a list of numbers representing exploitable partitions. How can I map those numbers to areas on the circuit?
3. During the tool's execution, the list of exploitable faults keeps enlarging while the list of exploitable partitions shrinks. This makes sense when I think of these two results in isolation: as the tool progresses, it is able to find more exploitable faults and prove bigger partitions to be secure. But, at the end of 'out/regfile_k1/log, we have a long list of exploitable faults and no exploitable partitions. I would be tempted to interpret this as the tool having proved that there are no exploitable partitions, so the design is secure, but then why there are listed so many exploitable faults?

Thank you for your help,
GTP