From 690bdc4a5abf18b2fe49adbf216d0abd6c87a514 Mon Sep 17 00:00:00 2001 From: Jakub Cabal Date: Wed, 18 Dec 2024 12:55:27 +0100 Subject: [PATCH] chore(axis-tools): prepare the entity for the new component AXIS_SPLITTER --- comp/axis_tools/flow/splitter/Modules.tcl | 17 +++++ .../flow/splitter/axis_splitter.vhd | 69 +++++++++++++++++++ comp/axis_tools/flow/splitter/synth/Makefile | 15 ++++ 3 files changed, 101 insertions(+) create mode 100644 comp/axis_tools/flow/splitter/Modules.tcl create mode 100644 comp/axis_tools/flow/splitter/axis_splitter.vhd create mode 100644 comp/axis_tools/flow/splitter/synth/Makefile diff --git a/comp/axis_tools/flow/splitter/Modules.tcl b/comp/axis_tools/flow/splitter/Modules.tcl new file mode 100644 index 000000000..a729605ee --- /dev/null +++ b/comp/axis_tools/flow/splitter/Modules.tcl @@ -0,0 +1,17 @@ +# Modules.tcl: Components include script +# Copyright (C) 2024 CESNET +# Author(s): Jakub Cabal +# +# SPDX-License-Identifier: BSD-3-Clause + +# Component paths + +# Packages +lappend PACKAGES "$OFM_PATH/comp/base/pkg/math_pack.vhd" +lappend PACKAGES "$OFM_PATH/comp/base/pkg/type_pack.vhd" + +# Components +#lappend COMPONENTS [ list "ASFIFOX" "$OFM_PATH/comp/base/fifo/asfifox" "FULL" ] + +# Files +lappend MOD "$ENTITY_BASE/axis_merger.vhd" diff --git a/comp/axis_tools/flow/splitter/axis_splitter.vhd b/comp/axis_tools/flow/splitter/axis_splitter.vhd new file mode 100644 index 000000000..d8b3458a4 --- /dev/null +++ b/comp/axis_tools/flow/splitter/axis_splitter.vhd @@ -0,0 +1,69 @@ +-- axis_splitter.vhd: AXI-Stream splitter +-- Copyright (C) 2024 CESNET +-- Author(s): Ondřej Schwarz +-- +-- SPDX-License-Identifier: BSD-3-Clause +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.math_pack.all; +use work.type_pack.all; + +-- Component AXIS_SPLITTER is used to split one input AXI Stream interface into +-- N output AXI Stream interfaces. The target output stream for each transaction +-- is determined by the RX_AXIS_SEL signal, which is valid with the first word +-- of the transaction. +-- +entity AXIS_SPLITTER is +generic ( + -- width of AXI-Stream data signal in bits + TDATA_WIDTH : natural := 512; + -- width of AXI-Stream user signal in bits + TUSER_WIDTH : natural := 64; + -- number of TX AXI-Stream interfaces + TX_STREAMS : natural := 512; + -- target device: AGILEX, STRATIX10, ULTRASCALE,... + DEVICE : string := "AGILEX" +); +port ( + -- ========================================================================= + -- Clock and reset signals + -- ========================================================================= + CLK : in std_logic; + RESET : in std_logic; + + -- ========================================================================= + -- RX AXI-Stream interfaces (CLK) + -- ========================================================================= + -- The signal RX_AXIS_SEL determines which output stream the transaction + -- must be sent to. The signal is valid with the first word of the transaction. + RX_AXIS_SEL : in std_logic_vector(log2(TX_STREAMS)-1 downto 0); + RX_AXIS_TDATA : in std_logic_vector(TDATA_WIDTH-1 downto 0); + RX_AXIS_TUSER : in std_logic_vector(TUSER_WIDTH-1 downto 0); + RX_AXIS_TKEEP : in std_logic_vector(TDATA_WIDTH/8-1 downto 0); + RX_AXIS_TLAST : in std_logic; + RX_AXIS_TVALID : in std_logic; + RX_AXIS_TREADY : out std_logic; + + -- ========================================================================= + -- TX AXI-Stream interface (CLK) + -- ========================================================================= + TX_AXIS_TDATA : out slv_array_t(TX_STREAMS-1 downto 0)(TDATA_WIDTH-1 downto 0); + TX_AXIS_TUSER : out slv_array_t(TX_STREAMS-1 downto 0)(TUSER_WIDTH-1 downto 0); + TX_AXIS_TKEEP : out slv_array_t(TX_STREAMS-1 downto 0)(TDATA_WIDTH/8-1 downto 0); + TX_AXIS_TLAST : out std_logic_vector(TX_STREAMS-1 downto 0); + TX_AXIS_TVALID : out std_logic_vector(TX_STREAMS-1 downto 0); + TX_AXIS_TREADY : in std_logic_vector(TX_STREAMS-1 downto 0); +); +end entity; + +architecture FULL of AXIS_SPLITTER is + +begin + + -- TODO @OndřejSchwarz + +end architecture; diff --git a/comp/axis_tools/flow/splitter/synth/Makefile b/comp/axis_tools/flow/splitter/synth/Makefile new file mode 100644 index 000000000..8dd141def --- /dev/null +++ b/comp/axis_tools/flow/splitter/synth/Makefile @@ -0,0 +1,15 @@ +# Makefile: Makefile to compile module +# Copyright (C) 2024 CESNET +# Author(s): Jakub Cabal +# +# SPDX-License-Identifier: BSD-3-Clause + +TOP_LEVEL_ENT=AXIS_SPLITTER + +SYNTH=quartus +export DEVICE=AGILEX + +.PHONY: all +all: comp + +include ../../../../../build/Makefile