From 69fd59102951b9edcf450d0b4cee8e8310f2249b Mon Sep 17 00:00:00 2001 From: Hesham Almatary Date: Wed, 12 Jul 2023 12:00:31 +0100 Subject: [PATCH 1/2] seL4: Add new compilation targets --- pycheribuild/config/compilation_targets.py | 48 +++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/pycheribuild/config/compilation_targets.py b/pycheribuild/config/compilation_targets.py index 3e608649b..1b7299d57 100644 --- a/pycheribuild/config/compilation_targets.py +++ b/pycheribuild/config/compilation_targets.py @@ -778,12 +778,53 @@ def localbase(self) -> Path: def is_baremetal(cls): return True + @classmethod + def triple_for_target(cls, target: "CrossCompileTarget", config: "CheriConfig", *, include_version: bool): + return target.cpu_architecture.value + "-none-elf" + @classmethod def uses_softfloat_by_default(cls, xtarget: "CrossCompileTarget"): # Note: RISC-V Baremetal/FreeRTOS currently only supports softfloat return xtarget.is_riscv(include_purecap=True) +class Sel4TargetInfo(BaremetalClangTargetInfo): + shortname: str = "sel4" + + @classmethod + def is_sel4(cls) -> bool: + return True + + @property + def sysroot_dir(self): + return self.config.sysroot_output_root / self.config.default_cheri_sdk_directory_name / ( + self.target.get_rootfs_target().generic_arch_suffix) / self.target_triple + + @classmethod + def _get_compiler_project(cls) -> "type[BuildLLVMMonoRepoBase]": + from ..projects.cross.llvm import BuildCheriLLVM + return BuildCheriLLVM + + +class Sel4MorelloTargetInfo(BaremetalClangTargetInfo): + shortname: str = "sel4" + uses_morello_llvm: bool = True + + @classmethod + def is_sel4(cls) -> bool: + return True + + @property + def sysroot_dir(self): + return self.config.sysroot_output_root / self.config.default_morello_sdk_directory_name / ( + self.target.get_rootfs_target().generic_arch_suffix) / self.target_triple + + @classmethod + def _get_compiler_project(cls) -> "type[BuildLLVMMonoRepoBase]": + from ..projects.cross.llvm import BuildMorelloLLVM + return BuildMorelloLLVM + + class NewlibBaremetalTargetInfo(BaremetalClangTargetInfo): shortname = "Newlib" os_prefix = "baremetal-newlib-" @@ -1192,6 +1233,11 @@ class CompilationTargets(BasicCompilationTargets): RTEMS_RISCV64 = CrossCompileTarget("riscv64", CPUArchitecture.RISCV64, RTEMSTargetInfo) RTEMS_RISCV64_PURECAP = CrossCompileTarget("riscv64-purecap", CPUArchitecture.RISCV64, RTEMSTargetInfo, is_cheri_purecap=True, non_cheri_target=RTEMS_RISCV64) + # seL4 targets + SEL4_RISCV64 = CrossCompileTarget("riscv64", CPUArchitecture.RISCV64, Sel4TargetInfo) + SEL4_MORELLO_NO_CHERI = CrossCompileTarget("morello-aarch64", CPUArchitecture.AARCH64, + Sel4MorelloTargetInfo) + ALL_SUPPORTED_SEL4_TARGETS = (SEL4_RISCV64, SEL4_MORELLO_NO_CHERI) ALL_CHERIBSD_RISCV_TARGETS = (CHERIBSD_RISCV_PURECAP, CHERIBSD_RISCV_HYBRID, CHERIBSD_RISCV_NO_CHERI) ALL_CHERIBSD_NON_MORELLO_TARGETS = (*ALL_CHERIBSD_RISCV_TARGETS, CHERIBSD_AARCH64, CHERIBSD_X86_64) @@ -1222,7 +1268,7 @@ class CompilationTargets(BasicCompilationTargets): ALL_SUPPORTED_CHERIBSD_AND_HOST_TARGETS = ALL_SUPPORTED_CHERIBSD_TARGETS + BasicCompilationTargets.ALL_NATIVE ALL_FREEBSD_AND_CHERIBSD_TARGETS = ALL_SUPPORTED_CHERIBSD_TARGETS + ALL_SUPPORTED_FREEBSD_TARGETS - ALL_SUPPORTED_BAREMETAL_TARGETS = ALL_NEWLIB_TARGETS + ALL_PICOLIBC_TARGETS + ALL_SUPPORTED_BAREMETAL_TARGETS = ALL_NEWLIB_TARGETS + ALL_PICOLIBC_TARGETS + ALL_SUPPORTED_SEL4_TARGETS ALL_SUPPORTED_RTEMS_TARGETS = (RTEMS_RISCV64, RTEMS_RISCV64_PURECAP) ALL_SUPPORTED_CHERIBSD_AND_BAREMETAL_AND_HOST_TARGETS = \ ALL_SUPPORTED_CHERIBSD_AND_HOST_TARGETS + ALL_SUPPORTED_BAREMETAL_TARGETS From 05d76cd8ac5adf2d9debe262f607e84288068420 Mon Sep 17 00:00:00 2001 From: Hesham Almatary Date: Wed, 12 Jul 2023 14:26:30 +0100 Subject: [PATCH 2/2] seL4: prefix LLVM's tools with supported seL4 target triples Mainly to get binutils symlinked as expected by the seL4's cmake build system. --- pycheribuild/projects/cross/llvm.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/pycheribuild/projects/cross/llvm.py b/pycheribuild/projects/cross/llvm.py index 4c83c96e1..17b2e4e2c 100644 --- a/pycheribuild/projects/cross/llvm.py +++ b/pycheribuild/projects/cross/llvm.py @@ -41,6 +41,8 @@ CheriBSDTargetInfo, CompilationTargets, FreeBSDTargetInfo, + Sel4MorelloTargetInfo, + Sel4TargetInfo, ) from ...config.target_info import AbstractProject, CompilerType, CrossCompileTarget from ...processutils import CompilerInfo @@ -547,6 +549,8 @@ def triple_prefixes_for_binaries(self) -> "Iterable[str]": include_version=False), CheriBSDTargetInfo.triple_for_target(CompilationTargets.CHERIBSD_X86_64, self.config, include_version=False), + Sel4TargetInfo.triple_for_target(CompilationTargets.SEL4_RISCV64, self.config, + include_version=False), ] return [x + "-" for x in triples] @@ -576,6 +580,8 @@ def triple_prefixes_for_binaries(self) -> "Iterable[str]": triples = [ CheriBSDMorelloTargetInfo.triple_for_target(CompilationTargets.CHERIBSD_MORELLO_PURECAP, self.config, include_version=False), + Sel4MorelloTargetInfo.triple_for_target(CompilationTargets.SEL4_MORELLO_NO_CHERI, self.config, + include_version=False), ] return [x + "-" for x in triples]