From 3d79e87388ddaef6c9fb7f99335808e418a0eaf4 Mon Sep 17 00:00:00 2001 From: liuzhili Date: Tue, 19 Feb 2019 17:49:28 +0800 Subject: [PATCH] update spd log --- cgminer.c | 4 ++ driver-avalon9.c | 129 ++++++++++++++++++++++++++++++++++++++++++++--- driver-avalon9.h | 12 ++++- 3 files changed, 137 insertions(+), 8 deletions(-) diff --git a/cgminer.c b/cgminer.c index c388e86ce1..199d7d562e 100644 --- a/cgminer.c +++ b/cgminer.c @@ -289,6 +289,7 @@ static char *opt_set_avalon9_voltage_level; static char *opt_set_avalon9_voltage_level_offset; static char *opt_set_avalon9_freq; static char *opt_set_avalon9_adjust_volt_info; +static char *opt_set_avalon9_spd_update; #endif #ifdef USE_AVALON_MINER static char *opt_set_avalonm_voltage; @@ -1770,6 +1771,9 @@ static struct opt_table opt_config_table[] = { OPT_WITH_CBARG("--avalon9-adjust-volt-info", set_avalon9_adjust_volt_info, NULL, &opt_set_avalon9_adjust_volt_info, "Set Avalon9 adjust volt info, range 0-9999"), + OPT_WITH_CBARG("--avalon9-spd-update", + set_avalon9_spd_update, NULL, &opt_set_avalon9_spd_update, + "Set Avalon9 spd update, eg. type/period"), #endif #ifdef USE_AVALON_MINER OPT_WITH_CBARG("--avalonm-voltage", diff --git a/driver-avalon9.c b/driver-avalon9.c index 48ef68b9b0..2e4731f01b 100644 --- a/driver-avalon9.c +++ b/driver-avalon9.c @@ -46,6 +46,9 @@ uint32_t opt_avalon9_adjust_volt_down_threshold = AVA9_DEFAULT_AJUST_VOLT_DOWN_T uint32_t opt_avalon9_adjust_volt_time = AVA9_DEFAULT_AJUST_VOLT_TIME; uint32_t opt_avalon9_adjust_volt_enable = AVA9_DEFAULT_AJUST_VOLT_ENABLE; +uint32_t opt_avalon9_spd_update_type = AVA9_DEFAULT_SPD_UPDATE_TYPE; +uint32_t opt_avalon9_spd_update_period = AVA9_DEFAULT_SPD_UPDATE_PERIOD; + int opt_avalon9_freq_sel = AVA9_DEFAULT_FREQUENCY_SEL; int opt_avalon9_polling_delay = AVA9_DEFAULT_POLLING_DELAY; @@ -476,6 +479,38 @@ static inline int get_temp_max(struct avalon9_info *info, int addr) return max; } +static inline int get_temp_average(struct avalon9_info *info, int addr) +{ + int i, j; + int average = -273; + int sum = 0; + int count = 0; + int tmp; + + for (i = 0; i < info->miner_count[addr]; i++) { + for (j = AVA9_DEFAULT_ASIC_AVERAGE_TEMP_START; j <= AVA9_DEFAULT_ASIC_AVERAGE_TEMP_END; j++) { + if (info->temp[addr][i][j] > 0) { + sum += info->temp[addr][i][j]; + count++; + } + } + + if (count) { + tmp = sum / count; + if (average < tmp) + average = tmp; + } + + sum = 0; + count = 0; + } + + if (average < info->temp_mm[addr]) + average = info->temp_mm[addr]; + + return average; +} + /* * Incremental PID controller * @@ -499,12 +534,36 @@ static inline int get_temp_max(struct avalon9_info *info, int addr) */ static inline uint32_t adjust_fan(struct avalon9_info *info, int id) { - int t; + int t, tm, ta; double delta_u; double delta_p, delta_i, delta_d; uint32_t pwm; + static uint8_t count = 0; + static uint8_t flag = 0; + static uint16_t time_count = 0; - t = get_temp_max(info, id); + tm = get_temp_max(info, id); + ta = get_temp_average(info, id); + + /* Before 10Mins, used max temp */ + if (time_count > 300) { + if ((tm > AVA9_DEFAULT_PID_TEMP_MAX) || flag) { + t = tm; + + if (!flag) + flag = 1; + + if (count++ > 5) { + flag = 0; + count = 0; + } + } else { + t = ta; + } + } else { + t = tm; + time_count++; + } /* update target error */ info->pid_e[id][2] = info->pid_e[id][1]; @@ -754,11 +813,18 @@ static int decode_pkg(struct cgpu_info *avalon9, struct avalon9_ret *ar, int mod memcpy(&tmp, ar->data + 0, 4); if (tmp) - info->get_asic[modular_id][miner_id][asic_id][0] = be32toh(tmp); + info->get_asic_buffer[modular_id][miner_id][asic_id][0] = be32toh(tmp); memcpy(&tmp, ar->data + 4, 4); if (tmp) - info->get_asic[modular_id][miner_id][asic_id][1] = be32toh(tmp); + info->get_asic_buffer[modular_id][miner_id][asic_id][1] = be32toh(tmp); + + if (opt_avalon9_spd_update_type == 0) + memcpy(info->get_asic[modular_id][miner_id][asic_id], info->get_asic_buffer[modular_id][miner_id][asic_id], sizeof(info->get_asic_buffer[modular_id][miner_id][asic_id])); + else if ((miner_id == AVA9_DEFAULT_MINER_CNT - 1) && (asic_id == AVA9_DEFAULT_ASIC_MAX - 1)) { + memcpy(info->get_asic[modular_id], info->get_asic_buffer[modular_id], sizeof(info->get_asic_buffer[modular_id])); + } + for (i = 0; i < AVA9_DEFAULT_PLL_CNT; i++) { memcpy(&tmp, ar->data + 8 + i * 2, 2); @@ -1583,6 +1649,10 @@ static int polling(struct cgpu_info *avalon9) int do_adjust_fan = 0; uint32_t fan_pwm; double device_tdiff; + uint8_t error_polling_cnt_limit = 10; + + if (opt_avalon9_spd_update_type == 1) + error_polling_cnt_limit = 200; cgtime(¤t_fan); device_tdiff = tdiff(¤t_fan, &(info->last_fan_adj)); @@ -1627,7 +1697,7 @@ static int polling(struct cgpu_info *avalon9) memcpy(send_pkg.data, info->mm_dna[i], AVA9_MM_DNA_LEN); avalon9_init_pkg(&send_pkg, AVA9_P_RSTMMTX, 1, 1); avalon9_iic_xfer_pkg(avalon9, i, &send_pkg, NULL); - if (info->error_polling_cnt[i] >= 10) + if (info->error_polling_cnt[i] >= error_polling_cnt_limit) detach_module(avalon9, i); } @@ -1758,6 +1828,36 @@ static void avalon9_init_setting(struct cgpu_info *avalon9, int addr) avalon9_iic_xfer_pkg(avalon9, addr, &send_pkg, NULL); } +static void avalon9_set_spd_update_option(struct cgpu_info *avalon9, int addr, + uint32_t spd_update_type, uint32_t spd_update_period) +{ + struct avalon9_info *info = avalon9->device_data; + struct avalon9_pkg send_pkg; + int32_t tmp; + + memset(send_pkg.data, 0, AVA9_P_DATA_LEN); + + tmp = be32toh(spd_update_type); + memcpy(send_pkg.data + 0, &tmp, 4); + applog(LOG_ERR, "%s-%d-%d: avalon9 set spd update type %d", + avalon9->drv->name, avalon9->device_id, addr, spd_update_type); + + tmp = be32toh(spd_update_period); + memcpy(send_pkg.data + 4, &tmp, 4); + applog(LOG_ERR, "%s-%d-%d: avalon9 set spd update period %d", + avalon9->drv->name, avalon9->device_id, addr, spd_update_period); + + /* Package the data */ + avalon9_init_pkg(&send_pkg, AVA9_P_SET_SPD_UPDATE, 1, 1); + + if (addr == AVA9_MODULE_BROADCAST) + avalon9_send_bc_pkgs(avalon9, &send_pkg); + else + avalon9_iic_xfer_pkg(avalon9, addr, &send_pkg, NULL); + + return; +} + static void avalon9_set_adjust_voltage_option(struct cgpu_info *avalon9, int addr, int32_t up_init, uint32_t up_factor, uint32_t up_threshold, int32_t down_init, uint32_t down_factor, uint32_t down_threshold, @@ -2190,6 +2290,8 @@ static int64_t avalon9_scanhash(struct thr_info *thr) } avalon9_init_setting(avalon9, i); + avalon9_set_spd_update_option(avalon9, i, opt_avalon9_spd_update_type, opt_avalon9_spd_update_period); + info->freq_mode[i] = AVA9_FREQ_PLLADJ_MODE; break; case AVA9_FREQ_PLLADJ_MODE: @@ -2357,7 +2459,7 @@ static struct api_data *avalon9_api_stats(struct cgpu_info *avalon9) } } dh = b ? (b / (a + b)) * 100 : 0; - sprintf(buf, " DH[%.3f%%]", dh); + sprintf(buf, " DH[%.3f%% %.0f %.0f]", dh, a/1000, b/1000); strcat(statbuf, buf); } @@ -2367,6 +2469,9 @@ static struct api_data *avalon9_api_stats(struct cgpu_info *avalon9) sprintf(buf, " TMax[%d]", get_temp_max(info, i)); strcat(statbuf, buf); + sprintf(buf, " TAverage[%d]", get_temp_average(info, i)); + strcat(statbuf, buf); + sprintf(buf, " Fan[%d]", info->fan_cpm[i]); strcat(statbuf, buf); @@ -2614,6 +2719,18 @@ static struct api_data *avalon9_api_stats(struct cgpu_info *avalon9) return root; } +char *set_avalon9_spd_update(char *arg) +{ + int ret; + + ret = sscanf(arg, "%d-%d", &opt_avalon9_spd_update_type, + &opt_avalon9_spd_update_period); + if (ret < 1) + return "Invalid value for spd updates"; + + return NULL; +} + /* format: voltage[-addr[-miner]] * addr[0, AVA9_DEFAULT_MODULARS - 1], 0 means all modulars * miner[0, miner_count], 0 means all miners diff --git a/driver-avalon9.h b/driver-avalon9.h index 3417e428ad..08386723f3 100644 --- a/driver-avalon9.h +++ b/driver-avalon9.h @@ -19,7 +19,7 @@ #define AVA9_DEFAULT_FAN_MIN 5 /* % */ #define AVA9_DEFAULT_FAN_MAX 100 -#define AVA9_DEFAULT_TEMP_TARGET 93 +#define AVA9_DEFAULT_TEMP_TARGET 90 #define AVA9_DEFAULT_TEMP_OVERHEAT 105 #define AVA9_DEFAULT_VOLTAGE_LEVEL_MIN -15 @@ -46,6 +46,9 @@ #define AVA9_DEFAULT_AJUST_VOLT_TIME 600 #define AVA9_DEFAULT_AJUST_VOLT_ENABLE 1 +#define AVA9_DEFAULT_SPD_UPDATE_TYPE 0 +#define AVA9_DEFAULT_SPD_UPDATE_PERIOD 300 + #define AVA9_DEFAULT_OVERCLOCKING_OFF 0 #define AVA9_DEFAULT_OVERCLOCKING_ON 1 @@ -102,6 +105,9 @@ #define AVA9_DEFAULT_PID_TEMP_MIN_DIFF 5 #define AVA9_DEFAULT_PID_TEMP_MAX 105 +#define AVA9_DEFAULT_ASIC_AVERAGE_TEMP_START 8 +#define AVA9_DEFAULT_ASIC_AVERAGE_TEMP_END 17 + #define AVA9_DEFAULT_LV2_TH_MS 0 #define AVA9_DEFAULT_LV3_TH_MS 0 #define AVA9_DEFAULT_LV4_TH_MS 0 @@ -190,7 +196,7 @@ #define AVA9_P_STATUS_PVT_RO 0x4f #define AVA9_P_SET_ADJUST_VOLT 0x51 #define AVA9_P_STATUS_ASIC_PLL 0x52 - +#define AVA9_P_SET_SPD_UPDATE 0x53 #define AVA9_MODULE_BROADCAST 0 /* End of avalon9 protocol package type */ @@ -324,6 +330,7 @@ struct avalon9_info { uint32_t get_pll[AVA9_DEFAULT_MODULARS][AVA9_DEFAULT_MINER_CNT][AVA9_DEFAULT_PLL_CNT]; uint32_t get_asic[AVA9_DEFAULT_MODULARS][AVA9_DEFAULT_MINER_CNT][AVA9_DEFAULT_ASIC_MAX][2 + AVA9_DEFAULT_PLL_CNT]; + uint32_t get_asic_buffer[AVA9_DEFAULT_MODULARS][AVA9_DEFAULT_MINER_CNT][AVA9_DEFAULT_ASIC_MAX][2 + AVA9_DEFAULT_PLL_CNT]; int8_t factory_info[AVA9_DEFAULT_MODULARS][AVA9_DEFAULT_FACTORY_INFO_CNT]; int8_t overclocking_info[AVA9_DEFAULT_OVERCLOCKING_CNT]; @@ -378,6 +385,7 @@ extern char *set_avalon9_freq(char *arg); extern char *set_avalon9_voltage_level(char *arg); extern char *set_avalon9_voltage_level_offset(char *arg); extern char *set_avalon9_adjust_volt_info(char *arg); +extern char *set_avalon9_spd_update(char *arg); extern int opt_avalon9_temp_target; extern int opt_avalon9_polling_delay; extern int opt_avalon9_aucspeed;