-
Notifications
You must be signed in to change notification settings - Fork 0
/
RS232v2.vhd
347 lines (302 loc) · 11.7 KB
/
RS232v2.vhd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
-- -------------------------------------------------------------
-- Company: me
-- Engineer: Walter Puccio
-- -------------------------------------------------------------
-- Module: RS232 interface 8,N,1 115200 Baud with 1MHz clk
--
-- Read command "RAA" <- DD
-- Write command "WAADD"
-- AA=HEX address
-- DD=HEX data
-- Fast binary write command "wad" (lower case 'w')
-- a=8bit binary address
-- d=8bit binary data
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
--USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY rs232v2 IS
generic (clkrate :integer := 40000000;
BMODE :integer := 0; --(0) Normal divider, (1) NCO divider
Baud :integer := 115200); --Check manually the error <+-5%
PORT( clk :IN std_logic; --fast clock
sysclk :IN std_logic; --slow clock
reset :IN std_logic; --active high
RX :IN std_logic; --RX
TX :OUT std_logic; --TX
RW :OUT std_logic; --Read(0)/Write(1)
EN :OUT std_logic; --Enable, active high
D_in :IN std_logic_vector(7 DOWNTO 0); --Data in
D_out :OUT std_logic_vector(7 DOWNTO 0); --Data out
Adr :OUT std_logic_vector(7 DOWNTO 0) --Address
);
END rs232v2;
----------------------------------------------------------------
----------------------------------------------------------------
ARCHITECTURE Behavioral OF rs232v2 IS
--DEC 2 HEX
type RomType is array (0 to 15) of std_logic_vector(7 downto 0);
CONSTANT ROM : RomType := (x"30",x"31",x"32",x"33",x"34",x"35",x"36",x"37",
x"38",x"39",x"41",x"42",x"43",x"44",x"45",x"46");
SIGNAL dec : std_logic_vector(3 DOWNTO 0);
SIGNAL bstate : std_logic;
SIGNAL bcount : std_logic_vector(7 DOWNTO 0);
SIGNAL btick : std_logic; --Baud rate x8
SIGNAL adr_i : std_logic_vector(7 DOWNTO 0);
SIGNAL rstate : std_logic_vector(1 DOWNTO 0);
SIGNAL rshift_reg : std_logic_vector(7 DOWNTO 0); --shift register
SIGNAL rs_cnt : std_logic_vector(3 DOWNTO 0); --RX sample skew
SIGNAL rb_cnt : std_logic_vector(3 DOWNTO 0); --Bit count
SIGNAL rx_rdy : std_logic;
SIGNAL tstate : std_logic_vector(7 DOWNTO 0);
SIGNAL tshift_reg : std_logic_vector(8 DOWNTO 0); --include start bit
SIGNAL ts_cnt : std_logic_vector(3 DOWNTO 0);
SIGNAL tb_cnt : std_logic_vector(3 DOWNTO 0);
SIGNAL rw_int : std_logic;
SIGNAL en_int : std_logic;
SIGNAL pstate : std_logic_vector(1 DOWNTO 0);
SIGNAL pen_int : std_logic;
SIGNAL prw_int : std_logic;
----------------------------------------------------------------
----------------------------------------------------------------
BEGIN
process(clk, reset)
begin
case BMODE is
when 0 => --Baud generator x8, prefered Baud clock
if reset='1' then
bcount <= (others =>'0');
btick <= '0';
elsif rising_edge(clk) then
if bcount>((clkrate-(12*Baud))/(8*Baud)) then
bcount <= (others =>'0');
btick <= '1';
else
bcount <= bcount + 1;
btick <= '0';
end if;
end if;
when 1 => --Baud generator x8 can give better Baud clock but is not prefered
if reset='1' then
bcount <= (others =>'0');
bstate <= '0';
btick <= '0';
elsif rising_edge(clk) then
bcount <= bcount + ((Baud*8*128+(clkrate/2))/clkrate); --set Baudrate
case bstate is
when '0' => --wait 1
if bcount(6)='1' then
btick <= '1';
bstate <= '1';
else btick <= '0';
end if;
when '1' =>
btick <= '0';
if bcount(6)='0' then bstate <= '0';
end if;
when others => bstate <= '0'; -- no loose ends
end case;
end if;
when others => rstate <= (others =>'0'); -- no loose ends
end case;
end process;
--HEX 2 DEC
dec <= x"0" when rshift_reg=48 else
x"1" when rshift_reg=49 else
x"2" when rshift_reg=50 else
x"3" when rshift_reg=51 else
x"4" when rshift_reg=52 else
x"5" when rshift_reg=53 else
x"6" when rshift_reg=54 else
x"7" when rshift_reg=55 else
x"8" when rshift_reg=56 else
x"9" when rshift_reg=57 else
x"A" when rshift_reg=65 OR rshift_reg=97 else
x"B" when rshift_reg=66 OR rshift_reg=98 else
x"C" when rshift_reg=67 OR rshift_reg=99 else
x"D" when rshift_reg=68 OR rshift_reg=100 else
x"E" when rshift_reg=69 OR rshift_reg=101 else
x"F" when rshift_reg=70 OR rshift_reg=102 else x"0";
--RX STATEMACHINE
process(clk, reset, rstate)
begin
if reset='1' then
rstate <= (others =>'0');
rshift_reg <= (others =>'0');
rs_cnt <= (others =>'0');
rb_cnt <= (others =>'0');
rx_rdy <= '0';
elsif rising_edge(clk) then
if btick='1' then
case rstate is
when "00" => --Wait for start bit
rx_rdy <= '0';
rs_cnt <= x"B"; --skew bit sampling to middle
rb_cnt <= x"7"; --# of bits to RX(-1)
if RX='0' then rstate <= "01";
end if;
when "01" => -- get RX data
if rs_cnt=0 then
rs_cnt <= x"7";
rshift_reg <= RX & rshift_reg(7 downto 1);
rb_cnt <= rb_cnt - 1;
if rb_cnt=0 then
rx_rdy <= '1';
rstate <= "10";
end if;
else rs_cnt <= rs_cnt - 1;
end if;
when "10" => -- wait for stop bit
rx_rdy <= '0';
rs_cnt <= rs_cnt - 1;
if rs_cnt=0 then rstate <= "00";
end if;
when others => rstate <= (others =>'0'); -- no loose ends
end case;
end if;
end if;
end process;
TX <= tshift_reg(0);
Adr(7 downto 0) <= adr_i;
--Decode & TX STATEMACHINE
process(clk, reset, tstate)
begin
if reset='1' then
tstate <= (others =>'0');
tshift_reg <= (others =>'1');
ts_cnt <= (others =>'0');
tb_cnt <= (others =>'0');
rw_int <= '0';
en_int <= '0';
adr_i <= (others =>'0');
D_out <= (others =>'0');
elsif rising_edge(clk) then
if btick='1' then
case tstate is
when x"00" => --Wait for command
en_int <= '0';
if rx_rdy='1' then
if rshift_reg=82 then --R(ead hex)?
rw_int <= '0';
tstate <= x"10";
elsif rshift_reg=87 then --W(rite hex)?
rw_int <= '1';
tstate <= x"10";
elsif rshift_reg=119 then --w(rite bin)?
rw_int <= '1';
tstate <= x"25";
end if;
else rw_int <= '0';
end if;
when x"10" => --Wait for (Hex) address
if rx_rdy='1' then
adr_i(7 downto 4) <= dec;
tstate <= x"11";
end if;
when x"11" => --Wait for (Hex) address
if rx_rdy='1' then
adr_i(3 downto 0) <= dec;
if rw_int='0' then
en_int <= '1';
tstate <= x"30";
else tstate <= x"20";
end if;
end if;
--Write(slow hex)
when x"20" => --Wait for (Hex) data
if rx_rdy='1' then
D_out(7 downto 4) <= dec;
tstate <= x"23";
end if;
when x"23" => --Wait for (Hex) data
if rx_rdy='1' then
D_out(3 downto 0) <= dec;
en_int <= '1';
tstate <= x"00";
end if;
--Write(fast bin)
when x"25" => --Wait for (bin) address
if rx_rdy='1' then
adr_i <= rshift_reg;
tstate <= x"26";
end if;
when x"26" => --Wait for (bin) data
if rx_rdy='1' then
D_out <= rshift_reg;
en_int <= '1';
tstate <= x"00";
end if;
--Read reply
when x"30" => --TX Data
en_int <= '0';
ts_cnt <= x"7";
tb_cnt <= x"A";
tshift_reg <= ROM(conv_integer(D_in(7 downto 4))) & '0';
tstate <= x"31";
when x"31" =>
if ts_cnt=0 then
ts_cnt <= x"7";
tshift_reg <= '1' & tshift_reg(8 downto 1);
tb_cnt <= tb_cnt - 1;
if tb_cnt=0 then tstate <= x"36";
end if;
else ts_cnt <= ts_cnt - 1;
end if;
when x"36" => --TX Data
en_int <= '0';
ts_cnt <= x"7";
tb_cnt <= x"A";
tshift_reg <= ROM(conv_integer(D_in(3 downto 0))) & '0';
tstate <= x"37";
when x"37" =>
if ts_cnt=0 then
ts_cnt <= x"7";
tshift_reg <= '1' & tshift_reg(8 downto 1);
tb_cnt <= tb_cnt - 1;
if tb_cnt=0 then tstate <= x"00";
end if;
else ts_cnt <= ts_cnt - 1;
end if;
when others => tstate <= (others =>'X'); -- no loose ends
end case;
end if;
end if;
end process;
EN <= pen_int;
RW <= prw_int;
--Enable pulse
process(clk, sysclk, reset)
begin
if reset='1' then
pstate <= (others =>'0');
pen_int <= '0';
prw_int <= '0';
elsif rising_edge(clk) then
case pstate is
when "00" => --wait for en_int=1
pen_int <= '0';
prw_int <= '0';
if en_int='1' then
pstate <= "01";
end if;
when "01" =>
if sysclk='0' then
pen_int <= '1';
prw_int <= rw_int;
pstate <= "10";
end if;
when "10" =>
if sysclk='1' then
pstate <= "11";
end if;
when "11" => --wait for en_int=0
if sysclk='0' AND en_int='0' then
pen_int <= '0';
pstate <= "00";
end if;
when others => pstate <= (others =>'0'); -- no loose ends
end case;
end if;
end process;
END Behavioral;