From 9ea9d05908432fc5f3632f3e397e3709f95ef636 Mon Sep 17 00:00:00 2001 From: Pan Li Date: Mon, 2 Sep 2024 15:54:43 +0800 Subject: [PATCH] RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD This patch would like to allow the IMM operand of the unsigned scalar .SAT_ADD. Like the operand 0, the operand 1 of .SAT_ADD will be zero extended to Xmode before underlying code generation. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_usadd): Zero extend the second operand of usadd as the first operand does. * config/riscv/riscv.md (usadd3): Allow imm operand for scalar usadd pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_u_add-11.c: Make asm check robust. * gcc.target/riscv/sat_u_add-15.c: Ditto. * gcc.target/riscv/sat_u_add-19.c: Ditto. * gcc.target/riscv/sat_u_add-23.c: Ditto. * gcc.target/riscv/sat_u_add-3.c: Ditto. * gcc.target/riscv/sat_u_add-7.c: Ditto. Signed-off-by: Pan Li --- gcc/config/riscv/riscv.cc | 2 +- gcc/config/riscv/riscv.md | 4 ++-- gcc/testsuite/gcc.target/riscv/sat_u_add-11.c | 2 +- gcc/testsuite/gcc.target/riscv/sat_u_add-15.c | 2 +- gcc/testsuite/gcc.target/riscv/sat_u_add-19.c | 2 +- gcc/testsuite/gcc.target/riscv/sat_u_add-23.c | 2 +- gcc/testsuite/gcc.target/riscv/sat_u_add-3.c | 2 +- gcc/testsuite/gcc.target/riscv/sat_u_add-7.c | 2 +- 8 files changed, 9 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 98720611e246..f82e64a6fec8 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -11970,7 +11970,7 @@ riscv_expand_usadd (rtx dest, rtx x, rtx y) rtx xmode_sum = gen_reg_rtx (Xmode); rtx xmode_lt = gen_reg_rtx (Xmode); rtx xmode_x = riscv_gen_zero_extend_rtx (x, mode); - rtx xmode_y = gen_lowpart (Xmode, y); + rtx xmode_y = riscv_gen_zero_extend_rtx (y, mode); rtx xmode_dest = gen_reg_rtx (Xmode); /* Step-1: sum = x + y */ diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 6f7efafb8abe..9f94b5aa0232 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -4360,8 +4360,8 @@ (define_expand "usadd3" [(match_operand:ANYI 0 "register_operand") - (match_operand:ANYI 1 "register_operand") - (match_operand:ANYI 2 "register_operand")] + (match_operand:ANYI 1 "reg_or_int_operand") + (match_operand:ANYI 2 "reg_or_int_operand")] "" { riscv_expand_usadd (operands[0], operands[1], operands[2]); diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-11.c index e248aeafa8ef..bd830ececad4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_add-11.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-11.c @@ -8,7 +8,7 @@ ** sat_u_add_uint32_t_fmt_3: ** slli\s+[atx][0-9]+,\s*a0,\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a0,\s*a1 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 ** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-15.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-15.c index bb8b991a84ee..de615a6225e9 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_add-15.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-15.c @@ -8,7 +8,7 @@ ** sat_u_add_uint32_t_fmt_4: ** slli\s+[atx][0-9]+,\s*a0,\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a0,\s*a1 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 ** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-19.c index 7e4ae12f2f51..2b793e2f8fdb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_add-19.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-19.c @@ -8,7 +8,7 @@ ** sat_u_add_uint32_t_fmt_5: ** slli\s+[atx][0-9]+,\s*a0,\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a0,\s*a1 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 ** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-23.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-23.c index 49bbb74a401e..5de086e11384 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_add-23.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-23.c @@ -8,7 +8,7 @@ ** sat_u_add_uint32_t_fmt_6: ** slli\s+[atx][0-9]+,\s*a0,\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a0,\s*a1 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 ** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-3.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-3.c index cd15dc964503..bd7ccb2a8c7d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_add-3.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-3.c @@ -8,7 +8,7 @@ ** sat_u_add_uint32_t_fmt_1: ** slli\s+[atx][0-9]+,\s*a0,\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a0,\s*a1 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 ** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-7.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-7.c index a0b79b15ac4a..496d5cfbe81d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_add-7.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-7.c @@ -8,7 +8,7 @@ ** sat_u_add_uint32_t_fmt_2: ** slli\s+[atx][0-9]+,\s*a0,\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a0,\s*a1 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 ** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+