-
Notifications
You must be signed in to change notification settings - Fork 1
/
virtual_instruction.c
150 lines (125 loc) · 4.17 KB
/
virtual_instruction.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
#include <rvh_test.h>
#include <page_tables.h>
bool virtual_instruction() {
TEST_START();
goto_priv(PRIV_VS);
TEST_SETUP_EXCEPT();
hfence_vvma();
TEST_ASSERT("vs executing hfence.vvma leads to virtual isntruction exception",
excpt.triggered == true &&
excpt.cause == CAUSE_VRTI
);
goto_priv(PRIV_VS);
TEST_SETUP_EXCEPT();
hfence_gvma();
TEST_ASSERT("vs executing hfence.gvma leads to virtual isntruction exception",
excpt.triggered == true &&
excpt.cause == CAUSE_VRTI
);
////////////////////////////////////////////////////////////////////////
goto_priv(PRIV_VS);
TEST_SETUP_EXCEPT();
volatile uint64_t tmp = hlvd(0);
TEST_ASSERT("vs hlvd leads to virtual isntruction exception",
excpt.triggered == true &&
excpt.cause == CAUSE_VRTI
);
////////////////////////////////////////////////////////////////////////
goto_priv(PRIV_M);
CSRS(CSR_HSTATUS, HSTATUS_VTSR);
goto_priv(PRIV_VS);
TEST_SETUP_EXCEPT();
TEST_EXEC_SRET();
TEST_ASSERT("vs sret leads to virtual instruction exception when vtsr set",
excpt.triggered == true &&
excpt.cause == CAUSE_VRTI
);
goto_priv(PRIV_M);
CSRC(CSR_HSTATUS, HSTATUS_VTSR);
////////////////////////////////////////////////////////////////////////
goto_priv(PRIV_M);
CSRS(CSR_HSTATUS, HSTATUS_VTVM);
goto_priv(PRIV_VS);
TEST_SETUP_EXCEPT();
sfence();
TEST_ASSERT("vs sfence leads to virtual instruction exception when vtvm set",
excpt.triggered == true &&
excpt.cause == CAUSE_VRTI
);
TEST_SETUP_EXCEPT();
CSRW(satp, 0x0);
TEST_ASSERT("vs satp acess leads to virtual instruction exception when vtvm set",
excpt.triggered == true &&
excpt.cause == CAUSE_VRTI
);
goto_priv(PRIV_M);
CSRC(CSR_HSTATUS, HSTATUS_VTVM);
////////////////////////////////////////////////////////////////////////
goto_priv(PRIV_M);
CSRS(CSR_HSTATUS, HSTATUS_VTW);
goto_priv(PRIV_VS);
TEST_SETUP_EXCEPT();
asm("wfi");
TEST_ASSERT("vs wfi leads to virtual instruction exception when vtw set",
excpt.triggered == true &&
excpt.cause == CAUSE_VRTI
);
/**
* We can test this the other way around because it will stall the program
*/
////////////////////////////////////////////////////////////////////////
goto_priv(PRIV_M);
CSRW(mcounteren, 0);
CSRW(CSR_HCOUNTEREN, 0);
goto_priv(PRIV_VS);
TEST_SETUP_EXCEPT();
volatile uint64_t time = CSRR(time);
TEST_ASSERT("vs access to time casuses virtual instruction exception",
excpt.triggered == true &&
excpt.cause == CAUSE_ILI
);
goto_priv(PRIV_M);
CSRS(mcounteren, HCOUNTEREN_TM);
CSRS(CSR_HCOUNTEREN, HCOUNTEREN_TM);
goto_priv(PRIV_VS);
TEST_SETUP_EXCEPT();
time = CSRR(time);
TEST_ASSERT("vs access to time casuses succsseful with mcounteren.tm and hcounteren.tm set",
excpt.triggered == true &&
excpt.cause == CAUSE_ILI
);
//////////////////////////////////////////////////////////////////////
goto_priv(PRIV_M);
CSRW(mcounteren, 0);
CSRW(CSR_HCOUNTEREN, 0);
goto_priv(PRIV_VS);
TEST_SETUP_EXCEPT();
CSRW(sscratch, 1);
volatile uint64_t cycle = CSRR(cycle);
TEST_ASSERT("vs access to cycle casuses virtual instruction exception",
excpt.triggered == true &&
excpt.cause == CAUSE_ILI
);
goto_priv(PRIV_M);
CSRS(mcounteren, HCOUNTEREN_CY);
CSRW(CSR_HCOUNTEREN, 0);
goto_priv(PRIV_VS);
TEST_SETUP_EXCEPT();
CSRW(sscratch, 1);
cycle = CSRR(cycle);
TEST_ASSERT("vs access to cycle casuses virtual instruction exception when mcounteren.cy set",
excpt.triggered == true &&
excpt.cause == CAUSE_VRTI
);
goto_priv(PRIV_M);
CSRS(mcounteren, HCOUNTEREN_CY);
CSRS(CSR_HCOUNTEREN, HCOUNTEREN_CY);
goto_priv(PRIV_VS);
TEST_SETUP_EXCEPT();
CSRW(sscratch, 1);
cycle = CSRR(cycle);
TEST_ASSERT("vs access to cycle casuses succsseful when mcounteren.cy and hcounteren.cy set",
excpt.triggered == false
);
TEST_END();
}