diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json
index 58373d8829..dd152ce9d3 100644
--- a/FEXCore/Source/Interface/IR/IR.json
+++ b/FEXCore/Source/Interface/IR/IR.json
@@ -204,7 +204,7 @@
         "HasSideEffects": true,
         "HasDest": true,
         "ImplicitFlagClobber": true,
-        "DestSize": "8"
+        "DestSize": "OpSize::i64Bit"
       },
 
       "ThreadRemoveCodeEntry": {
@@ -218,12 +218,12 @@
                  "uint32_t Res = (node << 12) | cpu;",
                  "This means it has a limitation of 4096 CPU cores. Which is fine and matches x86 behaviour"
                 ],
-        "DestSize": 8
+        "DestSize": "OpSize::i64Bit"
       },
       "GPR = GetRoundingMode": {
         "Desc": ["Gets the current rounding mode options"
                 ],
-        "DestSize": "4"
+        "DestSize": "OpSize::i32Bit"
       },
 
       "SetRoundingMode GPR:$RoundMode, i1:$SetDAZ, GPR:$MXCSR": {
@@ -234,7 +234,7 @@
       "GPR = PushRoundingMode u8:$RoundMode": {
         "Desc": ["Override the current rounding mode options for the thread, returning old FPCR"
                 ],
-        "DestSize": "8",
+        "DestSize": "OpSize::i64Bit",
         "HasSideEffects": true
       },
       "PopRoundingMode GPR:$FPCR": {
@@ -253,7 +253,7 @@
                  "it cannot use a regular destination too. This ensures RA correctness.",
                  "This is a kludge to deal with the IR's lack of multiple destinations",
                  "If ForPair is set, RA will try to allocate the base of a register pair"],
-        "DestSize": "8"
+        "DestSize": "OpSize::i64Bit"
       },
       "FPR = AllocateFPR OpSize:#RegisterSize, OpSize:#ElementSize": {
         "Desc": ["Like AllocateGPR, but for FPR"],
@@ -265,7 +265,7 @@
                  "This is a kludge to deal with the IR's lack of multiple destinations",
                  "RA will attempt to allocate to the register after $After.",
                  "It may not succeed."],
-        "DestSize": "8"
+        "DestSize": "OpSize::i64Bit"
       },
       "GPR = RDRAND i1:$GetReseeded": {
         "Desc": ["Uses the hardware random number generator to generate a 64bit number",
@@ -276,7 +276,7 @@
                  "RNG hardware is allowed to fail early and return. Software must always check this"
                 ],
         "HasSideEffects": true,
-        "DestSize": "8"
+        "DestSize": "OpSize::i64Bit"
       },
       "Yield": {
         "HasSideEffects": true,
@@ -309,7 +309,7 @@
         "HasSideEffects": true,
         "Desc": ["Dispatches a guest syscall through to the SyscallHandler class"
                 ],
-        "DestSize": "8"
+        "DestSize": "OpSize::i64Bit"
       },
 
       "GPR = InlineSyscall GPR:$Arg0, GPR:$Arg1, GPR:$Arg2, GPR:$Arg3, GPR:$Arg4, GPR:$Arg5, i32:$HostSyscallNumber, SyscallFlags:$Flags": {
@@ -321,7 +321,7 @@
                  "such as gettid (matches on x86/x86-64/Arm64)."
                 ],
 
-        "DestSize": "8"
+        "DestSize": "OpSize::i64Bit"
       },
 
       "Thunk GPR:$ArgPtr, SHA256Sum:$ThunkNameHash": {
@@ -330,25 +330,25 @@
 
       "GPR:$EAX, GPR:$EBX, GPR:$ECX, GPR:$EDX = CPUID GPR:$Function, GPR:$Leaf": {
         "Desc": ["Calls in to the CPUID handler function to return emulated CPUID"],
-        "DestSize": "4",
+        "DestSize": "OpSize::i32Bit",
         "HasSideEffects": true
       },
       "GPR:$EAX, GPR:$EDX = XGetBV GPR:$Function": {
         "Desc": ["Calls in to the XCR handler function to return emulated XCR"],
-        "DestSize": "4",
+        "DestSize": "OpSize::i32Bit",
         "HasSideEffects": true
       }
     },
     "Moves": {
       "GPR = Copy GPR:$Source": {
         "Desc": ["GPR copy, generated by RA to split live ranges"],
-        "DestSize": "8"
+        "DestSize": "OpSize::i64Bit"
       },
 
       "GPR = Swap1 GPR:$A, GPR:$B": {
         "Desc": ["GPR swap part 1, generated by RA. Returns value of first source.",
                  "Destination must be second GPR."],
-        "DestSize": "8"
+        "DestSize": "OpSize::i64Bit"
       },
 
       "GPR = Swap2": {
@@ -356,7 +356,7 @@
                  "Must immediately succeed Swap1 with no intervening instructions",
                  "Kludge to workaround single destination restriction on IR",
                  "Hopefully temporary"],
-        "DestSize": "8"
+        "DestSize": "OpSize::i64Bit"
       }
     },
     "StaticRA": {
@@ -514,20 +514,20 @@
 
       "GPR = LoadNZCV": {
         "Desc": ["Loads value of NZCV register"],
-        "DestSize": "4"
+        "DestSize": "OpSize::i32Bit"
       },
 
       "StoreNZCV GPR:$Value": {
         "HasSideEffects": true,
         "Desc": ["Stores value to NZCV register"],
-        "DestSize": "4"
+        "DestSize": "OpSize::i32Bit"
       },
 
       "GPR = LoadDF": {
         "Desc": ["Loads the decimal flag from the context object in -1/1",
                   "representation for easy consumption"
                 ],
-        "DestSize": "8"
+        "DestSize": "OpSize::i64Bit"
       },
 
       "SSA = LoadMem RegisterClass:$Class, OpSize:#Size, GPR:$Addr, GPR:$Offset, OpSize:$Align, MemOffsetType:$OffsetType, u8:$OffsetScale": {
@@ -598,7 +598,7 @@
         "DestSize": "RegisterSize",
         "NumElements": "RegisterSize / ElementSize"
       },
-      "FPR = VLoadVectorGatherMasked OpSize:#RegisterSize, OpSize:#ElementSize, FPR:$Incoming, FPR:$Mask, GPR:$AddrBase, FPR:$VectorIndexLow, FPR:$VectorIndexHigh, u8:$VectorIndexElementSize, u8:$OffsetScale, u8:$DataElementOffsetStart, u8:$IndexElementOffsetStart": {
+      "FPR = VLoadVectorGatherMasked OpSize:#RegisterSize, OpSize:#ElementSize, FPR:$Incoming, FPR:$Mask, GPR:$AddrBase, FPR:$VectorIndexLow, FPR:$VectorIndexHigh, OpSize:$VectorIndexElementSize, u8:$OffsetScale, u8:$DataElementOffsetStart, u8:$IndexElementOffsetStart": {
         "Desc": [
           "Does a masked load similar to VPGATHERD* where the upper bit of each element",
           "determines whether or not that element will be loaded from memory.",
@@ -679,14 +679,14 @@
                  "Returns the final address that gets generated without the prefix appended."
                 ],
         "HasSideEffects": true,
-        "DestSize": "8"
+        "DestSize": "OpSize::i64Bit"
       },
       "GPR:$DstAddress, GPR:$SrcAddress = MemCpy i1:$IsAtomic, OpSize:$Size, GPR:$Dest, GPR:$Src, GPR:$Length, GPR:$Direction": {
         "Desc": ["Duplicates behaviour of x86 MOVS repeat",
                  "Returns the final addresses after they have been incremented or decremented"
                 ],
         "HasSideEffects": true,
-        "DestSize": "8"
+        "DestSize": "OpSize::i64Bit"
       },
       "CacheLineClear GPR:$Addr, i1:$Serialize": {
         "Desc": ["Does a 64 byte cacheline clear at the address specified",
@@ -726,7 +726,7 @@
           "CacheLevel > 0 && CacheLevel < 4"
         ],
         "HasSideEffects": true,
-        "DestSize": "8"
+        "DestSize": "OpSize::i64Bit"
       },
       "VStoreNonTemporal OpSize:#RegisterSize, FPR:$Value, GPR:$Addr, i8:$Offset": {
         "Desc": ["Does a non-temporal memory store of a vector.",
@@ -966,7 +966,7 @@
                  "Only useful for 32-bit applications."
                 ],
         "ImplicitFlagClobber": true,
-        "DestSize": "8"
+        "DestSize": "OpSize::i64Bit"
       }
     },
     "ALU": {
@@ -996,14 +996,14 @@
         "Desc": ["Generates a 64bit constant inside of a GPR",
                  "Unsupported to create a constant in FPR"
                 ],
-        "DestSize": "8"
+        "DestSize": "OpSize::i64Bit"
       },
 
       "InlineConstant i64:$Constant": {
         "Desc": ["Generates a 64bit constant to be used directly, non-FPR"],
         "HasSideEffects": true,
         "RAOverride": "0",
-        "DestSize": "8"
+        "DestSize": "OpSize::i64Bit"
       },
 
       "GPR = CycleCounter": {
@@ -1016,7 +1016,7 @@
                  "Part of the ART frequency equation can be pulled from CPUID fn0000_0015[EBX & EAX]",
                  "But it's missing the ART multiplier still?"
                 ],
-        "DestSize": "8"
+        "DestSize": "OpSize::i64Bit"
       },
 
       "GPR = Neg OpSize:#Size, GPR:$Src, CondClass:$Cond{{COND_AL}}": {
@@ -1167,7 +1167,7 @@
       },
       "GPR = Parity GPR:$Raw, i1:$Mask, i1:$Invert": {
         "Desc": ["Calculates PF"],
-        "DestSize": "4"
+        "DestSize": "OpSize::i32Bit"
       },
       "RmifNZCV GPR:$Src, u8:$Rotate, u8:$Mask": {
         "Desc": ["Rotate, mask, and insert into NZCV on FlagM platforms"],
@@ -1390,7 +1390,7 @@
         "Desc": ["Set NZCV flags for specified variable integer shift with given result.",
                  "Returns updated raw PF."],
         "HasSideEffects": true,
-        "DestSize": "8"
+        "DestSize": "OpSize::i64Bit"
       },
       "RotateFlags OpSize:$Size, GPR:$Result, GPR:$Shift, i1:$Left": {
         "Desc": ["Set NZCV flags for specified variable integer rotate with given result."],
@@ -2467,7 +2467,7 @@
                  "flags into the upper 16-bits of the 32-bit result, as these can also be derived over the",
                  "course of creating the intermediate result"
                 ],
-        "DestSize": "4",
+        "DestSize": "OpSize::i32Bit",
         "JITDispatch": false
       },
       "GPR = VPCMPISTRX FPR:$LHS, FPR:$RHS, u8:$Control": {
@@ -2479,7 +2479,7 @@
                  "flags into the upper 16-bits of the 32-bit result, as these can also be derived over the",
                  "course of creating the intermediate result"
                 ],
-        "DestSize": "4",
+        "DestSize": "OpSize::i32Bit",
         "JITDispatch": false
       },
       "FPR = VFCADD OpSize:#RegisterSize, OpSize:#ElementSize, FPR:$Vector1, FPR:$Vector2, u16:$Rotate": {
@@ -2617,7 +2617,7 @@
     "Crypto": {
       "FPR = VAESImc FPR:$Vector": {
         "Desc": "Does a stage of the inverse mix column transformation",
-        "DestSize": "16"
+        "DestSize": "OpSize::i128Bit"
       },
       "FPR = VAESEnc OpSize:#RegisterSize, FPR:$State, FPR:$Key, FPR:$ZeroReg": {
         "Desc": "Does a step of AES encryption",
@@ -2637,7 +2637,7 @@
       },
       "FPR = VAESKeyGenAssist FPR:$Src, FPR:$KeyGenTBLSwizzle, FPR:$ZeroReg, u8:$RCON": {
         "Desc": "Assists in key generation",
-        "DestSize": "16"
+        "DestSize": "OpSize::i128Bit"
       },
       "FPR = VSha1H FPR:$Src": {
         "Desc": "Does vector scalar SHA1H instruction",
@@ -2650,7 +2650,7 @@
       "GPR = CRC32 GPR:$Src1, GPR:$Src2, OpSize:$SrcSize": {
         "Desc": ["CRC32 using polynomial 0x1EDC6F41"
                 ],
-        "DestSize": "4"
+        "DestSize": "OpSize::i32Bit"
       },
       "FPR = PCLMUL OpSize:#RegisterSize, FPR:$Src1, FPR:$Src2, u8:$Selector": {
         "Desc": [
@@ -2665,39 +2665,39 @@
     },
     "F64": {
       "FPR = F64ATAN FPR:$Src1, FPR:$Src2": {
-        "DestSize": "8",
+        "DestSize": "OpSize::i64Bit",
         "JITDispatch": false
       },
       "FPR = F64FPREM FPR:$Src1, FPR:$Src2": {
-        "DestSize": "8",
+        "DestSize": "OpSize::i64Bit",
         "JITDispatch": false
       },
       "FPR = F64FPREM1 FPR:$Src1, FPR:$Src2": {
-        "DestSize": "8",
+        "DestSize": "OpSize::i64Bit",
         "JITDispatch": false
       },
       "FPR = F64SCALE FPR:$Src1, FPR:$Src2": {
-        "DestSize": "8",
+        "DestSize": "OpSize::i64Bit",
         "JITDispatch": false
       },
       "FPR = F64F2XM1 FPR:$Src": {
-        "DestSize": "8",
+        "DestSize": "OpSize::i64Bit",
         "JITDispatch": false
       },
       "FPR = F64FYL2X FPR:$Src, FPR:$Src2": {
-        "DestSize": "8",
+        "DestSize": "OpSize::i64Bit",
         "JITDispatch": false
       },
       "FPR = F64TAN FPR:$Src": {
-        "DestSize": "8",
+        "DestSize": "OpSize::i64Bit",
         "JITDispatch": false
       },
       "FPR = F64SIN FPR:$Src": {
-        "DestSize": "8",
+        "DestSize": "OpSize::i64Bit",
         "JITDispatch": false
       },
       "FPR = F64COS FPR:$Src": {
-        "DestSize": "8",
+        "DestSize": "OpSize::i64Bit",
         "JITDispatch": false
       }
     },
@@ -2709,7 +2709,7 @@
         ],
         "X87": true,
         "HasSideEffects": true,
-        "DestSize": 8
+        "DestSize": "OpSize::i64Bit"
       },
       "StackForceSlow": {
         "Desc": [
@@ -2800,14 +2800,14 @@
         "Desc": [
           "Reads a value off the stack at the offset"
         ],
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "X87": true
       },
       "GPR = StackValidTag u8:$StackLocation": {
         "Desc": [
           "Returns 1 if the value in location TOP+$StackLocation is valid, 0 otherwise."
         ],
-        "DestSize": 4,
+        "DestSize": "OpSize::i32Bit",
         "X87": true
       },
       "F80AddStack u8:$SrcStack1, u8:$SrcStack2": {
@@ -2825,7 +2825,7 @@
         "X87": true
       },
       "FPR = F80Add FPR:$X80Src1, FPR:$X80Src2": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "F80SubStack u8:$DstStack, u8:$SrcStack1, u8:$SrcStack2": {
@@ -2858,7 +2858,7 @@
           "The result is returned.",
           "`FPR = X80Src2 - X80Src1`"
         ],
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "F80MulStack u8:$SrcStack1, u8:$SrcStack2": {
@@ -2876,7 +2876,7 @@
         "X87": true
       },
       "FPR = F80Mul FPR:$X80Src1, FPR:$X80Src2": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "F80DivStack u8:$DstStack, u8:$SrcStack1, u8:$SrcStack2": {
@@ -2912,7 +2912,7 @@
           "The result is returned.",
           "`FPR = X80Src1 / X80Src2`"
         ],
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "F80StackXchange u8:$SrcStack": {
@@ -2928,7 +2928,7 @@
           "Returns the new value at the top of the stack."
         ],
         "HasSideEffects": true,
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "X87": true
       },
       "FPR = F80StackAbs": {
@@ -2937,7 +2937,7 @@
           "Returns the new value at the top of the stack."
         ],
         "HasSideEffects": true,
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "X87": true
       },
       "F80PTANStack": {
@@ -2951,12 +2951,12 @@
         "Desc": [
           "Computes arctan(st1/st0) and stores it in st0. Then pops the stack."
         ],
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "X87": true,
         "HasSideEffects": true
       },
       "FPR = F80ATAN FPR:$X80Src1, FPR:$X80Src2": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "F80FPREMStack": {
@@ -2964,7 +2964,7 @@
         "HasSideEffects": true
       },
       "FPR = F80FPREM FPR:$X80Src1, FPR:$X80Src2": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "F80FPREM1Stack": {
@@ -2972,7 +2972,7 @@
         "HasSideEffects": true
       },
       "FPR = F80FPREM1 FPR:$X80Src1, FPR:$X80Src2": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "F80SCALEStack": {
@@ -2980,7 +2980,7 @@
         "HasSideEffects": true
       },
       "FPR = F80SCALE FPR:$X80Src1, FPR:$X80Src2": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "FPR = F80CVT OpSize:#Size, FPR:$X80Src": {
@@ -2992,11 +2992,11 @@
         "JITDispatch": false
       },
       "FPR = F80CVTTo FPR:$X80Src, OpSize:$SrcSize": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "FPR = F80CVTToInt GPR:$Src, OpSize:$SrcSize": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "F80RoundStack": {
@@ -3007,7 +3007,7 @@
         "HasSideEffects": true
       },
       "FPR = F80Round FPR:$X80Src": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "F80F2XM1Stack": {
@@ -3015,11 +3015,11 @@
         "HasSideEffects": true
       },
       "FPR = F80F2XM1 FPR:$X80Src": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "FPR = F80TAN FPR:$X80Src": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "F80SINStack": {
@@ -3027,7 +3027,7 @@
         "HasSideEffects": true
       },
       "FPR = F80SIN FPR:$X80Src": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "F80COSStack": {
@@ -3035,7 +3035,7 @@
         "HasSideEffects": true
       },
       "FPR = F80COS FPR:$X80Src": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "F80SINCOSStack": {
@@ -3047,22 +3047,22 @@
         "HasSideEffects": true
       },
       "FPR = F80SQRT FPR:$X80Src": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "FPR = F80XTRACT_EXP FPR:$X80Src": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "FPR = F80XTRACT_SIG FPR:$X80Src": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "GPR = F80StackTest u8:$SrcStack": {
         "Desc": [
           "Does comparison between value in stack at TOP + SrcStack"
         ],
-        "DestSize": "4",
+        "DestSize": "OpSize::i32Bit",
         "X87": true
       },
       "GPR = F80CmpStack u8:$SrcStack": {
@@ -3070,7 +3070,7 @@
           "Does a scalar unordered compare between the value at the top of the stack and the value in stack position TOP+$SrcStack and stores the flags in to a GPR",
           "Ordering flag result is true if either float input is NaN"
         ],
-        "DestSize": "4",
+        "DestSize": "OpSize::i32Bit",
         "X87": true
       },
       "GPR = F80CmpValue FPR:$X80Src": {
@@ -3078,7 +3078,7 @@
           "Does a scalar unordered compare between the value at the top of the stack and $X80Src and stores the asked for flags in to a GPR",
           "Ordering flag result is true if either float input is NaN"
         ],
-        "DestSize": "4",
+        "DestSize": "OpSize::i32Bit",
         "HasSideEffects": true,
         "X87": true
       },
@@ -3086,15 +3086,15 @@
         "Desc": ["Does a scalar unordered compare and stores the flags in to a GPR",
                  "Ordering flag result is true if either float input is NaN"
                 ],
-        "DestSize": "4",
+        "DestSize": "OpSize::i32Bit",
         "JITDispatch": false
       },
       "FPR = F80BCDLoad FPR:$X80Src": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "FPR = F80BCDStore FPR:$X80Src": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "FPR = F80FYL2XStack": {
@@ -3104,11 +3104,11 @@
           "Returns the new value at the top of the stack, i.e. the result of the operation."
         ],
         "HasSideEffects": true,
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "X87": true
       },
       "FPR = F80FYL2X FPR:$X80Src1, FPR:$X80Src2": {
-        "DestSize": "16",
+        "DestSize": "OpSize::i128Bit",
         "JITDispatch": false
       },
       "F80VBSLStack OpSize:#RegisterSize, FPR:$VectorMask, u8:$SrcStack1, u8:$SrcStack2": {