此项目是2018年大二下学期开设的数字逻辑实验课的大作业项目，我该门课程成绩97，绩点4.0。
此项目为实践计算机组成原理课上学到的CPU单周期、多周期、流水线的工作方式，通过前期熟悉储存器、ALU等结构，到自己实现单周期CPU，最终完成流水线CPU的设计、调试与仿真，具体介绍在MIPS_CPU设计实验报告中有介绍。
流水线的源代码已上传至 https://github.com/GANGE666/MIPS-Cup-Verilog
Single Cycle CPU can execute add, sub, and, or, slt, addi, lw, sw, beq, j, sll, lui, slti, bne, ori, andi, srl，jal, jr, jalr, addu and subu.
A classic 5-stage pipeline MIPS 32-bit processor.
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256K RAM
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128K Cache
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5 stage: Fetch, Decode, Execute, Memory and Write back
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The processor support follow insrtuction
- TYPE-R: AND, OR, ADD, SUB, SLT, NOR, SRL
- TYPE-I: ADDI, ANDI, ORI, XORI, LUI, SLTI
- MEM: LW, SW
- BRANCH: BEQ, BNE
- JUMP: J, JAR, JR, JALR
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If you want a single cycle process, you can use the code of first commit.