From 942048ccdb9960dd05ec85e1ac0faa20d63a875c Mon Sep 17 00:00:00 2001
From: Antonietta Russo <A.Russo@gsi.de>
Date: Thu, 23 May 2024 14:50:18 +0200
Subject: [PATCH 1/8] BLM_ACO: added the syn folder with project files

---
 syn/blm_aco/Makefile    |   18 +
 syn/blm_aco/Manifest.py |   19 +
 syn/blm_aco/blm_aco.qpf |   30 ++
 syn/blm_aco/blm_aco.qsf | 1129 +++++++++++++++++++++++++++++++++++++++
 syn/blm_aco/blm_aco.tcl |    4 +
 5 files changed, 1200 insertions(+)
 create mode 100644 syn/blm_aco/Makefile
 create mode 100644 syn/blm_aco/Manifest.py
 create mode 100644 syn/blm_aco/blm_aco.qpf
 create mode 100644 syn/blm_aco/blm_aco.qsf
 create mode 100644 syn/blm_aco/blm_aco.tcl

diff --git a/syn/blm_aco/Makefile b/syn/blm_aco/Makefile
new file mode 100644
index 000000000..231f572bf
--- /dev/null
+++ b/syn/blm_aco/Makefile
@@ -0,0 +1,18 @@
+TARGET		= blm_aco
+DEVICE		= EP2AGX125
+FLASH		  = EPCS128
+RAM_SIZE	= 32768
+PHK       = ../../modules/scu_bus/housekeeping_sw
+PBLM     = ../../top/blm_aco
+W1        = ../../ip_cores/wrpc-sw
+CFLAGS    = -I$(PHK)/include -I$(PBLM)
+USRCPUCLK = 125000
+
+include ../build.mk
+
+$(TARGET).mif:  housekeeping.mif
+
+housekeeping.elf: $(PHK)/main.c $(W1)/dev/w1.c $(W1)/dev/w1-temp.c $(W1)/dev/w1-hw.c
+
+clean::
+	rm -f $(POW)/*.o $(PHK)/main.o $(W1)/dev/*.o
diff --git a/syn/blm_aco/Manifest.py b/syn/blm_aco/Manifest.py
new file mode 100644
index 000000000..cb3f74098
--- /dev/null
+++ b/syn/blm_aco/Manifest.py
@@ -0,0 +1,19 @@
+target = "altera"
+action = "synthesis"
+
+fetchto = "../../ip_cores"
+
+syn_device = "ep2agx125df"
+syn_grade = "c5"
+syn_package = "25"
+syn_top = "blm_aco"
+syn_project = "blm_aco"
+
+quartus_preflow = "blm_aco.tcl"
+
+modules = {
+  "local" : [ 
+    "../../top/blm_aco/", 
+  ]
+}
+syn_tool = "quartus"
diff --git a/syn/blm_aco/blm_aco.qpf b/syn/blm_aco/blm_aco.qpf
new file mode 100644
index 000000000..fe418c6ec
--- /dev/null
+++ b/syn/blm_aco/blm_aco.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition
+# Date created = 14:31:14  February 16, 2023
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "18.1"
+DATE = "14:31:14  February 16, 2023"
+
+# Revisions
+
+PROJECT_REVISION = "blm_aco"
diff --git a/syn/blm_aco/blm_aco.qsf b/syn/blm_aco/blm_aco.qsf
new file mode 100644
index 000000000..38a072584
--- /dev/null
+++ b/syn/blm_aco/blm_aco.qsf
@@ -0,0 +1,1129 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name DEVICE ep2agx125df25c5
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 572
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
+set_global_assignment -name FAMILY "Arria II GX"
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON
+set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.0 SP2"
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:blm_aco.tcl"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:30:14 FEBRUARY 14, 2013"
+set_global_assignment -name SEED 2
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCS128
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "ACTIVE SERIAL"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_location_assignment PIN_A11 -to A_TA[10]
+set_location_assignment PIN_A12 -to A_TA[6]
+set_location_assignment PIN_A13 -to A_TA[0]
+set_location_assignment PIN_A14 -to A_TA[3]
+set_location_assignment PIN_A15 -to A_TA[9]
+set_location_assignment PIN_A16 -to UIO[2]
+set_location_assignment PIN_A17 -to UIO[3]
+set_location_assignment PIN_A18 -to UIO[4]
+set_location_assignment PIN_A19 -to UIO[15]
+set_location_assignment PIN_A20 -to UIO[10]
+set_location_assignment PIN_A2 -to PIO[16]
+set_location_assignment PIN_A3 -to PIO[49]
+set_location_assignment PIN_A5 -to PIO[41]
+set_location_assignment PIN_AA10 -to A_A[4]
+set_location_assignment PIN_AA11 -to A_A[15]
+set_location_assignment PIN_AA12 -to A_A[6]
+set_location_assignment PIN_AA14 -to A_D[7]
+set_location_assignment PIN_AA15 -to A_SPARE0
+set_location_assignment PIN_AA16 -to A_NDTACK
+set_location_assignment PIN_AA18 -to A_NSEL_EXT_DATA_DRV
+set_location_assignment PIN_AA1 -to PIO[103]
+set_location_assignment PIN_AA3 -to PIO[107]
+set_location_assignment PIN_AA4 -to PIO[109]
+set_location_assignment PIN_AA5 -to PIO[142]
+set_location_assignment PIN_AA6 -to A_A[8]
+set_location_assignment PIN_AA7 -to A_A[10]
+set_location_assignment PIN_AA8 -to A_A[11]
+set_location_assignment PIN_AA9 -to A_A[3]
+set_location_assignment PIN_AB10 -to PIO[122]
+set_location_assignment PIN_AB11 -to PIO[136]
+set_location_assignment PIN_AB12 -to PIO[145]
+set_location_assignment PIN_AB13 -to PIO[149]
+set_location_assignment PIN_AB14 -to A_D[12]
+set_location_assignment PIN_AB15 -to A_D[2]
+set_location_assignment PIN_AB16 -to A_D[6]
+set_location_assignment PIN_AB17 -to A_ONEWIRE
+set_location_assignment PIN_AB18 -to A_NBOARDSEL
+set_location_assignment PIN_AB19 -to A_RNW
+set_location_assignment PIN_AB1 -to PIO[128]
+set_location_assignment PIN_AB20 -to A_NADR_EN
+set_location_assignment PIN_AB21 -to A_NSRQ
+set_location_assignment PIN_AB2 -to PIO[130]
+set_location_assignment PIN_AB3 -to PIO[133]
+set_location_assignment PIN_AB4 -to PIO[140]
+set_location_assignment PIN_AB5 -to PIO[139]
+set_location_assignment PIN_AB6 -to A_A[9]
+set_location_assignment PIN_AB7 -to A_A[0]
+set_location_assignment PIN_AB8 -to A_A[2]
+set_location_assignment PIN_AB9 -to A_A[13]
+set_location_assignment PIN_AC12 -to PIO[143]
+set_location_assignment PIN_AC13 -to PIO[147]
+set_location_assignment PIN_AC15 -to A_D[4]
+set_location_assignment PIN_AC18 -to A_NSEL_EXT_SIGNAL_DRV
+set_location_assignment PIN_AC19 -to A_D[11]
+set_location_assignment PIN_AC1 -to PIO[123]
+set_location_assignment PIN_AC3 -to PIO[108]
+set_location_assignment PIN_AC4 -to PIO[127]
+set_location_assignment PIN_AC6 -to PIO[146]
+set_location_assignment PIN_AC9 -to A_A[12]
+set_location_assignment PIN_AD10 -to PIO[126]
+set_location_assignment PIN_AD11 -to PIO[138]
+set_location_assignment PIN_AD12 -to A_A[7]
+set_location_assignment PIN_AD13 -to CLK_20MHZ_D
+set_location_assignment PIN_AD15 -to A_D[3]
+set_location_assignment PIN_AD16 -to A_D[5]
+set_location_assignment PIN_AD17 -to A_D[8]
+set_location_assignment PIN_AD18 -to A_D[9]
+set_location_assignment PIN_AD19 -to A_D[10]
+set_location_assignment PIN_AD20 -to A_NRESET
+set_location_assignment PIN_AD21 -to A_NADR_FROM_SCUB
+set_location_assignment PIN_AD2 -to PIO[131]
+set_location_assignment PIN_AD3 -to PIO[135]
+set_location_assignment PIN_AD4 -to PIO[137]
+set_location_assignment PIN_AD5 -to PIO[141]
+set_location_assignment PIN_AD6 -to PIO[144]
+set_location_assignment PIN_AD7 -to A_A[1]
+set_location_assignment PIN_AD8 -to PIO[150]
+set_location_assignment PIN_AD9 -to PIO[124]
+set_location_assignment PIN_B10 -to PIO[45]
+set_location_assignment PIN_B12 -to A_TA[12]
+set_location_assignment PIN_B13 -to A_TA[4]
+set_location_assignment PIN_B15 -to A_TA[7]
+set_location_assignment PIN_B16 -to UIO[5]
+set_location_assignment PIN_B18 -to UIO[11]
+set_location_assignment PIN_B19 -to A_SEL[1]
+set_location_assignment PIN_B1 -to PIO[28]
+set_location_assignment PIN_B3 -to PIO[26]
+set_location_assignment PIN_B4 -to PIO[21]
+set_location_assignment PIN_B6 -to PIO[27]
+set_location_assignment PIN_B7 -to PIO[29]
+set_location_assignment PIN_B9 -to PIO[47]
+set_location_assignment PIN_C12 -to A_TA[14]
+set_location_assignment PIN_C13 -to A_TA[13]
+set_location_assignment PIN_C15 -to A_TA[2]
+set_location_assignment PIN_C16 -to A_TA[11]
+set_location_assignment PIN_C18 -to A_TCLK
+set_location_assignment PIN_C19 -to UIO[6]
+set_location_assignment PIN_C1 -to PIO[40]
+set_location_assignment PIN_C20 -to A_SEL[3]
+set_location_assignment PIN_C2 -to PIO[43]
+set_location_assignment PIN_C3 -to PIO[38]
+set_location_assignment PIN_C7 -to PIO[33]
+set_location_assignment PIN_D10 -to PIO[31]
+set_location_assignment PIN_D11 -to CLK_20MHZ_A
+set_location_assignment PIN_D12 -to UIO[0]
+set_location_assignment PIN_D13 -to UIO[1]
+set_location_assignment PIN_D14 -to A_TA[1]
+set_location_assignment PIN_D15 -to A_TA[15]
+set_location_assignment PIN_D1 -to PIO[39]
+set_location_assignment PIN_D2 -to PIO[52]
+set_location_assignment PIN_D3 -to PIO[18]
+set_location_assignment PIN_D4 -to PIO[50]
+set_location_assignment PIN_D7 -to A_NLED_D3
+set_location_assignment PIN_D8 -to PIO[23]
+set_location_assignment PIN_D9 -to PIO[19]
+set_location_assignment PIN_E12 -to UIO[7]
+set_location_assignment PIN_E13 -to UIO[8]
+set_location_assignment PIN_E15 -to UIO[13]
+set_location_assignment PIN_E16 -to A_SEL[2]
+set_location_assignment PIN_E1 -to PIO[20]
+set_location_assignment PIN_E3 -to PIO[22]
+set_location_assignment PIN_E4 -to PIO[35]
+set_location_assignment PIN_E7 -to A_NLED_D2
+set_location_assignment PIN_F10 -to PIO[78]
+set_location_assignment PIN_F12 -to CLK_IO
+set_location_assignment PIN_F13 -to A_TA[5]
+set_location_assignment PIN_F14 -to UIO[12]
+set_location_assignment PIN_F15 -to UIO[14]
+set_location_assignment PIN_F1 -to PIO[30]
+set_location_assignment PIN_F3 -to PIO[48]
+set_location_assignment PIN_F4 -to PIO[25]
+set_location_assignment PIN_F7 -to PIO[24]
+set_location_assignment PIN_F8 -to PIO[66]
+set_location_assignment PIN_F9 -to PIO[68]
+set_location_assignment PIN_G10 -to PIO[80]
+set_location_assignment PIN_G13 -to A_TA[8]
+set_location_assignment PIN_G14 -to UIO[9]
+set_location_assignment PIN_G16 -to A_SEL[0]
+set_location_assignment PIN_G1 -to PIO[42]
+set_location_assignment PIN_G2 -to PIO[32]
+set_location_assignment PIN_G3 -to PIO[62]
+set_location_assignment PIN_G4 -to PIO[55]
+set_location_assignment PIN_G5 -to PIO[37]
+set_location_assignment PIN_G6 -to PIO[17]
+set_location_assignment PIN_G7 -to PIO[34]
+set_location_assignment PIN_H16 -to A_NUSER_EN
+set_location_assignment PIN_H1 -to PIO[44]
+set_location_assignment PIN_H3 -to PIO[51]
+set_location_assignment PIN_H4 -to PIO[58]
+set_location_assignment PIN_H6 -to PIO[54]
+set_location_assignment PIN_H7 -to PIO[36]
+set_location_assignment PIN_J1 -to PIO[56]
+set_location_assignment PIN_J3 -to PIO[64]
+set_location_assignment PIN_J4 -to PIO[60]
+set_location_assignment PIN_J5 -to PIO[46]
+set_location_assignment PIN_J6 -to PIO[53]
+set_location_assignment PIN_K1 -to PIO[63]
+set_location_assignment PIN_K2 -to PIO[59]
+set_location_assignment PIN_K3 -to PIO[71]
+set_location_assignment PIN_K4 -to PIO[67]
+set_location_assignment PIN_K5 -to PIO[57]
+set_location_assignment PIN_L1 -to PIO[75]
+set_location_assignment PIN_L3 -to PIO[74]
+set_location_assignment PIN_L4 -to PIO[70]
+set_location_assignment PIN_L7 -to PIO[61]
+set_location_assignment PIN_M1 -to PIO[83]
+set_location_assignment PIN_M3 -to PIO[72]
+set_location_assignment PIN_M4 -to PIO[79]
+set_location_assignment PIN_M7 -to PIO[65]
+set_location_assignment PIN_N1 -to PIO[73]
+set_location_assignment PIN_N2 -to PIO[77]
+set_location_assignment PIN_N4 -to CLK_20MHZ_B
+set_location_assignment PIN_N6 -to PIO[82]
+set_location_assignment PIN_N7 -to PIO[69]
+set_location_assignment PIN_P1 -to PIO[76]
+set_location_assignment PIN_P4 -to CLK_20MHZ_C
+set_location_assignment PIN_P7 -to PIO[84]
+set_location_assignment PIN_R1 -to PIO[91]
+set_location_assignment PIN_R3 -to PIO[86]
+set_location_assignment PIN_R4 -to PIO[81]
+set_location_assignment PIN_R5 -to PIO[94]
+set_location_assignment PIN_R6 -to PIO[85]
+set_location_assignment PIN_R7 -to PIO[117]
+set_location_assignment PIN_T1 -to PIO[89]
+set_location_assignment PIN_T2 -to PIO[87]
+set_location_assignment PIN_T3 -to PIO[95]
+set_location_assignment PIN_T4 -to PIO[88]
+set_location_assignment PIN_T5 -to PIO[93]
+set_location_assignment PIN_T6 -to PIO[97]
+set_location_assignment PIN_U16 -to A_EXT_DATA_RD
+set_location_assignment PIN_U1 -to PIO[96]
+set_location_assignment PIN_U3 -to PIO[98]
+set_location_assignment PIN_U4 -to PIO[100]
+set_location_assignment PIN_U6 -to PIO[115]
+set_location_assignment PIN_U9 -to PIO[119]
+set_location_assignment PIN_V11 -to PIO[125]
+set_location_assignment PIN_V12 -to PIO[132]
+set_location_assignment PIN_V13 -to A_D[0]
+set_location_assignment PIN_V14 -to A_D[14]
+set_location_assignment PIN_V15 -to A_NDS
+set_location_assignment PIN_V16 -to A_NEVENT_STR
+set_location_assignment PIN_V1 -to PIO[92]
+set_location_assignment PIN_V3 -to PIO[90]
+set_location_assignment PIN_V4 -to PIO[114]
+set_location_assignment PIN_V5 -to PIO[99]
+set_location_assignment PIN_V6 -to PIO[116]
+set_location_assignment PIN_V7 -to PIO[148]
+set_location_assignment PIN_V9 -to A_A[14]
+set_location_assignment PIN_W10 -to PIO[121]
+set_location_assignment PIN_W11 -to A_A[5]
+set_location_assignment PIN_W12 -to PIO[134]
+set_location_assignment PIN_W13 -to A_D[13]
+set_location_assignment PIN_W14 -to A_D[1]
+set_location_assignment PIN_W16 -to A_SPARE1
+set_location_assignment PIN_W1 -to PIO[106]
+set_location_assignment PIN_W2 -to PIO[105]
+set_location_assignment PIN_W3 -to PIO[102]
+set_location_assignment PIN_W4 -to PIO[104]
+set_location_assignment PIN_W7 -to PIO[113]
+set_location_assignment PIN_W9 -to PIO[118]
+set_location_assignment PIN_Y12 -to PIO[129]
+set_location_assignment PIN_Y13 -to A_SYSCLOCK
+set_location_assignment PIN_Y15 -to A_D[15]
+set_location_assignment PIN_Y16 -to A_NEXT_SIGNAL_IN
+set_location_assignment PIN_Y1 -to PIO[101]
+set_location_assignment PIN_Y3 -to PIO[112]
+set_location_assignment PIN_Y4 -to PIO[111]
+set_location_assignment PIN_Y7 -to PIO[110]
+set_location_assignment PIN_Y9 -to PIO[120]
+
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_fsm.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/mil_hw_or_soft_ip.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ssd1325/src/hdl/generic_serial_master.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/transceiver_prbs/trans_loop.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_mil_scu/event_processing.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/heap/xwb_heap.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/platform/altera/xwrc_platform_altera.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/ad7606/ad7606.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/wb_asmi_slave.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/butis_t0/TimestampEncoder.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/daq/daq.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/chopper/Independent_Clk.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/remote_update.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xvme64x_pack.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/power_test/row_array.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/watchdog/watchdog_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/wbmstr_core.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_watchdog_v1.0.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/diob_debounce.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/uart_baudgen.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/p_connector.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/flash_loader/flash_loader_v01.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_puls_n.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/lpc_uart/lpc_uart_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Access_Decode.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/dm_diag/dm_diag_auto.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mbox/mbox.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/prio_encoder/prio_encoder_64_6.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/ddr3/ddr3_wrapper.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ftm/time_clk_cross.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lpc_uart/postcode.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/butis_t0/BuTis_T0_generator.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Buffer_pack.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/psram/psram_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/fg_quad_statistics.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CR_pack.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/io_control/src/hdl/io_control.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_timeout.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/arria2/arria2_lvds_obuf.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/flash/flash_top.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/eca_tap/eca_tap_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/power_test/row.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/serdes_clk_gen/serdes_clk_gen_regs.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/chopper/K12_K23_Logik_Leds.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/Epcs_spi.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/Beam_Loss_check_v1.1.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/scu_bus/scu_bus_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_32to64.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/diob/quench_detection.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_reset.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/oled_display/Display_RAM_Ini_v01.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/arria2/arria2_lvds_tx.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/dac714/dac714.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/cfi_flash/cfi_flash_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/nau8811/src/hdl/wb_nau8811_audio_driver_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/matrix_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/rdram.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/slib_counter.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_arria_reset/arria_reset.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/uart_interrupt.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/Debounce.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/networks/altera_networks_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/slib_mv_filter.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/arria5_lvds_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Buffer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_wb_event.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/oled_display/char_render.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/asmi5/asmi5/synthesis/asmi5.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_arria_reset/arria10_reset/arria10_reset/synth/arria10_reset.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/monster/monster_iodir.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/butis_t0/TimestampDecoder.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/serdes_clk_gen/xwb_serdes_clk_gen.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/in_reg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ftm/ftm_lm32_cluster.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/blm_24_9_9_9pll.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/beam_dump/beam_dump_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/heap/heap_top.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/transceiver_prbs/trans_rcfg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_internals_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_mil_scu/wb_mil_scu.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/heap/heap_writer.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/trans_pll/trans_pll.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/build_id/build_id_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/scu_diob_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/ebm_auto_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_mil_scu/wb_mil_scu_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/watchdog/watchdog.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/fg_quad_ifa.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/beam_dump/beam_dump.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/hw6408_vhdl.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/oled_display/oled_auto_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/prioq2/prio.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/dm_diag/dm_diag.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_rmw.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_slave.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/fg901040.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/gc_shiftreg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/arria2/arria2_lvds_rx.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/wr_arria2_phy.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/trans_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_swapper.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/scu_slave_fg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/scu_slave_fg_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/scu_bus/scu_bus_slave.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/IO_4x8.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/axi/z7_axi_gpio_expander/axi_gpio_expander.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/heap/heap_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_master_eb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/power_test/pwm.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_counter_pool_el.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_reset_multi_aasd.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/altera_lvds.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_scubus_channel.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/ebm_auto.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/remote_update_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/scu_bus/scu_bus_slave_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/scu_bus/wb_irq_scu_bus.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_split/xwb_split.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_comp_ctrl.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/daq/Zeitbasis_daq.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_data.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/ssd1325/src/hdl/generic_fifo_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/blm_aco.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_out_el_m.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/oled_display/spi_master.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/uart_transmitter.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_64to32.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/pll/altera_butis.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/fg_quad_scu_bus.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ddr3/ddr3_wrapper_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/platform/altera/wr_altera_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/cpri_phy_reconf/cpri_phy_reconf.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/psram/psram.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/io_spi_dac_8420.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/modulbus_loader.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ssd1325/src/hdl/generic_fifo.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_arria_reset/wb_arria_reset.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/io_reg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/slib_edge_detect.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/I2C_Cntrl.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/eca_tap/eca_tap.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/power_test/power_test_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/oled_display/oled_auto.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/altera_lvds_ibuf.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/chopper/Debounce_Skal.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ad7606/adc_modul_bus.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/arria2/arria2_lvds_ibuf.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/diob_sync.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/slib_clock_div.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/IOBP_LED_ID_Module.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/chopper/Kicker_Leds.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/wrf_loopback.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/scu_bus/housekeeping.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/outpuls.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/prio_encoder/prio_encoder_256_8.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/ssd1325/src/hdl/generic_serial_master_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lpc_uart/i8042_kbc.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_bus.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/div_n.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/slib_input_sync.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register_link.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_queue.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/chopper/Kanal.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/butis_t0/crc8_data8.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_auto.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/eca_tap/eca_tap_auto_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/Zeitbasis.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/aux_functions_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/tag_n.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/up_down_counter.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/scu_bus/scu_to_wb.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/local_125_to_12p5.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/pll/altera_reset.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_timer/wb_timer.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/fg_quad_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/prioq2/min3.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_timer/wb_timer_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/config_status.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/prioq2/prio_auto.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/altera_lvds_obuf.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/pci-core/src/hdl/wb_pci_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Am_Match.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/build_id/build_id.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_bridge.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/simple_tag_decoder/simple_tag_decoder.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/Mil_bipol_dec.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/altera_async_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/asmi10/asmi10/synth/asmi10.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_altera.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CR_CSR_Space.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/lpc_uart/lpc_uart.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_comparator.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/addac_reg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/tag_ctrl.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/temp_sens/hdl/wb_temp_sense_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/diob/spill_abort.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ad7606/adc_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/f_divider.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/Mil_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/cpri_phy_reconf/cpri_phy_reconf_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Init.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/slave_clk_switch.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_dpram_mixed.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_tlu.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/daq/daq_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/prioq2/min9_64.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/oled_display/display_console.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/local_20_to_12p5.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_tlp.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/dac714/dac714_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_ena_in_mux.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/power_test/power_test.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/flash/altera_flash_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/altera_lvds_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/sys_clk_or_local_clk.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/wb_asmi.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/daq/crc5x16.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/modulbus_v5.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_msi.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_tdp.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/modul2spi.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_gate_timing_seq_elem.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/uart_receiver.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/fg_quad_datapath.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/global_reg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/altera_sync_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/asmi_arriaII/asmi_arriaII/synthesis/asmi_arriaII.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/wb_remote_update.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/butis_t0/wr_serialtimestamp_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_channel.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/pll/pll_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/monster/monster.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/altera_lvds_tx.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/arria10_lvds_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/xwb_ds182x_readout.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/lemo_io.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/chopper/Bus_io.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ad7606/adc_scu_bus.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ftm/ftm_lm32.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/slib_fifo.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/daq/daq_chan_reg_logic.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/Mil_Enc_Vhdl.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/scu_bus/wb_scu_bus.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_SharedComps.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/PLL_SIO.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/led_n.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_delay_line.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/prioq2/prio_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/prioq2/queue_unit.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/oled_display/wb_console.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/led.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/arria2_lvds_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_in_mux.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_puls_ctrl.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/Rd_mb_ld.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/prio_encoder/prio_encoder_16_4.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/ssd1325/src/hdl/wb_ssd1325_serial_driver.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/prioq2/arbiter.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/Mil_dec_edge_timed.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lpc_uart/lpc_peripheral.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/heap/heap_pathfinder.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_ds182x_readout/gc_ds182x_readout.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/front_board_id_v0.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/tmr_scu_bus.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/ring_buffer.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/flanke.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/slib_input_filter.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/mil_en_decoder.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_gate_timing_seq.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_arria_reset/wb_arria_reset_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/serdes_clk_gen/serdes_clk_gen.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_tag_channel.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/ssd1325/src/hdl/wb_ssd1325_serial_driver_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic_regs.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_piso_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_remapper/xwb_remapper.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/monster/monster_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/eca_tap/eca_tap_auto.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/altasmi.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xVME64xCore_Top.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/cfi_flash/xwb_cfi_wrapper.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/reverse_lpb/reverse_lpb.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_scu_reg/wb_scu_reg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/K_EPCS_IF.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CSR_pack.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/ftm/ftm_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/flash/altera_spi.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/eca_lvds_channel.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/a10ts/src/hdl/a10ts_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_cnt_n.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_free.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/aw_io_reg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_arria_reset/arria5_reset.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/uart_16750.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CRAM.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Funct_Match.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_arria_reset/arria10_reset/arria10_reset/altera_remote_update_181/synth/arria10_reset_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/SysClock.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_mil_scu/mil_pll.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/oled_display/oled_display_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/led_blink.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_IRQ_Controller.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/diob/hw_interlock.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_scan.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/io_control/src/hdl/io_control_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/i2c_wrapper/src/hdl/wb_i2c_wrapper_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/pll/altera_phase.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/serdes_clk_gen/wb_serdes_clk_gen.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/serdes_clk_gen/wb_serdes_clk_gen_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/altera_lvds_rx.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/prioq2/prio_auto_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/Loader_MB.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mbox/mbox_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/axi/axi4_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/dm_diag/dm_diag_auto_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/simple_tag_decoder/simple_tag_decoder_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_auto_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_scu_reg/wb_scu_reg_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/PU_Reset.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target32_devs_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_pci_decoder.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux.v" -library work
+set_global_assignment -name VERILOG_FILE ../../modules/lpc_uart/serirq_defines.v -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wb_slave.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target32_sm.v" -library work
+set_global_assignment -name VERILOG_FILE ../../modules/remote_update/asmi5/asmi5/synthesis/submodules/asmi5_asmi_parallel_0.v -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_pcir_fifo_control.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ad_load_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target_unit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_perr_crit.v" -library work
+set_global_assignment -name VERILOG_FILE ../../modules/cfi_flash/cfi_ctrl.v -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target32_clk_en.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_perr_en_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" -library work
+set_global_assignment -name VERILOG_FILE ../../top/blm_aco/deglitcher.v -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux_ad_load_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_in_reg.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_pciw_fifo_control.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target32_stop_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_synchronizer_flop.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_bridge32.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_frame_crit.v" -library work
+set_global_assignment -name VERILOG_FILE ../../modules/lpc_uart/serirq_slave.v -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ad_en_crit.v" -library work
+set_global_assignment -name VERILOG_FILE ../../modules/remote_update/asmi_arriaII/asmi_arriaII/synthesis/submodules/asmi_arriaII_asmi_parallel_0.v -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_master32_sm.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_conf_space.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_irdy_out_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_pci_tpram.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_sync_module.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_parity_check.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wb_decoder.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wbs_wbb3_2_wbb2.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wbr_fifo_control.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_constants.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/altera/jtag_tap.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wb_slave_unit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_master32_sm_if.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_rst_int.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_conf_cyc_addr_dec.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_par_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_cur_out_reg.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_fifo_control.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_serr_en_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_user_constants.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" -library work
+set_global_assignment -name VERILOG_FILE ../../modules/cfi_flash/cfi_ctrl_engine.v -library work
+set_global_assignment -name VERILOG_FILE ../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_altera_asmi_parallel_181_svbigkq.v -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_cbe_en_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target32_interface.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_delayed_sync.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_frame_load_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/timescale.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_ram_16x40d.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_delayed_write_reg.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wb_addr_mux.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/bus_commands.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target32_trdy_crit.v" -library work
+set_global_assignment -name VERILOG_FILE ../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_altera_asmi_parallel_181_gdoqleq.v -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_spoci_ctrl.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_pciw_pcir_fifos.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_async_reset_flop.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ch_state_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_frame_en_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_wbr_fifos.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_serr_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_out_reg.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wb_tpram.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wb_master.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux_ad_en_crit.v" -library work
+set_global_assignment -name SDC_FILE ../../top/blm_aco/scu_diob.sdc
+set_global_assignment -name QIP_FILE "../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/wr_arria2_phy.qip"
+set_global_assignment -name QIP_FILE ../../modules/pll/arria2/arria2_pll.qip
+set_global_assignment -name QIP_FILE ../../modules/ddr3/arria2/arria2_ddr3.qip
+set_global_assignment -name QIP_FILE "../../ip_cores/general-cores/platform/altera/networks/arria2gx_networks.qip"
+set_global_assignment -name QIP_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/arria2_pcie.qip"
+set_global_assignment -name AHDL_FILE ../../modules/modulbus/i2c.tdf
+set_global_assignment -name TOP_LEVEL_ENTITY blm_aco
+set_global_assignment -name QIP_FILE ../../modules/pll/arria2/sys_pll.qip
+set_global_assignment -name QIP_FILE ../../modules/pll/arria2/ref_pll.qip
+set_global_assignment -name QIP_FILE ../../modules/pll/arria2/dmtd_pll.qip
\ No newline at end of file
diff --git a/syn/blm_aco/blm_aco.tcl b/syn/blm_aco/blm_aco.tcl
new file mode 100644
index 000000000..ae2e50cf3
--- /dev/null
+++ b/syn/blm_aco/blm_aco.tcl
@@ -0,0 +1,4 @@
+set platform "BLM"        
+source ../autogen.tcl
+source ../../modules/build_id/build_id_short.tcl 
+source ../../modules/pll/arria2/arria2_pll.tcl

From a24fe9affbf2ba3ed69a8b651f5032587be14c5e Mon Sep 17 00:00:00 2001
From: Antonietta Russo <a.russo@gsi.de>
Date: Thu, 6 Jun 2024 15:47:42 +0200
Subject: [PATCH 2/8] BLM_ACO: identified and eliminated some bugs

---
 top/blm_aco/BLM_out_el_m.vhd         |  5 +++--
 top/blm_aco/Beam_Loss_check_v1.1.vhd | 19 +++++++++++++++----
 2 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/top/blm_aco/BLM_out_el_m.vhd b/top/blm_aco/BLM_out_el_m.vhd
index ef4433c1d..35ed33294 100644
--- a/top/blm_aco/BLM_out_el_m.vhd
+++ b/top/blm_aco/BLM_out_el_m.vhd
@@ -55,7 +55,8 @@ TYPE    t_cnt     is array (0 to 5)  of integer;
 
 signal read_cnt: t_cnt:= (others => 0);
 --signal flag_cnt: t_cnt;
-signal read_counters: integer range 0 to 255;
+--signal read_counters: integer range 0 to 255;
+signal read_counters: integer range 0 to 127;
 
 signal ena_out: std_logic_vector(5 downto 0);
 
@@ -149,7 +150,7 @@ end process;
     status_reg_counter_value_process: process (up_down_counter_val,  BLM_out_sel_reg(121))
         begin
 
-            read_counters <= to_integer(unsigned(BLM_out_sel_Reg(126)(7 downto 0)));
+            read_counters <= to_integer(unsigned(BLM_out_sel_Reg(126)(6 downto 0)));
             cnt_readback <= up_down_counter_val(read_counters);
       
 
diff --git a/top/blm_aco/Beam_Loss_check_v1.1.vhd b/top/blm_aco/Beam_Loss_check_v1.1.vhd
index b8663052b..baf36a25a 100644
--- a/top/blm_aco/Beam_Loss_check_v1.1.vhd
+++ b/top/blm_aco/Beam_Loss_check_v1.1.vhd
@@ -88,7 +88,8 @@ signal gate_state: std_logic_vector(47 downto 0);
 signal gate_sm_state :t_gate_state_nr;
 --signal all_thres_ready: std_logic; -- to allow gate prepare only after writing all thresholds
 --signal or_thres: std_logic_vector(127 downto 0);
-signal UP_OVERFLOW_OUT: std_logic_vector(127 downto 0);
+signal UP_OVERFLOW_OUT: std_logic_vector(127 downto 0):=(others => '0');
+signal DOWN_OVERFLOW_OUT: std_logic_vector(127 downto 0):=(others => '0');
 
   component BLM_watchdog is
   
@@ -366,14 +367,24 @@ port map (
   --end loop;
  -- all_thres_ready <= and_reduce(or_thres);
 --end process;
-
-TEST_PROCESS: process (BLM_ctrl_reg(15))
+TEST_PROCESS: process (clk_sys,rstn_sys)
 begin
+    if rstn_sys='1' then 
+  
+     UP_OVERFLOW_OUT <= (others => '0');
+     DOWN_OVERFLOW_OUT <= (others =>'0');
+      
+elsif (clk_sys'EVENT AND clk_sys= '1') then 
+  DOWN_OVERFLOW_OUT <= DOWN_OVERFLOW;
+
+--TEST_PROCESS: process (BLM_ctrl_reg(15))
+--begin
   if BLM_ctrl_reg(15) ='0' then 
     UP_OVERFLOW_OUT <= UP_OVERFLOW;
   else
     UP_OVERFLOW_OUT <= UP_OVERFLOW(127 downto 80)& gate_state & "0000"& BLM_gate_in(5 downto 0) & BLM_gate_in(11 downto 6)& "0000"& gate_output(5 downto 0) & gate_output(11 downto 6); -- UP_OVERFLOW & gate_in & gate_out
   end if;
+end if;
   end process;
 
 
@@ -387,7 +398,7 @@ BLM_out_section: BLM_out_el
     --
   -- UP_OVERFLOW  =>UP_OVERFLOW,
    UP_OVERFLOW     =>UP_OVERFLOW_OUT, --UP_OVERFLOW(127 downto 80)& gate_state & "0000"& BLM_gate_in(5 downto 0) & BLM_gate_in(11 downto 6)& "0000"& gate_output(5 downto 0) & gate_output(11 downto 6), -- UP_OVERFLOW & gate_in & gate_out , -- ONLY FOR TESTS 
-   DOWN_OVERFLOW   => DOWN_OVERFLOW,
+   DOWN_OVERFLOW   => DOWN_OVERFLOW_OUT,
     wd_out           => out_1wd, --out_wd, --out_1wd,
     gate_in         => BLM_gate_in(5 downto 0) & BLM_gate_in(11 downto 6),--BLM_gate_in,
     gate_out        => gate_error(5 downto 0) & gate_error(11 downto 6),

From 203f3233b91698babb167a95e230a61795c47e1d Mon Sep 17 00:00:00 2001
From: Antonietta Russo <a.russo@gsi.de>
Date: Wed, 12 Jun 2024 15:51:30 +0200
Subject: [PATCH 3/8] BLM: version for counters debugging

---
 top/blm_aco/BLM_gate_timing_seq.vhd      | 10 ++---
 top/blm_aco/BLM_gate_timing_seq_elem.vhd | 44 +++++++++---------
 top/blm_aco/Beam_Loss_check_v1.1.vhd     | 57 ++++++++++--------------
 3 files changed, 51 insertions(+), 60 deletions(-)

diff --git a/top/blm_aco/BLM_gate_timing_seq.vhd b/top/blm_aco/BLM_gate_timing_seq.vhd
index b7d736dc6..62ca2157f 100644
--- a/top/blm_aco/BLM_gate_timing_seq.vhd
+++ b/top/blm_aco/BLM_gate_timing_seq.vhd
@@ -22,7 +22,7 @@ port(
   hold_time : in  t_BLM_gate_hold_Time_Array;
 --  all_thres_ready: in std_logic;
   gate_error : out std_logic_vector(n-1 downto 0);  -- gate doesn't start within the given timeout
-  state_nr: out t_gate_state_nr;
+  --state_nr: out t_gate_state_nr;
   gate_out: out std_logic_vector(n-1 downto 0)        -- out gate signal
 
 );
@@ -32,7 +32,7 @@ architecture rtl of BLM_gate_timing_seq is
 
   signal    gate_er:         std_logic_vector(n-1 downto 0):= (others =>'0');
   signal    Gate_In_Mtx:        std_logic_vector (n-1 downto 0):= (others =>'0');
-  signal    gate_state: t_gate_state_nr;
+ -- signal    gate_state: t_gate_state_nr;
 
 component BLM_gate_timing_seq_elem is
 
@@ -47,7 +47,7 @@ component BLM_gate_timing_seq_elem is
     hold: in std_logic_vector(15 downto 0);
 --
     gate_error : out std_logic;  -- gate doesn't start within the given timeout
-    gate_state_nr : out std_logic_vector (2 downto 0); --for tests
+   -- gate_state_nr : out std_logic_vector (2 downto 0); --for tests
     gate_out: out std_logic      -- out gate signal
   );
   end component BLM_gate_timing_seq_elem;
@@ -73,7 +73,7 @@ begin
               hold => hold_time(i),
         --      all_thres_ready=> all_thres_ready,
               gate_error => gate_er(i), 
-              gate_state_nr => gate_state(i),
+            --  gate_state_nr => gate_state(i),
               gate_out => Gate_In_Mtx(i)    -- out gate signal
             );
            end generate BLM_gate_timing;
@@ -81,7 +81,7 @@ begin
         
         gate_error <= gate_er;
         gate_out <= Gate_In_Mtx;
-         state_nr <= gate_state;
+   --      state_nr <= gate_state;
          
  end rtl;          		 
 	
diff --git a/top/blm_aco/BLM_gate_timing_seq_elem.vhd b/top/blm_aco/BLM_gate_timing_seq_elem.vhd
index bd3941a49..d7ef05b71 100644
--- a/top/blm_aco/BLM_gate_timing_seq_elem.vhd
+++ b/top/blm_aco/BLM_gate_timing_seq_elem.vhd
@@ -14,7 +14,7 @@ port(
   hold: in std_logic_vector(15 downto 0);
 
   gate_error : out std_logic;  -- gate doesn't start within the given timeout
-  gate_state_nr : out std_logic_vector (2 downto 0); --for tests
+ -- gate_state_nr : out std_logic_vector (2 downto 0); --for tests
   gate_out: out std_logic        -- out gate signal
 );
 end BLM_gate_timing_seq_elem;
@@ -29,7 +29,7 @@ signal gate_er: std_logic;
 signal gate_out_sm: std_logic;
 
 signal curr_val   :std_logic; --:='0';
-signal state_sm: integer range 0 to 5:= 0;
+--signal state_sm: integer range 0 to 5:= 0;
 
 signal timeout_reset : unsigned(29 downto 0); 
 signal timeout : unsigned(29 downto 0);
@@ -37,22 +37,22 @@ signal hold_time: unsigned(15 downto 0);
 
 begin
 
-  state_sm_proc: process(clk_i, rstn_i)--(gate_state)
-  begin
-  if ((rstn_i= '0')) then 
-    state_sm <= 0;
-  elsif rising_edge(clk_i) then
-    case gate_state is
-      when idle           => state_sm <= 0;
-      when prepare_state  => state_sm <= 1;
-      when gate           => state_sm <= 2;
-      when waiting        => state_sm <= 3;
-      when error          => state_sm <= 4;
-      when recover_state  => state_sm <= 5;
-      when others         => null;
-    end case;
-  end if;
-  end process;
+  --state_sm_proc: process(clk_i, rstn_i)--(gate_state)
+ -- begin
+ -- if ((rstn_i= '0')) then 
+ --   state_sm <= 0;
+ -- elsif rising_edge(clk_i) then
+ --   case gate_state is
+  --    when idle           => state_sm <= 0;
+  --    when prepare_state  => state_sm <= 1;
+   --   when gate           => state_sm <= 2;
+  --    when waiting        => state_sm <= 3;
+  --   when error          => state_sm <= 4;
+  --    when recover_state  => state_sm <= 5;
+  --    when others         => null;
+ --   end case;
+ -- end if;
+ -- end process;
 
 
 
@@ -65,14 +65,14 @@ gate_proc: process (clk_i, rstn_i)
         gate_error  <= '0';
         gate_out <='0';
         gate_er <='0';
-        gate_state <= idle;
-        gate_state_nr <= "000";
+       gate_state <= idle;
+      --  gate_state_nr <= "000";
         curr_val <='0';
-      --  ready <= '0';
+     
       elsif rising_edge(clk_i) then
 
         curr_val <= gate_in ;
-        gate_state_nr <=  std_logic_vector(to_unsigned(state_sm, gate_state_nr'length));
+       -- gate_state_nr <=  std_logic_vector(to_unsigned(state_sm, gate_state_nr'length));
         gate_error <= gate_er;
         gate_out <= gate_out_sm;
 
diff --git a/top/blm_aco/Beam_Loss_check_v1.1.vhd b/top/blm_aco/Beam_Loss_check_v1.1.vhd
index baf36a25a..634d792e8 100644
--- a/top/blm_aco/Beam_Loss_check_v1.1.vhd
+++ b/top/blm_aco/Beam_Loss_check_v1.1.vhd
@@ -122,7 +122,7 @@ component BLM_gate_timing_seq is
       hold_time : in  t_BLM_gate_hold_Time_Array;
      -- all_thres_ready: in std_logic;
       gate_error : out std_logic_vector(n-1 downto 0); -- gate doesn't start within the given timeout
-      state_nr: out t_gate_state_nr;
+    --  state_nr: out t_gate_state_nr;
       gate_out: out std_logic_vector(n-1 downto 0)        -- out gate signal
     );
     end component BLM_gate_timing_seq;
@@ -280,15 +280,15 @@ end process direct_gate_operation;
       hold_time => gate_hold_time,
    --   all_thres_ready => all_thres_ready,
       gate_error => gate_sm_error, -- gate error
-      state_nr => gate_sm_state,
+      --state_nr => gate_sm_state,
       gate_out => gate_sm_output --gate_output
     );
 
   gate_error <= gate_sm_error;
   gate_output <= gate_sm_output;
 
-  gate_state <= '0'& gate_sm_state(5) & '0'& gate_sm_state(4)& '0'& gate_sm_state(3)&'0'& gate_sm_state(2) & '0'& gate_sm_state(1)&'0'& gate_sm_state(0)&
-  '0'& gate_sm_state(11) & '0'& gate_sm_state(10)& '0'& gate_sm_state(9)&'0'& gate_sm_state(8) & '0'& gate_sm_state(7)&'0'& gate_sm_state(6);
+  --gate_state <= '0'& gate_sm_state(5) & '0'& gate_sm_state(4)& '0'& gate_sm_state(3)&'0'& gate_sm_state(2) & '0'& gate_sm_state(1)&'0'& gate_sm_state(0)&
+ -- '0'& gate_sm_state(11) & '0'& gate_sm_state(10)& '0'& gate_sm_state(9)&'0'& gate_sm_state(8) & '0'& gate_sm_state(7)&'0'& gate_sm_state(6);
 
 
   gate_hold_time_proc: process(BLM_gate_hold_time_Reg)
@@ -357,35 +357,25 @@ port map (
       end generate BLM_counter_pool;
 -----------------------------------------------------------------------------------------------
 -----------------------------------------------------------------------------------------------
--- out section
---all_thres_ready_proc: process(pos_threshold, neg_threshold)
+
+
+--TEST_PROCESS: process (clk_sys,rstn_sys)
 --begin
- -- for i in 0 to 127 loop
-  --  for j in 0 to 31 loop
-  --    or_thres(i)<= pos_threshold(i)(j) or neg_threshold(i)(j);
-  --  end loop;
-  --end loop;
- -- all_thres_ready <= and_reduce(or_thres);
---end process;
-TEST_PROCESS: process (clk_sys,rstn_sys)
-begin
-    if rstn_sys='1' then 
+ --   if rstn_sys='1' then 
   
-     UP_OVERFLOW_OUT <= (others => '0');
-     DOWN_OVERFLOW_OUT <= (others =>'0');
+  --   UP_OVERFLOW_OUT <= (others => '0');
+  --   DOWN_OVERFLOW_OUT <= (others =>'0');
       
-elsif (clk_sys'EVENT AND clk_sys= '1') then 
-  DOWN_OVERFLOW_OUT <= DOWN_OVERFLOW;
+--elsif (clk_sys'EVENT AND clk_sys= '1') then 
+ -- DOWN_OVERFLOW_OUT <= DOWN_OVERFLOW;
 
---TEST_PROCESS: process (BLM_ctrl_reg(15))
---begin
-  if BLM_ctrl_reg(15) ='0' then 
-    UP_OVERFLOW_OUT <= UP_OVERFLOW;
-  else
-    UP_OVERFLOW_OUT <= UP_OVERFLOW(127 downto 80)& gate_state & "0000"& BLM_gate_in(5 downto 0) & BLM_gate_in(11 downto 6)& "0000"& gate_output(5 downto 0) & gate_output(11 downto 6); -- UP_OVERFLOW & gate_in & gate_out
-  end if;
-end if;
-  end process;
+ -- if BLM_ctrl_reg(15) ='0' then 
+ --   UP_OVERFLOW_OUT <= UP_OVERFLOW;
+ -- else
+ --   UP_OVERFLOW_OUT <= UP_OVERFLOW(127 downto 80)& gate_state & "0000"& BLM_gate_in(5 downto 0) & BLM_gate_in(11 downto 6)& "0000"& gate_output(5 downto 0) & gate_output(11 downto 6); -- UP_OVERFLOW & gate_in & gate_out
+  --end if;
+--end if;
+ -- end process;
 
 
 BLM_out_section: BLM_out_el 
@@ -396,9 +386,11 @@ BLM_out_section: BLM_out_el
     -- +++
     BLM_out_sel_reg => BLM_out_sel_reg, 
     --
-  -- UP_OVERFLOW  =>UP_OVERFLOW,
-   UP_OVERFLOW     =>UP_OVERFLOW_OUT, --UP_OVERFLOW(127 downto 80)& gate_state & "0000"& BLM_gate_in(5 downto 0) & BLM_gate_in(11 downto 6)& "0000"& gate_output(5 downto 0) & gate_output(11 downto 6), -- UP_OVERFLOW & gate_in & gate_out , -- ONLY FOR TESTS 
-   DOWN_OVERFLOW   => DOWN_OVERFLOW_OUT,
+  --UP_OVERFLOW  =>UP_OVERFLOW,
+    UP_OVERFLOW => neg_threshold(0) & pos_threshold(0)&UP_OVERFLOW(63 downto 0),
+   --UP_OVERFLOW     => UP_OVERFLOW(127 downto 80)& gate_state & "0000"& BLM_gate_in(5 downto 0) & BLM_gate_in(11 downto 6)& "0000"& gate_output(5 downto 0) & gate_output(11 downto 6), -- UP_OVERFLOW & gate_in & gate_out , -- ONLY FOR TESTS 
+   --DOWN_OVERFLOW   => DOWN_OVERFLOW_OUT,
+   DOWN_OVERFLOW   => DOWN_OVERFLOW,
     wd_out           => out_1wd, --out_wd, --out_1wd,
     gate_in         => BLM_gate_in(5 downto 0) & BLM_gate_in(11 downto 6),--BLM_gate_in,
     gate_out        => gate_error(5 downto 0) & gate_error(11 downto 6),
@@ -407,7 +399,6 @@ BLM_out_section: BLM_out_el
     BLM_status_Reg  => BLM_status_Reg 
     );
 
-   
 
   end architecture;
 

From dfbb9018dd8d58c0832a2853d85cab686084bef8 Mon Sep 17 00:00:00 2001
From: Antonietta Russo <a.russo@gsi.de>
Date: Thu, 13 Jun 2024 14:20:23 +0200
Subject: [PATCH 4/8] BLM: changes in the up_down_counter implementation

---
 top/blm_aco/BLM_counter_pool_el.vhd  |  8 ++--
 top/blm_aco/Beam_Loss_check_v1.1.vhd |  4 +-
 top/blm_aco/up_down_counter.vhd      | 61 +++++++++++++++-------------
 3 files changed, 39 insertions(+), 34 deletions(-)

diff --git a/top/blm_aco/BLM_counter_pool_el.vhd b/top/blm_aco/BLM_counter_pool_el.vhd
index f548b9a32..94774750a 100644
--- a/top/blm_aco/BLM_counter_pool_el.vhd
+++ b/top/blm_aco/BLM_counter_pool_el.vhd
@@ -93,11 +93,11 @@ begin
             else
                 
                 cnt_enable <= ENABLE;
-                if  gate_reset_ena = '0' then
+          --      if  gate_reset_ena = '0' then
                     CLEAR <='0';   
-                else 
-                    CLEAR <= ENABLE;
-                end if;
+          --      else 
+          --          CLEAR <= ENABLE;
+           --     end if;
                 
             end if;
         end if;
diff --git a/top/blm_aco/Beam_Loss_check_v1.1.vhd b/top/blm_aco/Beam_Loss_check_v1.1.vhd
index 634d792e8..4d569f93a 100644
--- a/top/blm_aco/Beam_Loss_check_v1.1.vhd
+++ b/top/blm_aco/Beam_Loss_check_v1.1.vhd
@@ -386,8 +386,8 @@ BLM_out_section: BLM_out_el
     -- +++
     BLM_out_sel_reg => BLM_out_sel_reg, 
     --
-  --UP_OVERFLOW  =>UP_OVERFLOW,
-    UP_OVERFLOW => neg_threshold(0) & pos_threshold(0)&UP_OVERFLOW(63 downto 0),
+  UP_OVERFLOW  =>UP_OVERFLOW,
+   -- UP_OVERFLOW => neg_threshold(0) & pos_threshold(0)&UP_OVERFLOW(63 downto 0),
    --UP_OVERFLOW     => UP_OVERFLOW(127 downto 80)& gate_state & "0000"& BLM_gate_in(5 downto 0) & BLM_gate_in(11 downto 6)& "0000"& gate_output(5 downto 0) & gate_output(11 downto 6), -- UP_OVERFLOW & gate_in & gate_out , -- ONLY FOR TESTS 
    --DOWN_OVERFLOW   => DOWN_OVERFLOW_OUT,
    DOWN_OVERFLOW   => DOWN_OVERFLOW,
diff --git a/top/blm_aco/up_down_counter.vhd b/top/blm_aco/up_down_counter.vhd
index 2f0183976..ab4667652 100644
--- a/top/blm_aco/up_down_counter.vhd
+++ b/top/blm_aco/up_down_counter.vhd
@@ -14,7 +14,6 @@ entity up_down_counter is
         CLK         : in std_logic;      -- Clock
         nRST         : in std_logic;      -- Reset
         CLEAR       : in std_logic;      -- Clear counter register
-    --    LOAD        : in std_logic;      -- Load counter register
         ENABLE      : in std_logic;      -- Enable count operation
         UP_IN       : in std_logic;    -- Load counter register up input
         DOWN_IN     : in std_logic;    -- Load counter register down input
@@ -29,56 +28,62 @@ entity up_down_counter is
 end up_down_counter;
 
 architecture rtl of up_down_counter is
-  --  signal Counter  : signed(WIDTH-1 downto 0);         -- up Counter register
+
  
-  signal int_count: integer:=0;
-    signal up_OVERFLOW_FLAG: std_logic:='0';
-    signal  down_OVERFLOW_FLAG:std_logic:='0';
+  signal int_count, int_n_count,int_p_count: integer:=0;
+    signal up_OVERFLOW_FLAG: std_logic;
+    signal  down_OVERFLOW_FLAG:std_logic;
 begin
     -- Counter process
     COUNT_SHIFT: process (nRST, CLK)
     begin
         if (nRST = '0') then    
 
-          --  Counter <= (others => '0');                -- Reset counter register 
+        
             up_OVERFLOW_FLAG <='0';
             down_OVERFLOW_FLAG <='0';
             int_count <=0;
-
+            int_n_count <=0;
+            int_p_count <=0;
             
         elsif (CLK'event and CLK='1') then
         
             if (CLEAR = '1') then
 
-             --   Counter <= (others => '0');            -- Clear counter register
                 int_count <= 0;
+                int_n_count <=0;
+                int_p_count <=0;
                 up_OVERFLOW_FLAG <='0';
                 down_OVERFLOW_FLAG <='0';
 
             elsif ( ENABLE = '1') then   
        
-                if UP_IN ='1' then  --positive slope
-                    if DOWN_IN ='0' then 
-                        int_count <= int_count +1;
-                    end if;
-                elsif DOWN_IN ='1' then --negative slope
-                    int_count <= int_count -1;
-                end if;
-
-                        
-                if int_count = pos_threshold then         -- pos_threshold reached
-
-                    up_OVERFLOW_FLAG <='1';
-       
-                elsif int_count = neg_threshold then  -- neg_threshold reached
-             
-                    down_OVERFLOW_FLAG <='1';                 
-                
-                end if;
-            
+----------------------------
+            if UP_IN ='1' then 
+                int_p_count <= int_p_count +1;
+            end if;
+    
+            if DOWN_IN ='1' then
+                int_n_count <= int_n_count -1;
+            end if;
+
+            int_count <= int_p_count + int_n_count;
+    
+        
+            if int_count = pos_threshold then         -- pos_threshold reached
+
+                up_OVERFLOW_FLAG <='1';
+
+            elsif int_count = neg_threshold then  -- neg_threshold reached
+
+                down_OVERFLOW_FLAG <='1';                 
+
             end if;
+
         end if;
- end process;
+    end if;
+end process;
+-----------------------------
 UP_OVERFLOW <= up_OVERFLOW_FLAG;
 DOWN_OVERFLOW <= down_OVERFLOW_FLAG;
 cnt_val <=  std_logic_vector(to_signed(int_count, WIDTH));

From 6f20ebbcfc0aeae20157cea289825c5c6dd23582 Mon Sep 17 00:00:00 2001
From: Antonietta Russo <a.russo@gsi.de>
Date: Thu, 20 Jun 2024 16:45:35 +0200
Subject: [PATCH 5/8] BLM: inverted the up_counters inputs and down_counters
 inputs selection

---
 top/blm_aco/BLM_in_mux.vhd | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/top/blm_aco/BLM_in_mux.vhd b/top/blm_aco/BLM_in_mux.vhd
index 2d3df1bb7..18eee54dc 100644
--- a/top/blm_aco/BLM_in_mux.vhd
+++ b/top/blm_aco/BLM_in_mux.vhd
@@ -34,8 +34,8 @@ signal up, down : std_logic;
               
        elsif (clk'EVENT AND clk= '1') then 
            
-            up_sig_sel <= to_integer(unsigned (mux_sel(5 downto 0)));
-            down_sig_sel <= to_integer(unsigned (mux_sel(11 downto 6)));
+            down_sig_sel <= to_integer(unsigned (mux_sel(5 downto 0)));
+            up_sig_sel <= to_integer(unsigned (mux_sel(11 downto 6)));
 
                for i in 0 to  63 loop
                 if up_sig_sel = i then cnt_up<= in_mux(i);

From 66e6b79442b21f9591f5d56c7366bec771589758 Mon Sep 17 00:00:00 2001
From: Antonietta Russo <a.russo@gsi.de>
Date: Fri, 19 Jul 2024 10:00:50 +0200
Subject: [PATCH 6/8] BLM_ACO updated version after tests

---
 top/blm_aco/BLM_cnt_pulse_former.vhd     |   46 +
 top/blm_aco/BLM_counter_pool_el.vhd      |    2 +-
 top/blm_aco/BLM_gate_el_v1.0.vhd         |  178 ++
 top/blm_aco/BLM_gate_timing_seq_v1.2.vhd |   89 +
 top/blm_aco/BLM_out_el_m_v1.0.vhd        |  207 ++
 top/blm_aco/Beam_Loss_check_v1.2.vhd     |  360 +++
 top/blm_aco/IOBP_LED_ID_module_v1.0.vhd  |  149 ++
 top/blm_aco/Manifest.py                  |   19 +-
 top/blm_aco/blm_aco_v1.0.vhd             | 2552 ++++++++++++++++++++++
 top/blm_aco/front_board_id_v0.vhd        |   10 +-
 top/blm_aco/p_connector.vhd              |    5 +-
 top/blm_aco/scu_diob_pkg.vhd             |    3 +-
 top/blm_aco/up_down_counter.vhd          |   75 +-
 13 files changed, 3659 insertions(+), 36 deletions(-)
 create mode 100644 top/blm_aco/BLM_cnt_pulse_former.vhd
 create mode 100644 top/blm_aco/BLM_gate_el_v1.0.vhd
 create mode 100644 top/blm_aco/BLM_gate_timing_seq_v1.2.vhd
 create mode 100644 top/blm_aco/BLM_out_el_m_v1.0.vhd
 create mode 100644 top/blm_aco/Beam_Loss_check_v1.2.vhd
 create mode 100644 top/blm_aco/IOBP_LED_ID_module_v1.0.vhd
 create mode 100644 top/blm_aco/blm_aco_v1.0.vhd

diff --git a/top/blm_aco/BLM_cnt_pulse_former.vhd b/top/blm_aco/BLM_cnt_pulse_former.vhd
new file mode 100644
index 000000000..98cb64e6d
--- /dev/null
+++ b/top/blm_aco/BLM_cnt_pulse_former.vhd
@@ -0,0 +1,46 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.numeric_std.all;
+ 
+
+entity BLM_ct_pulse_former is
+
+    port (
+        CLK         : in std_logic;      -- Clock
+        nRST         : in std_logic;      -- Reset
+        SIG_IN       : in std_logic;    -- Load counter register up input
+        
+        SIG_OUT    : out std_logic      -- UP_Counter overflow
+    
+    );
+end BLM_ct_pulse_former;
+
+
+architecture rtl of BLM_ct_pulse_former is
+
+ 
+    signal sig, last_sig: std_logic;
+    signal cur_sig : std_logic;
+  begin
+
+    cur_sig <= SIG_IN;
+      COUNT_Pulse_former: process (nRST, CLK)
+      begin
+          if (nRST = '0') then    
+            sig <= '0';
+            last_sig <= '0';  
+         
+          elsif (CLK'event and CLK='1') then
+            last_sig <= cur_sig;
+            
+            if (cur_sig ='1') and (last_sig ='0') then 
+
+                sig <= '1';
+            else
+                sig <= '0';
+            end if;
+        end if;
+    end process;
+
+    SIG_OUT <= sig;
+end rtl;
\ No newline at end of file
diff --git a/top/blm_aco/BLM_counter_pool_el.vhd b/top/blm_aco/BLM_counter_pool_el.vhd
index 94774750a..a71255be5 100644
--- a/top/blm_aco/BLM_counter_pool_el.vhd
+++ b/top/blm_aco/BLM_counter_pool_el.vhd
@@ -83,7 +83,7 @@ begin
               
         elsif (clk'EVENT AND clk= '1') then 
 
-            if RESET ='1' then --counter reset
+            if (RESET ='1' or gate_reset_ena = '1') then --counter reset
 
                 cnt_enable <='0';
                 CLEAR <='1';
diff --git a/top/blm_aco/BLM_gate_el_v1.0.vhd b/top/blm_aco/BLM_gate_el_v1.0.vhd
new file mode 100644
index 000000000..e80217826
--- /dev/null
+++ b/top/blm_aco/BLM_gate_el_v1.0.vhd
@@ -0,0 +1,178 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity BLM_gate_timing_seq_elem is
+
+port(
+  clk_i : in std_logic;          -- 
+  rstn_i : in std_logic;        -- reset signal
+  gate_in : in std_logic;        -- input signal
+ direct_gate : in std_logic;
+  prepare : in std_logic;
+  recover : in std_logic;
+  hold: in std_logic_vector(15 downto 0);
+
+  gate_error : out std_logic;  -- gate doesn't start within the given timeout
+  gate_state_nr : out std_logic_vector (2 downto 0); --for tests
+  gate_out: out std_logic        -- out gate signal
+);
+end BLM_gate_timing_seq_elem;
+
+architecture rtl of BLM_gate_timing_seq_elem is
+
+type   gate_state_t is   (idle,prepare_state, gate, waiting, error, recover_state, direct_gate_state);
+signal gate_state:   gate_state_t;
+signal gate_state_sn:   gate_state_t:= idle;
+signal gate_er: std_logic;
+
+signal gate_out_sm: std_logic;
+
+signal curr_val   :std_logic; --:='0';
+signal state_sm: integer range 0 to 6:= 0;
+
+signal timeout_reset : unsigned(29 downto 0); 
+signal timeout : unsigned(29 downto 0);
+signal hold_time: unsigned(15 downto 0);
+
+begin
+
+  state_sm_proc: process(clk_i, rstn_i)--(gate_state)
+  begin
+  if ((rstn_i= '0')) then 
+    state_sm <= 0;
+  elsif rising_edge(clk_i) then
+
+    case gate_state is
+
+      when idle           => state_sm <= 0;
+      when prepare_state  => state_sm <= 1;
+      when gate           => state_sm <= 2;
+      when waiting        => state_sm <= 3;
+      when error          => state_sm <= 4;
+      when recover_state  => state_sm <= 5;
+      when direct_gate_state => state_sm <= 6;
+
+      when others         => null;
+    end case;
+  end if;
+ end process;
+
+
+
+
+gate_proc: process (clk_i, rstn_i)
+
+  begin
+
+      if ((rstn_i= '0')) then 
+        gate_error  <= '0';
+        gate_out <='0';
+        gate_er <='0';
+       gate_state <= idle;
+      gate_state_nr <= "000";
+        curr_val <='0';
+     
+      elsif rising_edge(clk_i) then
+
+        curr_val <= gate_in ;
+       gate_state_nr <=  std_logic_vector(to_unsigned(state_sm, gate_state_nr'length));
+        gate_error <= gate_er;
+        gate_out <= gate_out_sm;
+
+     hold_time <=unsigned(hold); 
+     timeout_reset <= hold_time &"00000000000000";
+         case gate_state is
+
+             when idle =>
+                   timeout <= timeout_reset;
+
+                  if direct_gate ='1' then
+                    gate_state <= direct_gate_state;
+                    gate_er <='0';
+                    
+
+                  else  
+                    if curr_val='1' then --0
+                      gate_er <='1';
+                      gate_state <= error;    
+                     
+                    elsif prepare ='1' then
+                       gate_state <=prepare_state;
+                   
+                     end if;
+                  end if;
+
+             when prepare_state => --1
+                    
+                     if curr_val ='1' then
+                       gate_state <= gate;
+                      gate_out_sm <= '1';
+                     
+                     else
+         
+           
+                            timeout <= timeout -1;
+                            if (to_integer(timeout )=0) then
+                                gate_er <='1';
+                                gate_state <= error;
+                            end if;
+
+                    end if;
+ 
+ 
+              when gate => --2
+                    
+                        if curr_val ='0' then
+                          gate_state <= waiting;
+                          gate_out_sm <='0';
+                         
+                        end if;
+
+              when waiting => --3
+                    
+                          if curr_val ='1' then
+                            gate_state <= error;
+                            gate_er <='1';
+                          
+                          elsif prepare ='0' then
+                           gate_state <= idle;
+                       
+                          end if;
+                
+              when error => --4
+                            gate_er <='1';
+                            if ((recover ='1') and (curr_val ='0')) then
+                                if prepare ='0' then
+                                    gate_state <= recover_state;
+                                end if;
+                            end if;
+                      
+              when recover_state => --5
+                    
+                              if recover ='0' then 
+                               gate_state <= idle;
+                               gate_er<='0';
+                               
+                              end if;
+                
+              when direct_gate_state => --6
+              -- +
+              
+              gate_out_sm <= curr_val;  
+
+              if direct_gate ='0' then
+                gate_state <= idle;
+              end if;
+
+              --gate_out_sm <= curr_val;
+
+              when others => null;
+          end case;
+        end if;
+
+  end process;
+ 
+         	    
+ end rtl;          		 
+	
diff --git a/top/blm_aco/BLM_gate_timing_seq_v1.2.vhd b/top/blm_aco/BLM_gate_timing_seq_v1.2.vhd
new file mode 100644
index 000000000..7bdf33ad0
--- /dev/null
+++ b/top/blm_aco/BLM_gate_timing_seq_v1.2.vhd
@@ -0,0 +1,89 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use work.scu_diob_pkg.all;
+
+entity BLM_gate_timing_seq is
+
+generic (
+  
+  n       : integer range 0 TO 12 :=12
+
+);
+
+port(
+
+  clk_i : in std_logic;         
+  rstn_i : in std_logic;        -- reset signal
+  gate_in : in std_logic_vector(n-1 downto 0);        -- input signal
+  direct_gate : in std_logic_vector(n-1 downto 0);
+ -- gate_seq_ena : in std_logic_vector(n-1 downto 0);     -- enable '1' for input connected to the counter
+  BLM_gate_recover: in std_logic_vector(11 downto 0); 
+  BLM_gate_prepare : in std_logic_vector(11 downto 0); 
+  hold_time : in  t_BLM_gate_hold_Time_Array;
+--  all_thres_ready: in std_logic;
+  gate_error : out std_logic_vector(n-1 downto 0);  -- gate doesn't start within the given timeout
+  state_nr: out t_gate_state_nr;
+  gate_out: out std_logic_vector(n-1 downto 0)        -- out gate signal
+
+);
+end BLM_gate_timing_seq;
+
+architecture rtl of BLM_gate_timing_seq is
+
+  signal    gate_er:         std_logic_vector(n-1 downto 0):= (others =>'0');
+  signal    Gate_In_Mtx:        std_logic_vector (n-1 downto 0):= (others =>'0');
+  signal    gate_state: t_gate_state_nr;
+
+component BLM_gate_timing_seq_elem is
+
+  
+  port(
+    clk_i : in std_logic;          --
+    rstn_i : in std_logic;        -- reset signal
+    gate_in : in std_logic;        -- input signal
+    direct_gate : in std_logic;
+    prepare : in std_logic;
+    recover : in std_logic;
+    hold: in std_logic_vector(15 downto 0);
+--
+    gate_error : out std_logic;  -- gate doesn't start within the given timeout
+   gate_state_nr : out std_logic_vector (2 downto 0); --for tests
+    gate_out: out std_logic      -- out gate signal
+  );
+  end component BLM_gate_timing_seq_elem;
+
+
+begin
+
+  
+
+         BLM_gate_timing: for i in 0 to (n-1) generate
+
+         begin
+    
+          gate_elem: BLM_gate_timing_seq_elem 
+
+       
+            port map(
+              clk_i=> clk_i,
+              rstn_i => rstn_i,
+              gate_in => gate_in(i),
+              direct_gate => direct_gate(i),
+              prepare => BLM_gate_prepare(i),
+              recover => BLM_gate_recover(i),
+              hold => hold_time(i),
+
+              gate_error => gate_er(i), 
+              gate_state_nr => gate_state(i),
+              gate_out => Gate_In_Mtx(i)    -- out gate signal
+            );
+           end generate BLM_gate_timing;
+    
+        
+        gate_error <= gate_er;
+        gate_out <= Gate_In_Mtx;
+         state_nr <= gate_state;
+         
+ end rtl;          		 
+	
diff --git a/top/blm_aco/BLM_out_el_m_v1.0.vhd b/top/blm_aco/BLM_out_el_m_v1.0.vhd
new file mode 100644
index 000000000..05a952366
--- /dev/null
+++ b/top/blm_aco/BLM_out_el_m_v1.0.vhd
@@ -0,0 +1,207 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.numeric_std.all;
+use work.scu_diob_pkg.all;
+use IEEE.std_logic_misc.all;
+
+ 
+entity BLM_out_el is
+    
+port (
+  CLK              : in std_logic;      -- Clock
+  nRST             : in std_logic;      -- Reset
+
+     BLM_out_sel_reg : in t_BLM_out_sel_reg_Array;  -- 122 x 16 bits = Reg120-0:  "0000" and 6 x (54 watchdog errors  + 12 gate errors + 256 counters overflows outputs) 
+                                                     -- + 4 more registers for 6 x 12 input gate (= 72 bits) to be send to the outputs.    
+                                                     --=> 126 registers             
+                                                    --   REg127             ex Reg121: counter outputs buffering enable (bit 15) and buffered output select (bit 7-0). Bits 14-8 not used     
+                                                                            
+
+  UP_OVERFLOW      : in std_logic_vector(127 downto 0);
+  DOWN_OVERFLOW    : in std_logic_vector(127 downto 0);
+
+  wd_out           : in std_logic_vector(53 downto 0);  -- wd_error
+  gate_in          : in std_logic_vector(11 downto 0); -- to be sent to the status registers
+  gate_error       : in std_logic_vector(11 downto 0); -- to be sent to the status registers
+  gate_out        : in std_logic_vector (11 downto 0); --gate error
+  counter_reg: in t_BLM_counter_Array;
+  gate_state: in std_logic_vector(47 downto 0);
+  led_id_state : in std_logic_vector(3 downto 0);
+  BLM_Output      : out std_logic_vector(5 downto 0);
+  --BLM_status_Reg : out t_IO_Reg_0_to_25_Array 
+  BLM_status_Reg : out t_IO_Reg_0_to_29_Array 
+  );
+
+end BLM_out_el;
+
+
+architecture rtl of BLM_out_el is
+
+signal sel_tot: std_logic_vector(2003 downto 0); --I need 4 more 16 bits registers 
+type t_sel is array (0 to 5) of std_logic_vector(333 downto 0);
+signal sel, product: t_sel;
+--type t_int_sel is array (0 to 5) of integer;
+--signal int_sel: t_int_sel;
+
+signal BLM_out_signal, Out_to_or: std_logic_vector(5 downto 0):=(others =>'0');
+
+signal OVERFLOW : std_logic_vector(333 downto 0);
+
+
+--signal gate_input: std_logic_vector(11 downto 0);
+signal out_cnt_wr : std_logic; 
+signal up_down_counter_val: t_BLM_counter_Array;
+signal cnt_readback: std_logic_vector(29 downto 0):=(others =>'0');
+TYPE    t_cnt     is array (0 to 5)  of integer;
+--signal read_cnt: integer range 0 to 127;
+
+signal read_cnt: t_cnt:= (others => 0);
+--signal flag_cnt: t_cnt;
+--signal read_counters: integer range 0 to 255;
+signal read_counters: integer range 0 to 127;
+
+signal ena_out: std_logic_vector(5 downto 0);
+signal gate_output : std_logic_vector(11 downto 0);
+signal gate_error_output: std_logic_vector(11 downto 0);
+signal wd_output: std_logic_vector(53 downto 0);
+signal gate_input : std_logic_vector(11 downto 0);
+
+begin
+
+
+OVERFLOW <= (not (gate_in)) & wd_out& gate_error & UP_OVERFLOW & DOWN_OVERFLOW;
+--gate_input <= gate_in;
+gate_output <= gate_out;
+gate_error_output <=gate_error;
+wd_output <= wd_out;
+gate_input <= gate_in;
+
+sel_signal_proc: process (BLM_out_sel_Reg)
+
+    begin
+
+        for i in 0 to 124 loop 
+            sel_tot((i*16+15) downto i*16)<=  BLM_out_sel_Reg(i);
+            sel_tot(2003 downto 2000) <= BLM_out_sel_Reg(125)(3 downto 0);
+        end loop;
+        
+        for k in 0 to 5 loop
+            sel(k) <= sel_tot((334*(k+1)-1) downto 334*k); 
+        end loop;
+        
+   end process;
+
+
+out_signals_proc: process (OVERFLOW, sel)
+begin
+    for j in 0 to 5 loop
+        for i in 0 to 333 loop
+            product(j)(i) <= sel(j)(i) and OVERFLOW(i);
+        end loop;
+           ena_out(j) <= or_reduce(sel(j));
+           -- if ena_out(j) = '1' then
+            --    BLM_out_signal(j) <= or_reduce(product(j));
+           -- else
+            --    BLM_out_signal(j) <= '1';
+           -- end if;    
+        
+    end loop;    
+end  process;
+
+      
+ena_out_signals_proc: process (clk, nRST)
+begin
+    if not nRST='1' then 
+        for j in 0 to 5 loop
+            
+            BLM_out_signal(j) <= '1';
+        end loop;
+    elsif (clk'EVENT AND clk= '1') then 
+        for j in 0 to 5 loop
+          
+           if ena_out(j) = '1' then
+               BLM_out_signal(j) <= or_reduce(product(j));
+            else
+                BLM_out_signal(j) <= '1';
+           end if;    
+        
+    end loop; 
+        
+    end if;   
+end  process;
+
+      
+----------------------------------------------------------------------------------------
+out_counter_buffer_proc: process (clk, nRST)
+begin
+    if not nRST='1' then 
+        for i in 0 to 127 loop
+            up_down_counter_val(i) <= (others =>'0');
+        end loop;
+         
+           out_cnt_wr <='0';
+  
+        elsif (clk'EVENT AND clk= '1') then 
+           
+                out_cnt_wr<=  BLM_out_sel_reg(126)(15);
+      
+
+               
+                if out_cnt_wr='1' then  
+
+                for i in 0 to 127 loop
+                    up_down_counter_val(i) <= counter_reg(i);
+            
+                    end loop;
+                end if;
+    
+        end if;        
+end process;
+
+    status_reg_counter_value_process: process (up_down_counter_val,  BLM_out_sel_reg(121))
+        begin
+
+            read_counters <= to_integer(unsigned(BLM_out_sel_Reg(126)(6 downto 0)));
+            cnt_readback <= up_down_counter_val(read_counters);
+      
+
+        end process;
+    --------------------------------------------------------------------------------------------------
+     -----                         BLM_STATUS_REGISTERS               
+     --------------------------------------------------------------------------------------------------
+     status_reg_overflow_proc: process (OVERFLOW)
+     begin
+        for i in 0 to 15 loop
+         --   BLM_status_reg(i) <= not OVERFLOW((i*16+15) downto i*16); 
+            BLM_status_reg(i) <=  OVERFLOW((i*16+15) downto i*16);
+        end loop;
+    end process;
+    BLM_status_reg(16) <= "0000"& gate_error_output;
+    BLM_status_reg(17) <= wd_output(15 downto 0);
+    BLM_status_reg(18) <= wd_output(31 downto 16);
+    BLM_status_reg(19) <= wd_output(47 downto 32);
+    BLM_status_reg(20) <= "0000000000" & wd_output(53 downto 48);
+    BLM_status_reg(21) <= cnt_readback(15 downto 0);
+    BLM_status_reg(22) <= cnt_readback(29) & cnt_readback(29) & cnt_readback(29 downto 16);
+    BLM_status_reg(23) <= "0000" & gate_input;
+    BLM_status_reg(24) <= "0000" & gate_output;
+    BLM_status_reg(25) <= "0000000000" & BLM_out_signal; 
+  --  --BLM_status_reg(20) <= "00" & not OVERFLOW(333 downto 320); -- bits 333-321 gate inputs, bits 321-320 = wd_out (53 downto 52)
+ --  -- BLM_status_reg(21)(5 downto 0) <= not BLM_out_signal; -- physical outputs
+ --   BLM_status_reg(20) <= "00" & OVERFLOW(333 downto 320); -- bits 333-321 gate inputs, bits 321-320 = wd_out (53 downto 52)
+ --   BLM_status_reg(21)(5 downto 0) <= BLM_out_signal; -- physical outputs
+ --   BLM_status_reg(21)(15 downto 6)  <= cnt_readback(9 downto 0);    
+ --   BLM_status_reg(22)<= cnt_readback(25 downto 10);
+ --   BLM_status_reg(23) <= gate_output& cnt_readback(29 downto 26);
+
+
+
+ BLM_status_reg(26) <= gate_state(15 downto 0); -- '0'& gate_sm_state(3)& '0'& gate_sm_state(2) & '0'& gate_sm_state(1)&'0'& gate_sm_state(0);
+
+ BLM_status_reg(27) <= gate_state(31 downto 16); -- '0'& gate_sm_state(7)&'0'& gate_sm_state(6)& '0'& gate_sm_state(5) & '0'& gate_sm_state(4)
+ BLM_status_reg(28) <=  gate_state(47 downto 32); --'0'& gate_sm_state(11) & '0'& gate_sm_state(10)& '0'& gate_sm_state(9)&'0'& gate_sm_state(8)
+ BLM_status_reg(29)(15 downto 4) <= (others => '0');
+ BLM_status_reg(29)(3 downto 0) <= led_id_state;
+ BLM_Output <= BLM_out_signal;
+
+end architecture;
\ No newline at end of file
diff --git a/top/blm_aco/Beam_Loss_check_v1.2.vhd b/top/blm_aco/Beam_Loss_check_v1.2.vhd
new file mode 100644
index 000000000..4b0746b12
--- /dev/null
+++ b/top/blm_aco/Beam_Loss_check_v1.2.vhd
@@ -0,0 +1,360 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.numeric_std.all;
+use IEEE.std_logic_misc.all;
+use work.scu_diob_pkg.all;
+
+entity Beam_Loss_check is
+    generic (
+    
+    WIDTH        : integer := 30     -- Counter width
+       
+);
+port (
+    clk_sys           : in std_logic;      -- Clock
+    rstn_sys          : in std_logic;      -- Reset
+
+   -- IN BLM 
+    BLM_data_in       : in std_logic_vector(53 downto 0);
+    BLM_gate_in       : in std_logic_vector(11 downto 0);
+    BLM_tst_ck_sig    : in std_logic_vector (10 downto 0);
+    IOBP_LED_nr       : in std_logic_vector(3 downto 0);
+    --IN registers
+    pos_threshold           : in t_BLM_th_Array; --t_BLM_th_Array is array (0 to 127) of std_logic_vector(31 downto 0);
+    neg_threshold           : in t_BLM_th_Array ;
+    BLM_wdog_hold_time_Reg  : in std_logic_vector(15 downto 0);
+    BLM_wd_reset            : in std_logic_vector(53 downto 0);
+    BLM_gate_hold_time_Reg  : in  t_BLM_gate_hold_Time_Array;
+    BLM_ctrl_Reg            : in std_logic_vector(15 downto 0);  
+                                                                -- bit 11-0 Direct Gate-usage, one bit for each gate signal input (BLM_gate_in), 
+                                                                -- bit 14 reset from gate
+                                                                -- bit 15 free
+
+    BLM_gate_seq_prep_ck_sel_Reg : in std_logic_vector(15 downto 0);-- bit 15 free
+                                                                   -- bit 12counter RESET,
+                                                                   -- bit 11-0f or gate_prepare signals
+                                                                  -- 
+    BLM_gate_recover_Reg : in std_logic_vector(15 downto 0); -- bit 15_12 free
+                                                            -- bit 11-0 for gate_prepare signals
+    BLM_in_sel_Reg          : in t_BLM_reg_Array; --128 x (4 bit for gate ena & 6 bit for up signal ena & 6 for down signal ena)
+    BLM_out_sel_reg : in t_BLM_out_sel_reg_Array;   --- 122 x 16 bits = Reg120-0:  "0000" and 6 x (54 watchdog errors  + 12 gate errors + 256 counters overflows outputs) 
+                                                    -- + 4 more registers for 6 x 12 input gate (= 72 bits) to be send to the outputs.    
+                                                   --=> 126 registers             
+                                                    --   REg127  (ex Reg121): counter outputs buffering enable (bit 15) and buffered output select (bit 7-0). Bits 14-8 not used     
+    -- OUT register
+   -- BLM_status_Reg    : out t_IO_Reg_0_to_25_Array ;
+   BLM_status_Reg : out t_IO_Reg_0_to_29_Array ;
+      -- OUT BLM
+      BLM_Out           : out std_logic_vector(5 downto 0) 
+);
+
+end Beam_Loss_check;
+
+architecture rtl of Beam_Loss_check is
+  
+  signal BLM_test_signal   : std_logic_vector(9 downto 0);  --Test signals + ground  --to reference  Test_In_Mtx
+ 
+  signal gate_clock : std_logic_vector (11 downto 0);  
+  signal g_clock: std_logic_vector(11 downto 0); 
+  signal VALUE_IN:  std_logic_vector(63 downto 0);
+ 
+  signal out_wd: std_logic_vector(53 downto 0);
+  signal out_1wd: std_logic_vector(53 downto 0);
+
+  signal INT_out: std_logic_vector(53 downto 0);
+  signal gate_error: std_logic_vector(11 downto 0);
+  signal Gate_In_Mtx: std_logic_vector (11 downto 0):= (OTHERS => '0');  -- gate outputs from the gate timing sequence control
+  signal UP_OVERFLOW: std_logic_vector(127 downto 0);     
+  signal DOWN_OVERFLOW: std_logic_vector(127 downto 0);  
+  signal gate_sel: integer range 0 to 127;
+  signal cnt_enable: std_logic_vector(127 downto 0);
+  signal BLM_Output_mtx: t_BLM_out_Array;
+  signal gate_output: std_logic_vector (11 downto 0);
+  signal wd_reset: std_logic_vector(53 downto 0);
+  signal BLM_gate_recover: std_logic_vector(11 downto 0);
+  signal BLM_gate_seq_clk_sel: std_logic_vector(2 downto 0);
+  signal BLM_gate_prepare : std_logic_vector(11 downto 0);
+  signal counter_value: t_BLM_counter_Array;
+signal gate_test_value: std_logic_vector(11 downto 0);
+signal gate_sm_error: std_logic_vector(11 downto 0);
+signal gate_sm_output: std_logic_vector(11 downto 0);
+signal gate_recover: std_logic_vector(11 downto 0);
+signal gate_prepare: std_logic_vector(11 downto 0);
+signal gate_hold_time: t_BLM_gate_hold_Time_Array;
+signal gate_state: std_logic_vector(47 downto 0);
+signal gate_sm_state :t_gate_state_nr;
+
+signal UP_OVERFLOW_OUT: std_logic_vector(127 downto 0):=(others => '0');
+signal DOWN_OVERFLOW_OUT: std_logic_vector(127 downto 0):=(others => '0');
+signal direct_gate: std_logic_vector(11 downto 0);
+signal LED_ID_state:  std_logic_vector(3 downto 0);
+
+  component BLM_watchdog is
+  
+    port(
+        clk_i : in std_logic;     -- chip-internal pulsed clk signal
+        rst_i : in std_logic;   -- reset signal
+        wd_reset: in std_logic; -- watchdog reset signal
+        hold: in std_logic_vector(15 downto 0);
+        in_watchdog : in std_logic;     -- input signal
+       -- ena_i : in std_logic;     -- enable '1' for input connected to the counter
+        INTL_out: out std_logic   -- interlock output for signal that doesn't change for a given time 
+    
+    );
+end component BLM_watchdog;
+
+component BLM_gate_timing_seq is
+
+    generic (
+ 
+
+      n       : integer range 0 TO 12 := 12
+    );
+    port(
+      clk_i : in std_logic;
+      rstn_i : in std_logic;        -- reset signal
+      gate_in : in std_logic_vector(n-1 downto 0);        -- input signal
+      direct_gate : in std_logic_vector(n-1 downto 0);
+      BLM_gate_recover: in std_logic_vector(11 downto 0); 
+      BLM_gate_prepare : in std_logic_vector(11 downto 0); 
+      hold_time : in  t_BLM_gate_hold_Time_Array;
+      gate_error : out std_logic_vector(n-1 downto 0); -- gate doesn't start within the given timeout
+    state_nr: out t_gate_state_nr;
+      gate_out: out std_logic_vector(n-1 downto 0)        -- out gate signal
+    );
+    end component BLM_gate_timing_seq;
+
+  component  BLM_ena_in_mux is
+      port (
+          CLK               : in std_logic;      -- Clock
+          nRST              : in std_logic;      -- Reset
+          mux_sel           : in t_BLM_reg_Array;
+          in_mux            : in std_logic_vector(11 downto 0);
+          cnt_enable        : out std_logic_vector(127 downto 0)
+      );
+  end component BLM_ena_in_mux;
+
+
+ component BLM_counter_pool_el is
+
+    generic (      
+        WIDTH        : integer := 30      -- Counter width
+            
+    );
+    port (
+        CLK               : in std_logic;      -- Clock
+        nRST              : in std_logic;      -- Reset
+        gate_reset_ena    : in std_logic;
+        RESET      : in std_logic;      -- global counter reset
+        ENABLE            : in std_logic;      -- Enable count operation (gate signals)
+        pos_threshold     : in std_logic_vector(31 downto 0);
+        neg_threshold     : in std_logic_vector(31 downto 0);
+        in_counter        : in std_logic_vector(63 downto 0);
+        BLM_cnt_Reg     : in std_logic_vector(15 downto 0);  -- bit 5-0 = up_in_counter select, bit 11-6 = down_in_counter select, 15..13 in_ena
+        cnt    : out std_logic_vector (WIDTH-1 downto 0);    -- Counter register
+   
+        UP_OVERFLOW       : out std_logic;     -- UP_Counter overflow for the input signals
+        DOWN_OVERFLOW     : out std_logic    -- DOWN_Counter overflow for the input signals
+
+    );
+  end component BLM_counter_pool_el;
+  
+
+  component  BLM_out_el is
+    
+      port (
+        CLK              : in std_logic;      -- Clock
+        nRST             : in std_logic;      -- Reset
+        BLM_out_sel_reg : in t_BLM_out_sel_reg_Array;   -- 122 x 16 bits = Reg120-0:  "0000" and 6 x (54 watchdog errors  + 12 gate errors + 256 counters overflows outputs) 
+                                                        --                 Reg121: counter outputs buffering enable (bit 15) and buffered output select (bit 7-0). Bits 14-8 not used               
+        UP_OVERFLOW      : in std_logic_vector(127 downto 0);
+        DOWN_OVERFLOW    : in std_logic_vector(127 downto 0);
+        
+        wd_out           : in std_logic_vector(53 downto 0); 
+        gate_in          : in std_logic_vector(11 downto 0); -- to be sent to the status registers
+        gate_error        : in std_logic_vector (11 downto 0); 
+        gate_out        : in std_logic_vector (11 downto 0); 
+        counter_reg: in t_BLM_counter_Array;
+      
+        gate_state: in std_logic_vector(47 downto 0);
+        led_id_state : in std_logic_vector(3 downto 0);
+        BLM_Output      : out std_logic_vector(5 downto 0);
+      --  BLM_status_Reg : out t_IO_Reg_0_to_25_Array 
+      BLM_status_Reg : out t_IO_Reg_0_to_29_Array   
+        );
+     
+    end component BLM_out_el;
+
+   
+---######################################################################################
+
+begin
+
+VALUE_IN <= BLM_test_signal & BLM_data_in;
+BLM_gate_recover <= BLM_gate_recover_Reg(11 downto 0);
+BLM_gate_prepare <= BLM_gate_seq_prep_ck_sel_Reg(11 downto 0);
+--direct_gate <= BLM_ctrl_Reg(11 downto 0);
+direct_gate <= BLM_ctrl_Reg(5 downto 0) & BLM_ctrl_Reg(11 downto 6);
+g_clock <= gate_clock;
+
+BLM_test_signal <=  BLM_tst_ck_sig(9) & -- 25 MHz
+                    BLM_tst_ck_sig(8)  & -- 24.9 MHz
+                    BLM_tst_ck_sig(7)  & -- 10 MHz
+                    BLM_tst_ck_sig(2)  & -- 9.9 MHz
+                    BLM_tst_ck_sig(6)  & -- 1 MHz
+                    BLM_tst_ck_sig(1)  & -- 0.99 MHz
+                    BLM_tst_ck_sig(5)  & -- 100 kHz
+                    BLM_tst_ck_sig(0)  & -- 99 kHz
+                    BLM_tst_ck_sig(4)  & -- 10 kHz
+                    '0';                 -- GND
+
+-- for direct Gate operations: if the corresponding BLM_ctrl_Reg (bit +2)='0' then BLM_gate_in signals 
+-- are used as input signal to the multiplexer  (BLM_ena_in_mux) which gives the counter enables.
+
+
+LED_ID_state <= IOBP_LED_nr;
+direct_gate_operation: process(BLM_ctrl_Reg, BLM_gate_in, gate_output)
+
+begin
+
+  for i in 0 to 5 loop
+    
+    if BLM_ctrl_Reg(i) = '1' then   --when '0', gate signals are directly sent to the 12 to 126 multiplexer for the counter enables assignments
+      gate_In_Mtx(i)<= BLM_gate_in(i+6);
+    else 
+      gate_IN_Mtx(i) <= gate_output(i+6);
+    end if;
+  end loop;
+  for i in 6 to 11 loop
+    
+    if BLM_ctrl_Reg(i) = '1' then   --when '0', gate signals are directly sent to the 12 to 128 multiplexer for the counter enables assignments
+      gate_In_Mtx(i)<= BLM_gate_in(i-6);
+    else 
+      gate_IN_Mtx(i) <= gate_output(i-6);
+    end if;
+  end loop;
+end process direct_gate_operation;
+
+
+  gate_board: BLM_gate_timing_seq
+
+    generic map (
+      n        => 12
+    )
+    port map(
+      clk_i => clk_sys,         --
+      rstn_i => rstn_sys,         -- reset signal
+      gate_in => BLM_gate_in,       -- gate input signals
+      direct_gate => direct_gate,
+      BLM_gate_recover => BLM_gate_recover(5 downto 0)&BLM_gate_recover(11 downto 6),
+      BLM_gate_prepare => BLM_gate_prepare(5 downto 0)&BLM_gate_prepare(11 downto 6),
+      hold_time => gate_hold_time,
+
+      gate_error => gate_sm_error, -- gate error
+      state_nr => gate_sm_state,
+      gate_out => gate_sm_output --gate_output
+    );
+
+  gate_error <= gate_sm_error;
+  gate_output <= gate_sm_output;
+
+  gate_state <= '0'& gate_sm_state(5) & '0'& gate_sm_state(4)& '0'& gate_sm_state(3)&'0'& gate_sm_state(2) & '0'& gate_sm_state(1)&'0'& gate_sm_state(0)&
+  '0'& gate_sm_state(11) & '0'& gate_sm_state(10)& '0'& gate_sm_state(9)&'0'& gate_sm_state(8) & '0'& gate_sm_state(7)&'0'& gate_sm_state(6);
+
+
+  gate_hold_time_proc: process(BLM_gate_hold_time_Reg)
+
+    begin
+      for i in 0 to 5 loop
+        gate_hold_time(i) <= BLM_gate_hold_time_Reg(i+6);
+      end loop;
+      for i in 6 to 11 loop
+        gate_hold_time(i) <= BLM_gate_hold_time_Reg(i-6);
+      end loop;
+
+    end process gate_hold_time_proc;
+
+       wd_elem_gen: for i in 0 to 53 generate
+
+        input_Watchdog: BLM_watchdog
+         
+          port map(
+            clk_i => clk_sys,  
+            rst_i => rstn_sys,   -- reset signal
+            wd_reset=>  BLM_wd_reset(i), -- watchdog reset signal
+            hold => BLM_wdog_hold_time_Reg,
+            in_watchdog => BLM_data_in(i),
+          --  ena_i =>    '1',  -- enable for input connected to the counter
+            INTL_out =>   out_1wd(i));
+            --INTL_out =>   out_wd(i));
+      end generate wd_elem_gen;
+
+
+
+
+---- counter ena mux ------------------------------------------------------------------------------
+BLM_counter_ena_block:  BLM_ena_in_mux 
+  port  map(
+    CLK            => clk_sys,  
+    nRST           => rstn_sys,
+    mux_sel        => BLM_in_sel_Reg,
+    in_mux         => gate_In_Mtx,
+    cnt_enable     => cnt_enable
+  );
+
+
+  ---- counter pool ------------------------------------------------------------------------------
+
+BLM_counter_pool: for i in 0 to 127 generate
+
+BLM_counter_pool_elem: BLM_counter_pool_el
+generic map (      
+      WIDTH  => 30)
+port map (
+  CLK            => clk_sys,  
+  nRST           => rstn_sys,
+  gate_reset_ena => BLM_ctrl_reg(14) and cnt_enable(i),
+  RESET          => BLM_gate_seq_prep_ck_sel_Reg(12),
+  ENABLE         => cnt_enable(i),
+  pos_threshold  => pos_threshold(i),
+  neg_threshold  => neg_threshold(i),
+  in_counter     => VALUE_IN,
+  
+  BLM_cnt_Reg    => BLM_in_sel_Reg(i),
+  cnt   => counter_value(i),
+
+  UP_OVERFLOW    => UP_OVERFLOW(i),
+  DOWN_OVERFLOW  => DOWN_OVERFLOW(i)
+  );
+      end generate BLM_counter_pool;
+-----------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------
+
+
+BLM_out_section: BLM_out_el 
+     
+  port map(
+    CLK          => clk_sys,
+    nRST           => rstn_sys,   -- Reset
+    -- +++
+    BLM_out_sel_reg => BLM_out_sel_reg, 
+    --
+  UP_OVERFLOW  =>UP_OVERFLOW,
+   -- UP_OVERFLOW => neg_threshold(0) & pos_threshold(0)&UP_OVERFLOW(63 downto 0),
+   --UP_OVERFLOW     => UP_OVERFLOW(127 downto 80)& gate_state & "0000"& BLM_gate_in(5 downto 0) & BLM_gate_in(11 downto 6)& "0000"& gate_output(5 downto 0) & gate_output(11 downto 6), -- UP_OVERFLOW & gate_in & gate_out , -- ONLY FOR TESTS 
+   --DOWN_OVERFLOW   => DOWN_OVERFLOW_OUT,
+   DOWN_OVERFLOW   => DOWN_OVERFLOW,
+    wd_out           => out_1wd, --out_wd, --out_1wd,
+    gate_in         => BLM_gate_in(5 downto 0) & BLM_gate_in(11 downto 6),--BLM_gate_in,
+    gate_error        => gate_error(5 downto 0) & gate_error(11 downto 6),
+    gate_out        => gate_output(5 downto 0) & gate_output(11 downto 6),
+    gate_state      => gate_state,
+    led_id_state    => LED_ID_state,
+    BLM_Output      => BLM_out,
+    counter_reg =>  counter_value,   
+    BLM_status_Reg  => BLM_status_Reg 
+    );
+
+
+  end architecture;
+
diff --git a/top/blm_aco/IOBP_LED_ID_module_v1.0.vhd b/top/blm_aco/IOBP_LED_ID_module_v1.0.vhd
new file mode 100644
index 000000000..ea16672a5
--- /dev/null
+++ b/top/blm_aco/IOBP_LED_ID_module_v1.0.vhd
@@ -0,0 +1,149 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.numeric_std.all;
+use work.scu_diob_pkg.all;
+
+entity IOBP_LED_ID_Module is
+
+port (
+        clk_sys           : in  std_logic;      
+        rstn_sys          : in  std_logic;      
+    --    Ena_Every_250ns   : in  std_logic; 
+    Ena_Every_500ns       : in std_logic;
+        AW_ID             : in  std_logic_vector(7 downto 0); -- Application_ID
+        IOBP_LED_ID_Bus_i : in  std_logic_vector(7 downto 0);   -- LED_ID_Bus_In
+        IOBP_Aktiv_LED_o  : in  t_led_array;    -- Active LEDs of the "Slave-Boards"
+        IOBP_Sel_LED      : in  t_led_array;    -- Sel-LED of the "Slave-Boards"
+        IOBP_LED_En       : out std_logic; -- Output-Enable for LED -ID-Bus
+        IOBP_STR_rot_o    : out std_logic_vector(12 downto 1);  -- LED-Str Red  for Slave 12-1
+        IOBP_STR_gruen_o  : out std_logic_vector(12 downto 1);  -- LED-Str Green for Slave 12-1
+        IOBP_STR_ID_o     : out std_logic_vector(12 downto 1);  -- ID-Str Green for Slave 12-1
+        IOBP_LED_ID_Bus_o : out std_logic_vector(7 downto 0);   -- LED_ID_Bus_Out
+        IOBP_ID           : out t_id_array ;    -- IDs of the "Slave-Boards"
+        IOBP_LED_state_nr : out std_logic_vector(3 downto 0)
+        );
+        end IOBP_LED_ID_Module;
+        
+architecture rtl of IOBP_LED_ID_Module is
+
+signal Slave_Loop_cnt:      integer range 0 to 12;         -- 1-12   -- Loop-Counter
+
+type   IOBP_LED_state_t is   (IOBP_START_DEL, IOBP_idle, led_id_wait, led_id_loop, led_str_rot_h, led_str_rot_l, led_gruen,
+                              led_str_gruen_h, led_str_gruen_l, iobp_led_dis, iobp_led_z, iobp_id_str_h, iobp_rd_id, iobp_id_str_l, iobp_end);
+--signal IOBP_state:   IOBP_LED_state_t:= IOBP_idle;
+signal IOBP_state:   IOBP_LED_state_t:= IOBP_START_DEL;        
+
+signal state_sm: integer range 0 to 15:= 0;
+begin
+
+
+    state_sm_proc: process(clk_sys, rstn_sys)--(IOBP_state)
+    begin
+    if ((rstn_sys= '0')) then 
+      state_sm <= 0;
+    elsif rising_edge(clk_sys) then
+  
+      case IOBP_state is
+  
+        when IOBP_START_DEL          => state_sm <= 0;
+        when IOBP_idle               => state_sm <= 1;
+        when led_id_wait             => state_sm <= 2;
+        when led_id_loop             => state_sm <= 3;
+        when led_str_rot_h           => state_sm <= 4;
+        when led_str_rot_l           => state_sm <= 5;
+        when led_gruen               => state_sm <= 6;
+        when led_str_gruen_h         => state_sm <= 7;
+        when led_str_gruen_l         => state_sm <= 8;
+        when iobp_led_dis            => state_sm <= 9;
+        when iobp_led_z              => state_sm <= 10;
+        when iobp_id_str_h           => state_sm <= 11;
+        when iobp_rd_id              => state_sm <= 12;
+        when iobp_id_str_l           => state_sm <= 13;
+        when iobp_end                => state_sm <= 14;
+        when others                  => state_sm <= 15;
+
+      end case;
+    end if;
+   end process;
+
+
+--P_IOBP_LED_ID_Loop:  process (clk_sys, Ena_Every_250ns, rstn_sys, IOBP_state)
+P_IOBP_LED_ID_Loop:  process (clk_sys, Ena_Every_500ns, rstn_sys, IOBP_state)
+
+    begin
+      if (not rstn_sys = '1') then
+        Slave_Loop_cnt       <=   1;                 --  Loop-Counter
+        IOBP_LED_En          <=  '0';                --  Output-Enable for LED- ID-Bus
+        IOBP_STR_rot_o       <=  (others => '0');    --  Led-Strobs 'red'
+        IOBP_STR_gruen_o     <=  (others => '0');    --  Led-Strobs 'green'
+        IOBP_STR_id_o        <=  (others => '0');    --  ID-Strobs
+        IOBP_state           <=  IOBP_START_DEL;
+        IOBP_LED_state_nr    <="0000";
+
+    ELSIF (clk_sys'EVENT AND clk_sys = '1' AND Ena_Every_500ns = '1') THEN
+   -- ELSIF (clk_sys'EVENT AND clk_sys = '1' AND Ena_Every_250ns = '1') THEN
+--  ELSIF ((rising_edge(clk_sys)) or Ena_Every_100ns)  then
+
+    IOBP_LED_state_nr <=  std_logic_vector(to_unsigned(state_sm, IOBP_LED_state_nr'length));
+
+      case IOBP_state is
+        when IOBP_START_DEL => IOBP_state  <= IOBP_idle;
+
+        when IOBP_idle   =>  Slave_Loop_cnt       <=  1;                 -- Loop-Counter
+
+                            if  (AW_ID(7 downto 0) = "00010011") THEN  IOBP_state  <= led_id_wait; -- AW_ID(7 downto 0) = c_AW_INLB12S1.ID
+                                                                       else  IOBP_state  <= IOBP_START_DEL;
+                            end if;
+
+        when led_id_wait      =>  IOBP_LED_En          <=  '1';                --  Output-Enable for LED- ID-Bus
+                                  IOBP_state  <= led_id_loop;
+
+        when led_id_loop      =>  IOBP_LED_ID_Bus_o(7 downto 6)  <=  ("0" & "0");
+                                  IOBP_LED_ID_Bus_o(5 downto 0)  <=  IOBP_Aktiv_LED_o(Slave_Loop_cnt)(6 downto 1);   -- Active-LED for Slave to LED-Port
+                                  IOBP_state  <= led_str_rot_h;
+
+        when led_str_rot_h    =>  IOBP_STR_rot_o(Slave_Loop_cnt) <=  '1';   -- Active LED for Slave (Slave_Loop_cnt) to LED-Port
+                                  IOBP_state  <= led_str_rot_l;
+
+        when led_str_rot_l    =>  IOBP_STR_rot_o(Slave_Loop_cnt) <=  '0';   -- Active LED for Slave (Slave_Loop_cnt) to LED-Port
+                                  IOBP_state  <= led_gruen;
+
+        when led_gruen        =>  IOBP_LED_ID_Bus_o(7 downto 6)  <=  ("0" & "0");
+                                  IOBP_LED_ID_Bus_o(5 downto 0)  <=  not IOBP_Sel_LED(Slave_Loop_cnt)(6 downto 1);   -- Sel-LED for Slave to LED-Port
+                                  IOBP_state  <= led_str_gruen_h;
+
+        when led_str_gruen_h  =>  IOBP_STR_gruen_o(Slave_Loop_cnt) <=  '1';   -- Sel-LED for Slave (Slave_Loop_cnt) to LED-Port
+                                  IOBP_state  <= led_str_gruen_l;
+
+        when led_str_gruen_l  =>  IOBP_STR_gruen_o(Slave_Loop_cnt) <=  '0';   -- Sel-LED for Slave (Slave_Loop_cnt)to LED-Port
+                                  IOBP_state  <= iobp_led_dis;
+
+        when iobp_led_dis     =>  IOBP_LED_En <=  '0';                        --  Disable Output for LED- ID-Bus
+                                  IOBP_state  <= iobp_led_z;
+
+        when iobp_led_z       =>  IOBP_state  <= iobp_id_str_l;
+
+        when iobp_id_str_l    =>  IOBP_STR_ID_o(Slave_Loop_cnt) <=  '1';   -- Sel-ID for Slave (Slave_Loop_cnt)
+                                  IOBP_state  <= iobp_rd_id;
+
+        when iobp_rd_id       =>  IOBP_ID(Slave_Loop_cnt) <=  IOBP_LED_ID_Bus_i;   -- Sel-ID for Slave (Slave_Loop_cnt)
+                                  IOBP_state  <= iobp_id_str_h;
+
+        when iobp_id_str_h    =>  IOBP_STR_ID_o(Slave_Loop_cnt) <=  '0';   -- Sel-ID for Slave (Slave_Loop_cnt)
+                                  IOBP_state  <= iobp_end;
+
+        when iobp_end         =>  Slave_Loop_cnt <=  Slave_Loop_cnt + 1;       -- Loop +1
+
+                                  if Slave_Loop_cnt < 13 then
+                                    IOBP_state     <= led_id_wait;
+                                  else
+                                    IOBP_state     <= IOBP_idle;
+                                  end if;
+
+        when others           =>  IOBP_state       <= IOBP_START_DEL;
+
+      end case;
+    end if;
+  end process P_IOBP_LED_ID_Loop;
+  
+  end rtl; 
diff --git a/top/blm_aco/Manifest.py b/top/blm_aco/Manifest.py
index 35dc30b86..bd8ead701 100644
--- a/top/blm_aco/Manifest.py
+++ b/top/blm_aco/Manifest.py
@@ -1,5 +1,5 @@
 files = [
-   "blm_aco.vhd",
+   "blm_aco_v1.0.vhd",
    "scu_diob_pkg.vhd",
    "scu_diob.sdc",
    "diob_debounce.vhd",
@@ -21,22 +21,21 @@
    "fg901040.vhd",
    "in_reg.vhd",
    "BLM_watchdog_v1.0.vhd",
-   "BLM_gate_timing_seq.vhd",
+   "BLM_gate_timing_seq_v1.2.vhd",
    "up_down_counter.vhd",
-   "Beam_Loss_check_v1.1.vhd",
+   "Beam_Loss_check_v1.2.vhd",
    "front_board_id_v0.vhd",
    "BLM_counter_pool_el.vhd",
-   #"BLM_out_el.vhd",
-   "BLM_out_el_m.vhd",
-   "IOBP_LED_ID_Module.vhd",
+   "BLM_out_el_m_v1.0.vhd",
+  # "IOBP_LED_ID_Module.vhd",
+  "IOBP_LED_ID_module_v1.0.vhd",
    "p_connector.vhd",
    "BLM_in_mux.vhd",
-   "BLM_gate_timing_seq_elem.vhd",
+   "BLM_gate_el_v1.0.vhd",
    "BLM_ena_in_mux.vhd",
    "blm_24_9_9_9pll.vhd",
-   "deglitcher.v"
-  # "gate_deglitcher.v",
-   #"deglitcher_v1.vhd"
+   "deglitcher.v",
+   "BLM_cnt_pulse_former.vhd"
 ]
 
 modules = {
diff --git a/top/blm_aco/blm_aco_v1.0.vhd b/top/blm_aco/blm_aco_v1.0.vhd
new file mode 100644
index 000000000..a0e11dde9
--- /dev/null
+++ b/top/blm_aco/blm_aco_v1.0.vhd
@@ -0,0 +1,2552 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.gencores_pkg.all;
+use work.scu_bus_slave_pkg.all;
+use work.aux_functions_pkg.all;
+use work.scu_diob_pkg.all;
+use work.pll_pkg.all;
+use work.monster_pkg.all;
+use work.daq_pkg.all;
+
+
+--  Base_addr    : DIOB-Config-Register1 (all bits can be read and written)
+--  +------------+---------------------------+------------------------------------------------------------------------------------------------------------------
+--  | Bit 15     | Test-Mode                 | 1 = Testmodus; for commissioning and diagnostics, 0 = Normal mode (default)
+--  +------------+---------------------------+------------------------------------------------------------------------------------------------------------------
+--  | Bit 14..12 | InReg-Debounce-Time       | Debounce time for digital inputs ;
+--  |            |                           | Debounce time  in in 2x µs; parameter Exponent (x) for Debounce time;
+--  |            |                           | Wertebereich 1 ... 128 µs *)
+--  +------------+---------------------------+------------------------------------------------------------------------------------------------------------------
+--  | Bit 11     | InReg-Debounce-Enable     | Control (Switching on/off) of the Debounce time (debouncing unit) for external digital signals
+--  |            |                           | 1 = Debouncing switched off
+--  |            |                           | 0 = Debouncing switched on
+--  +------------+---------------------------+------------------------------------------------------------------------------------------------------------------
+--  | Bit 10..8  | MirrorMode-InReg-Sel      | Selection of the input register for mirroring of the selected output register(see MirrorMode-OutReg-Sel)
+--  |            |                           | 0 = inactive
+--  |            |                           | 1...7 = Inputregisters 1 to 7; all unmasked bits (see MirrorMode-OutReg-Mask) of the output register x
+--  |            |                           | (x selected through MirrorMode-OutReg-Sel) are copied to the here selectedt input register (mirrored)
+--  +------------+---------------------------+------------------------------------------------------------------------------------------------------------------
+--  | Bit 7..5   | MirrorMode-OutReg-Sel     | Selection of the output register for mirroring of the bits in input register x (x selected through MirrorMode-InReg-Sel)
+--  |            |                           | 0 = inactive
+--  |            |                           | 1...7 = Outputregisters 1 to 7
+--  +------------+---------------------------+------------------------------------------------------------------------------------------------------------------
+--  | Bit 4      |--  Reserve                |
+--  +------------+---------------------------+------------------------------------------------------------------------------------------------------------------
+--  | Bit 3      | MirrorMode-OutReg         | Enables mirroring of the selected output register (MirrorMode-OutReg-Sel) to input register 1 or 2;
+--  |            |                           | 1 = Mirroring enabled
+--  |            |                           | 0 = Mirroring deactivated (default)
+--  +------------+---------------------------+------------------------------------------------------------------------------------------------------------------
+--  | Bit 2      | Clear-CntUnit-Config      | 1 = clearing all configuration registers of the counter channels(CounterUnit-Config-Reg 1 und 2)
+--  |            |                           | Bit is automatically deleted after evaluation; cannot be read back
+--  +------------+---------------------------+------------------------------------------------------------------------------------------------------------------
+--  | Bit 1      | Clear-CmpUnit-Config      | 1 = delete all configuration registers of the compare channels (CmpUnit-Config-Reg 1 und 2)
+--  |            |                           | Bit is automatically deleted after evaluation; cannot be read back
+--  +------------+---------------------------+------------------------------------------------------------------------------------------------------------------
+--  | Bit 0      | Clear-TAG-Config          | 1 = delete all configuration registers of the event control(TAG-Filtering)
+--  |                                        | Bit is automatically deleted after evaluation; cannot be read back
+--  +------------+---------------------------+------------------------------------------------------------------------------------------------------------------
+--                                                                                                                                --
+--                                                                                                                                --
+--                                                                                                                                --
+--      Base_addr +1 : DIOB-Config-Register2 (all bits can be read and written)                                                   --
+--   -----+-------------------------------------------------------------------------------------------------------------------    --
+--   15-0 |  free                                                                                                                 --
+--   -----+-------------------------------------------------------------------------------------------------------------------    --
+--                                                                                                                                --
+--                                                                                                                                --
+--      Base_addr +2 : DIOB-Status-Register1 (the status bits are deleted after reading)                                          --
+--   -----+-------------------------------------------------------------------------------------------------------------------    --
+--     15-6|  free                                                                                                                --
+--   -----+-------------------------------------------------------------------------------------------------------------------    --
+--      5-0|  Tag-Ctrl Status                                                                                                     --
+--   -----+-------------------------------------------------------------------------------------------------------------------    --
+--                                                                                                                                --
+--                                                                                                                                --
+--      Base_addr +3 : DIOB-Status-Register2 (the status bits are deleted after reading)                                          --
+--   -----+-------------------------------------------------------------------------------------------------------------------    --
+--   15-8 |  free                                                                                                                 --
+--   -----+-------------------------------------------------------------------------------------------------------------------    --
+--    7-0 |  Tag_Active           -- Flag: Bit7 = Tag7 (active) --- Bit0 = Tag0 (active)                                          --                                                                                                        --
+--   -----+-------------------------------------------------------------------------------------------------------------------    --
+
+--                                                                                                                                --
+--                                                                                                                                --
+--     Base_addr + 4 – Base_addr +6  reserved for expansion                                                                       --
+-----+------------------------------------------------------------------------------------------------------------------
+--     Base_addr + 7 Configuration register1 for interface part: The bits in the user (piggy)config register1 have a different    --
+--     meaning for each piggy                                                                                                     --
+--                                                                                                                                --
+------------------------------------------------------------------------------------------------------------------------------------
+entity blm_aco is
+generic (
+    CLK_sys_in_Hz:      integer := 125000000;
+    g_card_type:        string := "diob"
+        );
+
+port  (
+    ------------------------------ Clocks -------------------------------------------------------------------------
+    CLK_20MHz_A: in std_logic; -- Clock_A
+    CLK_20MHz_B: in std_logic; -- Clock_B
+    CLK_20MHz_C: in std_logic; -- Clock_C
+    CLK_20MHz_D: in std_logic; -- Clock_D
+
+    --------- Parallel SCU-Bus-Signals ----------------------------------------------------------------------------
+    A_A: in std_logic_vector(15 downto 0); -- SCU-Adress Bus
+    A_nADR_EN: out std_logic := '0'; -- '0' => external address driver of the slave active
+    A_nADR_FROM_SCUB: out std_logic := '0'; -- '0' => external address driver direction: SCU bus to slave
+    A_D: inout std_logic_vector(15 downto 0); -- SCU-Data Bus
+    A_nDS: in std_logic; -- Data strobe driven by master
+    A_RnW: in std_logic; -- Write/Read signal driven by master, '0' => read
+    A_nSel_Ext_Data_Drv: out std_logic; -- '0' => external data driver of the slave active
+    A_Ext_Data_RD: out std_logic; -- '0' => External data driver direction: SCU bus to slave (better default 0, or swap driver A/B)                                                             
+    A_nDtack: out std_logic; -- Data-Acknowlege zero active, '0' => enables external open drain driver
+    A_nSRQ: out std_logic; -- Service-Request zero active,   '0' => enables external open drain driver
+    A_nBoardSel: in std_logic; -- '0' => Master activates this slave
+    A_nEvent_Str: in std_logic; -- '0' => Master signals timing cycle
+    A_SysClock: in std_logic; -- Clock driven by master
+    A_Spare0: in std_logic; -- driven by master
+    A_Spare1: in std_logic; -- driven by master
+    A_nReset: in std_logic; -- Reset (active '0'), driven by master
+
+    A_nSEL_Ext_Signal_DRV: out std_logic; -- '0' => Driver for SCU bus control signals active
+    A_nExt_Signal_in: out std_logic; -- '0' => Driver for SCU bus control signals direction: SCU bus to slave (better default 0, or swap driver A/B)
+
+    ----------------- OneWire ----------------------------------------------------------------------------------------
+    A_OneWire: inout std_logic; -- Temp.-OneWire on the Slave
+
+    ------------ Logic analyser Signals -------------------------------------------------------------------------------
+    A_SEL: in std_logic_vector(3 downto 0); -- use to select sources for the logic analyser ports
+    A_Tclk: out std_logic; -- Clock  for logic analiser Port A
+    A_TA:   out std_logic_vector(15 downto 0); -- test port a
+
+    ---------------------------------- Diagnose-LED's -----------------------------------------------------------------
+    A_nLED_D2: out std_logic; -- Diagnosis-LED_D2 on the Base-Board
+    A_nLED_D3: out std_logic; -- Diagnosis-LED_D3 on the Base-Board
+
+    ------------ User I/O to VG-Bar -------------------------------------------------------------------------------
+    A_nUser_EN: out std_logic; -- Enable User-I/O
+    UIO: inout std_logic_vector(15 downto 0); -- User I/O VG-Bar
+
+    ---------------- Transfer connector for user I/O-----------------------------------------------------------------
+    CLK_IO: in std_logic; -- Clock for user_I/0
+    PIO: inout std_logic_vector(150 downto 16)  -- Dig. User I/0 to Piggy
+    );
+end blm_aco;
+
+
+architecture blm_aco_arch_for_Beam_Loss_Mon of blm_aco is
+
+--  +============================================================================================================================+
+--  |                                 Firmware_Version/Firmware_Release and Base-Addresses                                      |
+--  +============================================================================================================================+
+
+    CONSTANT c_Firmware_Version:    Integer := 0;      -- Firmware_Version
+    CONSTANT c_Firmware_Release:    Integer := 29;     -- Firmware_release Stand 19.05.2021 ( + neuer Zwischen-Backplane )
+--  CONSTANT c_Firmware_Release:    Integer := 16#FF#; -- Test-Firmware_release
+    CONSTANT clk_switch_status_cntrl_addr:       unsigned := x"0030";
+    CONSTANT c_lm32_ow_Base_Addr:   unsigned(15 downto 0):=  x"0040";  -- housekeeping/LM32
+    CONSTANT c_tmr_Base_Addr:       unsigned(15 downto 0):=  x"0330";  -- Timer
+    CONSTANT c_Conf_Sts1_Base_Addr:              Integer := 16#0500#;  -- Status-Config-Register 
+    CONSTANT c_AW_Port1_Base_Addr:               Integer := 16#0510#;  -- Anwender I/O-Register
+    CONSTANT c_Tag_Ctrl1_Base_Addr:              Integer := 16#0580#;  -- Tag-Control
+    CONSTANT c_IOBP_Masken_Base_Addr:            Integer := 16#0630#;  -- IO-Backplane Maske-Register
+    CONSTANT c_IOBP_ID_Base_Addr:                Integer := 16#0638#;  -- IO-Backplane Modul-ID-Register
+    CONSTANT c_Status_READBACK_Base_Addr:        Integer := 16#0670#;  -- IO-Backplane Output Readback Register: 24 x 16 bit registers --> +18h 
+    CONSTANT c_DIOB_DAQ_Base_Addr:               Integer := 16#2000#;  -- DAQ Base Address
+    CONSTANT c_BLM_thres_Base_Addr:              Integer := 16#0700#;  -- BLM threshold for the counter pool: 512 16 bit registers--> + 200h
+    CONSTANT c_BLM_in_sel_Base_Addr:             Integer := 16#1000#;   --BLM input mux select registers :      128 16 bit registers -->80h
+    CONSTANT c_BLM_out_sel_Base_Addr:            Integer := 16#1100#;   --BLM output mux select registers :      130 16 bit registers -->82h 
+    CONSTANT c_BLM_ctrl_Base_Addr:               Integer := 16#1200#;   --BLM control registers: 15 x 16 bit registers
+    
+
+--  +============================================================================================================================+
+--  |                                                 CONSTANT                                                                   |
+--  +============================================================================================================================+
+
+    CONSTANT c_cid_system:     integer range 0 to 16#FFFF#:= 55;     -- extension card: cid_system, CSCOHW=55
+
+    type ID_CID is record
+      ID   : std_logic_vector(7 downto 0);
+      CID  : integer range 0 to 16#FFFF#;
+    end record;
+--                                        +--------------- Piggy-ID(Hardware-coding)
+--                                        |     +--------- CID(extension card: cid_system)
+    CONSTANT c_AW_INLB12S1:   ID_CID:= (x"13", 67);   ---- Piggy-ID(coding), B"0001_0011", FG902_050        -- IO-Modul-Backplane with 12 slots
+  
+    CONSTANT c_BP_6LemoI1 :    ID_CID:= (x"03", 74);   ---- SUB-Piggy-ID(Codierung), B"0000_0011", FG902.130 -- 6xlemo In,  
+    CONSTANT c_BP_6LWLI1 :     ID_CID:= (x"04", 75);   ---- SUB-Piggy-ID(Codierung), B"0000_0100", FG902.110 -- 6x opt In,   
+    CONSTANT c_BP_6LWLO1 :     ID_CID:= (x"05", 76);   ---- SUB-Piggy-ID(Codierung), B"0000_0101", FG902.120 -- 6x opt Out,  
+    CONSTANT c_BP_6LEMO1 :     ID_CID:= (x"06", 77);   ---- SUB-Piggy-ID(Codierung), B"0000_0110", FG902.140 -- 6x opt Out,  
+    CONSTANT c_BP_6DigIn1:     ID_CID:= (x"07", 78);   ---- SUB-Piggy-ID(Codierung), B"0000_0111", FG902.150 -- 6xDIgIn1 IN,  
+
+    constant  stretch_cnt:    integer := 5;                               -- für LED's
+    constant  Clk_in_ns:      integer  :=  1000000000 /  clk_sys_in_Hz;          -- (=8ns,    @ 125MHz)
+    CONSTANT  CLK_sys_in_ps:  INTEGER  := (1000000000 / (CLK_sys_in_Hz / 1000));  --must actually be half-clk
+    constant  C_Strobe_1us:   integer := 1000 / Clk_in_ns;                       -- Number of clocks for 1us
+    constant  C_Strobe_2us:   integer := 2000 / Clk_in_ns;                       -- Number of clocks for 2us
+    constant  C_Strobe_3us:   integer := 003000 * 1000 / CLK_sys_in_ps;          -- Number of clocks for the Debounce Time of  3uS
+    constant  C_Strobe_7us:   integer := 007000 * 1000 / CLK_sys_in_ps;          -- Number of clocks for the Debounce Time of  7uS
+
+   TYPE      t_Integer_Array  is array (0 to 7) of integer range 0 to 16383;
+
+  --------------- Array für die Anzahl der Clock's für die B1dddebounce-Zeiten von 1,2,4,8,16,32,64,128 us ---------------
+
+
+  constant  Wert_2_Hoch_n:   t_Integer_Array := (001000 * 1000 / CLK_sys_in_ps,   -- Number of clocks for the Debounce Time of   1uS
+                                                 002000 * 1000 / CLK_sys_in_ps,   -- Number of clocks for the Debounce Time of   2uS
+                                                 004000 * 1000 / CLK_sys_in_ps,   -- Number of clocks for the Debounce Time of   4uS
+                                                 008000 * 1000 / CLK_sys_in_ps,   -- Number of clocks for the Debounce Time of   8uS
+                                                 016000 * 1000 / CLK_sys_in_ps,   -- Number of clocks for the Debounce Time of  16uS
+                                                 032000 * 1000 / CLK_sys_in_ps,   -- Number of clocks for the Debounce Time of  32uS
+                                                 064000 * 1000 / CLK_sys_in_ps,   -- Number of clocks for the Debounce Time of  64uS
+                                                 128000 * 1000 / CLK_sys_in_ps);  -- Number of clocks for the Debounce Time of 128uS
+
+  CONSTANT C_Strobe_100ns:  integer range 0 to 16383:= (000100 * 1000 / CLK_sys_in_ps);   -- Number of clocks for the Strobe 100ns
+
+  TYPE   t_Integer_Strobe_Array     is array (0 to 7) of integer range 0 to 65535;
+  constant Wert_Strobe_2_Hoch_n : t_Integer_Strobe_Array := (00001, 00002, 00004, 00008, 00016, 00032, 00064, 00128);
+
+  TYPE   t_status_error_update_Array     is array (0 to 7) of integer range 0 to 1023;
+--                                                                ( 2^0, 2^1, 2^2, 2^3, 2^4, 2^5, 2^6, 2^7
+--                                                                   0    2    4    8   16   32   64  128
+  constant Sts_Err_Zeit_2_Hoch_n : t_status_error_update_Array := (005, 010, 020, 040, 080, 160, 320, 640);
+
+--  +============================================================================================================================+
+--  |                                                    Component                                                               |
+--  +============================================================================================================================+
+
+component config_status
+  generic ( CS_Base_addr  : integer );
+  port (
+    Adr_from_SCUB_LA:     in   std_logic_vector(15 downto 0);    -- latched address from SCU_Bus
+    Data_from_SCUB_LA:    in   std_logic_vector(15 downto 0);    -- latched data from SCU_Bus
+    Ext_Adr_Val:          in   std_logic;                        -- '1' => "ADR_from_SCUB_LA" is valid
+    Ext_Rd_active:        in   std_logic;                        -- '1' => Rd-Cycle is active
+    Ext_Rd_fin:           in   std_logic;                        -- marks end of read cycle, active one for one clock period of sys_clk
+    Ext_Wr_active:        in   std_logic;                        -- '1' => Wr-Cycle is active
+    Ext_Wr_fin:           in   std_logic;                        -- marks end of write cycle, active one for one clock period of sys_clk
+    clk:                  in   std_logic;                        -- should be the same clk, used by SCU_Bus_Slave
+    nReset:               in   std_logic;
+    Diob_Status1:         in   std_logic_vector(15 downto 0);    -- Input-Port 1
+    Diob_Status2:         in   std_logic_vector(15 downto 0);    -- Input-Port 2
+    AW_Status1:           in   std_logic_vector(15 downto 0);    -- Input-Port 3
+    AW_Status2:           in   std_logic_vector(15 downto 0);    -- Input-Port 4
+    Diob_Config1:         out  std_logic_vector(15 downto 0);    -- Data-Reg. AWOut1
+    Diob_Config2:         out  std_logic_vector(15 downto 0);    -- Data-Reg. AWOut2
+    AW_Config1:           out  std_logic_vector(15 downto 0);    -- Data-Reg. AWOut3
+    AW_Config2:           out  std_logic_vector(15 downto 0);    -- Data-Reg. AWOut4
+    Mirr_OutReg_Maske:    out  std_logic_vector(15 downto 0);    -- Masking for mirror mode of the source register
+    Diob_Config1_wr:      out  std_logic;                        -- write-Strobe, Data-Reg. AWOut1
+    Diob_Config2_wr:      out  std_logic;                        -- write-Strobe, Data-Reg. AWOut2
+    AW_Config1_wr:        out  std_logic;                        -- write-Strobe, Data-Reg. AWOut3
+    AW_Config2_wr:        out  std_logic;                        -- write-Strobe, Data-Reg. AWOut4
+    Clr_Tag_Config:       out  std_logic;                        -- Clear Tag-Configurations-Register
+    Rd_active:            out  std_logic;                        -- read data available at 'Data_to_SCUB'-AWOut
+    Data_to_SCUB:         out  std_logic_vector(15 downto 0);    -- connect read sources to SCUB-Macro
+    Dtack_to_SCUB:        out  std_logic;                        -- connect Dtack to SCUB-Macro
+    LA:                   out  std_logic_vector(15 downto 0)
+      );
+end component config_status;
+
+
+component tag_ctrl
+  generic ( TAG_Base_addr  : integer );
+  port (
+    Adr_from_SCUB_LA:     in   std_logic_vector(15 downto 0);    -- latched address from SCU_Bus
+    Data_from_SCUB_LA:    in   std_logic_vector(15 downto 0);    -- latched data from SCU_Bus
+    Ext_Adr_Val:          in   std_logic;                        -- '1' => "ADR_from_SCUB_LA" is valid
+    Ext_Rd_active:        in   std_logic;                        -- '1' => Rd-Cycle is active
+    Ext_Rd_fin:           in   std_logic;                        -- marks end of read cycle, active one for one clock period of sys_clk
+    Ext_Wr_active:        in   std_logic;                        -- '1' => Wr-Cycle is active
+    Ext_Wr_fin:           in   std_logic;                        -- marks end of write cycle, active one for one clock period of sys_clk
+    Timing_Pattern_LA:    in   std_logic_vector(31 downto 0);    -- latched timing pattern from SCU_Bus for external user functions
+    Timing_Pattern_RCV:   in   std_logic;                        -- timing pattern received
+    Spare0:               in   std_logic;                        -- driven by Master
+    Spare1:               in   std_logic;                        -- driven by Master
+    clk:                  in   std_logic;                        -- should be the same clk, used by SCU_Bus_Slave
+    nReset:               in   std_logic;
+
+    SCU_AW_Input_Reg:     in   t_IO_Reg_1_to_7_Array;            -- Input-Port's  zum SCU-Bus
+
+    Clr_Tag_Config:       in   std_logic;                        -- clear all Tag-Masks
+    Max_AWOut_Reg_Nr:     in   integer range 0 to 7;             -- Maximum AWOut Reg number of the application
+    Max_AWIn_Reg_Nr:      in   integer range 0 to 7;             -- Maximum AWIn-Reg-Nummenumber of the application
+    Tag_matched_7_0:      out  std_logic_vector(7 downto 0);     -- Active on matched Tags for one clock period after matching, one bit for each tag unit
+
+    Tag_Maske_Reg:        out  t_IO_Reg_1_to_7_Array;            -- Tag-Output-Mask for Register 1-7
+    Tag_Outp_Reg:         out  t_IO_Reg_1_to_7_Array;            -- Tag-Output-Mask for Register 1-7
+
+    Tag_FG_Start:         out  std_logic;                        -- Start-Puls for the FG
+    Tag_Sts:              out  std_logic_vector(15 downto 0);    -- Tag-Status
+
+    Rd_active:            out  std_logic;                        -- read data available at 'Data_to_SCUB'-AWOut
+    Data_to_SCUB:         out  std_logic_vector(15 downto 0);    -- connect read sources to SCUB-Macro
+    Dtack_to_SCUB:        out  std_logic;                        -- connect Dtack to SCUB-Macro
+    Tag_Aktiv:            out  std_logic_vector( 7 downto 0);    -- Flag: Bit7 = Tag7 (active) --- Bit0 = Tag0 (active)
+    LA_tag_ctrl:          out  std_logic_vector(15 downto 0)
+    );
+end component tag_ctrl;
+
+
+COMPONENT io_reg
+  GENERIC ( Base_addr : INTEGER );
+  PORT
+  (
+    Adr_from_SCUB_LA:    IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Data_from_SCUB_LA:   IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Ext_Adr_Val:         IN  STD_LOGIC;
+    Ext_Rd_active:       IN  STD_LOGIC;
+    Ext_Rd_fin:          IN  STD_LOGIC;
+    Ext_Wr_active:       IN  STD_LOGIC;
+    Ext_Wr_fin:          IN  STD_LOGIC;
+    clk:                 IN  STD_LOGIC;
+    nReset:              IN  STD_LOGIC;
+    Reg_IO1:             OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Reg_IO2:             OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Reg_IO3:             OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Reg_IO4:             OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Reg_IO5:             OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Reg_IO6:             OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Reg_IO7:             OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Reg_IO8:             OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Reg_rd_active:       OUT STD_LOGIC;
+    Data_to_SCUB:        OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Dtack_to_SCUB:       OUT STD_LOGIC
+  );
+END COMPONENT io_reg;
+
+COMPONENT in_reg
+  GENERIC ( Base_addr : INTEGER );
+  PORT
+  (
+    Adr_from_SCUB_LA:    IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Data_from_SCUB_LA:   IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Ext_Adr_Val:         IN  STD_LOGIC;
+    Ext_Rd_active:       IN  STD_LOGIC;
+    Ext_Rd_fin:          IN  STD_LOGIC;
+    Ext_Wr_active:       IN  STD_LOGIC;
+    Ext_Wr_fin:          IN  STD_LOGIC;
+    clk:                 IN  STD_LOGIC;
+    nReset:              IN  STD_LOGIC;
+    Reg_In1:             IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Reg_In2:             IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Reg_In3:             IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Reg_In4:             IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Reg_In5:             IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Reg_In6:             IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Reg_In7:             IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Reg_In8:             IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Reg_rd_active:       OUT STD_LOGIC;
+    Data_to_SCUB:        OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    Dtack_to_SCUB:       OUT STD_LOGIC
+  );
+END COMPONENT in_reg;
+
+
+
+component zeitbasis
+generic (
+    CLK_in_Hz:      integer;
+    diag_on:      integer
+    );
+port  (
+    Res:        in  std_logic;
+    Clk:        in  std_logic;
+    Ena_every_100ns:  out std_logic;
+    Ena_every_166ns:  out std_logic;
+    Ena_every_250ns:  out std_logic;
+    Ena_every_500ns:  out std_logic;
+    Ena_every_1us:    out std_logic;
+    Ena_Every_20ms:   out std_logic
+    );
+end component zeitbasis;
+
+
+ component diob_debounce
+  generic (
+    DB_Tst_Cnt: integer := 3;
+    Test:       integer range 0 TO 1);
+  port (
+    DB_Cnt:     in  integer range 0 to 16383;
+    DB_In:      in  std_logic;
+    Reset:      in  std_logic;
+    Clk:        in  std_logic;
+    DB_Out:     out std_logic
+    );
+  end component diob_debounce;
+component deglitcher 
+  generic	(nr_stages : integer := 2   --3
+);
+port	
+(
+    clock: in std_logic;          
+  reset: in std_logic;          
+  degl_in : in std_logic;
+  degl_out: out std_logic
+);
+end component deglitcher; 
+
+component gate_deglitcher 
+  generic	(nr_stages : integer := 10   --3
+);
+port	
+(
+    clock: in std_logic;          
+  reset: in std_logic;          
+  degl_in : in std_logic;
+  degl_out: out std_logic
+);
+end component gate_deglitcher; 
+
+  COMPONENT daq 
+  generic (
+      Base_addr:          unsigned(15 downto 0);
+      CLK_sys_in_Hz:      integer := 125_000_000;               
+      ch_num:             integer := 16                      
+          );
+  
+  port  (
+        Adr_from_SCUB_LA:    in    std_logic_vector(15 downto 0);
+        Data_from_SCUB_LA:   in    std_logic_vector(15 downto 0);
+        Ext_Adr_Val:         in    std_logic;                    
+        Ext_Rd_active:       in    std_logic;                   
+        Ext_Wr_active:       in    std_logic;                   
+        clk_i:               in    std_logic;                    
+        nReset:              in    std_logic;
+  
+        diob_extension_id:   in    std_logic_vector(15 downto 0);
+  
+        user_rd_active:      out   std_logic;
+        Rd_Port:             out   std_logic_vector(15 downto 0);
+        Dtack:               out   std_logic;                    
+        daq_srq:             out   std_logic;                    
+        HiRes_srq:           out   std_logic;                    
+        Timing_Pattern_LA:   in    std_logic_vector(31 downto 0);
+        Timing_Pattern_RCV:  in    std_logic;                    
+  
+        --daq input channels
+        daq_dat_i:           in    t_daq_dat (1 to ch_num);    
+        daq_ext_trig:        in    t_daq_ctl (1 to ch_num)       
+      );
+      END COMPONENT daq;
+
+
+component Beam_Loss_check is
+  generic (
+    
+    WIDTH        : integer := 30     -- Counter width
+       
+);
+port (
+    clk_sys           : in std_logic;      -- Clock
+    rstn_sys          : in std_logic;      -- Reset
+
+   -- IN BLM 
+    BLM_data_in       : in std_logic_vector(53 downto 0);
+    BLM_gate_in       : in std_logic_vector(11 downto 0);
+    BLM_tst_ck_sig    : in std_logic_vector (10 downto 0);
+    IOBP_LED_nr       : in std_logic_vector(3 downto 0);
+    --IN registers
+    pos_threshold           : in t_BLM_th_Array; --t_BLM_th_Array is array (0 to 127) of std_logic_vector(31 downto 0);
+    neg_threshold           : in t_BLM_th_Array ;
+    BLM_wdog_hold_time_Reg  : in std_logic_vector(15 downto 0);
+    BLM_wd_reset            : in std_logic_vector(53 downto 0);
+    BLM_gate_hold_time_Reg  : in  t_BLM_gate_hold_Time_Array;
+    BLM_ctrl_Reg            : in std_logic_vector(15 downto 0); --bit 0 = counter RESET, bit 1 = counter LOAD, bit 2: when 0 the outputs of board in slot 12 are the direct outptuts of the output OR, 
+    --   when 1, the outputs in slot 12 are the values of AW_Output_Reg(6),  bit 15..3 free
+    BLM_gate_seq_prep_ck_sel_Reg : in std_logic_vector(15 downto 0);
+    BLM_gate_recover_Reg : in std_logic_vector(15 downto 0);
+  --  BLM_gate_seq_in_ena_Reg : in std_logic_vector(15 downto 0); --"00"& ena for gate board2 &"00" & ena for gate board1 
+    BLM_in_sel_Reg          : in t_BLM_reg_Array; --128 x (4 bit for gate ena & 6 bit for up signal ena & 6 for down signal ena)
+   BLM_out_sel_reg : in t_BLM_out_sel_reg_Array;    -- 122 x 16 bits = Reg120-0:  "0000" and 6 x (54 watchdog errors  + 12 gate errors + 256 counters overflows outputs) 
+                                                    -- + 4 more registers for 6 x 12 input gate (= 72 bits) to be send to the outputs.    
+                                                    --=> 126 registers             
+                                                    --   REg127             ex Reg121: counter outputs buffering enable (bit 15) and buffered output select (bit 7-0). Bits 14-8 not used     
+    -- OUT register
+   -- BLM_status_Reg    : out t_IO_Reg_0_to_25_Array ;
+   BLM_status_Reg    : out t_IO_Reg_0_to_29_Array ;
+
+      -- OUT BLM
+      BLM_Out           : out std_logic_vector(5 downto 0) 
+);
+
+  end component Beam_Loss_check;
+ 
+
+component front_board_id is 
+
+  Port 
+      ( clk : in STD_LOGIC;
+       nReset : in STD_LOGIC;
+       Deb_Sync : in STD_LOGIC_VECTOR(65 downto 0);
+       Deb_out   :in STD_LOGIC_VECTOR(65 downto 0);
+
+       IOBP_Masken_Reg1 : in STD_LOGIC_VECTOR(15 downto 0);
+       IOBP_Masken_Reg2 : in STD_LOGIC_VECTOR(15 downto 0);
+       IOBP_Masken_Reg3 : in STD_LOGIC_VECTOR(15 downto 0);
+       IOBP_Masken_Reg4 : in STD_LOGIC_VECTOR(15 downto 0);
+       IOBP_Masken_Reg5 : in STD_LOGIC_VECTOR(15 downto 0);
+       IOBP_Masken_Reg6 : in STD_LOGIC_VECTOR(15 downto 0);
+       PIO_SYNC         : in STD_LOGIC_VECTOR(142 DOWNTO 20);
+       IOBP_ID          : in t_id_array;
+       INTL_Output      : in std_logic_vector(5 downto 0);
+       AW_Output_Reg    : in std_logic_vector(5 downto 0);
+      -- nBLM_out_ena      : in std_logic;
+       AW_IOBP_Input_Reg     : out t_IO_Reg_1_to_7_Array;
+       IOBP_Output     : out std_logic_vector (5 downto 0);     
+       IOBP_Input     : out t_IOBP_array;
+       IOBP_Aktiv_LED_i   : out t_led_array;
+       OUT_SLOT         : out std_logic_vector(5 downto 0);
+       ENA_SLOT         : out std_logic_vector(5 downto 0);
+       IOBP_Sel_LED     : out t_led_array
+);
+end component front_board_id;
+
+component IOBP_LED_ID_Module 
+
+port (
+        clk_sys           : in  std_logic;      
+        rstn_sys          : in  std_logic;      
+        --Ena_Every_250ns   : in  std_logic; 
+        Ena_Every_500ns   : in std_logic;
+        AW_ID             : in  std_logic_vector(7 downto 0); -- Application_ID
+        IOBP_LED_ID_Bus_i : in  std_logic_vector(7 downto 0);   -- LED_ID_Bus_In
+        IOBP_Aktiv_LED_o  : in  t_led_array;    -- Active LEDs of the "Slave-Boards"
+        IOBP_Sel_LED      : in  t_led_array;    -- Sel-LED of the "Slave-Boards"
+        IOBP_LED_En       : out std_logic; -- Output-Enable for LED -ID-Bus
+        IOBP_STR_rot_o    : out std_logic_vector(12 downto 1);  -- LED-Str Red  for Slave 12-1
+        IOBP_STR_gruen_o  : out std_logic_vector(12 downto 1);  -- LED-Str Green for Slave 12-1
+        IOBP_STR_ID_o     : out std_logic_vector(12 downto 1);  -- ID-Str Green for Slave 12-1
+        IOBP_LED_ID_Bus_o : out std_logic_vector(7 downto 0);   -- LED_ID_Bus_Out
+        IOBP_ID           : out t_id_array ;    -- IDs of the "Slave-Boards"
+        IOBP_LED_state_nr : out std_logic_vector(3 downto 0)
+        
+        );
+ end component IOBP_LED_ID_Module;
+
+ component p_connector
+
+  port(
+    Powerup_Done		  : in std_logic;
+  signal_tap_clk_250mhz  : in std_logic;
+  A_SEL                  : in std_logic_vector(3 downto 0);
+  PIO_SYNC		           : in STD_LOGIC_VECTOR(150 DOWNTO 16); 
+  CLK_IO                 : in std_logic;                      -- Clock for user_I/0
+  DIOB_Config1           : in std_logic_vector(15 downto 0);
+  AW_Output_Reg          : in t_IO_Reg_1_to_7_Array;          -- Output-Register to the Piggys
+  UIO_SYNC		           : in STD_LOGIC_VECTOR(15 DOWNTO 0); 
+  hp_la_o                : in std_logic_vector(15 downto 0);
+  local_clk_is_running   : in std_logic; 
+  clk_blink              : in std_logic;
+  s_nLED_Sel             : in std_logic;   -- LED = Sel
+  s_nLED_Dtack           : in std_logic;   -- LED = Dtack
+  s_nLED_inR             : in std_logic;   -- LED = interrupt
+  s_nLED_User1_o         : in std_logic;   -- LED3 = User 1
+  s_nLED_User2_o         : in  std_logic;  -- LED2 = User 2
+  s_nLED_User3_o         : in std_logic;   -- LED1 = User 3
+  Tag_Sts                : in std_logic_vector(15 downto 0);  -- Tag-Status
+  Timing_Pattern_LA      : in std_logic_vector(31 downto 0);  --  latched timing pattern from SCU_Bus for external user functions
+  Tag_Aktiv              : in std_logic_vector( 7 downto 0);  -- Flag: Bit7 = Tag7 (active) --- Bit0 = Tag0 (active)       
+  IOBP_LED_ID_Bus_o      : in std_logic_vector(7 downto 0);   -- LED_ID_Bus_Out
+  IOBP_ID                : in t_id_array;                     -- IDs of the "Slave-Boards"
+  IOBP_LED_En            : in std_logic;                      -- Output-Enable für LED- ID-Bus 
+  IOBP_STR_rot_o         : in std_logic_vector(12 downto 1);  -- LED-Str Red for Slave 12-1
+  IOBP_STR_gruen_o       : in std_logic_vector(12 downto 1);  -- LED-Str Green for Slave 12-1
+  IOBP_STR_ID_o          : in std_logic_vector(12 downto 1);  -- ID-Str Green for Slave 12-1
+  IOBP_Output            : in std_logic_vector(5 downto 0);   -- Outputs "Slave-Boards 1-12" 
+  IOBP_Input             : in t_IOBP_array;                   -- Inputs "Slave-Boards 1-12"
+  Deb66_out              : in std_logic_vector(65 downto 0);
+  AW_IOBP_Input_Reg      : in t_IO_Reg_1_to_7_Array;  -- Input-Register of the Piggy's
+  PIO_ENA_SLOT_1         : in std_logic_vector(5 downto 0);
+  PIO_ENA_SLOT_2         : in std_logic_vector(5 downto 0);
+  PIO_ENA_SLOT_3         : in std_logic_vector(5 downto 0);
+  PIO_ENA_SLOT_4         : in std_logic_vector(5 downto 0);
+  PIO_ENA_SLOT_5         : in std_logic_vector(5 downto 0);
+  PIO_ENA_SLOT_6         : in std_logic_vector(5 downto 0);
+  PIO_ENA_SLOT_7         : in std_logic_vector(5 downto 0);
+  PIO_ENA_SLOT_8         : in std_logic_vector(5 downto 0);
+  PIO_ENA_SLOT_9         : in std_logic_vector(5 downto 0);
+  PIO_ENA_SLOT_10         : in std_logic_vector(5 downto 0);
+  PIO_ENA_SLOT_11         : in std_logic_vector(5 downto 0);
+  PIO_ENA_SLOT_12         : in std_logic_vector(5 downto 0);
+  PIO_OUT_SLOT_1         : in std_logic_vector(5 downto 0);
+  PIO_OUT_SLOT_3          : in std_logic_vector(5 downto 0);
+  PIO_OUT_SLOT_2          : in std_logic_vector(5 downto 0);
+  PIO_OUT_SLOT_4         : in std_logic_vector(5 downto 0);
+  PIO_OUT_SLOT_5       : in std_logic_vector(5 downto 0);
+  PIO_OUT_SLOT_6        : in std_logic_vector(5 downto 0);
+  PIO_OUT_SLOT_7       : in std_logic_vector(5 downto 0);
+  PIO_OUT_SLOT_8        : in std_logic_vector(5 downto 0);
+  PIO_OUT_SLOT_9      : in std_logic_vector(5 downto 0);
+  PIO_OUT_SLOT_10        : in std_logic_vector(5 downto 0);
+  PIO_OUT_SLOT_11       : in std_logic_vector(5 downto 0);
+  PIO_OUT_SLOT_12       : in std_logic_vector(5 downto 0);
+
+  --------------------------------------------------------------------------------------
+  A_TA                   : out std_logic_vector(15 downto 0); -- test port a
+  IOBP_LED_ID_Bus_i      : out  std_logic_vector(7 downto 0); 
+  PIO_OUT                : out   STD_LOGIC_VECTOR(150 DOWNTO 16); 
+  PIO_ENA                : out   STD_LOGIC_VECTOR(150 DOWNTO 16);   
+  UIO_OUT                : out   STD_LOGIC_VECTOR(15 DOWNTO 0);
+  UIO_ENA                : out   STD_LOGIC_VECTOR(15 DOWNTO 0);
+  AW_ID                  : out   std_logic_vector(7 downto 0);
+  AWIn_Deb_Time          : out   integer range 0 to 7;           -- Debounce-Time 2 High "AWIn_Deb_Time", value from DIOB-Config 1
+  Min_AWIn_Deb_Time      : out   integer range 0 to 7;           -- Minimal Debounce-Time 2 High"Min_AWIn_Deb_Time" 
+  Diob_Status1           : out   std_logic_vector(15 downto 0);
+  DIOB_Status2           : out   std_logic_vector(15 downto 0);
+  IOBP_Id_Reg1           : out std_logic_vector(15 downto 0);
+  IOBP_Id_Reg2           : out  std_logic_vector(15 downto 0);
+  IOBP_Id_Reg3           : out std_logic_vector(15 downto 0);
+  IOBP_Id_Reg4           : out  std_logic_vector(15 downto 0);
+  IOBP_Id_Reg5           : out  std_logic_vector(15 downto 0);
+  IOBP_Id_Reg6           : out    std_logic_vector(15 downto 0);
+  IOBP_Id_Reg7           : out   std_logic_vector(15 downto 0);
+  IOBP_Id_Reg8           : out    std_logic_vector(15 downto 0);
+  Deb66_in               : out     std_logic_vector(65 downto 0);
+  Syn66                  : out        std_logic_vector(65 downto 0);
+  AW_Input_Reg           : out   t_IO_Reg_1_to_8_Array;
+  A_Tclk                 : out std_logic;
+  extension_cid_group    : out  integer range 0 to 16#FFFF#;
+  extension_cid_system   : out integer range 0 to 16#FFFF#;
+  Max_AWOut_Reg_Nr       : out integer range 0 to 7;
+  Max_AWIn_Reg_Nr        : out  integer range 0 to 7;
+  Debounce_cnt           : out  integer range 0 to 16383;
+  s_nLED_User1_i         : out std_logic;  -- LED3 = User 1
+  s_nLED_User2_i         : out std_logic;  -- LED2 = User 2
+  s_nLED_User3_i         : out std_logic;
+  --IOBP_Output_Readback   : out t_IO_Reg_0_to_7_Array;
+  --IOBP_Output_Readback   : out std_logic_vector(15 downto 0);
+  Deb_Sync66             : out std_logic_vector(65 downto 0);
+  daq_dat                : out t_daq_dat;
+  daq_diob_ID            : out std_logic_vector(15 downto 0)
+  
+  
+    );
+    end component p_connector;
+
+    component blm_24_9_9_9pll
+    PORT
+    (
+      areset		: IN STD_LOGIC  := '0';
+      inclk0		: IN STD_LOGIC  := '0';
+      c0		: OUT STD_LOGIC ;
+      c1		: OUT STD_LOGIC 
+    );
+    end component blm_24_9_9_9pll;
+    
+
+
+component aw_io_reg
+  generic ( AW_Base_addr:   integer;
+            CLK_sys_in_Hz:  integer);
+  port (
+        Adr_from_SCUB_LA:     in   std_logic_vector(15 downto 0);    -- latched address from SCU_Bus
+        Data_from_SCUB_LA:    in   std_logic_vector(15 downto 0);    -- latched data from SCU_Bus
+        Ext_Adr_Val:          in   std_logic;                        -- '1' => "ADR_from_SCUB_LA" is valid
+        Ext_Rd_active:        in   std_logic;                        -- '1' => Rd-Cycle is active
+        Ext_Rd_fin:           in   std_logic;                        -- marks end of read cycle, active one for one clock period of sys_clk
+        Ext_Wr_active:        in   std_logic;                        -- '1' => Wr-Cycle is active
+        Ext_Wr_fin:           in   std_logic;                        -- marks end of write cycle, active one for one clock period of sys_clk
+        clk:                  in   std_logic;                        -- should be the same clk, used by SCU_Bus_Slave
+        Ena_every_1us:        in   std_logic;                        -- Clock-Enable-Puls alle Mikrosekunde, 1 Clock breit
+        nReset:               in   std_logic;
+
+        SCU_AW_Input_Reg:     in   t_IO_Reg_1_to_7_Array;            -- Input-Port's  zum SCU-Bus
+        SCU_AW_Output_Reg:    out  t_IO_Reg_1_to_7_Array;            -- Output-Port's vom SCU-Bus
+
+        AWOut_Reg1_wr:        out  std_logic;                        -- Daten-Reg. AWOut1
+        AWOut_Reg2_wr:        out  std_logic;                        -- Daten-Reg. AWOut2
+        AWOut_Reg3_wr:        out  std_logic;                        -- Daten-Reg. AWOut3
+        AWOut_Reg4_wr:        out  std_logic;                        -- Daten-Reg. AWOut4
+        AWOut_Reg5_wr:        out  std_logic;                        -- Daten-Reg. AWOut5
+        AWOut_Reg6_wr:        out  std_logic;                        -- Daten-Reg. AWOut6
+        AWOut_Reg7_wr:        out  std_logic;                        -- Daten-Reg. AWOut7
+
+        Rd_active:            out  std_logic;                        -- read data available at 'Data_to_SCUB'-AWOut
+        Data_to_SCUB:         out  std_logic_vector(15 downto 0);    -- connect read sources to SCUB-Macro
+        Dtack_to_SCUB:        out  std_logic;                        -- connect Dtack to SCUB-Macro
+        LA:                   out  std_logic_vector(15 downto 0)
+      );
+end component aw_io_reg;
+
+
+--  +============================================================================================================================+
+--  |                                                         signal                                                             |
+--  +============================================================================================================================+
+
+  signal clk_sys, clk_cal, locked : std_logic;
+  signal Debounce_cnt:              integer range 0 to 16383;   -- Clock's for the Debouncing Time
+
+  --  signal clk:                       std_logic := '0';
+
+  signal SCUB_SRQ:            std_logic;
+  signal SCUB_Dtack:          std_logic;
+  signal convst:              std_logic;
+  signal rst:                 std_logic;
+
+  signal Dtack_to_SCUB:       std_logic;
+
+  signal ADR_from_SCUB_LA:    std_logic_vector(15 downto 0);
+  signal Data_from_SCUB_LA:   std_logic_vector(15 downto 0);
+  signal Ext_Adr_Val:         std_logic;
+  signal Ext_Rd_active:       std_logic;
+  signal Ext_Wr_active:       std_logic;
+  signal Ext_Wr_fin_ovl:      std_logic;
+  signal Ext_RD_fin_ovl:      std_logic;
+  signal SCU_Ext_Wr_fin:      std_logic;
+  signal nPowerup_Res:        std_logic;
+  signal Timing_Pattern_LA:   std_logic_vector(31 downto 0);--  latched timing pattern from SCU_Bus for external user functions
+  signal Timing_Pattern_RCV:  std_logic;----------------------  timing pattern received
+
+  signal extension_cid_system:  integer range 0 to 16#FFFF#;  -- in,  extension card: cid_system
+  signal extension_cid_group:   integer range 0 to 16#FFFF#;  --in, extension card: cid_group
+
+  signal Max_AWOut_Reg_Nr:      integer range 0 to 7;           -- Maximal AWOut-Reg-Number of the application
+  signal Max_AWIn_Reg_Nr:       integer range 0 to 7;           -- Maximale AWIn-Reg-Number of the application
+
+  signal AWIn_Deb_Time:          integer range 0 to 7:= 0;           -- Debounce-Time 2 High "AWIn_Deb_Time", value from DIOB-Config 1
+  signal Min_AWIn_Deb_Time:      integer range 0 to 7:= 0;           -- Minimal Debounce-Time 2 High"Min_AWIn_Deb_Time"
+
+  signal tmr_rd_active:      std_logic;
+  signal tmr_data_to_SCUB:   std_logic_vector(15 downto 0);
+  signal tmr_dtack:          std_logic;
+  signal tmr_irq:            std_logic;
+
+  signal led_ena_cnt:        std_logic;
+
+  signal Data_to_SCUB:       std_logic_vector(15 downto 0);
+
+  signal reset_clks :        std_logic_vector(0 downto 0);
+  signal reset_rstn :        std_logic_vector(0 downto 0);
+  signal clk_sys_rstn :      std_logic;
+
+  signal owr_pwren_o:        std_logic_vector(1 downto 0);
+  signal owr_en_o:           std_logic_vector(1 downto 0);
+  signal owr_i:              std_logic_vector(1 downto 0);
+
+  signal wb_scu_rd_active:    std_logic;
+  signal wb_scu_dtack:        std_logic;
+  signal wb_scu_data_to_SCUB: std_logic_vector(15 downto 0);
+
+
+  signal Powerup_Res:     std_logic;  -- only for modelsim!
+  signal Powerup_Done:    std_logic;  -- this memory is set to one if an Powerup is done. Only the SCUB-Master can clear this bit.
+  signal WRnRD:           std_logic;  -- only for modelsim!
+
+  signal Deb_SCUB_Reset_out:  std_logic;
+  signal Standard_Reg_Acc:    std_logic;
+  signal Ext_Rd_fin:          std_logic;
+
+
+  signal test_out: std_logic_vector(15 downto 0);
+
+  signal Ena_Every_100ns: std_logic;
+  signal Ena_Every_166ns: std_logic;
+  signal Ena_Every_250ns: std_logic;
+  signal Ena_Every_500ns: std_logic;
+  signal Ena_Every_10ms:  std_logic;
+  signal Ena_Every_20ms:  std_logic;
+  signal Ena_Every_1us:   std_logic;
+  signal Ena_Every_250ms: std_logic;
+  signal Ena_Every_500ms: std_logic;
+
+  signal F_12p5_MHz:      std_logic;
+
+  signal test_port_in_0:  std_logic_vector(15 downto 0);
+  signal test_clocks:     std_logic_vector(15 downto 0);
+
+  signal s_nLED_Sel:      std_logic;   -- LED = Sel
+  signal s_nLED_Dtack:    std_logic;   -- LED = Dtack
+  signal s_nLED_inR:      std_logic;   -- LED = interrupt
+
+  signal s_nLED:          std_logic_vector(7 downto 0); -- LED's
+  signal AW_ID:           std_logic_vector(7 downto 0):=x"FF"; -- Application_ID
+
+
+--------------------------- Conf_Sts1 ----------------------------------------------------------------------
+
+  signal DIOB_Config1:           std_logic_vector(15 downto 0);
+  signal DIOB_Config2:           std_logic_vector(15 downto 0);
+  signal DIOB_Status1:           std_logic_vector(15 downto 0);
+  signal DIOB_Status2:           std_logic_vector(15 downto 0);
+  signal AW_Config1:             std_logic_vector(15 downto 0);
+  signal AW_Config2:             std_logic_vector(15 downto 0);
+  signal AW_Status1:             std_logic_vector(15 downto 0);
+  signal AW_Status2:             std_logic_vector(15 downto 0);
+
+  signal Diob_Config1_wr:        std_logic;                        -- write-Strobe, Data-Reg. Diob_Config1
+  signal Diob_Config2_wr:        std_logic;                        -- write-Strobe, Data-Reg. Diob_Config2
+  signal AW_Config1_wr:          std_logic;                        -- write-Strobe, Data-Reg. AW_Config1
+  signal AW_Config2_wr:          std_logic;                        -- write-Strobe, Data-Reg. AW_Config2
+  signal Clr_Tag_Config:         std_logic;                        -- clear alle Tag-Mask
+  signal Conf_Sts1_rd_active:    std_logic;
+  signal Conf_Sts1_Dtack:        std_logic;
+  signal Conf_Sts1_data_to_SCUB: std_logic_vector(15 downto 0);
+  signal LA_Conf_Sts1:           std_logic_vector(15 downto 0);
+
+
+--------------------------- AWIn ----------------------------------------------------------------------
+
+  signal SCU_AW_Input_Reg:        t_IO_Reg_1_to_7_Array;  -- Input-Register to SCU-Bus
+  signal AW_Input_Reg:            t_IO_Reg_1_to_8_Array;  -- Input-Register of the Piggys
+
+
+
+--------------------------- AWOut ----------------------------------------------------------------------
+
+  signal SCU_AW_Output_Reg:         t_IO_Reg_1_to_7_Array;  -- Output-Register from SCU-Bus
+  signal AW_Output_Reg:             t_IO_Reg_1_to_7_Array;  -- Output-Register to the Piggys
+
+  signal AWOut_Reg1_Wr:         std_logic;
+  signal AWOut_Reg2_Wr:         std_logic;
+  signal AWOut_Reg3_Wr:         std_logic;
+  signal AWOut_Reg4_Wr:         std_logic;
+  signal AWOut_Reg5_Wr:         std_logic;
+  signal AWOut_Reg6_Wr:         std_logic;
+  signal AWOut_Reg7_Wr:         std_logic;
+
+  signal AW_Port1_rd_active:    std_logic;
+  signal AW_Port1_Dtack:        std_logic;
+  signal AW_Port1_data_to_SCUB: std_logic_vector(15 downto 0);
+  signal Tag_Reg_Conf_Err:      std_logic;
+  signal LA_AW_Port1:           std_logic_vector(15 downto 0);
+
+--------------------------- Ctrl1 ----------------------------------------------------------------------
+
+  signal Tag_Maske_Reg:          t_IO_Reg_1_to_7_Array;           -- Tag-Output-Mask for Register 1-7
+  signal Tag_Outp_Reg:           t_IO_Reg_1_to_7_Array;           -- Tag-Output-Mask for Register 1-7
+  signal Tag_Sts:                std_logic_vector(15 downto 0);   -- Tag-Status
+  signal Tag_Ctrl1_rd_active:    std_logic;                       -- read data available at 'Data_to_SCUB'-Tag_Ctrl1
+  signal Tag_Ctrl1_Dtack:        std_logic;                       -- connect read sources to SCUB-Macro
+  signal Tag_Ctrl1_data_to_SCUB: std_logic_vector(15 downto 0);   -- connect Dtack to SCUB-Macro
+  signal Tag_Aktiv:              std_logic_vector( 7 downto 0);   -- Flag: Bit7 = Tag7 (aktiv) --- Bit0 = Tag0 (aktiv)
+  signal LA_Tag_Ctrl1:           std_logic_vector(15 downto 0);
+  signal  Tag_matched_7_0:              STD_LOGIC_VECTOR(7 DOWNTO 0);
+  signal hp_la_o:      std_logic_vector(15 downto 0); -- Output für HP-Logicanalysator
+
+  signal s_nLED_User1_i: std_logic;  -- LED3 = User 1
+  signal s_nLED_User2_i: std_logic;  -- LED2 = User 2
+  signal s_nLED_User3_i: std_logic;  -- LED1 = User 3
+  signal s_nLED_User1_o: std_logic;  -- LED3 = User 1
+  signal s_nLED_User2_o: std_logic;  -- LED2 = User 2
+  signal s_nLED_User3_o: std_logic;  -- LED1 = User 3
+
+  signal uart_txd_out:  std_logic;
+
+
+    ------------ Mirror-Mode-Signale --------------------------------------------------------------------------------------
+
+  signal AWIn_Reg_Array:        t_IO_Reg_1_to_7_Array;          -- Copy of AWIn-Register in an Array
+
+  signal Mirr_OutReg_Maske:     std_logic_vector(15 downto 0);  -- Masking for Mirror-Modus of the output registers
+  signal Mirr_AWOut_Reg_Nr:     integer range 0 to 7;           -- AWOut-Reg-Number
+
+  signal Mirr_AWIn_Reg_Nr:      integer range 0 to 7;           -- AWIn-Reg-Number
+
+  ------------ I/O Front Boards Signals--------------------------------------------------------------------------------------
+
+  signal IOBP_Masken_Reg1:        std_logic_vector(15 downto 0);
+  signal IOBP_Masken_Reg2:        std_logic_vector(15 downto 0);
+  signal IOBP_Masken_Reg3:        std_logic_vector(15 downto 0);
+  signal IOBP_Masken_Reg4:        std_logic_vector(15 downto 0);
+  signal IOBP_Masken_Reg5:        std_logic_vector(15 downto 0);
+  signal IOBP_Masken_Reg6:        std_logic_vector(15 downto 0);
+  signal IOBP_Masken_Reg7:        std_logic_vector(15 downto 0);
+  signal IOBP_Masken_Reg8:        std_logic_vector(15 downto 0);
+  signal IOBP_msk_rd_active:      std_logic;
+  signal IOBP_msk_Dtack:          std_logic;
+  signal IOBP_msk_data_to_SCUB:   std_logic_vector(15 downto 0);
+ --signal BLM_Status_Reg:    t_IO_Reg_0_to_25_Array ;
+ signal BLM_Status_Reg:    t_IO_Reg_0_to_29_Array ;
+
+signal IOBP_Output: std_logic_vector(5 downto 0);     -- Outputs "Slave-Karten 1-12"  --but I use only 1-2-3 respectiverly for slot 10-11-12
+
+signal IOBP_Input:  t_IOBP_array;    -- Inputs "Slave-Karten 1-12"
+  signal IOBP_Id_Reg1:            std_logic_vector(15 downto 0) := (OTHERS => '0');
+  signal IOBP_Id_Reg2:            std_logic_vector(15 downto 0) := (OTHERS => '0');
+  signal IOBP_Id_Reg3:            std_logic_vector(15 downto 0) := (OTHERS => '0');
+  signal IOBP_Id_Reg4:            std_logic_vector(15 downto 0) := (OTHERS => '0');
+  signal IOBP_Id_Reg5:            std_logic_vector(15 downto 0) := (OTHERS => '0');
+  signal IOBP_Id_Reg6:            std_logic_vector(15 downto 0) := (OTHERS => '0');
+  signal IOBP_Id_Reg7:            std_logic_vector(15 downto 0) := (OTHERS => '0');
+  signal IOBP_Id_Reg8:            std_logic_vector(15 downto 0) := (OTHERS => '0');
+  signal IOBP_id_rd_active:       std_logic;
+  signal IOBP_id_Dtack:           std_logic;
+  signal IOBP_id_data_to_SCUB:    std_logic_vector(15 downto 0);
+  signal IOBP_in_data_to_SCUB:    t_IO_Reg_0_to_3_Array;
+  signal IOBP_in_rd_active:       std_logic_vector(3 downto 0);
+  signal IOBP_in_Dtack:            std_logic_vector(3 downto 0);
+  signal IOBP_in_res_Dtack: std_logic;
+  signal IOBP_Sel_LED:      t_led_array;    -- Sel-LED's der "Slave-Karten"
+  signal IOBP_ID:           t_id_array;     -- IDs of the "Slave-Boards"
+  signal IOBP_Aktiv_LED_i:  t_led_array;    -- Aktiv-LED's der "Slave-Karten"
+  signal IOBP_Aktiv_LED_o:  t_led_array;    -- Aktiv-LED's der "Slave-Karten"
+
+  signal Syn66:        std_logic_vector(65 downto 0):= (OTHERS => '0');
+ 
+  
+signal Deg_Sync66:   std_logic_vector(65 downto 0);
+  signal  Deb66_out:    std_logic_vector(65 downto 0);
+signal  Deg66_in:     std_logic_vector(65 downto 0):= (OTHERS => '0');
+signal  Deg66_out:    std_logic_vector(65 downto 0);
+
+signal IOBP_STR_rot_o:    std_logic_vector(12 downto 1);  -- LED-Str Rot  für Slave 12-1
+signal IOBP_STR_gruen_o:  std_logic_vector(12 downto 1);  -- LED-Str Grün für Slave 12-1
+signal IOBP_STR_ID_o:     std_logic_vector(12 downto 1);  -- ID-Str Grün für Slave 12-1
+signal IOBP_LED_ID_Bus_o: std_logic_vector(7 downto 0);   -- LED_ID_Bus_Out
+signal IOBP_LED_ID_Bus_i: std_logic_vector(7 downto 0) :=    (OTHERS => '1');     -- Data_Output "Slave-Karte 1-12";   -- LED_ID_Bus_In
+signal IOBP_LED_En:       std_logic;                      -- Output-Enable für LED- ID-Bus
+signal Slave_Loop_cnt:      integer range 0 to 12;         -- 1-12   -- Loop-Counter
+
+signal AW_IOBP_Input_Reg:  t_IO_Reg_1_to_7_Array;  -- Input-Register of the Piggy's
+signal PIO_ENA_SLOT_1: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_ENA_SLOT_2: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_ENA_SLOT_3: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_ENA_SLOT_4: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_ENA_SLOT_5: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_ENA_SLOT_6: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_ENA_SLOT_7: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_ENA_SLOT_8: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_ENA_SLOT_9: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_ENA_SLOT_10: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_ENA_SLOT_11: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_ENA_SLOT_12: std_logic_vector(5 downto 0):= (OTHERS => '0');
+
+signal PIO_OUT_SLOT_1: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_OUT_SLOT_2: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_OUT_SLOT_3: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_OUT_SLOT_4: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_OUT_SLOT_5: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_OUT_SLOT_6: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_OUT_SLOT_7: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_OUT_SLOT_8: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_OUT_SLOT_9: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_OUT_SLOT_10: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_OUT_SLOT_11: std_logic_vector(5 downto 0):= (OTHERS => '0');
+signal PIO_OUT_SLOT_12: std_logic_vector(5 downto 0):= (OTHERS => '0');
+
+--------------------------------------------------------------------------------------
+
+  signal clk_blink: std_logic;
+
+  signal sys_clk_is_bad:          std_logic;
+  signal sys_clk_is_bad_led_n:    std_logic;
+  signal sys_clk_is_bad_la:       std_logic;
+  signal local_clk_is_bad:        std_logic;
+  signal local_clk_is_running:    std_logic;
+  signal local_clk_runs_led_n:    std_logic;
+  signal sys_clk_failed:          std_logic;
+  signal sys_clk_deviation:       std_logic;
+  signal sys_clk_deviation_la:    std_logic;
+  signal sys_clk_deviation_led_n: std_logic;
+  signal clk_switch_rd_data:      std_logic_vector(15 downto 0);
+  signal clk_switch_rd_active:    std_logic;
+  signal clk_switch_dtack:        std_logic;
+  signal pll_locked:              std_logic;
+  signal clk_switch_intr:         std_logic;
+
+  signal  signal_tap_clk_250mhz:  std_logic;
+  signal  clk_update:             std_logic;
+  signal  clk_flash:              std_logic;
+
+  signal  rstn_sys:               std_logic;
+  signal  rstn_update:            std_logic;
+  signal  rstn_flash:             std_logic;
+  signal  rstn_stc:               std_logic;
+
+  constant c_is_arria5: boolean := false;
+
+
+--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+  signal  PIO_SYNC:              STD_LOGIC_VECTOR(150 DOWNTO 16);  --  %%%%%  I/O-Synch und TriState-Steuerung   %%%%%
+  signal  PIO_SYNC1:             STD_LOGIC_VECTOR(150 DOWNTO 16);  --  %%%%%  I/O-Synch und TriState-Steuerung   %%%%%
+  signal  PIO_ENA:               STD_LOGIC_VECTOR(150 DOWNTO 16);  --  %%%%%  I/O-Synch und TriState-Steuerung   %%%%%
+  signal  PIO_ENA_SYNC:          STD_LOGIC_VECTOR(150 DOWNTO 16):=(OTHERS => '0'); --  %%%%%  I/O-Synch und TriState-Steuerung   %%%%%
+  signal  PIO_OUT:               STD_LOGIC_VECTOR(150 DOWNTO 16):=(OTHERS => '0'); --  %%%%%  I/O-Synch und TriState-Steuerung   %%%%%
+  signal  PIO_OUT_SYNC:          STD_LOGIC_VECTOR(150 DOWNTO 16);  --  %%%%%  I/O-Synch und TriState-Steuerung   %%%%%
+
+  signal  UIO_SYNC:              STD_LOGIC_VECTOR(15 DOWNTO 0);    --  %%%%%  I/O-Synch und TriState-Steuerung   %%%%%
+  signal  UIO_SYNC1:             STD_LOGIC_VECTOR(15 DOWNTO 0);    --  %%%%%  I/O-Synch und TriState-Steuerung   %%%%%
+  signal  UIO_ENA:               STD_LOGIC_VECTOR(15 DOWNTO 0):=(OTHERS => '0');     --  %%%%%  I/O-Synch und TriState-Steuerung   %%%%%
+  signal  UIO_ENA_SYNC:          STD_LOGIC_VECTOR(15 DOWNTO 0);    --  %%%%%  I/O-Synch und TriState-Steuerung   %%%%%
+  signal  UIO_OUT:               STD_LOGIC_VECTOR(15 DOWNTO 0):=(OTHERS => '0');    --  %%%%%  I/O-Synch und TriState-Steuerung   %%%%%
+  signal  UIO_OUT_SYNC:          STD_LOGIC_VECTOR(15 DOWNTO 0);    --  %%%%%  I/O-Synch und TriState-Steuerung   %%%%%
+--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
+
+
+------
+-- signal for test_signals and for gate_seq_clk signals:
+signal blm_clk_25MHz, blm_clk_24_9MHz, blm_clk_100MHz,blm_clk_10MHz,blm_clk_1MHz,blm_clk_100kHz,blm_clk_10kHz,blm_clk_1kHz,blm_clk_9_9MHz,blm_clk_0_99MHz,blm_clk_99kHz,blm_clk_9_9kHz ,blm_clk_0_99kHz : std_logic;
+---
+signal BLM_tst_ck_sig: std_logic_vector (10 downto 0);
+
+signal BLM_data_in: std_logic_vector(53 downto 0);
+signal INTL_Output: std_logic_vector(5 downto 0);     -- Output "Slave-Karten 12"  
+signal BLM_gate_in : std_logic_vector(11 downto 0);
+signal BLM_Out :  std_logic_vector(5 downto 0);
+signal BLM_deglitcher_data: std_logic_vector(65 downto 0);
+signal BLM_deg_gate_in: std_logic_vector(11 downto 0);
+-----------------DAQ-Signale---------------------------------------------------------------------------------------------------
+
+constant daq_ch_num: integer := 16;
+signal daq_diob_ID: std_logic_vector(15 downto 0):=x"00FF"; --hard-coded ID Value for DAQ Diob implementation of which bits 3-0 are used 
+
+signal daq_user_rd_active:    std_logic;
+signal daq_data_to_SCUB:           std_logic_vector(15 downto 0);-- Data to SCU Bus Macro
+signal daq_Dtack:             std_logic;                    -- Dtack to SCU Bus Macro
+signal daq_srq:               std_logic;                    -- consolidated irq lines from n daq channels for "channel fifo full"
+signal daq_HiRes_srq:         std_logic;                    -- consolidated irq lines from n HiRes channels for "HiRes Daq finished"
+--daq input channels signals
+signal daq_dat:             t_daq_dat (1 to daq_ch_num) := (others => dummy_daq_dat_in);
+signal daq_ext_trig:          t_daq_ctl (1 to daq_ch_num) := (others => dummy_daq_ctl_in);
+
+--------------------------------------------------------------------------------------------------------------------------------------
+--for thresholds
+
+signal pos_thres_Reg:       t_BLM_th_Array; --128x 2 x 16 bit pos threshold
+signal neg_thres_Reg:       t_BLM_th_Array; --128x 2 x 16 bit neg threshold
+signal BLM_th_active:       std_logic_vector(63 downto 0);
+signal BLM_th_Dtack:        std_logic_vector(63 downto 0);
+signal BLM_th_data_to_SCUB: t_BLM_data_Array; 
+signal BLM_th_res_Dtack: std_logic;
+-------------------------------------------------
+-----for BLM in_sel and gate mux enables
+signal BLM_in_sel_Reg :             t_BLM_reg_Array; --128 x (4 bit for gate ena & 6 bit for up signal ena & 6 for down signal ena)
+signal BLM_in_sel_rd_active :      std_logic_vector(15 downto 0);
+signal BLM_in_sel_Dtack :       std_logic_vector(15 downto 0);
+signal BLM_in_sel_data_to_SCUB: t_BLM_in_sel_Array;
+signal BLM_in_sel_res_Dtack     : std_logic;
+----------------------------------------------------------------
+
+----------------------------------------------------------------
+-----for hold times, gate enable and clock for gate sequence selection
+signal BLM_wdog_hold_time_Reg :  std_logic_vector(15 downto 0);
+signal BLM_gate_hold_time_Reg :  t_BLM_gate_hold_Time_Array;
+signal BLM_gate_seq_prep_ck_sel_Reg: std_logic_vector(15 downto 0); 
+signal BLM_gate_recover_Reg : std_logic_vector(15 downto 0);
+--signal BLM_gate_seq_in_ena_Reg :  std_logic_vector(15 downto 0);
+signal BLM_wd_reset_Reg: t_IO_Reg_0_to_3_Array;
+
+signal BLM_wd_reset: std_logic_vector(53 downto 0);
+signal BLM_ctrl_Reg:  std_logic_vector(15 downto 0); 
+signal BLM_ctrl_rd_active:    std_logic_vector(2 downto 0);
+signal BLM_ctrl_data_to_SCUB: t_IO_Reg_0_to_2_Array ;-- Data to SCU Bus Macro
+signal BLM_ctrl_Dtack:        std_logic_vector(2 downto 0);                  -- Dtack to SCU Bus Macro
+---------------------------------------
+            -- Dtack to SCU Bus Macro
+-----for BLM out_sel 
+signal BLM_out_sel_Reg :       t_BLM_out_sel_reg_Array; 
+
+signal BLM_out_sel_rd_active:  std_logic_vector(15 downto 0);
+signal BLM_out_sel_Dtack: std_logic_vector(15 downto 0);
+signal BLM_out_sel_data_to_SCUB: t_IO_Reg_0_to_15_Array;
+signal BLM_out_sel_res_Dtack     : std_logic;
+
+signal IOBP_LED_sm_nr: std_logic_vector(3 downto 0);
+---
+constant ZERO_th: std_logic_vector(BLM_th_Dtack'range) := (others => '0');
+constant ZERO_in_sel: std_logic_vector(BLM_in_sel_Dtack'range) := (others => '0');
+constant ZERO_status_sel: std_logic_vector(IOBP_in_Dtack'range) := (others => '0');
+constant ZERO_out_sel: std_logic_vector(BLM_out_sel_Dtack'range) := (others => '0');
+--  ###############################################################################################################################
+--  ###############################################################################################################################
+--  #####                                                                                                                     #####
+--  #####                                                 BEGIN                                                               #####
+--  #####                                                                                                                     #####
+--  ###############################################################################################################################
+--  ###############################################################################################################################
+
+  begin
+
+  A_nADR_EN             <= '0';
+  A_nADR_FROM_SCUB      <= '0';
+  A_nExt_Signal_in      <= '0';
+  A_nSEL_Ext_Signal_DRV <= '0';
+  A_nUser_EN            <= '0';
+
+
+--  %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+--  %%%%%                          I/O-Synch und TriState-Steuerung                                          %%%%%
+--  %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
+
+
+  p_in_sync:
+  process (clk_sys, rstn_sys)
+  begin
+    if  ( not rstn_sys    = '1') then
+      PIO_SYNC   <= (others => '0');
+      PIO_SYNC1  <= (others => '0');
+    elsif (rising_edge(clk_sys)) then
+      PIO_SYNC   <= PIO_SYNC1;
+      PIO_SYNC1  <= PIO;
+    end if;
+  end process p_in_sync;
+
+  p_out_sync:
+  process (clk_sys, rstn_sys)
+  begin
+    if  ( not rstn_sys    = '1') then
+      PIO_OUT_SYNC   <= (others => '0');
+    elsif (rising_edge(clk_sys)) then
+      PIO_OUT_SYNC   <= PIO_OUT;
+    end if;
+  end process p_out_sync;
+
+  p_ena_sync:
+  process (clk_sys, rstn_sys)
+  begin
+    if  ( not rstn_sys    = '1') then
+      PIO_ENA_SYNC   <= (others => '0');
+    elsif (rising_edge(clk_sys)) then
+      PIO_ENA_SYNC   <= PIO_ENA;
+    end if;
+  end process p_ena_sync;
+
+
+  p_diob_tristates: for I in 16 to 150 generate
+  process (PIO, PIO_OUT_SYNC, PIO_ENA_SYNC)
+  begin
+    if  PIO_ENA_SYNC(I)  = '0' then
+        PIO(I)          <= 'Z';
+    else
+        PIO(I)          <= PIO_OUT_SYNC(I);
+    end if;
+  end process p_diob_tristates;
+  end generate p_diob_tristates;
+
+
+
+  u_in_sync:
+  process (clk_sys, rstn_sys)
+  begin
+    if  ( not rstn_sys    = '1') then
+      UIO_SYNC   <= (others => '0');
+      UIO_SYNC1  <= (others => '0');
+    elsif (rising_edge(clk_sys)) then
+      UIO_SYNC   <= UIO_SYNC1;
+      UIO_SYNC1  <= UIO;
+    end if;
+  end process u_in_sync;
+
+  u_out_sync:
+  process (clk_sys, rstn_sys)
+  begin
+    if  ( not rstn_sys    = '1') then
+      UIO_OUT_SYNC   <= (others => '0');
+    elsif (rising_edge(clk_sys)) then
+      UIO_OUT_SYNC   <= UIO_OUT;
+    end if;
+  end process u_out_sync;
+
+  u_ena_sync:
+  process (clk_sys, rstn_sys)
+  begin
+    if  ( not rstn_sys    = '1') then
+      UIO_ENA_SYNC   <= (others => '0');
+    elsif (rising_edge(clk_sys)) then
+      UIO_ENA_SYNC   <= UIO_ENA;
+    end if;
+  end process u_ena_sync;
+
+
+  u_diob_tristates: for I in 0 to 15 generate
+  process (UIO, UIO_OUT_SYNC, UIO_ENA_SYNC)
+  begin
+    if  UIO_ENA_SYNC(I)  = '0' then
+        UIO(I)          <= 'Z';
+    else
+        UIO(I)          <= UIO_OUT_SYNC(I);
+    end if;
+  end process u_diob_tristates;
+  end generate u_diob_tristates;
+
+
+--  %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+--  %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
+
+  Powerup_Res <= not nPowerup_Res;  -- only for modelsim!
+  WRnRD       <= not A_RnW;         -- only for modelsim!
+
+  diob_clk_switch: slave_clk_switch
+    generic map (
+      Base_Addr => clk_switch_status_cntrl_addr,
+      card_type => g_card_type
+    )
+    port map(
+      local_clk_i             => CLK_20MHz_D,
+      sys_clk_i               => A_SysClock,
+      nReset                  => rstn_sys,
+      master_clk_o            => clk_sys,               -- core clocking
+      pll_locked              => pll_locked,
+      sys_clk_is_bad          => sys_clk_is_bad,
+      Adr_from_SCUB_LA        => ADR_from_SCUB_LA,      -- in, latched address from SCU_Bus
+      Data_from_SCUB_LA       => Data_from_SCUB_LA,     -- in, latched data from SCU_Bus
+      Ext_Adr_Val             => Ext_Adr_Val,           -- in, '1' => "ADR_from_SCUB_LA" is valid
+      Ext_Rd_active           => Ext_Rd_active,         -- in, '1' => Rd-Cycle is active
+      Ext_Wr_active           => Ext_Wr_active,         -- in, '1' => Wr-Cycle is active
+      Rd_Port                 => clk_switch_rd_data,    -- output for all read sources of this macro
+      Rd_Activ                => clk_switch_rd_active,  -- this acro has read data available at the Rd_Port.
+      Dtack                   => clk_switch_dtack,
+      signal_tap_clk_250mhz   => signal_tap_clk_250mhz,
+      clk_update              => clk_update,
+      clk_flash               => clk_flash,
+      clk_encdec              => open
+      );
+
+   reset : altera_reset
+    generic map(
+      g_plls   => 1,
+      g_clocks => 4,
+      g_areset => f_pick(c_is_arria5, 100, 1)*1024,
+      g_stable => f_pick(c_is_arria5, 100, 1)*1024)
+    port map(
+      clk_free_i    => clk_sys,
+      rstn_i        => A_nReset,
+      pll_lock_i(0) => pll_locked,
+      pll_arst_o    => open,
+      clocks_i(0)   => clk_sys,
+      clocks_i(1)   => signal_tap_clk_250mhz,
+      clocks_i(2)   => clk_update,
+      clocks_i(3)   => clk_flash,
+      rstn_o(0)     => rstn_sys,
+      rstn_o(1)     => rstn_stc,
+      rstn_o(2)     => rstn_update,
+      rstn_o(3)     => rstn_flash);
+
+
+Conf_Sts1: config_status
+generic map(
+      CS_Base_addr =>   c_Conf_Sts1_Base_Addr
+           )
+port map  (
+
+      Adr_from_SCUB_LA    =>  ADR_from_SCUB_LA,          -- latched address from SCU_Bus
+      Data_from_SCUB_LA   =>  Data_from_SCUB_LA,         -- latched data from SCU_Bus
+      Ext_Adr_Val         =>  Ext_Adr_Val,               -- '1' => "ADR_from_SCUB_LA" is valid
+      Ext_Rd_active       =>  Ext_Rd_active,             -- '1' => Rd-Cycle is active
+      Ext_Rd_fin          =>  Ext_Rd_fin,                -- marks end of read cycle, active one for one clock period of sys_clk
+      Ext_Wr_active       =>  Ext_Wr_active,             -- '1' => Wr-Cycle is active
+      Ext_Wr_fin          =>  SCU_Ext_Wr_fin,            -- marks end of write cycle, active one for one clock period of sys_clk
+      clk                 =>  clk_sys,                   -- should be the same clk, used by SCU_Bus_Slave
+      nReset              =>  rstn_sys,
+
+      Diob_Status1        =>  Diob_Status1,              -- Input-Diob_Status1
+      Diob_Status2        =>  Diob_Status2,              -- Input-Diob_Status2
+      AW_Status1          =>  AW_Status1,                -- Input-AW_Status1
+      AW_Status2          =>  AW_Status2,                -- Input-AW_Status2
+
+      Diob_Config1        =>  Diob_Config1,              -- Daten-Reg_Diob_Config1
+      Diob_Config2        =>  Diob_Config2,              -- Daten-Reg_Diob_Config2
+      AW_Config1          =>  AW_Config1,                -- Daten-Reg_AW_Config1
+      AW_Config2          =>  AW_Config2,                -- Daten-Reg_AW_Config2
+      Clr_Tag_Config      =>  Clr_Tag_Config,            -- Clear Tag-Konfigurations-Register
+
+      Diob_Config1_wr     =>  Diob_Config1_wr,           -- write-Strobe, Daten-Reg. AWOut1
+      Diob_Config2_wr     =>  Diob_Config2_wr,           -- write-Strobe, Daten-Reg. AWOut2
+      AW_Config1_wr       =>  AW_Config1_wr,             -- write-Strobe, Daten-Reg. AWOut3
+      AW_Config2_wr       =>  AW_Config2_wr,             -- write-Strobe, Daten-Reg. AWOut4
+
+      Mirr_OutReg_Maske   =>  Mirr_OutReg_Maske,   --  Maskierung für Spiegel-Modus des Ausgangsregisters
+
+      Rd_active           =>  Conf_Sts1_rd_active,       -- read data available at 'Data_to_SCUB'-AWOut
+      Dtack_to_SCUB       =>  Conf_Sts1_Dtack,           -- connect read sources to SCUB-Macro
+      Data_to_SCUB        =>  Conf_Sts1_data_to_SCUB,    -- connect Dtack to SCUB-Macro
+      LA                  =>  LA_Conf_Sts1
+      );
+
+
+
+
+Tag_Ctrl1: tag_ctrl
+generic map(
+      TAG_Base_addr =>   c_Tag_Ctrl1_Base_Addr
+           )
+port map  (
+
+      Adr_from_SCUB_LA    =>  ADR_from_SCUB_LA,          -- latched address from SCU_Bus
+      Data_from_SCUB_LA   =>  Data_from_SCUB_LA,         -- latched data from SCU_Bus
+      Ext_Adr_Val         =>  Ext_Adr_Val,               -- '1' => "ADR_from_SCUB_LA" is valid
+      Ext_Rd_active       =>  Ext_Rd_active,             -- '1' => Rd-Cycle is active
+      Ext_Rd_fin          =>  Ext_Rd_fin,                -- marks end of read cycle, active one for one clock period of sys_clk
+      Ext_Wr_active       =>  Ext_Wr_active,             -- '1' => Wr-Cycle is active
+      Ext_Wr_fin          =>  SCU_Ext_Wr_fin,            -- marks end of write cycle, active one for one clock period of sys_clk
+      Timing_Pattern_LA   =>  Timing_Pattern_LA,         -- latched timing pattern from SCU_Bus for external user functions
+      Timing_Pattern_RCV  =>  Timing_Pattern_RCV,        -- timing pattern received
+      Spare0              =>  A_Spare0,                  -- vom Master getrieben
+      Spare1              =>  A_Spare1,                  -- vom Master getrieben
+      clk                 =>  clk_sys,                   -- should be the same clk, used by SCU_Bus_Slave
+      nReset              =>  rstn_sys,
+      SCU_AW_Input_Reg    =>  SCU_AW_Input_Reg,          -- the same Input-Port's as for SCU-Bus
+      Clr_Tag_Config      =>  Clr_Tag_Config,            -- Clear Tag-Configurations-Register
+      Tag_matched_7_0     =>  Tag_matched_7_0,           -- Active on matched Tags for one clock period, one bit for each tag unit
+      Max_AWOut_Reg_Nr    =>  Max_AWOut_Reg_Nr,          -- Maximal AWOut-Reg-Number of the application
+      Max_AWIn_Reg_Nr     =>  Max_AWIn_Reg_Nr,           -- Maximal AWIn-Reg-Number of the application
+      Tag_Maske_Reg       =>  Tag_Maske_Reg,             -- Tag-Output-Mask for Register 1-7
+      Tag_Outp_Reg        =>  Tag_Outp_Reg,              -- Tag-Output-Mask for Register 1-7
+      Tag_FG_Start        =>  open,              -- Start-Puls for the FG
+      Tag_Sts             =>  Tag_Sts,                   -- Tag-Status
+      Rd_active           =>  Tag_Ctrl1_rd_active,       -- read data available at 'Data_to_SCUB'-AWOut
+      Data_to_SCUB        =>  Tag_Ctrl1_Data_to_SCUB,    -- connect read sources to SCUB-Macro
+      Dtack_to_SCUB       =>  Tag_Ctrl1_Dtack,           -- connect Dtack to SCUB-Macro
+      Tag_Aktiv           =>  Tag_Aktiv,                 -- Flag: Bit7 = Tag7 (aktiv) --- Bit0 = Tag0 (aktiv)
+      LA_Tag_Ctrl         =>  LA_Tag_Ctrl1
+      );
+
+
+
+      AW_Port1: aw_io_reg
+      generic map(
+            CLK_sys_in_Hz =>  125000000,
+            AW_Base_addr =>   c_AW_Port1_Base_Addr
+                 )
+      port map  (
+      
+            Adr_from_SCUB_LA    =>  ADR_from_SCUB_LA,    -- latched address from SCU_Bus
+            Data_from_SCUB_LA   =>  Data_from_SCUB_LA,   -- latched data from SCU_Bus
+            Ext_Adr_Val         =>  Ext_Adr_Val,         -- '1' => "ADR_from_SCUB_LA" is valid
+            Ext_Rd_active       =>  Ext_Rd_active,       -- '1' => Rd-Cycle is active
+            Ext_Rd_fin          =>  Ext_Rd_fin,          -- marks end of read cycle, active one for one clock period of sys_clk
+            Ext_Wr_active       =>  Ext_Wr_active,       -- '1' => Wr-Cycle is active
+            Ext_Wr_fin          =>  SCU_Ext_Wr_fin,      -- marks end of write cycle, active one for one clock period of sys_clk
+            clk                 =>  clk_sys,             -- should be the same clk, used by SCU_Bus_Slave
+            Ena_every_1us       =>  Ena_every_1us,       -- Clock-Enable-Puls alle Mikrosekunde, 1 Clock breit
+            nReset              =>  rstn_sys,
+      
+            SCU_AW_Input_Reg    =>  SCU_AW_Input_Reg,    -- Input-Port's  zum SCU-Bus
+            SCU_AW_Output_Reg   =>  SCU_AW_Output_Reg,   -- Output-Port's vom SCU-Bus
+      
+            AWOut_Reg1_wr       =>  AWOut_Reg1_wr,       -- Daten-Reg. AWOut1
+            AWOut_Reg2_wr       =>  AWOut_Reg2_wr,       -- Daten-Reg. AWOut2
+            AWOut_Reg3_wr       =>  AWOut_Reg3_wr,       -- Daten-Reg. AWOut3
+            AWOut_Reg4_wr       =>  AWOut_Reg4_wr,       -- Daten-Reg. AWOut4
+            AWOut_Reg5_wr       =>  AWOut_Reg5_wr,       -- Daten-Reg. AWOut5
+            AWOut_Reg6_wr       =>  AWOut_Reg6_wr,       -- Daten-Reg. AWOut6
+            AWOut_Reg7_wr       =>  AWOut_Reg7_wr,       -- Daten-Reg. AWOut7
+      
+            Rd_active           =>  AW_Port1_rd_active,       -- read data available at 'Data_to_SCUB'-AWOut
+            Dtack_to_SCUB       =>  AW_Port1_Dtack,           -- connect read sources to SCUB-Macro
+            Data_to_SCUB        =>  AW_Port1_data_to_SCUB,    -- connect Dtack to SCUB-Macro
+            LA                  =>  LA_AW_Port1
+            );
+      
+--------- AW-Output Mux zu den "Piggys" --------------------
+
+p_AW_Out_Mux:  PROCESS (Tag_Maske_Reg, Tag_Outp_Reg, SCU_AW_Output_Reg)
+    BEGin
+
+    for i in 0 to 15 loop
+
+------ Masken-Reg. aus Tag-Ctrl         Daten => Piggy             User-Output-Reg.                Daten => Piggy        Tag aus Tag-Ctrl
+------        |                              |                         |                              |                       |
+      IF Tag_Maske_Reg(1)(i)  = '0' then AW_Output_Reg(1)(i)  <= SCU_AW_Output_Reg(1)(i);  else  AW_Output_Reg(1)(i)  <= Tag_Outp_Reg(1)(i);  end if;    -- Daten-Reg. AWOut1
+      IF Tag_Maske_Reg(2)(i)  = '0' then AW_Output_Reg(2)(i)  <= SCU_AW_Output_Reg(2)(i);  else  AW_Output_Reg(2)(i)  <= Tag_Outp_Reg(2)(i);  end if;    -- Daten-Reg. AWOut2
+      IF Tag_Maske_Reg(3)(i)  = '0' then AW_Output_Reg(3)(i)  <= SCU_AW_Output_Reg(3)(i);  else  AW_Output_Reg(3)(i)  <= Tag_Outp_Reg(3)(i);  end if;    -- Daten-Reg. AWOut3
+      IF Tag_Maske_Reg(4)(i)  = '0' then AW_Output_Reg(4)(i)  <= SCU_AW_Output_Reg(4)(i);  else  AW_Output_Reg(4)(i)  <= Tag_Outp_Reg(4)(i);  end if;    -- Daten-Reg. AWOut4
+      IF Tag_Maske_Reg(5)(i)  = '0' then AW_Output_Reg(5)(i)  <= SCU_AW_Output_Reg(5)(i);  else  AW_Output_Reg(5)(i)  <= Tag_Outp_Reg(5)(i);  end if;    -- Daten-Reg. AWOut5
+      IF Tag_Maske_Reg(6)(i)  = '0' then AW_Output_Reg(6)(i)  <= SCU_AW_Output_Reg(6)(i);  else  AW_Output_Reg(6)(i)  <= Tag_Outp_Reg(6)(i);  end if;    -- Daten-Reg. AWOut6
+      IF Tag_Maske_Reg(7)(i)  = '0' then AW_Output_Reg(7)(i)  <= SCU_AW_Output_Reg(7)(i);  else  AW_Output_Reg(7)(i)  <= Tag_Outp_Reg(7)(i);  end if;    -- Daten-Reg. AWOut7
+    end loop;
+  END PROCESS p_AW_Out_Mux;
+
+
+
+IOBP_Maske: io_reg
+generic map(
+      Base_addr =>  c_IOBP_Masken_Base_Addr
+      )
+port map  (
+      Adr_from_SCUB_LA   =>  ADR_from_SCUB_LA,
+      Data_from_SCUB_LA  =>  Data_from_SCUB_LA,
+      Ext_Adr_Val        =>  Ext_Adr_Val,
+      Ext_Rd_active      =>  Ext_Rd_active,
+      Ext_Rd_fin         =>  Ext_Rd_fin,
+      Ext_Wr_active      =>  Ext_Wr_active,
+      Ext_Wr_fin         =>  SCU_Ext_Wr_fin,
+      clk                =>  clk_sys,
+      nReset             =>  rstn_sys,
+--
+      Reg_IO1            =>  IOBP_Masken_Reg1,
+      Reg_IO2            =>  IOBP_Masken_Reg2,
+      Reg_IO3            =>  IOBP_Masken_Reg3,
+      Reg_IO4            =>  IOBP_Masken_Reg4,
+      Reg_IO5            =>  IOBP_Masken_Reg5,
+      Reg_IO6            =>  IOBP_Masken_Reg6,
+      Reg_IO7            =>  IOBP_Masken_Reg7,
+      Reg_IO8            =>  IOBP_Masken_Reg8,
+      Reg_rd_active      =>  IOBP_msk_rd_active,
+      Dtack_to_SCUB      =>  IOBP_msk_Dtack,
+      Data_to_SCUB       =>  IOBP_msk_data_to_SCUB
+    );
+
+IOBP_ID_Reg: in_reg
+generic map(
+      Base_addr =>  c_IOBP_ID_Base_Addr
+      )
+port map  (
+      Adr_from_SCUB_LA   =>  ADR_from_SCUB_LA,
+      Data_from_SCUB_LA  =>  Data_from_SCUB_LA,
+      Ext_Adr_Val        =>  Ext_Adr_Val,
+      Ext_Rd_active      =>  Ext_Rd_active,
+      Ext_Rd_fin         =>  Ext_Rd_fin,
+      Ext_Wr_active      =>  Ext_Wr_active,
+      Ext_Wr_fin         =>  SCU_Ext_Wr_fin,
+      clk                =>  clk_sys,
+      nReset             =>  rstn_sys,
+--
+      Reg_In1            =>  IOBP_ID_Reg1,
+      Reg_In2            =>  IOBP_ID_Reg2,
+      Reg_In3            =>  IOBP_ID_Reg3,
+      Reg_In4            =>  IOBP_ID_Reg4,
+      Reg_In5            =>  IOBP_ID_Reg5,
+      Reg_In6            =>  IOBP_ID_Reg6,
+      Reg_In7            =>  IOBP_ID_Reg7,
+      Reg_In8            =>  IOBP_ID_Reg8,
+--
+      Reg_rd_active      =>  IOBP_id_rd_active,
+      Dtack_to_SCUB      =>  IOBP_id_Dtack,
+      Data_to_SCUB       =>  IOBP_id_data_to_SCUB
+    );
+-----------------------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------------------
+------------------- BLM Registers -------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------------------
+BLM_status_registers_0_23:for i in 0 to 2 generate 
+
+
+    BLM_Status_READBACK_Reg: in_reg
+    generic map(
+          Base_addr =>  c_Status_READBACK_Base_Addr +8*i
+          )
+    port map  (
+          Adr_from_SCUB_LA   =>  ADR_from_SCUB_LA,
+          Data_from_SCUB_LA  =>  Data_from_SCUB_LA,
+          Ext_Adr_Val        =>  Ext_Adr_Val,
+          Ext_Rd_active      =>  Ext_Rd_active,
+          Ext_Rd_fin         =>  Ext_Rd_fin,
+          Ext_Wr_active      =>  Ext_Wr_active,
+          Ext_Wr_fin         =>  SCU_Ext_Wr_fin,
+          clk                =>  clk_sys,
+          nReset             =>  rstn_sys,
+    --
+          Reg_In1            =>  BLM_Status_Reg(i*8),
+          Reg_In2            =>  BLM_Status_Reg(i*8+1),
+          Reg_In3            =>  BLM_Status_Reg(i*8+2),
+          Reg_In4            =>  BLM_Status_Reg(i*8+3),
+          Reg_In5            =>  BLM_Status_Reg(i*8+4),
+          Reg_In6            =>  BLM_Status_Reg(i*8+5),
+          Reg_In7            =>  BLM_Status_Reg(i*8+6),
+          Reg_In8            =>  BLM_Status_Reg(i*8+7),
+
+    --
+          Reg_rd_active      =>  IOBP_in_rd_active(i),
+          Dtack_to_SCUB      =>  IOBP_in_Dtack(i),
+          Data_to_SCUB       =>  IOBP_in_data_to_SCUB(i)
+        );
+    end generate BLM_status_registers_0_23;
+
+     
+
+
+        BLM_Status_READBACK_Reg_24_29: in_reg
+        generic map(
+              Base_addr =>  c_Status_READBACK_Base_Addr +24
+              )
+        port map  (
+              Adr_from_SCUB_LA   =>  ADR_from_SCUB_LA,
+              Data_from_SCUB_LA  =>  Data_from_SCUB_LA,
+              Ext_Adr_Val        =>  Ext_Adr_Val,
+              Ext_Rd_active      =>  Ext_Rd_active,
+              Ext_Rd_fin         =>  Ext_Rd_fin,
+              Ext_Wr_active      =>  Ext_Wr_active,
+              Ext_Wr_fin         =>  SCU_Ext_Wr_fin,
+              clk                =>  clk_sys,
+              nReset             =>  rstn_sys,
+        --
+              Reg_In1            =>  BLM_Status_Reg(24),
+              Reg_In2            =>  BLM_Status_Reg(24+1),
+              Reg_In3            =>  BLM_Status_Reg(24+2),
+              Reg_In4            =>  BLM_Status_Reg(24+3),
+              Reg_In5            =>  BLM_Status_Reg(24+4),
+              Reg_In6            =>  BLM_Status_Reg(24+5),
+              Reg_In7            =>  (others =>'0'),
+              Reg_In8            =>  (others =>'0'),
+    
+        --
+              Reg_rd_active      =>  IOBP_in_rd_active(3),
+              Dtack_to_SCUB      =>  IOBP_in_Dtack(3),
+              Data_to_SCUB       =>  IOBP_in_data_to_SCUB(3)
+            );
+     
+    
+
+threshold_registers: for i in 0 to 63 generate
+
+BLM_thr_Reg: io_reg
+        generic map(
+              Base_addr =>  c_BLM_thres_Base_Addr + 8*i
+              )
+        port map  (
+              Adr_from_SCUB_LA   =>  ADR_from_SCUB_LA,
+              Data_from_SCUB_LA  =>  Data_from_SCUB_LA,
+              Ext_Adr_Val        =>  Ext_Adr_Val,
+              Ext_Rd_active      =>  Ext_Rd_active,
+              Ext_Rd_fin         =>  Ext_Rd_fin,
+              Ext_Wr_active      =>  Ext_Wr_active,
+              Ext_Wr_fin         =>  SCU_Ext_Wr_fin,
+              clk                =>  clk_sys,
+              nReset             =>  rstn_sys,
+
+              Reg_IO1            =>  pos_thres_Reg(2*i)(15 downto 0),
+              Reg_IO2            =>  pos_thres_Reg(2*i)(31 downto 16),
+              Reg_IO3            =>  neg_thres_Reg(2*i)(15 downto 0),
+              Reg_IO4            =>  neg_thres_Reg(2*i)(31 downto 16),
+              Reg_IO5            =>  pos_thres_Reg(2*i+1)(15 downto 0),
+              Reg_IO6            =>  pos_thres_Reg(2*i+1)(31 downto 16),
+              Reg_IO7            =>  neg_thres_Reg(2*i+1)(15 downto 0),
+              Reg_IO8            =>  neg_thres_Reg(2*i+1)(31 downto 16),
+        --
+              Reg_rd_active      =>  BLM_th_active (i),
+              Dtack_to_SCUB      =>  BLM_th_Dtack(i),
+              Data_to_SCUB       =>  BLM_th_data_to_SCUB(i)
+            );
+  end generate threshold_registers;
+
+BLM_in_sel_registers: for i in 0 to 15 generate 
+
+BLM_in_sl_Reg: io_reg
+generic map(
+      Base_addr =>  c_BLM_in_sel_Base_Addr + 8*i
+      )
+port map  (
+      Adr_from_SCUB_LA   =>  ADR_from_SCUB_LA,
+      Data_from_SCUB_LA  =>  Data_from_SCUB_LA,
+      Ext_Adr_Val        =>  Ext_Adr_Val,
+      Ext_Rd_active      =>  Ext_Rd_active,
+      Ext_Rd_fin         =>  Ext_Rd_fin,
+      Ext_Wr_active      =>  Ext_Wr_active,
+      Ext_Wr_fin         =>  SCU_Ext_Wr_fin,
+      clk                =>  clk_sys,
+      nReset             =>  rstn_sys,
+--
+      Reg_IO1            =>  BLM_in_sel_Reg(i*8),
+      Reg_IO2            =>  BLM_in_sel_Reg(i*8+1),
+      Reg_IO3            =>  BLM_in_sel_Reg(i*8+2),
+      Reg_IO4            =>  BLM_in_sel_Reg(i*8+3),
+      Reg_IO5            =>  BLM_in_sel_Reg(i*8+4),
+      Reg_IO6            =>  BLM_in_sel_Reg(i*8+5),
+      Reg_IO7            =>  BLM_in_sel_Reg(i*8+6),
+      Reg_IO8            =>  BLM_in_sel_Reg(i*8+7),
+--
+      Reg_rd_active      =>  BLM_in_sel_rd_active(i),
+      Dtack_to_SCUB      =>  BLM_in_sel_Dtack(i),
+      Data_to_SCUB       =>  BLM_in_sel_data_to_SCUB(i)
+    );
+    end generate BLM_in_sel_registers;
+
+
+BLM_ctrl_Reg_1st_block: io_reg
+  generic map(
+        Base_addr =>  c_BLM_ctrl_Base_Addr
+        )
+  port map  (
+        Adr_from_SCUB_LA   =>  ADR_from_SCUB_LA,
+        Data_from_SCUB_LA  =>  Data_from_SCUB_LA,
+        Ext_Adr_Val        =>  Ext_Adr_Val,
+        Ext_Rd_active      =>  Ext_Rd_active,
+        Ext_Rd_fin         =>  Ext_Rd_fin,
+        Ext_Wr_active      =>  Ext_Wr_active,
+        Ext_Wr_fin         =>  SCU_Ext_Wr_fin,
+        clk                =>  clk_sys,
+        nReset             =>  rstn_sys,
+ 
+  Reg_IO1            =>  BLM_wdog_hold_time_Reg,     -- the same for all
+  Reg_IO2            =>  BLM_gate_seq_prep_ck_sel_Reg,    -- bit 15 not used
+                                                          -- bit 14-3 for gate_prepare signals
+                                                          -- bit 2-0 for the clock gate sel, the same for all
+
+  Reg_IO3            =>  BLM_ctrl_Reg,               --  bit 0 = counter RESET, 
+                                    
+                                                     --  bit 11..0 Direct Gate-usage, one bit for each gate signal input, 
+                                                     --  bit 14 reset from gate: when 1 the corresponding gate signal selecting the counter enable
+                                                     --         is used instead to reset it.
+                                                     -- bit 15 not used
+  Reg_IO4            =>  BLM_gate_recover_Reg, -- bit 15 -12 not used
+                                                -- bit 11-0 for gate_recover signals
+  Reg_IO5            =>   BLM_gate_hold_time_Reg(0), 
+  Reg_IO6            =>   BLM_gate_hold_time_Reg(1),
+  Reg_IO7            =>   BLM_gate_hold_time_Reg(2),
+  Reg_IO8            =>   BLM_gate_hold_time_Reg(3),
+
+  Reg_rd_active      =>   BLM_ctrl_rd_active(0),
+  Dtack_to_SCUB      =>   BLM_ctrl_Dtack(0),
+  Data_to_SCUB       =>   BLM_ctrl_data_to_SCUB(0)
+      );
+
+  BLM_ctrl_Reg_2nd_block: io_reg
+      generic map(
+            Base_addr =>  c_BLM_ctrl_Base_Addr + 8
+            )
+      port map  (
+            Adr_from_SCUB_LA   =>  ADR_from_SCUB_LA,
+            Data_from_SCUB_LA  =>  Data_from_SCUB_LA,
+            Ext_Adr_Val        =>  Ext_Adr_Val,
+            Ext_Rd_active      =>  Ext_Rd_active,
+            Ext_Rd_fin         =>  Ext_Rd_fin,
+            Ext_Wr_active      =>  Ext_Wr_active,
+            Ext_Wr_fin         =>  SCU_Ext_Wr_fin,
+            clk                =>  clk_sys,
+            nReset             =>  rstn_sys,
+     
+      Reg_IO1            =>   BLM_gate_hold_time_Reg(4),
+      Reg_IO2            =>   BLM_gate_hold_time_Reg(5),
+      Reg_IO3            =>   BLM_gate_hold_time_Reg(6),
+      Reg_IO4            =>   BLM_gate_hold_time_Reg(7),
+      Reg_IO5            =>   BLM_gate_hold_time_Reg(8),
+      Reg_IO6            =>   BLM_gate_hold_time_Reg(9),
+      Reg_IO7            =>   BLM_gate_hold_time_Reg(10),
+      Reg_IO8            =>   BLM_gate_hold_time_Reg(11),
+
+      Reg_rd_active      =>   BLM_ctrl_rd_active(1),
+      Dtack_to_SCUB      =>   BLM_ctrl_Dtack(1),
+      Data_to_SCUB       =>   BLM_ctrl_data_to_SCUB(1)
+          );
+
+      BLM_ctrl_Reg_3rdd_block: io_reg
+          generic map(
+                Base_addr =>  c_BLM_ctrl_Base_Addr + 16
+                )
+          port map  (
+                Adr_from_SCUB_LA   =>  ADR_from_SCUB_LA,
+                Data_from_SCUB_LA  =>  Data_from_SCUB_LA,
+                Ext_Adr_Val        =>  Ext_Adr_Val,
+                Ext_Rd_active      =>  Ext_Rd_active,
+                Ext_Rd_fin         =>  Ext_Rd_fin,
+                Ext_Wr_active      =>  Ext_Wr_active,
+                Ext_Wr_fin         =>  SCU_Ext_Wr_fin,
+                clk                =>  clk_sys,
+                nReset             =>  rstn_sys,
+         
+          Reg_IO1            =>   BLM_wd_reset_Reg(0),
+          Reg_IO2            =>   BLM_wd_reset_Reg(1),
+          Reg_IO3            =>   BLM_wd_reset_Reg(2),
+          Reg_IO4            =>   BLM_wd_reset_Reg(3),
+          Reg_IO5            =>   open,
+          Reg_IO6            =>   open,
+          Reg_IO7            =>   open,
+          Reg_IO8            =>   open,
+    
+          Reg_rd_active      =>   BLM_ctrl_rd_active(2),
+          Dtack_to_SCUB      =>   BLM_ctrl_Dtack(2),
+          Data_to_SCUB       =>   BLM_ctrl_data_to_SCUB(2)
+              );
+          
+  BLM_out_sel_registers: for i in 0 to 14 generate 
+
+      BLM_o_sel_Reg: io_reg
+      generic map(
+            Base_addr =>  c_BLM_out_sel_Base_Addr + 8*i
+            )
+      port map  (
+            Adr_from_SCUB_LA   =>  ADR_from_SCUB_LA,
+            Data_from_SCUB_LA  =>  Data_from_SCUB_LA,
+            Ext_Adr_Val        =>  Ext_Adr_Val,
+            Ext_Rd_active      =>  Ext_Rd_active,
+            Ext_Rd_fin         =>  Ext_Rd_fin,
+            Ext_Wr_active      =>  Ext_Wr_active,
+            Ext_Wr_fin         =>  SCU_Ext_Wr_fin,
+            clk                =>  clk_sys,
+            nReset             =>  rstn_sys,
+      --
+            Reg_IO1            =>  BLM_out_sel_Reg(i*8),
+            Reg_IO2            =>  BLM_out_sel_Reg(i*8+1),
+            Reg_IO3            =>  BLM_out_sel_Reg(i*8+2),
+            Reg_IO4            =>  BLM_out_sel_Reg(i*8+3),
+            Reg_IO5            =>  BLM_out_sel_Reg(i*8+4),
+            Reg_IO6            =>  BLM_out_sel_Reg(i*8+5),
+            Reg_IO7            =>  BLM_out_sel_Reg(i*8+6),
+            Reg_IO8            =>  BLM_out_sel_Reg(i*8+7),
+      --
+            Reg_rd_active      =>  BLM_out_sel_rd_active(i),
+            Dtack_to_SCUB      =>  BLM_out_sel_Dtack(i),
+            Data_to_SCUB       =>  BLM_out_sel_data_to_SCUB(i)
+          );
+          end generate BLM_out_sel_registers;
+
+          
+
+          BLM_o_sel_Reg_120_126: io_reg
+          generic map(
+                Base_addr =>  c_BLM_out_sel_Base_Addr + 120
+                )
+          port map  (
+                Adr_from_SCUB_LA   =>  ADR_from_SCUB_LA,
+                Data_from_SCUB_LA  =>  Data_from_SCUB_LA,
+                Ext_Adr_Val        =>  Ext_Adr_Val,
+                Ext_Rd_active      =>  Ext_Rd_active,
+                Ext_Rd_fin         =>  Ext_Rd_fin,
+                Ext_Wr_active      =>  Ext_Wr_active,
+                Ext_Wr_fin         =>  SCU_Ext_Wr_fin,
+                clk                =>  clk_sys,
+                nReset             =>  rstn_sys,
+          --
+                Reg_IO1            =>  BLM_out_sel_Reg(120),
+                Reg_IO2            =>  BLM_out_sel_Reg(121),
+                Reg_IO3            =>  BLM_out_sel_Reg(122),
+                Reg_IO4            =>  BLM_out_sel_Reg(123),
+                Reg_IO5            =>  BLM_out_sel_Reg(124),
+                Reg_IO6            =>  BLM_out_sel_Reg(125),
+                Reg_IO7            =>  BLM_out_sel_Reg(126),
+                Reg_IO8            =>  open,
+          --
+                Reg_rd_active      =>  BLM_out_sel_rd_active(15),
+                Dtack_to_SCUB      =>  BLM_out_sel_Dtack(15),
+                Data_to_SCUB       =>  BLM_out_sel_data_to_SCUB(15));
+
+
+          
+        DAQ_modul: daq
+        GENERIC MAP(
+          Base_addr           =>  to_unsigned(c_DIOB_DAQ_Base_Addr, 16),
+          CLK_sys_in_Hz       => 125000000,        
+          ch_num => daq_ch_num                  
+              )
+        
+        PORT MAP  (
+        
+            Adr_from_SCUB_LA      => ADR_from_SCUB_LA,
+            Data_from_SCUB_LA     => Data_from_SCUB_LA,
+            Ext_Adr_Val           => Ext_Adr_Val,
+            Ext_Rd_active         => Ext_Rd_active,
+            Ext_Wr_active         => Ext_Wr_active,
+            clk_i                 => clk_sys,
+            nReset                => rstn_sys,
+        
+            diob_extension_id     =>  daq_diob_ID,
+            user_rd_active        =>  daq_user_rd_active,   
+            Rd_Port               =>  daq_data_to_SCUB,  
+            Dtack                 =>  daq_Dtack,
+            daq_srq               =>  daq_srq,
+            HiRes_srq             =>  daq_HiRes_srq,   
+            Timing_Pattern_LA     => Timing_Pattern_LA,
+            Timing_Pattern_RCV    => Timing_Pattern_RCV, 
+        
+            --daq input channels
+            daq_dat_i             => daq_dat,
+            daq_ext_trig          =>  daq_ext_trig
+          );
+        
+testport_mux: process (A_SEL, AW_Config1, AW_Input_Reg, AW_Output_Reg, LA_Tag_Ctrl1,
+                       LA_AW_Port1, LA_Conf_Sts1, Timing_Pattern_RCV,
+                       Timing_Pattern_LA, test_port_in_0, test_clocks, uart_txd_out,
+                       Ext_Rd_active, Ext_Rd_fin, Ext_Rd_Fin_ovl, Ext_Wr_active, SCU_Ext_Wr_fin, Ext_Wr_fin_ovl
+                       )
+begin
+  case (not A_SEL) is
+    when X"0" => test_out <= AW_Config1;
+    when X"1" => test_out <= AW_Input_Reg(1);
+    when X"2" => test_out <= AW_Input_Reg(2);
+    when X"3" => test_out <= AW_Input_Reg(3);
+    when X"4" => test_out <= AW_Output_Reg(1);
+    when X"5" => test_out <= AW_Output_Reg(2);
+    when X"6" => test_out <= AW_Output_Reg(3);
+--                                                 +-------------------- '1' drives the external max level shifter
+    when X"7" => test_out <= X"000" & '0' & '0' & '1' & uart_txd_out;
+--
+    when X"8" => test_out <= LA_Tag_Ctrl1;   -- Logic analyser Signals "LA_Tag_Ctrl1"
+    when X"9" => test_out <= LA_Conf_Sts1;
+    when X"A" => test_out <= LA_AW_Port1; 
+    --
+    when X"B" => test_out <= X"00"&
+                              '0' &
+                              '0' &
+                              Ext_Rd_active  &  -- out, '1' => Rd-Cycle to external user register is active
+                              Ext_Rd_fin     &  -- out, marks end of read cycle, active one for one clock period of clk past cycle end (no overlap)
+                              Ext_Rd_Fin_ovl &  -- out, marks end of read cycle, active one for one clock period of clk during cycle end (overlap)
+                              Ext_Wr_active  &  -- out, '1' => Wr-Cycle to external user register is active
+                              SCU_Ext_Wr_fin &  -- out, marks end of write cycle, active high for one clock period of clk past cycle end (no overlap)
+                              Ext_Wr_fin_ovl;   -- out, marks end of write cycle, active high for one clock period of clk before write cycle finished (with overlap)
+--
+    when X"C" => test_out <= Timing_Pattern_RCV & Timing_Pattern_LA(14 downto 0);-- Timing
+   --
+    when X"D" =>    test_out <= X"0000";
+    when X"E" =>    test_out <= test_clocks;
+    when X"F" =>    test_out <= test_port_in_0;
+    when others =>  test_out <= (others => '0');
+  end case;
+end process testport_mux;
+
+hp_la_o <=  x"0000";  --test_out(15 downto 0);
+test_port_in_0 <= x"0000"; --- kein Clock's am Teststecker
+
+test_clocks <=  X"0"                                                                              -- bit15..12            
+              & '0' & '0' & '0' & '0'                                                             -- bit11..8
+              & '0' & pll_locked & sys_clk_deviation & sys_clk_deviation_la                       -- bit7..4
+              & local_clk_is_running & local_clk_is_bad & sys_clk_is_bad & sys_clk_is_bad_la;     -- bit3..0
+
+  -- open drain buffer for one wire
+        owr_i(0) <= A_OneWire;
+        A_OneWire <= owr_pwren_o(0) when (owr_pwren_o(0) = '1' or owr_en_o(0) = '1') else 'Z';
+
+zeit1 : zeitbasis
+generic map (
+      CLK_in_Hz =>  clk_sys_in_Hz,
+      diag_on   =>  1
+      )
+port map  (
+      Res               =>  not rstn_sys,
+      Clk               =>  clk_sys,
+      Ena_every_100ns   =>  Ena_Every_100ns,
+      Ena_every_166ns   =>  Ena_Every_166ns,
+      Ena_every_250ns   =>  Ena_every_250ns,
+      Ena_every_500ns   =>  Ena_every_500ns,
+      Ena_every_1us     =>  Ena_every_1us,
+      Ena_Every_20ms    =>  Ena_Every_20ms
+      );
+
+
+p_led_sel: led_n
+  generic map (stretch_cnt => stretch_cnt)
+  port map      (ena => Ena_Every_20ms, CLK => clk_sys, Sig_in => (not A_nBoardSel and not A_nDS), nLED => s_nLED_Sel);-- LED: sel Board
+
+p_led_dtack: led_n
+  generic map (stretch_cnt => stretch_cnt)
+  port map      (ena => Ena_Every_20ms, CLK => clk_sys, Sig_in => SCUB_Dtack, nLED => s_nLED_Dtack);-- LED: Dtack to SCU-Bus
+
+p_led_inr: led_n
+  generic map (stretch_cnt => stretch_cnt)
+  port map      (ena => Ena_Every_20ms, CLK => clk_sys, Sig_in => SCUB_SRQ, nLED => s_nLED_inR);-- LED: interrupt
+
+--p_led_pu: led_n
+--  generic map (stretch_cnt => stretch_cnt)
+--  port map      (ena => Ena_Every_20ms, CLK => clk_sys, Sig_in => not (rstn_sys), nLED => s_nLED_PU);-- LED: rstn_syset
+
+p_led_user1: led_n
+  generic map (stretch_cnt => stretch_cnt)
+  port map      (ena => Ena_Every_20ms, CLK => clk_sys, Sig_in => s_nLED_User1_i, nLED => s_nLED_User1_o);-- LED3 = User 1
+
+p_led_user2: led_n
+  generic map (stretch_cnt => stretch_cnt)
+  port map      (ena => Ena_Every_20ms, CLK => clk_sys, Sig_in => s_nLED_User2_i, nLED => s_nLED_User2_o);-- LED3 = User 1
+
+p_led_user3: led_n
+  generic map (stretch_cnt => stretch_cnt)
+  port map      (ena => Ena_Every_20ms, CLK => clk_sys, Sig_in => s_nLED_User3_i, nLED => s_nLED_User3_o);-- LED3 = User 1
+
+
+
+A_nLED_D2 <=   s_nLED_Sel;    -- Diagnose-LED_D2 = BoardSelekt
+A_nLED_D3 <=   s_nLED_Dtack;  -- Diagnose-LED_D3 = Dtack
+
+
+
+sel_every_10ms: div_n
+  generic map (n => integer(10.0e-3 / 1.0e-6), diag_on => 0)  -- ena nur jede us für einen Takt aktiv, deshalb n = 10000
+    port map  ( res => not rstn_sys,
+                clk => clk_sys,
+                ena => ENA_every_1us,
+                div_o => ENA_every_10ms
+              );
+
+sel_every_250ms: div_n
+  generic map (n => 12, diag_on => 0)  -- ena nur alle 20ms fr einen Takt aktiv, deshalb 13x20ms = 260ms
+    port map  ( res => not rstn_sys,
+                clk => clk_sys,
+                ena => Ena_Every_20ms,
+                div_o => ENA_every_250ms
+              );
+
+sel_every_500ms: div_n
+  generic map (n => 25, diag_on => 0)  -- ena nur alle 20ms fr einen Takt aktiv, deshalb 25x20ms = 500ms
+    port map  ( res => not rstn_sys,
+                clk => clk_sys,
+                ena => Ena_Every_20ms,
+                div_o => ENA_every_500ms
+              );
+
+
+p_clk_blink:
+process (clk_sys, rstn_sys, ENA_every_250ms)
+begin
+  if  ( not rstn_sys    = '1') then
+      clk_blink   <= '0';
+  elsif (rising_edge(clk_sys)) then
+    if (ENA_every_500ms = '1') then
+      clk_blink <= not clk_blink;
+    end if;
+  end if;
+end process;
+
+
+
+clk_switch_intr <= local_clk_is_running or sys_clk_deviation_la;
+
+SCU_Slave: SCU_Bus_Slave
+generic map (
+    CLK_in_Hz               => clk_sys_in_Hz,
+    Firmware_Release        => c_Firmware_Release,  -------------------- important: => Firmware_Release
+    Firmware_Version        => c_Firmware_Version,  -------------------- important: => Firmware_Version
+    CID_System              => 55, ------------------------------------- important: => CSCOHW
+    intr_Enable             => b"0000_0000_0000_0001")
+port map (
+    SCUB_Addr               => A_A,                                   -- in, SCU_Bus: address bus
+    nSCUB_Timing_Cyc        => A_nEvent_Str,                          -- in, SCU_Bus signal: low active SCU_Bus runs timing cycle
+    SCUB_Data               => A_D,                                   -- inout, SCU_Bus: data bus (FPGA tri state buffer)
+    nSCUB_Slave_Sel         => A_nBoardSel,                           -- in, SCU_Bus: '0' => SCU master select slave
+    nSCUB_DS                => A_nDS,                                 -- in, SCU_Bus: '0' => SCU master activate data strobe
+    SCUB_RDnWR              => A_RnW,                                 -- in, SCU_Bus: '1' => SCU master read slave
+    clk                     => clk_sys,
+    nSCUB_Reset_in          => A_nReset,                              -- in, SCU_Bus-Signal: '0' => 'nSCUB_Reset_in' is active
+    Data_to_SCUB            => Data_to_SCUB,                          -- in, connect read sources from external user functions
+    Dtack_to_SCUB           => Dtack_to_SCUB,                         -- in, connect Dtack from from external user functions
+   intr_in                 => '0'& '0' & tmr_irq &  daq_srq           -- bit 15..12
+                               & daq_HiRes_srq & '0' & '0' &'0'       -- bit 11..8
+
+                              & x"0"                                  -- bit 7..4
+                              & '0' & '0' & clk_switch_intr,          -- bit 3..1
+    User_Ready              => '1',
+    CID_GROUP               => 26,                                    -- important: => "FG900500_SCU_Diob1"
+    extension_cid_system    => extension_cid_system,                  -- in, extension card: cid_system
+    extension_cid_group     => extension_cid_group,                   -- in, extension card: cid_group
+    Data_from_SCUB_LA       => Data_from_SCUB_LA,                     -- out, latched data from SCU_Bus for external user functions
+    ADR_from_SCUB_LA        => ADR_from_SCUB_LA,                      -- out, latched address from SCU_Bus for external user functions
+    Timing_Pattern_LA       => Timing_Pattern_LA,                     -- out, latched timing pattern from SCU_Bus for external user functions
+    Timing_Pattern_RCV      => Timing_Pattern_RCV,                    -- out, timing pattern received
+    nSCUB_Dtack_Opdrn       => open,                                  -- out, for direct connect to SCU_Bus opendrain signal
+                                                                      -- '0' => slave give dtack to SCU master
+    SCUB_Dtack              => SCUB_Dtack,                            -- out, for connect via ext. open collector driver
+                                                                      -- '1' => slave give dtack to SCU master
+    nSCUB_SRQ_Opdrn         => open,                                  -- out, for direct connect to SCU_Bus opendrain signal
+                                                                      -- '0' => slave service request to SCU ma
+    SCUB_SRQ                => SCUB_SRQ,                              -- out, for connect via ext. open collector driver
+                                                                      -- '1' => slave service request to SCU master
+    nSel_Ext_Data_Drv       => A_nSel_Ext_Data_Drv,                   -- out, '0' => select the external data driver on the SCU_Bus slave
+    Ext_Data_Drv_Rd         => A_Ext_Data_RD,                         -- out, '1' => direction of the external data driver on the
+                                                                      -- SCU_Bus slave is to the SCU_Bus
+    Standard_Reg_Acc        => Standard_Reg_Acc,                      -- out, '1' => mark the access to register of this macro
+    Ext_Adr_Val             => Ext_Adr_Val,                           -- out, for external user functions: '1' => "ADR_from_SCUB_LA" is valid
+    Ext_Rd_active           => Ext_Rd_active,                         -- out, '1' => Rd-Cycle to external user register is active
+    Ext_Rd_fin              => Ext_Rd_fin,                            -- out, marks end of read cycle, active one for one clock period
+                                                                      -- of clk past cycle end (no overlap)
+    Ext_Rd_Fin_ovl          => Ext_Rd_Fin_ovl,                        -- out, marks end of read cycle, active one for one clock period
+                                                                      -- of clk during cycle end (overlap)
+    Ext_Wr_active           => Ext_Wr_active,                         -- out, '1' => Wr-Cycle to external user register is active
+    Ext_Wr_fin              => SCU_Ext_Wr_fin,                        -- out, marks end of write cycle, active high for one clock period
+                                                                      -- of clk past cycle end (no overlap)
+    Ext_Wr_fin_ovl          => Ext_Wr_fin_ovl,                        -- out, marks end of write cycle, active high for one clock period
+                                                                      -- of clk before write cycle finished (with overlap)
+    Deb_SCUB_Reset_out      => Deb_SCUB_Reset_out,                    -- out, the debounced 'nSCUB_Reset_in'-signal, is active high,
+                                                                      -- can be used to reset
+                                                                      -- external macros, when 'nSCUB_Reset_in' is '0'
+    nPowerup_Res            => nPowerup_Res,                          -- out, this macro generates a power up reset
+    Powerup_Done            => Powerup_Done                           -- out, this signal is set after powerup. Only the SCUB-Master can clear this bit.
+    );
+
+lm32_ow: housekeeping
+generic map (
+  Base_addr => c_lm32_ow_Base_Addr)
+port map (
+  clk_sys     => clk_sys,
+  clk_update  => clk_update,
+  clk_flash   => clk_flash,
+  rstn_sys    => rstn_sys,
+  rstn_update => rstn_update,
+  rstn_flash  => rstn_flash,
+
+
+  ADR_from_SCUB_LA  => ADR_from_SCUB_LA,
+  Data_from_SCUB_LA => Data_from_SCUB_LA,
+  Ext_Adr_Val       => Ext_Adr_Val,
+  Ext_Rd_active     => Ext_Rd_active,
+  Ext_Wr_active     => Ext_Wr_active,
+  user_rd_active    => wb_scu_rd_active,
+  Data_to_SCUB      => wb_scu_data_to_SCUB,
+  Dtack_to_SCUB     => wb_scu_dtack,
+
+  owr_pwren_o       => owr_pwren_o,
+  owr_en_o          => owr_en_o,
+  owr_i             => owr_i,
+
+  debug_serial_o    => uart_txd_out,
+  debug_serial_i    => '0');
+
+
+
+  tmr: tmr_scu_bus
+  generic map (
+    Base_addr     => c_tmr_Base_Addr,
+    diag_on_is_1  => 1)
+  port map (
+    clk           => clk_sys,
+    nrst          => rstn_sys,
+    tmr_irq       => tmr_irq,
+
+    Adr_from_SCUB_LA  => ADR_from_SCUB_LA,
+    Data_from_SCUB_LA => Data_from_SCUB_LA,
+    Ext_Adr_Val       => Ext_Adr_Val,
+    Ext_Rd_active     => Ext_Rd_active,
+    Ext_Wr_active     => Ext_Wr_active,
+    user_rd_active    => tmr_rd_active,
+    Data_to_SCUB      => tmr_data_to_SCUB,
+    Dtack_to_SCUB     => tmr_dtack);
+
+rd_port_mux:  process ( clk_switch_rd_active,     clk_switch_rd_data,
+                        wb_scu_rd_active,         wb_scu_data_to_SCUB,
+                        Tag_Ctrl1_rd_active,      Tag_Ctrl1_data_to_SCUB,
+                        Conf_Sts1_rd_active,      Conf_Sts1_data_to_SCUB,
+                        tmr_rd_active,            tmr_data_to_SCUB,
+                        AW_Port1_rd_active,       AW_Port1_data_to_SCUB,
+                        IOBP_msk_rd_active,       IOBP_msk_data_to_SCUB,
+                        IOBP_id_rd_active,        IOBP_id_data_to_SCUB,
+                        IOBP_in_rd_active,        IOBP_in_data_to_SCUB,
+                        daq_user_rd_active,       daq_data_to_SCUB,
+                        BLM_ctrl_rd_active,       BLM_ctrl_data_to_SCUB,
+                        BLM_th_active,            BLM_th_data_to_SCUB,
+                        BLM_in_sel_rd_active,     BLM_in_sel_data_to_SCUB
+                      )
+
+
+  variable sel: unsigned(11 downto 0);
+  variable sel_th: unsigned(63 downto 0);
+  variable sel_in_sel: unsigned(15 downto 0);
+  variable sel_st: unsigned(3 downto 0);
+  variable sel_out_sel: unsigned(15 downto 0); 
+
+  begin
+
+
+    sel_in_sel := unsigned(BLM_in_sel_rd_active);
+    sel_th:= unsigned (BLM_th_active);
+    sel_st:= unsigned(IOBP_in_rd_active);
+    sel_out_sel := unsigned(BLM_out_sel_rd_active);
+    
+    sel:=  BLM_ctrl_rd_active(1)& BLM_ctrl_rd_active(1)&BLM_ctrl_rd_active(0)  &  daq_user_rd_active & 
+            AW_Port1_rd_active & tmr_rd_active &  wb_scu_rd_active & clk_switch_rd_active &
+            Conf_Sts1_rd_active & Tag_Ctrl1_rd_active & IOBP_msk_rd_active & IOBP_id_rd_active ;
+  
+if to_integer(sel(11 downto 0))>0 then
+  case sel(11 downto 0) IS
+      when "100000000000" => Data_to_SCUB <= BLM_ctrl_data_to_SCUB(2);
+      when "010000000000" => Data_to_SCUB <= BLM_ctrl_data_to_SCUB(1);
+      when "001000000000" => Data_to_SCUB <= BLM_ctrl_data_to_SCUB(0);
+      when "000100000000" => Data_to_SCUB <= daq_data_to_SCUB;
+      when "000010000000" => Data_to_SCUB <= AW_Port1_data_to_SCUB;  
+      when "000001000000" => Data_to_SCUB <= tmr_data_to_SCUB;
+      when "000000100000" => Data_to_SCUB <= wb_scu_data_to_SCUB;
+      when "000000010000" => Data_to_SCUB <= clk_switch_rd_data;
+      when "000000001000" => Data_to_SCUB <= Conf_Sts1_data_to_SCUB;
+      when "000000000100" => Data_to_SCUB <= Tag_Ctrl1_data_to_SCUB;
+      when "000000000010" => Data_to_SCUB <= IOBP_msk_data_to_SCUB;
+      when "000000000001" => Data_to_SCUB <= IOBP_id_data_to_SCUB;
+
+      when others      => Data_to_SCUB <= (others => '0');
+    end case;
+else 
+    if to_integer(sel_th)>0 then
+        for i in 0 to 63 loop
+          if sel_th(i) = '1' then 
+            Data_to_SCUB <= BLM_th_data_to_SCUB(i);
+          end if;
+        end loop;
+        else 
+        if to_integer(sel_in_sel) > 0 then  
+           for i in 0 to 15 loop
+             if sel_in_sel(i) = '1' then 
+                Data_to_SCUB <= BLM_in_sel_data_to_SCUB(i);
+             end if;
+           end loop;
+           else
+           if to_integer(sel_st) > 0 then  
+           for i in 0 to 3 loop
+             if sel_st(i) = '1' then 
+                Data_to_SCUB <= IOBP_in_data_to_SCUB(i);
+             end if;
+           end loop;
+           else
+           if to_integer(sel_out_sel) > 0 then  
+           for i in 0 to 15 loop
+             if sel_out_sel(i) = '1' then 
+                Data_to_SCUB <=  BLM_out_sel_data_to_SCUB(i);
+             end if;
+           end loop;
+        
+        else 
+           Data_to_SCUB <= (others =>'0');
+        end if;
+    end if;
+    end if;
+  end if;
+  end if;  
+           
+  end process rd_port_mux;
+
+  ------------------------------------------------------
+  -----Dtack_to_SCUB for gate/wd ena registers
+  new_Dtack_sproc: process(BLM_th_Dtack,BLM_in_sel_Dtack)
+  begin
+  
+------------------------------------------------------
+
+  ------------------------------------------------------
+  -----Dtack_to_SCUB for threshold registers
+ 
+    if (BLM_th_Dtack = ZERO_th) then BLM_th_res_Dtack <='0';
+    else BLM_th_res_Dtack <='1';
+    end if;
+  ------------------------------------------------------
+  -----Dtack_to_SCUB for input and gate ena registers
+ 
+  if (BLM_in_sel_Dtack =ZERO_in_sel) then BLM_in_sel_res_Dtack <='0';
+  else BLM_in_sel_res_Dtack <='1';
+  end if;
+   
+ ------------------------------------------------------
+-----Dtack_to_SCUB for out_sel registers
+ 
+if (BLM_out_sel_Dtack =ZERO_out_sel) then BLM_out_sel_res_Dtack <='0';
+else BLM_out_sel_res_Dtack <='1';
+end if;
+   
+
+-----Dtack_to_SCUB for status registers
+ 
+if (IOBP_in_Dtack =ZERO_status_sel) then IOBP_in_res_Dtack <='0';
+else IOBP_in_res_Dtack <='1';
+end if;
+   
+-------------- Dtack_to_SCUB -----------------------------
+
+    Dtack_to_SCUB <= ( tmr_dtack  or AW_Port1_Dtack   or wb_scu_dtack  or clk_switch_dtack  or Conf_Sts1_Dtack  or Tag_Ctrl1_Dtack  or
+                         IOBP_msk_Dtack   or IOBP_id_Dtack    or    IOBP_in_res_Dtack or daq_Dtack or 
+                         BLM_ctrl_Dtack(2) or BLM_ctrl_Dtack(1) or  BLM_ctrl_Dtack(0) or BLM_th_res_Dtack or BLM_in_sel_res_Dtack or BLM_out_sel_res_Dtack);
+
+    A_nDtack <= NOT(SCUB_Dtack);
+    A_nSRQ   <= NOT(SCUB_SRQ);
+  end process;
+
+--  +============================================================================================================================+
+--  |            §§§                        Anwender-IO: IOBP (INLB12S1)  -- FG902_050                                           |
+--  +============================================================================================================================+
+--Deb66:  for I in 0 to 65 generate
+--DB_I:  diob_debounce
+--GENERIC MAP (DB_Tst_Cnt   => 3,
+--             Test         => 0)             --
+--          port map(DB_Cnt => Debounce_cnt,     -- Debounce-Zeit in Clock's
+--                   DB_in  => Deb66_in(I),   -- Signal-Input
+--                   Reset  => not rstn_sys,  -- Powerup-Reset
+--                   clk    => clk_sys,       -- Sys-Clock
+--                   DB_Out => Deb66_out(I)); -- Debounce-Signal-Out
+--end generate Deb66;
+
+Deg_in_signals:  for I in 0 to 53 generate
+DB_I: deglitcher 
+  generic	map (nr_stages => 1
+)
+port map 
+(
+    clock => clk_sys,        
+   reset=> not rstn_sys,           
+  degl_in => Deg66_in(I), 
+  degl_out => Deg66_out(I)
+);
+  end generate Deg_in_signals;
+
+--Deg_gate_signals: for I in 54 to 65 generate
+--DB_I: gate_deglitcher 
+--  generic	map (nr_stages => 10
+--)
+--port map 
+--(
+  --  clock => clk_sys,        
+  -- reset=> not rstn_sys,           
+  --degl_in => Deg66_in(I), 
+  --degl_out => Deg66_out(I)
+--);
+  -- end generate Deg_gate_signals;
+--  Deg_gate_signals: for I in 0 to 11 generate
+--DB_GI: gate_deglitcher 
+--  generic	map (nr_stages => 10
+--)
+--port map 
+--(
+ --   clock => clk_sys,        
+--   reset=> not rstn_sys,           
+--  degl_in => Deg66_in(I+54), 
+--  degl_out => Deg66_out(I+54)
+--);
+--  end generate Deg_gate_signals;
+
+  Deb_GI:  for I in 0 to 11 generate
+ DB_GI:  diob_debounce
+GENERIC MAP (DB_Tst_Cnt   => 20, --3,
+            Test         => 0)             --
+          port map(DB_Cnt => Debounce_cnt,     -- Debounce-Zeit in Clock's
+                   DB_in  => Deg66_in(I+54),   -- Signal-Input
+                  Reset  => not rstn_sys,  -- Powerup-Reset
+                  clk    => clk_sys,       -- Sys-Clock
+                  DB_Out => Deg66_out(I+54)); -- Debounce-Signal-Out
+end generate Deb_GI;
+--
+--         =========== Component's für die 72 "aktiv" Led's ===========
+--
+IOBP_In_LEDn:  for J in 1 to 12 generate
+--                ---------------------------------------------------------------------------
+                  IOBP_In_LEDn_Slave1:  for I in 1 to 6 generate
+                    DB_I:  LED_n
+                    GENERIC MAP (stretch_cnt => stretch_cnt)             --
+                              port map(ena   => Ena_Every_20ms,          -- Enable-Clock
+                                      CLK    => clk_sys,                 -- Sys-Clock
+                                      Sig_in => IOBP_Aktiv_LED_i(J)(I),  -- Signal-Input
+                                      nLED   => IOBP_Aktiv_LED_o(J)(I)); -- Signal-Out
+                    end generate IOBP_In_LEDn_Slave1;
+--                ---------------------------------------------------------------------------
+                  end generate IOBP_In_LEDn;
+--
+---Beam Loss Monitor new version
+
+
+
+
+BLM_data_in <= AW_IOBP_Input_Reg(5)(5 downto 0) & AW_IOBP_Input_Reg(4)(11 downto 6) & AW_IOBP_Input_Reg(4)(5 downto 0) &
+               AW_IOBP_Input_Reg(3)(11 downto 6) & AW_IOBP_Input_Reg(3)(5 downto 0) & AW_IOBP_Input_Reg(2)(11 downto 6) & 
+               AW_IOBP_Input_Reg(2)(5 downto 0) &  AW_IOBP_Input_Reg(1)(11 downto 6) & AW_IOBP_Input_Reg(1)(5 downto 0); 
+
+BLM_gate_in <= AW_IOBP_Input_Reg(5)(11 downto 6) & AW_IOBP_Input_Reg(6)(5 downto 0);
+---
+BLM_tst_ck_sig <= blm_clk_100MHz & blm_clk_25MHz & blm_clk_24_9MHz & blm_clk_10MHz & blm_clk_1MHz & blm_clk_100kHz & blm_clk_10kHz & blm_clk_1kHz & blm_clk_9_9MHz & blm_clk_0_99MHz & blm_clk_99kHz;-- & blm_clk_9_9kHz& blm_clk_0_99kHz;
+BLM_wd_reset <= BLM_wd_reset_Reg(3)(5 downto 0)&BLM_wd_reset_Reg(2) & BLM_wd_reset_Reg(1) &BLM_wd_reset_Reg(0);
+
+--for tests
+BLM_deglitcher_data <= Deg66_out;
+
+BLM_Module : Beam_Loss_check 
+
+  generic map (
+
+  WIDTH => 32     -- Counter width
+     
+)
+
+  port map(
+    clk_sys        => clk_sys,    -- Clock
+    rstn_sys       => rstn_sys,     -- Reset
+
+ -- IN BLM 
+  BLM_data_in      => BLM_data_in,--BLM_deglitcher_data(53 downto 0), --BLM_data_in,
+  BLM_gate_in      => BLM_gate_in,
+  BLM_tst_ck_sig   => BLM_tst_ck_sig,
+  IOBP_LED_nr      => IOBP_LED_sm_nr,
+  --IN registers
+  pos_threshold            => pos_thres_Reg,
+  neg_threshold            => neg_thres_Reg,
+  BLM_wdog_hold_time_Reg   => BLM_wdog_hold_time_Reg,
+  BLM_wd_reset => BLM_wd_reset,
+  BLM_gate_hold_time_Reg   => BLM_gate_hold_time_Reg,
+  BLM_ctrl_Reg             => BLM_ctrl_Reg,
+  BLM_gate_seq_prep_ck_sel_Reg  => BLM_gate_seq_prep_ck_sel_Reg,
+  BLM_gate_recover_Reg => BLM_gate_recover_Reg,
+  --BLM_gate_seq_in_ena_Reg  => BLM_gate_seq_in_ena_Reg,
+  BLM_in_sel_Reg           => BLM_in_sel_Reg,
+  BLM_out_sel_reg          => BLM_out_sel_Reg,
+
+  -- OUT register
+  BLM_status_Reg           => BLM_status_Reg,
+    -- OUT BLM
+  BLM_Out                 => BLM_out
+);
+
+
+
+front_board_id_Module: front_board_id 
+port map   
+( clk               => clk_sys,
+nReset            => rstn_sys,
+Deb_Sync          => Deg_Sync66,
+Deb_out           => Deg66_out,
+IOBP_Masken_Reg1  => IOBP_Masken_Reg1,
+IOBP_Masken_Reg2  => IOBP_Masken_Reg2,
+IOBP_Masken_Reg3  => IOBP_Masken_Reg3,
+IOBP_Masken_Reg4  => IOBP_Masken_Reg4,
+IOBP_Masken_Reg5  => IOBP_Masken_Reg5,
+IOBP_Masken_Reg6  => IOBP_Masken_Reg6,
+PIO_SYNC          => PIO_SYNC(142 DOWNTO 20),
+IOBP_ID           => IOBP_ID,
+INTL_Output       =>  BLM_out, --INTL_Output,
+AW_Output_Reg     => AW_Output_Reg(6)(11 downto  6),
+--nBLM_out_ena        => BLM_ctrl_Reg(1), -- 
+AW_IOBP_Input_Reg => AW_IOBP_Input_Reg,
+IOBP_Output       => IOBP_Output,
+IOBP_Input        => IOBP_Input,
+IOBP_Aktiv_LED_i    => IOBP_Aktiv_LED_i,
+OUT_SLOT          => PIO_OUT_SLOT_12,
+ENA_SLOT          => PIO_ENA_SLOT_12, 
+IOBP_Sel_LED      => IOBP_Sel_LED
+
+);
+
+     -------------------------------------------------------------------------------------------------------
+     ------------------------------ Loop für LED_Output's und ID read --------------------------------------
+     -------------------------------------------------------------------------------------------------------
+
+     P_IOBP_LED_ID_Loop_module: IOBP_LED_ID_Module 
+
+      port map (
+              clk_sys           => clk_sys,      
+              rstn_sys          => rstn_sys,    
+             -- Ena_Every_250ns   => Ena_Every_250ns,
+              Ena_Every_500ns => Ena_Every_500ns,
+
+              AW_ID             => AW_ID,
+              IOBP_LED_ID_Bus_i => IOBP_LED_ID_Bus_i,
+              IOBP_Aktiv_LED_o  => IOBP_Aktiv_LED_o,
+              IOBP_Sel_LED      => IOBP_Sel_LED,
+              IOBP_LED_En       => IOBP_LED_En,
+              IOBP_STR_rot_o    => IOBP_STR_rot_o,
+              IOBP_STR_gruen_o  => IOBP_STR_gruen_o,
+              IOBP_STR_ID_o     => IOBP_STR_ID_o,
+              IOBP_LED_ID_Bus_o => IOBP_LED_ID_Bus_o,
+              IOBP_ID           => IOBP_ID,
+              IOBP_LED_state_nr =>  IOBP_LED_sm_nr
+              
+              );
+
+
+
+  --  ###############################################################################################################################
+--  #####                                                                                                                     #####
+--  #####                             Input-Muliplexer to SCU-Bus for the Mirror-Mode                                         #####
+--  #####                                                                                                                     #####
+--  ###############################################################################################################################
+
+P_AW_SCU_In:  process (rstn_sys, clk_sys, Diob_Config1, Mirr_AWOut_Reg_Nr, SCU_AW_Output_Reg)
+
+begin
+  if rstn_sys = '0' then
+
+    SCU_AW_Input_Reg <= (others => (others => '0'));
+
+  elsif rising_edge(clk_sys) then
+
+    IF  (Diob_Config1(3) = '0')  THEN   -- 0 = Default: kein "Mirror-Mode"
+
+    for i in 1 to 7 loop
+      SCU_AW_Input_Reg(i)  <= AW_Input_Reg(i); -- Input's bleiben unverändert
+     end loop; 
+     
+
+    ELSE
+
+    --############################# Mirror-Mode ##################################
+
+      Mirr_AWOut_Reg_Nr      <= to_integer(unsigned(Diob_Config1)( 7 downto 5));      -- Output-Reg. Nr. 1..7
+      Mirr_AWIn_Reg_Nr       <= to_integer(unsigned(Diob_Config1)(10 downto 8));      -- Input-Reg. Nr. 1..7
+
+      For REG_Nr in 1 to 7 loop
+
+        IF REG_Nr = Mirr_AWIn_Reg_Nr THEN  -- Maskierte Bits vom Output-Register "Mirr_AWOut_Reg_Nr" --> Input_Register "Mirr_AWIn_Reg_Nr"
+
+           FOR Bit_Nr in 0 to 15 loop
+                if  (Mirr_OutReg_Maske(Bit_Nr)) = '1' then
+                      SCU_AW_Input_Reg(REG_Nr)(Bit_Nr)   <= SCU_AW_Output_Reg (Mirr_AWOut_Reg_Nr)(Bit_Nr);   -- Copy Output-Bit --> Input-Bit
+                else  SCU_AW_Input_Reg(REG_Nr)(Bit_Nr)   <= AW_Input_Reg(REG_Nr)           (Bit_Nr);   -- Input-Bit bleibt unverändert
+                end if;
+           end loop;
+
+        ELSE
+          FOR Bit_Nr in 0 to 15 loop
+            SCU_AW_Input_Reg(REG_Nr)(Bit_Nr)   <= AW_Input_Reg(REG_Nr)(Bit_Nr);    -- Input-Bit bleibt unverändert
+          end loop;
+        END IF; -- Mirror-Mode
+      end loop;
+
+    END IF;
+  END IF;
+
+  end process P_AW_SCU_In;
+
+
+--  ###############################################################################################################################
+--  ###############################################################################################################################
+--  #####                                                                                                                     #####
+--  #####               PROCESS: IO Signals assignment via JPIO1(150pol.) ==> "Piggy-Type"                    #####
+--  #####                                                                                                                     #####
+--  ###############################################################################################################################
+--  ###############################################################################################################################
+
+AW_B12s1_connection: p_connector 
+
+  port map
+  (
+    Powerup_Done		       => Powerup_Done,
+    signal_tap_clk_250mhz  => signal_tap_clk_250mhz,
+    A_SEL                  => A_SEL,
+    PIO_SYNC		           => PIO_SYNC,
+    CLK_IO                 => CLK_IO,
+    DIOB_Config1           => DIOB_Config1, 
+    AW_Output_Reg          => AW_Output_Reg,
+    UIO_SYNC		           => UIO_SYNC,
+    hp_la_o                => hp_la_o,
+    local_clk_is_running   => local_clk_is_running,
+    clk_blink              => clk_blink,
+    s_nLED_Sel             => s_nLED_Sel,
+    s_nLED_Dtack           => s_nLED_Dtack,
+    s_nLED_inR             => s_nLED_inR,
+    s_nLED_User1_o         => s_nLED_User1_o,
+    s_nLED_User2_o         => s_nLED_User2_o,
+    s_nLED_User3_o         => s_nLED_User3_o,
+    Tag_Sts                => Tag_Sts,
+    Timing_Pattern_LA      => Timing_Pattern_LA,
+    Tag_Aktiv              => Tag_Aktiv,    
+    IOBP_LED_ID_Bus_o      => IOBP_LED_ID_Bus_o,
+    IOBP_ID                => IOBP_ID,
+    IOBP_LED_En            => IOBP_LED_En,
+    IOBP_STR_rot_o         => IOBP_STR_rot_o,
+    IOBP_STR_gruen_o       => IOBP_STR_gruen_o,
+    IOBP_STR_ID_o          => IOBP_STR_ID_o,
+    IOBP_Output            => IOBP_Output,
+    IOBP_Input             => IOBP_Input,
+    Deb66_out              => Deg66_out,
+    AW_IOBP_Input_Reg      => AW_IOBP_Input_Reg,
+    A_TA                   => A_TA,
+    PIO_ENA_SLOT_1         =>  PIO_ENA_SLOT_1,
+    PIO_ENA_SLOT_2          => PIO_ENA_SLOT_2,
+    PIO_ENA_SLOT_3        => PIO_ENA_SLOT_3,
+    PIO_ENA_SLOT_4         => PIO_ENA_SLOT_4,
+    PIO_ENA_SLOT_5        => PIO_ENA_SLOT_5,
+    PIO_ENA_SLOT_6         => PIO_ENA_SLOT_6,
+    PIO_ENA_SLOT_7        => PIO_ENA_SLOT_7,
+    PIO_ENA_SLOT_8         => PIO_ENA_SLOT_8,
+    PIO_ENA_SLOT_9      => PIO_ENA_SLOT_9,
+    PIO_ENA_SLOT_10         => PIO_ENA_SLOT_10,
+    PIO_ENA_SLOT_11         => PIO_ENA_SLOT_11,
+    PIO_ENA_SLOT_12         => PIO_ENA_SLOT_12,
+    PIO_OUT_SLOT_1         =>  PIO_OUT_SLOT_1,
+    PIO_OUT_SLOT_2          => PIO_OUT_SLOT_2,
+    PIO_OUT_SLOT_3        => PIO_OUT_SLOT_3,
+    PIO_OUT_SLOT_4         => PIO_OUT_SLOT_4,
+    PIO_OUT_SLOT_5        => PIO_OUT_SLOT_5,
+    PIO_OUT_SLOT_6         => PIO_OUT_SLOT_6,
+    PIO_OUT_SLOT_7        => PIO_OUT_SLOT_7,
+    PIO_OUT_SLOT_8         => PIO_OUT_SLOT_8,
+    PIO_OUT_SLOT_9      => PIO_OUT_SLOT_9,
+    PIO_OUT_SLOT_10         => PIO_OUT_SLOT_10,
+    PIO_OUT_SLOT_11         => PIO_OUT_SLOT_11,
+    PIO_OUT_SLOT_12         => PIO_OUT_SLOT_12,
+    ------------------------------
+    IOBP_LED_ID_Bus_i      =>  IOBP_LED_ID_Bus_i,
+    PIO_OUT                => PIO_OUT,
+    PIO_ENA                => PIO_ENA,
+    UIO_OUT                => UIO_OUT,
+    UIO_ENA                => UIO_ENA,
+    AW_ID                  => AW_ID,
+    AWIn_Deb_Time          => AWIn_Deb_Time ,
+    Min_AWIn_Deb_Time      => Min_AWIn_Deb_Time,
+    Diob_Status1           => Diob_Status1,
+    DIOB_Status2           => Diob_Status2,
+    IOBP_Id_Reg1           => IOBP_Id_Reg1,
+    IOBP_Id_Reg2           => IOBP_Id_Reg2,
+    IOBP_Id_Reg3           => IOBP_Id_Reg3,
+    IOBP_Id_Reg4           => IOBP_Id_Reg4,
+    IOBP_Id_Reg5           => IOBP_Id_Reg5,
+    IOBP_Id_Reg6           => IOBP_Id_Reg6,
+    IOBP_Id_Reg7           => IOBP_Id_Reg7,
+    IOBP_Id_Reg8           => IOBP_Id_Reg8,
+    Deb66_in               => Deg66_in,
+    Syn66                  => Syn66,
+    AW_Input_Reg           => AW_Input_Reg,
+    A_Tclk                 => A_Tclk,
+    extension_cid_group    => extension_cid_group,
+    extension_cid_system   => extension_cid_system,
+    Max_AWOut_Reg_Nr       => Max_AWOut_Reg_Nr,
+    Max_AWIn_Reg_Nr        => Max_AWIn_Reg_Nr ,
+    Debounce_cnt           => Debounce_cnt ,
+    s_nLED_User1_i         => s_nLED_User1_i,
+    s_nLED_User2_i         => s_nLED_User2_i,
+    s_nLED_User3_i         => s_nLED_User3_i,
+    --IOBP_Output_Readback   =>  BLM_Status_Reg(0),
+    Deb_Sync66             => Deg_Sync66,
+    daq_dat                => daq_dat,
+    daq_diob_ID            => daq_diob_ID
+    
+    );
+
+
+    blm_clk_sig24_9_9_9MHz: blm_24_9_9_9pll 
+    PORT map
+    (
+      areset	=> rstn_sys,
+      inclk0	=> clk_sys,
+
+      c0	=>  blm_clk_24_9MHz,
+      c1		=>  blm_clk_9_9MHz
+    );
+ 
+
+  blm_clk_100MHz <= ENA_every_10ms;
+  blm_clk_10MHz  <= Ena_every_100ns;
+  blm_clk_1MHz   <= Ena_every_1us;
+
+
+  comp_25_Mhz_gen: div_n
+  generic map (n => 4, diag_on => 0)  
+  port map(
+                clk => clk_sys,
+                ena => blm_clk_100MHz,
+                div_o => blm_clk_25MHz
+   );             
+
+
+  comp_0_99_Mhz_gen: div_n
+  generic map (n => 10, diag_on => 0)
+    port map(
+                clk => clk_sys,
+                ena => blm_clk_9_9MHz,
+                div_o => blm_clk_0_99MHz
+     
+  );
+
+
+  comp_100_kHz_gen:  div_n
+  generic map (n => 1000, diag_on => 0) 
+  port map(  
+                clk => clk_sys,
+                ena => blm_clk_100MHz,
+                div_o => blm_clk_100kHz
+  );
+
+
+  comp_99kHz_gen:  div_n
+  generic map (n => 100, diag_on => 0)  
+  port map(
+                clk => clk_sys,
+                ena => blm_clk_9_9MHz,
+                div_o => blm_clk_99kHz
+     
+  );
+
+
+
+  comp_10_kHz_gen:  div_n
+  generic map (n => 1000, diag_on => 0)  
+  port map (
+                clk => clk_sys,
+                ena => blm_clk_100MHz,
+                div_o => blm_clk_10kHz
+  );
+
+
+  comp_1_kHz_gen: div_n
+  generic map (n => 10000, diag_on => 0)  
+  port map(
+                clk => clk_sys,
+                ena => blm_clk_100MHz,
+                div_o =>  blm_clk_1kHz
+  );
+  
+end architecture;
diff --git a/top/blm_aco/front_board_id_v0.vhd b/top/blm_aco/front_board_id_v0.vhd
index c36084683..fd7a4dd83 100644
--- a/top/blm_aco/front_board_id_v0.vhd
+++ b/top/blm_aco/front_board_id_v0.vhd
@@ -25,7 +25,7 @@ Port ( clk : in STD_LOGIC;
        IOBP_ID          : in t_id_array;
        INTL_Output      : in std_logic_vector(5 downto 0);
        AW_Output_Reg    : in std_logic_vector(5 downto 0);
-       nBLM_out_ena      : in std_logic;
+     --  nBLM_out_ena      : in std_logic;
        AW_IOBP_Input_Reg     : out t_IO_Reg_1_to_7_Array;
        IOBP_Output     : out std_logic_vector (5 downto 0);     
        IOBP_Input     : out t_IOBP_array;
@@ -374,12 +374,12 @@ begin
                                                     ------------------------------------------------------------------
                                                     --- AW_Config register assigment to be defined
                                                     ------------------------------------------------------------------
-                                                      if nBLM_out_ena ='0' then -- correct values to be checked
+                                                     -- if nBLM_out_ena ='0' then -- correct values to be checked
 
                                                         IOBP_Out <= INTL_Output;
-                                                      else
-                                                        IOBP_Out <= AW_Output_Reg AND not IOBP_Masken_Reg6(11 downto 6);
-                                                      end if;
+                                                    --  else
+                                                     --   IOBP_Out <= AW_Output_Reg AND not IOBP_Masken_Reg6(11 downto 6);
+                                                    --  end if;
                                                       --------------------------------------------------------------------     
                                                       OUT_SLOT <= not IOBP_Out;                                                  
                                                       --OUT_SLOT <=IOBP_Input(1); --  not IOBP_Out;
diff --git a/top/blm_aco/p_connector.vhd b/top/blm_aco/p_connector.vhd
index 17ced4c92..ec9f8da8b 100644
--- a/top/blm_aco/p_connector.vhd
+++ b/top/blm_aco/p_connector.vhd
@@ -260,7 +260,8 @@ port(
 
     --input: Anwender_ID ---
       AW_ID(7 downto 0)         <=  PIO_SYNC(150 downto 143);
-
+IOBP_Id_Reg7(15 downto 8) <= (others => '0');
+IOBP_Id_Reg7(7 downto 0)  <= AW_ID(7 downto 0);
 
     --  --- Output: Anwender-LED's ---
 
@@ -275,7 +276,7 @@ port(
 
    (PIO_ENA(17), PIO_ENA(19), PIO_ENA(21), PIO_ENA(23),
     PIO_ENA(25), PIO_ENA(27), PIO_ENA(29), PIO_ENA(31) )  <=  std_logic_vector'("11111111"); --  Output-Enable
-
+PIO_ENA(150 downto 143) <= std_logic_vector'("00000000");
 
     A_TA(15 downto 0) <= hp_la_o(15 downto 0); ----------------- Output für HP-Logic-Analysator
 
diff --git a/top/blm_aco/scu_diob_pkg.vhd b/top/blm_aco/scu_diob_pkg.vhd
index 9ac8c4f35..6e05e9a1d 100644
--- a/top/blm_aco/scu_diob_pkg.vhd
+++ b/top/blm_aco/scu_diob_pkg.vhd
@@ -28,7 +28,7 @@ package scu_diob_pkg is
   --TYPE  t_BLM_out_reg_Array    is array (0 to 191) of std_logic_vector(15 downto 0);
     TYPE  t_BLM_out_sel_reg_Array    is array (0 to 126) of std_logic_vector(15 downto 0);
  -- TYPE t_BLM_reg_Array is array (natural range <>) of std_logic_vector(15 downto 0);
-TYPE  t_IO_Reg_0_to_23_Array is array(0 to 23) of std_logic_vector(15 downto 0);
+TYPE  t_IO_Reg_0_to_25_Array is array(0 to 25) of std_logic_vector(15 downto 0);
  TYPE     t_IO_Reg_0_to_27_Array     is array (0 to 27)  of std_logic_vector(15 downto 0);
  TYPE    t_BLM_gate_hold_Time_Array  is array (0 to 11)  of std_logic_vector(15 downto 0);
  TYPE     t_IO_Reg_0_to_15_Array     is array (0 to 15)  of std_logic_vector(15 downto 0);
@@ -38,4 +38,5 @@ TYPE  t_IO_Reg_0_to_23_Array is array(0 to 23) of std_logic_vector(15 downto 0);
  TYPE    t_BLM_in_sel_Array           is array (0 to 15) of std_logic_vector(15 downto 0);
  TYPE    t_BLM_counter_Array           is array (0 to 127) of std_logic_vector(29 downto 0);
  TYPE    t_gate_state_nr is array (0 to 11) of std_logic_vector(2 downto 0);
+ TYPE  t_IO_Reg_0_to_29_Array is array(0 to 29) of std_logic_vector(15 downto 0);
 end scu_diob_pkg;
diff --git a/top/blm_aco/up_down_counter.vhd b/top/blm_aco/up_down_counter.vhd
index ab4667652..24a9241e2 100644
--- a/top/blm_aco/up_down_counter.vhd
+++ b/top/blm_aco/up_down_counter.vhd
@@ -30,10 +30,48 @@ end up_down_counter;
 architecture rtl of up_down_counter is
 
  
-  signal int_count, int_n_count,int_p_count: integer:=0;
+  signal int_count: integer:=0;
+  
+--  signal int_n_count,int_p_count: integer:=0;
     signal up_OVERFLOW_FLAG: std_logic;
     signal  down_OVERFLOW_FLAG:std_logic;
+signal up_input, down_input: std_logic;
+signal up_sig, down_sig: std_logic;
+signal res_cnt : integer :=0;
+
+    component BLM_ct_pulse_former is
+
+        port (
+            CLK         : in std_logic;      -- Clock
+            nRST         : in std_logic;      -- Reset
+            SIG_IN       : in std_logic;    -- Load counter register up input
+            SIG_OUT    : out std_logic     -- UP_Counter overflow
+        
+        );
+        end component BLM_ct_pulse_former;
 begin
+
+
+
+    Pulse_enable_UP: BLM_ct_pulse_former 
+
+        port map(
+            CLK       => CLK,    -- Clock
+            nRST       => nRST,      -- Reset
+            SIG_IN    => up_sig,
+            SIG_OUT   => up_input
+        );
+
+    Pulse_enable_DOWN: BLM_ct_pulse_former 
+
+        port map(
+            CLK       => CLK,    -- Clock
+            nRST       => nRST,      -- Reset
+            SIG_IN    => down_sig,
+            SIG_OUT   => DOWN_input
+        );
+
+
     -- Counter process
     COUNT_SHIFT: process (nRST, CLK)
     begin
@@ -43,51 +81,54 @@ begin
             up_OVERFLOW_FLAG <='0';
             down_OVERFLOW_FLAG <='0';
             int_count <=0;
-            int_n_count <=0;
-            int_p_count <=0;
+            res_cnt <= 0;
             
         elsif (CLK'event and CLK='1') then
+            res_cnt <= int_count;
         
             if (CLEAR = '1') then
 
                 int_count <= 0;
-                int_n_count <=0;
-                int_p_count <=0;
+       
                 up_OVERFLOW_FLAG <='0';
                 down_OVERFLOW_FLAG <='0';
 
             elsif ( ENABLE = '1') then   
        
 ----------------------------
-            if UP_IN ='1' then 
-                int_p_count <= int_p_count +1;
-            end if;
+            if up_input ='1' then 
+
+                int_count <= int_count +1;
+
+            elsif down_input ='1' then
     
-            if DOWN_IN ='1' then
-                int_n_count <= int_n_count -1;
-            end if;
+                int_count <= int_count -1;
 
-            int_count <= int_p_count + int_n_count;
+            end if;
     
-        
-            if int_count = pos_threshold then         -- pos_threshold reached
+        end if;
+
+-- comparation to threshold out from the enable ='1' condition
+
+            if res_cnt > pos_threshold then         -- pos_threshold reached
 
                 up_OVERFLOW_FLAG <='1';
 
-            elsif int_count = neg_threshold then  -- neg_threshold reached
+            elsif res_cnt < neg_threshold then  -- neg_threshold reached
 
                 down_OVERFLOW_FLAG <='1';                 
 
             end if;
 
-        end if;
+      --  end if;
     end if;
 end process;
 -----------------------------
 UP_OVERFLOW <= up_OVERFLOW_FLAG;
 DOWN_OVERFLOW <= down_OVERFLOW_FLAG;
 cnt_val <=  std_logic_vector(to_signed(int_count, WIDTH));
-
+up_sig <= UP_IN;
+down_sig <= DOWN_IN;
 
 end rtl;
 

From cd249e59df7c03d75d0464739692653f4e2029c7 Mon Sep 17 00:00:00 2001
From: Antonietta Russo <a.russo@gsi.de>
Date: Fri, 19 Jul 2024 10:09:40 +0200
Subject: [PATCH 7/8] BLM ACO latest version

---
 top/blm_aco/BLM_out_el_m.vhd         | 41 +++++++++++++++++-------
 top/blm_aco/Beam_Loss_check_v1.1.vhd | 12 ++++---
 top/blm_aco/IOBP_LED_ID_Module.vhd   | 21 +++++++-----
 top/blm_aco/blm_aco.vhd              | 48 ++++++++++++++++++++++++----
 4 files changed, 91 insertions(+), 31 deletions(-)

diff --git a/top/blm_aco/BLM_out_el_m.vhd b/top/blm_aco/BLM_out_el_m.vhd
index 35ed33294..9c7c45df7 100644
--- a/top/blm_aco/BLM_out_el_m.vhd
+++ b/top/blm_aco/BLM_out_el_m.vhd
@@ -22,11 +22,12 @@ port (
 
   wd_out           : in std_logic_vector(53 downto 0);  -- wd_error
   gate_in          : in std_logic_vector(11 downto 0); -- to be sent to the status registers
+  gate_error       : in std_logic_vector(11 downto 0); -- to be sent to the status registers
   gate_out        : in std_logic_vector (11 downto 0); --gate error
   counter_reg: in t_BLM_counter_Array;
  
   BLM_Output      : out std_logic_vector(5 downto 0);
-  BLM_status_Reg : out t_IO_Reg_0_to_23_Array 
+  BLM_status_Reg : out t_IO_Reg_0_to_25_Array 
 
   );
 
@@ -59,12 +60,20 @@ signal read_cnt: t_cnt:= (others => 0);
 signal read_counters: integer range 0 to 127;
 
 signal ena_out: std_logic_vector(5 downto 0);
+signal gate_output : std_logic_vector(11 downto 0);
+signal gate_error_output: std_logic_vector(11 downto 0);
+signal wd_output: std_logic_vector(53 downto 0);
+signal gate_input : std_logic_vector(11 downto 0);
 
 begin
 
 
-OVERFLOW <= gate_in& wd_out& gate_out & UP_OVERFLOW & DOWN_OVERFLOW;
+OVERFLOW <= gate_in& wd_out& gate_error & UP_OVERFLOW & DOWN_OVERFLOW;
 --gate_input <= gate_in;
+gate_output <= gate_out;
+gate_error_output <=gate_error;
+wd_output <= wd_out;
+gate_input <= gate_in;
 
 sel_signal_proc: process (BLM_out_sel_Reg)
 
@@ -160,19 +169,29 @@ end process;
      --------------------------------------------------------------------------------------------------
      status_reg_overflow_proc: process (OVERFLOW)
      begin
-        for i in 0 to 19 loop
+        for i in 0 to 15 loop
          --   BLM_status_reg(i) <= not OVERFLOW((i*16+15) downto i*16); 
             BLM_status_reg(i) <=  OVERFLOW((i*16+15) downto i*16);
         end loop;
     end process;
-    
-    --BLM_status_reg(20) <= "00" & not OVERFLOW(333 downto 320); -- bits 333-321 gate inputs, bits 321-320 = wd_out (53 downto 52)
-   -- BLM_status_reg(21)(5 downto 0) <= not BLM_out_signal; -- physical outputs
-    BLM_status_reg(20) <= "00" & OVERFLOW(333 downto 320); -- bits 333-321 gate inputs, bits 321-320 = wd_out (53 downto 52)
-    BLM_status_reg(21)(5 downto 0) <= BLM_out_signal; -- physical outputs
-    BLM_status_reg(21)(15 downto 6)  <= (others =>'0');    
-    BLM_status_reg(22)<= cnt_readback(15 downto 0);
-    BLM_status_reg(23) <= "00"& cnt_readback(29 downto 16);
+    BLM_status_reg(16) <= "0000"& gate_error_output;
+    BLM_status_reg(17) <= wd_output(15 downto 0);
+    BLM_status_reg(18) <= wd_output(31 downto 16);
+    BLM_status_reg(19) <= wd_output(47 downto 32);
+    BLM_status_reg(20) <= "0000000000" & wd_output(53 downto 48);
+    BLM_status_reg(21) <= cnt_readback(15 downto 0);
+    BLM_status_reg(22) <= "00" & cnt_readback(29 downto 16);
+    BLM_status_reg(23) <= "0000" & gate_input;
+    BLM_status_reg(24) <= "0000" & gate_output;
+    BLM_status_reg(25) <= "0000000000" & BLM_out_signal; 
+  --  --BLM_status_reg(20) <= "00" & not OVERFLOW(333 downto 320); -- bits 333-321 gate inputs, bits 321-320 = wd_out (53 downto 52)
+ --  -- BLM_status_reg(21)(5 downto 0) <= not BLM_out_signal; -- physical outputs
+ --   BLM_status_reg(20) <= "00" & OVERFLOW(333 downto 320); -- bits 333-321 gate inputs, bits 321-320 = wd_out (53 downto 52)
+ --   BLM_status_reg(21)(5 downto 0) <= BLM_out_signal; -- physical outputs
+ --   BLM_status_reg(21)(15 downto 6)  <= cnt_readback(9 downto 0);    
+ --   BLM_status_reg(22)<= cnt_readback(25 downto 10);
+ --   BLM_status_reg(23) <= gate_output& cnt_readback(29 downto 26);
+  
 
 
  BLM_Output <= BLM_out_signal;
diff --git a/top/blm_aco/Beam_Loss_check_v1.1.vhd b/top/blm_aco/Beam_Loss_check_v1.1.vhd
index 4d569f93a..d8ec53536 100644
--- a/top/blm_aco/Beam_Loss_check_v1.1.vhd
+++ b/top/blm_aco/Beam_Loss_check_v1.1.vhd
@@ -44,7 +44,7 @@ port (
                                                    --=> 126 registers             
                                                     --   REg127  (ex Reg121): counter outputs buffering enable (bit 15) and buffered output select (bit 7-0). Bits 14-8 not used     
     -- OUT register
-    BLM_status_Reg    : out t_IO_Reg_0_to_23_Array ;
+    BLM_status_Reg    : out t_IO_Reg_0_to_25_Array ;
 
       -- OUT BLM
       BLM_Out           : out std_logic_vector(5 downto 0) 
@@ -175,12 +175,13 @@ component BLM_gate_timing_seq is
         
         wd_out           : in std_logic_vector(53 downto 0); 
         gate_in          : in std_logic_vector(11 downto 0); -- to be sent to the status registers
+        gate_error        : in std_logic_vector (11 downto 0); 
         gate_out        : in std_logic_vector (11 downto 0); 
         counter_reg: in t_BLM_counter_Array;
       
 
         BLM_Output      : out std_logic_vector(5 downto 0);
-        BLM_status_Reg : out t_IO_Reg_0_to_23_Array 
+        BLM_status_Reg : out t_IO_Reg_0_to_25_Array 
         
         );
      
@@ -193,8 +194,8 @@ begin
 
 VALUE_IN <= BLM_test_signal & BLM_data_in;
 BLM_gate_recover <= BLM_gate_recover_Reg(11 downto 0);
-BLM_gate_prepare <= BLM_gate_seq_prep_ck_sel_Reg(14 downto 3);
-BLM_gate_seq_clk_sel <= BLM_gate_seq_prep_ck_sel_Reg(2 downto 0);
+BLM_gate_prepare <= BLM_gate_seq_prep_ck_sel_Reg(11 downto 0);
+--BLM_gate_seq_clk_sel <= BLM_gate_seq_prep_ck_sel_Reg(2 downto 0);
 
  -- gate_timing_clock_sel_proc: process( BLM_gate_seq_clk_sel)
  --   begin
@@ -393,7 +394,8 @@ BLM_out_section: BLM_out_el
    DOWN_OVERFLOW   => DOWN_OVERFLOW,
     wd_out           => out_1wd, --out_wd, --out_1wd,
     gate_in         => BLM_gate_in(5 downto 0) & BLM_gate_in(11 downto 6),--BLM_gate_in,
-    gate_out        => gate_error(5 downto 0) & gate_error(11 downto 6),
+    gate_error        => gate_error(5 downto 0) & gate_error(11 downto 6),
+    gate_out        => gate_output(5 downto 0) & gate_output(11 downto 6),
     BLM_Output      => BLM_out,
     counter_reg =>  counter_value,   
     BLM_status_Reg  => BLM_status_Reg 
diff --git a/top/blm_aco/IOBP_LED_ID_Module.vhd b/top/blm_aco/IOBP_LED_ID_Module.vhd
index 5753e7d7b..308db9913 100644
--- a/top/blm_aco/IOBP_LED_ID_Module.vhd
+++ b/top/blm_aco/IOBP_LED_ID_Module.vhd
@@ -8,7 +8,8 @@ entity IOBP_LED_ID_Module is
 port (
         clk_sys           : in  std_logic;      
         rstn_sys          : in  std_logic;      
-        Ena_Every_250ns   : in  std_logic; 
+    --    Ena_Every_250ns   : in  std_logic; 
+    Ena_Every_500ns       : in std_logic;
         AW_ID             : in  std_logic_vector(7 downto 0); -- Application_ID
         IOBP_LED_ID_Bus_i : in  std_logic_vector(7 downto 0);   -- LED_ID_Bus_In
         IOBP_Aktiv_LED_o  : in  t_led_array;    -- Active LEDs of the "Slave-Boards"
@@ -27,13 +28,14 @@ architecture rtl of IOBP_LED_ID_Module is
 
 signal Slave_Loop_cnt:      integer range 0 to 12;         -- 1-12   -- Loop-Counter
 
-type   IOBP_LED_state_t is   (IOBP_idle, led_id_wait, led_id_loop, led_str_rot_h, led_str_rot_l, led_gruen,
+type   IOBP_LED_state_t is   (IOBP_START_DEL, IOBP_idle, led_id_wait, led_id_loop, led_str_rot_h, led_str_rot_l, led_gruen,
                               led_str_gruen_h, led_str_gruen_l, iobp_led_dis, iobp_led_z, iobp_id_str_h, iobp_rd_id, iobp_id_str_l, iobp_end);
-signal IOBP_state:   IOBP_LED_state_t:= IOBP_idle;
-        
+--signal IOBP_state:   IOBP_LED_state_t:= IOBP_idle;
+signal IOBP_state:   IOBP_LED_state_t:= IOBP_START_DEL;        
 begin
 
-P_IOBP_LED_ID_Loop:  process (clk_sys, Ena_Every_250ns, rstn_sys, IOBP_state)
+--P_IOBP_LED_ID_Loop:  process (clk_sys, Ena_Every_250ns, rstn_sys, IOBP_state)
+P_IOBP_LED_ID_Loop:  process (clk_sys, Ena_Every_500ns, rstn_sys, IOBP_state)
 
     begin
       if (not rstn_sys = '1') then
@@ -42,11 +44,14 @@ P_IOBP_LED_ID_Loop:  process (clk_sys, Ena_Every_250ns, rstn_sys, IOBP_state)
         IOBP_STR_rot_o       <=  (others => '0');    --  Led-Strobs 'red'
         IOBP_STR_gruen_o     <=  (others => '0');    --  Led-Strobs 'green'
         IOBP_STR_id_o        <=  (others => '0');    --  ID-Strobs
+        IOBP_state           <=  IOBP_START_DEL;
 
-
-    ELSIF (clk_sys'EVENT AND clk_sys = '1' AND Ena_Every_250ns = '1') THEN
+        ELSIF (clk_sys'EVENT AND clk_sys = '1' AND Ena_Every_500ns = '1') THEN
+   -- ELSIF (clk_sys'EVENT AND clk_sys = '1' AND Ena_Every_250ns = '1') THEN
 --  ELSIF ((rising_edge(clk_sys)) or Ena_Every_100ns)  then
       case IOBP_state is
+        when IOBP_START_DEL => IOBP_state  <= IOBP_idle;
+
         when IOBP_idle   =>  Slave_Loop_cnt       <=  1;                 -- Loop-Counter
 
                             if  (AW_ID(7 downto 0) = "00010011") THEN  IOBP_state  <= led_id_wait; -- AW_ID(7 downto 0) = c_AW_INLB12S1.ID
@@ -98,7 +103,7 @@ P_IOBP_LED_ID_Loop:  process (clk_sys, Ena_Every_250ns, rstn_sys, IOBP_state)
                                     IOBP_state     <= IOBP_idle;
                                   end if;
 
-        when others           =>  IOBP_state       <= IOBP_idle;
+        when others           =>  IOBP_state       <= IOBP_START_DEL;
 
       end case;
     end if;
diff --git a/top/blm_aco/blm_aco.vhd b/top/blm_aco/blm_aco.vhd
index ec3e42cfa..3eb395a7f 100755
--- a/top/blm_aco/blm_aco.vhd
+++ b/top/blm_aco/blm_aco.vhd
@@ -466,7 +466,7 @@ port (
                                                     --=> 126 registers             
                                                     --   REg127             ex Reg121: counter outputs buffering enable (bit 15) and buffered output select (bit 7-0). Bits 14-8 not used     
     -- OUT register
-    BLM_status_Reg    : out t_IO_Reg_0_to_23_Array ;
+    BLM_status_Reg    : out t_IO_Reg_0_to_25_Array ;
 
       -- OUT BLM
       BLM_Out           : out std_logic_vector(5 downto 0) 
@@ -856,7 +856,7 @@ end component aw_io_reg;
   signal IOBP_msk_rd_active:      std_logic;
   signal IOBP_msk_Dtack:          std_logic;
   signal IOBP_msk_data_to_SCUB:   std_logic_vector(15 downto 0);
- signal BLM_Status_Reg:    t_IO_Reg_0_to_23_Array ;
+ signal BLM_Status_Reg:    t_IO_Reg_0_to_25_Array ;
 
 signal IOBP_Output: std_logic_vector(5 downto 0);     -- Outputs "Slave-Karten 1-12"  --but I use only 1-2-3 respectiverly for slot 10-11-12
 
@@ -872,9 +872,9 @@ signal IOBP_Input:  t_IOBP_array;    -- Inputs "Slave-Karten 1-12"
   signal IOBP_id_rd_active:       std_logic;
   signal IOBP_id_Dtack:           std_logic;
   signal IOBP_id_data_to_SCUB:    std_logic_vector(15 downto 0);
-  signal IOBP_in_data_to_SCUB:    t_IO_Reg_0_to_2_Array;
-  signal IOBP_in_rd_active:       std_logic_vector(2 downto 0);
-  signal IOBP_in_Dtack:            std_logic_vector(2 downto 0);
+  signal IOBP_in_data_to_SCUB:    t_IO_Reg_0_to_3_Array;
+  signal IOBP_in_rd_active:       std_logic_vector(3 downto 0);
+  signal IOBP_in_Dtack:            std_logic_vector(3 downto 0);
   signal IOBP_in_res_Dtack: std_logic;
   signal IOBP_Sel_LED:      t_led_array;    -- Sel-LED's der "Slave-Karten"
   signal IOBP_ID:           t_id_array;     -- IDs of the "Slave-Boards"
@@ -1444,6 +1444,40 @@ BLM_status_registers_0_23:for i in 0 to 2 generate
         );
     end generate BLM_status_registers_0_23;
 
+     
+
+
+        BLM_Status_READBACK_Reg_24_25: in_reg
+        generic map(
+              Base_addr =>  c_Status_READBACK_Base_Addr +24
+              )
+        port map  (
+              Adr_from_SCUB_LA   =>  ADR_from_SCUB_LA,
+              Data_from_SCUB_LA  =>  Data_from_SCUB_LA,
+              Ext_Adr_Val        =>  Ext_Adr_Val,
+              Ext_Rd_active      =>  Ext_Rd_active,
+              Ext_Rd_fin         =>  Ext_Rd_fin,
+              Ext_Wr_active      =>  Ext_Wr_active,
+              Ext_Wr_fin         =>  SCU_Ext_Wr_fin,
+              clk                =>  clk_sys,
+              nReset             =>  rstn_sys,
+        --
+              Reg_In1            =>  BLM_Status_Reg(24),
+              Reg_In2            =>  BLM_Status_Reg(24+1),
+              Reg_In3            =>  (others =>'0'),
+              Reg_In4            =>  (others =>'0'),
+              Reg_In5            =>  (others =>'0'),
+              Reg_In6            =>  (others =>'0'),
+              Reg_In7            =>  (others =>'0'),
+              Reg_In8            =>  (others =>'0'),
+    
+        --
+              Reg_rd_active      =>  IOBP_in_rd_active(3),
+              Dtack_to_SCUB      =>  IOBP_in_Dtack(3),
+              Data_to_SCUB       =>  IOBP_in_data_to_SCUB(3)
+            );
+     
+    
 
 threshold_registers: for i in 0 to 63 generate
 
@@ -1975,7 +2009,7 @@ rd_port_mux:  process ( clk_switch_rd_active,     clk_switch_rd_data,
   variable sel: unsigned(11 downto 0);
   variable sel_th: unsigned(63 downto 0);
   variable sel_in_sel: unsigned(15 downto 0);
-  variable sel_st: unsigned(2 downto 0);
+  variable sel_st: unsigned(3 downto 0);
   variable sel_out_sel: unsigned(15 downto 0); 
 
   begin
@@ -2023,7 +2057,7 @@ else
            end loop;
            else
            if to_integer(sel_st) > 0 then  
-           for i in 0 to 2 loop
+           for i in 0 to 3 loop
              if sel_st(i) = '1' then 
                 Data_to_SCUB <= IOBP_in_data_to_SCUB(i);
              end if;

From 00cf0bb51c6429d7bbb71ae47f59920cb4572871 Mon Sep 17 00:00:00 2001
From: Antonietta Russo <a.russo@gsi.de>
Date: Fri, 19 Jul 2024 10:17:25 +0200
Subject: [PATCH 8/8] updated the quartus setting file

---
 syn/blm_aco/blm_aco.qsf | 1809 ++++++++++++++++++++-------------------
 1 file changed, 934 insertions(+), 875 deletions(-)

diff --git a/syn/blm_aco/blm_aco.qsf b/syn/blm_aco/blm_aco.qsf
index 38a072584..e5c9ad505 100644
--- a/syn/blm_aco/blm_aco.qsf
+++ b/syn/blm_aco/blm_aco.qsf
@@ -188,6 +188,57 @@
 
 
 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+set_global_assignment -name AHDL_FILE ../../modules/modulbus/i2c.tdf
 set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH
 set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name DEVICE ep2agx125df25c5
@@ -215,915 +266,923 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:blm_aco.tcl"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:30:14 FEBRUARY 14, 2013"
+set_global_assignment -name QIP_FILE "../../ip_cores/general-cores/platform/altera/networks/arria2gx_networks.qip"
+set_global_assignment -name QIP_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/arria2_pcie.qip"
+set_global_assignment -name QIP_FILE "../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/wr_arria2_phy.qip"
+set_global_assignment -name QIP_FILE ../../modules/ddr3/arria2/arria2_ddr3.qip
+set_global_assignment -name QIP_FILE ../../modules/pll/arria2/arria2_pll.qip
+set_global_assignment -name QIP_FILE ../../modules/pll/arria2/dmtd_pll.qip
+set_global_assignment -name QIP_FILE ../../modules/pll/arria2/ref_pll.qip
+set_global_assignment -name QIP_FILE ../../modules/pll/arria2/sys_pll.qip
+set_global_assignment -name SDC_FILE ../../top/blm_aco/scu_diob.sdc
 set_global_assignment -name SEED 2
 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
 set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCS128
 set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "ACTIVE SERIAL"
 set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
+set_global_assignment -name TOP_LEVEL_ENTITY blm_aco
 set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-set_location_assignment PIN_A11 -to A_TA[10]
-set_location_assignment PIN_A12 -to A_TA[6]
-set_location_assignment PIN_A13 -to A_TA[0]
-set_location_assignment PIN_A14 -to A_TA[3]
-set_location_assignment PIN_A15 -to A_TA[9]
-set_location_assignment PIN_A16 -to UIO[2]
-set_location_assignment PIN_A17 -to UIO[3]
-set_location_assignment PIN_A18 -to UIO[4]
-set_location_assignment PIN_A19 -to UIO[15]
-set_location_assignment PIN_A20 -to UIO[10]
-set_location_assignment PIN_A2 -to PIO[16]
-set_location_assignment PIN_A3 -to PIO[49]
-set_location_assignment PIN_A5 -to PIO[41]
-set_location_assignment PIN_AA10 -to A_A[4]
-set_location_assignment PIN_AA11 -to A_A[15]
-set_location_assignment PIN_AA12 -to A_A[6]
-set_location_assignment PIN_AA14 -to A_D[7]
-set_location_assignment PIN_AA15 -to A_SPARE0
-set_location_assignment PIN_AA16 -to A_NDTACK
-set_location_assignment PIN_AA18 -to A_NSEL_EXT_DATA_DRV
-set_location_assignment PIN_AA1 -to PIO[103]
-set_location_assignment PIN_AA3 -to PIO[107]
-set_location_assignment PIN_AA4 -to PIO[109]
-set_location_assignment PIN_AA5 -to PIO[142]
-set_location_assignment PIN_AA6 -to A_A[8]
-set_location_assignment PIN_AA7 -to A_A[10]
-set_location_assignment PIN_AA8 -to A_A[11]
-set_location_assignment PIN_AA9 -to A_A[3]
-set_location_assignment PIN_AB10 -to PIO[122]
-set_location_assignment PIN_AB11 -to PIO[136]
-set_location_assignment PIN_AB12 -to PIO[145]
-set_location_assignment PIN_AB13 -to PIO[149]
-set_location_assignment PIN_AB14 -to A_D[12]
-set_location_assignment PIN_AB15 -to A_D[2]
-set_location_assignment PIN_AB16 -to A_D[6]
-set_location_assignment PIN_AB17 -to A_ONEWIRE
-set_location_assignment PIN_AB18 -to A_NBOARDSEL
-set_location_assignment PIN_AB19 -to A_RNW
-set_location_assignment PIN_AB1 -to PIO[128]
-set_location_assignment PIN_AB20 -to A_NADR_EN
-set_location_assignment PIN_AB21 -to A_NSRQ
-set_location_assignment PIN_AB2 -to PIO[130]
-set_location_assignment PIN_AB3 -to PIO[133]
-set_location_assignment PIN_AB4 -to PIO[140]
-set_location_assignment PIN_AB5 -to PIO[139]
-set_location_assignment PIN_AB6 -to A_A[9]
-set_location_assignment PIN_AB7 -to A_A[0]
-set_location_assignment PIN_AB8 -to A_A[2]
-set_location_assignment PIN_AB9 -to A_A[13]
-set_location_assignment PIN_AC12 -to PIO[143]
-set_location_assignment PIN_AC13 -to PIO[147]
-set_location_assignment PIN_AC15 -to A_D[4]
-set_location_assignment PIN_AC18 -to A_NSEL_EXT_SIGNAL_DRV
-set_location_assignment PIN_AC19 -to A_D[11]
-set_location_assignment PIN_AC1 -to PIO[123]
-set_location_assignment PIN_AC3 -to PIO[108]
-set_location_assignment PIN_AC4 -to PIO[127]
-set_location_assignment PIN_AC6 -to PIO[146]
-set_location_assignment PIN_AC9 -to A_A[12]
-set_location_assignment PIN_AD10 -to PIO[126]
-set_location_assignment PIN_AD11 -to PIO[138]
-set_location_assignment PIN_AD12 -to A_A[7]
-set_location_assignment PIN_AD13 -to CLK_20MHZ_D
-set_location_assignment PIN_AD15 -to A_D[3]
-set_location_assignment PIN_AD16 -to A_D[5]
-set_location_assignment PIN_AD17 -to A_D[8]
-set_location_assignment PIN_AD18 -to A_D[9]
-set_location_assignment PIN_AD19 -to A_D[10]
-set_location_assignment PIN_AD20 -to A_NRESET
-set_location_assignment PIN_AD21 -to A_NADR_FROM_SCUB
-set_location_assignment PIN_AD2 -to PIO[131]
-set_location_assignment PIN_AD3 -to PIO[135]
-set_location_assignment PIN_AD4 -to PIO[137]
-set_location_assignment PIN_AD5 -to PIO[141]
-set_location_assignment PIN_AD6 -to PIO[144]
-set_location_assignment PIN_AD7 -to A_A[1]
-set_location_assignment PIN_AD8 -to PIO[150]
-set_location_assignment PIN_AD9 -to PIO[124]
-set_location_assignment PIN_B10 -to PIO[45]
-set_location_assignment PIN_B12 -to A_TA[12]
-set_location_assignment PIN_B13 -to A_TA[4]
-set_location_assignment PIN_B15 -to A_TA[7]
-set_location_assignment PIN_B16 -to UIO[5]
-set_location_assignment PIN_B18 -to UIO[11]
-set_location_assignment PIN_B19 -to A_SEL[1]
-set_location_assignment PIN_B1 -to PIO[28]
-set_location_assignment PIN_B3 -to PIO[26]
-set_location_assignment PIN_B4 -to PIO[21]
-set_location_assignment PIN_B6 -to PIO[27]
-set_location_assignment PIN_B7 -to PIO[29]
-set_location_assignment PIN_B9 -to PIO[47]
-set_location_assignment PIN_C12 -to A_TA[14]
-set_location_assignment PIN_C13 -to A_TA[13]
-set_location_assignment PIN_C15 -to A_TA[2]
-set_location_assignment PIN_C16 -to A_TA[11]
-set_location_assignment PIN_C18 -to A_TCLK
-set_location_assignment PIN_C19 -to UIO[6]
-set_location_assignment PIN_C1 -to PIO[40]
-set_location_assignment PIN_C20 -to A_SEL[3]
-set_location_assignment PIN_C2 -to PIO[43]
-set_location_assignment PIN_C3 -to PIO[38]
-set_location_assignment PIN_C7 -to PIO[33]
-set_location_assignment PIN_D10 -to PIO[31]
-set_location_assignment PIN_D11 -to CLK_20MHZ_A
-set_location_assignment PIN_D12 -to UIO[0]
-set_location_assignment PIN_D13 -to UIO[1]
-set_location_assignment PIN_D14 -to A_TA[1]
-set_location_assignment PIN_D15 -to A_TA[15]
-set_location_assignment PIN_D1 -to PIO[39]
-set_location_assignment PIN_D2 -to PIO[52]
-set_location_assignment PIN_D3 -to PIO[18]
-set_location_assignment PIN_D4 -to PIO[50]
-set_location_assignment PIN_D7 -to A_NLED_D3
-set_location_assignment PIN_D8 -to PIO[23]
-set_location_assignment PIN_D9 -to PIO[19]
-set_location_assignment PIN_E12 -to UIO[7]
-set_location_assignment PIN_E13 -to UIO[8]
-set_location_assignment PIN_E15 -to UIO[13]
-set_location_assignment PIN_E16 -to A_SEL[2]
-set_location_assignment PIN_E1 -to PIO[20]
-set_location_assignment PIN_E3 -to PIO[22]
-set_location_assignment PIN_E4 -to PIO[35]
-set_location_assignment PIN_E7 -to A_NLED_D2
-set_location_assignment PIN_F10 -to PIO[78]
-set_location_assignment PIN_F12 -to CLK_IO
-set_location_assignment PIN_F13 -to A_TA[5]
-set_location_assignment PIN_F14 -to UIO[12]
-set_location_assignment PIN_F15 -to UIO[14]
-set_location_assignment PIN_F1 -to PIO[30]
-set_location_assignment PIN_F3 -to PIO[48]
-set_location_assignment PIN_F4 -to PIO[25]
-set_location_assignment PIN_F7 -to PIO[24]
-set_location_assignment PIN_F8 -to PIO[66]
-set_location_assignment PIN_F9 -to PIO[68]
-set_location_assignment PIN_G10 -to PIO[80]
-set_location_assignment PIN_G13 -to A_TA[8]
-set_location_assignment PIN_G14 -to UIO[9]
-set_location_assignment PIN_G16 -to A_SEL[0]
-set_location_assignment PIN_G1 -to PIO[42]
-set_location_assignment PIN_G2 -to PIO[32]
-set_location_assignment PIN_G3 -to PIO[62]
-set_location_assignment PIN_G4 -to PIO[55]
-set_location_assignment PIN_G5 -to PIO[37]
-set_location_assignment PIN_G6 -to PIO[17]
-set_location_assignment PIN_G7 -to PIO[34]
-set_location_assignment PIN_H16 -to A_NUSER_EN
-set_location_assignment PIN_H1 -to PIO[44]
-set_location_assignment PIN_H3 -to PIO[51]
-set_location_assignment PIN_H4 -to PIO[58]
-set_location_assignment PIN_H6 -to PIO[54]
-set_location_assignment PIN_H7 -to PIO[36]
-set_location_assignment PIN_J1 -to PIO[56]
-set_location_assignment PIN_J3 -to PIO[64]
-set_location_assignment PIN_J4 -to PIO[60]
-set_location_assignment PIN_J5 -to PIO[46]
-set_location_assignment PIN_J6 -to PIO[53]
-set_location_assignment PIN_K1 -to PIO[63]
-set_location_assignment PIN_K2 -to PIO[59]
-set_location_assignment PIN_K3 -to PIO[71]
-set_location_assignment PIN_K4 -to PIO[67]
-set_location_assignment PIN_K5 -to PIO[57]
-set_location_assignment PIN_L1 -to PIO[75]
-set_location_assignment PIN_L3 -to PIO[74]
-set_location_assignment PIN_L4 -to PIO[70]
-set_location_assignment PIN_L7 -to PIO[61]
-set_location_assignment PIN_M1 -to PIO[83]
-set_location_assignment PIN_M3 -to PIO[72]
-set_location_assignment PIN_M4 -to PIO[79]
-set_location_assignment PIN_M7 -to PIO[65]
-set_location_assignment PIN_N1 -to PIO[73]
-set_location_assignment PIN_N2 -to PIO[77]
-set_location_assignment PIN_N4 -to CLK_20MHZ_B
-set_location_assignment PIN_N6 -to PIO[82]
-set_location_assignment PIN_N7 -to PIO[69]
-set_location_assignment PIN_P1 -to PIO[76]
-set_location_assignment PIN_P4 -to CLK_20MHZ_C
-set_location_assignment PIN_P7 -to PIO[84]
-set_location_assignment PIN_R1 -to PIO[91]
-set_location_assignment PIN_R3 -to PIO[86]
-set_location_assignment PIN_R4 -to PIO[81]
-set_location_assignment PIN_R5 -to PIO[94]
-set_location_assignment PIN_R6 -to PIO[85]
-set_location_assignment PIN_R7 -to PIO[117]
-set_location_assignment PIN_T1 -to PIO[89]
-set_location_assignment PIN_T2 -to PIO[87]
-set_location_assignment PIN_T3 -to PIO[95]
-set_location_assignment PIN_T4 -to PIO[88]
-set_location_assignment PIN_T5 -to PIO[93]
-set_location_assignment PIN_T6 -to PIO[97]
-set_location_assignment PIN_U16 -to A_EXT_DATA_RD
-set_location_assignment PIN_U1 -to PIO[96]
-set_location_assignment PIN_U3 -to PIO[98]
-set_location_assignment PIN_U4 -to PIO[100]
-set_location_assignment PIN_U6 -to PIO[115]
-set_location_assignment PIN_U9 -to PIO[119]
-set_location_assignment PIN_V11 -to PIO[125]
-set_location_assignment PIN_V12 -to PIO[132]
-set_location_assignment PIN_V13 -to A_D[0]
-set_location_assignment PIN_V14 -to A_D[14]
-set_location_assignment PIN_V15 -to A_NDS
-set_location_assignment PIN_V16 -to A_NEVENT_STR
-set_location_assignment PIN_V1 -to PIO[92]
-set_location_assignment PIN_V3 -to PIO[90]
-set_location_assignment PIN_V4 -to PIO[114]
-set_location_assignment PIN_V5 -to PIO[99]
-set_location_assignment PIN_V6 -to PIO[116]
-set_location_assignment PIN_V7 -to PIO[148]
-set_location_assignment PIN_V9 -to A_A[14]
-set_location_assignment PIN_W10 -to PIO[121]
-set_location_assignment PIN_W11 -to A_A[5]
-set_location_assignment PIN_W12 -to PIO[134]
-set_location_assignment PIN_W13 -to A_D[13]
-set_location_assignment PIN_W14 -to A_D[1]
-set_location_assignment PIN_W16 -to A_SPARE1
-set_location_assignment PIN_W1 -to PIO[106]
-set_location_assignment PIN_W2 -to PIO[105]
-set_location_assignment PIN_W3 -to PIO[102]
-set_location_assignment PIN_W4 -to PIO[104]
-set_location_assignment PIN_W7 -to PIO[113]
-set_location_assignment PIN_W9 -to PIO[118]
-set_location_assignment PIN_Y12 -to PIO[129]
-set_location_assignment PIN_Y13 -to A_SYSCLOCK
-set_location_assignment PIN_Y15 -to A_D[15]
-set_location_assignment PIN_Y16 -to A_NEXT_SIGNAL_IN
-set_location_assignment PIN_Y1 -to PIO[101]
-set_location_assignment PIN_Y3 -to PIO[112]
-set_location_assignment PIN_Y4 -to PIO[111]
-set_location_assignment PIN_Y7 -to PIO[110]
-set_location_assignment PIN_Y9 -to PIO[120]
-
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_fsm.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/mil/mil_hw_or_soft_ip.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/ssd1325/src/hdl/generic_serial_master.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/transceiver_prbs/trans_loop.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/wb_mil_scu/event_processing.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/heap/xwb_heap.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/platform/altera/xwrc_platform_altera.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/ad7606/ad7606.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/remote_update/wb_asmi_slave.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/butis_t0/TimestampEncoder.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/daq/daq.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/chopper/Independent_Clk.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/remote_update/remote_update.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xvme64x_pack.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/power_test/row_array.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/watchdog/watchdog_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/wbmstr_core.vhd -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_watchdog_v1.0.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/diob_debounce.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/uart/uart_baudgen.vhd -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/altera/jtag_tap.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/bus_commands.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_async_reset_flop.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_bridge32.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_cbe_en_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_conf_cyc_addr_dec.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_conf_space.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_constants.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_cur_out_reg.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_delayed_sync.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_delayed_write_reg.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_frame_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_frame_en_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_frame_load_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_in_reg.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux_ad_en_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux_ad_load_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_irdy_out_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ad_en_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ad_load_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ch_state_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_master32_sm_if.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_master32_sm.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_out_reg.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_par_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_parity_check.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_pci_decoder.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_pcir_fifo_control.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_pci_tpram.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_pciw_fifo_control.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_pciw_pcir_fifos.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_perr_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_perr_en_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_ram_16x40d.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_rst_int.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_serr_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_serr_en_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_spoci_ctrl.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_synchronizer_flop.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_sync_module.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target32_clk_en.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target32_devs_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target32_interface.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target32_sm.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target32_stop_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target32_trdy_crit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target_unit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_user_constants.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wb_addr_mux.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wb_decoder.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wb_master.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wbr_fifo_control.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wb_slave_unit.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wb_slave.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wbs_wbb3_2_wbb2.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wb_tpram.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_fifo_control.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_wbr_fifos.v" -library work
+set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/timescale.v" -library work
+set_global_assignment -name VERILOG_FILE ../../modules/cfi_flash/cfi_ctrl_engine.v -library work
+set_global_assignment -name VERILOG_FILE ../../modules/cfi_flash/cfi_ctrl.v -library work
+set_global_assignment -name VERILOG_FILE ../../modules/lpc_uart/serirq_defines.v -library work
+set_global_assignment -name VERILOG_FILE ../../modules/lpc_uart/serirq_slave.v -library work
+set_global_assignment -name VERILOG_FILE ../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_altera_asmi_parallel_181_gdoqleq.v -library work
+set_global_assignment -name VERILOG_FILE ../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_altera_asmi_parallel_181_svbigkq.v -library work
+set_global_assignment -name VERILOG_FILE ../../modules/remote_update/asmi5/asmi5/synthesis/submodules/asmi5_asmi_parallel_0.v -library work
+set_global_assignment -name VERILOG_FILE ../../modules/remote_update/asmi_arriaII/asmi_arriaII/synthesis/submodules/asmi_arriaII_asmi_parallel_0.v -library work
+set_global_assignment -name VERILOG_FILE ../../top/blm_aco/deglitcher.v -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/ebm_auto_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/ebm_auto.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/p_connector.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/flash_loader/flash_loader_v01.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_puls_n.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/lpc_uart/lpc_uart_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Access_Decode.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/dm_diag/dm_diag_auto.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/mbox/mbox.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/aux_functions/prio_encoder/prio_encoder_64_6.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/ddr3/ddr3_wrapper.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/ftm/time_clk_cross.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/lpc_uart/postcode.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/butis_t0/BuTis_T0_generator.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Am_Match.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Buffer_pack.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/psram/psram_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/fg_quad_statistics.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Buffer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_bus.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CRAM.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CR_CSR_Space.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CR_pack.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/io_control/src/hdl/io_control.vhd -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_timeout.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/lvds/arria2/arria2_lvds_obuf.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/flash/flash_top.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/eca_tap/eca_tap_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/power_test/row.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/function_generators/serdes_clk_gen/serdes_clk_gen_regs.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/chopper/K12_K23_Logik_Leds.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/modulbus/Epcs_spi.vhd -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/Beam_Loss_check_v1.1.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/scu_bus/scu_bus_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_32to64.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/diob/quench_detection.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_reset.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/oled_display/Display_RAM_Ini_v01.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/lvds/arria2/arria2_lvds_tx.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/dac714/dac714.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/cfi_flash/cfi_flash_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/nau8811/src/hdl/wb_nau8811_audio_driver_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/matrix_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/modulbus/rdram.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/uart/slib_counter.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/wb_arria_reset/arria_reset.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/uart/uart_interrupt.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/aux_functions/Debounce.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/networks/altera_networks_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/uart/slib_mv_filter.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/lvds/arria5_lvds_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CSR_pack.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Funct_Match.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Init.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_IRQ_Controller.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_SharedComps.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_swapper.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_master_eb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_slave.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xVME64xCore_Top.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xvme64x_pack.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/axi/axi4_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/axi/z7_axi_gpio_expander/axi_gpio_expander.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Buffer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_comparator.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_delay_line.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_ds182x_readout/gc_ds182x_readout.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_wb_event.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/oled_display/char_render.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/remote_update/asmi5/asmi5/synthesis/asmi5.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/wb_arria_reset/arria10_reset/arria10_reset/synth/arria10_reset.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/monster/monster_iodir.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/butis_t0/TimestampDecoder.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/function_generators/serdes_clk_gen/xwb_serdes_clk_gen.vhd -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/in_reg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/ftm/ftm_lm32_cluster.vhd -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/blm_24_9_9_9pll.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/beam_dump/beam_dump_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/heap/heap_top.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/transceiver_prbs/trans_rcfg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_internals_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/wb_mil_scu/wb_mil_scu.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/heap/heap_writer.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/trans_pll/trans_pll.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/build_id/build_id_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/scu_diob_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/ebm_auto_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/wb_mil_scu/wb_mil_scu_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/watchdog/watchdog.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_reset_multi_aasd.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_reset.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/fg_quad_ifa.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/beam_dump/beam_dump.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/mil/hw6408_vhdl.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/oled_display/oled_auto_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/prioq2/prio.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/dm_diag/dm_diag.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_rmw.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_slave.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/fg901040.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/matrix_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/altera_async_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/altera_sync_fifo.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/gc_shiftreg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/lvds/arria2/arria2_lvds_rx.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/wr_arria2_phy.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/trans_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_swapper.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/function_generators/scu_slave_fg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/function_generators/scu_slave_fg_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/scu_bus/scu_bus_slave.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/aux_functions/IO_4x8.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/axi/z7_axi_gpio_expander/axi_gpio_expander.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/heap/heap_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_master_eb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_dpram_mixed.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/power_test/pwm.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_counter_pool_el.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_reset_multi_aasd.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/lvds/altera_lvds.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_scubus_channel.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/ebm_auto.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/remote_update/remote_update_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/scu_bus/scu_bus_slave_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/scu_bus/wb_irq_scu_bus.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_split/xwb_split.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_comp_ctrl.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/daq/Zeitbasis_daq.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_data.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/ssd1325/src/hdl/generic_fifo_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/blm_aco.vhd -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_out_el_m.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/oled_display/spi_master.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/uart/uart_transmitter.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_64to32.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/pll/altera_butis.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/fg_quad_scu_bus.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/ddr3/ddr3_wrapper_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/platform/altera/wr_altera_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/cpri_phy_reconf/cpri_phy_reconf.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/psram/psram.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/io_spi_dac_8420.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_bridge.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/modulbus/modulbus_loader.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/ssd1325/src/hdl/generic_fifo.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/wb_arria_reset/wb_arria_reset.vhd -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/io_reg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/uart/slib_edge_detect.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/modulbus/I2C_Cntrl.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/eca_tap/eca_tap.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/power_test/power_test_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/oled_display/oled_auto.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/lvds/altera_lvds_ibuf.vhd -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/chopper/Debounce_Skal.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/ad7606/adc_modul_bus.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/lvds/arria2/arria2_lvds_ibuf.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/diob_sync.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/uart/slib_clock_div.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/xwb_ds182x_readout.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/IOBP_LED_ID_Module.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/chopper/Kicker_Leds.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/wrf_loopback.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/scu_bus/housekeeping.vhd -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/outpuls.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/aux_functions/prio_encoder/prio_encoder_256_8.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/ssd1325/src/hdl/generic_serial_master_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/lpc_uart/i8042_kbc.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_bus.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/aux_functions/div_n.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/uart/slib_input_sync.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register_link.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_queue.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/chopper/Kanal.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/butis_t0/crc8_data8.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_remapper/xwb_remapper.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_auto.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/eca_tap/eca_tap_auto_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/aux_functions/Zeitbasis.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/aux_functions/aux_functions_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/tag_n.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/up_down_counter.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/scu_bus/scu_to_wb.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/aux_functions/local_125_to_12p5.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/pll/altera_reset.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/wb_timer/wb_timer.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/fg_quad_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/prioq2/min3.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/wb_timer/wb_timer_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/config_status.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/prioq2/prio_auto.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/lvds/altera_lvds_obuf.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/pci-core/src/hdl/wb_pci_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Am_Match.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/build_id/build_id.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_bridge.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/simple_tag_decoder/simple_tag_decoder.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/mil/Mil_bipol_dec.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/altera_async_fifo.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/remote_update/asmi10/asmi10/synth/asmi10.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_altera.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CR_CSR_Space.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/lpc_uart/lpc_uart.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_comparator.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/addac_reg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/tag_ctrl.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_split/xwb_split.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic_regs.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/temp_sens/hdl/wb_temp_sense_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/diob/spill_abort.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/ad7606/adc_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/modulbus/f_divider.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/mil/Mil_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/cpri_phy_reconf/cpri_phy_reconf_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Init.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/aux_functions/slave_clk_switch.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_dpram_mixed.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_tlu.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/daq/daq_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/prioq2/min9_64.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/oled_display/display_console.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/aux_functions/local_20_to_12p5.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/flash/altera_flash_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/flash/altera_spi.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/flash/flash_top.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/networks/altera_networks_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_32to64.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_64to32.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_altera.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_tlp.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/dac714/dac714_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_ena_in_mux.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/pci-core/src/hdl/wb_pci_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/wrf_loopback.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/power_test/power_test.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/flash/altera_flash_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/lvds/altera_lvds_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/aux_functions/sys_clk_or_local_clk.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/remote_update/wb_asmi.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/daq/crc5x16.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/modulbus/modulbus_v5.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_auto_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_auto.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_channel.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_data.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_free.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_internals_pkg.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_msi.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_piso_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_queue.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_rmw.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_scan.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_scubus_channel.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_tag_channel.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_tdp.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_fsm.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_tlu.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_wb_event.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/modulbus/modul2spi.vhd -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_gate_timing_seq_elem.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/uart/uart_receiver.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/fg_quad_datapath.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/modulbus/global_reg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/altera_sync_fifo.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/remote_update/asmi_arriaII/asmi_arriaII/synthesis/asmi_arriaII.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/remote_update/wb_remote_update.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/butis_t0/wr_serialtimestamp_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_channel.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/pll/pll_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/monster/monster.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/lvds/altera_lvds_tx.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/lvds/arria10_lvds_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/xwb_ds182x_readout.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/aux_functions/lemo_io.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/chopper/Bus_io.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/ad7606/adc_scu_bus.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/ftm/ftm_lm32.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/uart/slib_fifo.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/daq/daq_chan_reg_logic.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/mil/Mil_Enc_Vhdl.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/scu_bus/wb_scu_bus.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_SharedComps.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/mil/PLL_SIO.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/aux_functions/led_n.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_delay_line.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/prioq2/prio_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/prioq2/queue_unit.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/oled_display/wb_console.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/modulbus/led.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/lvds/arria2_lvds_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_in_mux.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_puls_ctrl.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/modulbus/Rd_mb_ld.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/aux_functions/prio_encoder/prio_encoder_16_4.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/ssd1325/src/hdl/wb_ssd1325_serial_driver.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/prioq2/arbiter.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/mil/Mil_dec_edge_timed.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/lpc_uart/lpc_peripheral.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/heap/heap_pathfinder.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_ds182x_readout/gc_ds182x_readout.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/front_board_id_v0.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/aux_functions/tmr_scu_bus.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/ring_buffer.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/flanke.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/uart/slib_input_filter.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/mil/mil_en_decoder.vhd -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_gate_timing_seq.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/wb_arria_reset/wb_arria_reset_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/function_generators/serdes_clk_gen/serdes_clk_gen.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_tag_channel.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/ssd1325/src/hdl/wb_ssd1325_serial_driver_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic_regs.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_piso_fifo.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_remapper/xwb_remapper.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/monster/monster_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/eca_tap/eca_tap_auto.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/remote_update/altasmi.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xVME64xCore_Top.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/cfi_flash/xwb_cfi_wrapper.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/reverse_lpb/reverse_lpb.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/wb_scu_reg/wb_scu_reg.vhd -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" -library work
 set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/modulbus/K_EPCS_IF.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CSR_pack.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/ftm/ftm_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/flash/altera_spi.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/lvds/eca_lvds_channel.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/platform/altera/wr_altera_pkg.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/wr_arria2_phy.vhd" -library work
+set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/platform/altera/xwrc_platform_altera.vhd" -library work
 set_global_assignment -name VHDL_FILE ../../modules/a10ts/src/hdl/a10ts_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_cnt_n.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_free.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../top/blm_aco/aw_io_reg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/wb_arria_reset/arria5_reset.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/uart/uart_16750.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CRAM.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Funct_Match.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/wb_arria_reset/arria10_reset/arria10_reset/altera_remote_update_181/synth/arria10_reset_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/mil/SysClock.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/wb_mil_scu/mil_pll.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/oled_display/oled_display_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/led_blink.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_IRQ_Controller.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/ad7606/ad7606.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ad7606/adc_modul_bus.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ad7606/adc_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ad7606/adc_scu_bus.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/aux_functions_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/Debounce.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/div_n.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/IO_4x8.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/led_n.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/lemo_io.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/local_125_to_12p5.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/local_20_to_12p5.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/prio_encoder/prio_encoder_16_4.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/prio_encoder/prio_encoder_256_8.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/prio_encoder/prio_encoder_64_6.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/slave_clk_switch.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/sys_clk_or_local_clk.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/tmr_scu_bus.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/aux_functions/Zeitbasis.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/beam_dump/beam_dump_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/beam_dump/beam_dump.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/build_id/build_id_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/build_id/build_id.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/butis_t0/BuTis_T0_generator.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/butis_t0/crc8_data8.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/butis_t0/TimestampDecoder.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/butis_t0/TimestampEncoder.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/butis_t0/wr_serialtimestamp_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/cfi_flash/cfi_flash_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/cfi_flash/xwb_cfi_wrapper.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/chopper/Bus_io.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/chopper/Debounce_Skal.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/chopper/Independent_Clk.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/chopper/K12_K23_Logik_Leds.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/chopper/Kanal.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/chopper/Kicker_Leds.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/cpri_phy_reconf/cpri_phy_reconf_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/cpri_phy_reconf/cpri_phy_reconf.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/dac714/dac714_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/dac714/dac714.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/daq/crc5x16.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/daq/daq_chan_reg_logic.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/daq/daq_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/daq/daq.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/daq/Zeitbasis_daq.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ddr3/ddr3_wrapper_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ddr3/ddr3_wrapper.vhd -library work
 set_global_assignment -name VHDL_FILE ../../modules/diob/hw_interlock.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_scan.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/io_control/src/hdl/io_control_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/i2c_wrapper/src/hdl/wb_i2c_wrapper_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/pll/altera_phase.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/function_generators/serdes_clk_gen/wb_serdes_clk_gen.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/function_generators/serdes_clk_gen/wb_serdes_clk_gen_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/lvds/altera_lvds_rx.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/prioq2/prio_auto_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/modulbus/Loader_MB.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/mbox/mbox_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/axi/axi4_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd" -library work
+set_global_assignment -name VHDL_FILE ../../modules/diob/quench_detection.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/diob/spill_abort.vhd -library work
 set_global_assignment -name VHDL_FILE ../../modules/dm_diag/dm_diag_auto_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/simple_tag_decoder/simple_tag_decoder_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/wr-cores/modules/wr_eca/eca_auto_pkg.vhd" -library work
-set_global_assignment -name VHDL_FILE ../../modules/wb_scu_reg/wb_scu_reg_pkg.vhd -library work
-set_global_assignment -name VHDL_FILE ../../modules/mil/PU_Reset.vhd -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" -library work
-set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target32_devs_crit.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_pci_decoder.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux.v" -library work
-set_global_assignment -name VERILOG_FILE ../../modules/lpc_uart/serirq_defines.v -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wb_slave.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target32_sm.v" -library work
-set_global_assignment -name VERILOG_FILE ../../modules/remote_update/asmi5/asmi5/synthesis/submodules/asmi5_asmi_parallel_0.v -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_pcir_fifo_control.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ad_load_crit.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target_unit.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_perr_crit.v" -library work
-set_global_assignment -name VERILOG_FILE ../../modules/cfi_flash/cfi_ctrl.v -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target32_clk_en.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_perr_en_crit.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" -library work
-set_global_assignment -name VERILOG_FILE ../../top/blm_aco/deglitcher.v -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux_ad_load_crit.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_in_reg.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_pciw_fifo_control.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target32_stop_crit.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_synchronizer_flop.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_bridge32.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_frame_crit.v" -library work
-set_global_assignment -name VERILOG_FILE ../../modules/lpc_uart/serirq_slave.v -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ad_en_crit.v" -library work
-set_global_assignment -name VERILOG_FILE ../../modules/remote_update/asmi_arriaII/asmi_arriaII/synthesis/submodules/asmi_arriaII_asmi_parallel_0.v -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_master32_sm.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_conf_space.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_irdy_out_crit.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_pci_tpram.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_sync_module.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_parity_check.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wb_decoder.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wbs_wbb3_2_wbb2.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wbr_fifo_control.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_constants.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/altera/jtag_tap.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wb_slave_unit.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_master32_sm_if.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_rst_int.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_conf_cyc_addr_dec.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_par_crit.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_cur_out_reg.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_fifo_control.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_serr_en_crit.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_user_constants.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" -library work
-set_global_assignment -name VERILOG_FILE ../../modules/cfi_flash/cfi_ctrl_engine.v -library work
-set_global_assignment -name VERILOG_FILE ../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_altera_asmi_parallel_181_svbigkq.v -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_cbe_en_crit.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target32_interface.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_delayed_sync.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_frame_load_crit.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/timescale.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_ram_16x40d.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_delayed_write_reg.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wb_addr_mux.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/bus_commands.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_target32_trdy_crit.v" -library work
-set_global_assignment -name VERILOG_FILE ../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_altera_asmi_parallel_181_gdoqleq.v -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_spoci_ctrl.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_pciw_pcir_fifos.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_async_reset_flop.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ch_state_crit.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_frame_en_crit.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_wbr_fifos.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_serr_crit.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_out_reg.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wb_tpram.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_wb_master.v" -library work
-set_global_assignment -name VERILOG_FILE "../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux_ad_en_crit.v" -library work
-set_global_assignment -name SDC_FILE ../../top/blm_aco/scu_diob.sdc
-set_global_assignment -name QIP_FILE "../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/wr_arria2_phy.qip"
-set_global_assignment -name QIP_FILE ../../modules/pll/arria2/arria2_pll.qip
-set_global_assignment -name QIP_FILE ../../modules/ddr3/arria2/arria2_ddr3.qip
-set_global_assignment -name QIP_FILE "../../ip_cores/general-cores/platform/altera/networks/arria2gx_networks.qip"
-set_global_assignment -name QIP_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/arria2_pcie.qip"
-set_global_assignment -name AHDL_FILE ../../modules/modulbus/i2c.tdf
-set_global_assignment -name TOP_LEVEL_ENTITY blm_aco
-set_global_assignment -name QIP_FILE ../../modules/pll/arria2/sys_pll.qip
-set_global_assignment -name QIP_FILE ../../modules/pll/arria2/ref_pll.qip
-set_global_assignment -name QIP_FILE ../../modules/pll/arria2/dmtd_pll.qip
\ No newline at end of file
+set_global_assignment -name VHDL_FILE ../../modules/dm_diag/dm_diag_auto.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/dm_diag/dm_diag.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/eca_tap/eca_tap_auto_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/eca_tap/eca_tap_auto.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/eca_tap/eca_tap_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/eca_tap/eca_tap.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/flash_loader/flash_loader_v01.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ftm/ftm_lm32_cluster.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ftm/ftm_lm32.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ftm/ftm_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ftm/time_clk_cross.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/fg_quad_datapath.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/fg_quad_ifa.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/fg_quad_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/fg_quad_scu_bus.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/fg_quad_statistics.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/ring_buffer.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/fg_quad/wbmstr_core.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/scu_slave_fg_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/scu_slave_fg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/serdes_clk_gen/serdes_clk_gen_regs.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/serdes_clk_gen/serdes_clk_gen.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/serdes_clk_gen/wb_serdes_clk_gen_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/serdes_clk_gen/wb_serdes_clk_gen.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/function_generators/serdes_clk_gen/xwb_serdes_clk_gen.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/heap/heap_pathfinder.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/heap/heap_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/heap/heap_top.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/heap/heap_writer.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/heap/xwb_heap.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/i2c_wrapper/src/hdl/wb_i2c_wrapper_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/io_control/src/hdl/io_control_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/io_control/src/hdl/io_control.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/led_blink.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lpc_uart/i8042_kbc.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lpc_uart/lpc_peripheral.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lpc_uart/lpc_uart_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lpc_uart/lpc_uart.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lpc_uart/postcode.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/altera_lvds_ibuf.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/altera_lvds_obuf.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/altera_lvds_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/altera_lvds_rx.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/altera_lvds_tx.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/altera_lvds.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/arria10_lvds_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/arria2/arria2_lvds_ibuf.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/arria2/arria2_lvds_obuf.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/arria2/arria2_lvds_rx.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/arria2/arria2_lvds_tx.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/arria2_lvds_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/arria5_lvds_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/lvds/eca_lvds_channel.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mbox/mbox_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mbox/mbox.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/hw6408_vhdl.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/Mil_bipol_dec.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/Mil_dec_edge_timed.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/Mil_Enc_Vhdl.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/mil_en_decoder.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/mil_hw_or_soft_ip.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/Mil_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/PLL_SIO.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/PU_Reset.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/mil/SysClock.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/Epcs_spi.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/f_divider.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/global_reg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/I2C_Cntrl.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/K_EPCS_IF.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/led.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/Loader_MB.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/modul2spi.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/modulbus_loader.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/modulbus_v5.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/Rd_mb_ld.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/modulbus/rdram.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/monster/monster_iodir.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/monster/monster_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/monster/monster.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/nau8811/src/hdl/wb_nau8811_audio_driver_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/oled_display/char_render.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/oled_display/display_console.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/oled_display/Display_RAM_Ini_v01.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/oled_display/oled_auto_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/oled_display/oled_auto.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/oled_display/oled_display_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/oled_display/spi_master.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/oled_display/wb_console.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/pll/altera_butis.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/pll/altera_phase.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/pll/altera_reset.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/pll/pll_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/power_test/power_test_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/power_test/power_test.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/power_test/pwm.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/power_test/row_array.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/power_test/row.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/prioq2/arbiter.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/prioq2/min3.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/prioq2/min9_64.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/prioq2/prio_auto_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/prioq2/prio_auto.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/prioq2/prio_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/prioq2/prio.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/prioq2/queue_unit.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/psram/psram_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/psram/psram.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/altasmi.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/asmi10/asmi10/synth/asmi10.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/asmi5/asmi5/synthesis/asmi5.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/asmi_arriaII/asmi_arriaII/synthesis/asmi_arriaII.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/remote_update_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/remote_update.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/wb_asmi_slave.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/wb_asmi.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/remote_update/wb_remote_update.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/reverse_lpb/reverse_lpb.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/scu_bus/housekeeping.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/scu_bus/scu_bus_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/scu_bus/scu_bus_slave_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/scu_bus/scu_bus_slave.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/scu_bus/scu_to_wb.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/scu_bus/wb_irq_scu_bus.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/scu_bus/wb_scu_bus.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/simple_tag_decoder/simple_tag_decoder_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/simple_tag_decoder/simple_tag_decoder.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ssd1325/src/hdl/generic_fifo_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ssd1325/src/hdl/generic_fifo.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ssd1325/src/hdl/generic_serial_master_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ssd1325/src/hdl/generic_serial_master.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ssd1325/src/hdl/wb_ssd1325_serial_driver_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/ssd1325/src/hdl/wb_ssd1325_serial_driver.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/temp_sens/hdl/wb_temp_sense_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/transceiver_prbs/trans_loop.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/transceiver_prbs/trans_rcfg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/trans_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/trans_pll/trans_pll.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/slib_clock_div.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/slib_counter.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/slib_edge_detect.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/slib_fifo.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/slib_input_filter.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/slib_input_sync.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/slib_mv_filter.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/uart_16750.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/uart_baudgen.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/uart_interrupt.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/uart_receiver.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/uart/uart_transmitter.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/watchdog/watchdog_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/watchdog/watchdog.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_arria_reset/arria10_reset/arria10_reset/altera_remote_update_181/synth/arria10_reset_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_arria_reset/arria10_reset/arria10_reset/synth/arria10_reset.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_arria_reset/arria5_reset.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_arria_reset/arria_reset.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_arria_reset/wb_arria_reset_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_arria_reset/wb_arria_reset.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_mil_scu/event_processing.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_mil_scu/mil_pll.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_mil_scu/wb_mil_scu_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_mil_scu/wb_mil_scu.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_scu_reg/wb_scu_reg_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_scu_reg/wb_scu_reg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_timer/wb_timer_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../modules/wb_timer/wb_timer.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/addac_reg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_cnt_n.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_comp_ctrl.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_puls_ctrl.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_puls_n.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_timeout.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/aw_io_reg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/Beam_Loss_check_v1.2.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/blm_24_9_9_9pll.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/blm_aco_v1.0.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_cnt_pulse_former.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_counter_pool_el.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_ena_in_mux.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_gate_el_v1.0.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_gate_timing_seq_v1.2.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_in_mux.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_out_el_m_v1.0.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_watchdog_v1.0.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/config_status.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/diob_debounce.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/diob_sync.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/fg901040.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/flanke.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/front_board_id_v0.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/in_reg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/IOBP_LED_ID_module_v1.0.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/io_reg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/io_spi_dac_8420.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/outpuls.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/p_connector.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/scu_diob_pkg.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/tag_ctrl.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/tag_n.vhd -library work
+set_global_assignment -name VHDL_FILE ../../top/blm_aco/up_down_counter.vhd -library work
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to A_nSEL_Ext_Signal_DRV
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PIO[143]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PIO[144]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PIO[145]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PIO[146]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PIO[147]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PIO[148]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PIO[149]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PIO[150]
+set_location_assignment PIN_A11 -to A_TA[10]
+set_location_assignment PIN_A12 -to A_TA[6]
+set_location_assignment PIN_A13 -to A_TA[0]
+set_location_assignment PIN_A14 -to A_TA[3]
+set_location_assignment PIN_A15 -to A_TA[9]
+set_location_assignment PIN_A16 -to UIO[2]
+set_location_assignment PIN_A17 -to UIO[3]
+set_location_assignment PIN_A18 -to UIO[4]
+set_location_assignment PIN_A19 -to UIO[15]
+set_location_assignment PIN_A20 -to UIO[10]
+set_location_assignment PIN_A2 -to PIO[16]
+set_location_assignment PIN_A3 -to PIO[49]
+set_location_assignment PIN_A5 -to PIO[41]
+set_location_assignment PIN_AA10 -to A_A[4]
+set_location_assignment PIN_AA11 -to A_A[15]
+set_location_assignment PIN_AA12 -to A_A[6]
+set_location_assignment PIN_AA14 -to A_D[7]
+set_location_assignment PIN_AA15 -to A_SPARE0
+set_location_assignment PIN_AA16 -to A_NDTACK
+set_location_assignment PIN_AA18 -to A_NSEL_EXT_DATA_DRV
+set_location_assignment PIN_AA1 -to PIO[103]
+set_location_assignment PIN_AA3 -to PIO[107]
+set_location_assignment PIN_AA4 -to PIO[109]
+set_location_assignment PIN_AA5 -to PIO[142]
+set_location_assignment PIN_AA6 -to A_A[8]
+set_location_assignment PIN_AA7 -to A_A[10]
+set_location_assignment PIN_AA8 -to A_A[11]
+set_location_assignment PIN_AA9 -to A_A[3]
+set_location_assignment PIN_AB10 -to PIO[122]
+set_location_assignment PIN_AB11 -to PIO[136]
+set_location_assignment PIN_AB12 -to PIO[145]
+set_location_assignment PIN_AB13 -to PIO[149]
+set_location_assignment PIN_AB14 -to A_D[12]
+set_location_assignment PIN_AB15 -to A_D[2]
+set_location_assignment PIN_AB16 -to A_D[6]
+set_location_assignment PIN_AB17 -to A_ONEWIRE
+set_location_assignment PIN_AB18 -to A_NBOARDSEL
+set_location_assignment PIN_AB19 -to A_RNW
+set_location_assignment PIN_AB1 -to PIO[128]
+set_location_assignment PIN_AB20 -to A_NADR_EN
+set_location_assignment PIN_AB21 -to A_NSRQ
+set_location_assignment PIN_AB2 -to PIO[130]
+set_location_assignment PIN_AB3 -to PIO[133]
+set_location_assignment PIN_AB4 -to PIO[140]
+set_location_assignment PIN_AB5 -to PIO[139]
+set_location_assignment PIN_AB6 -to A_A[9]
+set_location_assignment PIN_AB7 -to A_A[0]
+set_location_assignment PIN_AB8 -to A_A[2]
+set_location_assignment PIN_AB9 -to A_A[13]
+set_location_assignment PIN_AC12 -to PIO[143]
+set_location_assignment PIN_AC13 -to PIO[147]
+set_location_assignment PIN_AC15 -to A_D[4]
+set_location_assignment PIN_AC18 -to A_NSEL_EXT_SIGNAL_DRV
+set_location_assignment PIN_AC19 -to A_D[11]
+set_location_assignment PIN_AC1 -to PIO[123]
+set_location_assignment PIN_AC3 -to PIO[108]
+set_location_assignment PIN_AC4 -to PIO[127]
+set_location_assignment PIN_AC6 -to PIO[146]
+set_location_assignment PIN_AC9 -to A_A[12]
+set_location_assignment PIN_AD10 -to PIO[126]
+set_location_assignment PIN_AD11 -to PIO[138]
+set_location_assignment PIN_AD12 -to A_A[7]
+set_location_assignment PIN_AD13 -to CLK_20MHZ_D
+set_location_assignment PIN_AD15 -to A_D[3]
+set_location_assignment PIN_AD16 -to A_D[5]
+set_location_assignment PIN_AD17 -to A_D[8]
+set_location_assignment PIN_AD18 -to A_D[9]
+set_location_assignment PIN_AD19 -to A_D[10]
+set_location_assignment PIN_AD20 -to A_NRESET
+set_location_assignment PIN_AD21 -to A_NADR_FROM_SCUB
+set_location_assignment PIN_AD2 -to PIO[131]
+set_location_assignment PIN_AD3 -to PIO[135]
+set_location_assignment PIN_AD4 -to PIO[137]
+set_location_assignment PIN_AD5 -to PIO[141]
+set_location_assignment PIN_AD6 -to PIO[144]
+set_location_assignment PIN_AD7 -to A_A[1]
+set_location_assignment PIN_AD8 -to PIO[150]
+set_location_assignment PIN_AD9 -to PIO[124]
+set_location_assignment PIN_B10 -to PIO[45]
+set_location_assignment PIN_B12 -to A_TA[12]
+set_location_assignment PIN_B13 -to A_TA[4]
+set_location_assignment PIN_B15 -to A_TA[7]
+set_location_assignment PIN_B16 -to UIO[5]
+set_location_assignment PIN_B18 -to UIO[11]
+set_location_assignment PIN_B19 -to A_SEL[1]
+set_location_assignment PIN_B1 -to PIO[28]
+set_location_assignment PIN_B3 -to PIO[26]
+set_location_assignment PIN_B4 -to PIO[21]
+set_location_assignment PIN_B6 -to PIO[27]
+set_location_assignment PIN_B7 -to PIO[29]
+set_location_assignment PIN_B9 -to PIO[47]
+set_location_assignment PIN_C12 -to A_TA[14]
+set_location_assignment PIN_C13 -to A_TA[13]
+set_location_assignment PIN_C15 -to A_TA[2]
+set_location_assignment PIN_C16 -to A_TA[11]
+set_location_assignment PIN_C18 -to A_TCLK
+set_location_assignment PIN_C19 -to UIO[6]
+set_location_assignment PIN_C1 -to PIO[40]
+set_location_assignment PIN_C20 -to A_SEL[3]
+set_location_assignment PIN_C2 -to PIO[43]
+set_location_assignment PIN_C3 -to PIO[38]
+set_location_assignment PIN_C7 -to PIO[33]
+set_location_assignment PIN_D10 -to PIO[31]
+set_location_assignment PIN_D11 -to CLK_20MHZ_A
+set_location_assignment PIN_D12 -to UIO[0]
+set_location_assignment PIN_D13 -to UIO[1]
+set_location_assignment PIN_D14 -to A_TA[1]
+set_location_assignment PIN_D15 -to A_TA[15]
+set_location_assignment PIN_D1 -to PIO[39]
+set_location_assignment PIN_D2 -to PIO[52]
+set_location_assignment PIN_D3 -to PIO[18]
+set_location_assignment PIN_D4 -to PIO[50]
+set_location_assignment PIN_D7 -to A_NLED_D3
+set_location_assignment PIN_D8 -to PIO[23]
+set_location_assignment PIN_D9 -to PIO[19]
+set_location_assignment PIN_E12 -to UIO[7]
+set_location_assignment PIN_E13 -to UIO[8]
+set_location_assignment PIN_E15 -to UIO[13]
+set_location_assignment PIN_E16 -to A_SEL[2]
+set_location_assignment PIN_E1 -to PIO[20]
+set_location_assignment PIN_E3 -to PIO[22]
+set_location_assignment PIN_E4 -to PIO[35]
+set_location_assignment PIN_E7 -to A_NLED_D2
+set_location_assignment PIN_F10 -to PIO[78]
+set_location_assignment PIN_F12 -to CLK_IO
+set_location_assignment PIN_F13 -to A_TA[5]
+set_location_assignment PIN_F14 -to UIO[12]
+set_location_assignment PIN_F15 -to UIO[14]
+set_location_assignment PIN_F1 -to PIO[30]
+set_location_assignment PIN_F3 -to PIO[48]
+set_location_assignment PIN_F4 -to PIO[25]
+set_location_assignment PIN_F7 -to PIO[24]
+set_location_assignment PIN_F8 -to PIO[66]
+set_location_assignment PIN_F9 -to PIO[68]
+set_location_assignment PIN_G10 -to PIO[80]
+set_location_assignment PIN_G13 -to A_TA[8]
+set_location_assignment PIN_G14 -to UIO[9]
+set_location_assignment PIN_G16 -to A_SEL[0]
+set_location_assignment PIN_G1 -to PIO[42]
+set_location_assignment PIN_G2 -to PIO[32]
+set_location_assignment PIN_G3 -to PIO[62]
+set_location_assignment PIN_G4 -to PIO[55]
+set_location_assignment PIN_G5 -to PIO[37]
+set_location_assignment PIN_G6 -to PIO[17]
+set_location_assignment PIN_G7 -to PIO[34]
+set_location_assignment PIN_H16 -to A_NUSER_EN
+set_location_assignment PIN_H1 -to PIO[44]
+set_location_assignment PIN_H3 -to PIO[51]
+set_location_assignment PIN_H4 -to PIO[58]
+set_location_assignment PIN_H6 -to PIO[54]
+set_location_assignment PIN_H7 -to PIO[36]
+set_location_assignment PIN_J1 -to PIO[56]
+set_location_assignment PIN_J3 -to PIO[64]
+set_location_assignment PIN_J4 -to PIO[60]
+set_location_assignment PIN_J5 -to PIO[46]
+set_location_assignment PIN_J6 -to PIO[53]
+set_location_assignment PIN_K1 -to PIO[63]
+set_location_assignment PIN_K2 -to PIO[59]
+set_location_assignment PIN_K3 -to PIO[71]
+set_location_assignment PIN_K4 -to PIO[67]
+set_location_assignment PIN_K5 -to PIO[57]
+set_location_assignment PIN_L1 -to PIO[75]
+set_location_assignment PIN_L3 -to PIO[74]
+set_location_assignment PIN_L4 -to PIO[70]
+set_location_assignment PIN_L7 -to PIO[61]
+set_location_assignment PIN_M1 -to PIO[83]
+set_location_assignment PIN_M3 -to PIO[72]
+set_location_assignment PIN_M4 -to PIO[79]
+set_location_assignment PIN_M7 -to PIO[65]
+set_location_assignment PIN_N1 -to PIO[73]
+set_location_assignment PIN_N2 -to PIO[77]
+set_location_assignment PIN_N4 -to CLK_20MHZ_B
+set_location_assignment PIN_N6 -to PIO[82]
+set_location_assignment PIN_N7 -to PIO[69]
+set_location_assignment PIN_P1 -to PIO[76]
+set_location_assignment PIN_P4 -to CLK_20MHZ_C
+set_location_assignment PIN_P7 -to PIO[84]
+set_location_assignment PIN_R1 -to PIO[91]
+set_location_assignment PIN_R3 -to PIO[86]
+set_location_assignment PIN_R4 -to PIO[81]
+set_location_assignment PIN_R5 -to PIO[94]
+set_location_assignment PIN_R6 -to PIO[85]
+set_location_assignment PIN_R7 -to PIO[117]
+set_location_assignment PIN_T1 -to PIO[89]
+set_location_assignment PIN_T2 -to PIO[87]
+set_location_assignment PIN_T3 -to PIO[95]
+set_location_assignment PIN_T4 -to PIO[88]
+set_location_assignment PIN_T5 -to PIO[93]
+set_location_assignment PIN_T6 -to PIO[97]
+set_location_assignment PIN_U16 -to A_EXT_DATA_RD
+set_location_assignment PIN_U1 -to PIO[96]
+set_location_assignment PIN_U3 -to PIO[98]
+set_location_assignment PIN_U4 -to PIO[100]
+set_location_assignment PIN_U6 -to PIO[115]
+set_location_assignment PIN_U9 -to PIO[119]
+set_location_assignment PIN_V11 -to PIO[125]
+set_location_assignment PIN_V12 -to PIO[132]
+set_location_assignment PIN_V13 -to A_D[0]
+set_location_assignment PIN_V14 -to A_D[14]
+set_location_assignment PIN_V15 -to A_NDS
+set_location_assignment PIN_V16 -to A_NEVENT_STR
+set_location_assignment PIN_V1 -to PIO[92]
+set_location_assignment PIN_V3 -to PIO[90]
+set_location_assignment PIN_V4 -to PIO[114]
+set_location_assignment PIN_V5 -to PIO[99]
+set_location_assignment PIN_V6 -to PIO[116]
+set_location_assignment PIN_V7 -to PIO[148]
+set_location_assignment PIN_V9 -to A_A[14]
+set_location_assignment PIN_W10 -to PIO[121]
+set_location_assignment PIN_W11 -to A_A[5]
+set_location_assignment PIN_W12 -to PIO[134]
+set_location_assignment PIN_W13 -to A_D[13]
+set_location_assignment PIN_W14 -to A_D[1]
+set_location_assignment PIN_W16 -to A_SPARE1
+set_location_assignment PIN_W1 -to PIO[106]
+set_location_assignment PIN_W2 -to PIO[105]
+set_location_assignment PIN_W3 -to PIO[102]
+set_location_assignment PIN_W4 -to PIO[104]
+set_location_assignment PIN_W7 -to PIO[113]
+set_location_assignment PIN_W9 -to PIO[118]
+set_location_assignment PIN_Y12 -to PIO[129]
+set_location_assignment PIN_Y13 -to A_SYSCLOCK
+set_location_assignment PIN_Y15 -to A_D[15]
+set_location_assignment PIN_Y16 -to A_NEXT_SIGNAL_IN
+set_location_assignment PIN_Y1 -to PIO[101]
+set_location_assignment PIN_Y3 -to PIO[112]
+set_location_assignment PIN_Y4 -to PIO[111]
+set_location_assignment PIN_Y7 -to PIO[110]
+set_location_assignment PIN_Y9 -to PIO[120]