From 2675df0bb8fd74cb2d305cc57908b5f5368de4c2 Mon Sep 17 00:00:00 2001
From: HidetaroTanaka <s227891v@st.me.tuat.ac.jp>
Date: Tue, 30 Jan 2024 13:57:38 +0900
Subject: [PATCH] a

---
 ...ationTest.scala => CoreApplicationTest.scala} | 16 ++++++++--------
 .../hajime/vectormodules/VectorCpuSpec.scala     |  2 +-
 2 files changed, 9 insertions(+), 9 deletions(-)
 rename src/test/scala/hajime/simple4Stage/{Core_ApplicationTest.scala => CoreApplicationTest.scala} (85%)

diff --git a/src/test/scala/hajime/simple4Stage/Core_ApplicationTest.scala b/src/test/scala/hajime/simple4Stage/CoreApplicationTest.scala
similarity index 85%
rename from src/test/scala/hajime/simple4Stage/Core_ApplicationTest.scala
rename to src/test/scala/hajime/simple4Stage/CoreApplicationTest.scala
index b7914af..1a386a6 100644
--- a/src/test/scala/hajime/simple4Stage/Core_ApplicationTest.scala
+++ b/src/test/scala/hajime/simple4Stage/CoreApplicationTest.scala
@@ -5,12 +5,12 @@ import chiseltest._
 import org.scalatest.flatspec._
 import hajime.vectormodules.MemInitializer._
 
-object Core_ApplicationTest {
-  def get_toHostChar[T <: CpuModule](dut: CoreAndCache[T]): Char = {
+object CoreApplicationTest {
+  def getToHostChar[T <: CpuModule](dut: CoreAndCache[T]): Char = {
     dut.io.toHost.bits.peekInt().toChar
   }
 
-  def get_toHostValid[T <: CpuModule](dut: CoreAndCache[T]): Boolean = {
+  def getToHostValid[T <: CpuModule](dut: CoreAndCache[T]): Boolean = {
     dut.io.toHost.valid.peekBoolean()
   }
 
@@ -26,11 +26,11 @@ object Core_ApplicationTest {
     dut.io.hartid.poke(0.U)
 
     var toHostWrittenChar: List[Char] = Nil
-    while (!(get_toHostValid(dut) && (get_toHostChar(dut) == '\u0000'))) {
+    while (!(getToHostValid(dut) && (getToHostChar(dut) == '\u0000'))) {
       dut.clock.step()
-      if (get_toHostValid(dut)) {
-        // print(get_toHostChar())
-        toHostWrittenChar = toHostWrittenChar :+ get_toHostChar(dut)
+      if (getToHostValid(dut)) {
+        // print(getToHostChar())
+        toHostWrittenChar = toHostWrittenChar :+ getToHostChar(dut)
       }
     }
     dut.io.debugIO.debugAbiMap.a0.expect(0.U(64.W))
@@ -39,7 +39,7 @@ object Core_ApplicationTest {
   }
 }
 
-import Core_ApplicationTest._
+import CoreApplicationTest._
 
 class Rv64iApplicationTest extends AnyFlatSpec with ChiselScalatestTester {
   val rv64iTestList = Seq(
diff --git a/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala b/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala
index 7cffc1f..819909c 100644
--- a/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala
+++ b/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala
@@ -2,7 +2,7 @@ package hajime.vectormodules
 
 import chisel3._
 import chiseltest._
-import hajime.simple4Stage.Core_ApplicationTest._
+import hajime.simple4Stage.CoreApplicationTest._
 import hajime.vectormodules.MemInitializer._
 import hajime.simple4Stage._
 import org.scalatest.flatspec._