From a0542bd14c10e82e6b5305d7219e5948cc9a33d7 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Tue, 28 Nov 2023 14:42:08 +0900 Subject: [PATCH 01/13] a --- .../applications_vector/vector_matmul.dump | 2962 +++++++++-------- .../vector_matmul/vector_matmul.c | 192 +- .../vector_matmul_data.hex | 824 +++-- .../vector_matmul_inst.hex | 252 +- .../simple4Stage/Core_ApplicationTest.scala | 2 +- 5 files changed, 2398 insertions(+), 1834 deletions(-) diff --git a/src/main/resources/applications_vector/vector_matmul.dump b/src/main/resources/applications_vector/vector_matmul.dump index c832d0f7..cbf19d96 100644 --- a/src/main/resources/applications_vector/vector_matmul.dump +++ b/src/main/resources/applications_vector/vector_matmul.dump @@ -40,7 +40,7 @@ Disassembly of section .text.init: 80: 03828293 add t0,t0,56 # b4 84: 30529073 csrw mtvec,t0 88: 00005197 auipc gp,0x5 - 8c: dd018193 add gp,gp,-560 # 4e58 <__global_pointer$> + 8c: 15018193 add gp,gp,336 # 51d8 <__global_pointer$> 90: 10000217 auipc tp,0x10000 94: ff720213 add tp,tp,-9 # 10000087 <_end+0x3f> 98: fc027213 and tp,tp,-64 @@ -48,8 +48,8 @@ Disassembly of section .text.init: a0: 00100593 li a1,1 a4: 00b57063 bgeu a0,a1,a4 <_start+0xa4> a8: 00006137 lui sp,0x6 - ac: ff01011b addw sp,sp,-16 # 5ff0 <__global_pointer$+0x1198> - b0: 76c0006f j 81c <_init> + ac: ff01011b addw sp,sp,-16 # 5ff0 <_tbss_end+0xe10> + b0: 7680006f j 818 <_init> 00000000000000b4 : b4: ef010113 add sp,sp,-272 @@ -87,10 +87,10 @@ Disassembly of section .text.init: 134: 34202573 csrr a0,mcause 138: 341025f3 csrr a1,mepc 13c: 00010613 mv a2,sp - 140: 3e4000ef jal 524 + 140: 3e0000ef jal 520 144: 34151073 csrw mepc,a0 148: 000022b7 lui t0,0x2 - 14c: 8002829b addw t0,t0,-2048 # 1800 + 14c: 8002829b addw t0,t0,-2048 # 1800 150: 3002a073 csrs mstatus,t0 154: 00813083 ld ra,8(sp) 158: 01013103 ld sp,16(sp) @@ -144,32 +144,32 @@ Disassembly of section .text: 200: c0002973 rdcycle s2 204: b0302473 csrr s0,mhpmcounter3 208: 00004517 auipc a0,0x4 - 20c: 2a850513 add a0,a0,680 # 44b0 - 210: 170000ef jal 380 + 20c: 62850513 add a0,a0,1576 # 4830 + 210: 16c000ef jal 37c 214: 00810593 add a1,sp,8 218: 00090513 mv a0,s2 - 21c: 120000ef jal 33c + 21c: 11c000ef jal 338 220: 00810513 add a0,sp,8 - 224: 15c000ef jal 380 + 224: 158000ef jal 37c 228: 00004517 auipc a0,0x4 - 22c: 29050513 add a0,a0,656 # 44b8 - 230: 150000ef jal 380 + 22c: 61050513 add a0,a0,1552 # 4838 + 230: 14c000ef jal 37c 234: 00810593 add a1,sp,8 238: 00048513 mv a0,s1 - 23c: 100000ef jal 33c + 23c: 0fc000ef jal 338 240: 00810513 add a0,sp,8 - 244: 13c000ef jal 380 + 244: 138000ef jal 37c 248: 00004517 auipc a0,0x4 - 24c: 28050513 add a0,a0,640 # 44c8 - 250: 130000ef jal 380 + 24c: 60050513 add a0,a0,1536 # 4848 + 250: 12c000ef jal 37c 254: 00810593 add a1,sp,8 258: 00040513 mv a0,s0 - 25c: 0e0000ef jal 33c + 25c: 0dc000ef jal 338 260: 00810513 add a0,sp,8 - 264: 11c000ef jal 380 + 264: 118000ef jal 37c 268: 00004517 auipc a0,0x4 - 26c: 27050513 add a0,a0,624 # 44d8 - 270: 110000ef jal 380 + 26c: 5f050513 add a0,a0,1520 # 4858 + 270: 10c000ef jal 37c 274: 03813083 ld ra,56(sp) 278: 03013403 ld s0,48(sp) 27c: 02813483 ld s1,40(sp) @@ -177,1351 +177,1665 @@ Disassembly of section .text: 284: 04010113 add sp,sp,64 288: 00008067 ret -000000000000028c : - 28c: 00050893 mv a7,a0 - 290: 04060a63 beqz a2,2e4 - 294: 00261313 sll t1,a2,0x2 - 298: 00060793 mv a5,a2 - 29c: 00000513 li a0,0 - 2a0: 0d07f857 vsetvli a6,a5,e32,m1,ta,ma - 2a4: 0008069b sext.w a3,a6 - 2a8: 420561d7 vmv.s.x v3,a0 - 2ac: 0208e087 vle32.v v1,(a7) - 2b0: 0a65e107 vlse32.v v2,(a1),t1 - 2b4: 961120d7 vmul.vv v1,v1,v2 - 2b8: 0211a0d7 vredsum.vs v1,v1,v3 - 2bc: 42102557 vmv.x.s a0,v1 - 2c0: 02c8073b mulw a4,a6,a2 - 2c4: 00269693 sll a3,a3,0x2 - 2c8: 410787bb subw a5,a5,a6 - 2cc: 0005051b sext.w a0,a0 - 2d0: 00d888b3 add a7,a7,a3 - 2d4: 00271713 sll a4,a4,0x2 - 2d8: 00e585b3 add a1,a1,a4 - 2dc: fc0792e3 bnez a5,2a0 - 2e0: 00008067 ret - 2e4: 00000513 li a0,0 - 2e8: 00008067 ret +000000000000028c <_e8_32x32_matmul>: + 28c: 02000793 li a5,32 + 290: 0c07f057 vsetvli zero,a5,e8,m1,ta,ma + 294: 02000813 li a6,32 + 298: 00050893 mv a7,a0 + 29c: 40050313 add t1,a0,1024 + 2a0: 02000513 li a0,32 + 2a4: 02088087 vle8.v v1,(a7) + 2a8: 42006257 vmv.s.x v4,zero + 2ac: 00000793 li a5,0 + 2b0: 00f58733 add a4,a1,a5 + 2b4: 0b070107 vlse8.v v2,(a4),a6 + 2b8: 961121d7 vmul.vv v3,v1,v2 + 2bc: 023221d7 vredsum.vs v3,v3,v4 + 2c0: 423026d7 vmv.x.s a3,v3 + 2c4: 0007871b sext.w a4,a5 + 2c8: 00e60733 add a4,a2,a4 + 2cc: 00d70023 sb a3,0(a4) + 2d0: 00178793 add a5,a5,1 + 2d4: fca79ee3 bne a5,a0,2b0 <_e8_32x32_matmul+0x24> + 2d8: 02088893 add a7,a7,32 + 2dc: 02060613 add a2,a2,32 + 2e0: fc6892e3 bne a7,t1,2a4 <_e8_32x32_matmul+0x18> + 2e4: 00008067 ret -00000000000002ec : - 2ec: b0201073 csrw minstret,zero - 2f0: b0001073 csrw mcycle,zero - 2f4: 00008067 ret +00000000000002e8 : + 2e8: b0201073 csrw minstret,zero + 2ec: b0001073 csrw mcycle,zero + 2f0: 00008067 ret -00000000000002f8 : - 2f8: 03000793 li a5,48 - 2fc: 00f58023 sb a5,0(a1) - 300: 07800793 li a5,120 - 304: 00f580a3 sb a5,1(a1) - 308: 00158813 add a6,a1,1 - 30c: 00958793 add a5,a1,9 - 310: 00900613 li a2,9 - 314: 00f57713 and a4,a0,15 - 318: 03770693 add a3,a4,55 - 31c: 00e66463 bltu a2,a4,324 - 320: 03070693 add a3,a4,48 - 324: 00d78023 sb a3,0(a5) - 328: fff78793 add a5,a5,-1 - 32c: 40455513 sra a0,a0,0x4 - 330: fef812e3 bne a6,a5,314 - 334: 00058523 sb zero,10(a1) - 338: 00008067 ret +00000000000002f4 : + 2f4: 03000793 li a5,48 + 2f8: 00f58023 sb a5,0(a1) + 2fc: 07800793 li a5,120 + 300: 00f580a3 sb a5,1(a1) + 304: 00158813 add a6,a1,1 + 308: 00958793 add a5,a1,9 + 30c: 00900613 li a2,9 + 310: 00f57713 and a4,a0,15 + 314: 03770693 add a3,a4,55 + 318: 00e66463 bltu a2,a4,320 + 31c: 03070693 add a3,a4,48 + 320: 00d78023 sb a3,0(a5) + 324: fff78793 add a5,a5,-1 + 328: 40455513 sra a0,a0,0x4 + 32c: fef812e3 bne a6,a5,310 + 330: 00058523 sb zero,10(a1) + 334: 00008067 ret -000000000000033c : - 33c: 03000793 li a5,48 - 340: 00f58023 sb a5,0(a1) - 344: 07800793 li a5,120 - 348: 00f580a3 sb a5,1(a1) - 34c: 00158813 add a6,a1,1 - 350: 01158793 add a5,a1,17 - 354: 00900613 li a2,9 - 358: 00f57713 and a4,a0,15 - 35c: 03770693 add a3,a4,55 - 360: 00e66463 bltu a2,a4,368 - 364: 03070693 add a3,a4,48 - 368: 00d78023 sb a3,0(a5) - 36c: fff78793 add a5,a5,-1 - 370: 40455513 sra a0,a0,0x4 - 374: fef812e3 bne a6,a5,358 - 378: 00058923 sb zero,18(a1) - 37c: 00008067 ret +0000000000000338 : + 338: 03000793 li a5,48 + 33c: 00f58023 sb a5,0(a1) + 340: 07800793 li a5,120 + 344: 00f580a3 sb a5,1(a1) + 348: 00158813 add a6,a1,1 + 34c: 01158793 add a5,a1,17 + 350: 00900613 li a2,9 + 354: 00f57713 and a4,a0,15 + 358: 03770693 add a3,a4,55 + 35c: 00e66463 bltu a2,a4,364 + 360: 03070693 add a3,a4,48 + 364: 00d78023 sb a3,0(a5) + 368: fff78793 add a5,a5,-1 + 36c: 40455513 sra a0,a0,0x4 + 370: fef812e3 bne a6,a5,354 + 374: 00058923 sb zero,18(a1) + 378: 00008067 ret -0000000000000380 : - 380: 00054783 lbu a5,0(a0) - 384: 00078c63 beqz a5,39c - 388: 10000737 lui a4,0x10000 - 38c: 00f70023 sb a5,0(a4) # 10000000 - 390: 00154783 lbu a5,1(a0) - 394: 00150513 add a0,a0,1 - 398: fe079ae3 bnez a5,38c - 39c: 00008067 ret +000000000000037c : + 37c: 00054783 lbu a5,0(a0) + 380: 00078c63 beqz a5,398 + 384: 10000737 lui a4,0x10000 + 388: 00f70023 sb a5,0(a4) # 10000000 + 38c: 00154783 lbu a5,1(a0) + 390: 00150513 add a0,a0,1 + 394: fe079ae3 bnez a5,388 + 398: 00008067 ret -00000000000003a0 : - 3a0: fe010113 add sp,sp,-32 - 3a4: c0202673 rdinstret a2 - 3a8: c00025f3 rdcycle a1 - 3ac: 00004717 auipc a4,0x4 - 3b0: 13470713 add a4,a4,308 # 44e0 - 3b4: 06300793 li a5,99 - 3b8: 100006b7 lui a3,0x10000 - 3bc: 00f68023 sb a5,0(a3) # 10000000 - 3c0: 00174783 lbu a5,1(a4) - 3c4: 00170713 add a4,a4,1 - 3c8: fe079ae3 bnez a5,3bc - 3cc: ffff8737 lui a4,0xffff8 - 3d0: 83074713 xor a4,a4,-2000 - 3d4: 01910793 add a5,sp,25 - 3d8: 00e11423 sh a4,8(sp) - 3dc: 00910813 add a6,sp,9 - 3e0: 00078713 mv a4,a5 - 3e4: 00900893 li a7,9 - 3e8: 00f5f693 and a3,a1,15 - 3ec: 03768513 add a0,a3,55 - 3f0: 00d8e463 bltu a7,a3,3f8 - 3f4: 03068513 add a0,a3,48 - 3f8: 00a70023 sb a0,0(a4) # ffffffffffff8000 <_end+0xffffffffefff7fb8> - 3fc: fff70713 add a4,a4,-1 - 400: 4045d593 sra a1,a1,0x4 - 404: fee812e3 bne a6,a4,3e8 - 408: 00814703 lbu a4,8(sp) - 40c: 00010d23 sb zero,26(sp) - 410: 00810693 add a3,sp,8 - 414: 100005b7 lui a1,0x10000 - 418: 00070a63 beqz a4,42c - 41c: 00e58023 sb a4,0(a1) # 10000000 - 420: 0016c703 lbu a4,1(a3) - 424: 00168693 add a3,a3,1 - 428: fe071ae3 bnez a4,41c - 42c: 00004697 auipc a3,0x4 - 430: 0bc68693 add a3,a3,188 # 44e8 - 434: 00a00713 li a4,10 - 438: 100005b7 lui a1,0x10000 - 43c: 00e58023 sb a4,0(a1) # 10000000 - 440: 0016c703 lbu a4,1(a3) - 444: 00168693 add a3,a3,1 - 448: fe071ae3 bnez a4,43c - 44c: ffff8737 lui a4,0xffff8 - 450: 83074713 xor a4,a4,-2000 - 454: 00060693 mv a3,a2 - 458: 00e11423 sh a4,8(sp) - 45c: 00900593 li a1,9 - 460: 00f6f713 and a4,a3,15 - 464: 03770613 add a2,a4,55 # ffffffffffff8037 <_end+0xffffffffefff7fef> - 468: 00e5e463 bltu a1,a4,470 - 46c: 03070613 add a2,a4,48 - 470: 00c78023 sb a2,0(a5) - 474: fff78793 add a5,a5,-1 - 478: 4046d693 sra a3,a3,0x4 - 47c: fef812e3 bne a6,a5,460 - 480: 00814783 lbu a5,8(sp) - 484: 00010d23 sb zero,26(sp) - 488: 00810713 add a4,sp,8 - 48c: 100006b7 lui a3,0x10000 - 490: 00078a63 beqz a5,4a4 - 494: 00f68023 sb a5,0(a3) # 10000000 - 498: 00174783 lbu a5,1(a4) - 49c: 00170713 add a4,a4,1 - 4a0: fe079ae3 bnez a5,494 - 4a4: 100007b7 lui a5,0x10000 - 4a8: 00a00713 li a4,10 - 4ac: 00e78023 sb a4,0(a5) # 10000000 - 4b0: 02010113 add sp,sp,32 - 4b4: 00008067 ret +000000000000039c : + 39c: fe010113 add sp,sp,-32 + 3a0: c0202673 rdinstret a2 + 3a4: c00025f3 rdcycle a1 + 3a8: 00004717 auipc a4,0x4 + 3ac: 4b870713 add a4,a4,1208 # 4860 + 3b0: 06300793 li a5,99 + 3b4: 100006b7 lui a3,0x10000 + 3b8: 00f68023 sb a5,0(a3) # 10000000 + 3bc: 00174783 lbu a5,1(a4) + 3c0: 00170713 add a4,a4,1 + 3c4: fe079ae3 bnez a5,3b8 + 3c8: ffff8737 lui a4,0xffff8 + 3cc: 83074713 xor a4,a4,-2000 + 3d0: 01910793 add a5,sp,25 + 3d4: 00e11423 sh a4,8(sp) + 3d8: 00910813 add a6,sp,9 + 3dc: 00078713 mv a4,a5 + 3e0: 00900893 li a7,9 + 3e4: 00f5f693 and a3,a1,15 + 3e8: 03768513 add a0,a3,55 + 3ec: 00d8e463 bltu a7,a3,3f4 + 3f0: 03068513 add a0,a3,48 + 3f4: 00a70023 sb a0,0(a4) # ffffffffffff8000 <_end+0xffffffffefff7fb8> + 3f8: fff70713 add a4,a4,-1 + 3fc: 4045d593 sra a1,a1,0x4 + 400: fee812e3 bne a6,a4,3e4 + 404: 00814703 lbu a4,8(sp) + 408: 00010d23 sb zero,26(sp) + 40c: 00810693 add a3,sp,8 + 410: 100005b7 lui a1,0x10000 + 414: 00070a63 beqz a4,428 + 418: 00e58023 sb a4,0(a1) # 10000000 + 41c: 0016c703 lbu a4,1(a3) + 420: 00168693 add a3,a3,1 + 424: fe071ae3 bnez a4,418 + 428: 00004697 auipc a3,0x4 + 42c: 44068693 add a3,a3,1088 # 4868 + 430: 00a00713 li a4,10 + 434: 100005b7 lui a1,0x10000 + 438: 00e58023 sb a4,0(a1) # 10000000 + 43c: 0016c703 lbu a4,1(a3) + 440: 00168693 add a3,a3,1 + 444: fe071ae3 bnez a4,438 + 448: ffff8737 lui a4,0xffff8 + 44c: 83074713 xor a4,a4,-2000 + 450: 00060693 mv a3,a2 + 454: 00e11423 sh a4,8(sp) + 458: 00900593 li a1,9 + 45c: 00f6f713 and a4,a3,15 + 460: 03770613 add a2,a4,55 # ffffffffffff8037 <_end+0xffffffffefff7fef> + 464: 00e5e463 bltu a1,a4,46c + 468: 03070613 add a2,a4,48 + 46c: 00c78023 sb a2,0(a5) + 470: fff78793 add a5,a5,-1 + 474: 4046d693 sra a3,a3,0x4 + 478: fef812e3 bne a6,a5,45c + 47c: 00814783 lbu a5,8(sp) + 480: 00010d23 sb zero,26(sp) + 484: 00810713 add a4,sp,8 + 488: 100006b7 lui a3,0x10000 + 48c: 00078a63 beqz a5,4a0 + 490: 00f68023 sb a5,0(a3) # 10000000 + 494: 00174783 lbu a5,1(a4) + 498: 00170713 add a4,a4,1 + 49c: fe079ae3 bnez a5,490 + 4a0: 100007b7 lui a5,0x10000 + 4a4: 00a00713 li a4,10 + 4a8: 00e78023 sb a4,0(a5) # 10000000 + 4ac: 02010113 add sp,sp,32 + 4b0: 00008067 ret -00000000000004b8 : - 4b8: fe010113 add sp,sp,-32 - 4bc: 00813823 sd s0,16(sp) - 4c0: 00113c23 sd ra,24(sp) - 4c4: 00050413 mv s0,a0 - 4c8: 00004717 auipc a4,0x4 - 4cc: 03070713 add a4,a4,48 # 44f8 - 4d0: 04500793 li a5,69 - 4d4: 100006b7 lui a3,0x10000 - 4d8: 00f68023 sb a5,0(a3) # 10000000 - 4dc: 00174783 lbu a5,1(a4) - 4e0: 00170713 add a4,a4,1 - 4e4: fe079ae3 bnez a5,4d8 - 4e8: 00010593 mv a1,sp - 4ec: 00040513 mv a0,s0 - 4f0: e09ff0ef jal 2f8 - 4f4: 00014703 lbu a4,0(sp) - 4f8: 00070e63 beqz a4,514 - 4fc: 00010793 mv a5,sp - 500: 100006b7 lui a3,0x10000 - 504: 00e68023 sb a4,0(a3) # 10000000 - 508: 0017c703 lbu a4,1(a5) - 50c: 00178793 add a5,a5,1 - 510: fe071ae3 bnez a4,504 - 514: 00040513 mv a0,s0 - 518: 100007b7 lui a5,0x10000 - 51c: 00078023 sb zero,0(a5) # 10000000 - 520: 0000006f j 520 +00000000000004b4 : + 4b4: fe010113 add sp,sp,-32 + 4b8: 00813823 sd s0,16(sp) + 4bc: 00113c23 sd ra,24(sp) + 4c0: 00050413 mv s0,a0 + 4c4: 00004717 auipc a4,0x4 + 4c8: 3b470713 add a4,a4,948 # 4878 + 4cc: 04500793 li a5,69 + 4d0: 100006b7 lui a3,0x10000 + 4d4: 00f68023 sb a5,0(a3) # 10000000 + 4d8: 00174783 lbu a5,1(a4) + 4dc: 00170713 add a4,a4,1 + 4e0: fe079ae3 bnez a5,4d4 + 4e4: 00010593 mv a1,sp + 4e8: 00040513 mv a0,s0 + 4ec: e09ff0ef jal 2f4 + 4f0: 00014703 lbu a4,0(sp) + 4f4: 00070e63 beqz a4,510 + 4f8: 00010793 mv a5,sp + 4fc: 100006b7 lui a3,0x10000 + 500: 00e68023 sb a4,0(a3) # 10000000 + 504: 0017c703 lbu a4,1(a5) + 508: 00178793 add a5,a5,1 + 50c: fe071ae3 bnez a4,500 + 510: 00040513 mv a0,s0 + 514: 100007b7 lui a5,0x10000 + 518: 00078023 sb zero,0(a5) # 10000000 + 51c: 0000006f j 51c -0000000000000524 : - 524: ffff87b7 lui a5,0xffff8 - 528: fd010113 add sp,sp,-48 - 52c: 8307c793 xor a5,a5,-2000 - 530: 00f11423 sh a5,8(sp) - 534: 02113423 sd ra,40(sp) - 538: 01910793 add a5,sp,25 - 53c: 00910813 add a6,sp,9 - 540: 00900613 li a2,9 - 544: 00f5f713 and a4,a1,15 - 548: 03770693 add a3,a4,55 - 54c: 00e66463 bltu a2,a4,554 - 550: 03070693 add a3,a4,48 - 554: 00d78023 sb a3,0(a5) # ffffffffffff8000 <_end+0xffffffffefff7fb8> - 558: fff78793 add a5,a5,-1 - 55c: 4045d593 sra a1,a1,0x4 - 560: ff0792e3 bne a5,a6,544 - 564: 00010d23 sb zero,26(sp) - 568: 00b00793 li a5,11 - 56c: 02a7e063 bltu a5,a0,58c - 570: 00004717 auipc a4,0x4 - 574: f1070713 add a4,a4,-240 # 4480 - 578: 00251513 sll a0,a0,0x2 - 57c: 00e50533 add a0,a0,a4 - 580: 00052783 lw a5,0(a0) - 584: 00e787b3 add a5,a5,a4 - 588: 00078067 jr a5 - 58c: 00004717 auipc a4,0x4 - 590: 09470713 add a4,a4,148 # 4620 - 594: 05500793 li a5,85 - 598: 100006b7 lui a3,0x10000 - 59c: 00f68023 sb a5,0(a3) # 10000000 - 5a0: 00174783 lbu a5,1(a4) - 5a4: 00170713 add a4,a4,1 - 5a8: fe079ae3 bnez a5,59c - 5ac: 00814783 lbu a5,8(sp) - 5b0: 00810713 add a4,sp,8 - 5b4: 100006b7 lui a3,0x10000 - 5b8: 00078a63 beqz a5,5cc - 5bc: 00f68023 sb a5,0(a3) # 10000000 - 5c0: 00174783 lbu a5,1(a4) - 5c4: 00170713 add a4,a4,1 - 5c8: fe079ae3 bnez a5,5bc - 5cc: 00004717 auipc a4,0x4 - 5d0: 07470713 add a4,a4,116 # 4640 - 5d4: 00a00793 li a5,10 - 5d8: 100006b7 lui a3,0x10000 - 5dc: 00f68023 sb a5,0(a3) # 10000000 - 5e0: 00174783 lbu a5,1(a4) - 5e4: 00170713 add a4,a4,1 - 5e8: fe079ae3 bnez a5,5dc - 5ec: fff00513 li a0,-1 - 5f0: ec9ff0ef jal 4b8 - 5f4: 00004717 auipc a4,0x4 - 5f8: f1470713 add a4,a4,-236 # 4508 - 5fc: 04900793 li a5,73 - 600: 100006b7 lui a3,0x10000 - 604: 00f68023 sb a5,0(a3) # 10000000 - 608: 00174783 lbu a5,1(a4) - 60c: 00170713 add a4,a4,1 - 610: fe079ae3 bnez a5,604 - 614: 00814783 lbu a5,8(sp) - 618: 00810713 add a4,sp,8 - 61c: 100006b7 lui a3,0x10000 - 620: fc0786e3 beqz a5,5ec - 624: 00f68023 sb a5,0(a3) # 10000000 - 628: 00174783 lbu a5,1(a4) - 62c: 00170713 add a4,a4,1 - 630: fe079ae3 bnez a5,624 - 634: fb9ff06f j 5ec - 638: 00004717 auipc a4,0x4 - 63c: ef870713 add a4,a4,-264 # 4530 - 640: 04900793 li a5,73 - 644: 100006b7 lui a3,0x10000 - 648: 00f68023 sb a5,0(a3) # 10000000 - 64c: 00174783 lbu a5,1(a4) - 650: 00170713 add a4,a4,1 - 654: fe079ae3 bnez a5,648 - 658: 00814783 lbu a5,8(sp) - 65c: f80788e3 beqz a5,5ec - 660: 00810713 add a4,sp,8 - 664: 100006b7 lui a3,0x10000 - 668: 00f68023 sb a5,0(a3) # 10000000 - 66c: 00174783 lbu a5,1(a4) - 670: 00170713 add a4,a4,1 - 674: fe079ae3 bnez a5,668 - 678: f75ff06f j 5ec - 67c: 00004717 auipc a4,0x4 - 680: edc70713 add a4,a4,-292 # 4558 - 684: 04900793 li a5,73 - 688: 100006b7 lui a3,0x10000 - 68c: 00f68023 sb a5,0(a3) # 10000000 - 690: 00174783 lbu a5,1(a4) - 694: 00170713 add a4,a4,1 - 698: fe079ae3 bnez a5,68c - 69c: 00814783 lbu a5,8(sp) - 6a0: f40786e3 beqz a5,5ec - 6a4: 00810713 add a4,sp,8 - 6a8: 100006b7 lui a3,0x10000 - 6ac: 00f68023 sb a5,0(a3) # 10000000 - 6b0: 00174783 lbu a5,1(a4) - 6b4: 00170713 add a4,a4,1 - 6b8: fe079ae3 bnez a5,6ac - 6bc: f31ff06f j 5ec - 6c0: 00004717 auipc a4,0x4 - 6c4: eb870713 add a4,a4,-328 # 4578 - 6c8: 04c00793 li a5,76 - 6cc: 100006b7 lui a3,0x10000 - 6d0: 00f68023 sb a5,0(a3) # 10000000 - 6d4: 00174783 lbu a5,1(a4) - 6d8: 00170713 add a4,a4,1 - 6dc: fe079ae3 bnez a5,6d0 - 6e0: 00814783 lbu a5,8(sp) - 6e4: f00784e3 beqz a5,5ec - 6e8: 00810713 add a4,sp,8 - 6ec: 100006b7 lui a3,0x10000 - 6f0: 00f68023 sb a5,0(a3) # 10000000 - 6f4: 00174783 lbu a5,1(a4) - 6f8: 00170713 add a4,a4,1 - 6fc: fe079ae3 bnez a5,6f0 - 700: eedff06f j 5ec - 704: 00004717 auipc a4,0x4 - 708: e9470713 add a4,a4,-364 # 4598 - 70c: 04c00793 li a5,76 - 710: 100006b7 lui a3,0x10000 - 714: 00f68023 sb a5,0(a3) # 10000000 - 718: 00174783 lbu a5,1(a4) - 71c: 00170713 add a4,a4,1 - 720: fe079ae3 bnez a5,714 - 724: 00814783 lbu a5,8(sp) - 728: ec0782e3 beqz a5,5ec - 72c: 00810713 add a4,sp,8 - 730: 100006b7 lui a3,0x10000 - 734: 00f68023 sb a5,0(a3) # 10000000 - 738: 00174783 lbu a5,1(a4) - 73c: 00170713 add a4,a4,1 - 740: fe079ae3 bnez a5,734 - 744: ea9ff06f j 5ec - 748: 00004717 auipc a4,0x4 - 74c: e7070713 add a4,a4,-400 # 45b8 - 750: 05300793 li a5,83 - 754: 100006b7 lui a3,0x10000 - 758: 00f68023 sb a5,0(a3) # 10000000 - 75c: 00174783 lbu a5,1(a4) - 760: 00170713 add a4,a4,1 - 764: fe079ae3 bnez a5,758 - 768: 00814783 lbu a5,8(sp) - 76c: e80780e3 beqz a5,5ec - 770: 00810713 add a4,sp,8 - 774: 100006b7 lui a3,0x10000 - 778: 00f68023 sb a5,0(a3) # 10000000 - 77c: 00174783 lbu a5,1(a4) - 780: 00170713 add a4,a4,1 - 784: fe079ae3 bnez a5,778 - 788: e65ff06f j 5ec - 78c: 00004717 auipc a4,0x4 - 790: e5470713 add a4,a4,-428 # 45e0 - 794: 05300793 li a5,83 - 798: 100006b7 lui a3,0x10000 - 79c: 00f68023 sb a5,0(a3) # 10000000 - 7a0: 00174783 lbu a5,1(a4) - 7a4: 00170713 add a4,a4,1 - 7a8: fe079ae3 bnez a5,79c - 7ac: 00814783 lbu a5,8(sp) - 7b0: e2078ee3 beqz a5,5ec - 7b4: 00810713 add a4,sp,8 - 7b8: 100006b7 lui a3,0x10000 - 7bc: 00f68023 sb a5,0(a3) # 10000000 - 7c0: 00174783 lbu a5,1(a4) - 7c4: 00170713 add a4,a4,1 - 7c8: fe079ae3 bnez a5,7bc - 7cc: e21ff06f j 5ec - 7d0: 00004717 auipc a4,0x4 - 7d4: e3070713 add a4,a4,-464 # 4600 - 7d8: 04500793 li a5,69 - 7dc: 100006b7 lui a3,0x10000 - 7e0: 00f68023 sb a5,0(a3) # 10000000 - 7e4: 00174783 lbu a5,1(a4) - 7e8: 00170713 add a4,a4,1 - 7ec: fe079ae3 bnez a5,7e0 - 7f0: 00814783 lbu a5,8(sp) - 7f4: de078ce3 beqz a5,5ec - 7f8: 00810713 add a4,sp,8 - 7fc: 100006b7 lui a3,0x10000 - 800: 00f68023 sb a5,0(a3) # 10000000 - 804: 00174783 lbu a5,1(a4) - 808: 00170713 add a4,a4,1 - 80c: fe079ae3 bnez a5,800 - 810: dddff06f j 5ec +0000000000000520 : + 520: ffff87b7 lui a5,0xffff8 + 524: fd010113 add sp,sp,-48 + 528: 8307c793 xor a5,a5,-2000 + 52c: 00f11423 sh a5,8(sp) + 530: 02113423 sd ra,40(sp) + 534: 01910793 add a5,sp,25 + 538: 00910813 add a6,sp,9 + 53c: 00900613 li a2,9 + 540: 00f5f713 and a4,a1,15 + 544: 03770693 add a3,a4,55 + 548: 00e66463 bltu a2,a4,550 + 54c: 03070693 add a3,a4,48 + 550: 00d78023 sb a3,0(a5) # ffffffffffff8000 <_end+0xffffffffefff7fb8> + 554: fff78793 add a5,a5,-1 + 558: 4045d593 sra a1,a1,0x4 + 55c: ff0792e3 bne a5,a6,540 + 560: 00010d23 sb zero,26(sp) + 564: 00b00793 li a5,11 + 568: 02a7e063 bltu a5,a0,588 + 56c: 00004717 auipc a4,0x4 + 570: 29470713 add a4,a4,660 # 4800 + 574: 00251513 sll a0,a0,0x2 + 578: 00e50533 add a0,a0,a4 + 57c: 00052783 lw a5,0(a0) + 580: 00e787b3 add a5,a5,a4 + 584: 00078067 jr a5 + 588: 00004717 auipc a4,0x4 + 58c: 41870713 add a4,a4,1048 # 49a0 + 590: 05500793 li a5,85 + 594: 100006b7 lui a3,0x10000 + 598: 00f68023 sb a5,0(a3) # 10000000 + 59c: 00174783 lbu a5,1(a4) + 5a0: 00170713 add a4,a4,1 + 5a4: fe079ae3 bnez a5,598 + 5a8: 00814783 lbu a5,8(sp) + 5ac: 00810713 add a4,sp,8 + 5b0: 100006b7 lui a3,0x10000 + 5b4: 00078a63 beqz a5,5c8 + 5b8: 00f68023 sb a5,0(a3) # 10000000 + 5bc: 00174783 lbu a5,1(a4) + 5c0: 00170713 add a4,a4,1 + 5c4: fe079ae3 bnez a5,5b8 + 5c8: 00004717 auipc a4,0x4 + 5cc: 3f870713 add a4,a4,1016 # 49c0 + 5d0: 00a00793 li a5,10 + 5d4: 100006b7 lui a3,0x10000 + 5d8: 00f68023 sb a5,0(a3) # 10000000 + 5dc: 00174783 lbu a5,1(a4) + 5e0: 00170713 add a4,a4,1 + 5e4: fe079ae3 bnez a5,5d8 + 5e8: fff00513 li a0,-1 + 5ec: ec9ff0ef jal 4b4 + 5f0: 00004717 auipc a4,0x4 + 5f4: 29870713 add a4,a4,664 # 4888 + 5f8: 04900793 li a5,73 + 5fc: 100006b7 lui a3,0x10000 + 600: 00f68023 sb a5,0(a3) # 10000000 + 604: 00174783 lbu a5,1(a4) + 608: 00170713 add a4,a4,1 + 60c: fe079ae3 bnez a5,600 + 610: 00814783 lbu a5,8(sp) + 614: 00810713 add a4,sp,8 + 618: 100006b7 lui a3,0x10000 + 61c: fc0786e3 beqz a5,5e8 + 620: 00f68023 sb a5,0(a3) # 10000000 + 624: 00174783 lbu a5,1(a4) + 628: 00170713 add a4,a4,1 + 62c: fe079ae3 bnez a5,620 + 630: fb9ff06f j 5e8 + 634: 00004717 auipc a4,0x4 + 638: 27c70713 add a4,a4,636 # 48b0 + 63c: 04900793 li a5,73 + 640: 100006b7 lui a3,0x10000 + 644: 00f68023 sb a5,0(a3) # 10000000 + 648: 00174783 lbu a5,1(a4) + 64c: 00170713 add a4,a4,1 + 650: fe079ae3 bnez a5,644 + 654: 00814783 lbu a5,8(sp) + 658: f80788e3 beqz a5,5e8 + 65c: 00810713 add a4,sp,8 + 660: 100006b7 lui a3,0x10000 + 664: 00f68023 sb a5,0(a3) # 10000000 + 668: 00174783 lbu a5,1(a4) + 66c: 00170713 add a4,a4,1 + 670: fe079ae3 bnez a5,664 + 674: f75ff06f j 5e8 + 678: 00004717 auipc a4,0x4 + 67c: 26070713 add a4,a4,608 # 48d8 + 680: 04900793 li a5,73 + 684: 100006b7 lui a3,0x10000 + 688: 00f68023 sb a5,0(a3) # 10000000 + 68c: 00174783 lbu a5,1(a4) + 690: 00170713 add a4,a4,1 + 694: fe079ae3 bnez a5,688 + 698: 00814783 lbu a5,8(sp) + 69c: f40786e3 beqz a5,5e8 + 6a0: 00810713 add a4,sp,8 + 6a4: 100006b7 lui a3,0x10000 + 6a8: 00f68023 sb a5,0(a3) # 10000000 + 6ac: 00174783 lbu a5,1(a4) + 6b0: 00170713 add a4,a4,1 + 6b4: fe079ae3 bnez a5,6a8 + 6b8: f31ff06f j 5e8 + 6bc: 00004717 auipc a4,0x4 + 6c0: 23c70713 add a4,a4,572 # 48f8 + 6c4: 04c00793 li a5,76 + 6c8: 100006b7 lui a3,0x10000 + 6cc: 00f68023 sb a5,0(a3) # 10000000 + 6d0: 00174783 lbu a5,1(a4) + 6d4: 00170713 add a4,a4,1 + 6d8: fe079ae3 bnez a5,6cc + 6dc: 00814783 lbu a5,8(sp) + 6e0: f00784e3 beqz a5,5e8 + 6e4: 00810713 add a4,sp,8 + 6e8: 100006b7 lui a3,0x10000 + 6ec: 00f68023 sb a5,0(a3) # 10000000 + 6f0: 00174783 lbu a5,1(a4) + 6f4: 00170713 add a4,a4,1 + 6f8: fe079ae3 bnez a5,6ec + 6fc: eedff06f j 5e8 + 700: 00004717 auipc a4,0x4 + 704: 21870713 add a4,a4,536 # 4918 + 708: 04c00793 li a5,76 + 70c: 100006b7 lui a3,0x10000 + 710: 00f68023 sb a5,0(a3) # 10000000 + 714: 00174783 lbu a5,1(a4) + 718: 00170713 add a4,a4,1 + 71c: fe079ae3 bnez a5,710 + 720: 00814783 lbu a5,8(sp) + 724: ec0782e3 beqz a5,5e8 + 728: 00810713 add a4,sp,8 + 72c: 100006b7 lui a3,0x10000 + 730: 00f68023 sb a5,0(a3) # 10000000 + 734: 00174783 lbu a5,1(a4) + 738: 00170713 add a4,a4,1 + 73c: fe079ae3 bnez a5,730 + 740: ea9ff06f j 5e8 + 744: 00004717 auipc a4,0x4 + 748: 1f470713 add a4,a4,500 # 4938 + 74c: 05300793 li a5,83 + 750: 100006b7 lui a3,0x10000 + 754: 00f68023 sb a5,0(a3) # 10000000 + 758: 00174783 lbu a5,1(a4) + 75c: 00170713 add a4,a4,1 + 760: fe079ae3 bnez a5,754 + 764: 00814783 lbu a5,8(sp) + 768: e80780e3 beqz a5,5e8 + 76c: 00810713 add a4,sp,8 + 770: 100006b7 lui a3,0x10000 + 774: 00f68023 sb a5,0(a3) # 10000000 + 778: 00174783 lbu a5,1(a4) + 77c: 00170713 add a4,a4,1 + 780: fe079ae3 bnez a5,774 + 784: e65ff06f j 5e8 + 788: 00004717 auipc a4,0x4 + 78c: 1d870713 add a4,a4,472 # 4960 + 790: 05300793 li a5,83 + 794: 100006b7 lui a3,0x10000 + 798: 00f68023 sb a5,0(a3) # 10000000 + 79c: 00174783 lbu a5,1(a4) + 7a0: 00170713 add a4,a4,1 + 7a4: fe079ae3 bnez a5,798 + 7a8: 00814783 lbu a5,8(sp) + 7ac: e2078ee3 beqz a5,5e8 + 7b0: 00810713 add a4,sp,8 + 7b4: 100006b7 lui a3,0x10000 + 7b8: 00f68023 sb a5,0(a3) # 10000000 + 7bc: 00174783 lbu a5,1(a4) + 7c0: 00170713 add a4,a4,1 + 7c4: fe079ae3 bnez a5,7b8 + 7c8: e21ff06f j 5e8 + 7cc: 00004717 auipc a4,0x4 + 7d0: 1b470713 add a4,a4,436 # 4980 + 7d4: 04500793 li a5,69 + 7d8: 100006b7 lui a3,0x10000 + 7dc: 00f68023 sb a5,0(a3) # 10000000 + 7e0: 00174783 lbu a5,1(a4) + 7e4: 00170713 add a4,a4,1 + 7e8: fe079ae3 bnez a5,7dc + 7ec: 00814783 lbu a5,8(sp) + 7f0: de078ce3 beqz a5,5e8 + 7f4: 00810713 add a4,sp,8 + 7f8: 100006b7 lui a3,0x10000 + 7fc: 00f68023 sb a5,0(a3) # 10000000 + 800: 00174783 lbu a5,1(a4) + 804: 00170713 add a4,a4,1 + 808: fe079ae3 bnez a5,7fc + 80c: dddff06f j 5e8 -0000000000000814 : - 814: 00051063 bnez a0,814 - 818: 00008067 ret +0000000000000810 : + 810: 00051063 bnez a0,810 + 814: 00008067 ret -000000000000081c <_init>: - 81c: ff010113 add sp,sp,-16 - 820: 00000593 li a1,0 - 824: 00000513 li a0,0 - 828: 00113423 sd ra,8(sp) - 82c: 1d8000ef jal a04
- 830: c89ff0ef jal 4b8 +0000000000000818 <_init>: + 818: ff010113 add sp,sp,-16 + 81c: 00000593 li a1,0 + 820: 00000513 li a0,0 + 824: 00113423 sd ra,8(sp) + 828: 1d8000ef jal a00
+ 82c: c89ff0ef jal 4b4 -0000000000000834 : - 834: 00b567b3 or a5,a0,a1 - 838: 00c7e7b3 or a5,a5,a2 - 83c: 0077f793 and a5,a5,7 - 840: 00c50833 add a6,a0,a2 - 844: 02078463 beqz a5,86c - 848: 00c58633 add a2,a1,a2 - 84c: 00050793 mv a5,a0 - 850: 0b057663 bgeu a0,a6,8fc - 854: 0005c703 lbu a4,0(a1) - 858: 00158593 add a1,a1,1 - 85c: 00178793 add a5,a5,1 - 860: fee78fa3 sb a4,-1(a5) - 864: fec598e3 bne a1,a2,854 - 868: 00008067 ret - 86c: 04050693 add a3,a0,64 - 870: 0906f863 bgeu a3,a6,900 - 874: 00058713 mv a4,a1 - 878: 00068793 mv a5,a3 - 87c: 00073383 ld t2,0(a4) - 880: 00873283 ld t0,8(a4) - 884: 01073f83 ld t6,16(a4) - 888: 01873f03 ld t5,24(a4) - 88c: 02073e83 ld t4,32(a4) - 890: 02873e03 ld t3,40(a4) - 894: 03073303 ld t1,48(a4) - 898: 03873883 ld a7,56(a4) - 89c: 04078793 add a5,a5,64 - 8a0: f877b023 sd t2,-128(a5) - 8a4: f857b423 sd t0,-120(a5) - 8a8: f9f7b823 sd t6,-112(a5) - 8ac: f9e7bc23 sd t5,-104(a5) - 8b0: fbd7b023 sd t4,-96(a5) - 8b4: fbc7b423 sd t3,-88(a5) - 8b8: fa67b823 sd t1,-80(a5) - 8bc: fb17bc23 sd a7,-72(a5) - 8c0: 04070713 add a4,a4,64 - 8c4: fb07ece3 bltu a5,a6,87c - 8c8: fbf60613 add a2,a2,-65 - 8cc: fc067793 and a5,a2,-64 - 8d0: 04078793 add a5,a5,64 - 8d4: fc067613 and a2,a2,-64 - 8d8: 00f585b3 add a1,a1,a5 - 8dc: 00c687b3 add a5,a3,a2 - 8e0: f907f4e3 bgeu a5,a6,868 - 8e4: 0005b703 ld a4,0(a1) - 8e8: 00878793 add a5,a5,8 - 8ec: 00858593 add a1,a1,8 - 8f0: fee7bc23 sd a4,-8(a5) - 8f4: ff07e8e3 bltu a5,a6,8e4 +0000000000000830 : + 830: 00b567b3 or a5,a0,a1 + 834: 00c7e7b3 or a5,a5,a2 + 838: 0077f793 and a5,a5,7 + 83c: 00c50833 add a6,a0,a2 + 840: 02078463 beqz a5,868 + 844: 00c58633 add a2,a1,a2 + 848: 00050793 mv a5,a0 + 84c: 0b057663 bgeu a0,a6,8f8 + 850: 0005c703 lbu a4,0(a1) + 854: 00158593 add a1,a1,1 + 858: 00178793 add a5,a5,1 + 85c: fee78fa3 sb a4,-1(a5) + 860: fec598e3 bne a1,a2,850 + 864: 00008067 ret + 868: 04050693 add a3,a0,64 + 86c: 0906f863 bgeu a3,a6,8fc + 870: 00058713 mv a4,a1 + 874: 00068793 mv a5,a3 + 878: 00073383 ld t2,0(a4) + 87c: 00873283 ld t0,8(a4) + 880: 01073f83 ld t6,16(a4) + 884: 01873f03 ld t5,24(a4) + 888: 02073e83 ld t4,32(a4) + 88c: 02873e03 ld t3,40(a4) + 890: 03073303 ld t1,48(a4) + 894: 03873883 ld a7,56(a4) + 898: 04078793 add a5,a5,64 + 89c: f877b023 sd t2,-128(a5) + 8a0: f857b423 sd t0,-120(a5) + 8a4: f9f7b823 sd t6,-112(a5) + 8a8: f9e7bc23 sd t5,-104(a5) + 8ac: fbd7b023 sd t4,-96(a5) + 8b0: fbc7b423 sd t3,-88(a5) + 8b4: fa67b823 sd t1,-80(a5) + 8b8: fb17bc23 sd a7,-72(a5) + 8bc: 04070713 add a4,a4,64 + 8c0: fb07ece3 bltu a5,a6,878 + 8c4: fbf60613 add a2,a2,-65 + 8c8: fc067793 and a5,a2,-64 + 8cc: 04078793 add a5,a5,64 + 8d0: fc067613 and a2,a2,-64 + 8d4: 00f585b3 add a1,a1,a5 + 8d8: 00c687b3 add a5,a3,a2 + 8dc: f907f4e3 bgeu a5,a6,864 + 8e0: 0005b703 ld a4,0(a1) + 8e4: 00878793 add a5,a5,8 + 8e8: 00858593 add a1,a1,8 + 8ec: fee7bc23 sd a4,-8(a5) + 8f0: ff07e8e3 bltu a5,a6,8e0 + 8f4: 00008067 ret 8f8: 00008067 ret - 8fc: 00008067 ret - 900: 00050793 mv a5,a0 - 904: fddff06f j 8e0 + 8fc: 00050793 mv a5,a0 + 900: fddff06f j 8dc -0000000000000908 : - 908: 00c567b3 or a5,a0,a2 - 90c: 0077f793 and a5,a5,7 - 910: 00c50633 add a2,a0,a2 - 914: 0ff5f713 zext.b a4,a1 - 918: 00078e63 beqz a5,934 - 91c: 00050793 mv a5,a0 - 920: 02c57c63 bgeu a0,a2,958 - 924: 00178793 add a5,a5,1 - 928: fee78fa3 sb a4,-1(a5) - 92c: fef61ce3 bne a2,a5,924 - 930: 00008067 ret - 934: 00004797 auipc a5,0x4 - 938: d247b783 ld a5,-732(a5) # 4658 - 93c: 02f70733 mul a4,a4,a5 - 940: fec578e3 bgeu a0,a2,930 - 944: 00050793 mv a5,a0 - 948: 00878793 add a5,a5,8 - 94c: fee7bc23 sd a4,-8(a5) - 950: fec7ece3 bltu a5,a2,948 +0000000000000904 : + 904: 00c567b3 or a5,a0,a2 + 908: 0077f793 and a5,a5,7 + 90c: 00c50633 add a2,a0,a2 + 910: 0ff5f713 zext.b a4,a1 + 914: 00078e63 beqz a5,930 + 918: 00050793 mv a5,a0 + 91c: 02c57c63 bgeu a0,a2,954 + 920: 00178793 add a5,a5,1 + 924: fee78fa3 sb a4,-1(a5) + 928: fef61ce3 bne a2,a5,920 + 92c: 00008067 ret + 930: 00004797 auipc a5,0x4 + 934: 0a87b783 ld a5,168(a5) # 49d8 + 938: 02f70733 mul a4,a4,a5 + 93c: fec578e3 bgeu a0,a2,92c + 940: 00050793 mv a5,a0 + 944: 00878793 add a5,a5,8 + 948: fee7bc23 sd a4,-8(a5) + 94c: fec7ece3 bltu a5,a2,944 + 950: 00008067 ret 954: 00008067 ret - 958: 00008067 ret -000000000000095c : - 95c: 00054783 lbu a5,0(a0) - 960: 00078e63 beqz a5,97c - 964: 00050793 mv a5,a0 - 968: 0017c703 lbu a4,1(a5) - 96c: 00178793 add a5,a5,1 - 970: fe071ce3 bnez a4,968 - 974: 40a78533 sub a0,a5,a0 - 978: 00008067 ret - 97c: 00000513 li a0,0 - 980: 00008067 ret +0000000000000958 : + 958: 00054783 lbu a5,0(a0) + 95c: 00078e63 beqz a5,978 + 960: 00050793 mv a5,a0 + 964: 0017c703 lbu a4,1(a5) + 968: 00178793 add a5,a5,1 + 96c: fe071ce3 bnez a4,964 + 970: 40a78533 sub a0,a5,a0 + 974: 00008067 ret + 978: 00000513 li a0,0 + 97c: 00008067 ret -0000000000000984 : - 984: 00b506b3 add a3,a0,a1 - 988: 00050793 mv a5,a0 - 98c: 00059863 bnez a1,99c - 990: 0240006f j 9b4 - 994: 00178793 add a5,a5,1 - 998: 00f68a63 beq a3,a5,9ac - 99c: 0007c703 lbu a4,0(a5) - 9a0: fe071ae3 bnez a4,994 - 9a4: 40a78533 sub a0,a5,a0 - 9a8: 00008067 ret - 9ac: 40a68533 sub a0,a3,a0 - 9b0: 00008067 ret - 9b4: 00000513 li a0,0 - 9b8: 00008067 ret +0000000000000980 : + 980: 00b506b3 add a3,a0,a1 + 984: 00050793 mv a5,a0 + 988: 00059863 bnez a1,998 + 98c: 0240006f j 9b0 + 990: 00178793 add a5,a5,1 + 994: 00f68a63 beq a3,a5,9a8 + 998: 0007c703 lbu a4,0(a5) + 99c: fe071ae3 bnez a4,990 + 9a0: 40a78533 sub a0,a5,a0 + 9a4: 00008067 ret + 9a8: 40a68533 sub a0,a3,a0 + 9ac: 00008067 ret + 9b0: 00000513 li a0,0 + 9b4: 00008067 ret -00000000000009bc : - 9bc: 00054783 lbu a5,0(a0) - 9c0: 00158593 add a1,a1,1 - 9c4: 00150513 add a0,a0,1 - 9c8: fff5c703 lbu a4,-1(a1) - 9cc: 00078a63 beqz a5,9e0 - 9d0: fee786e3 beq a5,a4,9bc - 9d4: 0007851b sext.w a0,a5 - 9d8: 40e5053b subw a0,a0,a4 - 9dc: 00008067 ret - 9e0: 00000513 li a0,0 - 9e4: ff5ff06f j 9d8 +00000000000009b8 : + 9b8: 00054783 lbu a5,0(a0) + 9bc: 00158593 add a1,a1,1 + 9c0: 00150513 add a0,a0,1 + 9c4: fff5c703 lbu a4,-1(a1) + 9c8: 00078a63 beqz a5,9dc + 9cc: fee786e3 beq a5,a4,9b8 + 9d0: 0007851b sext.w a0,a5 + 9d4: 40e5053b subw a0,a0,a4 + 9d8: 00008067 ret + 9dc: 00000513 li a0,0 + 9e0: ff5ff06f j 9d4 -00000000000009e8 : - 9e8: 00050793 mv a5,a0 - 9ec: 0005c703 lbu a4,0(a1) - 9f0: 00178793 add a5,a5,1 - 9f4: 00158593 add a1,a1,1 - 9f8: fee78fa3 sb a4,-1(a5) - 9fc: fe0718e3 bnez a4,9ec - a00: 00008067 ret +00000000000009e4 : + 9e4: 00050793 mv a5,a0 + 9e8: 0005c703 lbu a4,0(a1) + 9ec: 00178793 add a5,a5,1 + 9f0: 00158593 add a1,a1,1 + 9f4: fee78fa3 sb a4,-1(a5) + 9f8: fe0718e3 bnez a4,9e8 + 9fc: 00008067 ret Disassembly of section .text.startup: -0000000000000a04
: - a04: fe010113 add sp,sp,-32 - a08: 00113c23 sd ra,24(sp) - a0c: 00813823 sd s0,16(sp) - a10: 00913423 sd s1,8(sp) - a14: 01213023 sd s2,0(sp) - a18: b0201073 csrw minstret,zero - a1c: b0001073 csrw mcycle,zero - a20: b0301073 csrw mhpmcounter3,zero - a24: 00003417 auipc s0,0x3 - a28: 5dc40413 add s0,s0,1500 # 4000 - a2c: 00004497 auipc s1,0x4 - a30: 81448493 add s1,s1,-2028 # 4240 - a34: 00004297 auipc t0,0x4 - a38: c2c28293 add t0,t0,-980 # 4660 - a3c: 00040f13 mv t5,s0 - a40: 00004f97 auipc t6,0x4 - a44: 830f8f93 add t6,t6,-2000 # 4270 - a48: 03000313 li t1,48 - a4c: 00003e17 auipc t3,0x3 - a50: 7f4e0e13 add t3,t3,2036 # 4240 - a54: 00028e93 mv t4,t0 - a58: 000e0513 mv a0,t3 - a5c: 000f0593 mv a1,t5 - a60: 00000893 li a7,0 - a64: 00c00693 li a3,12 - a68: 0d06f757 vsetvli a4,a3,e32,m1,ta,ma - a6c: 0007061b sext.w a2,a4 - a70: 4208e1d7 vmv.s.x v3,a7 - a74: 0205e087 vle32.v v1,(a1) - a78: 0a656107 vlse32.v v2,(a0),t1 - a7c: 961120d7 vmul.vv v1,v1,v2 - a80: 0211a0d7 vredsum.vs v1,v1,v3 - a84: 42102857 vmv.x.s a6,v1 - a88: 0017179b sllw a5,a4,0x1 - a8c: 00e787bb addw a5,a5,a4 - a90: 0027979b sllw a5,a5,0x2 - a94: 00261613 sll a2,a2,0x2 - a98: 00279793 sll a5,a5,0x2 - a9c: 40e686bb subw a3,a3,a4 - aa0: 0008089b sext.w a7,a6 - aa4: 00c585b3 add a1,a1,a2 - aa8: 00f50533 add a0,a0,a5 - aac: fa069ee3 bnez a3,a68 - ab0: 010ea023 sw a6,0(t4) - ab4: 004e0e13 add t3,t3,4 - ab8: 004e8e93 add t4,t4,4 - abc: f9cf9ee3 bne t6,t3,a58 - ac0: 030f0f13 add t5,t5,48 - ac4: 03028293 add t0,t0,48 - ac8: f89f12e3 bne t5,s1,a4c - acc: f1cff0ef jal 1e8 - ad0: b0201073 csrw minstret,zero - ad4: b0001073 csrw mcycle,zero - ad8: b0301073 csrw mhpmcounter3,zero - adc: a4818913 add s2,gp,-1464 # 48a0 - ae0: 00090313 mv t1,s2 - ae4: 00004897 auipc a7,0x4 - ae8: 9cc88893 add a7,a7,-1588 # 44b0 - aec: 00004e17 auipc t3,0x4 - af0: 994e0e13 add t3,t3,-1644 # 4480 - af4: 000e0513 mv a0,t3 - af8: 00030813 mv a6,t1 - afc: dc050713 add a4,a0,-576 - b00: 00040693 mv a3,s0 - b04: 00000613 li a2,0 - b08: 0006a583 lw a1,0(a3) - b0c: 00072783 lw a5,0(a4) - b10: 03070713 add a4,a4,48 - b14: 00468693 add a3,a3,4 - b18: 02b787bb mulw a5,a5,a1 - b1c: 00c7863b addw a2,a5,a2 - b20: fea714e3 bne a4,a0,b08 - b24: 00c82023 sw a2,0(a6) - b28: 00470513 add a0,a4,4 - b2c: 00480813 add a6,a6,4 - b30: fca896e3 bne a7,a0,afc - b34: 03040413 add s0,s0,48 - b38: 03030313 add t1,t1,48 - b3c: fa941ce3 bne s0,s1,af4 - b40: ea8ff0ef jal 1e8 - b44: 00004697 auipc a3,0x4 - b48: b4c68693 add a3,a3,-1204 # 4690 - b4c: a7818593 add a1,gp,-1416 # 48d0 - b50: 00100513 li a0,1 - b54: fd068793 add a5,a3,-48 - b58: 00090713 mv a4,s2 - b5c: 00050a63 beqz a0,b70 - b60: 0007a503 lw a0,0(a5) - b64: 00072603 lw a2,0(a4) - b68: 40c50533 sub a0,a0,a2 - b6c: 00153513 seqz a0,a0 - b70: 00478793 add a5,a5,4 - b74: 00470713 add a4,a4,4 - b78: fed792e3 bne a5,a3,b5c - b7c: 03078693 add a3,a5,48 - b80: 03090913 add s2,s2,48 - b84: fcb698e3 bne a3,a1,b54 - b88: 01813083 ld ra,24(sp) - b8c: 01013403 ld s0,16(sp) - b90: 00813483 ld s1,8(sp) - b94: 00013903 ld s2,0(sp) - b98: 00154513 xor a0,a0,1 - b9c: 02010113 add sp,sp,32 - ba0: 00008067 ret - ba4: fff00513 li a0,-1 - ba8: 00008067 ret +0000000000000a00
: + a00: ff010113 add sp,sp,-16 + a04: 00113423 sd ra,8(sp) + a08: 00813023 sd s0,0(sp) + a0c: b0201073 csrw minstret,zero + a10: b0001073 csrw mcycle,zero + a14: b0301073 csrw mhpmcounter3,zero + a18: 00004617 auipc a2,0x4 + a1c: fc860613 add a2,a2,-56 # 49e0 + a20: 00003597 auipc a1,0x3 + a24: 5e058593 add a1,a1,1504 # 4000 + a28: 00004517 auipc a0,0x4 + a2c: 9d850513 add a0,a0,-1576 # 4400 + a30: 85dff0ef jal 28c <_e8_32x32_matmul> + a34: fb4ff0ef jal 1e8 + a38: b0201073 csrw minstret,zero + a3c: b0001073 csrw mcycle,zero + a40: b0301073 csrw mhpmcounter3,zero + a44: c0818413 add s0,gp,-1016 # 4de0 + a48: 00040e93 mv t4,s0 + a4c: 00000e13 li t3,0 + a50: 00004f17 auipc t5,0x4 + a54: 9b0f0f13 add t5,t5,-1616 # 4400 + a58: 00004317 auipc t1,0x4 + a5c: 9c830313 add t1,t1,-1592 # 4420 + a60: 02000f93 li t6,32 + a64: 005e1893 sll a7,t3,0x5 + a68: 000f0513 mv a0,t5 + a6c: 01e888b3 add a7,a7,t5 + a70: 000e8813 mv a6,t4 + a74: c0050713 add a4,a0,-1024 + a78: 00088613 mv a2,a7 + a7c: 00000793 li a5,0 + a80: 00064683 lbu a3,0(a2) + a84: 00074583 lbu a1,0(a4) + a88: 02070713 add a4,a4,32 + a8c: 00160613 add a2,a2,1 + a90: 02b686bb mulw a3,a3,a1 + a94: 00f687bb addw a5,a3,a5 + a98: 0187979b sllw a5,a5,0x18 + a9c: 4187d79b sraw a5,a5,0x18 + aa0: fea710e3 bne a4,a0,a80 + aa4: 00f80023 sb a5,0(a6) + aa8: 00170513 add a0,a4,1 + aac: 00180813 add a6,a6,1 + ab0: fca312e3 bne t1,a0,a74 + ab4: 001e0e13 add t3,t3,1 + ab8: 020e8e93 add t4,t4,32 + abc: fbfe14e3 bne t3,t6,a64 + ac0: f28ff0ef jal 1e8 + ac4: 00004697 auipc a3,0x4 + ac8: f3c68693 add a3,a3,-196 # 4a00 + acc: c2818593 add a1,gp,-984 # 4e00 + ad0: 00100513 li a0,1 + ad4: fe068793 add a5,a3,-32 + ad8: 00040713 mv a4,s0 + adc: 00050a63 beqz a0,af0 + ae0: 00078503 lb a0,0(a5) + ae4: 00070603 lb a2,0(a4) + ae8: 40c50533 sub a0,a0,a2 + aec: 00153513 seqz a0,a0 + af0: 00178793 add a5,a5,1 + af4: 00170713 add a4,a4,1 + af8: fed792e3 bne a5,a3,adc + afc: 02078693 add a3,a5,32 + b00: 02040413 add s0,s0,32 + b04: fcb698e3 bne a3,a1,ad4 + b08: 00813083 ld ra,8(sp) + b0c: 00013403 ld s0,0(sp) + b10: 00154513 xor a0,a0,1 + b14: 01010113 add sp,sp,16 + b18: 00008067 ret + b1c: fff00513 li a0,-1 + b20: 00008067 ret Disassembly of section .rodata: -0000000000004000 : - 4000: ff9c .2byte 0xff9c - 4002: ffff .2byte 0xffff - 4004: 0000 vmsge.vx v0,v0,zero,v0.t - 4006: 0000 vmsge.vx v0,v0,zero,v0.t - 4008: 0051 .2byte 0x51 - 400a: 0000 vmsge.vx v0,v0,zero,v0.t - 400c: 0054 .2byte 0x54 - 400e: 0000 vmsge.vx v0,v0,zero,v0.t - 4010: 002e .2byte 0x2e - 4012: 0000 vmsge.vx v0,v0,zero,v0.t - 4014: ffa1 vmsge.vx v31,v0,ra,v0.t - 4016: ffff .2byte 0xffff - 4018: ffd9 .2byte 0xffd9 - 401a: ffff .2byte 0xffff - 401c: 000c .2byte 0xc - 401e: 0000 vmsge.vx v0,v0,zero,v0.t - 4020: 0044 .2byte 0x44 - 4022: 0000 vmsge.vx v0,v0,zero,v0.t - 4024: 0059 .2byte 0x59 - 4026: 0000 vmsge.vx v0,v0,zero,v0.t - 4028: ffba .2byte 0xffba - 402a: ffff .2byte 0xffff - 402c: 005e .2byte 0x5e - 402e: 0000 vmsge.vx v0,v0,zero,v0.t - 4030: ffd8 .2byte 0xffd8 - 4032: ffff .2byte 0xffff - 4034: 0032 .2byte 0x32 - 4036: 0000 vmsge.vx v0,v0,zero,v0.t - 4038: 006e .2byte 0x6e - 403a: 0000 vmsge.vx v0,v0,zero,v0.t - 403c: 0000005b .4byte 0x5b - 4040: 0000004b .4byte 0x4b - 4044: 00000033 add zero,zero,zero - 4048: 0055 .2byte 0x55 - 404a: 0000 vmsge.vx v0,v0,zero,v0.t - 404c: 00000017 auipc zero,0x0 - 4050: ff92 .2byte 0xff92 - 4052: ffff .2byte 0xffff - 4054: ff99 .2byte 0xff99 - 4056: ffff .2byte 0xffff - 4058: ff98 .2byte 0xff98 - 405a: ffff .2byte 0xffff - 405c: 002e .2byte 0x2e - 405e: 0000 vmsge.vx v0,v0,zero,v0.t - 4060: ffea .2byte 0xffea - 4062: ffff .2byte 0xffff - 4064: 0068 .2byte 0x68 - 4066: 0000 vmsge.vx v0,v0,zero,v0.t - 4068: 0000002b .4byte 0x2b - 406c: 00000043 vmsge.vx v0,v0,zero,v0.t - 4070: fffc .2byte 0xfffc - 4072: ffff .2byte 0xffff - 4074: 0039 .2byte 0x39 - 4076: 0000 vmsge.vx v0,v0,zero,v0.t - 4078: ffad .2byte 0xffad - 407a: ffff .2byte 0xffff - 407c: ffda .2byte 0xffda - 407e: ffff .2byte 0xffff - 4080: ffffffb3 .4byte 0xffffffb3 - 4084: ffb0 .2byte 0xffb0 - 4086: ffff .2byte 0xffff - 4088: ffffffbf 00000022 .8byte 0x22ffffffbf - 4090: ffd6 .2byte 0xffd6 - 4092: ffff .2byte 0xffff - 4094: ffb9 .2byte 0xffb9 - 4096: ffff .2byte 0xffff - 4098: ff80 vmsge.vx v31,v0,ra,v0.t - 409a: ffff .2byte 0xffff - 409c: 0010 .2byte 0x10 - 409e: 0000 vmsge.vx v0,v0,zero,v0.t - 40a0: 0001 vmsge.vx v0,v0,zero,v0.t - 40a2: 0000 vmsge.vx v0,v0,zero,v0.t - 40a4: 00000017 auipc zero,0x0 - 40a8: fffffff3 csrrc t6,0xfff,31 - 40ac: ffd6 .2byte 0xffd6 - 40ae: ffff .2byte 0xffff - 40b0: ffe1 vmsge.vx v31,v0,ra,v0.t - 40b2: ffff .2byte 0xffff - 40b4: ff98 .2byte 0xff98 - 40b6: ffff .2byte 0xffff - 40b8: ff8c .2byte 0xff8c - 40ba: ffff .2byte 0xffff - 40bc: 0068 .2byte 0x68 - 40be: 0000 vmsge.vx v0,v0,zero,v0.t - 40c0: 007e .2byte 0x7e - 40c2: 0000 vmsge.vx v0,v0,zero,v0.t - 40c4: ffffffd7 vsetivli t6,31,1023 - 40c8: fff0 .2byte 0xfff0 - 40ca: ffff .2byte 0xffff - 40cc: ffc0 vmsge.vx v31,v0,ra,v0.t - 40ce: ffff .2byte 0xffff - 40d0: ffec .2byte 0xffec - 40d2: ffff .2byte 0xffff - 40d4: ffb0 .2byte 0xffb0 - 40d6: ffff .2byte 0xffff - 40d8: fff6 .2byte 0xfff6 - 40da: ffff .2byte 0xffff - 40dc: 0019 .2byte 0x19 - 40de: 0000 vmsge.vx v0,v0,zero,v0.t - 40e0: 00000023 sb zero,0(zero) # 0 <_start> - 40e4: 0006 .2byte 0x6 - 40e6: 0000 vmsge.vx v0,v0,zero,v0.t - 40e8: ffffffa7 .4byte 0xffffffa7 - 40ec: ffda .2byte 0xffda - 40ee: ffff .2byte 0xffff - 40f0: 0050 .2byte 0x50 - 40f2: 0000 vmsge.vx v0,v0,zero,v0.t - 40f4: ffde .2byte 0xffde - 40f6: ffff .2byte 0xffff - 40f8: ffac .2byte 0xffac - 40fa: ffff .2byte 0xffff - 40fc: 006a .2byte 0x6a - 40fe: 0000 vmsge.vx v0,v0,zero,v0.t - 4100: 0072 .2byte 0x72 - 4102: 0000 vmsge.vx v0,v0,zero,v0.t - 4104: 005d .2byte 0x5d - 4106: 0000 vmsge.vx v0,v0,zero,v0.t - 4108: 00000077 .4byte 0x77 - 410c: ff90 .2byte 0xff90 - 410e: ffff .2byte 0xffff - 4110: 0016 .2byte 0x16 - 4112: 0000 vmsge.vx v0,v0,zero,v0.t - 4114: 004c .2byte 0x4c - 4116: 0000 vmsge.vx v0,v0,zero,v0.t - 4118: 006d .2byte 0x6d - 411a: 0000 vmsge.vx v0,v0,zero,v0.t - 411c: ffcd .2byte 0xffcd - 411e: ffff .2byte 0xffff - 4120: 0054 .2byte 0x54 - 4122: 0000 vmsge.vx v0,v0,zero,v0.t - 4124: ffffff9b .4byte 0xffffff9b - 4128: fff6 .2byte 0xfff6 - 412a: ffff .2byte 0xffff - 412c: ffcd .2byte 0xffcd - 412e: ffff .2byte 0xffff - 4130: ffca .2byte 0xffca - 4132: ffff .2byte 0xffff - 4134: 00000057 vadd.vv v0,v0,v0,v0.t - 4138: ffea .2byte 0xffea - 413a: ffff .2byte 0xffff - 413c: ffffff87 .4byte 0xffffff87 - 4140: ff8c .2byte 0xff8c - 4142: ffff .2byte 0xffff - 4144: 005c .2byte 0x5c - 4146: 0000 vmsge.vx v0,v0,zero,v0.t - 4148: ffb6 .2byte 0xffb6 - 414a: ffff .2byte 0xffff - 414c: 0021 vmsge.vx v0,v0,zero,v0.t - 414e: 0000 vmsge.vx v0,v0,zero,v0.t - 4150: 00000017 auipc zero,0x0 - 4154: ffcd .2byte 0xffcd - 4156: ffff .2byte 0xffff - 4158: 0061 vmsge.vx v0,v0,zero,v0.t - 415a: 0000 vmsge.vx v0,v0,zero,v0.t - 415c: ffffff9b .4byte 0xffffff9b - 4160: 00000077 .4byte 0x77 - 4164: ffaa .2byte 0xffaa - 4166: ffff .2byte 0xffff - 4168: ffed .2byte 0xffed - 416a: ffff .2byte 0xffff - 416c: 0070 .2byte 0x70 - 416e: 0000 vmsge.vx v0,v0,zero,v0.t - 4170: 0046 .2byte 0x46 - 4172: 0000 vmsge.vx v0,v0,zero,v0.t - 4174: ffcd .2byte 0xffcd - 4176: ffff .2byte 0xffff - 4178: 0018 .2byte 0x18 - 417a: 0000 vmsge.vx v0,v0,zero,v0.t - 417c: 003d .2byte 0x3d - 417e: 0000 vmsge.vx v0,v0,zero,v0.t - 4180: 001f 0000 0029 .byte 0x1f, 0x00, 0x00, 0x00, 0x29, 0x00 - 4186: 0000 vmsge.vx v0,v0,zero,v0.t - 4188: ffffff83 vmsge.vx v31,v31,t6 - 418c: fffffff7 .4byte 0xfffffff7 - 4190: 0000004f .4byte 0x4f - 4194: ffd6 .2byte 0xffd6 - 4196: ffff .2byte 0xffff - 4198: ff92 .2byte 0xff92 - 419a: ffff .2byte 0xffff - 419c: ffba .2byte 0xffba - 419e: ffff .2byte 0xffff - 41a0: ffdd .2byte 0xffdd +0000000000004000 : + 4000: fdff .2byte 0xfdff + 4002: fd04 .2byte 0xfd04 + 4004: 0501 vmsge.vx v10,v0,zero,v0.t + 4006: fcfe .2byte 0xfcfe + 4008: 06fa .2byte 0x6fa + 400a: fd04 .2byte 0xfd04 + 400c: fffa .2byte 0xfffa + 400e: 0305 .2byte 0x305 + 4010: 0600 vmsge.vx v12,v0,zero,v0.t + 4012: 02f8 .2byte 0x2f8 + 4014: fefc .2byte 0xfefc + 4016: fafd .2byte 0xfafd + 4018: 04f8 .2byte 0x4f8 + 401a: fa02fb03 vmsge.vx v22,v0,t0 + 401e: 0206 .2byte 0x206 + 4020: fdfc .2byte 0xfdfc + 4022: ff02 vmsge.vx v30,v0,ra,v0.t + 4024: 0302 vmsge.vx v6,v0,zero,v0.t + 4026: 00fe .2byte 0xfe + 4028: 01fe .2byte 0x1fe + 402a: fe04 .2byte 0xfe04 + 402c: 05f9fa03 vmsge.vx v20,v31,s3,v0.t + 4030: 06f8 .2byte 0x6f8 + 4032: 0601 vmsge.vx v12,v0,zero,v0.t + 4034: fefc .2byte 0xfefc + 4036: 03fd .2byte 0x3fd + 4038: 0101 vmsge.vx v2,v0,zero,v0.t + 403a: ff05 .2byte 0xff05 + 403c: fc04 .2byte 0xfc04 + 403e: fb01 vmsge.vx v22,v0,ra,v0.t + 4040: fcff .2byte 0xfcff + 4042: 0505 .2byte 0x505 + 4044: 0005 .2byte 0x5 + 4046: 04fe .2byte 0x4fe + 4048: 0406 .2byte 0x406 + 404a: fcfc .2byte 0xfcfc + 404c: f902 vmsge.vx v18,v0,ra,v0.t + 404e: fa06 .2byte 0xfa06 + 4050: fdf8 .2byte 0xfdf8 + 4052: 06fdf9fb .4byte 0x6fdf9fb + 4056: 05fd .2byte 0x5fd + 4058: 0105 .2byte 0x105 + 405a: 05fc0403 lb s0,95(s8) + 405e: fd05 .2byte 0xfd05 + 4060: f905 .2byte 0xf905 + 4062: 0605 .2byte 0x605 + 4064: 0405 .2byte 0x405 + 4066: fb02 vmsge.vx v22,v0,ra,v0.t + 4068: 0000 vmsge.vx v0,v0,zero,v0.t + 406a: fafcf803 vmsge.vx v16,v15,s9 + 406e: fbf9 .2byte 0xfbf9 + 4070: 03fd .2byte 0x3fd + 4072: 0204 .2byte 0x204 + 4074: fef8 .2byte 0xfef8 + 4076: f90205fb .4byte 0xf90205fb + 407a: fff8 .2byte 0xfff8 + 407c: 06fe .2byte 0x6fe + 407e: fbfa .2byte 0xfbfa + 4080: fa06 .2byte 0xfa06 + 4082: fafd .2byte 0xfafd + 4084: 0106 .2byte 0x106 + 4086: 0404 .2byte 0x404 + 4088: 05fc .2byte 0x5fc + 408a: fa00f8fb .4byte 0xfa00f8fb + 408e: 01fc .2byte 0x1fc + 4090: fc00 vmsge.vx v24,v0,ra,v0.t + 4092: 03fa .2byte 0x3fa + 4094: fdfc .2byte 0xfdfc + 4096: 0304 .2byte 0x304 + 4098: f802 vmsge.vx v16,v0,ra,v0.t + 409a: 00fa .2byte 0xfa + 409c: f8f8 .2byte 0xf8f8 + 409e: 0202 vmsge.vx v4,v0,zero,v0.t + 40a0: fb02f803 vmsge.vx v16,v16,t0 + 40a4: fc01 vmsge.vx v24,v0,ra,v0.t + 40a6: fbff .2byte 0xfbff + 40a8: f9fe .2byte 0xf9fe + 40aa: 0506 .2byte 0x506 + 40ac: 0302 vmsge.vx v6,v0,zero,v0.t + 40ae: 0205 .2byte 0x205 + 40b0: ff01 vmsge.vx v30,v0,ra,v0.t + 40b2: 02f9 .2byte 0x2f9 + 40b4: 0304 .2byte 0x304 + 40b6: fefa .2byte 0xfefa + 40b8: fd05 .2byte 0xfd05 + 40ba: 0405 .2byte 0x405 + 40bc: 01fc .2byte 0x1fc + 40be: 030001fb .4byte 0x30001fb + 40c2: fdff .2byte 0xfdff + 40c4: 0200 vmsge.vx v4,v0,zero,v0.t + 40c6: 0602f9fb .4byte 0x602f9fb + 40ca: fbfa .2byte 0xfbfa + 40cc: ff02 vmsge.vx v30,v0,ra,v0.t + 40ce: ff06 .2byte 0xff06 + 40d0: 0405 .2byte 0x405 + 40d2: 0400 vmsge.vx v8,v0,zero,v0.t + 40d4: f8fa .2byte 0xf8fa + 40d6: 01fc03fb .4byte 0x1fc03fb + 40da: 03ff 0302 fbfa fffd .byte 0xff, 0x03, 0x02, 0x03, 0xfa, 0xfb, 0xfd, 0xff, 0xf9, 0xff + 40e2: fff9 + 40e4: 03f8 .2byte 0x3f8 + 40e6: faf8 .2byte 0xfaf8 + 40e8: ffff .2byte 0xffff + 40ea: 0104 .2byte 0x104 + 40ec: fbfcf903 vmsge.vx v18,v31,s9 + 40f0: fffc .2byte 0xfffc + 40f2: 0204f903 vmsge.vx v18,v0,s1 + 40f6: fc00 vmsge.vx v24,v0,ra,v0.t + 40f8: fb01 vmsge.vx v22,v0,ra,v0.t + 40fa: 06ff 04fa fc02 0106 .byte 0xff, 0x06, 0xfa, 0x04, 0x02, 0xfc, 0x06, 0x01, 0x05, 0xf8 + 4102: f805 + 4104: fafe .2byte 0xfafe + 4106: 01fe .2byte 0x1fe + 4108: 0302 vmsge.vx v6,v0,zero,v0.t + 410a: 04fd .2byte 0x4fd + 410c: f8ff .2byte 0xf8ff + 410e: fe05 .2byte 0xfe05 + 4110: fbfcfefb .4byte 0xfbfcfefb + 4114: 03ff fffd 01fd 02fd .byte 0xff, 0x03, 0xfd, 0xff, 0xfd, 0x01, 0xfd, 0x02, 0xfc, 0xfb + 411c: fbfc + 411e: fb01 vmsge.vx v22,v0,ra,v0.t + 4120: 0500 vmsge.vx v10,v0,zero,v0.t + 4122: fcff .2byte 0xfcff + 4124: fbfd .2byte 0xfbfd + 4126: 04fb0203 lb tp,79(s6) + 412a: 05fe .2byte 0x5fe + 412c: 00f9 .2byte 0xf9 + 412e: 04ff fbfc 0203 ff06 .byte 0xff, 0x04, 0xfc, 0xfb, 0x03, 0x02, 0x06, 0xff, 0xfb, 0x06 + 4136: 06fb + 4138: f804 .2byte 0xf804 + 413a: 01f8 .2byte 0x1f8 + 413c: fdfe .2byte 0xfdfe + 413e: f901 vmsge.vx v18,v0,ra,v0.t + 4140: f801 vmsge.vx v16,v0,ra,v0.t + 4142: 0505 .2byte 0x505 + 4144: 0400 vmsge.vx v8,v0,zero,v0.t + 4146: fe04 .2byte 0xfe04 + 4148: fc05 .2byte 0xfc05 + 414a: fcf9fbfb .4byte 0xfcf9fbfb + 414e: fe00 vmsge.vx v28,v0,ra,v0.t + 4150: 0500 vmsge.vx v10,v0,zero,v0.t + 4152: fafc .2byte 0xfafc + 4154: 01fe .2byte 0x1fe + 4156: 0205 .2byte 0x205 + 4158: 0602 vmsge.vx v12,v0,zero,v0.t + 415a: 0305 .2byte 0x305 + 415c: fe05 .2byte 0xfe05 + 415e: 0604 .2byte 0x604 + 4160: 0600 vmsge.vx v12,v0,zero,v0.t + 4162: 0301 vmsge.vx v6,v0,zero,v0.t + 4164: f9fa .2byte 0xf9fa + 4166: 0604 .2byte 0x604 + 4168: faf9 .2byte 0xfaf9 + 416a: 0506 .2byte 0x506 + 416c: 03f8 .2byte 0x3f8 + 416e: fc06 .2byte 0xfc06 + 4170: fb040203 lb tp,-80(s0) + 4174: fcfc .2byte 0xfcfc + 4176: 03f8 .2byte 0x3f8 + 4178: 04fc .2byte 0x4fc + 417a: fcfa .2byte 0xfcfa + 417c: 04fe .2byte 0x4fe + 417e: 06fd .2byte 0x6fd + 4180: f805 .2byte 0xf805 + 4182: fafd .2byte 0xfafd + 4184: 00f8 .2byte 0xf8 + 4186: 00fa .2byte 0xfa + 4188: 03fc .2byte 0x3fc + 418a: fb05 .2byte 0xfb05 + 418c: f804 .2byte 0xf804 + 418e: 06fd .2byte 0x6fd + 4190: fa06 .2byte 0xfa06 + 4192: 0302 vmsge.vx v6,v0,zero,v0.t + 4194: fa00fc03 vmsge.vx v24,v0,ra + 4198: fdfd .2byte 0xfdfd + 419a: 0406 .2byte 0x406 + 419c: 00fc .2byte 0xfc + 419e: 05f801fb .4byte 0x5f801fb 41a2: ffff .2byte 0xffff - 41a4: fff4 .2byte 0xfff4 - 41a6: ffff .2byte 0xffff - 41a8: ffe9 .2byte 0xffe9 - 41aa: ffff .2byte 0xffff - 41ac: ffe0 vmsge.vx v31,v0,ra,v0.t - 41ae: ffff .2byte 0xffff - 41b0: ff96 .2byte 0xff96 - 41b2: ffff .2byte 0xffff - 41b4: ff98 .2byte 0xff98 - 41b6: ffff .2byte 0xffff - 41b8: 0051 .2byte 0x51 - 41ba: 0000 vmsge.vx v0,v0,zero,v0.t - 41bc: 00000033 add zero,zero,zero - 41c0: 0004 .2byte 0x4 - 41c2: 0000 vmsge.vx v0,v0,zero,v0.t - 41c4: 004a .2byte 0x4a - 41c6: 0000 vmsge.vx v0,v0,zero,v0.t - 41c8: 0069 .2byte 0x69 - 41ca: 0000 vmsge.vx v0,v0,zero,v0.t - 41cc: ffb9 .2byte 0xffb9 - 41ce: ffff .2byte 0xffff - 41d0: fff4 .2byte 0xfff4 - 41d2: ffff .2byte 0xffff - 41d4: ff8e .2byte 0xff8e - 41d6: ffff .2byte 0xffff - 41d8: 0068 .2byte 0x68 - 41da: 0000 vmsge.vx v0,v0,zero,v0.t - 41dc: ffd8 .2byte 0xffd8 - 41de: ffff .2byte 0xffff - 41e0: ffb8 .2byte 0xffb8 - 41e2: ffff .2byte 0xffff - 41e4: ffffffd7 vsetivli t6,31,1023 - 41e8: ffa4 .2byte 0xffa4 - 41ea: ffff .2byte 0xffff - 41ec: ffffffd7 vsetivli t6,31,1023 - 41f0: 0054 .2byte 0x54 - 41f2: 0000 vmsge.vx v0,v0,zero,v0.t - 41f4: ffda .2byte 0xffda - 41f6: ffff .2byte 0xffff - 41f8: ffc4 .2byte 0xffc4 - 41fa: ffff .2byte 0xffff - 41fc: 0011 .2byte 0x11 - 41fe: 0000 vmsge.vx v0,v0,zero,v0.t - 4200: 007d .2byte 0x7d - 4202: 0000 vmsge.vx v0,v0,zero,v0.t - 4204: ff95 .2byte 0xff95 - 4206: ffff .2byte 0xffff - 4208: ffb2 .2byte 0xffb2 - 420a: ffff .2byte 0xffff - 420c: ff99 .2byte 0xff99 - 420e: ffff .2byte 0xffff - 4210: ffd2 .2byte 0xffd2 - 4212: ffff .2byte 0xffff - 4214: ffffffcb .4byte 0xffffffcb - 4218: 0000003b addw zero,zero,zero - 421c: ffffffab .4byte 0xffffffab - 4220: 0000000b .4byte 0xb - 4224: ffda .2byte 0xffda - 4226: ffff .2byte 0xffff - 4228: fff2 .2byte 0xfff2 - 422a: ffff .2byte 0xffff - 422c: 005d .2byte 0x5d - 422e: 0000 vmsge.vx v0,v0,zero,v0.t - 4230: 0026 .2byte 0x26 - 4232: 0000 vmsge.vx v0,v0,zero,v0.t - 4234: 0014 .2byte 0x14 - 4236: 0000 vmsge.vx v0,v0,zero,v0.t - 4238: ffd2 .2byte 0xffd2 - 423a: ffff .2byte 0xffff - 423c: 000a .2byte 0xa - ... + 41a4: f801 vmsge.vx v16,v0,ra,v0.t + 41a6: fdfa .2byte 0xfdfa + 41a8: fafd00fb .4byte 0xfafd00fb + 41ac: 02fc .2byte 0x2fc + 41ae: fcf9 .2byte 0xfcf9 + 41b0: 0305 .2byte 0x305 + 41b2: 0602 vmsge.vx v12,v0,zero,v0.t + 41b4: fbfc .2byte 0xfbfc + 41b6: fafd .2byte 0xfafd + 41b8: 020205fb .4byte 0x20205fb + 41bc: fa05 .2byte 0xfa05 + 41be: fa04 .2byte 0xfa04 + 41c0: 03fdfb03 vmsge.vx v22,v31,s11 + 41c4: 0404 .2byte 0x404 + 41c6: 06fe .2byte 0x6fe + 41c8: fc04 .2byte 0xfc04 + 41ca: fa01 vmsge.vx v20,v0,ra,v0.t + 41cc: f8ff .2byte 0xf8ff + 41ce: f9f8 .2byte 0xf9f8 + 41d0: f8fdfdfb .4byte 0xf8fdfdfb + 41d4: fd01 vmsge.vx v26,v0,ra,v0.t + 41d6: fcff .2byte 0xfcff + 41d8: 00fa .2byte 0xfa + 41da: 0606fc03 vmsge.vx v24,v0,a3 + 41de: fc02 vmsge.vx v24,v0,ra,v0.t + 41e0: 00fa .2byte 0xfa + 41e2: fdf8 .2byte 0xfdf8 + 41e4: 0205 .2byte 0x205 + 41e6: fe01 vmsge.vx v28,v0,ra,v0.t + 41e8: 06f8 .2byte 0x6f8 + 41ea: f901 vmsge.vx v18,v0,ra,v0.t + 41ec: 0300 vmsge.vx v6,v0,zero,v0.t + 41ee: 0001 vmsge.vx v0,v0,zero,v0.t + 41f0: f8ff .2byte 0xf8ff + 41f2: fe030503 lb a0,-32(t1) + 41f6: 0101 vmsge.vx v2,v0,zero,v0.t + 41f8: fb00 vmsge.vx v22,v0,ra,v0.t + 41fa: 05fe .2byte 0x5fe + 41fc: fcfa .2byte 0xfcfa + 41fe: 0402 vmsge.vx v8,v0,zero,v0.t + 4200: 04ff fe05 f8f8 fd01 .byte 0xff, 0x04, 0x05, 0xfe, 0xf8, 0xf8, 0x01, 0xfd, 0x01, 0x05 + 4208: 0501 + 420a: 02fa .2byte 0x2fa + 420c: 0601 vmsge.vx v12,v0,zero,v0.t + 420e: fa01 vmsge.vx v20,v0,ra,v0.t + 4210: 05ff 03f8 fe05 f8fd .byte 0xff, 0x05, 0xf8, 0x03, 0x05, 0xfe, 0xfd, 0xf8, 0x00, 0xf8 + 4218: f800 + 421a: fffd .2byte 0xfffd + 421c: fa04 .2byte 0xfa04 + 421e: 0402 vmsge.vx v8,v0,zero,v0.t + 4220: fdfef903 vmsge.vx v18,v31,t4,v0.t + 4224: 0504 .2byte 0x504 + 4226: 0606 .2byte 0x606 + 4228: f9fb0003 lb zero,-97(s6) + 422c: f8fa .2byte 0xf8fa + 422e: 06fc .2byte 0x6fc + 4230: 02fa .2byte 0x2fa + 4232: fa05 .2byte 0xfa05 + 4234: f9fa .2byte 0xf9fa + 4236: 0304 .2byte 0x304 + 4238: fc01 vmsge.vx v24,v0,ra,v0.t + 423a: 0601 vmsge.vx v12,v0,zero,v0.t + 423c: 02fefefb .4byte 0x2fefefb + 4240: 0301 vmsge.vx v6,v0,zero,v0.t + 4242: fcfe .2byte 0xfcfe + 4244: 0602 vmsge.vx v12,v0,zero,v0.t + 4246: 05f9 .2byte 0x5f9 + 4248: fe01 vmsge.vx v28,v0,ra,v0.t + 424a: faf8 .2byte 0xfaf8 + 424c: fbf8 .2byte 0xfbf8 + 424e: 03ff fbf8 fd03 fe02 .byte 0xff, 0x03, 0xf8, 0xfb, 0x03, 0xfd, 0x02, 0xfe, 0xf9, 0x05 + 4256: 05f9 + 4258: 05ff 00fd 02fc 04fb .byte 0xff, 0x05, 0xfd, 0x00, 0xfc, 0x02, 0xfb, 0x04, 0x02, 0x01 + 4260: 0102 + 4262: fa05 .2byte 0xfa05 + 4264: fa05 .2byte 0xfa05 + 4266: 0206 .2byte 0x206 + 4268: f804 .2byte 0xf804 + 426a: fa06 .2byte 0xfa06 + 426c: ff01 vmsge.vx v30,v0,ra,v0.t + 426e: fffb01fb .4byte 0xfffb01fb + 4272: 0206 .2byte 0x206 + 4274: 05fc .2byte 0x5fc + 4276: f902 vmsge.vx v18,v0,ra,v0.t + 4278: 0101 vmsge.vx v2,v0,zero,v0.t + 427a: ff06 .2byte 0xff06 + 427c: fc01 vmsge.vx v24,v0,ra,v0.t + 427e: 0301 vmsge.vx v6,v0,zero,v0.t + 4280: fb01 vmsge.vx v22,v0,ra,v0.t + 4282: fe06 .2byte 0xfe06 + 4284: f9ff .2byte 0xf9ff + 4286: faf8 .2byte 0xfaf8 + 4288: 06f9 .2byte 0x6f9 + 428a: fb00fafb .4byte 0xfb00fafb + 428e: fb05 .2byte 0xfb05 + 4290: fbfa .2byte 0xfbfa + 4292: fe02 vmsge.vx v28,v0,ra,v0.t + 4294: 0202 vmsge.vx v4,v0,zero,v0.t + 4296: f802 vmsge.vx v16,v0,ra,v0.t + 4298: fcfc .2byte 0xfcfc + 429a: 0401 vmsge.vx v8,v0,zero,v0.t + 429c: 05ff 0205 0103 0603 .byte 0xff, 0x05, 0x05, 0x02, 0x03, 0x01, 0x03, 0x06, 0x06, 0xfb + 42a4: fb06 + 42a6: 0401 vmsge.vx v8,v0,zero,v0.t + 42a8: fa06 .2byte 0xfa06 + 42aa: 03f8 .2byte 0x3f8 + 42ac: 04fa .2byte 0x4fa + 42ae: 0201 vmsge.vx v4,v0,zero,v0.t + 42b0: fa05fdfb .4byte 0xfa05fdfb + 42b4: 04fe .2byte 0x4fe + 42b6: 00f8 .2byte 0xf8 + 42b8: 0405 .2byte 0x405 + 42ba: fafc .2byte 0xfafc + 42bc: fc00 vmsge.vx v24,v0,ra,v0.t + 42be: 06fa .2byte 0x6fa + 42c0: 0404 .2byte 0x404 + 42c2: fff8 .2byte 0xfff8 + 42c4: 05fc .2byte 0x5fc + 42c6: 00fa .2byte 0xfa + 42c8: ff01 vmsge.vx v30,v0,ra,v0.t + 42ca: 04fd .2byte 0x4fd + 42cc: f806fdfb .4byte 0xf806fdfb + 42d0: 0004 .2byte 0x4 + 42d2: 05f8 .2byte 0x5f8 + 42d4: 01f9 .2byte 0x1f9 + 42d6: 02f8 .2byte 0x2f8 + 42d8: 04fe .2byte 0x4fe + 42da: fbf8 .2byte 0xfbf8 + 42dc: 03ff 0501 f900 fffc .byte 0xff, 0x03, 0x01, 0x05, 0x00, 0xf9, 0xfc, 0xff, 0x03, 0xf9 + 42e4: f903 + 42e6: fffffc03 vmsge.vx v24,v31,t6 + 42ea: 06f8 .2byte 0x6f8 + 42ec: fc01 vmsge.vx v24,v0,ra,v0.t + 42ee: fcf9 .2byte 0xfcf9 + 42f0: fafd .2byte 0xfafd + 42f2: 03fcff03 vmsge.vx v30,v31,s9 + 42f6: 0206 .2byte 0x206 + 42f8: 0205 .2byte 0x205 + 42fa: 0505 .2byte 0x505 + 42fc: fefc .2byte 0xfefc + 42fe: f9fc .2byte 0xf9fc + 4300: 0506 .2byte 0x506 + 4302: fdfc .2byte 0xfdfc + 4304: 04fc .2byte 0x4fc + 4306: fe01 vmsge.vx v28,v0,ra,v0.t + 4308: 03fa .2byte 0x3fa + 430a: fa02 vmsge.vx v20,v0,ra,v0.t + 430c: 02ff0103 lb sp,47(t5) + 4310: 03f9 .2byte 0x3f9 + 4312: f9f8 .2byte 0xf9f8 + 4314: fafe .2byte 0xfafe + 4316: f800 vmsge.vx v16,v0,ra,v0.t + 4318: 0405 .2byte 0x405 + 431a: fbfa .2byte 0xfbfa + 431c: f906fd03 vmsge.vx v26,v16,a3,v0.t + 4320: 05fc .2byte 0x5fc + 4322: 0102 vmsge.vx v2,v0,zero,v0.t + 4324: fbfe .2byte 0xfbfe + 4326: 0502 vmsge.vx v10,v0,zero,v0.t + 4328: 0604 .2byte 0x604 + 432a: 0305 .2byte 0x305 + 432c: f804 .2byte 0xf804 + 432e: 02050003 lb zero,32(a0) + 4332: 00f9 .2byte 0xf9 + 4334: 06fa .2byte 0x6fa + 4336: 0504 .2byte 0x504 + 4338: fb06 .2byte 0xfb06 + 433a: 0500 vmsge.vx v10,v0,zero,v0.t + 433c: 0101 vmsge.vx v2,v0,zero,v0.t + 433e: 00fc .2byte 0xfc + 4340: fffe .2byte 0xfffe + 4342: fefc0003 lb zero,-17(s8) + 4346: 0402 vmsge.vx v8,v0,zero,v0.t + 4348: f9fc .2byte 0xf9fc + 434a: fc01 vmsge.vx v24,v0,ra,v0.t + 434c: fffd .2byte 0xfffd + 434e: fa05 .2byte 0xfa05 + 4350: fd00 vmsge.vx v26,v0,ra,v0.t + 4352: 01f9 .2byte 0x1f9 + 4354: 0202 vmsge.vx v4,v0,zero,v0.t + 4356: f806 .2byte 0xf806 + 4358: 0400 vmsge.vx v8,v0,zero,v0.t + 435a: fe00 vmsge.vx v28,v0,ra,v0.t + 435c: fffcfafb .4byte 0xfffcfafb + 4360: fb02 vmsge.vx v22,v0,ra,v0.t + 4362: fdfd .2byte 0xfdfd + 4364: fffe .2byte 0xfffe + 4366: 02fbf903 vmsge.vx v18,v15,s7 + 436a: 0501 vmsge.vx v10,v0,zero,v0.t + 436c: 00f8 .2byte 0xf8 + 436e: fd04 .2byte 0xfd04 + 4370: fdfe .2byte 0xfdfe + 4372: fdf8f8fb .4byte 0xfdf8f8fb + 4376: f804 .2byte 0xf804 + 4378: 06ff f802 0303 feff .byte 0xff, 0x06, 0x02, 0xf8, 0x03, 0x03, 0xff, 0xfe, 0xfb, 0x02 + 4380: 02fb + 4382: f9fe .2byte 0xf9fe + 4384: 00ff 00fe 0505 fcfe .byte 0xff, 0x00, 0xfe, 0x00, 0x05, 0x05, 0xfe, 0xfc, 0x06, 0xf8 + 438c: f806 + 438e: 00fdfbfb .4byte 0xfdfbfb + 4392: fd01 vmsge.vx v26,v0,ra,v0.t + 4394: ff06 .2byte 0xff06 + 4396: 06fc .2byte 0x6fc + 4398: 0106 .2byte 0x106 + 439a: f9fa .2byte 0xf9fa + 439c: ff04 .2byte 0xff04 + 439e: feff .2byte 0xfeff + 43a0: 04030103 lb sp,64(t1) + 43a4: 0300 vmsge.vx v6,v0,zero,v0.t + 43a6: 0000 vmsge.vx v0,v0,zero,v0.t + 43a8: f9fa .2byte 0xf9fa + 43aa: ffff .2byte 0xffff + 43ac: ff06 .2byte 0xff06 + 43ae: 01fa .2byte 0x1fa + 43b0: 0201fafb .4byte 0x201fafb + 43b4: f9fa .2byte 0xf9fa + 43b6: 0102 vmsge.vx v2,v0,zero,v0.t + 43b8: f906 .2byte 0xf906 + 43ba: 03fc .2byte 0x3fc + 43bc: fd00 vmsge.vx v26,v0,ra,v0.t + 43be: fffd .2byte 0xfffd + 43c0: fef8 .2byte 0xfef8 + 43c2: fe06 .2byte 0xfe06 + 43c4: fff8 .2byte 0xfff8 + 43c6: 02fd .2byte 0x2fd + 43c8: fffc .2byte 0xfffc + 43ca: f8fa .2byte 0xf8fa + 43cc: f905 .2byte 0xf905 + 43ce: f901 vmsge.vx v18,v0,ra,v0.t + 43d0: f906 .2byte 0xf906 + 43d2: fdf9 .2byte 0xfdf9 + 43d4: 06fa .2byte 0x6fa + 43d6: f8fe .2byte 0xf8fe + 43d8: fafc .2byte 0xfafc + 43da: fdff .2byte 0xfdff + 43dc: fe02 vmsge.vx v28,v0,ra,v0.t + 43de: 05fa .2byte 0x5fa + 43e0: 01fd .2byte 0x1fd + 43e2: 0604 .2byte 0x604 + 43e4: 01fc .2byte 0x1fc + 43e6: ffff .2byte 0xffff + 43e8: 06fa .2byte 0x6fa + 43ea: fcfd .2byte 0xfcfd + 43ec: fdfe0203 lb tp,-33(t3) + 43f0: fefa .2byte 0xfefa + 43f2: fe05 .2byte 0xfe05 + 43f4: fb06 .2byte 0xfb06 + 43f6: f901 vmsge.vx v18,v0,ra,v0.t + 43f8: fefd .2byte 0xfefd + 43fa: 01ff fd03 0605 .byte 0xff, 0x01, 0x03, 0xfd, 0x05, 0x06, 0xfe, 0x00, 0xfe, 0xfe + 4402: -0000000000004240 : - 4240: ffd1 .2byte 0xffd1 - 4242: ffff .2byte 0xffff - 4244: 0052 .2byte 0x52 - 4246: 0000 vmsge.vx v0,v0,zero,v0.t - 4248: ffffffdb .4byte 0xffffffdb - 424c: fff0 .2byte 0xfff0 - 424e: ffff .2byte 0xffff - 4250: ffdd .2byte 0xffdd - 4252: ffff .2byte 0xffff - 4254: 0005 .2byte 0x5 - 4256: 0000 vmsge.vx v0,v0,zero,v0.t - 4258: ff84 .2byte 0xff84 - 425a: ffff .2byte 0xffff - 425c: 005f 0000 ffca .byte 0x5f, 0x00, 0x00, 0x00, 0xca, 0xff - 4262: ffff .2byte 0xffff - 4264: 0059 .2byte 0x59 - 4266: 0000 vmsge.vx v0,v0,zero,v0.t - 4268: ffffffab .4byte 0xffffffab - 426c: 0020 vmsge.vx v0,v0,zero,v0.t - 426e: 0000 vmsge.vx v0,v0,zero,v0.t - 4270: 00000057 vadd.vv v0,v0,v0,v0.t - 4274: ffae .2byte 0xffae - 4276: ffff .2byte 0xffff - 4278: ffa6 .2byte 0xffa6 - 427a: ffff .2byte 0xffff - 427c: fffffffb .4byte 0xfffffffb - 4280: ffe4 .2byte 0xffe4 - 4282: ffff .2byte 0xffff - 4284: ffd8 .2byte 0xffd8 - 4286: ffff .2byte 0xffff - 4288: 0036 .2byte 0x36 - 428a: 0000 vmsge.vx v0,v0,zero,v0.t - 428c: 0004 .2byte 0x4 - 428e: 0000 vmsge.vx v0,v0,zero,v0.t - 4290: fff2 .2byte 0xfff2 - 4292: ffff .2byte 0xffff - 4294: 0044 .2byte 0x44 - 4296: 0000 vmsge.vx v0,v0,zero,v0.t - 4298: 0072 .2byte 0x72 - 429a: 0000 vmsge.vx v0,v0,zero,v0.t - 429c: fffe .2byte 0xfffe - 429e: ffff .2byte 0xffff - 42a0: 00000037 lui zero,0x0 - 42a4: ffffffdb .4byte 0xffffffdb - 42a8: ffffffa3 vmsge.vx v31,v31,t6 - 42ac: ffd5 .2byte 0xffd5 - 42ae: ffff .2byte 0xffff - 42b0: ff98 .2byte 0xff98 - 42b2: ffff .2byte 0xffff - 42b4: 001d .2byte 0x1d - 42b6: 0000 vmsge.vx v0,v0,zero,v0.t - 42b8: 0015 .2byte 0x15 - 42ba: 0000 vmsge.vx v0,v0,zero,v0.t - 42bc: 0016 .2byte 0x16 - 42be: 0000 vmsge.vx v0,v0,zero,v0.t - 42c0: 0000001b sext.w zero,zero - 42c4: 003e .2byte 0x3e - 42c6: 0000 vmsge.vx v0,v0,zero,v0.t - 42c8: 0022 vmsge.vx v0,v0,zero,v0.t - 42ca: 0000 vmsge.vx v0,v0,zero,v0.t - 42cc: 0075 .2byte 0x75 - 42ce: 0000 vmsge.vx v0,v0,zero,v0.t - 42d0: ffc6 .2byte 0xffc6 - 42d2: ffff .2byte 0xffff - 42d4: 0071 .2byte 0x71 - 42d6: 0000 vmsge.vx v0,v0,zero,v0.t - 42d8: 0000002b .4byte 0x2b - 42dc: 0018 .2byte 0x18 - 42de: 0000 vmsge.vx v0,v0,zero,v0.t - 42e0: ffffffdb .4byte 0xffffffdb - 42e4: 0005 .2byte 0x5 - 42e6: 0000 vmsge.vx v0,v0,zero,v0.t - 42e8: 0000002b .4byte 0x2b - 42ec: 006d .2byte 0x6d - 42ee: 0000 vmsge.vx v0,v0,zero,v0.t - 42f0: ff84 .2byte 0xff84 - 42f2: ffff .2byte 0xffff - 42f4: ffffff83 vmsge.vx v31,v31,t6 - 42f8: ffd8 .2byte 0xffd8 - 42fa: ffff .2byte 0xffff - 42fc: 0056 .2byte 0x56 - 42fe: 0000 vmsge.vx v0,v0,zero,v0.t - 4300: 0062 vmsge.vx v0,v0,zero,v0.t - 4302: 0000 vmsge.vx v0,v0,zero,v0.t - 4304: ffc2 vmsge.vx v31,v0,ra,v0.t - 4306: ffff .2byte 0xffff - 4308: 0029 .2byte 0x29 - 430a: 0000 vmsge.vx v0,v0,zero,v0.t - 430c: ffb1 .2byte 0xffb1 - 430e: ffff .2byte 0xffff - 4310: fffffff7 .4byte 0xfffffff7 - 4314: 00000067 jr zero # 0 <_start> - 4318: ffffffd3 .4byte 0xffffffd3 - 431c: 0066 .2byte 0x66 - 431e: 0000 vmsge.vx v0,v0,zero,v0.t - 4320: 0049 .2byte 0x49 - 4322: 0000 vmsge.vx v0,v0,zero,v0.t - 4324: ff96 .2byte 0xff96 - 4326: ffff .2byte 0xffff - 4328: 0064 .2byte 0x64 - 432a: 0000 vmsge.vx v0,v0,zero,v0.t - 432c: 0031 .2byte 0x31 - 432e: 0000 vmsge.vx v0,v0,zero,v0.t - 4330: ffc6 .2byte 0xffc6 - 4332: ffff .2byte 0xffff - 4334: 0019 .2byte 0x19 - 4336: 0000 vmsge.vx v0,v0,zero,v0.t - 4338: ffce .2byte 0xffce - 433a: ffff .2byte 0xffff - 433c: 003e .2byte 0x3e - 433e: 0000 vmsge.vx v0,v0,zero,v0.t - 4340: 007d .2byte 0x7d - 4342: 0000 vmsge.vx v0,v0,zero,v0.t - 4344: 00000073 ecall - 4348: ffb0 .2byte 0xffb0 - 434a: ffff .2byte 0xffff - 434c: 00000043 vmsge.vx v0,v0,zero,v0.t - 4350: ffffffcf .4byte 0xffffffcf - 4354: 0002 vmsge.vx v0,v0,zero,v0.t - 4356: 0000 vmsge.vx v0,v0,zero,v0.t - 4358: ffe2 vmsge.vx v31,v0,ra,v0.t - 435a: ffff .2byte 0xffff - 435c: ffba .2byte 0xffba - 435e: ffff .2byte 0xffff - 4360: 00000027 vse8.v v0,(zero),v0.t - 4364: 0000007b .4byte 0x7b - 4368: ffe2 vmsge.vx v31,v0,ra,v0.t - 436a: ffff .2byte 0xffff - 436c: ff85 .2byte 0xff85 - 436e: ffff .2byte 0xffff - 4370: fff8 .2byte 0xfff8 - 4372: ffff .2byte 0xffff - 4374: 001a .2byte 0x1a - 4376: 0000 vmsge.vx v0,v0,zero,v0.t - 4378: 00000043 vmsge.vx v0,v0,zero,v0.t - 437c: ffe2 vmsge.vx v31,v0,ra,v0.t - 437e: ffff .2byte 0xffff - 4380: ffbc .2byte 0xffbc - 4382: ffff .2byte 0xffff - 4384: 0020 vmsge.vx v0,v0,zero,v0.t - 4386: 0000 vmsge.vx v0,v0,zero,v0.t - 4388: 0000000f fence unknown,unknown - 438c: 0068 .2byte 0x68 - 438e: 0000 vmsge.vx v0,v0,zero,v0.t - 4390: ffa5 .2byte 0xffa5 - 4392: ffff .2byte 0xffff - 4394: 003c .2byte 0x3c - 4396: 0000 vmsge.vx v0,v0,zero,v0.t - 4398: 0015 .2byte 0x15 - 439a: 0000 vmsge.vx v0,v0,zero,v0.t - 439c: ff9e .2byte 0xff9e - 439e: ffff .2byte 0xffff - 43a0: 00000073 ecall - 43a4: ffc4 .2byte 0xffc4 - 43a6: ffff .2byte 0xffff - 43a8: 0028 .2byte 0x28 - 43aa: 0000 vmsge.vx v0,v0,zero,v0.t - 43ac: ffd5 .2byte 0xffd5 - 43ae: ffff .2byte 0xffff - 43b0: 005f 0000 ffcc .byte 0x5f, 0x00, 0x00, 0x00, 0xcc, 0xff - 43b6: ffff .2byte 0xffff - 43b8: 00000043 vmsge.vx v0,v0,zero,v0.t - 43bc: ffc8 .2byte 0xffc8 - 43be: ffff .2byte 0xffff - 43c0: fff8 .2byte 0xfff8 - 43c2: ffff .2byte 0xffff - 43c4: ffae .2byte 0xffae - 43c6: ffff .2byte 0xffff - 43c8: 001c .2byte 0x1c - 43ca: 0000 vmsge.vx v0,v0,zero,v0.t - 43cc: ffffffa3 vmsge.vx v31,v31,t6 - 43d0: ffbc .2byte 0xffbc - 43d2: ffff .2byte 0xffff - 43d4: ffca .2byte 0xffca - 43d6: ffff .2byte 0xffff - 43d8: fffffff7 .4byte 0xfffffff7 - 43dc: ffd0 .2byte 0xffd0 - 43de: ffff .2byte 0xffff - 43e0: fff5 .2byte 0xfff5 - 43e2: ffff .2byte 0xffff - 43e4: 005d .2byte 0x5d - 43e6: 0000 vmsge.vx v0,v0,zero,v0.t - 43e8: 0010 .2byte 0x10 - 43ea: 0000 vmsge.vx v0,v0,zero,v0.t - 43ec: 0040 vmsge.vx v0,v0,zero,v0.t - 43ee: 0000 vmsge.vx v0,v0,zero,v0.t - 43f0: 0011 .2byte 0x11 - 43f2: 0000 vmsge.vx v0,v0,zero,v0.t - 43f4: ff96 .2byte 0xff96 - 43f6: ffff .2byte 0xffff - 43f8: ffba .2byte 0xffba - 43fa: ffff .2byte 0xffff - 43fc: ffa6 .2byte 0xffa6 - 43fe: ffff .2byte 0xffff - 4400: 00000023 sb zero,0(zero) # 0 <_start> - 4404: 004e .2byte 0x4e - 4406: 0000 vmsge.vx v0,v0,zero,v0.t - 4408: 0061 vmsge.vx v0,v0,zero,v0.t - 440a: 0000 vmsge.vx v0,v0,zero,v0.t - 440c: ff81 vmsge.vx v31,v0,ra,v0.t - 440e: ffff .2byte 0xffff - 4410: ffb2 .2byte 0xffb2 - 4412: ffff .2byte 0xffff - 4414: ffe4 .2byte 0xffe4 - 4416: ffff .2byte 0xffff - 4418: 007d .2byte 0x7d - 441a: 0000 vmsge.vx v0,v0,zero,v0.t - 441c: 0045 .2byte 0x45 - 441e: 0000 vmsge.vx v0,v0,zero,v0.t - 4420: 002c .2byte 0x2c - 4422: 0000 vmsge.vx v0,v0,zero,v0.t - 4424: ffb2 .2byte 0xffb2 - 4426: ffff .2byte 0xffff - 4428: 001a .2byte 0x1a - 442a: 0000 vmsge.vx v0,v0,zero,v0.t - 442c: 0034 .2byte 0x34 - 442e: 0000 vmsge.vx v0,v0,zero,v0.t - 4430: 0061 vmsge.vx v0,v0,zero,v0.t - 4432: 0000 vmsge.vx v0,v0,zero,v0.t - 4434: fff6 .2byte 0xfff6 - 4436: ffff .2byte 0xffff - 4438: 003e .2byte 0x3e - 443a: 0000 vmsge.vx v0,v0,zero,v0.t - 443c: ffb2 .2byte 0xffb2 - 443e: ffff .2byte 0xffff - 4440: ff92 .2byte 0xff92 - 4442: ffff .2byte 0xffff - 4444: fff8 .2byte 0xfff8 - 4446: ffff .2byte 0xffff - 4448: ff82 vmsge.vx v31,v0,ra,v0.t - 444a: ffff .2byte 0xffff - 444c: 00000073 ecall - 4450: ff84 .2byte 0xff84 - 4452: ffff .2byte 0xffff - 4454: 0012 .2byte 0x12 - 4456: 0000 vmsge.vx v0,v0,zero,v0.t - 4458: 0036 .2byte 0x36 - 445a: 0000 vmsge.vx v0,v0,zero,v0.t - 445c: 0029 .2byte 0x29 - 445e: 0000 vmsge.vx v0,v0,zero,v0.t - 4460: fff8 .2byte 0xfff8 - 4462: ffff .2byte 0xffff - 4464: 001a .2byte 0x1a - 4466: 0000 vmsge.vx v0,v0,zero,v0.t - 4468: fff5 .2byte 0xfff5 - 446a: ffff .2byte 0xffff - 446c: ff80 vmsge.vx v31,v0,ra,v0.t - 446e: ffff .2byte 0xffff - 4470: 0014 .2byte 0x14 - 4472: 0000 vmsge.vx v0,v0,zero,v0.t - 4474: ff9c .2byte 0xff9c - 4476: ffff .2byte 0xffff - 4478: ffdf ffff 0001 .byte 0xdf, 0xff, 0xff, 0xff, 0x01, 0x00 - 447e: 0000 vmsge.vx v0,v0,zero,v0.t - 4480: c174 .2byte 0xc174 - 4482: ffff .2byte 0xffff - 4484: c1b8 .2byte 0xc1b8 - 4486: ffff .2byte 0xffff - 4488: c1fc .2byte 0xc1fc - 448a: ffff .2byte 0xffff - 448c: c10c .2byte 0xc10c - 448e: ffff .2byte 0xffff - 4490: c240 vmsge.vx v4,v0,ra,v0.t - 4492: ffff .2byte 0xffff - 4494: c284 .2byte 0xc284 +0000000000004400 : + 4400: 00fe .2byte 0xfe + 4402: fefe .2byte 0xfefe + 4404: fffa .2byte 0xfffa + 4406: 04f8 .2byte 0x4f8 + 4408: 02f806fb .4byte 0x2f806fb + 440c: fe00 vmsge.vx v28,v0,ra,v0.t + 440e: 0000 vmsge.vx v0,v0,zero,v0.t + 4410: fbf8 .2byte 0xfbf8 + 4412: 0505 .2byte 0x505 + 4414: 0002 vmsge.vx v0,v0,zero,v0.t + 4416: fbfc .2byte 0xfbfc + 4418: f904 .2byte 0xf904 + 441a: 00f9 .2byte 0xf9 + 441c: 0101 vmsge.vx v2,v0,zero,v0.t + 441e: fefa .2byte 0xfefa + 4420: f9f9 .2byte 0xf9f9 + 4422: fd02 vmsge.vx v26,v0,ra,v0.t + 4424: fafbfc03 vmsge.vx v24,v15,s7 + 4428: f9fe .2byte 0xf9fe + 442a: fc00 vmsge.vx v24,v0,ra,v0.t + 442c: fdfe .2byte 0xfdfe + 442e: 05fe .2byte 0x5fe + 4430: 00fe .2byte 0xfe + 4432: 0404 .2byte 0x404 + 4434: f9f9 .2byte 0xf9f9 + 4436: fcff .2byte 0xfcff + 4438: fef8fbfb .4byte 0xfef8fbfb + 443c: f9ff .2byte 0xf9ff + 443e: ff01 vmsge.vx v30,v0,ra,v0.t + 4440: 0204 .2byte 0x204 + 4442: f906 .2byte 0xf906 + 4444: fbfc .2byte 0xfbfc + 4446: 0200 vmsge.vx v4,v0,zero,v0.t + 4448: 0300 vmsge.vx v6,v0,zero,v0.t + 444a: 01fb0103 lb sp,31(s6) + 444e: fef9 .2byte 0xfef9 + 4450: faf9 .2byte 0xfaf9 + 4452: fef9 .2byte 0xfef9 + 4454: 06ff fbf8 0106 0004 .byte 0xff, 0x06, 0xf8, 0xfb, 0x06, 0x01, 0x04, 0x00, 0x01, 0x00 + 445c: 0001 + 445e: 0505 .2byte 0x505 + 4460: f806 .2byte 0xf806 + 4462: fa01 vmsge.vx v20,v0,ra,v0.t + 4464: 0404 .2byte 0x404 + 4466: 03fa .2byte 0x3fa + 4468: fbfa .2byte 0xfbfa + 446a: f9ff .2byte 0xf9ff + 446c: f9ff .2byte 0xf9ff + 446e: f900 vmsge.vx v18,v0,ra,v0.t + 4470: 0005 .2byte 0x5 + 4472: fafc .2byte 0xfafc + 4474: fffa .2byte 0xfffa + 4476: fbfe .2byte 0xfbfe + 4478: 0405 .2byte 0x405 + 447a: 04f9 .2byte 0x4f9 + 447c: 0600 vmsge.vx v12,v0,zero,v0.t + 447e: f8030403 lb s0,-128(t1) + 4482: 05f9 .2byte 0x5f9 + 4484: f802 vmsge.vx v16,v0,ra,v0.t + 4486: 0302 vmsge.vx v6,v0,zero,v0.t + 4488: 0606fe03 vmsge.vx v28,v0,a3 + 448c: 06f9 .2byte 0x6f9 + 448e: 0106 .2byte 0x106 + 4490: 02fdf903 vmsge.vx v18,v15,s11 + 4494: f901 vmsge.vx v18,v0,ra,v0.t 4496: ffff .2byte 0xffff - 4498: c2c8 .2byte 0xc2c8 - 449a: ffff .2byte 0xffff - 449c: c30c .2byte 0xc30c - 449e: ffff .2byte 0xffff - 44a0: c10c .2byte 0xc10c - 44a2: ffff .2byte 0xffff - 44a4: c10c .2byte 0xc10c - 44a6: ffff .2byte 0xffff - 44a8: c10c .2byte 0xc10c - 44aa: ffff .2byte 0xffff - 44ac: c350 .2byte 0xc350 - 44ae: ffff .2byte 0xffff + 4498: f8fe .2byte 0xf8fe + 449a: fd02 vmsge.vx v26,v0,ra,v0.t + 449c: fbff .2byte 0xfbff + 449e: fc04 .2byte 0xfc04 + 44a0: 02ff 06fa 01fc fe03 .byte 0xff, 0x02, 0xfa, 0x06, 0xfc, 0x01, 0x03, 0xfe, 0x05, 0x05 + 44a8: 0505 + 44aa: 03fc .2byte 0x3fc + 44ac: faff .2byte 0xfaff + 44ae: f8fa .2byte 0xf8fa + 44b0: 0201 vmsge.vx v4,v0,zero,v0.t + 44b2: ff01 vmsge.vx v30,v0,ra,v0.t + 44b4: 01ff 0301 0306 fb00 .byte 0xff, 0x01, 0x01, 0x03, 0x06, 0x03, 0x00, 0xfb, 0xf9, 0xfe + 44bc: fef9 + 44be: fe01 vmsge.vx v28,v0,ra,v0.t + 44c0: fdfc .2byte 0xfdfc + 44c2: f8f8 .2byte 0xf8f8 + 44c4: 04f8 .2byte 0x4f8 + 44c6: f805 .2byte 0xf805 + 44c8: f9fc .2byte 0xf9fc + 44ca: 05fdfc03 vmsge.vx v24,v31,s11,v0.t + 44ce: 06fc .2byte 0x6fc + 44d0: 0302 vmsge.vx v6,v0,zero,v0.t + 44d2: fdfd .2byte 0xfdfd + 44d4: f9f8 .2byte 0xf9f8 + 44d6: 060400fb .4byte 0x60400fb + 44da: 0305 .2byte 0x305 + 44dc: fdf9 .2byte 0xfdf9 + 44de: f804 .2byte 0xf804 + 44e0: 03fb0403 lb s0,63(s6) + 44e4: fc00 vmsge.vx v24,v0,ra,v0.t + 44e6: fdf9 .2byte 0xfdf9 + 44e8: 00ff 01fd 02fd 0204 .byte 0xff, 0x00, 0xfd, 0x01, 0xfd, 0x02, 0x04, 0x02, 0xfc, 0xf9 + 44f0: f9fc + 44f2: 04f9 .2byte 0x4f9 + 44f4: fb01 vmsge.vx v22,v0,ra,v0.t + 44f6: fa04 .2byte 0xfa04 + 44f8: 00060303 lb t1,0(a2) + 44fc: fcff .2byte 0xfcff + 44fe: f9f9 .2byte 0xf9f9 + 4500: 0506fc03 vmsge.vx v24,v16,a3,v0.t + 4504: f8f8 .2byte 0xf8f8 + 4506: fd05 .2byte 0xfd05 + 4508: 04fd .2byte 0x4fd + 450a: 03fd .2byte 0x3fd + 450c: fe02 vmsge.vx v28,v0,ra,v0.t + 450e: fdfbfafb .4byte 0xfdfbfafb + 4512: 03fe .2byte 0x3fe + 4514: fa00 vmsge.vx v20,v0,ra,v0.t + 4516: f8f8 .2byte 0xf8f8 + 4518: fdfc .2byte 0xfdfc + 451a: fd02 vmsge.vx v26,v0,ra,v0.t + 451c: f906 .2byte 0xf906 + 451e: fdfd .2byte 0xfdfd + 4520: 0502 vmsge.vx v10,v0,zero,v0.t + 4522: fb01 vmsge.vx v22,v0,ra,v0.t + 4524: 05f8 .2byte 0x5f8 + 4526: fe020003 lb zero,-32(tp) # ffffffffffffffe0 <_end+0xffffffffefffff98> + 452a: fffe00fb .4byte 0xfffe00fb + 452e: fd03f9fb .4byte 0xfd03f9fb + 4532: ffff .2byte 0xffff + 4534: 0205 .2byte 0x205 + 4536: 03fe .2byte 0x3fe + 4538: 0305 .2byte 0x305 + 453a: fbff0103 lb sp,-65(t5) + 453e: f906 .2byte 0xf906 + 4540: 0204 .2byte 0x204 + 4542: 0306 .2byte 0x306 + 4544: fb00 vmsge.vx v22,v0,ra,v0.t + 4546: faff .2byte 0xfaff + 4548: fdff .2byte 0xfdff + 454a: f8ff .2byte 0xf8ff + 454c: f8fc .2byte 0xf8fc + 454e: fff9 .2byte 0xfff9 + 4550: 06fa .2byte 0x6fa + 4552: fc04 .2byte 0xfc04 + 4554: 04f9 .2byte 0x4f9 + 4556: 0206 .2byte 0x206 + 4558: fbfa .2byte 0xfbfa + 455a: f902 vmsge.vx v18,v0,ra,v0.t + 455c: fcfc .2byte 0xfcfc + 455e: 0500 vmsge.vx v10,v0,zero,v0.t + 4560: 04fc .2byte 0x4fc + 4562: 0000 vmsge.vx v0,v0,zero,v0.t + 4564: fd05 .2byte 0xfd05 + 4566: 0004 .2byte 0x4 + 4568: 06fe .2byte 0x6fe + 456a: fcfa .2byte 0xfcfa + 456c: fb00 vmsge.vx v22,v0,ra,v0.t + 456e: f9fa .2byte 0xf9fa + 4570: faff .2byte 0xfaff + 4572: fdfd .2byte 0xfdfd + 4574: 0101 vmsge.vx v2,v0,zero,v0.t + 4576: fbfc0403 lb s0,-65(s8) + 457a: fb06 .2byte 0xfb06 + 457c: 05fe .2byte 0x5fe + 457e: 0005 .2byte 0x5 + 4580: fdf8 .2byte 0xfdf8 + 4582: 06f8 .2byte 0x6f8 + 4584: 03ff 05fb fcfb f8fa .byte 0xff, 0x03, 0xfb, 0x05, 0xfb, 0xfc, 0xfa, 0xf8, 0xf9, 0xf9 + 458c: f9f9 + 458e: f9fcfa03 vmsge.vx v20,v31,s9,v0.t + 4592: 0201 vmsge.vx v4,v0,zero,v0.t + 4594: fbf8 .2byte 0xfbf8 + 4596: ff02 vmsge.vx v30,v0,ra,v0.t + 4598: ff01 vmsge.vx v30,v0,ra,v0.t + 459a: 05fa .2byte 0x5fa + 459c: 05fa .2byte 0x5fa + 459e: fa05 .2byte 0xfa05 + 45a0: fd05 .2byte 0xfd05 + 45a2: fafa .2byte 0xfafa + 45a4: fffd .2byte 0xfffd + 45a6: fcf8 .2byte 0xfcf8 + 45a8: fd02 vmsge.vx v26,v0,ra,v0.t + 45aa: 05fb05fb .4byte 0x5fb05fb + 45ae: f8fc .2byte 0xf8fc + 45b0: 01f9 .2byte 0x1f9 + 45b2: fd00 vmsge.vx v26,v0,ra,v0.t + 45b4: 0601 vmsge.vx v12,v0,zero,v0.t + 45b6: ff02 vmsge.vx v30,v0,ra,v0.t + 45b8: 0501 vmsge.vx v10,v0,zero,v0.t + 45ba: 0402 vmsge.vx v8,v0,zero,v0.t + 45bc: fe04 .2byte 0xfe04 + 45be: 0301 vmsge.vx v6,v0,zero,v0.t + 45c0: 02fe .2byte 0x2fe + 45c2: fbff .2byte 0xfbff + 45c4: 06f904fb .4byte 0x6f904fb + 45c8: 01fc .2byte 0x1fc + 45ca: f801 vmsge.vx v16,v0,ra,v0.t + 45cc: 0602 vmsge.vx v12,v0,zero,v0.t + 45ce: fff9 .2byte 0xfff9 + 45d0: 05fcfb03 vmsge.vx v22,v31,s9,v0.t + 45d4: 01f9 .2byte 0x1f9 + 45d6: 01fc .2byte 0x1fc + 45d8: 03fd .2byte 0x3fd + 45da: 01fc .2byte 0x1fc + 45dc: 0605 .2byte 0x605 + 45de: 04fd .2byte 0x4fd + 45e0: 00fa .2byte 0xfa + 45e2: 06040203 lb tp,96(s0) + 45e6: 04f8 .2byte 0x4f8 + 45e8: f9ff .2byte 0xf9ff + 45ea: fdfc .2byte 0xfdfc + 45ec: fefc .2byte 0xfefc + 45ee: ff000103 lb sp,-16(zero) # fffffffffffffff0 <_end+0xffffffffefffffa8> + 45f2: f802 vmsge.vx v16,v0,ra,v0.t + 45f4: 06f903fb .4byte 0x6f903fb + 45f8: f905 .2byte 0xf905 + 45fa: ff02 vmsge.vx v30,v0,ra,v0.t + 45fc: fff8 .2byte 0xfff8 + 45fe: fbfc .2byte 0xfbfc + 4600: fb06 .2byte 0xfb06 + 4602: fd00 vmsge.vx v26,v0,ra,v0.t + 4604: 0302 vmsge.vx v6,v0,zero,v0.t + 4606: fbff .2byte 0xfbff + 4608: 00ff 03fd f9f9 fbf9 .byte 0xff, 0x00, 0xfd, 0x03, 0xf9, 0xf9, 0xf9, 0xfb, 0x00, 0xf8 + 4610: f800 + 4612: 01fe .2byte 0x1fe + 4614: 06fd .2byte 0x6fd + 4616: fefe .2byte 0xfefe + 4618: f8ff .2byte 0xf8ff + 461a: 01fa .2byte 0x1fa + 461c: 0501 vmsge.vx v10,v0,zero,v0.t + 461e: 0205 .2byte 0x205 + 4620: fd00 vmsge.vx v26,v0,ra,v0.t + 4622: fafc .2byte 0xfafc + 4624: 06ff 01f8 f803 f9f9 .byte 0xff, 0x06, 0xf8, 0x01, 0x03, 0xf8, 0xf9, 0xf9, 0xff, 0xfb + 462c: fbff + 462e: fc02fcfb .4byte 0xfc02fcfb + 4632: 01fbfc03 vmsge.vx v24,v31,s7,v0.t + 4636: 05ff 00fe 03f8 f8fe .byte 0xff, 0x05, 0xfe, 0x00, 0xf8, 0x03, 0xfe, 0xf8, 0xfb, 0x01 + 463e: 01fb + 4640: fffa .2byte 0xfffa + 4642: 0501 vmsge.vx v10,v0,zero,v0.t + 4644: ff06 .2byte 0xff06 + 4646: f9fd .2byte 0xf9fd + 4648: 0106 .2byte 0x106 + 464a: 0606 .2byte 0x606 + 464c: f8f8 .2byte 0xf8f8 + 464e: fefa .2byte 0xfefa + 4650: fe01 vmsge.vx v28,v0,ra,v0.t + 4652: 06ff0103 lb sp,111(t5) + 4656: fe02f803 vmsge.vx v16,v0,t0 + 465a: 0601 vmsge.vx v12,v0,zero,v0.t + 465c: 00ff fcf8 05fb 04ff .byte 0xff, 0x00, 0xf8, 0xfc, 0xfb, 0x05, 0xff, 0x04, 0x04, 0x02 + 4664: 0204 + 4666: 06f8 .2byte 0x6f8 + 4668: f800 vmsge.vx v16,v0,ra,v0.t + 466a: fbfd .2byte 0xfbfd + 466c: fbff .2byte 0xfbff + 466e: 05f9 .2byte 0x5f9 + 4670: fc04 .2byte 0xfc04 + 4672: 0505 .2byte 0x505 + 4674: fafd .2byte 0xfafd + 4676: 0301 vmsge.vx v6,v0,zero,v0.t + 4678: fbfc .2byte 0xfbfc + 467a: 06f8 .2byte 0x6f8 + 467c: fafc0203 lb tp,-81(s8) + 4680: f8000203 lb tp,-128(zero) # ffffffffffffff80 <_end+0xffffffffefffff38> + 4684: 0102 vmsge.vx v2,v0,zero,v0.t + 4686: 06fc .2byte 0x6fc + 4688: 0306 .2byte 0x306 + 468a: ff01 vmsge.vx v30,v0,ra,v0.t + 468c: fd06 .2byte 0xfd06 + 468e: 04fe .2byte 0x4fe + 4690: f9fa .2byte 0xf9fa + 4692: f8f8 .2byte 0xf8f8 + 4694: fcfa .2byte 0xfcfa + 4696: 04f8 .2byte 0x4f8 + 4698: 0100 vmsge.vx v2,v0,zero,v0.t + 469a: fa00 vmsge.vx v20,v0,ra,v0.t + 469c: fd02 vmsge.vx v26,v0,ra,v0.t + 469e: f900 vmsge.vx v18,v0,ra,v0.t + 46a0: 03fa .2byte 0x3fa + 46a2: 01fc .2byte 0x1fc + 46a4: 0001 vmsge.vx v0,v0,zero,v0.t + 46a6: 04fc .2byte 0x4fc + 46a8: f806 .2byte 0xf806 + 46aa: f804 .2byte 0xf804 + 46ac: f8fe .2byte 0xf8fe + 46ae: 00fa .2byte 0xfa + 46b0: 03fa .2byte 0x3fa + 46b2: 06f8 .2byte 0x6f8 + 46b4: 0301 vmsge.vx v6,v0,zero,v0.t + 46b6: fc00 vmsge.vx v24,v0,ra,v0.t + 46b8: fafc .2byte 0xfafc + 46ba: 0002 vmsge.vx v0,v0,zero,v0.t + 46bc: f904 .2byte 0xf904 + 46be: ff06 .2byte 0xff06 + 46c0: 01f9 .2byte 0x1f9 + 46c2: f8fc .2byte 0xf8fc + 46c4: 05f9 .2byte 0x5f9 + 46c6: 03f9fdfb .4byte 0x3f9fdfb + 46ca: 00f9 .2byte 0xf9 + 46cc: 0602 vmsge.vx v12,v0,zero,v0.t + 46ce: fbfa .2byte 0xfbfa + 46d0: fafc .2byte 0xfafc + 46d2: 0300 vmsge.vx v6,v0,zero,v0.t + 46d4: fb02 vmsge.vx v22,v0,ra,v0.t + 46d6: 010504fb .4byte 0x10504fb + 46da: 06fe .2byte 0x6fe + 46dc: f901 vmsge.vx v18,v0,ra,v0.t + 46de: fe02 vmsge.vx v28,v0,ra,v0.t + 46e0: fb04 .2byte 0xfb04 + 46e2: fc03fffb .4byte 0xfc03fffb + 46e6: fa06 .2byte 0xfa06 + 46e8: fc06 .2byte 0xfc06 + 46ea: fdff .2byte 0xfdff + 46ec: 05fd .2byte 0x5fd + 46ee: 06f8 .2byte 0x6f8 + 46f0: 03fc .2byte 0x3fc + 46f2: 03fd .2byte 0x3fd + 46f4: 04f8 .2byte 0x4f8 + 46f6: 0404 .2byte 0x404 + 46f8: fc00 vmsge.vx v24,v0,ra,v0.t + 46fa: fffa0203 lb tp,-1(s4) + 46fe: 0405 .2byte 0x405 + 4700: fd04 .2byte 0xfd04 + 4702: 05f9 .2byte 0x5f9 + 4704: 05040203 lb tp,80(s0) + 4708: 0300 vmsge.vx v6,v0,zero,v0.t + 470a: 0105fefb .4byte 0x105fefb + 470e: fcfa .2byte 0xfcfa + 4710: 01fe0603 lb a2,31(t3) + 4714: 0406 .2byte 0x406 + 4716: faf9 .2byte 0xfaf9 + 4718: f9fe .2byte 0xf9fe + 471a: f900 vmsge.vx v18,v0,ra,v0.t + 471c: fcfd .2byte 0xfcfd + 471e: fcfc .2byte 0xfcfc + 4720: f801 vmsge.vx v16,v0,ra,v0.t + 4722: 01fe .2byte 0x1fe + 4724: fef9 .2byte 0xfef9 + 4726: 01fa .2byte 0x1fa + 4728: 0104 .2byte 0x104 + 472a: 00f90203 lb tp,15(s2) + 472e: ff02 vmsge.vx v30,v0,ra,v0.t + 4730: 0501f803 vmsge.vx v16,v16,gp,v0.t + 4734: 0001 vmsge.vx v0,v0,zero,v0.t + 4736: 06fa .2byte 0x6fa + 4738: fef9 .2byte 0xfef9 + 473a: fdf8 .2byte 0xfdf8 + 473c: 0200fc03 vmsge.vx v24,v0,ra + 4740: fd01 vmsge.vx v26,v0,ra,v0.t + 4742: 02fd .2byte 0x2fd + 4744: fa04 .2byte 0xfa04 + 4746: fc01 vmsge.vx v24,v0,ra,v0.t + 4748: f9f9 .2byte 0xf9f9 + 474a: ff00 vmsge.vx v30,v0,ra,v0.t + 474c: f904 .2byte 0xf904 + 474e: fd00 vmsge.vx v26,v0,ra,v0.t + 4750: f8fbfe03 vmsge.vx v28,v15,s7,v0.t + 4754: 0305 .2byte 0x305 + 4756: 05fc .2byte 0x5fc + 4758: 0004fb03 vmsge.vx v22,v0,s1,v0.t + 475c: fbfd .2byte 0xfbfd + 475e: fd01 vmsge.vx v26,v0,ra,v0.t + 4760: 0406 .2byte 0x406 + 4762: fbf8 .2byte 0xfbf8 + 4764: fb01 vmsge.vx v22,v0,ra,v0.t + 4766: 03fa .2byte 0x3fa + 4768: fef9 .2byte 0xfef9 + 476a: 0100 vmsge.vx v2,v0,zero,v0.t + 476c: 03fc .2byte 0x3fc + 476e: 05f8 .2byte 0x5f8 + 4770: fe02 vmsge.vx v28,v0,ra,v0.t + 4772: 0100 vmsge.vx v2,v0,zero,v0.t + 4774: fbfe .2byte 0xfbfe + 4776: fe06 .2byte 0xfe06 + 4778: fffc01fb .4byte 0xfffc01fb + 477c: 0104 .2byte 0x104 + 477e: f9fc .2byte 0xf9fc + 4780: f804 .2byte 0xf804 + 4782: 00fe .2byte 0xfe + 4784: fe06f9fb .4byte 0xfe06f9fb + 4788: fa00 vmsge.vx v20,v0,ra,v0.t + 478a: 0402 vmsge.vx v8,v0,zero,v0.t + 478c: fef9 .2byte 0xfef9 + 478e: 0400 vmsge.vx v8,v0,zero,v0.t + 4790: ff01 vmsge.vx v30,v0,ra,v0.t + 4792: 0005 .2byte 0x5 + 4794: 0400f903 vmsge.vx v18,v0,ra,v0.t + 4798: 04f9 .2byte 0x4f9 + 479a: f900 vmsge.vx v18,v0,ra,v0.t + 479c: 0300 vmsge.vx v6,v0,zero,v0.t + 479e: fdf9 .2byte 0xfdf9 + 47a0: 03030103 lb sp,48(t1) + 47a4: f9fb0603 lb a2,-97(s6) + 47a8: faf9 .2byte 0xfaf9 + 47aa: 05f8 .2byte 0x5f8 + 47ac: 01ff 0503 0201 fe03 .byte 0xff, 0x01, 0x03, 0x05, 0x01, 0x02, 0x03, 0xfe, 0xfb, 0x01 + 47b4: 01fb + 47b6: ffff .2byte 0xffff + 47b8: fc04 .2byte 0xfc04 + 47ba: fc06 .2byte 0xfc06 + 47bc: fd05 .2byte 0xfd05 + 47be: 05fe .2byte 0x5fe + 47c0: fbfe .2byte 0xfbfe + 47c2: 0000 vmsge.vx v0,v0,zero,v0.t + 47c4: fff9 .2byte 0xfff9 + 47c6: ffff .2byte 0xffff + 47c8: fc01 vmsge.vx v24,v0,ra,v0.t + 47ca: fb00 vmsge.vx v22,v0,ra,v0.t + 47cc: fd05 .2byte 0xfd05 + 47ce: fefa .2byte 0xfefa + 47d0: 05ff f800 f801 fbfe .byte 0xff, 0x05, 0x00, 0xf8, 0x01, 0xf8, 0xfe, 0xfb, 0xf9, 0xfa + 47d8: faf9 + 47da: f802 vmsge.vx v16,v0,ra,v0.t + 47dc: 04fe .2byte 0x4fe + 47de: 01ff 00f8 fb03 fbff .byte 0xff, 0x01, 0xf8, 0x00, 0x03, 0xfb, 0xff, 0xfb, 0x01, 0xfc + 47e6: fc01 + 47e8: fe06 .2byte 0xfe06 + 47ea: 03fd .2byte 0x3fd + 47ec: fdf9 .2byte 0xfdf9 + 47ee: fa00 vmsge.vx v20,v0,ra,v0.t + 47f0: fd02fb03 vmsge.vx v22,v16,t0,v0.t + 47f4: fef9 .2byte 0xfef9 + 47f6: 06fe .2byte 0x6fe + 47f8: 01f8 .2byte 0x1f8 + 47fa: fcf8 .2byte 0xfcf8 + 47fc: 0205 .2byte 0x205 + 47fe: bdf00403 lb s0,-1057(zero) # fffffffffffffbdf <_end+0xffffffffeffffb97> + 4802: ffff .2byte 0xffff + 4804: be34 .2byte 0xbe34 + 4806: ffff .2byte 0xffff + 4808: be78 .2byte 0xbe78 + 480a: ffff .2byte 0xffff + 480c: bd88 .2byte 0xbd88 + 480e: ffff .2byte 0xffff + 4810: bebc .2byte 0xbebc + 4812: ffff .2byte 0xffff + 4814: bf00 vmsge.vx v30,v0,ra,v0.t + 4816: ffff .2byte 0xffff + 4818: bf44 .2byte 0xbf44 + 481a: ffff .2byte 0xffff + 481c: bf88 .2byte 0xbf88 + 481e: ffff .2byte 0xffff + 4820: bd88 .2byte 0xbd88 + 4822: ffff .2byte 0xffff + 4824: bd88 .2byte 0xbd88 + 4826: ffff .2byte 0xffff + 4828: bd88 .2byte 0xbd88 + 482a: ffff .2byte 0xffff + 482c: bfcc .2byte 0xbfcc + 482e: ffff .2byte 0xffff Disassembly of section .rodata.str1.8: -00000000000044b0 <.rodata.str1.8>: - 44b0: 4c435943 vmsge.vx v18,v4,t1,v0.t - 44b4: 3a45 .2byte 0x3a45 - 44b6: 0020 vmsge.vx v0,v0,zero,v0.t - 44b8: 490a .2byte 0x490a - 44ba: 534e .2byte 0x534e - 44bc: 5254 .2byte 0x5254 - 44be: 5445 .2byte 0x5445 - 44c0: 203a .2byte 0x203a - 44c2: 0000 vmsge.vx v0,v0,zero,v0.t - 44c4: 0000 vmsge.vx v0,v0,zero,v0.t - 44c6: 0000 vmsge.vx v0,v0,zero,v0.t - 44c8: 4d0a .2byte 0x4d0a - 44ca: 5048 .2byte 0x5048 - 44cc: 434d .2byte 0x434d - 44ce: 544e554f .4byte 0x544e554f - 44d2: 5245 .2byte 0x5245 - 44d4: 00203a33 snez s4,sp - 44d8: 000a .2byte 0xa - 44da: 0000 vmsge.vx v0,v0,zero,v0.t - 44dc: 0000 vmsge.vx v0,v0,zero,v0.t - 44de: 0000 vmsge.vx v0,v0,zero,v0.t - 44e0: 6c637963 bgeu t1,t1,4bb2 <_tbss_end+0xd2> - 44e4: 3a65 .2byte 0x3a65 - 44e6: 0020 vmsge.vx v0,v0,zero,v0.t - 44e8: 690a .2byte 0x690a - 44ea: 736e .2byte 0x736e - 44ec: 7274 .2byte 0x7274 - 44ee: 7465 .2byte 0x7465 - 44f0: 203a .2byte 0x203a - 44f2: 0000 vmsge.vx v0,v0,zero,v0.t - 44f4: 0000 vmsge.vx v0,v0,zero,v0.t - 44f6: 0000 vmsge.vx v0,v0,zero,v0.t - 44f8: 7845 .2byte 0x7845 - 44fa: 7469 .2byte 0x7469 - 44fc: 6320 vmsge.vx v6,v0,zero,v0.t - 44fe: 3a65646f jal s0,5a8a4 <__global_pointer$+0x55a4c> - 4502: 0020 vmsge.vx v0,v0,zero,v0.t - 4504: 0000 vmsge.vx v0,v0,zero,v0.t - 4506: 0000 vmsge.vx v0,v0,zero,v0.t - 4508: 4e49 .2byte 0x4e49 - 450a: 55525453 .4byte 0x55525453 - 450e: 4f495443 vmsge.vx v8,v20,s2 - 4512: 204e .2byte 0x204e - 4514: 4441 vmsge.vx v8,v0,zero,v0.t - 4516: 5244 .2byte 0x5244 - 4518: 5345 .2byte 0x5345 - 451a: 494d2053 .4byte 0x494d2053 - 451e: 494c4153 .4byte 0x494c4153 - 4522: 44454e47 .4byte 0x44454e47 - 4526: 6120 vmsge.vx v2,v0,zero,v0.t - 4528: 2074 .2byte 0x2074 - 452a: 4350 .2byte 0x4350 - 452c: 203a .2byte 0x203a - 452e: 0000 vmsge.vx v0,v0,zero,v0.t - 4530: 4e49 .2byte 0x4e49 - 4532: 55525453 .4byte 0x55525453 - 4536: 4f495443 vmsge.vx v8,v20,s2 - 453a: 204e .2byte 0x204e - 453c: 4341 vmsge.vx v6,v0,zero,v0.t - 453e: 53534543 vmsge.vx v10,v21,t1 - 4542: 4620 vmsge.vx v12,v0,zero,v0.t - 4544: 5541 vmsge.vx v10,v0,zero,v0.t - 4546: 544c .2byte 0x544c - 4548: 6120 vmsge.vx v2,v0,zero,v0.t - 454a: 2074 .2byte 0x2074 - 454c: 4350 .2byte 0x4350 - 454e: 203a .2byte 0x203a +0000000000004830 <.rodata.str1.8>: + 4830: 4c435943 vmsge.vx v18,v4,t1,v0.t + 4834: 3a45 .2byte 0x3a45 + 4836: 0020 vmsge.vx v0,v0,zero,v0.t + 4838: 490a .2byte 0x490a + 483a: 534e .2byte 0x534e + 483c: 5254 .2byte 0x5254 + 483e: 5445 .2byte 0x5445 + 4840: 203a .2byte 0x203a + 4842: 0000 vmsge.vx v0,v0,zero,v0.t + 4844: 0000 vmsge.vx v0,v0,zero,v0.t + 4846: 0000 vmsge.vx v0,v0,zero,v0.t + 4848: 4d0a .2byte 0x4d0a + 484a: 5048 .2byte 0x5048 + 484c: 434d .2byte 0x434d + 484e: 544e554f .4byte 0x544e554f + 4852: 5245 .2byte 0x5245 + 4854: 00203a33 snez s4,sp + 4858: 000a .2byte 0xa + 485a: 0000 vmsge.vx v0,v0,zero,v0.t + 485c: 0000 vmsge.vx v0,v0,zero,v0.t + 485e: 0000 vmsge.vx v0,v0,zero,v0.t + 4860: 6c637963 bgeu t1,t1,4f32 + 4864: 3a65 .2byte 0x3a65 + 4866: 0020 vmsge.vx v0,v0,zero,v0.t + 4868: 690a .2byte 0x690a + 486a: 736e .2byte 0x736e + 486c: 7274 .2byte 0x7274 + 486e: 7465 .2byte 0x7465 + 4870: 203a .2byte 0x203a + 4872: 0000 vmsge.vx v0,v0,zero,v0.t + 4874: 0000 vmsge.vx v0,v0,zero,v0.t + 4876: 0000 vmsge.vx v0,v0,zero,v0.t + 4878: 7845 .2byte 0x7845 + 487a: 7469 .2byte 0x7469 + 487c: 6320 vmsge.vx v6,v0,zero,v0.t + 487e: 3a65646f jal s0,5ac24 <_tbss_end+0x55a44> + 4882: 0020 vmsge.vx v0,v0,zero,v0.t + 4884: 0000 vmsge.vx v0,v0,zero,v0.t + 4886: 0000 vmsge.vx v0,v0,zero,v0.t + 4888: 4e49 .2byte 0x4e49 + 488a: 55525453 .4byte 0x55525453 + 488e: 4f495443 vmsge.vx v8,v20,s2 + 4892: 204e .2byte 0x204e + 4894: 4441 vmsge.vx v8,v0,zero,v0.t + 4896: 5244 .2byte 0x5244 + 4898: 5345 .2byte 0x5345 + 489a: 494d2053 .4byte 0x494d2053 + 489e: 494c4153 .4byte 0x494c4153 + 48a2: 44454e47 .4byte 0x44454e47 + 48a6: 6120 vmsge.vx v2,v0,zero,v0.t + 48a8: 2074 .2byte 0x2074 + 48aa: 4350 .2byte 0x4350 + 48ac: 203a .2byte 0x203a + 48ae: 0000 vmsge.vx v0,v0,zero,v0.t + 48b0: 4e49 .2byte 0x4e49 + 48b2: 55525453 .4byte 0x55525453 + 48b6: 4f495443 vmsge.vx v8,v20,s2 + 48ba: 204e .2byte 0x204e + 48bc: 4341 vmsge.vx v6,v0,zero,v0.t + 48be: 53534543 vmsge.vx v10,v21,t1 + 48c2: 4620 vmsge.vx v12,v0,zero,v0.t + 48c4: 5541 vmsge.vx v10,v0,zero,v0.t + 48c6: 544c .2byte 0x544c + 48c8: 6120 vmsge.vx v2,v0,zero,v0.t + 48ca: 2074 .2byte 0x2074 + 48cc: 4350 .2byte 0x4350 + 48ce: 203a .2byte 0x203a ... - 4558: 4c49 .2byte 0x4c49 - 455a: 454c .2byte 0x454c - 455c: 204c4147 .4byte 0x204c4147 - 4560: 4e49 .2byte 0x4e49 - 4562: 55525453 .4byte 0x55525453 - 4566: 4f495443 vmsge.vx v8,v20,s2 - 456a: 204e .2byte 0x204e - 456c: 7461 vmsge.vx v8,v0,zero,v0.t - 456e: 5020 vmsge.vx v0,v0,zero,v0.t - 4570: 00203a43 vmsge.vx v20,v2,zero,v0.t - 4574: 0000 vmsge.vx v0,v0,zero,v0.t - 4576: 0000 vmsge.vx v0,v0,zero,v0.t - 4578: 4f4c .2byte 0x4f4c - 457a: 4441 vmsge.vx v8,v0,zero,v0.t - 457c: 4120 vmsge.vx v2,v0,zero,v0.t - 457e: 4444 .2byte 0x4444 - 4580: 4552 .2byte 0x4552 - 4582: 4d205353 .4byte 0x4d205353 - 4586: 5349 .2byte 0x5349 - 4588: 4c41 vmsge.vx v24,v0,zero,v0.t - 458a: 4749 .2byte 0x4749 - 458c: 454e .2byte 0x454e - 458e: 2044 .2byte 0x2044 - 4590: 7461 vmsge.vx v8,v0,zero,v0.t - 4592: 5020 vmsge.vx v0,v0,zero,v0.t - 4594: 00203a43 vmsge.vx v20,v2,zero,v0.t - 4598: 4f4c .2byte 0x4f4c - 459a: 4441 vmsge.vx v8,v0,zero,v0.t - 459c: 4120 vmsge.vx v2,v0,zero,v0.t - 459e: 53454343 vmsge.vx v6,v20,a0 - 45a2: 41462053 .4byte 0x41462053 - 45a6: 4c55 .2byte 0x4c55 - 45a8: 2054 .2byte 0x2054 - 45aa: 7461 vmsge.vx v8,v0,zero,v0.t - 45ac: 5020 vmsge.vx v0,v0,zero,v0.t - 45ae: 00203a43 vmsge.vx v20,v2,zero,v0.t - 45b2: 0000 vmsge.vx v0,v0,zero,v0.t - 45b4: 0000 vmsge.vx v0,v0,zero,v0.t - 45b6: 0000 vmsge.vx v0,v0,zero,v0.t - 45b8: 524f5453 .4byte 0x524f5453 - 45bc: 2045 .2byte 0x2045 - 45be: 4441 vmsge.vx v8,v0,zero,v0.t - 45c0: 5244 .2byte 0x5244 - 45c2: 5345 .2byte 0x5345 - 45c4: 494d2053 .4byte 0x494d2053 - 45c8: 494c4153 .4byte 0x494c4153 - 45cc: 44454e47 .4byte 0x44454e47 - 45d0: 6120 vmsge.vx v2,v0,zero,v0.t - 45d2: 2074 .2byte 0x2074 - 45d4: 4350 .2byte 0x4350 - 45d6: 203a .2byte 0x203a + 48d8: 4c49 .2byte 0x4c49 + 48da: 454c .2byte 0x454c + 48dc: 204c4147 .4byte 0x204c4147 + 48e0: 4e49 .2byte 0x4e49 + 48e2: 55525453 .4byte 0x55525453 + 48e6: 4f495443 vmsge.vx v8,v20,s2 + 48ea: 204e .2byte 0x204e + 48ec: 7461 vmsge.vx v8,v0,zero,v0.t + 48ee: 5020 vmsge.vx v0,v0,zero,v0.t + 48f0: 00203a43 vmsge.vx v20,v2,zero,v0.t + 48f4: 0000 vmsge.vx v0,v0,zero,v0.t + 48f6: 0000 vmsge.vx v0,v0,zero,v0.t + 48f8: 4f4c .2byte 0x4f4c + 48fa: 4441 vmsge.vx v8,v0,zero,v0.t + 48fc: 4120 vmsge.vx v2,v0,zero,v0.t + 48fe: 4444 .2byte 0x4444 + 4900: 4552 .2byte 0x4552 + 4902: 4d205353 .4byte 0x4d205353 + 4906: 5349 .2byte 0x5349 + 4908: 4c41 vmsge.vx v24,v0,zero,v0.t + 490a: 4749 .2byte 0x4749 + 490c: 454e .2byte 0x454e + 490e: 2044 .2byte 0x2044 + 4910: 7461 vmsge.vx v8,v0,zero,v0.t + 4912: 5020 vmsge.vx v0,v0,zero,v0.t + 4914: 00203a43 vmsge.vx v20,v2,zero,v0.t + 4918: 4f4c .2byte 0x4f4c + 491a: 4441 vmsge.vx v8,v0,zero,v0.t + 491c: 4120 vmsge.vx v2,v0,zero,v0.t + 491e: 53454343 vmsge.vx v6,v20,a0 + 4922: 41462053 .4byte 0x41462053 + 4926: 4c55 .2byte 0x4c55 + 4928: 2054 .2byte 0x2054 + 492a: 7461 vmsge.vx v8,v0,zero,v0.t + 492c: 5020 vmsge.vx v0,v0,zero,v0.t + 492e: 00203a43 vmsge.vx v20,v2,zero,v0.t + 4932: 0000 vmsge.vx v0,v0,zero,v0.t + 4934: 0000 vmsge.vx v0,v0,zero,v0.t + 4936: 0000 vmsge.vx v0,v0,zero,v0.t + 4938: 524f5453 .4byte 0x524f5453 + 493c: 2045 .2byte 0x2045 + 493e: 4441 vmsge.vx v8,v0,zero,v0.t + 4940: 5244 .2byte 0x5244 + 4942: 5345 .2byte 0x5345 + 4944: 494d2053 .4byte 0x494d2053 + 4948: 494c4153 .4byte 0x494c4153 + 494c: 44454e47 .4byte 0x44454e47 + 4950: 6120 vmsge.vx v2,v0,zero,v0.t + 4952: 2074 .2byte 0x2074 + 4954: 4350 .2byte 0x4350 + 4956: 203a .2byte 0x203a ... - 45e0: 524f5453 .4byte 0x524f5453 - 45e4: 2045 .2byte 0x2045 - 45e6: 4341 vmsge.vx v6,v0,zero,v0.t - 45e8: 53534543 vmsge.vx v10,v21,t1 - 45ec: 4620 vmsge.vx v12,v0,zero,v0.t - 45ee: 5541 vmsge.vx v10,v0,zero,v0.t - 45f0: 544c .2byte 0x544c - 45f2: 6120 vmsge.vx v2,v0,zero,v0.t - 45f4: 2074 .2byte 0x2074 - 45f6: 4350 .2byte 0x4350 - 45f8: 203a .2byte 0x203a - 45fa: 0000 vmsge.vx v0,v0,zero,v0.t - 45fc: 0000 vmsge.vx v0,v0,zero,v0.t - 45fe: 0000 vmsge.vx v0,v0,zero,v0.t - 4600: 4345 .2byte 0x4345 - 4602: 4c41 vmsge.vx v24,v0,zero,v0.t - 4604: 204c .2byte 0x204c - 4606: 5246 .2byte 0x5246 - 4608: 4d204d4f .4byte 0x4d204d4f - 460c: 4d2d .2byte 0x4d2d - 460e: 2045444f .4byte 0x2045444f - 4612: 7461 vmsge.vx v8,v0,zero,v0.t - 4614: 5020 vmsge.vx v0,v0,zero,v0.t - 4616: 00203a43 vmsge.vx v20,v2,zero,v0.t - 461a: 0000 vmsge.vx v0,v0,zero,v0.t - 461c: 0000 vmsge.vx v0,v0,zero,v0.t - 461e: 0000 vmsge.vx v0,v0,zero,v0.t - 4620: 4e55 .2byte 0x4e55 - 4622: 574f4e4b .4byte 0x574f4e4b - 4626: 204e .2byte 0x204e - 4628: 5845 .2byte 0x5845 - 462a: 54504543 vmsge.vx v10,v5,zero,v0.t - 462e: 4f49 .2byte 0x4f49 - 4630: 204e .2byte 0x204e - 4632: 7461 vmsge.vx v8,v0,zero,v0.t - 4634: 5020 vmsge.vx v0,v0,zero,v0.t - 4636: 00203a43 vmsge.vx v20,v2,zero,v0.t - 463a: 0000 vmsge.vx v0,v0,zero,v0.t - 463c: 0000 vmsge.vx v0,v0,zero,v0.t - 463e: 0000 vmsge.vx v0,v0,zero,v0.t - 4640: 430a .2byte 0x430a - 4642: 4548 .2byte 0x4548 - 4644: 4d204b43 vmsge.vx v22,v18,zero,v0.t - 4648: 53554143 vmsge.vx v2,v21,a0 - 464c: 2045 .2byte 0x2045 - 464e: 6e69 .2byte 0x6e69 - 4650: 5220 vmsge.vx v4,v0,zero,v0.t - 4652: 4c54 .2byte 0x4c54 + 4960: 524f5453 .4byte 0x524f5453 + 4964: 2045 .2byte 0x2045 + 4966: 4341 vmsge.vx v6,v0,zero,v0.t + 4968: 53534543 vmsge.vx v10,v21,t1 + 496c: 4620 vmsge.vx v12,v0,zero,v0.t + 496e: 5541 vmsge.vx v10,v0,zero,v0.t + 4970: 544c .2byte 0x544c + 4972: 6120 vmsge.vx v2,v0,zero,v0.t + 4974: 2074 .2byte 0x2074 + 4976: 4350 .2byte 0x4350 + 4978: 203a .2byte 0x203a + 497a: 0000 vmsge.vx v0,v0,zero,v0.t + 497c: 0000 vmsge.vx v0,v0,zero,v0.t + 497e: 0000 vmsge.vx v0,v0,zero,v0.t + 4980: 4345 .2byte 0x4345 + 4982: 4c41 vmsge.vx v24,v0,zero,v0.t + 4984: 204c .2byte 0x204c + 4986: 5246 .2byte 0x5246 + 4988: 4d204d4f .4byte 0x4d204d4f + 498c: 4d2d .2byte 0x4d2d + 498e: 2045444f .4byte 0x2045444f + 4992: 7461 vmsge.vx v8,v0,zero,v0.t + 4994: 5020 vmsge.vx v0,v0,zero,v0.t + 4996: 00203a43 vmsge.vx v20,v2,zero,v0.t + 499a: 0000 vmsge.vx v0,v0,zero,v0.t + 499c: 0000 vmsge.vx v0,v0,zero,v0.t + 499e: 0000 vmsge.vx v0,v0,zero,v0.t + 49a0: 4e55 .2byte 0x4e55 + 49a2: 574f4e4b .4byte 0x574f4e4b + 49a6: 204e .2byte 0x204e + 49a8: 5845 .2byte 0x5845 + 49aa: 54504543 vmsge.vx v10,v5,zero,v0.t + 49ae: 4f49 .2byte 0x4f49 + 49b0: 204e .2byte 0x204e + 49b2: 7461 vmsge.vx v8,v0,zero,v0.t + 49b4: 5020 vmsge.vx v0,v0,zero,v0.t + 49b6: 00203a43 vmsge.vx v20,v2,zero,v0.t + 49ba: 0000 vmsge.vx v0,v0,zero,v0.t + 49bc: 0000 vmsge.vx v0,v0,zero,v0.t + 49be: 0000 vmsge.vx v0,v0,zero,v0.t + 49c0: 430a .2byte 0x430a + 49c2: 4548 .2byte 0x4548 + 49c4: 4d204b43 vmsge.vx v22,v18,zero,v0.t + 49c8: 53554143 vmsge.vx v2,v21,a0 + 49cc: 2045 .2byte 0x2045 + 49ce: 6e69 .2byte 0x6e69 + 49d0: 5220 vmsge.vx v4,v0,zero,v0.t + 49d2: 4c54 .2byte 0x4c54 ... Disassembly of section .sdata: -0000000000004658 <__global_pointer$-0x800>: - 4658: 0101 vmsge.vx v2,v0,zero,v0.t - 465a: 0101 vmsge.vx v2,v0,zero,v0.t - 465c: 0101 vmsge.vx v2,v0,zero,v0.t - 465e: 0101 vmsge.vx v2,v0,zero,v0.t +00000000000049d8 <__global_pointer$-0x800>: + 49d8: 0101 vmsge.vx v2,v0,zero,v0.t + 49da: 0101 vmsge.vx v2,v0,zero,v0.t + 49dc: 0101 vmsge.vx v2,v0,zero,v0.t + 49de: 0101 vmsge.vx v2,v0,zero,v0.t Disassembly of section .bss: -0000000000004660 : +00000000000049e0 : ... -00000000000048a0 : +0000000000004de0 : ... Disassembly of section .tohost: diff --git a/src/main/resources/applications_vector/vector_matmul/vector_matmul.c b/src/main/resources/applications_vector/vector_matmul/vector_matmul.c index 77b58d0b..65a8ae77 100644 --- a/src/main/resources/applications_vector/vector_matmul/vector_matmul.c +++ b/src/main/resources/applications_vector/vector_matmul/vector_matmul.c @@ -1,34 +1,105 @@ #include "util.h" #define size_t long -#define N 12 +#define N 32 -const int array1[12][12] = {{-100, 0, 81, 84, 46, -95, -39, 12, 68, 89, -70, 94}, - {-40, 50, 110, 91, 75, 51, 85, 23, -110, -103, -104, 46}, - {-22, 104, 43, 67, -4, 57, -83, -38, -77, -80, -65, 34}, - {-42, -71, -128, 16, 1, 23, -13, -42, -31, -104, -116, 104}, - {126, -41, -16, -64, -20, -80, -10, 25, 35, 6, -89, -38}, - {80, -34, -84, 106, 114, 93, 119, -112, 22, 76, 109, -51}, - {84, -101, -10, -51, -54, 87, -22, -121, -116, 92, -74, 33}, - {23, -51, 97, -101, 119, -86, -19, 112, 70, -51, 24, 61}, - {31, 41, -125, -9, 79, -42, -110, -70, -35, -12, -23, -32}, - {-106, -104, 81, 51, 4, 74, 105, -71, -12, -114, 104, -40}, - {-72, -41, -92, -41, 84, -38, -60, 17, 125, -107, -78, -103}, - {-46, -53, 59, -85, 11, -38, -14, 93, 38, 20, -46, 10}}; -const int array2[12][12] = {{-47, 82, -37, -16, -35, 5, -124, 95, -54, 89, -85, 32}, - {87, -82, -90, -5, -28, -40, 54, 4, -14, 68, 114, -2}, - {55, -37, -93, -43, -104, 29, 21, 22, 27, 62, 34, 117}, - {-58, 113, 43, 24, -37, 5, 43, 109, -124, -125, -40, 86}, - {98, -62, 41, -79, -9, 103, -45, 102, 73, -106, 100, 49}, - {-58, 25, -50, 62, 125, 115, -80, 67, -49, 2, -30, -70}, - {39, 123, -30, -123, -8, 26, 67, -30, -68, 32, 15, 104}, - {-91, 60, 21, -98, 115, -60, 40, -43, 95, -52, 67, -56}, - {-8, -82, 28, -93, -68, -54, -9, -48, -11, 93, 16, 64}, - {17, -106, -70, -90, 35, 78, 97, -127, -78, -28, 125, 69}, - {44, -78, 26, 52, 97, -10, 62, -78, -110, -8, -126, 115}, - {-124, 18, 54, 41, -8, 26, -11, -128, 20, -100, -33, 1}}; -int resultArray[12][12] = {0}; -int answerArray[12][12] = {0}; +const signed char array1[32][32] = {{-2, 0, -2, -2, -6, -1, -8, 4, -5, 6, -8, 2, 0, -2, 0, 0, -8, -5, 5, 5, 2, 0, -4, -5, 4, -7, -7, 0, 1, 1, -6, -2}, + {-7, -7, 2, -3, 3, -4, -5, -6, -2, -7, 0, -4, -2, -3, -2, 5, -2, 0, 4, 4, -7, -7, -1, -4, -5, -5, -8, -2, -1, -7, 1, -1}, + {4, 2, 6, -7, -4, -5, 0, 2, 0, 3, 3, 1, -5, 1, -7, -2, -7, -6, -7, -2, -1, 6, -8, -5, 6, 1, 4, 0, 1, 0, 5, 5}, + {6, -8, 1, -6, 4, 4, -6, 3, -6, -5, -1, -7, -1, -7, 0, -7, 5, 0, -4, -6, -6, -1, -2, -5, 5, 4, -7, 4, 0, 6, 3, 4}, + {3, -8, -7, 5, 2, -8, 2, 3, 3, -2, 6, 6, -7, 6, 6, 1, 3, -7, -3, 2, 1, -7, -1, -1, -2, -8, 2, -3, -1, -5, 4, -4}, + {-1, 2, -6, 6, -4, 1, 3, -2, 5, 5, -4, 3, -1, -6, -6, -8, 1, 2, 1, -1, -1, 1, 1, 3, 6, 3, 0, -5, -7, -2, 1, -2}, + {-4, -3, -8, -8, -8, 4, 5, -8, -4, -7, 3, -4, -3, 5, -4, 6, 2, 3, -3, -3, -8, -7, -5, 0, 4, 6, 5, 3, -7, -3, 4, -8}, + {3, 4, -5, 3, 0, -4, -7, -3, -1, 0, -3, 1, -3, 2, 4, 2, -4, -7, -7, 4, 1, -5, 4, -6, 3, 3, 6, 0, -1, -4, -7, -7}, + {3, -4, 6, 5, -8, -8, 5, -3, -3, 4, -3, 3, 2, -2, -5, -6, -5, -3, -2, 3, 0, -6, -8, -8, -4, -3, 2, -3, 6, -7, -3, -3}, + {2, 5, 1, -5, -8, 5, 3, 0, 2, -2, -5, 0, -2, -1, -5, -7, 3, -3, -1, -1, 5, 2, -2, 3, 5, 3, 3, 1, -1, -5, 6, -7}, + {4, 2, 6, 3, 0, -5, -1, -6, -1, -3, -1, -8, -4, -8, -7, -1, -6, 6, 4, -4, -7, 4, 6, 2, -6, -5, 2, -7, -4, -4, 0, 5}, + {-4, 4, 0, 0, 5, -3, 4, 0, -2, 6, -6, -4, 0, -5, -6, -7, -1, -6, -3, -3, 1, 1, 3, 4, -4, -5, 6, -5, -2, 5, 5, 0}, + {-8, -3, -8, 6, -1, 3, -5, 5, -5, -4, -6, -8, -7, -7, 3, -6, -4, -7, 1, 2, -8, -5, 2, -1, 1, -1, -6, 5, -6, 5, 5, -6}, + {5, -3, -6, -6, -3, -1, -8, -4, 2, -3, -5, 5, -5, 5, -4, -8, -7, 1, 0, -3, 1, 6, 2, -1, 1, 5, 2, 4, 4, -2, 1, 3}, + {-2, 2, -1, -5, -5, 4, -7, 6, -4, 1, 1, -8, 2, 6, -7, -1, 3, -5, -4, 5, -7, 1, -4, 1, -3, 3, -4, 1, 5, 6, -3, 4}, + {-6, 0, 3, 2, 4, 6, -8, 4, -1, -7, -4, -3, -4, -2, 3, 1, 0, -1, 2, -8, -5, 3, -7, 6, 5, -7, 2, -1, -8, -1, -4, -5}, + {6, -5, 0, -3, 2, 3, -1, -5, -1, 0, -3, 3, -7, -7, -7, -5, 0, -8, -2, 1, -3, 6, -2, -2, -1, -8, -6, 1, 1, 5, 5, 2}, + {0, -3, -4, -6, -1, 6, -8, 1, 3, -8, -7, -7, -1, -5, -5, -4, 2, -4, 3, -4, -5, 1, -1, 5, -2, 0, -8, 3, -2, -8, -5, 1}, + {-6, -1, 1, 5, 6, -1, -3, -7, 6, 1, 6, 6, -8, -8, -6, -2, 1, -2, 3, 1, -1, 6, 3, -8, 2, -2, 1, 6, -1, 0, -8, -4}, + {-5, 5, -1, 4, 4, 2, -8, 6, 0, -8, -3, -5, -1, -5, -7, 5, 4, -4, 5, 5, -3, -6, 1, 3, -4, -5, -8, 6, 3, 2, -4, -6}, + {3, 2, 0, -8, 2, 1, -4, 6, 6, 3, 1, -1, 6, -3, -2, 4, -6, -7, -8, -8, -6, -4, -8, 4, 0, 1, 0, -6, 2, -3, 0, -7}, + {-6, 3, -4, 1, 1, 0, -4, 4, 6, -8, 4, -8, -2, -8, -6, 0, -6, 3, -8, 6, 1, 3, 0, -4, -4, -6, 2, 0, 4, -7, 6, -1}, + {-7, 1, -4, -8, -7, 5, -5, -3, -7, 3, -7, 0, 2, 6, -6, -5, -4, -6, 0, 3, 2, -5, -5, 4, 5, 1, -2, 6, 1, -7, 2, -2}, + {4, -5, -5, -1, 3, -4, 6, -6, 6, -4, -1, -3, -3, 5, -8, 6, -4, 3, -3, 3, -8, 4, 4, 4, 0, -4, 3, 2, -6, -1, 5, 4}, + {4, -3, -7, 5, 3, 2, 4, 5, 0, 3, -5, -2, 5, 1, -6, -4, 3, 6, -2, 1, 6, 4, -7, -6, -2, -7, 0, -7, -3, -4, -4, -4}, + {1, -8, -2, 1, -7, -2, -6, 1, 4, 1, 3, 2, -7, 0, 2, -1, 3, -8, 1, 5, 1, 0, -6, 6, -7, -2, -8, -3, 3, -4, 0, 2}, + {1, -3, -3, 2, 4, -6, 1, -4, -7, -7, 0, -1, 4, -7, 0, -3, 3, -2, -5, -8, 5, 3, -4, 5, 3, -5, 4, 0, -3, -5, 1, -3}, + {6, 4, -8, -5, 1, -5, -6, 3, -7, -2, 0, 1, -4, 3, -8, 5, 2, -2, 0, 1, -2, -5, 6, -2, -5, 1, -4, -1, 4, 1, -4, -7}, + {4, -8, -2, 0, -5, -7, 6, -2, 0, -6, 2, 4, -7, -2, 0, 4, 1, -1, 5, 0, 3, -7, 0, 4, -7, 4, 0, -7, 0, 3, -7, -3}, + {3, 1, 3, 3, 3, 6, -5, -7, -7, -6, -8, 5, -1, 1, 3, 5, 1, 2, 3, -2, -5, 1, -1, -1, 4, -4, 6, -4, 5, -3, -2, 5}, + {-2, -5, 0, 0, -7, -1, -1, -1, 1, -4, 0, -5, 5, -3, -6, -2, -1, 5, 0, -8, 1, -8, -2, -5, -7, -6, 2, -8, -2, 4, -1, 1}, + {-8, 0, 3, -5, -1, -5, 1, -4, 6, -2, -3, 3, -7, -3, 0, -6, 3, -5, 2, -3, -7, -2, -2, 6, -8, 1, -8, -4, 5, 2, 3, 4}}; +const signed char array2[32][32] = {{-1, -3, 4, -3, 1, 5, -2, -4, -6, 6, 4, -3, -6, -1, 5, 3, 0, 6, -8, 2, -4, -2, -3, -6, -8, 4, 3, -5, 2, -6, 6, 2}, + {-4, -3, 2, -1, 2, 3, -2, 0, -2, 1, 4, -2, 3, -6, -7, 5, -8, 6, 1, 6, -4, -2, -3, 3, 1, 1, 5, -1, 4, -4, 1, -5}, + {-1, -4, 5, 5, 5, 0, -2, 4, 6, 4, -4, -4, 2, -7, 6, -6, -8, -3, -5, -7, -3, 6, -3, 5, 5, 1, 3, 4, -4, 5, 5, -3}, + {5, -7, 5, 6, 5, 4, 2, -5, 0, 0, 3, -8, -4, -6, -7, -5, -3, 3, 4, 2, -8, -2, -5, 5, 2, -7, -8, -1, -2, 6, -6, -5}, + {6, -6, -3, -6, 6, 1, 4, 4, -4, 5, -5, -8, 0, -6, -4, 1, 0, -4, -6, 3, -4, -3, 4, 3, 2, -8, -6, 0, -8, -8, 2, 2}, + {3, -8, 2, -5, 1, -4, -1, -5, -2, -7, 6, 5, 2, 3, 5, 2, 1, -1, -7, 2, 4, 3, -6, -2, 5, -3, 5, 4, -4, 1, -5, 1}, + {0, 3, -1, -3, 0, 2, -5, -7, 2, 6, -6, -5, 2, -1, 6, -1, 5, 4, 0, 4, -6, -8, -5, 3, -4, 1, -1, 3, 2, 3, -6, -5}, + {-3, -1, -7, -1, -8, 3, -8, -6, -1, -1, 4, 1, 3, -7, -4, -5, -4, -1, 3, -7, 4, 2, 0, -4, 1, -5, -1, 6, -6, 4, 2, -4}, + {6, 1, 5, -8, -2, -6, -2, 1, 2, 3, -3, 4, -1, -8, 5, -2, -5, -2, -4, -5, -1, 3, -3, -1, -3, 1, -3, 2, -4, -5, 1, -5}, + {0, 5, -1, -4, -3, -5, 3, 2, -5, 4, -2, 5, -7, 0, -1, 4, -4, -5, 3, 2, 6, -1, -5, 6, 4, -8, -8, 1, -2, -3, 1, -7}, + {1, -8, 5, 5, 0, 4, 4, -2, 5, -4, -5, -5, -7, -4, 0, -2, 0, 5, -4, -6, -2, 1, 5, 2, 2, 6, 5, 3, 5, -2, 4, 6}, + {0, 6, 1, 3, -6, -7, 4, 6, -7, -6, 6, 5, -8, 3, 6, -4, 3, 2, 4, -5, -4, -4, -8, 3, -4, 4, -6, -4, -2, 4, -3, 6}, + {5, -8, -3, -6, -8, 0, -6, 0, -4, 3, 5, -5, 4, -8, -3, 6, 6, -6, 2, 3, 3, -4, 0, -6, -3, -3, 6, 4, -4, 0, -5, 1}, + {-8, 5, -1, -1, 1, -8, -6, -3, -5, 0, -3, -6, -4, 2, -7, -4, 5, 3, 2, 6, -4, -5, -3, -6, -5, 5, 2, 2, 5, -6, 4, -6}, + {3, -5, -3, 3, 4, 4, -2, 6, 4, -4, 1, -6, -1, -8, -8, -7, -5, -3, -3, -8, 1, -3, -1, -4, -6, 0, 3, -4, 6, 6, 2, -4}, + {-6, 0, -8, -3, 5, 2, 1, -2, -8, 6, 1, -7, 0, 3, 1, 0, -1, -8, 3, 5, 3, -2, 1, 1, 0, -5, -2, 5, -6, -4, 2, 4}, + {-1, 4, 5, -2, -8, -8, 1, -3, 1, 5, -6, 2, 1, 6, 1, -6, -1, 5, -8, 3, 5, -2, -3, -8, 0, -8, -3, -1, 4, -6, 2, 4}, + {3, -7, -2, -3, 4, 5, 6, 6, 3, 0, -5, -7, -6, -8, -4, 6, -6, 2, 5, -6, -6, -7, 4, 3, 1, -4, 1, 6, -5, -2, -2, 2}, + {1, 3, -2, -4, 2, 6, -7, 5, 1, -2, -8, -6, -8, -5, -1, 3, -8, -5, 3, -3, 2, -2, -7, 5, -1, 5, -3, 0, -4, 2, -5, 4}, + {2, 1, 5, -6, 5, -6, 6, 2, 4, -8, 6, -6, 1, -1, -5, 1, -5, -1, 6, 2, -4, 5, 2, -7, 1, 1, 6, -1, 1, -4, 1, 3}, + {1, -5, 6, -2, -1, -7, -8, -6, -7, 6, -5, -6, 0, -5, 5, -5, -6, -5, 2, -2, 2, 2, 2, -8, -4, -4, 1, 4, -1, 5, 5, 2}, + {3, 1, 3, 6, 6, -5, 1, 4, 6, -6, -8, 3, -6, 4, 1, 2, -5, -3, 5, -6, -2, 4, -8, 0, 5, 4, -4, -6, 0, -4, -6, 6}, + {4, 4, -8, -1, -4, 5, -6, 0, 1, -1, -3, 4, -5, -3, 6, -8, 4, 0, -8, 5, -7, 1, -8, 2, -2, 4, -8, -5, -1, 3, 1, 5}, + {0, -7, -4, -1, 3, -7, 3, -4, -1, -1, -8, 6, 1, -4, -7, -4, -3, -6, 3, -1, -4, 3, 6, 2, 5, 2, 5, 5, -4, -2, -4, -7}, + {6, 5, -4, -3, -4, 4, 1, -2, -6, 3, 2, -6, 3, 1, -1, 2, -7, 3, -8, -7, -2, -6, 0, -8, 5, 4, -6, -5, 3, -3, 6, -7}, + {-4, 5, 2, 1, -2, -5, 2, 5, 4, 6, 5, 3, 4, -8, 3, 0, 5, 2, -7, 0, -6, 6, 4, 5, 6, -5, 0, 5, 1, 1, -4, 0}, + {-2, -1, 3, 0, -4, -2, 2, 4, -4, -7, 1, -4, -3, -1, 5, -6, 0, -3, -7, 1, 2, 2, 6, -8, 0, 4, 0, -2, -5, -6, -4, -1}, + {2, -5, -3, -3, -2, -1, 3, -7, -5, 2, 1, 5, -8, 0, 4, -3, -2, -3, -5, -8, -8, -3, 4, -8, -1, 6, 2, -8, 3, 3, -1, -2}, + {-5, 2, -2, -7, -1, 0, -2, 0, 5, 5, -2, -4, 6, -8, -5, -5, -3, 0, 1, -3, 6, -1, -4, 6, 6, 1, -6, -7, 4, -1, -1, -2}, + {3, 1, 3, 4, 0, 3, 0, 0, -6, -7, -1, -1, 6, -1, -6, 1, -5, -6, 1, 2, -6, -7, 2, 1, 6, -7, -4, 3, 0, -3, -3, -1}, + {-8, -2, 6, -2, -8, -1, -3, 2, -4, -1, -6, -8, 5, -7, 1, -7, 6, -7, -7, -3, -6, 6, -2, -8, -4, -6, -1, -3, 2, -2, -6, 5}, + {-3, 1, 4, 6, -4, 1, -1, -1, -6, 6, -3, -4, 3, 2, -2, -3, -6, -2, 5, -2, 6, -5, 1, -7, -3, -2, -1, 1, 3, -3, 5, 6}}; +signed char resultArray[32][32] = {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}; +signed char answerArray[32][32] = {0}; extern void printstr(char* str); extern void int64ToHex(long num, char* str); @@ -56,53 +127,42 @@ void showCounters(void) { printstr("\n"); } -/// -/// vec1を横ベクトル，vec2を縦ベクトルとした内積 -/// -int innerProd(const int* vec1, const int* vec2, int n) { - int vl, avl = n; - int sum = 0; - while(avl != 0) { - asm volatile ("vsetvli %0, %1, e32, m1, ta, ma" - : "=r"(vl) - : "r"(avl)); - asm volatile ("vmv.s.x v3, %0" - : - : "r"(sum)); - asm volatile ("vle32.v v1, (%0)" - : - : "r"(vec1)); - asm volatile ("vlse32.v v2, (%0), %1" - : - : "r"(vec2), "r"(n*sizeof(int))); - asm volatile ("vmul.vv v1, v1, v2"); - asm volatile ("vredsum.vs v1, v1, v3"); - asm volatile ("vmv.x.s %0, v1" - : "=r"(sum)); - vec1 += vl; - vec2 += vl * n; - avl -= vl; +/// @brief 8bit幅の32*32行列乗算 +/// @param array1 +/// @param array2 +/// @param resultArray +void _e8_32x32_matmul(const signed char array1[32][32], const signed char array2[32][32], signed char resultArray[32][32]) { + asm volatile ("vsetvli zero, %0, e8, m1, ta, ma"::"r"(32)); + int i=0, j=0; + for(i=0; i<32; i++) { + // array1の横ベクトルをロード + // v1 = array1[i][*] + asm volatile ("vle8.v v1, (%0)"::"r"(&(array1[i][0]))); + asm volatile ("vmv.s.x v4, zero"); + for(j=0; j<32; j++) { + // array2の縦ベクトルをロード + // v2 = array2[*][j] + asm volatile ("vlse8.v v2, (%0), %1"::"r"(&(array2[0][j])), "r"(32)); + asm volatile ("vmul.vv v3, v1, v2"); + asm volatile ("vredsum.vs v3, v3, v4"); + asm volatile ("vmv.x.s %0, v3":"=r"(resultArray[i][j])); + // resultArray[i*32+j] = tmp; + } } - return sum; } int main(int argc, char** argv) { int i, j, k; clrCounters(); - for(i=0; i<12; i++) { - for(j=0; j<12; j++) { - // resultArray[i][j] = array1[i][*] * array2[*][j] - resultArray[i][j] = innerProd(&(array1[i][0]), &(array2[0][j]), 12); - } - } + _e8_32x32_matmul(array1, array2, resultArray); showCounters(); clrCounters(); - for(i=0; i<12; i++) { - for(j=0; j<12; j++) { - int sum = 0; - for(k=0; k<12; k++) { + for(i=0; i<32; i++) { + for(j=0; j<32; j++) { + signed char sum = 0; + for(k=0; k<32; k++) { sum += array1[i][k] * array2[k][j]; } answerArray[i][j] = sum; @@ -110,8 +170,8 @@ int main(int argc, char** argv) { } showCounters(); _Bool correct = 1; - for(i=0; i<12; i++) { - for(j=0; j<12; j++) { + for(i=0; i<32; i++) { + for(j=0; j<32; j++) { correct = correct && (resultArray[i][j] == answerArray[i][j]); } } diff --git a/src/main/resources/applications_vector/vector_matmul_data.hex b/src/main/resources/applications_vector/vector_matmul_data.hex index e19d431d..8cf52c42 100644 --- a/src/main/resources/applications_vector/vector_matmul_data.hex +++ b/src/main/resources/applications_vector/vector_matmul_data.hex @@ -1,303 +1,527 @@ -ffffff9c -00000000 -00000051 -00000054 -0000002e -ffffffa1 -ffffffd9 -0000000c -00000044 -00000059 -ffffffba -0000005e -ffffffd8 -00000032 -0000006e -0000005b -0000004b -00000033 -00000055 -00000017 -ffffff92 -ffffff99 -ffffff98 -0000002e -ffffffea -00000068 -0000002b -00000043 -fffffffc -00000039 -ffffffad -ffffffda -ffffffb3 -ffffffb0 -ffffffbf -00000022 -ffffffd6 -ffffffb9 -ffffff80 -00000010 -00000001 -00000017 -fffffff3 -ffffffd6 -ffffffe1 -ffffff98 -ffffff8c -00000068 -0000007e -ffffffd7 -fffffff0 -ffffffc0 -ffffffec -ffffffb0 -fffffff6 -00000019 -00000023 -00000006 -ffffffa7 -ffffffda -00000050 -ffffffde -ffffffac -0000006a -00000072 -0000005d -00000077 -ffffff90 -00000016 -0000004c -0000006d -ffffffcd -00000054 -ffffff9b -fffffff6 -ffffffcd -ffffffca -00000057 -ffffffea -ffffff87 -ffffff8c -0000005c -ffffffb6 -00000021 -00000017 -ffffffcd -00000061 -ffffff9b -00000077 -ffffffaa -ffffffed -00000070 -00000046 -ffffffcd -00000018 -0000003d -0000001f -00000029 -ffffff83 -fffffff7 -0000004f -ffffffd6 -ffffff92 -ffffffba -ffffffdd -fffffff4 -ffffffe9 -ffffffe0 -ffffff96 -ffffff98 -00000051 -00000033 -00000004 -0000004a -00000069 -ffffffb9 -fffffff4 -ffffff8e -00000068 -ffffffd8 -ffffffb8 -ffffffd7 -ffffffa4 -ffffffd7 -00000054 -ffffffda -ffffffc4 -00000011 -0000007d -ffffff95 -ffffffb2 -ffffff99 -ffffffd2 -ffffffcb -0000003b -ffffffab -0000000b -ffffffda -fffffff2 -0000005d -00000026 -00000014 -ffffffd2 -0000000a -ffffffd1 -00000052 -ffffffdb -fffffff0 -ffffffdd -00000005 -ffffff84 -0000005f -ffffffca -00000059 -ffffffab -00000020 -00000057 -ffffffae -ffffffa6 -fffffffb -ffffffe4 -ffffffd8 -00000036 -00000004 -fffffff2 -00000044 -00000072 -fffffffe -00000037 -ffffffdb -ffffffa3 -ffffffd5 -ffffff98 -0000001d -00000015 -00000016 -0000001b -0000003e -00000022 -00000075 -ffffffc6 -00000071 -0000002b -00000018 -ffffffdb -00000005 -0000002b -0000006d -ffffff84 -ffffff83 -ffffffd8 -00000056 -00000062 -ffffffc2 -00000029 -ffffffb1 -fffffff7 -00000067 -ffffffd3 -00000066 -00000049 -ffffff96 -00000064 -00000031 -ffffffc6 -00000019 -ffffffce -0000003e -0000007d -00000073 -ffffffb0 -00000043 -ffffffcf -00000002 -ffffffe2 -ffffffba -00000027 -0000007b -ffffffe2 -ffffff85 -fffffff8 -0000001a -00000043 -ffffffe2 -ffffffbc -00000020 -0000000f -00000068 -ffffffa5 -0000003c -00000015 -ffffff9e -00000073 -ffffffc4 -00000028 -ffffffd5 -0000005f -ffffffcc -00000043 -ffffffc8 -fffffff8 -ffffffae -0000001c -ffffffa3 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--- a/src/main/resources/applications_vector/vector_matmul_inst.hex +++ b/src/main/resources/applications_vector/vector_matmul_inst.hex @@ -33,7 +33,7 @@ 03828293 30529073 00005197 -dd018193 +15018193 10000217 ff720213 fc027213 @@ -42,7 +42,7 @@ f1402573 00b57063 00006137 ff01011b -76c0006f +7680006f ef010113 00113423 00213823 @@ -78,7 +78,7 @@ ef010113 34202573 341025f3 00010613 -3e4000ef +3e0000ef 34151073 000022b7 8002829b @@ -129,61 +129,60 @@ c02024f3 c0002973 b0302473 00004517 -2a850513 -170000ef +62850513 +16c000ef 00810593 00090513 -120000ef +11c000ef 00810513 -15c000ef +158000ef 00004517 -29050513 -150000ef +61050513 +14c000ef 00810593 00048513 -100000ef +0fc000ef 00810513 -13c000ef +138000ef 00004517 -28050513 -130000ef +60050513 +12c000ef 00810593 00040513 -0e0000ef +0dc000ef 00810513 -11c000ef +118000ef 00004517 -27050513 -110000ef +5f050513 +10c000ef 03813083 03013403 02813483 02013903 04010113 00008067 +02000793 +0c07f057 +02000813 00050893 -04060a63 -00261313 -00060793 -00000513 -0d07f857 -0008069b -420561d7 -0208e087 -0a65e107 -961120d7 -0211a0d7 -42102557 -02c8073b -00269693 -410787bb -0005051b -00d888b3 -00271713 -00e585b3 -fc0792e3 -00008067 -00000513 +40050313 +02000513 +02088087 +42006257 +00000793 +00f58733 +0b070107 +961121d7 +023221d7 +423026d7 +0007871b +00e60733 +00d70023 +00178793 +fca79ee3 +02088893 +02060613 +fc6892e3 00008067 b0201073 b0001073 @@ -234,7 +233,7 @@ fe010113 c0202673 c00025f3 00004717 -13470713 +4b870713 06300793 100006b7 00f68023 @@ -266,7 +265,7 @@ fee812e3 00168693 fe071ae3 00004697 -0bc68693 +44068693 00a00713 100005b7 00e58023 @@ -305,7 +304,7 @@ fe010113 00113c23 00050413 00004717 -03070713 +3b470713 04500793 100006b7 00f68023 @@ -347,14 +346,14 @@ ff0792e3 00b00793 02a7e063 00004717 -f1070713 +29470713 00251513 00e50533 00052783 00e787b3 00078067 00004717 -09470713 +41870713 05500793 100006b7 00f68023 @@ -370,7 +369,7 @@ fe079ae3 00170713 fe079ae3 00004717 -07470713 +3f870713 00a00793 100006b7 00f68023 @@ -380,7 +379,7 @@ fe079ae3 fff00513 ec9ff0ef 00004717 -f1470713 +29870713 04900793 100006b7 00f68023 @@ -397,7 +396,7 @@ fc0786e3 fe079ae3 fb9ff06f 00004717 -ef870713 +27c70713 04900793 100006b7 00f68023 @@ -414,7 +413,7 @@ f80788e3 fe079ae3 f75ff06f 00004717 -edc70713 +26070713 04900793 100006b7 00f68023 @@ -431,7 +430,7 @@ f40786e3 fe079ae3 f31ff06f 00004717 -eb870713 +23c70713 04c00793 100006b7 00f68023 @@ -448,7 +447,7 @@ f00784e3 fe079ae3 eedff06f 00004717 -e9470713 +21870713 04c00793 100006b7 00f68023 @@ -465,7 +464,7 @@ ec0782e3 fe079ae3 ea9ff06f 00004717 -e7070713 +1f470713 05300793 100006b7 00f68023 @@ -482,7 +481,7 @@ e80780e3 fe079ae3 e65ff06f 00004717 -e5470713 +1d870713 05300793 100006b7 00f68023 @@ -499,7 +498,7 @@ e2078ee3 fe079ae3 e21ff06f 00004717 -e3070713 +1b470713 04500793 100006b7 00f68023 @@ -588,7 +587,7 @@ fee78fa3 fef61ce3 00008067 00004797 -d247b783 +0a87b783 02f70733 fec578e3 00050793 @@ -639,109 +638,76 @@ ff5ff06f fee78fa3 fe0718e3 00008067 -fe010113 -00113c23 -00813823 -00913423 -01213023 +ff010113 +00113423 +00813023 b0201073 b0001073 b0301073 -00003417 -5dc40413 -00004497 -81448493 -00004297 -c2c28293 -00040f13 -00004f97 -830f8f93 -03000313 -00003e17 -7f4e0e13 -00028e93 -000e0513 -000f0593 -00000893 -00c00693 -0d06f757 -0007061b -4208e1d7 -0205e087 -0a656107 -961120d7 -0211a0d7 -42102857 -0017179b -00e787bb -0027979b -00261613 -00279793 -40e686bb -0008089b -00c585b3 -00f50533 -fa069ee3 -010ea023 -004e0e13 -004e8e93 -f9cf9ee3 -030f0f13 -03028293 -f89f12e3 -f1cff0ef +00004617 +fc860613 +00003597 +5e058593 +00004517 +9d850513 +85dff0ef +fb4ff0ef b0201073 b0001073 b0301073 -a4818913 -00090313 -00004897 -9cc88893 -00004e17 -994e0e13 -000e0513 -00030813 -dc050713 -00040693 -00000613 -0006a583 -00072783 -03070713 -00468693 -02b787bb -00c7863b -fea714e3 -00c82023 -00470513 -00480813 -fca896e3 -03040413 -03030313 -fa941ce3 -ea8ff0ef +c0818413 +00040e93 +00000e13 +00004f17 +9b0f0f13 +00004317 +9c830313 +02000f93 +005e1893 +000f0513 +01e888b3 +000e8813 +c0050713 +00088613 +00000793 +00064683 +00074583 +02070713 +00160613 +02b686bb +00f687bb +0187979b +4187d79b +fea710e3 +00f80023 +00170513 +00180813 +fca312e3 +001e0e13 +020e8e93 +fbfe14e3 +f28ff0ef 00004697 -b4c68693 -a7818593 +f3c68693 +c2818593 00100513 -fd068793 -00090713 +fe068793 +00040713 00050a63 -0007a503 -00072603 +00078503 +00070603 40c50533 00153513 -00478793 -00470713 +00178793 +00170713 fed792e3 -03078693 -03090913 +02078693 +02040413 fcb698e3 -01813083 -01013403 -00813483 -00013903 +00813083 +00013403 00154513 -02010113 +01010113 00008067 fff00513 00008067 diff --git a/src/test/scala/hajime/simple4Stage/Core_ApplicationTest.scala b/src/test/scala/hajime/simple4Stage/Core_ApplicationTest.scala index f0f77d90..4cad269f 100644 --- a/src/test/scala/hajime/simple4Stage/Core_ApplicationTest.scala +++ b/src/test/scala/hajime/simple4Stage/Core_ApplicationTest.scala @@ -21,7 +21,7 @@ object Core_ApplicationTest { }.fork { initialiseMemWithAxi(s"src/main/resources/applications_${testType}/${testName}_data.hex", dut.io.dmem_initialiseAXI, dut.io.dcache_initialising, dut.clock, 0x4000) }.join() - dut.clock.setTimeout(65536) + dut.clock.setTimeout(1048576) dut.io.reset_vector.poke(0.U) dut.io.hartid.poke(0.U) From 6222eb72cc626d448d314447e6f2d6eabc2270d9 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Wed, 29 Nov 2023 18:05:20 +0900 Subject: [PATCH 02/13] some Register Initialisations --- src/main/scala/hajime/common/HajimeCoreParams.scala | 1 + src/main/scala/hajime/simple4Stage/Core.scala | 2 +- src/main/scala/hajime/vectormodules/VectorCpu.scala | 8 ++++++-- .../scala/hajime/publicmodules/Dcache_for_Verilator.scala | 3 ++- 4 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/main/scala/hajime/common/HajimeCoreParams.scala b/src/main/scala/hajime/common/HajimeCoreParams.scala index 4ea8ac0d..3a4d79f4 100644 --- a/src/main/scala/hajime/common/HajimeCoreParams.scala +++ b/src/main/scala/hajime/common/HajimeCoreParams.scala @@ -32,6 +32,7 @@ case class HajimeCoreParams( useVector: Boolean = true, usePackedSIMD: Boolean = false, debug: Boolean = true, + fpga: Boolean = false, vlen: Int = 256, vecAluExecUnitNum: Int = 2, ) { diff --git a/src/main/scala/hajime/simple4Stage/Core.scala b/src/main/scala/hajime/simple4Stage/Core.scala index cf90cfbd..b0df1974 100644 --- a/src/main/scala/hajime/simple4Stage/Core.scala +++ b/src/main/scala/hajime/simple4Stage/Core.scala @@ -47,7 +47,7 @@ class Core[T <: CpuModule](cpu: Class[T])(implicit params: HajimeCoreParams) ext } object Core extends App { - implicit val params = HajimeCoreParams() + implicit val params = HajimeCoreParams(useException = false, useVector = true, debug = false) def apply[T <: CpuModule](cpu: Class[T])(implicit params: HajimeCoreParams): Core[T] = { if(cpu == classOf[VectorCpu] && !params.useVector) { throw new Exception("useVector is false") diff --git a/src/main/scala/hajime/vectormodules/VectorCpu.scala b/src/main/scala/hajime/vectormodules/VectorCpu.scala index ad9d2ca0..fcfe9476 100644 --- a/src/main/scala/hajime/vectormodules/VectorCpu.scala +++ b/src/main/scala/hajime/vectormodules/VectorCpu.scala @@ -62,8 +62,12 @@ class VectorCpu(implicit params: HajimeCoreParams) extends CpuModule with Scalar val decoded_inst = Wire(new InstBundle()) decoded_inst := io.frontend.resp.bits.inst - val ID_EX_REG = Reg(Valid(new ID_EX_IO())) - val EX_WB_REG = Reg(Valid(new EX_WB_IO())) + val ID_EX_REG = RegInit(Valid(new ID_EX_IO()).Lit( + _.valid -> false.B, + )) + val EX_WB_REG = RegInit(Valid(new EX_WB_IO()).Lit( + _.valid -> false.B, + )) // これらがtrueならばベクトル命令を発行できる val vs1NonRequiredOrReady = !vrfReadyTable.io.vs1Check.valid || vrfReadyTable.io.vs1Check.ready diff --git a/src/test/scala/hajime/publicmodules/Dcache_for_Verilator.scala b/src/test/scala/hajime/publicmodules/Dcache_for_Verilator.scala index 3ae51d0a..90649a78 100644 --- a/src/test/scala/hajime/publicmodules/Dcache_for_Verilator.scala +++ b/src/test/scala/hajime/publicmodules/Dcache_for_Verilator.scala @@ -11,6 +11,7 @@ import org.scalatest.flatspec._ import scala.io._ // 命令キャッシュと異なりマスター側のreadyが下がることは無いので，出力のストールは考えない +// TODO: FPGA用に例えばledへの出力を追加する，正常終了フラグや例外終了フラグなど class Dcache_for_Verilator(dcacheBaseAddr: Int, tohost: Int, memsize: Int = 0x2000) extends Module with ChecksAxiReadResp with ChecksAxiWriteResp{ require(memsize % 8 == 0, s"memsize $memsize is not multiple of 8") @@ -79,5 +80,5 @@ class Dcache_for_Verilator(dcacheBaseAddr: Int, tohost: Int, memsize: Int = 0x20 object Dcache_for_Verilator extends App { def apply(dcacheBaseAddr: Int = 0x00004000, tohost: Int = 0x10000000, memsize: Int = 0x2000): Dcache_for_Verilator = new Dcache_for_Verilator(dcacheBaseAddr, tohost, memsize) - ChiselStage.emitSystemVerilogFile(Dcache_for_Verilator(), firtoolOpts = COMPILE_CONSTANTS.FIRTOOLOPS) + ChiselStage.emitSystemVerilogFile(Dcache_for_Verilator(dcacheBaseAddr = 0x00004000, tohost = 0x10000000, memsize = 8192), firtoolOpts = COMPILE_CONSTANTS.FIRTOOLOPS) } \ No newline at end of file From 3a94d89e2a6ea87b59dba1a50b5ba85b76ca1883 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Wed, 29 Nov 2023 18:08:48 +0900 Subject: [PATCH 03/13] apps for FPGA --- .../resources/applications_for_fpga/build.sh | 0 .../applications_for_fpga/headers/crt.S | 162 + .../applications_for_fpga/headers/encoding.h | 5013 +++++++++++++++++ .../applications_for_fpga/headers/syscalls.c | 156 + .../applications_for_fpga/headers/test.ld | 66 + src/main/resources/build_helloworld_asm.sh | 17 +- src/main/resources/simpleTest.S | 26 + src/main/resources/simpleTest.dump | 106 + src/main/resources/simpleTest_inst.hex | 81 + .../Data32To64.scala | 12 + 10 files changed, 5634 insertions(+), 5 deletions(-) create mode 100644 src/main/resources/applications_for_fpga/build.sh create mode 100644 src/main/resources/applications_for_fpga/headers/crt.S create mode 100644 src/main/resources/applications_for_fpga/headers/encoding.h create mode 100644 src/main/resources/applications_for_fpga/headers/syscalls.c create mode 100644 src/main/resources/applications_for_fpga/headers/test.ld create mode 100644 src/main/resources/simpleTest.S create mode 100644 src/main/resources/simpleTest.dump create mode 100644 src/main/resources/simpleTest_inst.hex create mode 100644 src/main/scala/my_random_useful_programs/Data32To64.scala diff --git a/src/main/resources/applications_for_fpga/build.sh b/src/main/resources/applications_for_fpga/build.sh new file mode 100644 index 00000000..e69de29b diff --git a/src/main/resources/applications_for_fpga/headers/crt.S b/src/main/resources/applications_for_fpga/headers/crt.S new file mode 100644 index 00000000..a2f8fca5 --- /dev/null +++ b/src/main/resources/applications_for_fpga/headers/crt.S @@ -0,0 +1,162 @@ +# See LICENSE for license details. + +#include "encoding.h" + +#if __riscv_xlen == 64 +# define LREG ld +# define SREG sd +# define REGBYTES 8 +#else +# define LREG lw +# define SREG sw +# define REGBYTES 4 +#endif + + .section ".text.init" + .globl _start +_start: + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10,0 + li x11,0 + li x12,0 + li x13,0 + li x14,0 + li x15,0 + li x16,0 + li x17,0 + li x18,0 + li x19,0 + li x20,0 + li x21,0 + li x22,0 + li x23,0 + li x24,0 + li x25,0 + li x26,0 + li x27,0 + li x28,0 + li x29,0 + li x30,0 + li x31,0 + + # initialize trap vector + la t0, trap_entry + csrw mtvec, t0 + + # initialize global pointer +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + la tp, _end + 63 + and tp, tp, -64 + + # get core id + csrr a0, mhartid + # for now, assume only 1 core + li a1, 1 +1:bgeu a0, a1, 1b + + # initialise stack pointer + li sp, 0x00005FF0 + + j _init + + .align 2 +trap_entry: + addi sp, sp, -272 + + SREG x1, 1*REGBYTES(sp) + SREG x2, 2*REGBYTES(sp) + SREG x3, 3*REGBYTES(sp) + SREG x4, 4*REGBYTES(sp) + SREG x5, 5*REGBYTES(sp) + SREG x6, 6*REGBYTES(sp) + SREG x7, 7*REGBYTES(sp) + SREG x8, 8*REGBYTES(sp) + SREG x9, 9*REGBYTES(sp) + SREG x10, 10*REGBYTES(sp) + SREG x11, 11*REGBYTES(sp) + SREG x12, 12*REGBYTES(sp) + SREG x13, 13*REGBYTES(sp) + SREG x14, 14*REGBYTES(sp) + SREG x15, 15*REGBYTES(sp) + SREG x16, 16*REGBYTES(sp) + SREG x17, 17*REGBYTES(sp) + SREG x18, 18*REGBYTES(sp) + SREG x19, 19*REGBYTES(sp) + SREG x20, 20*REGBYTES(sp) + SREG x21, 21*REGBYTES(sp) + SREG x22, 22*REGBYTES(sp) + SREG x23, 23*REGBYTES(sp) + SREG x24, 24*REGBYTES(sp) + SREG x25, 25*REGBYTES(sp) + SREG x26, 26*REGBYTES(sp) + SREG x27, 27*REGBYTES(sp) + SREG x28, 28*REGBYTES(sp) + SREG x29, 29*REGBYTES(sp) + SREG x30, 30*REGBYTES(sp) + SREG x31, 31*REGBYTES(sp) + + csrr a0, mcause + csrr a1, mepc + mv a2, sp + jal handle_trap + csrw mepc, a0 + + # Remain in M-mode after eret + # we can write to mstatus but core supports only M-mode and ignore this + li t0, MSTATUS_MPP + csrs mstatus, t0 + + LREG x1, 1*REGBYTES(sp) + LREG x2, 2*REGBYTES(sp) + LREG x3, 3*REGBYTES(sp) + LREG x4, 4*REGBYTES(sp) + LREG x5, 5*REGBYTES(sp) + LREG x6, 6*REGBYTES(sp) + LREG x7, 7*REGBYTES(sp) + LREG x8, 8*REGBYTES(sp) + LREG x9, 9*REGBYTES(sp) + LREG x10, 10*REGBYTES(sp) + LREG x11, 11*REGBYTES(sp) + LREG x12, 12*REGBYTES(sp) + LREG x13, 13*REGBYTES(sp) + LREG x14, 14*REGBYTES(sp) + LREG x15, 15*REGBYTES(sp) + LREG x16, 16*REGBYTES(sp) + LREG x17, 17*REGBYTES(sp) + LREG x18, 18*REGBYTES(sp) + LREG x19, 19*REGBYTES(sp) + LREG x20, 20*REGBYTES(sp) + LREG x21, 21*REGBYTES(sp) + LREG x22, 22*REGBYTES(sp) + LREG x23, 23*REGBYTES(sp) + LREG x24, 24*REGBYTES(sp) + LREG x25, 25*REGBYTES(sp) + LREG x26, 26*REGBYTES(sp) + LREG x27, 27*REGBYTES(sp) + LREG x28, 28*REGBYTES(sp) + LREG x29, 29*REGBYTES(sp) + LREG x30, 30*REGBYTES(sp) + LREG x31, 31*REGBYTES(sp) + + addi sp, sp, 272 + mret + +.section ".tohost","aw",@progbits +.align 6 +.globl tohost +tohost: .dword 0 +.align 6 +.globl fromhost +fromhost: .dword 0 diff --git a/src/main/resources/applications_for_fpga/headers/encoding.h b/src/main/resources/applications_for_fpga/headers/encoding.h new file mode 100644 index 00000000..01889d1a --- /dev/null +++ b/src/main/resources/applications_for_fpga/headers/encoding.h @@ -0,0 +1,5013 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* Copyright (c) 2023 RISC-V International */ + +/* + * This file is auto-generated by running 'make' in + * https://github.com/riscv/riscv-opcodes (02b4866) + */ + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_UBE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_VS 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS_SBE 0x0000001000000000 +#define MSTATUS_MBE 0x0000002000000000 +#define MSTATUS_GVA 0x0000004000000000 +#define MSTATUS_MPV 0x0000008000000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define MSTATUSH_SBE 0x00000010 +#define MSTATUSH_MBE 0x00000020 +#define MSTATUSH_GVA 0x00000040 +#define MSTATUSH_MPV 0x00000080 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_UBE 0x00000040 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_VS 0x00000600 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define HSTATUS_VSXL 0x300000000 +#define HSTATUS_VTSR 0x00400000 +#define HSTATUS_VTW 0x00200000 +#define HSTATUS_VTVM 0x00100000 +#define HSTATUS_VGEIN 0x0003f000 +#define HSTATUS_HU 0x00000200 +#define HSTATUS_SPVP 0x00000100 +#define HSTATUS_SPV 0x00000080 +#define HSTATUS_GVA 0x00000040 +#define HSTATUS_VSBE 0x00000020 + +#define USTATUS_UIE 0x00000001 +#define USTATUS_UPIE 0x00000010 + +#define MNSTATUS_NMIE 0x00000008 +#define MNSTATUS_MNPP 0x00001800 +#define MNSTATUS_MNPV 0x00000080 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 +#define DCSR_CAUSE_GROUP 6 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_USIP (1 << IRQ_U_SOFT) +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_VSSIP (1 << IRQ_VS_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_UTIP (1 << IRQ_U_TIMER) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_VSTIP (1 << IRQ_VS_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_UEIP (1 << IRQ_U_EXT) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_VSEIP (1 << IRQ_VS_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) +#define MIP_SGEIP (1 << IRQ_S_GEXT) +#define MIP_LCOFIP (1 << IRQ_LCOF) + +#define MIP_S_MASK (MIP_SSIP | MIP_STIP | MIP_SEIP) +#define MIP_VS_MASK (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) +#define MIP_HS_MASK (MIP_VS_MASK | MIP_SGEIP) + +#define MIDELEG_FORCED_MASK MIP_HS_MASK + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define MENVCFG_FIOM 0x00000001 +#define MENVCFG_CBIE 0x00000030 +#define MENVCFG_CBCFE 0x00000040 +#define MENVCFG_CBZE 0x00000080 +#define MENVCFG_HADE 0x2000000000000000 +#define MENVCFG_PBMTE 0x4000000000000000 +#define MENVCFG_STCE 0x8000000000000000 + +#define MENVCFGH_HADE 0x20000000 +#define MENVCFGH_PBMTE 0x40000000 +#define MENVCFGH_STCE 0x80000000 + +#define MSTATEEN0_CS 0x00000001 +#define MSTATEEN0_FCSR 0x00000002 +#define MSTATEEN0_JVT 0x00000004 +#define MSTATEEN0_HCONTEXT 0x0200000000000000 +#define MSTATEEN0_HENVCFG 0x4000000000000000 +#define MSTATEEN_HSTATEEN 0x8000000000000000 + +#define MSTATEEN0H_HCONTEXT 0x02000000 +#define MSTATEEN0H_HENVCFG 0x40000000 +#define MSTATEENH_HSTATEEN 0x80000000 + +#define MHPMEVENT_VUINH 0x0400000000000000 +#define MHPMEVENT_VSINH 0x0800000000000000 +#define MHPMEVENT_UINH 0x1000000000000000 +#define MHPMEVENT_SINH 0x2000000000000000 +#define MHPMEVENT_MINH 0x4000000000000000 +#define MHPMEVENT_OF 0x8000000000000000 + +#define MHPMEVENTH_VUINH 0x04000000 +#define MHPMEVENTH_VSINH 0x08000000 +#define MHPMEVENTH_UINH 0x10000000 +#define MHPMEVENTH_SINH 0x20000000 +#define MHPMEVENTH_MINH 0x40000000 +#define MHPMEVENTH_OF 0x80000000 + +#define HENVCFG_FIOM 0x00000001 +#define HENVCFG_CBIE 0x00000030 +#define HENVCFG_CBCFE 0x00000040 +#define HENVCFG_CBZE 0x00000080 +#define HENVCFG_HADE 0x2000000000000000 +#define HENVCFG_PBMTE 0x4000000000000000 +#define HENVCFG_STCE 0x8000000000000000 + +#define HENVCFGH_HADE 0x20000000 +#define HENVCFGH_PBMTE 0x40000000 +#define HENVCFGH_STCE 0x80000000 + +#define HSTATEEN0_CS 0x00000001 +#define HSTATEEN0_FCSR 0x00000002 +#define HSTATEEN0_JVT 0x00000004 +#define HSTATEEN0_SCONTEXT 0x0200000000000000 +#define HSTATEEN0_SENVCFG 0x4000000000000000 +#define HSTATEEN_SSTATEEN 0x8000000000000000 + +#define HSTATEEN0H_SCONTEXT 0x02000000 +#define HSTATEEN0H_SENVCFG 0x40000000 +#define HSTATEENH_SSTATEEN 0x80000000 + +#define SENVCFG_FIOM 0x00000001 +#define SENVCFG_CBIE 0x00000030 +#define SENVCFG_CBCFE 0x00000040 +#define SENVCFG_CBZE 0x00000080 + +#define SSTATEEN0_CS 0x00000001 +#define SSTATEEN0_FCSR 0x00000002 +#define SSTATEEN0_JVT 0x00000004 + +#define MSECCFG_MML 0x00000001 +#define MSECCFG_MMWP 0x00000002 +#define MSECCFG_RLB 0x00000004 +#define MSECCFG_USEED 0x00000100 +#define MSECCFG_SSEED 0x00000200 + +/* jvt fields */ +#define JVT_MODE 0x3F +#define JVT_BASE (~0x3F) + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_M 3 + +#define PRV_HS (PRV_S + 1) + +#define SATP32_MODE 0x80000000 +#define SATP32_ASID 0x7FC00000 +#define SATP32_PPN 0x003FFFFF +#define SATP64_MODE 0xF000000000000000 +#define SATP64_ASID 0x0FFFF00000000000 +#define SATP64_PPN 0x00000FFFFFFFFFFF + +#define SATP_MODE_OFF 0 +#define SATP_MODE_SV32 1 +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 11 + +#define HGATP32_MODE 0x80000000 +#define HGATP32_VMID 0x1FC00000 +#define HGATP32_PPN 0x003FFFFF + +#define HGATP64_MODE 0xF000000000000000 +#define HGATP64_VMID 0x03FFF00000000000 +#define HGATP64_PPN 0x00000FFFFFFFFFFF + +#define HGATP_MODE_OFF 0 +#define HGATP_MODE_SV32X4 1 +#define HGATP_MODE_SV39X4 8 +#define HGATP_MODE_SV48X4 9 +#define HGATP_MODE_SV57X4 10 + +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 +#define PMP_SHIFT 2 + +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 +#define PMP_NAPOT 0x18 + +#define IRQ_U_SOFT 0 +#define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_U_TIMER 4 +#define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_U_EXT 8 +#define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_COP 12 +#define IRQ_LCOF 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +/* page table entry (PTE) fields */ +#define PTE_V 0x001 /* Valid */ +#define PTE_R 0x002 /* Read */ +#define PTE_W 0x004 /* Write */ +#define PTE_X 0x008 /* Execute */ +#define PTE_U 0x010 /* User */ +#define PTE_G 0x020 /* Global */ +#define PTE_A 0x040 /* Accessed */ +#define PTE_D 0x080 /* Dirty */ +#define PTE_SOFT 0x300 /* Reserved for Software */ +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */ +#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */ +#define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */ +#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */ + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#if __riscv_xlen == 64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +# define SATP_MODE SATP64_MODE +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +# define SATP_MODE SATP32_MODE +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif + +/* Automatically generated by parse_opcodes. */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_ADD16 0x40000077 +#define MASK_ADD16 0xfe00707f +#define MATCH_ADD32 0x40002077 +#define MASK_ADD32 0xfe00707f +#define MATCH_ADD64 0xc0001077 +#define MASK_ADD64 0xfe00707f +#define MATCH_ADD8 0x48000077 +#define MASK_ADD8 0xfe00707f +#define MATCH_ADD_UW 0x800003b +#define MASK_ADD_UW 0xfe00707f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_AES32DSI 0x2a000033 +#define MASK_AES32DSI 0x3e00707f +#define MATCH_AES32DSMI 0x2e000033 +#define MASK_AES32DSMI 0x3e00707f +#define MATCH_AES32ESI 0x22000033 +#define MASK_AES32ESI 0x3e00707f +#define MATCH_AES32ESMI 0x26000033 +#define MASK_AES32ESMI 0x3e00707f +#define MATCH_AES64DS 0x3a000033 +#define MASK_AES64DS 0xfe00707f +#define MATCH_AES64DSM 0x3e000033 +#define MASK_AES64DSM 0xfe00707f +#define MATCH_AES64ES 0x32000033 +#define MASK_AES64ES 0xfe00707f +#define MATCH_AES64ESM 0x36000033 +#define MASK_AES64ESM 0xfe00707f +#define MATCH_AES64IM 0x30001013 +#define MASK_AES64IM 0xfff0707f +#define MATCH_AES64KS1I 0x31001013 +#define MASK_AES64KS1I 0xff00707f +#define MATCH_AES64KS2 0x7e000033 +#define MASK_AES64KS2 0xfe00707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ANDN 0x40007033 +#define MASK_ANDN 0xfe00707f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_AVE 0xe0000077 +#define MASK_AVE 0xfe00707f +#define MATCH_BCLR 0x48001033 +#define MASK_BCLR 0xfe00707f +#define MATCH_BCLRI 0x48001013 +#define MASK_BCLRI 0xfc00707f +#define MATCH_BCOMPRESS 0x8006033 +#define MASK_BCOMPRESS 0xfe00707f +#define MATCH_BCOMPRESSW 0x800603b +#define MASK_BCOMPRESSW 0xfe00707f +#define MATCH_BDECOMPRESS 0x48006033 +#define MASK_BDECOMPRESS 0xfe00707f +#define MATCH_BDECOMPRESSW 0x4800603b +#define MASK_BDECOMPRESSW 0xfe00707f +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BEXT 0x48005033 +#define MASK_BEXT 0xfe00707f +#define MATCH_BEXTI 0x48005013 +#define MASK_BEXTI 0xfc00707f +#define MATCH_BFP 0x48007033 +#define MASK_BFP 0xfe00707f +#define MATCH_BFPW 0x4800703b +#define MASK_BFPW 0xfe00707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_BINV 0x68001033 +#define MASK_BINV 0xfe00707f +#define MATCH_BINVI 0x68001013 +#define MASK_BINVI 0xfc00707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BMATFLIP 0x60301013 +#define MASK_BMATFLIP 0xfff0707f +#define MATCH_BMATOR 0x8003033 +#define MASK_BMATOR 0xfe00707f +#define MATCH_BMATXOR 0x48003033 +#define MASK_BMATXOR 0xfe00707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BSET 0x28001033 +#define MASK_BSET 0xfe00707f +#define MATCH_BSETI 0x28001013 +#define MASK_BSETI 0xfc00707f +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_LBU 0x8000 +#define MASK_C_LBU 0xfc03 +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_LH 0x8440 +#define MASK_C_LH 0xfc43 +#define MATCH_C_LHU 0x8400 +#define MASK_C_LHU 0xfc43 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_MUL 0x9c41 +#define MASK_C_MUL 0xfc63 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xef83 +#define MATCH_C_NOT 0x9c75 +#define MASK_C_NOT 0xfc7f +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_SB 0x8800 +#define MASK_C_SB 0xfc03 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_SEXT_B 0x9c65 +#define MASK_C_SEXT_B 0xfc7f +#define MATCH_C_SEXT_H 0x9c6d +#define MASK_C_SEXT_H 0xfc7f +#define MATCH_C_SH 0x8c00 +#define MASK_C_SH 0xfc43 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_ZEXT_B 0x9c61 +#define MASK_C_ZEXT_B 0xfc7f +#define MATCH_C_ZEXT_H 0x9c69 +#define MASK_C_ZEXT_H 0xfc7f +#define MATCH_C_ZEXT_W 0x9c71 +#define MASK_C_ZEXT_W 0xfc7f +#define MATCH_CBO_CLEAN 0x10200f +#define MASK_CBO_CLEAN 0xfff07fff +#define MATCH_CBO_FLUSH 0x20200f +#define MASK_CBO_FLUSH 0xfff07fff +#define MATCH_CBO_INVAL 0x200f +#define MASK_CBO_INVAL 0xfff07fff +#define MATCH_CBO_ZERO 0x40200f +#define MASK_CBO_ZERO 0xfff07fff +#define MATCH_CLMUL 0xa001033 +#define MASK_CLMUL 0xfe00707f +#define MATCH_CLMULH 0xa003033 +#define MASK_CLMULH 0xfe00707f +#define MATCH_CLMULR 0xa002033 +#define MASK_CLMULR 0xfe00707f +#define MATCH_CLRS16 0xae800077 +#define MASK_CLRS16 0xfff0707f +#define MATCH_CLRS32 0xaf800077 +#define MASK_CLRS32 0xfff0707f +#define MATCH_CLRS8 0xae000077 +#define MASK_CLRS8 0xfff0707f +#define MATCH_CLZ 0x60001013 +#define MASK_CLZ 0xfff0707f +#define MATCH_CLZ16 0xae900077 +#define MASK_CLZ16 0xfff0707f +#define MATCH_CLZ32 0xaf900077 +#define MASK_CLZ32 0xfff0707f +#define MATCH_CLZ8 0xae100077 +#define MASK_CLZ8 0xfff0707f +#define MATCH_CLZW 0x6000101b +#define MASK_CLZW 0xfff0707f +#define MATCH_CM_JALT 0xa002 +#define MASK_CM_JALT 0xfc03 +#define MATCH_CM_MVA01S 0xac62 +#define MASK_CM_MVA01S 0xfc63 +#define MATCH_CM_MVSA01 0xac22 +#define MASK_CM_MVSA01 0xfc63 +#define MATCH_CM_POP 0xba02 +#define MASK_CM_POP 0xff03 +#define MATCH_CM_POPRET 0xbe02 +#define MASK_CM_POPRET 0xff03 +#define MATCH_CM_POPRETZ 0xbc02 +#define MASK_CM_POPRETZ 0xff03 +#define MATCH_CM_PUSH 0xb802 +#define MASK_CM_PUSH 0xff03 +#define MATCH_CMIX 0x6001033 +#define MASK_CMIX 0x600707f +#define MATCH_CMOV 0x6005033 +#define MASK_CMOV 0x600707f +#define MATCH_CMPEQ16 0x4c000077 +#define MASK_CMPEQ16 0xfe00707f +#define MATCH_CMPEQ8 0x4e000077 +#define MASK_CMPEQ8 0xfe00707f +#define MATCH_CPOP 0x60201013 +#define MASK_CPOP 0xfff0707f +#define MATCH_CPOPW 0x6020101b +#define MASK_CPOPW 0xfff0707f +#define MATCH_CRAS16 0x44000077 +#define MASK_CRAS16 0xfe00707f +#define MATCH_CRAS32 0x44002077 +#define MASK_CRAS32 0xfe00707f +#define MATCH_CRC32_B 0x61001013 +#define MASK_CRC32_B 0xfff0707f +#define MATCH_CRC32_D 0x61301013 +#define MASK_CRC32_D 0xfff0707f +#define MATCH_CRC32_H 0x61101013 +#define MASK_CRC32_H 0xfff0707f +#define MATCH_CRC32_W 0x61201013 +#define MASK_CRC32_W 0xfff0707f +#define MATCH_CRC32C_B 0x61801013 +#define MASK_CRC32C_B 0xfff0707f +#define MATCH_CRC32C_D 0x61b01013 +#define MASK_CRC32C_D 0xfff0707f +#define MATCH_CRC32C_H 0x61901013 +#define MASK_CRC32C_H 0xfff0707f +#define MATCH_CRC32C_W 0x61a01013 +#define MASK_CRC32C_W 0xfff0707f +#define MATCH_CRSA16 0x46000077 +#define MASK_CRSA16 0xfe00707f +#define MATCH_CRSA32 0x46002077 +#define MASK_CRSA32 0xfe00707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CTZ 0x60101013 +#define MASK_CTZ 0xfff0707f +#define MATCH_CTZW 0x6010101b +#define MASK_CTZW 0xfff0707f +#define MATCH_CZERO_EQZ 0xe005033 +#define MASK_CZERO_EQZ 0xfe00707f +#define MATCH_CZERO_NEZ 0xe007033 +#define MASK_CZERO_NEZ 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FADD_H 0x4000053 +#define MASK_FADD_H 0xfe00007f +#define MATCH_FADD_Q 0x6000053 +#define MASK_FADD_Q 0xfe00007f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCLASS_H 0xe4001053 +#define MASK_FCLASS_H 0xfff0707f +#define MATCH_FCLASS_Q 0xe6001053 +#define MASK_FCLASS_Q 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_D_H 0x42200053 +#define MASK_FCVT_D_H 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FCVT_D_Q 0x42300053 +#define MASK_FCVT_D_Q 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_H_D 0x44100053 +#define MASK_FCVT_H_D 0xfff0007f +#define MATCH_FCVT_H_L 0xd4200053 +#define MASK_FCVT_H_L 0xfff0007f +#define MATCH_FCVT_H_LU 0xd4300053 +#define MASK_FCVT_H_LU 0xfff0007f +#define MATCH_FCVT_H_Q 0x44300053 +#define MASK_FCVT_H_Q 0xfff0007f +#define MATCH_FCVT_H_S 0x44000053 +#define MASK_FCVT_H_S 0xfff0007f +#define MATCH_FCVT_H_W 0xd4000053 +#define MASK_FCVT_H_W 0xfff0007f +#define MATCH_FCVT_H_WU 0xd4100053 +#define MASK_FCVT_H_WU 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_L_H 0xc4200053 +#define MASK_FCVT_L_H 0xfff0007f +#define MATCH_FCVT_L_Q 0xc6200053 +#define MASK_FCVT_L_Q 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FCVT_LU_H 0xc4300053 +#define MASK_FCVT_LU_H 0xfff0007f +#define MATCH_FCVT_LU_Q 0xc6300053 +#define MASK_FCVT_LU_Q 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FCVT_Q_D 0x46100053 +#define MASK_FCVT_Q_D 0xfff0007f +#define MATCH_FCVT_Q_H 0x46200053 +#define MASK_FCVT_Q_H 0xfff0007f +#define MATCH_FCVT_Q_L 0xd6200053 +#define MASK_FCVT_Q_L 0xfff0007f +#define MATCH_FCVT_Q_LU 0xd6300053 +#define MASK_FCVT_Q_LU 0xfff0007f +#define MATCH_FCVT_Q_S 0x46000053 +#define MASK_FCVT_Q_S 0xfff0007f +#define MATCH_FCVT_Q_W 0xd6000053 +#define MASK_FCVT_Q_W 0xfff0007f +#define MATCH_FCVT_Q_WU 0xd6100053 +#define MASK_FCVT_Q_WU 0xfff0007f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_S_H 0x40200053 +#define MASK_FCVT_S_H 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FCVT_S_Q 0x40300053 +#define MASK_FCVT_S_Q 0xfff0007f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_W_H 0xc4000053 +#define MASK_FCVT_W_H 0xfff0007f +#define MATCH_FCVT_W_Q 0xc6000053 +#define MASK_FCVT_W_Q 0xfff0007f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_WU_H 0xc4100053 +#define MASK_FCVT_WU_H 0xfff0007f +#define MATCH_FCVT_WU_Q 0xc6100053 +#define MASK_FCVT_WU_Q 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FDIV_H 0x1c000053 +#define MASK_FDIV_H 0xfe00007f +#define MATCH_FDIV_Q 0x1e000053 +#define MASK_FDIV_Q 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FEQ_H 0xa4002053 +#define MASK_FEQ_H 0xfe00707f +#define MATCH_FEQ_Q 0xa6002053 +#define MASK_FEQ_Q 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLE_H 0xa4000053 +#define MASK_FLE_H 0xfe00707f +#define MATCH_FLE_Q 0xa6000053 +#define MASK_FLE_Q 0xfe00707f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLH 0x1007 +#define MASK_FLH 0x707f +#define MATCH_FLQ 0x4007 +#define MASK_FLQ 0x707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FLT_H 0xa4001053 +#define MASK_FLT_H 0xfe00707f +#define MATCH_FLT_Q 0xa6001053 +#define MASK_FLT_Q 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMADD_H 0x4000043 +#define MASK_FMADD_H 0x600007f +#define MATCH_FMADD_Q 0x6000043 +#define MASK_FMADD_Q 0x600007f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FMAX_H 0x2c001053 +#define MASK_FMAX_H 0xfe00707f +#define MATCH_FMAX_Q 0x2e001053 +#define MASK_FMAX_Q 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMIN_H 0x2c000053 +#define MASK_FMIN_H 0xfe00707f +#define MATCH_FMIN_Q 0x2e000053 +#define MASK_FMIN_Q 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FMSUB_H 0x4000047 +#define MASK_FMSUB_H 0x600007f +#define MATCH_FMSUB_Q 0x6000047 +#define MASK_FMSUB_Q 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FMUL_H 0x14000053 +#define MASK_FMUL_H 0xfe00007f +#define MATCH_FMUL_Q 0x16000053 +#define MASK_FMUL_Q 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FMV_H_X 0xf4000053 +#define MASK_FMV_H_X 0xfff0707f +#define MATCH_FMV_W_X 0xf0000053 +#define MASK_FMV_W_X 0xfff0707f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FMV_X_H 0xe4000053 +#define MASK_FMV_X_H 0xfff0707f +#define MATCH_FMV_X_W 0xe0000053 +#define MASK_FMV_X_W 0xfff0707f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_FNMADD_H 0x400004f +#define MASK_FNMADD_H 0x600007f +#define MATCH_FNMADD_Q 0x600004f +#define MASK_FNMADD_Q 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMSUB_H 0x400004b +#define MASK_FNMSUB_H 0x600007f +#define MATCH_FNMSUB_Q 0x600004b +#define MASK_FNMSUB_Q 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJ_H 0x24000053 +#define MASK_FSGNJ_H 0xfe00707f +#define MATCH_FSGNJ_Q 0x26000053 +#define MASK_FSGNJ_Q 0xfe00707f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJN_H 0x24001053 +#define MASK_FSGNJN_H 0xfe00707f +#define MATCH_FSGNJN_Q 0x26001053 +#define MASK_FSGNJN_Q 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FSGNJX_H 0x24002053 +#define MASK_FSGNJX_H 0xfe00707f +#define MATCH_FSGNJX_Q 0x26002053 +#define MASK_FSGNJX_Q 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FSH 0x1027 +#define MASK_FSH 0x707f +#define MATCH_FSL 0x4001033 +#define MASK_FSL 0x600707f +#define MATCH_FSLW 0x400103b +#define MASK_FSLW 0x600707f +#define MATCH_FSQ 0x4027 +#define MASK_FSQ 0x707f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FSQRT_H 0x5c000053 +#define MASK_FSQRT_H 0xfff0007f +#define MATCH_FSQRT_Q 0x5e000053 +#define MASK_FSQRT_Q 0xfff0007f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FSR 0x4005033 +#define MASK_FSR 0x600707f +#define MATCH_FSRI 0x4005013 +#define MASK_FSRI 0x400707f +#define MATCH_FSRIW 0x400501b +#define MASK_FSRIW 0x600707f +#define MATCH_FSRW 0x400503b +#define MASK_FSRW 0x600707f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FSUB_H 0xc000053 +#define MASK_FSUB_H 0xfe00007f +#define MATCH_FSUB_Q 0xe000053 +#define MASK_FSUB_Q 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_GORC 0x28005033 +#define MASK_GORC 0xfe00707f +#define MATCH_GORCI 0x28005013 +#define MASK_GORCI 0xfc00707f +#define MATCH_GORCIW 0x2800501b +#define MASK_GORCIW 0xfe00707f +#define MATCH_GORCW 0x2800503b +#define MASK_GORCW 0xfe00707f +#define MATCH_GREV 0x68005033 +#define MASK_GREV 0xfe00707f +#define MATCH_GREVI 0x68005013 +#define MASK_GREVI 0xfc00707f +#define MATCH_GREVIW 0x6800501b +#define MASK_GREVIW 0xfe00707f +#define MATCH_GREVW 0x6800503b +#define MASK_GREVW 0xfe00707f +#define MATCH_HFENCE_GVMA 0x62000073 +#define MASK_HFENCE_GVMA 0xfe007fff +#define MATCH_HFENCE_VVMA 0x22000073 +#define MASK_HFENCE_VVMA 0xfe007fff +#define MATCH_HINVAL_GVMA 0x66000073 +#define MASK_HINVAL_GVMA 0xfe007fff +#define MATCH_HINVAL_VVMA 0x26000073 +#define MASK_HINVAL_VVMA 0xfe007fff +#define MATCH_HLV_B 0x60004073 +#define MASK_HLV_B 0xfff0707f +#define MATCH_HLV_BU 0x60104073 +#define MASK_HLV_BU 0xfff0707f +#define MATCH_HLV_D 0x6c004073 +#define MASK_HLV_D 0xfff0707f +#define MATCH_HLV_H 0x64004073 +#define MASK_HLV_H 0xfff0707f +#define MATCH_HLV_HU 0x64104073 +#define MASK_HLV_HU 0xfff0707f +#define MATCH_HLV_W 0x68004073 +#define MASK_HLV_W 0xfff0707f +#define MATCH_HLV_WU 0x68104073 +#define MASK_HLV_WU 0xfff0707f +#define MATCH_HLVX_HU 0x64304073 +#define MASK_HLVX_HU 0xfff0707f +#define MATCH_HLVX_WU 0x68304073 +#define MASK_HLVX_WU 0xfff0707f +#define MATCH_HSV_B 0x62004073 +#define MASK_HSV_B 0xfe007fff +#define MATCH_HSV_D 0x6e004073 +#define MASK_HSV_D 0xfe007fff +#define MATCH_HSV_H 0x66004073 +#define MASK_HSV_H 0xfe007fff +#define MATCH_HSV_W 0x6a004073 +#define MASK_HSV_W 0xfe007fff +#define MATCH_INSB 0xac000077 +#define MASK_INSB 0xff80707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_KABS16 0xad100077 +#define MASK_KABS16 0xfff0707f +#define MATCH_KABS32 0xad200077 +#define MASK_KABS32 0xfff0707f +#define MATCH_KABS8 0xad000077 +#define MASK_KABS8 0xfff0707f +#define MATCH_KABSW 0xad400077 +#define MASK_KABSW 0xfff0707f +#define MATCH_KADD16 0x10000077 +#define MASK_KADD16 0xfe00707f +#define MATCH_KADD32 0x10002077 +#define MASK_KADD32 0xfe00707f +#define MATCH_KADD64 0x90001077 +#define MASK_KADD64 0xfe00707f +#define MATCH_KADD8 0x18000077 +#define MASK_KADD8 0xfe00707f +#define MATCH_KADDH 0x4001077 +#define MASK_KADDH 0xfe00707f +#define MATCH_KADDW 0x1077 +#define MASK_KADDW 0xfe00707f +#define MATCH_KCRAS16 0x14000077 +#define MASK_KCRAS16 0xfe00707f +#define MATCH_KCRAS32 0x14002077 +#define MASK_KCRAS32 0xfe00707f +#define MATCH_KCRSA16 0x16000077 +#define MASK_KCRSA16 0xfe00707f +#define MATCH_KCRSA32 0x16002077 +#define MASK_KCRSA32 0xfe00707f +#define MATCH_KDMABB 0xd2001077 +#define MASK_KDMABB 0xfe00707f +#define MATCH_KDMABB16 0xd8001077 +#define MASK_KDMABB16 0xfe00707f +#define MATCH_KDMABT 0xe2001077 +#define MASK_KDMABT 0xfe00707f +#define MATCH_KDMABT16 0xe8001077 +#define MASK_KDMABT16 0xfe00707f +#define MATCH_KDMATT 0xf2001077 +#define MASK_KDMATT 0xfe00707f +#define MATCH_KDMATT16 0xf8001077 +#define MASK_KDMATT16 0xfe00707f +#define MATCH_KDMBB 0xa001077 +#define MASK_KDMBB 0xfe00707f +#define MATCH_KDMBB16 0xda001077 +#define MASK_KDMBB16 0xfe00707f +#define MATCH_KDMBT 0x1a001077 +#define MASK_KDMBT 0xfe00707f +#define MATCH_KDMBT16 0xea001077 +#define MASK_KDMBT16 0xfe00707f +#define MATCH_KDMTT 0x2a001077 +#define MASK_KDMTT 0xfe00707f +#define MATCH_KDMTT16 0xfa001077 +#define MASK_KDMTT16 0xfe00707f +#define MATCH_KHM16 0x86000077 +#define MASK_KHM16 0xfe00707f +#define MATCH_KHM8 0x8e000077 +#define MASK_KHM8 0xfe00707f +#define MATCH_KHMBB 0xc001077 +#define MASK_KHMBB 0xfe00707f +#define MATCH_KHMBB16 0xdc001077 +#define MASK_KHMBB16 0xfe00707f +#define MATCH_KHMBT 0x1c001077 +#define MASK_KHMBT 0xfe00707f +#define MATCH_KHMBT16 0xec001077 +#define MASK_KHMBT16 0xfe00707f +#define MATCH_KHMTT 0x2c001077 +#define MASK_KHMTT 0xfe00707f +#define MATCH_KHMTT16 0xfc001077 +#define MASK_KHMTT16 0xfe00707f +#define MATCH_KHMX16 0x96000077 +#define MASK_KHMX16 0xfe00707f +#define MATCH_KHMX8 0x9e000077 +#define MASK_KHMX8 0xfe00707f +#define MATCH_KMABB 0x5a001077 +#define MASK_KMABB 0xfe00707f +#define MATCH_KMABB32 0x5a002077 +#define MASK_KMABB32 0xfe00707f +#define MATCH_KMABT 0x6a001077 +#define MASK_KMABT 0xfe00707f +#define MATCH_KMABT32 0x6a002077 +#define MASK_KMABT32 0xfe00707f +#define MATCH_KMADA 0x48001077 +#define MASK_KMADA 0xfe00707f +#define MATCH_KMADRS 0x6c001077 +#define MASK_KMADRS 0xfe00707f +#define MATCH_KMADRS32 0x6c002077 +#define MASK_KMADRS32 0xfe00707f +#define MATCH_KMADS 0x5c001077 +#define MASK_KMADS 0xfe00707f +#define MATCH_KMADS32 0x5c002077 +#define MASK_KMADS32 0xfe00707f +#define MATCH_KMAR64 0x94001077 +#define MASK_KMAR64 0xfe00707f +#define MATCH_KMATT 0x7a001077 +#define MASK_KMATT 0xfe00707f +#define MATCH_KMATT32 0x7a002077 +#define MASK_KMATT32 0xfe00707f +#define MATCH_KMAXDA 0x4a001077 +#define MASK_KMAXDA 0xfe00707f +#define MATCH_KMAXDA32 0x4a002077 +#define MASK_KMAXDA32 0xfe00707f +#define MATCH_KMAXDS 0x7c001077 +#define MASK_KMAXDS 0xfe00707f +#define MATCH_KMAXDS32 0x7c002077 +#define MASK_KMAXDS32 0xfe00707f +#define MATCH_KMDA 0x38001077 +#define MASK_KMDA 0xfe00707f +#define MATCH_KMDA32 0x38002077 +#define MASK_KMDA32 0xfe00707f +#define MATCH_KMMAC 0x60001077 +#define MASK_KMMAC 0xfe00707f +#define MATCH_KMMAC_U 0x70001077 +#define MASK_KMMAC_U 0xfe00707f +#define MATCH_KMMAWB 0x46001077 +#define MASK_KMMAWB 0xfe00707f +#define MATCH_KMMAWB2 0xce001077 +#define MASK_KMMAWB2 0xfe00707f +#define MATCH_KMMAWB2_U 0xde001077 +#define MASK_KMMAWB2_U 0xfe00707f +#define MATCH_KMMAWB_U 0x56001077 +#define MASK_KMMAWB_U 0xfe00707f +#define MATCH_KMMAWT 0x66001077 +#define MASK_KMMAWT 0xfe00707f +#define MATCH_KMMAWT2 0xee001077 +#define MASK_KMMAWT2 0xfe00707f +#define MATCH_KMMAWT2_U 0xfe001077 +#define MASK_KMMAWT2_U 0xfe00707f +#define MATCH_KMMAWT_U 0x76001077 +#define MASK_KMMAWT_U 0xfe00707f +#define MATCH_KMMSB 0x42001077 +#define MASK_KMMSB 0xfe00707f +#define MATCH_KMMSB_U 0x52001077 +#define MASK_KMMSB_U 0xfe00707f +#define MATCH_KMMWB2 0x8e001077 +#define MASK_KMMWB2 0xfe00707f +#define MATCH_KMMWB2_U 0x9e001077 +#define MASK_KMMWB2_U 0xfe00707f +#define MATCH_KMMWT2 0xae001077 +#define MASK_KMMWT2 0xfe00707f +#define MATCH_KMMWT2_U 0xbe001077 +#define MASK_KMMWT2_U 0xfe00707f +#define MATCH_KMSDA 0x4c001077 +#define MASK_KMSDA 0xfe00707f +#define MATCH_KMSDA32 0x4c002077 +#define MASK_KMSDA32 0xfe00707f +#define MATCH_KMSR64 0x96001077 +#define MASK_KMSR64 0xfe00707f +#define MATCH_KMSXDA 0x4e001077 +#define MASK_KMSXDA 0xfe00707f +#define MATCH_KMSXDA32 0x4e002077 +#define MASK_KMSXDA32 0xfe00707f +#define MATCH_KMXDA 0x3a001077 +#define MASK_KMXDA 0xfe00707f +#define MATCH_KMXDA32 0x3a002077 +#define MASK_KMXDA32 0xfe00707f +#define MATCH_KSLL16 0x64000077 +#define MASK_KSLL16 0xfe00707f +#define MATCH_KSLL32 0x64002077 +#define MASK_KSLL32 0xfe00707f +#define MATCH_KSLL8 0x6c000077 +#define MASK_KSLL8 0xfe00707f +#define MATCH_KSLLI16 0x75000077 +#define MASK_KSLLI16 0xff00707f +#define MATCH_KSLLI32 0x84002077 +#define MASK_KSLLI32 0xfe00707f +#define MATCH_KSLLI8 0x7c800077 +#define MASK_KSLLI8 0xff80707f +#define MATCH_KSLLIW 0x36001077 +#define MASK_KSLLIW 0xfe00707f +#define MATCH_KSLLW 0x26001077 +#define MASK_KSLLW 0xfe00707f +#define MATCH_KSLRA16 0x56000077 +#define MASK_KSLRA16 0xfe00707f +#define MATCH_KSLRA16_U 0x66000077 +#define MASK_KSLRA16_U 0xfe00707f +#define MATCH_KSLRA32 0x56002077 +#define MASK_KSLRA32 0xfe00707f +#define MATCH_KSLRA32_U 0x66002077 +#define MASK_KSLRA32_U 0xfe00707f +#define MATCH_KSLRA8 0x5e000077 +#define MASK_KSLRA8 0xfe00707f +#define MATCH_KSLRA8_U 0x6e000077 +#define MASK_KSLRA8_U 0xfe00707f +#define MATCH_KSLRAW 0x6e001077 +#define MASK_KSLRAW 0xfe00707f +#define MATCH_KSLRAW_U 0x7e001077 +#define MASK_KSLRAW_U 0xfe00707f +#define MATCH_KSTAS16 0xc4002077 +#define MASK_KSTAS16 0xfe00707f +#define MATCH_KSTAS32 0xc0002077 +#define MASK_KSTAS32 0xfe00707f +#define MATCH_KSTSA16 0xc6002077 +#define MASK_KSTSA16 0xfe00707f +#define MATCH_KSTSA32 0xc2002077 +#define MASK_KSTSA32 0xfe00707f +#define MATCH_KSUB16 0x12000077 +#define MASK_KSUB16 0xfe00707f +#define MATCH_KSUB32 0x12002077 +#define MASK_KSUB32 0xfe00707f +#define MATCH_KSUB64 0x92001077 +#define MASK_KSUB64 0xfe00707f +#define MATCH_KSUB8 0x1a000077 +#define MASK_KSUB8 0xfe00707f +#define MATCH_KSUBH 0x6001077 +#define MASK_KSUBH 0xfe00707f +#define MATCH_KSUBW 0x2001077 +#define MASK_KSUBW 0xfe00707f +#define MATCH_KWMMUL 0x62001077 +#define MASK_KWMMUL 0xfe00707f +#define MATCH_KWMMUL_U 0x72001077 +#define MASK_KWMMUL_U 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_MADDR32 0xc4001077 +#define MASK_MADDR32 0xfe00707f +#define MATCH_MAX 0xa006033 +#define MASK_MAX 0xfe00707f +#define MATCH_MAXU 0xa007033 +#define MASK_MAXU 0xfe00707f +#define MATCH_MIN 0xa004033 +#define MASK_MIN 0xfe00707f +#define MATCH_MINU 0xa005033 +#define MASK_MINU 0xfe00707f +#define MATCH_MNRET 0x70200073 +#define MASK_MNRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_MSUBR32 0xc6001077 +#define MASK_MSUBR32 0xfe00707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_MULR64 0xf0001077 +#define MASK_MULR64 0xfe00707f +#define MATCH_MULSR64 0xe0001077 +#define MASK_MULSR64 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ORN 0x40006033 +#define MASK_ORN 0xfe00707f +#define MATCH_PACK 0x8004033 +#define MASK_PACK 0xfe00707f +#define MATCH_PACKH 0x8007033 +#define MASK_PACKH 0xfe00707f +#define MATCH_PACKU 0x48004033 +#define MASK_PACKU 0xfe00707f +#define MATCH_PACKUW 0x4800403b +#define MASK_PACKUW 0xfe00707f +#define MATCH_PACKW 0x800403b +#define MASK_PACKW 0xfe00707f +#define MATCH_PAUSE 0x100000f +#define MASK_PAUSE 0xffffffff +#define MATCH_PBSAD 0xfc000077 +#define MASK_PBSAD 0xfe00707f +#define MATCH_PBSADA 0xfe000077 +#define MASK_PBSADA 0xfe00707f +#define MATCH_PKBB16 0xe001077 +#define MASK_PKBB16 0xfe00707f +#define MATCH_PKBT16 0x1e001077 +#define MASK_PKBT16 0xfe00707f +#define MATCH_PKBT32 0x1e002077 +#define MASK_PKBT32 0xfe00707f +#define MATCH_PKTB16 0x3e001077 +#define MASK_PKTB16 0xfe00707f +#define MATCH_PKTB32 0x3e002077 +#define MASK_PKTB32 0xfe00707f +#define MATCH_PKTT16 0x2e001077 +#define MASK_PKTT16 0xfe00707f +#define MATCH_PREFETCH_I 0x6013 +#define MASK_PREFETCH_I 0x1f07fff +#define MATCH_PREFETCH_R 0x106013 +#define MASK_PREFETCH_R 0x1f07fff +#define MATCH_PREFETCH_W 0x306013 +#define MASK_PREFETCH_W 0x1f07fff +#define MATCH_RADD16 0x77 +#define MASK_RADD16 0xfe00707f +#define MATCH_RADD32 0x2077 +#define MASK_RADD32 0xfe00707f +#define MATCH_RADD64 0x80001077 +#define MASK_RADD64 0xfe00707f +#define MATCH_RADD8 0x8000077 +#define MASK_RADD8 0xfe00707f +#define MATCH_RADDW 0x20001077 +#define MASK_RADDW 0xfe00707f +#define MATCH_RCRAS16 0x4000077 +#define MASK_RCRAS16 0xfe00707f +#define MATCH_RCRAS32 0x4002077 +#define MASK_RCRAS32 0xfe00707f +#define MATCH_RCRSA16 0x6000077 +#define MASK_RCRSA16 0xfe00707f +#define MATCH_RCRSA32 0x6002077 +#define MASK_RCRSA32 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_ROL 0x60001033 +#define MASK_ROL 0xfe00707f +#define MATCH_ROLW 0x6000103b +#define MASK_ROLW 0xfe00707f +#define MATCH_ROR 0x60005033 +#define MASK_ROR 0xfe00707f +#define MATCH_RORI 0x60005013 +#define MASK_RORI 0xfc00707f +#define MATCH_RORIW 0x6000501b +#define MASK_RORIW 0xfe00707f +#define MATCH_RORW 0x6000503b +#define MASK_RORW 0xfe00707f +#define MATCH_RSTAS16 0xb4002077 +#define MASK_RSTAS16 0xfe00707f +#define MATCH_RSTAS32 0xb0002077 +#define MASK_RSTAS32 0xfe00707f +#define MATCH_RSTSA16 0xb6002077 +#define MASK_RSTSA16 0xfe00707f +#define MATCH_RSTSA32 0xb2002077 +#define MASK_RSTSA32 0xfe00707f +#define MATCH_RSUB16 0x2000077 +#define MASK_RSUB16 0xfe00707f +#define MATCH_RSUB32 0x2002077 +#define MASK_RSUB32 0xfe00707f +#define MATCH_RSUB64 0x82001077 +#define MASK_RSUB64 0xfe00707f +#define MATCH_RSUB8 0xa000077 +#define MASK_RSUB8 0xfe00707f +#define MATCH_RSUBW 0x22001077 +#define MASK_RSUBW 0xfe00707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_SCLIP16 0x84000077 +#define MASK_SCLIP16 0xff00707f +#define MATCH_SCLIP32 0xe4000077 +#define MASK_SCLIP32 0xfe00707f +#define MATCH_SCLIP8 0x8c000077 +#define MASK_SCLIP8 0xff80707f +#define MATCH_SCMPLE16 0x1c000077 +#define MASK_SCMPLE16 0xfe00707f +#define MATCH_SCMPLE8 0x1e000077 +#define MASK_SCMPLE8 0xfe00707f +#define MATCH_SCMPLT16 0xc000077 +#define MASK_SCMPLT16 0xfe00707f +#define MATCH_SCMPLT8 0xe000077 +#define MASK_SCMPLT8 0xfe00707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_SEXT_B 0x60401013 +#define MASK_SEXT_B 0xfff0707f +#define MATCH_SEXT_H 0x60501013 +#define MASK_SEXT_H 0xfff0707f +#define MATCH_SFENCE_INVAL_IR 0x18100073 +#define MASK_SFENCE_INVAL_IR 0xffffffff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff +#define MATCH_SFENCE_W_INVAL 0x18000073 +#define MASK_SFENCE_W_INVAL 0xffffffff +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SH1ADD 0x20002033 +#define MASK_SH1ADD 0xfe00707f +#define MATCH_SH1ADD_UW 0x2000203b +#define MASK_SH1ADD_UW 0xfe00707f +#define MATCH_SH2ADD 0x20004033 +#define MASK_SH2ADD 0xfe00707f +#define MATCH_SH2ADD_UW 0x2000403b +#define MASK_SH2ADD_UW 0xfe00707f +#define MATCH_SH3ADD 0x20006033 +#define MASK_SH3ADD 0xfe00707f +#define MATCH_SH3ADD_UW 0x2000603b +#define MASK_SH3ADD_UW 0xfe00707f +#define MATCH_SHA256SIG0 0x10201013 +#define MASK_SHA256SIG0 0xfff0707f +#define MATCH_SHA256SIG1 0x10301013 +#define MASK_SHA256SIG1 0xfff0707f +#define MATCH_SHA256SUM0 0x10001013 +#define MASK_SHA256SUM0 0xfff0707f +#define MATCH_SHA256SUM1 0x10101013 +#define MASK_SHA256SUM1 0xfff0707f +#define MATCH_SHA512SIG0 0x10601013 +#define MASK_SHA512SIG0 0xfff0707f +#define MATCH_SHA512SIG0H 0x5c000033 +#define MASK_SHA512SIG0H 0xfe00707f +#define MATCH_SHA512SIG0L 0x54000033 +#define MASK_SHA512SIG0L 0xfe00707f +#define MATCH_SHA512SIG1 0x10701013 +#define MASK_SHA512SIG1 0xfff0707f +#define MATCH_SHA512SIG1H 0x5e000033 +#define MASK_SHA512SIG1H 0xfe00707f +#define MATCH_SHA512SIG1L 0x56000033 +#define MASK_SHA512SIG1L 0xfe00707f +#define MATCH_SHA512SUM0 0x10401013 +#define MASK_SHA512SUM0 0xfff0707f +#define MATCH_SHA512SUM0R 0x50000033 +#define MASK_SHA512SUM0R 0xfe00707f +#define MATCH_SHA512SUM1 0x10501013 +#define MASK_SHA512SUM1 0xfff0707f +#define MATCH_SHA512SUM1R 0x52000033 +#define MASK_SHA512SUM1R 0xfe00707f +#define MATCH_SHFL 0x8001033 +#define MASK_SHFL 0xfe00707f +#define MATCH_SHFLI 0x8001013 +#define MASK_SHFLI 0xfe00707f +#define MATCH_SHFLW 0x800103b +#define MASK_SHFLW 0xfe00707f +#define MATCH_SINVAL_VMA 0x16000073 +#define MASK_SINVAL_VMA 0xfe007fff +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLL16 0x54000077 +#define MASK_SLL16 0xfe00707f +#define MATCH_SLL32 0x54002077 +#define MASK_SLL32 0xfe00707f +#define MATCH_SLL8 0x5c000077 +#define MASK_SLL8 0xfe00707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLLI16 0x74000077 +#define MASK_SLLI16 0xff00707f +#define MATCH_SLLI32 0x74002077 +#define MASK_SLLI32 0xfe00707f +#define MATCH_SLLI8 0x7c000077 +#define MASK_SLLI8 0xff80707f +#define MATCH_SLLI_RV32 0x1013 +#define MASK_SLLI_RV32 0xfe00707f +#define MATCH_SLLI_UW 0x800101b +#define MASK_SLLI_UW 0xfc00707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SLO 0x20001033 +#define MASK_SLO 0xfe00707f +#define MATCH_SLOI 0x20001013 +#define MASK_SLOI 0xfc00707f +#define MATCH_SLOIW 0x2000101b +#define MASK_SLOIW 0xfe00707f +#define MATCH_SLOW 0x2000103b +#define MASK_SLOW 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_SM3P0 0x10801013 +#define MASK_SM3P0 0xfff0707f +#define MATCH_SM3P1 0x10901013 +#define MASK_SM3P1 0xfff0707f +#define MATCH_SM4ED 0x30000033 +#define MASK_SM4ED 0x3e00707f +#define MATCH_SM4KS 0x34000033 +#define MASK_SM4KS 0x3e00707f +#define MATCH_SMAL 0x5e001077 +#define MASK_SMAL 0xfe00707f +#define MATCH_SMALBB 0x88001077 +#define MASK_SMALBB 0xfe00707f +#define MATCH_SMALBT 0x98001077 +#define MASK_SMALBT 0xfe00707f +#define MATCH_SMALDA 0x8c001077 +#define MASK_SMALDA 0xfe00707f +#define MATCH_SMALDRS 0x9a001077 +#define MASK_SMALDRS 0xfe00707f +#define MATCH_SMALDS 0x8a001077 +#define MASK_SMALDS 0xfe00707f +#define MATCH_SMALTT 0xa8001077 +#define MASK_SMALTT 0xfe00707f +#define MATCH_SMALXDA 0x9c001077 +#define MASK_SMALXDA 0xfe00707f +#define MATCH_SMALXDS 0xaa001077 +#define MASK_SMALXDS 0xfe00707f +#define MATCH_SMAQA 0xc8000077 +#define MASK_SMAQA 0xfe00707f +#define MATCH_SMAQA_SU 0xca000077 +#define MASK_SMAQA_SU 0xfe00707f +#define MATCH_SMAR64 0x84001077 +#define MASK_SMAR64 0xfe00707f +#define MATCH_SMAX16 0x82000077 +#define MASK_SMAX16 0xfe00707f +#define MATCH_SMAX32 0x92002077 +#define MASK_SMAX32 0xfe00707f +#define MATCH_SMAX8 0x8a000077 +#define MASK_SMAX8 0xfe00707f +#define MATCH_SMBB16 0x8001077 +#define MASK_SMBB16 0xfe00707f +#define MATCH_SMBT16 0x18001077 +#define MASK_SMBT16 0xfe00707f +#define MATCH_SMBT32 0x18002077 +#define MASK_SMBT32 0xfe00707f +#define MATCH_SMDRS 0x68001077 +#define MASK_SMDRS 0xfe00707f +#define MATCH_SMDRS32 0x68002077 +#define MASK_SMDRS32 0xfe00707f +#define MATCH_SMDS 0x58001077 +#define MASK_SMDS 0xfe00707f +#define MATCH_SMDS32 0x58002077 +#define MASK_SMDS32 0xfe00707f +#define MATCH_SMIN16 0x80000077 +#define MASK_SMIN16 0xfe00707f +#define MATCH_SMIN32 0x90002077 +#define MASK_SMIN32 0xfe00707f +#define MATCH_SMIN8 0x88000077 +#define MASK_SMIN8 0xfe00707f +#define MATCH_SMMUL 0x40001077 +#define MASK_SMMUL 0xfe00707f +#define MATCH_SMMUL_U 0x50001077 +#define MASK_SMMUL_U 0xfe00707f +#define MATCH_SMMWB 0x44001077 +#define MASK_SMMWB 0xfe00707f +#define MATCH_SMMWB_U 0x54001077 +#define MASK_SMMWB_U 0xfe00707f +#define MATCH_SMMWT 0x64001077 +#define MASK_SMMWT 0xfe00707f +#define MATCH_SMMWT_U 0x74001077 +#define MASK_SMMWT_U 0xfe00707f +#define MATCH_SMSLDA 0xac001077 +#define MASK_SMSLDA 0xfe00707f +#define MATCH_SMSLXDA 0xbc001077 +#define MASK_SMSLXDA 0xfe00707f +#define MATCH_SMSR64 0x86001077 +#define MASK_SMSR64 0xfe00707f +#define MATCH_SMTT16 0x28001077 +#define MASK_SMTT16 0xfe00707f +#define MATCH_SMTT32 0x28002077 +#define MASK_SMTT32 0xfe00707f +#define MATCH_SMUL16 0xa0000077 +#define MASK_SMUL16 0xfe00707f +#define MATCH_SMUL8 0xa8000077 +#define MASK_SMUL8 0xfe00707f +#define MATCH_SMULX16 0xa2000077 +#define MASK_SMULX16 0xfe00707f +#define MATCH_SMULX8 0xaa000077 +#define MASK_SMULX8 0xfe00707f +#define MATCH_SMXDS 0x78001077 +#define MASK_SMXDS 0xfe00707f +#define MATCH_SMXDS32 0x78002077 +#define MASK_SMXDS32 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_SRA16 0x50000077 +#define MASK_SRA16 0xfe00707f +#define MATCH_SRA16_U 0x60000077 +#define MASK_SRA16_U 0xfe00707f +#define MATCH_SRA32 0x50002077 +#define MASK_SRA32 0xfe00707f +#define MATCH_SRA32_U 0x60002077 +#define MASK_SRA32_U 0xfe00707f +#define MATCH_SRA8 0x58000077 +#define MASK_SRA8 0xfe00707f +#define MATCH_SRA8_U 0x68000077 +#define MASK_SRA8_U 0xfe00707f +#define MATCH_SRA_U 0x24001077 +#define MASK_SRA_U 0xfe00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_SRAI16 0x70000077 +#define MASK_SRAI16 0xff00707f +#define MATCH_SRAI16_U 0x71000077 +#define MASK_SRAI16_U 0xff00707f +#define MATCH_SRAI32 0x70002077 +#define MASK_SRAI32 0xfe00707f +#define MATCH_SRAI32_U 0x80002077 +#define MASK_SRAI32_U 0xfe00707f +#define MATCH_SRAI8 0x78000077 +#define MASK_SRAI8 0xff80707f +#define MATCH_SRAI8_U 0x78800077 +#define MASK_SRAI8_U 0xff80707f +#define MATCH_SRAI_RV32 0x40005013 +#define MASK_SRAI_RV32 0xfe00707f +#define MATCH_SRAI_U 0xd4001077 +#define MASK_SRAI_U 0xfc00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_SRAIW_U 0x34001077 +#define MASK_SRAIW_U 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRL16 0x52000077 +#define MASK_SRL16 0xfe00707f +#define MATCH_SRL16_U 0x62000077 +#define MASK_SRL16_U 0xfe00707f +#define MATCH_SRL32 0x52002077 +#define MASK_SRL32 0xfe00707f +#define MATCH_SRL32_U 0x62002077 +#define MASK_SRL32_U 0xfe00707f +#define MATCH_SRL8 0x5a000077 +#define MASK_SRL8 0xfe00707f +#define MATCH_SRL8_U 0x6a000077 +#define MASK_SRL8_U 0xfe00707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRLI16 0x72000077 +#define MASK_SRLI16 0xff00707f +#define MATCH_SRLI16_U 0x73000077 +#define MASK_SRLI16_U 0xff00707f +#define MATCH_SRLI32 0x72002077 +#define MASK_SRLI32 0xfe00707f +#define MATCH_SRLI32_U 0x82002077 +#define MASK_SRLI32_U 0xfe00707f +#define MATCH_SRLI8 0x7a000077 +#define MASK_SRLI8 0xff80707f +#define MATCH_SRLI8_U 0x7a800077 +#define MASK_SRLI8_U 0xff80707f +#define MATCH_SRLI_RV32 0x5013 +#define MASK_SRLI_RV32 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRO 0x20005033 +#define MASK_SRO 0xfe00707f +#define MATCH_SROI 0x20005013 +#define MASK_SROI 0xfc00707f +#define MATCH_SROIW 0x2000501b +#define MASK_SROIW 0xfe00707f +#define MATCH_SROW 0x2000503b +#define MASK_SROW 0xfe00707f +#define MATCH_STAS16 0xf4002077 +#define MASK_STAS16 0xfe00707f +#define MATCH_STAS32 0xf0002077 +#define MASK_STAS32 0xfe00707f +#define MATCH_STSA16 0xf6002077 +#define MASK_STSA16 0xfe00707f +#define MATCH_STSA32 0xf2002077 +#define MASK_STSA32 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SUB16 0x42000077 +#define MASK_SUB16 0xfe00707f +#define MATCH_SUB32 0x42002077 +#define MASK_SUB32 0xfe00707f +#define MATCH_SUB64 0xc2001077 +#define MASK_SUB64 0xfe00707f +#define MATCH_SUB8 0x4a000077 +#define MASK_SUB8 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SUNPKD810 0xac800077 +#define MASK_SUNPKD810 0xfff0707f +#define MATCH_SUNPKD820 0xac900077 +#define MASK_SUNPKD820 0xfff0707f +#define MATCH_SUNPKD830 0xaca00077 +#define MASK_SUNPKD830 0xfff0707f +#define MATCH_SUNPKD831 0xacb00077 +#define MASK_SUNPKD831 0xfff0707f +#define MATCH_SUNPKD832 0xad300077 +#define MASK_SUNPKD832 0xfff0707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_UCLIP16 0x85000077 +#define MASK_UCLIP16 0xff00707f +#define MATCH_UCLIP32 0xf4000077 +#define MASK_UCLIP32 0xfe00707f +#define MATCH_UCLIP8 0x8d000077 +#define MASK_UCLIP8 0xff80707f +#define MATCH_UCMPLE16 0x3c000077 +#define MASK_UCMPLE16 0xfe00707f +#define MATCH_UCMPLE8 0x3e000077 +#define MASK_UCMPLE8 0xfe00707f +#define MATCH_UCMPLT16 0x2c000077 +#define MASK_UCMPLT16 0xfe00707f +#define MATCH_UCMPLT8 0x2e000077 +#define MASK_UCMPLT8 0xfe00707f +#define MATCH_UKADD16 0x30000077 +#define MASK_UKADD16 0xfe00707f +#define MATCH_UKADD32 0x30002077 +#define MASK_UKADD32 0xfe00707f +#define MATCH_UKADD64 0xb0001077 +#define MASK_UKADD64 0xfe00707f +#define MATCH_UKADD8 0x38000077 +#define MASK_UKADD8 0xfe00707f +#define MATCH_UKADDH 0x14001077 +#define MASK_UKADDH 0xfe00707f +#define MATCH_UKADDW 0x10001077 +#define MASK_UKADDW 0xfe00707f +#define MATCH_UKCRAS16 0x34000077 +#define MASK_UKCRAS16 0xfe00707f +#define MATCH_UKCRAS32 0x34002077 +#define MASK_UKCRAS32 0xfe00707f +#define MATCH_UKCRSA16 0x36000077 +#define MASK_UKCRSA16 0xfe00707f +#define MATCH_UKCRSA32 0x36002077 +#define MASK_UKCRSA32 0xfe00707f +#define MATCH_UKMAR64 0xb4001077 +#define MASK_UKMAR64 0xfe00707f +#define MATCH_UKMSR64 0xb6001077 +#define MASK_UKMSR64 0xfe00707f +#define MATCH_UKSTAS16 0xe4002077 +#define MASK_UKSTAS16 0xfe00707f +#define MATCH_UKSTAS32 0xe0002077 +#define MASK_UKSTAS32 0xfe00707f +#define MATCH_UKSTSA16 0xe6002077 +#define MASK_UKSTSA16 0xfe00707f +#define MATCH_UKSTSA32 0xe2002077 +#define MASK_UKSTSA32 0xfe00707f +#define MATCH_UKSUB16 0x32000077 +#define MASK_UKSUB16 0xfe00707f +#define MATCH_UKSUB32 0x32002077 +#define MASK_UKSUB32 0xfe00707f +#define MATCH_UKSUB64 0xb2001077 +#define MASK_UKSUB64 0xfe00707f +#define MATCH_UKSUB8 0x3a000077 +#define MASK_UKSUB8 0xfe00707f +#define MATCH_UKSUBH 0x16001077 +#define MASK_UKSUBH 0xfe00707f +#define MATCH_UKSUBW 0x12001077 +#define MASK_UKSUBW 0xfe00707f +#define MATCH_UMAQA 0xcc000077 +#define MASK_UMAQA 0xfe00707f +#define MATCH_UMAR64 0xa4001077 +#define MASK_UMAR64 0xfe00707f +#define MATCH_UMAX16 0x92000077 +#define MASK_UMAX16 0xfe00707f +#define MATCH_UMAX32 0xa2002077 +#define MASK_UMAX32 0xfe00707f +#define MATCH_UMAX8 0x9a000077 +#define MASK_UMAX8 0xfe00707f +#define MATCH_UMIN16 0x90000077 +#define MASK_UMIN16 0xfe00707f +#define MATCH_UMIN32 0xa0002077 +#define MASK_UMIN32 0xfe00707f +#define MATCH_UMIN8 0x98000077 +#define MASK_UMIN8 0xfe00707f +#define MATCH_UMSR64 0xa6001077 +#define MASK_UMSR64 0xfe00707f +#define MATCH_UMUL16 0xb0000077 +#define MASK_UMUL16 0xfe00707f +#define MATCH_UMUL8 0xb8000077 +#define MASK_UMUL8 0xfe00707f +#define MATCH_UMULX16 0xb2000077 +#define MASK_UMULX16 0xfe00707f +#define MATCH_UMULX8 0xba000077 +#define MASK_UMULX8 0xfe00707f +#define MATCH_UNSHFL 0x8005033 +#define MASK_UNSHFL 0xfe00707f +#define MATCH_UNSHFLI 0x8005013 +#define MASK_UNSHFLI 0xfe00707f +#define MATCH_UNSHFLW 0x800503b +#define MASK_UNSHFLW 0xfe00707f +#define MATCH_URADD16 0x20000077 +#define MASK_URADD16 0xfe00707f +#define MATCH_URADD32 0x20002077 +#define MASK_URADD32 0xfe00707f +#define MATCH_URADD64 0xa0001077 +#define MASK_URADD64 0xfe00707f +#define MATCH_URADD8 0x28000077 +#define MASK_URADD8 0xfe00707f +#define MATCH_URADDW 0x30001077 +#define MASK_URADDW 0xfe00707f +#define MATCH_URCRAS16 0x24000077 +#define MASK_URCRAS16 0xfe00707f +#define MATCH_URCRAS32 0x24002077 +#define MASK_URCRAS32 0xfe00707f +#define MATCH_URCRSA16 0x26000077 +#define MASK_URCRSA16 0xfe00707f +#define MATCH_URCRSA32 0x26002077 +#define MASK_URCRSA32 0xfe00707f +#define MATCH_URSTAS16 0xd4002077 +#define MASK_URSTAS16 0xfe00707f +#define MATCH_URSTAS32 0xd0002077 +#define MASK_URSTAS32 0xfe00707f +#define MATCH_URSTSA16 0xd6002077 +#define MASK_URSTSA16 0xfe00707f +#define MATCH_URSTSA32 0xd2002077 +#define MASK_URSTSA32 0xfe00707f +#define MATCH_URSUB16 0x22000077 +#define MASK_URSUB16 0xfe00707f +#define MATCH_URSUB32 0x22002077 +#define MASK_URSUB32 0xfe00707f +#define MATCH_URSUB64 0xa2001077 +#define MASK_URSUB64 0xfe00707f +#define MATCH_URSUB8 0x2a000077 +#define MASK_URSUB8 0xfe00707f +#define MATCH_URSUBW 0x32001077 +#define MASK_URSUBW 0xfe00707f +#define MATCH_VAADD_VV 0x24002057 +#define MASK_VAADD_VV 0xfc00707f +#define MATCH_VAADD_VX 0x24006057 +#define MASK_VAADD_VX 0xfc00707f +#define MATCH_VAADDU_VV 0x20002057 +#define MASK_VAADDU_VV 0xfc00707f +#define MATCH_VAADDU_VX 0x20006057 +#define MASK_VAADDU_VX 0xfc00707f +#define MATCH_VADC_VIM 0x40003057 +#define MASK_VADC_VIM 0xfe00707f +#define MATCH_VADC_VVM 0x40000057 +#define MASK_VADC_VVM 0xfe00707f +#define MATCH_VADC_VXM 0x40004057 +#define MASK_VADC_VXM 0xfe00707f +#define MATCH_VADD_VI 0x3057 +#define MASK_VADD_VI 0xfc00707f +#define MATCH_VADD_VV 0x57 +#define MASK_VADD_VV 0xfc00707f +#define MATCH_VADD_VX 0x4057 +#define MASK_VADD_VX 0xfc00707f +#define MATCH_VAMOADDEI16_V 0x502f +#define MASK_VAMOADDEI16_V 0xf800707f +#define MATCH_VAMOADDEI32_V 0x602f +#define MASK_VAMOADDEI32_V 0xf800707f +#define MATCH_VAMOADDEI64_V 0x702f +#define MASK_VAMOADDEI64_V 0xf800707f +#define MATCH_VAMOADDEI8_V 0x2f +#define MASK_VAMOADDEI8_V 0xf800707f +#define MATCH_VAMOANDEI16_V 0x6000502f +#define MASK_VAMOANDEI16_V 0xf800707f +#define MATCH_VAMOANDEI32_V 0x6000602f +#define MASK_VAMOANDEI32_V 0xf800707f +#define MATCH_VAMOANDEI64_V 0x6000702f +#define MASK_VAMOANDEI64_V 0xf800707f +#define MATCH_VAMOANDEI8_V 0x6000002f +#define MASK_VAMOANDEI8_V 0xf800707f +#define MATCH_VAMOMAXEI16_V 0xa000502f +#define MASK_VAMOMAXEI16_V 0xf800707f +#define MATCH_VAMOMAXEI32_V 0xa000602f +#define MASK_VAMOMAXEI32_V 0xf800707f +#define MATCH_VAMOMAXEI64_V 0xa000702f +#define MASK_VAMOMAXEI64_V 0xf800707f +#define MATCH_VAMOMAXEI8_V 0xa000002f +#define MASK_VAMOMAXEI8_V 0xf800707f +#define MATCH_VAMOMAXUEI16_V 0xe000502f +#define MASK_VAMOMAXUEI16_V 0xf800707f +#define MATCH_VAMOMAXUEI32_V 0xe000602f +#define MASK_VAMOMAXUEI32_V 0xf800707f +#define MATCH_VAMOMAXUEI64_V 0xe000702f +#define MASK_VAMOMAXUEI64_V 0xf800707f +#define MATCH_VAMOMAXUEI8_V 0xe000002f +#define MASK_VAMOMAXUEI8_V 0xf800707f +#define MATCH_VAMOMINEI16_V 0x8000502f +#define MASK_VAMOMINEI16_V 0xf800707f +#define MATCH_VAMOMINEI32_V 0x8000602f +#define MASK_VAMOMINEI32_V 0xf800707f +#define MATCH_VAMOMINEI64_V 0x8000702f +#define MASK_VAMOMINEI64_V 0xf800707f +#define MATCH_VAMOMINEI8_V 0x8000002f +#define MASK_VAMOMINEI8_V 0xf800707f +#define MATCH_VAMOMINUEI16_V 0xc000502f +#define MASK_VAMOMINUEI16_V 0xf800707f +#define MATCH_VAMOMINUEI32_V 0xc000602f +#define MASK_VAMOMINUEI32_V 0xf800707f +#define MATCH_VAMOMINUEI64_V 0xc000702f +#define MASK_VAMOMINUEI64_V 0xf800707f +#define MATCH_VAMOMINUEI8_V 0xc000002f +#define MASK_VAMOMINUEI8_V 0xf800707f +#define MATCH_VAMOOREI16_V 0x4000502f +#define MASK_VAMOOREI16_V 0xf800707f +#define MATCH_VAMOOREI32_V 0x4000602f +#define MASK_VAMOOREI32_V 0xf800707f +#define MATCH_VAMOOREI64_V 0x4000702f +#define MASK_VAMOOREI64_V 0xf800707f +#define MATCH_VAMOOREI8_V 0x4000002f +#define MASK_VAMOOREI8_V 0xf800707f +#define MATCH_VAMOSWAPEI16_V 0x800502f +#define MASK_VAMOSWAPEI16_V 0xf800707f +#define MATCH_VAMOSWAPEI32_V 0x800602f +#define MASK_VAMOSWAPEI32_V 0xf800707f +#define MATCH_VAMOSWAPEI64_V 0x800702f +#define MASK_VAMOSWAPEI64_V 0xf800707f +#define MATCH_VAMOSWAPEI8_V 0x800002f +#define MASK_VAMOSWAPEI8_V 0xf800707f +#define MATCH_VAMOXOREI16_V 0x2000502f +#define MASK_VAMOXOREI16_V 0xf800707f +#define MATCH_VAMOXOREI32_V 0x2000602f +#define MASK_VAMOXOREI32_V 0xf800707f +#define MATCH_VAMOXOREI64_V 0x2000702f +#define MASK_VAMOXOREI64_V 0xf800707f +#define MATCH_VAMOXOREI8_V 0x2000002f +#define MASK_VAMOXOREI8_V 0xf800707f +#define MATCH_VAND_VI 0x24003057 +#define MASK_VAND_VI 0xfc00707f +#define MATCH_VAND_VV 0x24000057 +#define MASK_VAND_VV 0xfc00707f +#define MATCH_VAND_VX 0x24004057 +#define MASK_VAND_VX 0xfc00707f +#define MATCH_VASUB_VV 0x2c002057 +#define MASK_VASUB_VV 0xfc00707f +#define MATCH_VASUB_VX 0x2c006057 +#define MASK_VASUB_VX 0xfc00707f +#define MATCH_VASUBU_VV 0x28002057 +#define MASK_VASUBU_VV 0xfc00707f +#define MATCH_VASUBU_VX 0x28006057 +#define MASK_VASUBU_VX 0xfc00707f +#define MATCH_VCOMPRESS_VM 0x5e002057 +#define MASK_VCOMPRESS_VM 0xfe00707f +#define MATCH_VCPOP_M 0x40082057 +#define MASK_VCPOP_M 0xfc0ff07f +#define MATCH_VDIV_VV 0x84002057 +#define MASK_VDIV_VV 0xfc00707f +#define MATCH_VDIV_VX 0x84006057 +#define MASK_VDIV_VX 0xfc00707f +#define MATCH_VDIVU_VV 0x80002057 +#define MASK_VDIVU_VV 0xfc00707f +#define MATCH_VDIVU_VX 0x80006057 +#define MASK_VDIVU_VX 0xfc00707f +#define MATCH_VFADD_VF 0x5057 +#define MASK_VFADD_VF 0xfc00707f +#define MATCH_VFADD_VV 0x1057 +#define MASK_VFADD_VV 0xfc00707f +#define MATCH_VFCLASS_V 0x4c081057 +#define MASK_VFCLASS_V 0xfc0ff07f +#define MATCH_VFCVT_F_X_V 0x48019057 +#define MASK_VFCVT_F_X_V 0xfc0ff07f +#define MATCH_VFCVT_F_XU_V 0x48011057 +#define MASK_VFCVT_F_XU_V 0xfc0ff07f +#define MATCH_VFCVT_RTZ_X_F_V 0x48039057 +#define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f +#define MATCH_VFCVT_RTZ_XU_F_V 0x48031057 +#define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f +#define MATCH_VFCVT_X_F_V 0x48009057 +#define MASK_VFCVT_X_F_V 0xfc0ff07f +#define MATCH_VFCVT_XU_F_V 0x48001057 +#define MASK_VFCVT_XU_F_V 0xfc0ff07f +#define MATCH_VFDIV_VF 0x80005057 +#define MASK_VFDIV_VF 0xfc00707f +#define MATCH_VFDIV_VV 0x80001057 +#define MASK_VFDIV_VV 0xfc00707f +#define MATCH_VFIRST_M 0x4008a057 +#define MASK_VFIRST_M 0xfc0ff07f +#define MATCH_VFMACC_VF 0xb0005057 +#define MASK_VFMACC_VF 0xfc00707f +#define MATCH_VFMACC_VV 0xb0001057 +#define MASK_VFMACC_VV 0xfc00707f +#define MATCH_VFMADD_VF 0xa0005057 +#define MASK_VFMADD_VF 0xfc00707f +#define MATCH_VFMADD_VV 0xa0001057 +#define MASK_VFMADD_VV 0xfc00707f +#define MATCH_VFMAX_VF 0x18005057 +#define MASK_VFMAX_VF 0xfc00707f +#define MATCH_VFMAX_VV 0x18001057 +#define MASK_VFMAX_VV 0xfc00707f +#define MATCH_VFMERGE_VFM 0x5c005057 +#define MASK_VFMERGE_VFM 0xfe00707f +#define MATCH_VFMIN_VF 0x10005057 +#define MASK_VFMIN_VF 0xfc00707f +#define MATCH_VFMIN_VV 0x10001057 +#define MASK_VFMIN_VV 0xfc00707f +#define MATCH_VFMSAC_VF 0xb8005057 +#define MASK_VFMSAC_VF 0xfc00707f +#define MATCH_VFMSAC_VV 0xb8001057 +#define MASK_VFMSAC_VV 0xfc00707f +#define MATCH_VFMSUB_VF 0xa8005057 +#define MASK_VFMSUB_VF 0xfc00707f +#define MATCH_VFMSUB_VV 0xa8001057 +#define MASK_VFMSUB_VV 0xfc00707f +#define MATCH_VFMUL_VF 0x90005057 +#define MASK_VFMUL_VF 0xfc00707f +#define MATCH_VFMUL_VV 0x90001057 +#define MASK_VFMUL_VV 0xfc00707f +#define MATCH_VFMV_F_S 0x42001057 +#define MASK_VFMV_F_S 0xfe0ff07f +#define MATCH_VFMV_S_F 0x42005057 +#define MASK_VFMV_S_F 0xfff0707f +#define MATCH_VFMV_V_F 0x5e005057 +#define MASK_VFMV_V_F 0xfff0707f +#define MATCH_VFNCVT_F_F_W 0x480a1057 +#define MASK_VFNCVT_F_F_W 0xfc0ff07f +#define MATCH_VFNCVT_F_X_W 0x48099057 +#define MASK_VFNCVT_F_X_W 0xfc0ff07f +#define MATCH_VFNCVT_F_XU_W 0x48091057 +#define MASK_VFNCVT_F_XU_W 0xfc0ff07f +#define MATCH_VFNCVT_ROD_F_F_W 0x480a9057 +#define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f +#define MATCH_VFNCVT_RTZ_X_F_W 0x480b9057 +#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f +#define MATCH_VFNCVT_RTZ_XU_F_W 0x480b1057 +#define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f +#define MATCH_VFNCVT_X_F_W 0x48089057 +#define MASK_VFNCVT_X_F_W 0xfc0ff07f +#define MATCH_VFNCVT_XU_F_W 0x48081057 +#define MASK_VFNCVT_XU_F_W 0xfc0ff07f +#define MATCH_VFNMACC_VF 0xb4005057 +#define MASK_VFNMACC_VF 0xfc00707f +#define MATCH_VFNMACC_VV 0xb4001057 +#define MASK_VFNMACC_VV 0xfc00707f +#define MATCH_VFNMADD_VF 0xa4005057 +#define MASK_VFNMADD_VF 0xfc00707f +#define MATCH_VFNMADD_VV 0xa4001057 +#define MASK_VFNMADD_VV 0xfc00707f +#define MATCH_VFNMSAC_VF 0xbc005057 +#define MASK_VFNMSAC_VF 0xfc00707f +#define MATCH_VFNMSAC_VV 0xbc001057 +#define MASK_VFNMSAC_VV 0xfc00707f +#define MATCH_VFNMSUB_VF 0xac005057 +#define MASK_VFNMSUB_VF 0xfc00707f +#define MATCH_VFNMSUB_VV 0xac001057 +#define MASK_VFNMSUB_VV 0xfc00707f +#define MATCH_VFRDIV_VF 0x84005057 +#define MASK_VFRDIV_VF 0xfc00707f +#define MATCH_VFREC7_V 0x4c029057 +#define MASK_VFREC7_V 0xfc0ff07f +#define MATCH_VFREDMAX_VS 0x1c001057 +#define MASK_VFREDMAX_VS 0xfc00707f +#define MATCH_VFREDMIN_VS 0x14001057 +#define MASK_VFREDMIN_VS 0xfc00707f +#define MATCH_VFREDOSUM_VS 0xc001057 +#define MASK_VFREDOSUM_VS 0xfc00707f +#define MATCH_VFREDUSUM_VS 0x4001057 +#define MASK_VFREDUSUM_VS 0xfc00707f +#define MATCH_VFRSQRT7_V 0x4c021057 +#define MASK_VFRSQRT7_V 0xfc0ff07f +#define MATCH_VFRSUB_VF 0x9c005057 +#define MASK_VFRSUB_VF 0xfc00707f +#define MATCH_VFSGNJ_VF 0x20005057 +#define MASK_VFSGNJ_VF 0xfc00707f +#define MATCH_VFSGNJ_VV 0x20001057 +#define MASK_VFSGNJ_VV 0xfc00707f +#define MATCH_VFSGNJN_VF 0x24005057 +#define MASK_VFSGNJN_VF 0xfc00707f +#define MATCH_VFSGNJN_VV 0x24001057 +#define MASK_VFSGNJN_VV 0xfc00707f +#define MATCH_VFSGNJX_VF 0x28005057 +#define MASK_VFSGNJX_VF 0xfc00707f +#define MATCH_VFSGNJX_VV 0x28001057 +#define MASK_VFSGNJX_VV 0xfc00707f +#define MATCH_VFSLIDE1DOWN_VF 0x3c005057 +#define MASK_VFSLIDE1DOWN_VF 0xfc00707f +#define MATCH_VFSLIDE1UP_VF 0x38005057 +#define MASK_VFSLIDE1UP_VF 0xfc00707f +#define MATCH_VFSQRT_V 0x4c001057 +#define MASK_VFSQRT_V 0xfc0ff07f +#define MATCH_VFSUB_VF 0x8005057 +#define MASK_VFSUB_VF 0xfc00707f +#define MATCH_VFSUB_VV 0x8001057 +#define MASK_VFSUB_VV 0xfc00707f +#define MATCH_VFWADD_VF 0xc0005057 +#define MASK_VFWADD_VF 0xfc00707f +#define MATCH_VFWADD_VV 0xc0001057 +#define MASK_VFWADD_VV 0xfc00707f +#define MATCH_VFWADD_WF 0xd0005057 +#define MASK_VFWADD_WF 0xfc00707f +#define MATCH_VFWADD_WV 0xd0001057 +#define MASK_VFWADD_WV 0xfc00707f +#define MATCH_VFWCVT_F_F_V 0x48061057 +#define MASK_VFWCVT_F_F_V 0xfc0ff07f +#define MATCH_VFWCVT_F_X_V 0x48059057 +#define MASK_VFWCVT_F_X_V 0xfc0ff07f +#define MATCH_VFWCVT_F_XU_V 0x48051057 +#define MASK_VFWCVT_F_XU_V 0xfc0ff07f +#define MATCH_VFWCVT_RTZ_X_F_V 0x48079057 +#define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f +#define MATCH_VFWCVT_RTZ_XU_F_V 0x48071057 +#define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f +#define MATCH_VFWCVT_X_F_V 0x48049057 +#define MASK_VFWCVT_X_F_V 0xfc0ff07f +#define MATCH_VFWCVT_XU_F_V 0x48041057 +#define MASK_VFWCVT_XU_F_V 0xfc0ff07f +#define MATCH_VFWMACC_VF 0xf0005057 +#define MASK_VFWMACC_VF 0xfc00707f +#define MATCH_VFWMACC_VV 0xf0001057 +#define MASK_VFWMACC_VV 0xfc00707f +#define MATCH_VFWMSAC_VF 0xf8005057 +#define MASK_VFWMSAC_VF 0xfc00707f +#define MATCH_VFWMSAC_VV 0xf8001057 +#define MASK_VFWMSAC_VV 0xfc00707f +#define MATCH_VFWMUL_VF 0xe0005057 +#define MASK_VFWMUL_VF 0xfc00707f +#define MATCH_VFWMUL_VV 0xe0001057 +#define MASK_VFWMUL_VV 0xfc00707f +#define MATCH_VFWNMACC_VF 0xf4005057 +#define MASK_VFWNMACC_VF 0xfc00707f +#define MATCH_VFWNMACC_VV 0xf4001057 +#define MASK_VFWNMACC_VV 0xfc00707f +#define MATCH_VFWNMSAC_VF 0xfc005057 +#define MASK_VFWNMSAC_VF 0xfc00707f +#define MATCH_VFWNMSAC_VV 0xfc001057 +#define MASK_VFWNMSAC_VV 0xfc00707f +#define MATCH_VFWREDOSUM_VS 0xcc001057 +#define MASK_VFWREDOSUM_VS 0xfc00707f +#define MATCH_VFWREDUSUM_VS 0xc4001057 +#define MASK_VFWREDUSUM_VS 0xfc00707f +#define MATCH_VFWSUB_VF 0xc8005057 +#define MASK_VFWSUB_VF 0xfc00707f +#define MATCH_VFWSUB_VV 0xc8001057 +#define MASK_VFWSUB_VV 0xfc00707f +#define MATCH_VFWSUB_WF 0xd8005057 +#define MASK_VFWSUB_WF 0xfc00707f +#define MATCH_VFWSUB_WV 0xd8001057 +#define MASK_VFWSUB_WV 0xfc00707f +#define MATCH_VID_V 0x5008a057 +#define MASK_VID_V 0xfdfff07f +#define MATCH_VIOTA_M 0x50082057 +#define MASK_VIOTA_M 0xfc0ff07f +#define MATCH_VL1RE16_V 0x2805007 +#define MASK_VL1RE16_V 0xfff0707f +#define MATCH_VL1RE32_V 0x2806007 +#define MASK_VL1RE32_V 0xfff0707f +#define MATCH_VL1RE64_V 0x2807007 +#define MASK_VL1RE64_V 0xfff0707f +#define MATCH_VL1RE8_V 0x2800007 +#define MASK_VL1RE8_V 0xfff0707f +#define MATCH_VL2RE16_V 0x22805007 +#define MASK_VL2RE16_V 0xfff0707f +#define MATCH_VL2RE32_V 0x22806007 +#define MASK_VL2RE32_V 0xfff0707f +#define MATCH_VL2RE64_V 0x22807007 +#define MASK_VL2RE64_V 0xfff0707f +#define MATCH_VL2RE8_V 0x22800007 +#define MASK_VL2RE8_V 0xfff0707f +#define MATCH_VL4RE16_V 0x62805007 +#define MASK_VL4RE16_V 0xfff0707f +#define MATCH_VL4RE32_V 0x62806007 +#define MASK_VL4RE32_V 0xfff0707f +#define MATCH_VL4RE64_V 0x62807007 +#define MASK_VL4RE64_V 0xfff0707f +#define MATCH_VL4RE8_V 0x62800007 +#define MASK_VL4RE8_V 0xfff0707f +#define MATCH_VL8RE16_V 0xe2805007 +#define MASK_VL8RE16_V 0xfff0707f +#define MATCH_VL8RE32_V 0xe2806007 +#define MASK_VL8RE32_V 0xfff0707f +#define MATCH_VL8RE64_V 0xe2807007 +#define MASK_VL8RE64_V 0xfff0707f +#define MATCH_VL8RE8_V 0xe2800007 +#define MASK_VL8RE8_V 0xfff0707f +#define MATCH_VLE1024_V 0x10007007 +#define MASK_VLE1024_V 0x1df0707f +#define MATCH_VLE1024FF_V 0x11007007 +#define MASK_VLE1024FF_V 0x1df0707f +#define MATCH_VLE128_V 0x10000007 +#define MASK_VLE128_V 0x1df0707f +#define MATCH_VLE128FF_V 0x11000007 +#define MASK_VLE128FF_V 0x1df0707f +#define MATCH_VLE16_V 0x5007 +#define MASK_VLE16_V 0x1df0707f +#define MATCH_VLE16FF_V 0x1005007 +#define MASK_VLE16FF_V 0x1df0707f +#define MATCH_VLE256_V 0x10005007 +#define MASK_VLE256_V 0x1df0707f +#define MATCH_VLE256FF_V 0x11005007 +#define MASK_VLE256FF_V 0x1df0707f +#define MATCH_VLE32_V 0x6007 +#define MASK_VLE32_V 0x1df0707f +#define MATCH_VLE32FF_V 0x1006007 +#define MASK_VLE32FF_V 0x1df0707f +#define MATCH_VLE512_V 0x10006007 +#define MASK_VLE512_V 0x1df0707f +#define MATCH_VLE512FF_V 0x11006007 +#define MASK_VLE512FF_V 0x1df0707f +#define MATCH_VLE64_V 0x7007 +#define MASK_VLE64_V 0x1df0707f +#define MATCH_VLE64FF_V 0x1007007 +#define MASK_VLE64FF_V 0x1df0707f +#define MATCH_VLE8_V 0x7 +#define MASK_VLE8_V 0x1df0707f +#define MATCH_VLE8FF_V 0x1000007 +#define MASK_VLE8FF_V 0x1df0707f +#define MATCH_VLM_V 0x2b00007 +#define MASK_VLM_V 0xfff0707f +#define MATCH_VLOXEI1024_V 0x1c007007 +#define MASK_VLOXEI1024_V 0x1c00707f +#define MATCH_VLOXEI128_V 0x1c000007 +#define MASK_VLOXEI128_V 0x1c00707f +#define MATCH_VLOXEI16_V 0xc005007 +#define MASK_VLOXEI16_V 0x1c00707f +#define MATCH_VLOXEI256_V 0x1c005007 +#define MASK_VLOXEI256_V 0x1c00707f +#define MATCH_VLOXEI32_V 0xc006007 +#define MASK_VLOXEI32_V 0x1c00707f +#define MATCH_VLOXEI512_V 0x1c006007 +#define MASK_VLOXEI512_V 0x1c00707f +#define MATCH_VLOXEI64_V 0xc007007 +#define MASK_VLOXEI64_V 0x1c00707f +#define MATCH_VLOXEI8_V 0xc000007 +#define MASK_VLOXEI8_V 0x1c00707f +#define MATCH_VLSE1024_V 0x18007007 +#define MASK_VLSE1024_V 0x1c00707f +#define MATCH_VLSE128_V 0x18000007 +#define MASK_VLSE128_V 0x1c00707f +#define MATCH_VLSE16_V 0x8005007 +#define MASK_VLSE16_V 0x1c00707f +#define MATCH_VLSE256_V 0x18005007 +#define MASK_VLSE256_V 0x1c00707f +#define MATCH_VLSE32_V 0x8006007 +#define MASK_VLSE32_V 0x1c00707f +#define MATCH_VLSE512_V 0x18006007 +#define MASK_VLSE512_V 0x1c00707f +#define MATCH_VLSE64_V 0x8007007 +#define MASK_VLSE64_V 0x1c00707f +#define MATCH_VLSE8_V 0x8000007 +#define MASK_VLSE8_V 0x1c00707f +#define MATCH_VLUXEI1024_V 0x14007007 +#define MASK_VLUXEI1024_V 0x1c00707f +#define MATCH_VLUXEI128_V 0x14000007 +#define MASK_VLUXEI128_V 0x1c00707f +#define MATCH_VLUXEI16_V 0x4005007 +#define MASK_VLUXEI16_V 0x1c00707f +#define MATCH_VLUXEI256_V 0x14005007 +#define MASK_VLUXEI256_V 0x1c00707f +#define MATCH_VLUXEI32_V 0x4006007 +#define MASK_VLUXEI32_V 0x1c00707f +#define MATCH_VLUXEI512_V 0x14006007 +#define MASK_VLUXEI512_V 0x1c00707f +#define MATCH_VLUXEI64_V 0x4007007 +#define MASK_VLUXEI64_V 0x1c00707f +#define MATCH_VLUXEI8_V 0x4000007 +#define MASK_VLUXEI8_V 0x1c00707f +#define MATCH_VMACC_VV 0xb4002057 +#define MASK_VMACC_VV 0xfc00707f +#define MATCH_VMACC_VX 0xb4006057 +#define MASK_VMACC_VX 0xfc00707f +#define MATCH_VMADC_VI 0x46003057 +#define MASK_VMADC_VI 0xfe00707f +#define MATCH_VMADC_VIM 0x44003057 +#define MASK_VMADC_VIM 0xfe00707f +#define MATCH_VMADC_VV 0x46000057 +#define MASK_VMADC_VV 0xfe00707f +#define MATCH_VMADC_VVM 0x44000057 +#define MASK_VMADC_VVM 0xfe00707f +#define MATCH_VMADC_VX 0x46004057 +#define MASK_VMADC_VX 0xfe00707f +#define MATCH_VMADC_VXM 0x44004057 +#define MASK_VMADC_VXM 0xfe00707f +#define MATCH_VMADD_VV 0xa4002057 +#define MASK_VMADD_VV 0xfc00707f +#define MATCH_VMADD_VX 0xa4006057 +#define MASK_VMADD_VX 0xfc00707f +#define MATCH_VMAND_MM 0x64002057 +#define MASK_VMAND_MM 0xfc00707f +#define MATCH_VMANDN_MM 0x60002057 +#define MASK_VMANDN_MM 0xfc00707f +#define MATCH_VMAX_VV 0x1c000057 +#define MASK_VMAX_VV 0xfc00707f +#define MATCH_VMAX_VX 0x1c004057 +#define MASK_VMAX_VX 0xfc00707f +#define MATCH_VMAXU_VV 0x18000057 +#define MASK_VMAXU_VV 0xfc00707f +#define MATCH_VMAXU_VX 0x18004057 +#define MASK_VMAXU_VX 0xfc00707f +#define MATCH_VMERGE_VIM 0x5c003057 +#define MASK_VMERGE_VIM 0xfe00707f +#define MATCH_VMERGE_VVM 0x5c000057 +#define MASK_VMERGE_VVM 0xfe00707f +#define MATCH_VMERGE_VXM 0x5c004057 +#define MASK_VMERGE_VXM 0xfe00707f +#define MATCH_VMFEQ_VF 0x60005057 +#define MASK_VMFEQ_VF 0xfc00707f +#define MATCH_VMFEQ_VV 0x60001057 +#define MASK_VMFEQ_VV 0xfc00707f +#define MATCH_VMFGE_VF 0x7c005057 +#define MASK_VMFGE_VF 0xfc00707f +#define MATCH_VMFGT_VF 0x74005057 +#define MASK_VMFGT_VF 0xfc00707f +#define MATCH_VMFLE_VF 0x64005057 +#define MASK_VMFLE_VF 0xfc00707f +#define MATCH_VMFLE_VV 0x64001057 +#define MASK_VMFLE_VV 0xfc00707f +#define MATCH_VMFLT_VF 0x6c005057 +#define MASK_VMFLT_VF 0xfc00707f +#define MATCH_VMFLT_VV 0x6c001057 +#define MASK_VMFLT_VV 0xfc00707f +#define MATCH_VMFNE_VF 0x70005057 +#define MASK_VMFNE_VF 0xfc00707f +#define MATCH_VMFNE_VV 0x70001057 +#define MASK_VMFNE_VV 0xfc00707f +#define MATCH_VMIN_VV 0x14000057 +#define MASK_VMIN_VV 0xfc00707f +#define MATCH_VMIN_VX 0x14004057 +#define MASK_VMIN_VX 0xfc00707f +#define MATCH_VMINU_VV 0x10000057 +#define MASK_VMINU_VV 0xfc00707f +#define MATCH_VMINU_VX 0x10004057 +#define MASK_VMINU_VX 0xfc00707f +#define MATCH_VMNAND_MM 0x74002057 +#define MASK_VMNAND_MM 0xfc00707f +#define MATCH_VMNOR_MM 0x78002057 +#define MASK_VMNOR_MM 0xfc00707f +#define MATCH_VMOR_MM 0x68002057 +#define MASK_VMOR_MM 0xfc00707f +#define MATCH_VMORN_MM 0x70002057 +#define MASK_VMORN_MM 0xfc00707f +#define MATCH_VMSBC_VV 0x4e000057 +#define MASK_VMSBC_VV 0xfe00707f +#define MATCH_VMSBC_VVM 0x4c000057 +#define MASK_VMSBC_VVM 0xfe00707f +#define MATCH_VMSBC_VX 0x4e004057 +#define MASK_VMSBC_VX 0xfe00707f +#define MATCH_VMSBC_VXM 0x4c004057 +#define MASK_VMSBC_VXM 0xfe00707f +#define MATCH_VMSBF_M 0x5000a057 +#define MASK_VMSBF_M 0xfc0ff07f +#define MATCH_VMSEQ_VI 0x60003057 +#define MASK_VMSEQ_VI 0xfc00707f +#define MATCH_VMSEQ_VV 0x60000057 +#define MASK_VMSEQ_VV 0xfc00707f +#define MATCH_VMSEQ_VX 0x60004057 +#define MASK_VMSEQ_VX 0xfc00707f +#define MATCH_VMSGT_VI 0x7c003057 +#define MASK_VMSGT_VI 0xfc00707f +#define MATCH_VMSGT_VX 0x7c004057 +#define MASK_VMSGT_VX 0xfc00707f +#define MATCH_VMSGTU_VI 0x78003057 +#define MASK_VMSGTU_VI 0xfc00707f +#define MATCH_VMSGTU_VX 0x78004057 +#define MASK_VMSGTU_VX 0xfc00707f +#define MATCH_VMSIF_M 0x5001a057 +#define MASK_VMSIF_M 0xfc0ff07f +#define MATCH_VMSLE_VI 0x74003057 +#define MASK_VMSLE_VI 0xfc00707f +#define MATCH_VMSLE_VV 0x74000057 +#define MASK_VMSLE_VV 0xfc00707f +#define MATCH_VMSLE_VX 0x74004057 +#define MASK_VMSLE_VX 0xfc00707f +#define MATCH_VMSLEU_VI 0x70003057 +#define MASK_VMSLEU_VI 0xfc00707f +#define MATCH_VMSLEU_VV 0x70000057 +#define MASK_VMSLEU_VV 0xfc00707f +#define MATCH_VMSLEU_VX 0x70004057 +#define MASK_VMSLEU_VX 0xfc00707f +#define MATCH_VMSLT_VV 0x6c000057 +#define MASK_VMSLT_VV 0xfc00707f +#define MATCH_VMSLT_VX 0x6c004057 +#define MASK_VMSLT_VX 0xfc00707f +#define MATCH_VMSLTU_VV 0x68000057 +#define MASK_VMSLTU_VV 0xfc00707f +#define MATCH_VMSLTU_VX 0x68004057 +#define MASK_VMSLTU_VX 0xfc00707f +#define MATCH_VMSNE_VI 0x64003057 +#define MASK_VMSNE_VI 0xfc00707f +#define MATCH_VMSNE_VV 0x64000057 +#define MASK_VMSNE_VV 0xfc00707f +#define MATCH_VMSNE_VX 0x64004057 +#define MASK_VMSNE_VX 0xfc00707f +#define MATCH_VMSOF_M 0x50012057 +#define MASK_VMSOF_M 0xfc0ff07f +#define MATCH_VMUL_VV 0x94002057 +#define MASK_VMUL_VV 0xfc00707f +#define MATCH_VMUL_VX 0x94006057 +#define MASK_VMUL_VX 0xfc00707f +#define MATCH_VMULH_VV 0x9c002057 +#define MASK_VMULH_VV 0xfc00707f +#define MATCH_VMULH_VX 0x9c006057 +#define MASK_VMULH_VX 0xfc00707f +#define MATCH_VMULHSU_VV 0x98002057 +#define MASK_VMULHSU_VV 0xfc00707f +#define MATCH_VMULHSU_VX 0x98006057 +#define MASK_VMULHSU_VX 0xfc00707f +#define MATCH_VMULHU_VV 0x90002057 +#define MASK_VMULHU_VV 0xfc00707f +#define MATCH_VMULHU_VX 0x90006057 +#define MASK_VMULHU_VX 0xfc00707f +#define MATCH_VMV1R_V 0x9e003057 +#define MASK_VMV1R_V 0xfe0ff07f +#define MATCH_VMV2R_V 0x9e00b057 +#define MASK_VMV2R_V 0xfe0ff07f +#define MATCH_VMV4R_V 0x9e01b057 +#define MASK_VMV4R_V 0xfe0ff07f +#define MATCH_VMV8R_V 0x9e03b057 +#define MASK_VMV8R_V 0xfe0ff07f +#define MATCH_VMV_S_X 0x42006057 +#define MASK_VMV_S_X 0xfff0707f +#define MATCH_VMV_V_I 0x5e003057 +#define MASK_VMV_V_I 0xfff0707f +#define MATCH_VMV_V_V 0x5e000057 +#define MASK_VMV_V_V 0xfff0707f +#define MATCH_VMV_V_X 0x5e004057 +#define MASK_VMV_V_X 0xfff0707f +#define MATCH_VMV_X_S 0x42002057 +#define MASK_VMV_X_S 0xfe0ff07f +#define MATCH_VMXNOR_MM 0x7c002057 +#define MASK_VMXNOR_MM 0xfc00707f +#define MATCH_VMXOR_MM 0x6c002057 +#define MASK_VMXOR_MM 0xfc00707f +#define MATCH_VNCLIP_WI 0xbc003057 +#define MASK_VNCLIP_WI 0xfc00707f +#define MATCH_VNCLIP_WV 0xbc000057 +#define MASK_VNCLIP_WV 0xfc00707f +#define MATCH_VNCLIP_WX 0xbc004057 +#define MASK_VNCLIP_WX 0xfc00707f +#define MATCH_VNCLIPU_WI 0xb8003057 +#define MASK_VNCLIPU_WI 0xfc00707f +#define MATCH_VNCLIPU_WV 0xb8000057 +#define MASK_VNCLIPU_WV 0xfc00707f +#define MATCH_VNCLIPU_WX 0xb8004057 +#define MASK_VNCLIPU_WX 0xfc00707f +#define MATCH_VNMSAC_VV 0xbc002057 +#define MASK_VNMSAC_VV 0xfc00707f +#define MATCH_VNMSAC_VX 0xbc006057 +#define MASK_VNMSAC_VX 0xfc00707f +#define MATCH_VNMSUB_VV 0xac002057 +#define MASK_VNMSUB_VV 0xfc00707f +#define MATCH_VNMSUB_VX 0xac006057 +#define MASK_VNMSUB_VX 0xfc00707f +#define MATCH_VNSRA_WI 0xb4003057 +#define MASK_VNSRA_WI 0xfc00707f +#define MATCH_VNSRA_WV 0xb4000057 +#define MASK_VNSRA_WV 0xfc00707f +#define MATCH_VNSRA_WX 0xb4004057 +#define MASK_VNSRA_WX 0xfc00707f +#define MATCH_VNSRL_WI 0xb0003057 +#define MASK_VNSRL_WI 0xfc00707f +#define MATCH_VNSRL_WV 0xb0000057 +#define MASK_VNSRL_WV 0xfc00707f +#define MATCH_VNSRL_WX 0xb0004057 +#define MASK_VNSRL_WX 0xfc00707f +#define MATCH_VOR_VI 0x28003057 +#define MASK_VOR_VI 0xfc00707f +#define MATCH_VOR_VV 0x28000057 +#define MASK_VOR_VV 0xfc00707f +#define MATCH_VOR_VX 0x28004057 +#define MASK_VOR_VX 0xfc00707f +#define MATCH_VREDAND_VS 0x4002057 +#define MASK_VREDAND_VS 0xfc00707f +#define MATCH_VREDMAX_VS 0x1c002057 +#define MASK_VREDMAX_VS 0xfc00707f +#define MATCH_VREDMAXU_VS 0x18002057 +#define MASK_VREDMAXU_VS 0xfc00707f +#define MATCH_VREDMIN_VS 0x14002057 +#define MASK_VREDMIN_VS 0xfc00707f +#define MATCH_VREDMINU_VS 0x10002057 +#define MASK_VREDMINU_VS 0xfc00707f +#define MATCH_VREDOR_VS 0x8002057 +#define MASK_VREDOR_VS 0xfc00707f +#define MATCH_VREDSUM_VS 0x2057 +#define MASK_VREDSUM_VS 0xfc00707f +#define MATCH_VREDXOR_VS 0xc002057 +#define MASK_VREDXOR_VS 0xfc00707f +#define MATCH_VREM_VV 0x8c002057 +#define MASK_VREM_VV 0xfc00707f +#define MATCH_VREM_VX 0x8c006057 +#define MASK_VREM_VX 0xfc00707f +#define MATCH_VREMU_VV 0x88002057 +#define MASK_VREMU_VV 0xfc00707f +#define MATCH_VREMU_VX 0x88006057 +#define MASK_VREMU_VX 0xfc00707f +#define MATCH_VRGATHER_VI 0x30003057 +#define MASK_VRGATHER_VI 0xfc00707f +#define MATCH_VRGATHER_VV 0x30000057 +#define MASK_VRGATHER_VV 0xfc00707f +#define MATCH_VRGATHER_VX 0x30004057 +#define MASK_VRGATHER_VX 0xfc00707f +#define MATCH_VRGATHEREI16_VV 0x38000057 +#define MASK_VRGATHEREI16_VV 0xfc00707f +#define MATCH_VRSUB_VI 0xc003057 +#define MASK_VRSUB_VI 0xfc00707f +#define MATCH_VRSUB_VX 0xc004057 +#define MASK_VRSUB_VX 0xfc00707f +#define MATCH_VS1R_V 0x2800027 +#define MASK_VS1R_V 0xfff0707f +#define MATCH_VS2R_V 0x22800027 +#define MASK_VS2R_V 0xfff0707f +#define MATCH_VS4R_V 0x62800027 +#define MASK_VS4R_V 0xfff0707f +#define MATCH_VS8R_V 0xe2800027 +#define MASK_VS8R_V 0xfff0707f +#define MATCH_VSADD_VI 0x84003057 +#define MASK_VSADD_VI 0xfc00707f +#define MATCH_VSADD_VV 0x84000057 +#define MASK_VSADD_VV 0xfc00707f +#define MATCH_VSADD_VX 0x84004057 +#define MASK_VSADD_VX 0xfc00707f +#define MATCH_VSADDU_VI 0x80003057 +#define MASK_VSADDU_VI 0xfc00707f +#define MATCH_VSADDU_VV 0x80000057 +#define MASK_VSADDU_VV 0xfc00707f +#define MATCH_VSADDU_VX 0x80004057 +#define MASK_VSADDU_VX 0xfc00707f +#define MATCH_VSBC_VVM 0x48000057 +#define MASK_VSBC_VVM 0xfe00707f +#define MATCH_VSBC_VXM 0x48004057 +#define MASK_VSBC_VXM 0xfe00707f +#define MATCH_VSE1024_V 0x10007027 +#define MASK_VSE1024_V 0x1df0707f +#define MATCH_VSE128_V 0x10000027 +#define MASK_VSE128_V 0x1df0707f +#define MATCH_VSE16_V 0x5027 +#define MASK_VSE16_V 0x1df0707f +#define MATCH_VSE256_V 0x10005027 +#define MASK_VSE256_V 0x1df0707f +#define MATCH_VSE32_V 0x6027 +#define MASK_VSE32_V 0x1df0707f +#define MATCH_VSE512_V 0x10006027 +#define MASK_VSE512_V 0x1df0707f +#define MATCH_VSE64_V 0x7027 +#define MASK_VSE64_V 0x1df0707f +#define MATCH_VSE8_V 0x27 +#define MASK_VSE8_V 0x1df0707f +#define MATCH_VSETIVLI 0xc0007057 +#define MASK_VSETIVLI 0xc000707f +#define MATCH_VSETVL 0x80007057 +#define MASK_VSETVL 0xfe00707f +#define MATCH_VSETVLI 0x7057 +#define MASK_VSETVLI 0x8000707f +#define MATCH_VSEXT_VF2 0x4803a057 +#define MASK_VSEXT_VF2 0xfc0ff07f +#define MATCH_VSEXT_VF4 0x4802a057 +#define MASK_VSEXT_VF4 0xfc0ff07f +#define MATCH_VSEXT_VF8 0x4801a057 +#define MASK_VSEXT_VF8 0xfc0ff07f +#define MATCH_VSLIDE1DOWN_VX 0x3c006057 +#define MASK_VSLIDE1DOWN_VX 0xfc00707f +#define MATCH_VSLIDE1UP_VX 0x38006057 +#define MASK_VSLIDE1UP_VX 0xfc00707f +#define MATCH_VSLIDEDOWN_VI 0x3c003057 +#define MASK_VSLIDEDOWN_VI 0xfc00707f +#define MATCH_VSLIDEDOWN_VX 0x3c004057 +#define MASK_VSLIDEDOWN_VX 0xfc00707f +#define MATCH_VSLIDEUP_VI 0x38003057 +#define MASK_VSLIDEUP_VI 0xfc00707f +#define MATCH_VSLIDEUP_VX 0x38004057 +#define MASK_VSLIDEUP_VX 0xfc00707f +#define MATCH_VSLL_VI 0x94003057 +#define MASK_VSLL_VI 0xfc00707f +#define MATCH_VSLL_VV 0x94000057 +#define MASK_VSLL_VV 0xfc00707f +#define MATCH_VSLL_VX 0x94004057 +#define MASK_VSLL_VX 0xfc00707f +#define MATCH_VSM_V 0x2b00027 +#define MASK_VSM_V 0xfff0707f +#define MATCH_VSMUL_VV 0x9c000057 +#define MASK_VSMUL_VV 0xfc00707f +#define MATCH_VSMUL_VX 0x9c004057 +#define MASK_VSMUL_VX 0xfc00707f +#define MATCH_VSOXEI1024_V 0x1c007027 +#define MASK_VSOXEI1024_V 0x1c00707f +#define MATCH_VSOXEI128_V 0x1c000027 +#define MASK_VSOXEI128_V 0x1c00707f +#define MATCH_VSOXEI16_V 0xc005027 +#define MASK_VSOXEI16_V 0x1c00707f +#define MATCH_VSOXEI256_V 0x1c005027 +#define MASK_VSOXEI256_V 0x1c00707f +#define MATCH_VSOXEI32_V 0xc006027 +#define MASK_VSOXEI32_V 0x1c00707f +#define MATCH_VSOXEI512_V 0x1c006027 +#define MASK_VSOXEI512_V 0x1c00707f +#define MATCH_VSOXEI64_V 0xc007027 +#define MASK_VSOXEI64_V 0x1c00707f +#define MATCH_VSOXEI8_V 0xc000027 +#define MASK_VSOXEI8_V 0x1c00707f +#define MATCH_VSRA_VI 0xa4003057 +#define MASK_VSRA_VI 0xfc00707f +#define MATCH_VSRA_VV 0xa4000057 +#define MASK_VSRA_VV 0xfc00707f +#define MATCH_VSRA_VX 0xa4004057 +#define MASK_VSRA_VX 0xfc00707f +#define MATCH_VSRL_VI 0xa0003057 +#define MASK_VSRL_VI 0xfc00707f +#define MATCH_VSRL_VV 0xa0000057 +#define MASK_VSRL_VV 0xfc00707f +#define MATCH_VSRL_VX 0xa0004057 +#define MASK_VSRL_VX 0xfc00707f +#define MATCH_VSSE1024_V 0x18007027 +#define MASK_VSSE1024_V 0x1c00707f +#define MATCH_VSSE128_V 0x18000027 +#define MASK_VSSE128_V 0x1c00707f +#define MATCH_VSSE16_V 0x8005027 +#define MASK_VSSE16_V 0x1c00707f +#define MATCH_VSSE256_V 0x18005027 +#define MASK_VSSE256_V 0x1c00707f +#define MATCH_VSSE32_V 0x8006027 +#define MASK_VSSE32_V 0x1c00707f +#define MATCH_VSSE512_V 0x18006027 +#define MASK_VSSE512_V 0x1c00707f +#define MATCH_VSSE64_V 0x8007027 +#define MASK_VSSE64_V 0x1c00707f +#define MATCH_VSSE8_V 0x8000027 +#define MASK_VSSE8_V 0x1c00707f +#define MATCH_VSSRA_VI 0xac003057 +#define MASK_VSSRA_VI 0xfc00707f +#define MATCH_VSSRA_VV 0xac000057 +#define MASK_VSSRA_VV 0xfc00707f +#define MATCH_VSSRA_VX 0xac004057 +#define MASK_VSSRA_VX 0xfc00707f +#define MATCH_VSSRL_VI 0xa8003057 +#define MASK_VSSRL_VI 0xfc00707f +#define MATCH_VSSRL_VV 0xa8000057 +#define MASK_VSSRL_VV 0xfc00707f +#define MATCH_VSSRL_VX 0xa8004057 +#define MASK_VSSRL_VX 0xfc00707f +#define MATCH_VSSUB_VV 0x8c000057 +#define MASK_VSSUB_VV 0xfc00707f +#define MATCH_VSSUB_VX 0x8c004057 +#define MASK_VSSUB_VX 0xfc00707f +#define MATCH_VSSUBU_VV 0x88000057 +#define MASK_VSSUBU_VV 0xfc00707f +#define MATCH_VSSUBU_VX 0x88004057 +#define MASK_VSSUBU_VX 0xfc00707f +#define MATCH_VSUB_VV 0x8000057 +#define MASK_VSUB_VV 0xfc00707f +#define MATCH_VSUB_VX 0x8004057 +#define MASK_VSUB_VX 0xfc00707f +#define MATCH_VSUXEI1024_V 0x14007027 +#define MASK_VSUXEI1024_V 0x1c00707f +#define MATCH_VSUXEI128_V 0x14000027 +#define MASK_VSUXEI128_V 0x1c00707f +#define MATCH_VSUXEI16_V 0x4005027 +#define MASK_VSUXEI16_V 0x1c00707f +#define MATCH_VSUXEI256_V 0x14005027 +#define MASK_VSUXEI256_V 0x1c00707f +#define MATCH_VSUXEI32_V 0x4006027 +#define MASK_VSUXEI32_V 0x1c00707f +#define MATCH_VSUXEI512_V 0x14006027 +#define MASK_VSUXEI512_V 0x1c00707f +#define MATCH_VSUXEI64_V 0x4007027 +#define MASK_VSUXEI64_V 0x1c00707f +#define MATCH_VSUXEI8_V 0x4000027 +#define MASK_VSUXEI8_V 0x1c00707f +#define MATCH_VWADD_VV 0xc4002057 +#define MASK_VWADD_VV 0xfc00707f +#define MATCH_VWADD_VX 0xc4006057 +#define MASK_VWADD_VX 0xfc00707f +#define MATCH_VWADD_WV 0xd4002057 +#define MASK_VWADD_WV 0xfc00707f +#define MATCH_VWADD_WX 0xd4006057 +#define MASK_VWADD_WX 0xfc00707f +#define MATCH_VWADDU_VV 0xc0002057 +#define MASK_VWADDU_VV 0xfc00707f +#define MATCH_VWADDU_VX 0xc0006057 +#define MASK_VWADDU_VX 0xfc00707f +#define MATCH_VWADDU_WV 0xd0002057 +#define MASK_VWADDU_WV 0xfc00707f +#define MATCH_VWADDU_WX 0xd0006057 +#define MASK_VWADDU_WX 0xfc00707f +#define MATCH_VWMACC_VV 0xf4002057 +#define MASK_VWMACC_VV 0xfc00707f +#define MATCH_VWMACC_VX 0xf4006057 +#define MASK_VWMACC_VX 0xfc00707f +#define MATCH_VWMACCSU_VV 0xfc002057 +#define MASK_VWMACCSU_VV 0xfc00707f +#define MATCH_VWMACCSU_VX 0xfc006057 +#define MASK_VWMACCSU_VX 0xfc00707f +#define MATCH_VWMACCU_VV 0xf0002057 +#define MASK_VWMACCU_VV 0xfc00707f +#define MATCH_VWMACCU_VX 0xf0006057 +#define MASK_VWMACCU_VX 0xfc00707f +#define MATCH_VWMACCUS_VX 0xf8006057 +#define MASK_VWMACCUS_VX 0xfc00707f +#define MATCH_VWMUL_VV 0xec002057 +#define MASK_VWMUL_VV 0xfc00707f +#define MATCH_VWMUL_VX 0xec006057 +#define MASK_VWMUL_VX 0xfc00707f +#define MATCH_VWMULSU_VV 0xe8002057 +#define MASK_VWMULSU_VV 0xfc00707f +#define MATCH_VWMULSU_VX 0xe8006057 +#define MASK_VWMULSU_VX 0xfc00707f +#define MATCH_VWMULU_VV 0xe0002057 +#define MASK_VWMULU_VV 0xfc00707f +#define MATCH_VWMULU_VX 0xe0006057 +#define MASK_VWMULU_VX 0xfc00707f +#define MATCH_VWREDSUM_VS 0xc4000057 +#define MASK_VWREDSUM_VS 0xfc00707f +#define MATCH_VWREDSUMU_VS 0xc0000057 +#define MASK_VWREDSUMU_VS 0xfc00707f +#define MATCH_VWSUB_VV 0xcc002057 +#define MASK_VWSUB_VV 0xfc00707f +#define MATCH_VWSUB_VX 0xcc006057 +#define MASK_VWSUB_VX 0xfc00707f +#define MATCH_VWSUB_WV 0xdc002057 +#define MASK_VWSUB_WV 0xfc00707f +#define MATCH_VWSUB_WX 0xdc006057 +#define MASK_VWSUB_WX 0xfc00707f +#define MATCH_VWSUBU_VV 0xc8002057 +#define MASK_VWSUBU_VV 0xfc00707f +#define MATCH_VWSUBU_VX 0xc8006057 +#define MASK_VWSUBU_VX 0xfc00707f +#define MATCH_VWSUBU_WV 0xd8002057 +#define MASK_VWSUBU_WV 0xfc00707f +#define MATCH_VWSUBU_WX 0xd8006057 +#define MASK_VWSUBU_WX 0xfc00707f +#define MATCH_VXOR_VI 0x2c003057 +#define MASK_VXOR_VI 0xfc00707f +#define MATCH_VXOR_VV 0x2c000057 +#define MASK_VXOR_VV 0xfc00707f +#define MATCH_VXOR_VX 0x2c004057 +#define MASK_VXOR_VX 0xfc00707f +#define MATCH_VZEXT_VF2 0x48032057 +#define MASK_VZEXT_VF2 0xfc0ff07f +#define MATCH_VZEXT_VF4 0x48022057 +#define MASK_VZEXT_VF4 0xfc0ff07f +#define MATCH_VZEXT_VF8 0x48012057 +#define MASK_VZEXT_VF8 0xfc0ff07f +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_WRS_NTO 0xd00073 +#define MASK_WRS_NTO 0xffffffff +#define MATCH_WRS_STO 0x1d00073 +#define MASK_WRS_STO 0xffffffff +#define MATCH_XNOR 0x40004033 +#define MASK_XNOR 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_XPERM16 0x28006033 +#define MASK_XPERM16 0xfe00707f +#define MATCH_XPERM32 0x28000033 +#define MASK_XPERM32 0xfe00707f +#define MATCH_XPERM4 0x28002033 +#define MASK_XPERM4 0xfe00707f +#define MATCH_XPERM8 0x28004033 +#define MASK_XPERM8 0xfe00707f +#define MATCH_ZUNPKD810 0xacc00077 +#define MASK_ZUNPKD810 0xfff0707f +#define MATCH_ZUNPKD820 0xacd00077 +#define MASK_ZUNPKD820 0xfff0707f +#define MATCH_ZUNPKD830 0xace00077 +#define MASK_ZUNPKD830 0xfff0707f +#define MATCH_ZUNPKD831 0xacf00077 +#define MASK_ZUNPKD831 0xfff0707f +#define MATCH_ZUNPKD832 0xad700077 +#define MASK_ZUNPKD832 0xfff0707f + +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_VSTART 0x8 +#define CSR_VXSAT 0x9 +#define CSR_VXRM 0xa +#define CSR_VCSR 0xf +#define CSR_SEED 0x15 +#define CSR_JVT 0x17 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_VL 0xc20 +#define CSR_VTYPE 0xc21 +#define CSR_VLENB 0xc22 +#define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SENVCFG 0x10a +#define CSR_SSTATEEN0 0x10c +#define CSR_SSTATEEN1 0x10d +#define CSR_SSTATEEN2 0x10e +#define CSR_SSTATEEN3 0x10f +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_STIMECMP 0x14d +#define CSR_SISELECT 0x150 +#define CSR_SIREG 0x151 +#define CSR_STOPEI 0x15c +#define CSR_SATP 0x180 +#define CSR_SCONTEXT 0x5a8 +#define CSR_VSSTATUS 0x200 +#define CSR_VSIE 0x204 +#define CSR_VSTVEC 0x205 +#define CSR_VSSCRATCH 0x240 +#define CSR_VSEPC 0x241 +#define CSR_VSCAUSE 0x242 +#define CSR_VSTVAL 0x243 +#define CSR_VSIP 0x244 +#define CSR_VSTIMECMP 0x24d +#define CSR_VSISELECT 0x250 +#define CSR_VSIREG 0x251 +#define CSR_VSTOPEI 0x25c +#define CSR_VSATP 0x280 +#define CSR_HSTATUS 0x600 +#define CSR_HEDELEG 0x602 +#define CSR_HIDELEG 0x603 +#define CSR_HIE 0x604 +#define CSR_HTIMEDELTA 0x605 +#define CSR_HCOUNTEREN 0x606 +#define CSR_HGEIE 0x607 +#define CSR_HVIEN 0x608 +#define CSR_HVICTL 0x609 +#define CSR_HENVCFG 0x60a +#define CSR_HSTATEEN0 0x60c +#define CSR_HSTATEEN1 0x60d +#define CSR_HSTATEEN2 0x60e +#define CSR_HSTATEEN3 0x60f +#define CSR_HTVAL 0x643 +#define CSR_HIP 0x644 +#define CSR_HVIP 0x645 +#define CSR_HVIPRIO1 0x646 +#define CSR_HVIPRIO2 0x647 +#define CSR_HTINST 0x64a +#define CSR_HGATP 0x680 +#define CSR_HCONTEXT 0x6a8 +#define CSR_HGEIP 0xe12 +#define CSR_VSTOPI 0xeb0 +#define CSR_SCOUNTOVF 0xda0 +#define CSR_STOPI 0xdb0 +#define CSR_UTVT 0x7 +#define CSR_UNXTI 0x45 +#define CSR_UINTSTATUS 0x46 +#define CSR_USCRATCHCSW 0x48 +#define CSR_USCRATCHCSWL 0x49 +#define CSR_STVT 0x107 +#define CSR_SNXTI 0x145 +#define CSR_SINTSTATUS 0x146 +#define CSR_SSCRATCHCSW 0x148 +#define CSR_SSCRATCHCSWL 0x149 +#define CSR_MTVT 0x307 +#define CSR_MNXTI 0x345 +#define CSR_MINTSTATUS 0x346 +#define CSR_MSCRATCHCSW 0x348 +#define CSR_MSCRATCHCSWL 0x349 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MVIEN 0x308 +#define CSR_MVIP 0x309 +#define CSR_MENVCFG 0x30a +#define CSR_MSTATEEN0 0x30c +#define CSR_MSTATEEN1 0x30d +#define CSR_MSTATEEN2 0x30e +#define CSR_MSTATEEN3 0x30f +#define CSR_MCOUNTINHIBIT 0x320 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_MTINST 0x34a +#define CSR_MTVAL2 0x34b +#define CSR_MISELECT 0x350 +#define CSR_MIREG 0x351 +#define CSR_MTOPEI 0x35c +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPCFG4 0x3a4 +#define CSR_PMPCFG5 0x3a5 +#define CSR_PMPCFG6 0x3a6 +#define CSR_PMPCFG7 0x3a7 +#define CSR_PMPCFG8 0x3a8 +#define CSR_PMPCFG9 0x3a9 +#define CSR_PMPCFG10 0x3aa +#define CSR_PMPCFG11 0x3ab +#define CSR_PMPCFG12 0x3ac +#define CSR_PMPCFG13 0x3ad +#define CSR_PMPCFG14 0x3ae +#define CSR_PMPCFG15 0x3af +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_PMPADDR16 0x3c0 +#define CSR_PMPADDR17 0x3c1 +#define CSR_PMPADDR18 0x3c2 +#define CSR_PMPADDR19 0x3c3 +#define CSR_PMPADDR20 0x3c4 +#define CSR_PMPADDR21 0x3c5 +#define CSR_PMPADDR22 0x3c6 +#define CSR_PMPADDR23 0x3c7 +#define CSR_PMPADDR24 0x3c8 +#define CSR_PMPADDR25 0x3c9 +#define CSR_PMPADDR26 0x3ca +#define CSR_PMPADDR27 0x3cb +#define CSR_PMPADDR28 0x3cc +#define CSR_PMPADDR29 0x3cd +#define CSR_PMPADDR30 0x3ce +#define CSR_PMPADDR31 0x3cf +#define CSR_PMPADDR32 0x3d0 +#define CSR_PMPADDR33 0x3d1 +#define CSR_PMPADDR34 0x3d2 +#define CSR_PMPADDR35 0x3d3 +#define CSR_PMPADDR36 0x3d4 +#define CSR_PMPADDR37 0x3d5 +#define CSR_PMPADDR38 0x3d6 +#define CSR_PMPADDR39 0x3d7 +#define CSR_PMPADDR40 0x3d8 +#define CSR_PMPADDR41 0x3d9 +#define CSR_PMPADDR42 0x3da +#define CSR_PMPADDR43 0x3db +#define CSR_PMPADDR44 0x3dc +#define CSR_PMPADDR45 0x3dd +#define CSR_PMPADDR46 0x3de +#define CSR_PMPADDR47 0x3df +#define CSR_PMPADDR48 0x3e0 +#define CSR_PMPADDR49 0x3e1 +#define CSR_PMPADDR50 0x3e2 +#define CSR_PMPADDR51 0x3e3 +#define CSR_PMPADDR52 0x3e4 +#define CSR_PMPADDR53 0x3e5 +#define CSR_PMPADDR54 0x3e6 +#define CSR_PMPADDR55 0x3e7 +#define CSR_PMPADDR56 0x3e8 +#define CSR_PMPADDR57 0x3e9 +#define CSR_PMPADDR58 0x3ea +#define CSR_PMPADDR59 0x3eb +#define CSR_PMPADDR60 0x3ec +#define CSR_PMPADDR61 0x3ed +#define CSR_PMPADDR62 0x3ee +#define CSR_PMPADDR63 0x3ef +#define CSR_MSECCFG 0x747 +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_TINFO 0x7a4 +#define CSR_TCONTROL 0x7a5 +#define CSR_MCONTEXT 0x7a8 +#define CSR_MSCONTEXT 0x7aa +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH0 0x7b2 +#define CSR_DSCRATCH1 0x7b3 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_MCONFIGPTR 0xf15 +#define CSR_MTOPI 0xfb0 +#define CSR_SIEH 0x114 +#define CSR_SIPH 0x154 +#define CSR_STIMECMPH 0x15d +#define CSR_VSIEH 0x214 +#define CSR_VSIPH 0x254 +#define CSR_VSTIMECMPH 0x25d +#define CSR_HTIMEDELTAH 0x615 +#define CSR_HIDELEGH 0x613 +#define CSR_HVIENH 0x618 +#define CSR_HENVCFGH 0x61a +#define CSR_HVIPH 0x655 +#define CSR_HVIPRIO1H 0x656 +#define CSR_HVIPRIO2H 0x657 +#define CSR_HSTATEEN0H 0x61c +#define CSR_HSTATEEN1H 0x61d +#define CSR_HSTATEEN2H 0x61e +#define CSR_HSTATEEN3H 0x61f +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MSTATUSH 0x310 +#define CSR_MIDELEGH 0x313 +#define CSR_MIEH 0x314 +#define CSR_MVIENH 0x318 +#define CSR_MVIPH 0x319 +#define CSR_MENVCFGH 0x31a +#define CSR_MSTATEEN0H 0x31c +#define CSR_MSTATEEN1H 0x31d +#define CSR_MSTATEEN2H 0x31e +#define CSR_MSTATEEN3H 0x31f +#define CSR_MIPH 0x354 +#define CSR_MHPMEVENT3H 0x723 +#define CSR_MHPMEVENT4H 0x724 +#define CSR_MHPMEVENT5H 0x725 +#define CSR_MHPMEVENT6H 0x726 +#define CSR_MHPMEVENT7H 0x727 +#define CSR_MHPMEVENT8H 0x728 +#define CSR_MHPMEVENT9H 0x729 +#define CSR_MHPMEVENT10H 0x72a +#define CSR_MHPMEVENT11H 0x72b +#define CSR_MHPMEVENT12H 0x72c +#define CSR_MHPMEVENT13H 0x72d +#define CSR_MHPMEVENT14H 0x72e +#define CSR_MHPMEVENT15H 0x72f +#define CSR_MHPMEVENT16H 0x730 +#define CSR_MHPMEVENT17H 0x731 +#define CSR_MHPMEVENT18H 0x732 +#define CSR_MHPMEVENT19H 0x733 +#define CSR_MHPMEVENT20H 0x734 +#define CSR_MHPMEVENT21H 0x735 +#define CSR_MHPMEVENT22H 0x736 +#define CSR_MHPMEVENT23H 0x737 +#define CSR_MHPMEVENT24H 0x738 +#define CSR_MHPMEVENT25H 0x739 +#define CSR_MHPMEVENT26H 0x73a +#define CSR_MHPMEVENT27H 0x73b +#define CSR_MHPMEVENT28H 0x73c +#define CSR_MHPMEVENT29H 0x73d +#define CSR_MHPMEVENT30H 0x73e +#define CSR_MHPMEVENT31H 0x73f +#define CSR_MNSCRATCH 0x740 +#define CSR_MNEPC 0x741 +#define CSR_MNCAUSE 0x742 +#define CSR_MNSTATUS 0x744 +#define CSR_MSECCFGH 0x757 +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f + +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 +#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 +#define CAUSE_VIRTUAL_INSTRUCTION 0x16 +#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 + +#define INSN_FIELD_RD 0xf80 +#define INSN_FIELD_RT 0xf8000 +#define INSN_FIELD_RS1 0xf8000 +#define INSN_FIELD_RS2 0x1f00000 +#define INSN_FIELD_RS3 0xf8000000 +#define INSN_FIELD_AQRL 0x6000000 +#define INSN_FIELD_AQ 0x4000000 +#define INSN_FIELD_RL 0x2000000 +#define INSN_FIELD_FM 0xf0000000 +#define INSN_FIELD_PRED 0xf000000 +#define INSN_FIELD_SUCC 0xf00000 +#define INSN_FIELD_RM 0x7000 +#define INSN_FIELD_FUNCT3 0x7000 +#define INSN_FIELD_FUNCT2 0x6000000 +#define INSN_FIELD_IMM20 0xfffff000 +#define INSN_FIELD_JIMM20 0xfffff000 +#define INSN_FIELD_IMM12 0xfff00000 +#define INSN_FIELD_CSR 0xfff00000 +#define INSN_FIELD_IMM12HI 0xfe000000 +#define INSN_FIELD_BIMM12HI 0xfe000000 +#define INSN_FIELD_IMM12LO 0xf80 +#define INSN_FIELD_BIMM12LO 0xf80 +#define INSN_FIELD_ZIMM 0xf8000 +#define INSN_FIELD_SHAMTQ 0x7f00000 +#define INSN_FIELD_SHAMTW 0x1f00000 +#define INSN_FIELD_SHAMTW4 0xf00000 +#define INSN_FIELD_SHAMTD 0x3f00000 +#define INSN_FIELD_BS 0xc0000000 +#define INSN_FIELD_RNUM 0xf00000 +#define INSN_FIELD_RC 0x3e000000 +#define INSN_FIELD_IMM2 0x300000 +#define INSN_FIELD_IMM3 0x700000 +#define INSN_FIELD_IMM4 0xf00000 +#define INSN_FIELD_IMM5 0x1f00000 +#define INSN_FIELD_IMM6 0x3f00000 +#define INSN_FIELD_OPCODE 0x7f +#define INSN_FIELD_FUNCT7 0xfe000000 +#define INSN_FIELD_VD 0xf80 +#define INSN_FIELD_VS3 0xf80 +#define INSN_FIELD_VS1 0xf8000 +#define INSN_FIELD_VS2 0x1f00000 +#define INSN_FIELD_VM 0x2000000 +#define INSN_FIELD_WD 0x4000000 +#define INSN_FIELD_AMOOP 0xf8000000 +#define INSN_FIELD_NF 0xe0000000 +#define INSN_FIELD_SIMM5 0xf8000 +#define INSN_FIELD_ZIMM10 0x3ff00000 +#define INSN_FIELD_ZIMM11 0x7ff00000 +#define INSN_FIELD_C_NZUIMM10 0x1fe0 +#define INSN_FIELD_C_UIMM7LO 0x60 +#define INSN_FIELD_C_UIMM7HI 0x1c00 +#define INSN_FIELD_C_UIMM8LO 0x60 +#define INSN_FIELD_C_UIMM8HI 0x1c00 +#define INSN_FIELD_C_UIMM9LO 0x60 +#define INSN_FIELD_C_UIMM9HI 0x1c00 +#define INSN_FIELD_C_NZIMM6LO 0x7c +#define INSN_FIELD_C_NZIMM6HI 0x1000 +#define INSN_FIELD_C_IMM6LO 0x7c +#define INSN_FIELD_C_IMM6HI 0x1000 +#define INSN_FIELD_C_NZIMM10HI 0x1000 +#define INSN_FIELD_C_NZIMM10LO 0x7c +#define INSN_FIELD_C_NZIMM18HI 0x1000 +#define INSN_FIELD_C_NZIMM18LO 0x7c +#define INSN_FIELD_C_IMM12 0x1ffc +#define INSN_FIELD_C_BIMM9LO 0x7c +#define INSN_FIELD_C_BIMM9HI 0x1c00 +#define INSN_FIELD_C_NZUIMM5 0x7c +#define INSN_FIELD_C_NZUIMM6LO 0x7c +#define INSN_FIELD_C_NZUIMM6HI 0x1000 +#define INSN_FIELD_C_UIMM8SPLO 0x7c +#define INSN_FIELD_C_UIMM8SPHI 0x1000 +#define INSN_FIELD_C_UIMM8SP_S 0x1f80 +#define INSN_FIELD_C_UIMM10SPLO 0x7c +#define INSN_FIELD_C_UIMM10SPHI 0x1000 +#define INSN_FIELD_C_UIMM9SPLO 0x7c +#define INSN_FIELD_C_UIMM9SPHI 0x1000 +#define INSN_FIELD_C_UIMM10SP_S 0x1f80 +#define INSN_FIELD_C_UIMM9SP_S 0x1f80 +#define INSN_FIELD_C_UIMM2 0x60 +#define INSN_FIELD_C_UIMM1 0x20 +#define INSN_FIELD_C_RLIST 0xf0 +#define INSN_FIELD_C_SPIMM 0xc +#define INSN_FIELD_C_INDEX 0x3fc +#define INSN_FIELD_RS1_P 0x380 +#define INSN_FIELD_RS2_P 0x1c +#define INSN_FIELD_RD_P 0x1c +#define INSN_FIELD_RD_RS1_N0 0xf80 +#define INSN_FIELD_RD_RS1_P 0x380 +#define INSN_FIELD_RD_RS1 0xf80 +#define INSN_FIELD_RD_N2 0xf80 +#define INSN_FIELD_RD_N0 0xf80 +#define INSN_FIELD_RS1_N0 0xf80 +#define INSN_FIELD_C_RS2_N0 0x7c +#define INSN_FIELD_C_RS1_N0 0xf80 +#define INSN_FIELD_C_RS2 0x7c +#define INSN_FIELD_C_SREG1 0x380 +#define INSN_FIELD_C_SREG2 0x1c +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(add16, MATCH_ADD16, MASK_ADD16) +DECLARE_INSN(add32, MATCH_ADD32, MASK_ADD32) +DECLARE_INSN(add64, MATCH_ADD64, MASK_ADD64) +DECLARE_INSN(add8, MATCH_ADD8, MASK_ADD8) +DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(aes32dsi, MATCH_AES32DSI, MASK_AES32DSI) +DECLARE_INSN(aes32dsmi, MATCH_AES32DSMI, MASK_AES32DSMI) +DECLARE_INSN(aes32esi, MATCH_AES32ESI, MASK_AES32ESI) +DECLARE_INSN(aes32esmi, MATCH_AES32ESMI, MASK_AES32ESMI) +DECLARE_INSN(aes64ds, MATCH_AES64DS, MASK_AES64DS) +DECLARE_INSN(aes64dsm, MATCH_AES64DSM, MASK_AES64DSM) +DECLARE_INSN(aes64es, MATCH_AES64ES, MASK_AES64ES) +DECLARE_INSN(aes64esm, MATCH_AES64ESM, MASK_AES64ESM) +DECLARE_INSN(aes64im, MATCH_AES64IM, MASK_AES64IM) +DECLARE_INSN(aes64ks1i, MATCH_AES64KS1I, MASK_AES64KS1I) +DECLARE_INSN(aes64ks2, MATCH_AES64KS2, MASK_AES64KS2) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(ave, MATCH_AVE, MASK_AVE) +DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR) +DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI) +DECLARE_INSN(bcompress, MATCH_BCOMPRESS, MASK_BCOMPRESS) +DECLARE_INSN(bcompressw, MATCH_BCOMPRESSW, MASK_BCOMPRESSW) +DECLARE_INSN(bdecompress, MATCH_BDECOMPRESS, MASK_BDECOMPRESS) +DECLARE_INSN(bdecompressw, MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW) +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT) +DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI) +DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP) +DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(binv, MATCH_BINV, MASK_BINV) +DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP) +DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR) +DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(bset, MATCH_BSET, MASK_BSET) +DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_lbu, MATCH_C_LBU, MASK_C_LBU) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH) +DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_mul, MATCH_C_MUL, MASK_C_MUL) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_not, MATCH_C_NOT, MASK_C_NOT) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_sext_b, MATCH_C_SEXT_B, MASK_C_SEXT_B) +DECLARE_INSN(c_sext_h, MATCH_C_SEXT_H, MASK_C_SEXT_H) +DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_zext_b, MATCH_C_ZEXT_B, MASK_C_ZEXT_B) +DECLARE_INSN(c_zext_h, MATCH_C_ZEXT_H, MASK_C_ZEXT_H) +DECLARE_INSN(c_zext_w, MATCH_C_ZEXT_W, MASK_C_ZEXT_W) +DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN) +DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH) +DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL) +DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO) +DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL) +DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH) +DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR) +DECLARE_INSN(clrs16, MATCH_CLRS16, MASK_CLRS16) +DECLARE_INSN(clrs32, MATCH_CLRS32, MASK_CLRS32) +DECLARE_INSN(clrs8, MATCH_CLRS8, MASK_CLRS8) +DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ) +DECLARE_INSN(clz16, MATCH_CLZ16, MASK_CLZ16) +DECLARE_INSN(clz32, MATCH_CLZ32, MASK_CLZ32) +DECLARE_INSN(clz8, MATCH_CLZ8, MASK_CLZ8) +DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW) +DECLARE_INSN(cm_jalt, MATCH_CM_JALT, MASK_CM_JALT) +DECLARE_INSN(cm_mva01s, MATCH_CM_MVA01S, MASK_CM_MVA01S) +DECLARE_INSN(cm_mvsa01, MATCH_CM_MVSA01, MASK_CM_MVSA01) +DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP) +DECLARE_INSN(cm_popret, MATCH_CM_POPRET, MASK_CM_POPRET) +DECLARE_INSN(cm_popretz, MATCH_CM_POPRETZ, MASK_CM_POPRETZ) +DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH) +DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX) +DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV) +DECLARE_INSN(cmpeq16, MATCH_CMPEQ16, MASK_CMPEQ16) +DECLARE_INSN(cmpeq8, MATCH_CMPEQ8, MASK_CMPEQ8) +DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP) +DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW) +DECLARE_INSN(cras16, MATCH_CRAS16, MASK_CRAS16) +DECLARE_INSN(cras32, MATCH_CRAS32, MASK_CRAS32) +DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B) +DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D) +DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H) +DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W) +DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B) +DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D) +DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H) +DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W) +DECLARE_INSN(crsa16, MATCH_CRSA16, MASK_CRSA16) +DECLARE_INSN(crsa32, MATCH_CRSA32, MASK_CRSA32) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ) +DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW) +DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ) +DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H) +DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H) +DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D) +DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L) +DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU) +DECLARE_INSN(fcvt_h_q, MATCH_FCVT_H_Q, MASK_FCVT_H_Q) +DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S) +DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W) +DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H) +DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H) +DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) +DECLARE_INSN(fcvt_q_h, MATCH_FCVT_Q_H, MASK_FCVT_Q_H) +DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) +DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) +DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) +DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) +DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H) +DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H) +DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H) +DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H) +DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H) +DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flh, MATCH_FLH, MASK_FLH) +DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H) +DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H) +DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H) +DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H) +DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H) +DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H) +DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X) +DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H) +DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H) +DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H) +DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H) +DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H) +DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H) +DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH) +DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL) +DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW) +DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H) +DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR) +DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI) +DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW) +DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H) +DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC) +DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI) +DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW) +DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW) +DECLARE_INSN(grev, MATCH_GREV, MASK_GREV) +DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI) +DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW) +DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW) +DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA) +DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA) +DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA) +DECLARE_INSN(hinval_vvma, MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA) +DECLARE_INSN(hlv_b, MATCH_HLV_B, MASK_HLV_B) +DECLARE_INSN(hlv_bu, MATCH_HLV_BU, MASK_HLV_BU) +DECLARE_INSN(hlv_d, MATCH_HLV_D, MASK_HLV_D) +DECLARE_INSN(hlv_h, MATCH_HLV_H, MASK_HLV_H) +DECLARE_INSN(hlv_hu, MATCH_HLV_HU, MASK_HLV_HU) +DECLARE_INSN(hlv_w, MATCH_HLV_W, MASK_HLV_W) +DECLARE_INSN(hlv_wu, MATCH_HLV_WU, MASK_HLV_WU) +DECLARE_INSN(hlvx_hu, MATCH_HLVX_HU, MASK_HLVX_HU) +DECLARE_INSN(hlvx_wu, MATCH_HLVX_WU, MASK_HLVX_WU) +DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B) +DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D) +DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H) +DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W) +DECLARE_INSN(insb, MATCH_INSB, MASK_INSB) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(kabs16, MATCH_KABS16, MASK_KABS16) +DECLARE_INSN(kabs32, MATCH_KABS32, MASK_KABS32) +DECLARE_INSN(kabs8, MATCH_KABS8, MASK_KABS8) +DECLARE_INSN(kabsw, MATCH_KABSW, MASK_KABSW) +DECLARE_INSN(kadd16, MATCH_KADD16, MASK_KADD16) +DECLARE_INSN(kadd32, MATCH_KADD32, MASK_KADD32) +DECLARE_INSN(kadd64, MATCH_KADD64, MASK_KADD64) +DECLARE_INSN(kadd8, MATCH_KADD8, MASK_KADD8) +DECLARE_INSN(kaddh, MATCH_KADDH, MASK_KADDH) +DECLARE_INSN(kaddw, MATCH_KADDW, MASK_KADDW) +DECLARE_INSN(kcras16, MATCH_KCRAS16, MASK_KCRAS16) +DECLARE_INSN(kcras32, MATCH_KCRAS32, MASK_KCRAS32) +DECLARE_INSN(kcrsa16, MATCH_KCRSA16, MASK_KCRSA16) +DECLARE_INSN(kcrsa32, MATCH_KCRSA32, MASK_KCRSA32) +DECLARE_INSN(kdmabb, MATCH_KDMABB, MASK_KDMABB) +DECLARE_INSN(kdmabb16, MATCH_KDMABB16, MASK_KDMABB16) +DECLARE_INSN(kdmabt, MATCH_KDMABT, MASK_KDMABT) +DECLARE_INSN(kdmabt16, MATCH_KDMABT16, MASK_KDMABT16) +DECLARE_INSN(kdmatt, MATCH_KDMATT, MASK_KDMATT) +DECLARE_INSN(kdmatt16, MATCH_KDMATT16, MASK_KDMATT16) +DECLARE_INSN(kdmbb, MATCH_KDMBB, MASK_KDMBB) +DECLARE_INSN(kdmbb16, MATCH_KDMBB16, MASK_KDMBB16) +DECLARE_INSN(kdmbt, MATCH_KDMBT, MASK_KDMBT) +DECLARE_INSN(kdmbt16, MATCH_KDMBT16, MASK_KDMBT16) +DECLARE_INSN(kdmtt, MATCH_KDMTT, MASK_KDMTT) +DECLARE_INSN(kdmtt16, MATCH_KDMTT16, MASK_KDMTT16) +DECLARE_INSN(khm16, MATCH_KHM16, MASK_KHM16) +DECLARE_INSN(khm8, MATCH_KHM8, MASK_KHM8) +DECLARE_INSN(khmbb, MATCH_KHMBB, MASK_KHMBB) +DECLARE_INSN(khmbb16, MATCH_KHMBB16, MASK_KHMBB16) +DECLARE_INSN(khmbt, MATCH_KHMBT, MASK_KHMBT) +DECLARE_INSN(khmbt16, MATCH_KHMBT16, MASK_KHMBT16) +DECLARE_INSN(khmtt, MATCH_KHMTT, MASK_KHMTT) +DECLARE_INSN(khmtt16, MATCH_KHMTT16, MASK_KHMTT16) +DECLARE_INSN(khmx16, MATCH_KHMX16, MASK_KHMX16) +DECLARE_INSN(khmx8, MATCH_KHMX8, MASK_KHMX8) +DECLARE_INSN(kmabb, MATCH_KMABB, MASK_KMABB) +DECLARE_INSN(kmabb32, MATCH_KMABB32, MASK_KMABB32) +DECLARE_INSN(kmabt, MATCH_KMABT, MASK_KMABT) +DECLARE_INSN(kmabt32, MATCH_KMABT32, MASK_KMABT32) +DECLARE_INSN(kmada, MATCH_KMADA, MASK_KMADA) +DECLARE_INSN(kmadrs, MATCH_KMADRS, MASK_KMADRS) +DECLARE_INSN(kmadrs32, MATCH_KMADRS32, MASK_KMADRS32) +DECLARE_INSN(kmads, MATCH_KMADS, MASK_KMADS) +DECLARE_INSN(kmads32, MATCH_KMADS32, MASK_KMADS32) +DECLARE_INSN(kmar64, MATCH_KMAR64, MASK_KMAR64) +DECLARE_INSN(kmatt, MATCH_KMATT, MASK_KMATT) +DECLARE_INSN(kmatt32, MATCH_KMATT32, MASK_KMATT32) +DECLARE_INSN(kmaxda, MATCH_KMAXDA, MASK_KMAXDA) +DECLARE_INSN(kmaxda32, MATCH_KMAXDA32, MASK_KMAXDA32) +DECLARE_INSN(kmaxds, MATCH_KMAXDS, MASK_KMAXDS) +DECLARE_INSN(kmaxds32, MATCH_KMAXDS32, MASK_KMAXDS32) +DECLARE_INSN(kmda, MATCH_KMDA, MASK_KMDA) +DECLARE_INSN(kmda32, MATCH_KMDA32, MASK_KMDA32) +DECLARE_INSN(kmmac, MATCH_KMMAC, MASK_KMMAC) +DECLARE_INSN(kmmac_u, MATCH_KMMAC_U, MASK_KMMAC_U) +DECLARE_INSN(kmmawb, MATCH_KMMAWB, MASK_KMMAWB) +DECLARE_INSN(kmmawb2, MATCH_KMMAWB2, MASK_KMMAWB2) +DECLARE_INSN(kmmawb2_u, MATCH_KMMAWB2_U, MASK_KMMAWB2_U) +DECLARE_INSN(kmmawb_u, MATCH_KMMAWB_U, MASK_KMMAWB_U) +DECLARE_INSN(kmmawt, MATCH_KMMAWT, MASK_KMMAWT) +DECLARE_INSN(kmmawt2, MATCH_KMMAWT2, MASK_KMMAWT2) +DECLARE_INSN(kmmawt2_u, MATCH_KMMAWT2_U, MASK_KMMAWT2_U) +DECLARE_INSN(kmmawt_u, MATCH_KMMAWT_U, MASK_KMMAWT_U) +DECLARE_INSN(kmmsb, MATCH_KMMSB, MASK_KMMSB) +DECLARE_INSN(kmmsb_u, MATCH_KMMSB_U, MASK_KMMSB_U) +DECLARE_INSN(kmmwb2, MATCH_KMMWB2, MASK_KMMWB2) +DECLARE_INSN(kmmwb2_u, MATCH_KMMWB2_U, MASK_KMMWB2_U) +DECLARE_INSN(kmmwt2, MATCH_KMMWT2, MASK_KMMWT2) +DECLARE_INSN(kmmwt2_u, MATCH_KMMWT2_U, MASK_KMMWT2_U) +DECLARE_INSN(kmsda, MATCH_KMSDA, MASK_KMSDA) +DECLARE_INSN(kmsda32, MATCH_KMSDA32, MASK_KMSDA32) +DECLARE_INSN(kmsr64, MATCH_KMSR64, MASK_KMSR64) +DECLARE_INSN(kmsxda, MATCH_KMSXDA, MASK_KMSXDA) +DECLARE_INSN(kmsxda32, MATCH_KMSXDA32, MASK_KMSXDA32) +DECLARE_INSN(kmxda, MATCH_KMXDA, MASK_KMXDA) +DECLARE_INSN(kmxda32, MATCH_KMXDA32, MASK_KMXDA32) +DECLARE_INSN(ksll16, MATCH_KSLL16, MASK_KSLL16) +DECLARE_INSN(ksll32, MATCH_KSLL32, MASK_KSLL32) +DECLARE_INSN(ksll8, MATCH_KSLL8, MASK_KSLL8) +DECLARE_INSN(kslli16, MATCH_KSLLI16, MASK_KSLLI16) +DECLARE_INSN(kslli32, MATCH_KSLLI32, MASK_KSLLI32) +DECLARE_INSN(kslli8, MATCH_KSLLI8, MASK_KSLLI8) +DECLARE_INSN(kslliw, MATCH_KSLLIW, MASK_KSLLIW) +DECLARE_INSN(ksllw, MATCH_KSLLW, MASK_KSLLW) +DECLARE_INSN(kslra16, MATCH_KSLRA16, MASK_KSLRA16) +DECLARE_INSN(kslra16_u, MATCH_KSLRA16_U, MASK_KSLRA16_U) +DECLARE_INSN(kslra32, MATCH_KSLRA32, MASK_KSLRA32) +DECLARE_INSN(kslra32_u, MATCH_KSLRA32_U, MASK_KSLRA32_U) +DECLARE_INSN(kslra8, MATCH_KSLRA8, MASK_KSLRA8) +DECLARE_INSN(kslra8_u, MATCH_KSLRA8_U, MASK_KSLRA8_U) +DECLARE_INSN(kslraw, MATCH_KSLRAW, MASK_KSLRAW) +DECLARE_INSN(kslraw_u, MATCH_KSLRAW_U, MASK_KSLRAW_U) +DECLARE_INSN(kstas16, MATCH_KSTAS16, MASK_KSTAS16) +DECLARE_INSN(kstas32, MATCH_KSTAS32, MASK_KSTAS32) +DECLARE_INSN(kstsa16, MATCH_KSTSA16, MASK_KSTSA16) +DECLARE_INSN(kstsa32, MATCH_KSTSA32, MASK_KSTSA32) +DECLARE_INSN(ksub16, MATCH_KSUB16, MASK_KSUB16) +DECLARE_INSN(ksub32, MATCH_KSUB32, MASK_KSUB32) +DECLARE_INSN(ksub64, MATCH_KSUB64, MASK_KSUB64) +DECLARE_INSN(ksub8, MATCH_KSUB8, MASK_KSUB8) +DECLARE_INSN(ksubh, MATCH_KSUBH, MASK_KSUBH) +DECLARE_INSN(ksubw, MATCH_KSUBW, MASK_KSUBW) +DECLARE_INSN(kwmmul, MATCH_KWMMUL, MASK_KWMMUL) +DECLARE_INSN(kwmmul_u, MATCH_KWMMUL_U, MASK_KWMMUL_U) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(maddr32, MATCH_MADDR32, MASK_MADDR32) +DECLARE_INSN(max, MATCH_MAX, MASK_MAX) +DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU) +DECLARE_INSN(min, MATCH_MIN, MASK_MIN) +DECLARE_INSN(minu, MATCH_MINU, MASK_MINU) +DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(msubr32, MATCH_MSUBR32, MASK_MSUBR32) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(mulr64, MATCH_MULR64, MASK_MULR64) +DECLARE_INSN(mulsr64, MATCH_MULSR64, MASK_MULSR64) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(orn, MATCH_ORN, MASK_ORN) +DECLARE_INSN(pack, MATCH_PACK, MASK_PACK) +DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH) +DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU) +DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW) +DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW) +DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE) +DECLARE_INSN(pbsad, MATCH_PBSAD, MASK_PBSAD) +DECLARE_INSN(pbsada, MATCH_PBSADA, MASK_PBSADA) +DECLARE_INSN(pkbb16, MATCH_PKBB16, MASK_PKBB16) +DECLARE_INSN(pkbt16, MATCH_PKBT16, MASK_PKBT16) +DECLARE_INSN(pkbt32, MATCH_PKBT32, MASK_PKBT32) +DECLARE_INSN(pktb16, MATCH_PKTB16, MASK_PKTB16) +DECLARE_INSN(pktb32, MATCH_PKTB32, MASK_PKTB32) +DECLARE_INSN(pktt16, MATCH_PKTT16, MASK_PKTT16) +DECLARE_INSN(prefetch_i, MATCH_PREFETCH_I, MASK_PREFETCH_I) +DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R) +DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W) +DECLARE_INSN(radd16, MATCH_RADD16, MASK_RADD16) +DECLARE_INSN(radd32, MATCH_RADD32, MASK_RADD32) +DECLARE_INSN(radd64, MATCH_RADD64, MASK_RADD64) +DECLARE_INSN(radd8, MATCH_RADD8, MASK_RADD8) +DECLARE_INSN(raddw, MATCH_RADDW, MASK_RADDW) +DECLARE_INSN(rcras16, MATCH_RCRAS16, MASK_RCRAS16) +DECLARE_INSN(rcras32, MATCH_RCRAS32, MASK_RCRAS32) +DECLARE_INSN(rcrsa16, MATCH_RCRSA16, MASK_RCRSA16) +DECLARE_INSN(rcrsa32, MATCH_RCRSA32, MASK_RCRSA32) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(rol, MATCH_ROL, MASK_ROL) +DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW) +DECLARE_INSN(ror, MATCH_ROR, MASK_ROR) +DECLARE_INSN(rori, MATCH_RORI, MASK_RORI) +DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW) +DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW) +DECLARE_INSN(rstas16, MATCH_RSTAS16, MASK_RSTAS16) +DECLARE_INSN(rstas32, MATCH_RSTAS32, MASK_RSTAS32) +DECLARE_INSN(rstsa16, MATCH_RSTSA16, MASK_RSTSA16) +DECLARE_INSN(rstsa32, MATCH_RSTSA32, MASK_RSTSA32) +DECLARE_INSN(rsub16, MATCH_RSUB16, MASK_RSUB16) +DECLARE_INSN(rsub32, MATCH_RSUB32, MASK_RSUB32) +DECLARE_INSN(rsub64, MATCH_RSUB64, MASK_RSUB64) +DECLARE_INSN(rsub8, MATCH_RSUB8, MASK_RSUB8) +DECLARE_INSN(rsubw, MATCH_RSUBW, MASK_RSUBW) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(sclip16, MATCH_SCLIP16, MASK_SCLIP16) +DECLARE_INSN(sclip32, MATCH_SCLIP32, MASK_SCLIP32) +DECLARE_INSN(sclip8, MATCH_SCLIP8, MASK_SCLIP8) +DECLARE_INSN(scmple16, MATCH_SCMPLE16, MASK_SCMPLE16) +DECLARE_INSN(scmple8, MATCH_SCMPLE8, MASK_SCMPLE8) +DECLARE_INSN(scmplt16, MATCH_SCMPLT16, MASK_SCMPLT16) +DECLARE_INSN(scmplt8, MATCH_SCMPLT8, MASK_SCMPLT8) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B) +DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H) +DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR) +DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) +DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD) +DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW) +DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD) +DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW) +DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD) +DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW) +DECLARE_INSN(sha256sig0, MATCH_SHA256SIG0, MASK_SHA256SIG0) +DECLARE_INSN(sha256sig1, MATCH_SHA256SIG1, MASK_SHA256SIG1) +DECLARE_INSN(sha256sum0, MATCH_SHA256SUM0, MASK_SHA256SUM0) +DECLARE_INSN(sha256sum1, MATCH_SHA256SUM1, MASK_SHA256SUM1) +DECLARE_INSN(sha512sig0, MATCH_SHA512SIG0, MASK_SHA512SIG0) +DECLARE_INSN(sha512sig0h, MATCH_SHA512SIG0H, MASK_SHA512SIG0H) +DECLARE_INSN(sha512sig0l, MATCH_SHA512SIG0L, MASK_SHA512SIG0L) +DECLARE_INSN(sha512sig1, MATCH_SHA512SIG1, MASK_SHA512SIG1) +DECLARE_INSN(sha512sig1h, MATCH_SHA512SIG1H, MASK_SHA512SIG1H) +DECLARE_INSN(sha512sig1l, MATCH_SHA512SIG1L, MASK_SHA512SIG1L) +DECLARE_INSN(sha512sum0, MATCH_SHA512SUM0, MASK_SHA512SUM0) +DECLARE_INSN(sha512sum0r, MATCH_SHA512SUM0R, MASK_SHA512SUM0R) +DECLARE_INSN(sha512sum1, MATCH_SHA512SUM1, MASK_SHA512SUM1) +DECLARE_INSN(sha512sum1r, MATCH_SHA512SUM1R, MASK_SHA512SUM1R) +DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL) +DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI) +DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW) +DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(sll16, MATCH_SLL16, MASK_SLL16) +DECLARE_INSN(sll32, MATCH_SLL32, MASK_SLL32) +DECLARE_INSN(sll8, MATCH_SLL8, MASK_SLL8) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slli16, MATCH_SLLI16, MASK_SLLI16) +DECLARE_INSN(slli32, MATCH_SLLI32, MASK_SLLI32) +DECLARE_INSN(slli8, MATCH_SLLI8, MASK_SLLI8) +DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) +DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(slo, MATCH_SLO, MASK_SLO) +DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI) +DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW) +DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(sm3p0, MATCH_SM3P0, MASK_SM3P0) +DECLARE_INSN(sm3p1, MATCH_SM3P1, MASK_SM3P1) +DECLARE_INSN(sm4ed, MATCH_SM4ED, MASK_SM4ED) +DECLARE_INSN(sm4ks, MATCH_SM4KS, MASK_SM4KS) +DECLARE_INSN(smal, MATCH_SMAL, MASK_SMAL) +DECLARE_INSN(smalbb, MATCH_SMALBB, MASK_SMALBB) +DECLARE_INSN(smalbt, MATCH_SMALBT, MASK_SMALBT) +DECLARE_INSN(smalda, MATCH_SMALDA, MASK_SMALDA) +DECLARE_INSN(smaldrs, MATCH_SMALDRS, MASK_SMALDRS) +DECLARE_INSN(smalds, MATCH_SMALDS, MASK_SMALDS) +DECLARE_INSN(smaltt, MATCH_SMALTT, MASK_SMALTT) +DECLARE_INSN(smalxda, MATCH_SMALXDA, MASK_SMALXDA) +DECLARE_INSN(smalxds, MATCH_SMALXDS, MASK_SMALXDS) +DECLARE_INSN(smaqa, MATCH_SMAQA, MASK_SMAQA) +DECLARE_INSN(smaqa_su, MATCH_SMAQA_SU, MASK_SMAQA_SU) +DECLARE_INSN(smar64, MATCH_SMAR64, MASK_SMAR64) +DECLARE_INSN(smax16, MATCH_SMAX16, MASK_SMAX16) +DECLARE_INSN(smax32, MATCH_SMAX32, MASK_SMAX32) +DECLARE_INSN(smax8, MATCH_SMAX8, MASK_SMAX8) +DECLARE_INSN(smbb16, MATCH_SMBB16, MASK_SMBB16) +DECLARE_INSN(smbt16, MATCH_SMBT16, MASK_SMBT16) +DECLARE_INSN(smbt32, MATCH_SMBT32, MASK_SMBT32) +DECLARE_INSN(smdrs, MATCH_SMDRS, MASK_SMDRS) +DECLARE_INSN(smdrs32, MATCH_SMDRS32, MASK_SMDRS32) +DECLARE_INSN(smds, MATCH_SMDS, MASK_SMDS) +DECLARE_INSN(smds32, MATCH_SMDS32, MASK_SMDS32) +DECLARE_INSN(smin16, MATCH_SMIN16, MASK_SMIN16) +DECLARE_INSN(smin32, MATCH_SMIN32, MASK_SMIN32) +DECLARE_INSN(smin8, MATCH_SMIN8, MASK_SMIN8) +DECLARE_INSN(smmul, MATCH_SMMUL, MASK_SMMUL) +DECLARE_INSN(smmul_u, MATCH_SMMUL_U, MASK_SMMUL_U) +DECLARE_INSN(smmwb, MATCH_SMMWB, MASK_SMMWB) +DECLARE_INSN(smmwb_u, MATCH_SMMWB_U, MASK_SMMWB_U) +DECLARE_INSN(smmwt, MATCH_SMMWT, MASK_SMMWT) +DECLARE_INSN(smmwt_u, MATCH_SMMWT_U, MASK_SMMWT_U) +DECLARE_INSN(smslda, MATCH_SMSLDA, MASK_SMSLDA) +DECLARE_INSN(smslxda, MATCH_SMSLXDA, MASK_SMSLXDA) +DECLARE_INSN(smsr64, MATCH_SMSR64, MASK_SMSR64) +DECLARE_INSN(smtt16, MATCH_SMTT16, MASK_SMTT16) +DECLARE_INSN(smtt32, MATCH_SMTT32, MASK_SMTT32) +DECLARE_INSN(smul16, MATCH_SMUL16, MASK_SMUL16) +DECLARE_INSN(smul8, MATCH_SMUL8, MASK_SMUL8) +DECLARE_INSN(smulx16, MATCH_SMULX16, MASK_SMULX16) +DECLARE_INSN(smulx8, MATCH_SMULX8, MASK_SMULX8) +DECLARE_INSN(smxds, MATCH_SMXDS, MASK_SMXDS) +DECLARE_INSN(smxds32, MATCH_SMXDS32, MASK_SMXDS32) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(sra16, MATCH_SRA16, MASK_SRA16) +DECLARE_INSN(sra16_u, MATCH_SRA16_U, MASK_SRA16_U) +DECLARE_INSN(sra32, MATCH_SRA32, MASK_SRA32) +DECLARE_INSN(sra32_u, MATCH_SRA32_U, MASK_SRA32_U) +DECLARE_INSN(sra8, MATCH_SRA8, MASK_SRA8) +DECLARE_INSN(sra8_u, MATCH_SRA8_U, MASK_SRA8_U) +DECLARE_INSN(sra_u, MATCH_SRA_U, MASK_SRA_U) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(srai16, MATCH_SRAI16, MASK_SRAI16) +DECLARE_INSN(srai16_u, MATCH_SRAI16_U, MASK_SRAI16_U) +DECLARE_INSN(srai32, MATCH_SRAI32, MASK_SRAI32) +DECLARE_INSN(srai32_u, MATCH_SRAI32_U, MASK_SRAI32_U) +DECLARE_INSN(srai8, MATCH_SRAI8, MASK_SRAI8) +DECLARE_INSN(srai8_u, MATCH_SRAI8_U, MASK_SRAI8_U) +DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) +DECLARE_INSN(srai_u, MATCH_SRAI_U, MASK_SRAI_U) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(sraiw_u, MATCH_SRAIW_U, MASK_SRAIW_U) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(srl16, MATCH_SRL16, MASK_SRL16) +DECLARE_INSN(srl16_u, MATCH_SRL16_U, MASK_SRL16_U) +DECLARE_INSN(srl32, MATCH_SRL32, MASK_SRL32) +DECLARE_INSN(srl32_u, MATCH_SRL32_U, MASK_SRL32_U) +DECLARE_INSN(srl8, MATCH_SRL8, MASK_SRL8) +DECLARE_INSN(srl8_u, MATCH_SRL8_U, MASK_SRL8_U) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srli16, MATCH_SRLI16, MASK_SRLI16) +DECLARE_INSN(srli16_u, MATCH_SRLI16_U, MASK_SRLI16_U) +DECLARE_INSN(srli32, MATCH_SRLI32, MASK_SRLI32) +DECLARE_INSN(srli32_u, MATCH_SRLI32_U, MASK_SRLI32_U) +DECLARE_INSN(srli8, MATCH_SRLI8, MASK_SRLI8) +DECLARE_INSN(srli8_u, MATCH_SRLI8_U, MASK_SRLI8_U) +DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sro, MATCH_SRO, MASK_SRO) +DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI) +DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW) +DECLARE_INSN(srow, MATCH_SROW, MASK_SROW) +DECLARE_INSN(stas16, MATCH_STAS16, MASK_STAS16) +DECLARE_INSN(stas32, MATCH_STAS32, MASK_STAS32) +DECLARE_INSN(stsa16, MATCH_STSA16, MASK_STSA16) +DECLARE_INSN(stsa32, MATCH_STSA32, MASK_STSA32) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sub16, MATCH_SUB16, MASK_SUB16) +DECLARE_INSN(sub32, MATCH_SUB32, MASK_SUB32) +DECLARE_INSN(sub64, MATCH_SUB64, MASK_SUB64) +DECLARE_INSN(sub8, MATCH_SUB8, MASK_SUB8) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sunpkd810, MATCH_SUNPKD810, MASK_SUNPKD810) +DECLARE_INSN(sunpkd820, MATCH_SUNPKD820, MASK_SUNPKD820) +DECLARE_INSN(sunpkd830, MATCH_SUNPKD830, MASK_SUNPKD830) +DECLARE_INSN(sunpkd831, MATCH_SUNPKD831, MASK_SUNPKD831) +DECLARE_INSN(sunpkd832, MATCH_SUNPKD832, MASK_SUNPKD832) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(uclip16, MATCH_UCLIP16, MASK_UCLIP16) +DECLARE_INSN(uclip32, MATCH_UCLIP32, MASK_UCLIP32) +DECLARE_INSN(uclip8, MATCH_UCLIP8, MASK_UCLIP8) +DECLARE_INSN(ucmple16, MATCH_UCMPLE16, MASK_UCMPLE16) +DECLARE_INSN(ucmple8, MATCH_UCMPLE8, MASK_UCMPLE8) +DECLARE_INSN(ucmplt16, MATCH_UCMPLT16, MASK_UCMPLT16) +DECLARE_INSN(ucmplt8, MATCH_UCMPLT8, MASK_UCMPLT8) +DECLARE_INSN(ukadd16, MATCH_UKADD16, MASK_UKADD16) +DECLARE_INSN(ukadd32, MATCH_UKADD32, MASK_UKADD32) +DECLARE_INSN(ukadd64, MATCH_UKADD64, MASK_UKADD64) +DECLARE_INSN(ukadd8, MATCH_UKADD8, MASK_UKADD8) +DECLARE_INSN(ukaddh, MATCH_UKADDH, MASK_UKADDH) +DECLARE_INSN(ukaddw, MATCH_UKADDW, MASK_UKADDW) +DECLARE_INSN(ukcras16, MATCH_UKCRAS16, MASK_UKCRAS16) +DECLARE_INSN(ukcras32, MATCH_UKCRAS32, MASK_UKCRAS32) +DECLARE_INSN(ukcrsa16, MATCH_UKCRSA16, MASK_UKCRSA16) +DECLARE_INSN(ukcrsa32, MATCH_UKCRSA32, MASK_UKCRSA32) +DECLARE_INSN(ukmar64, MATCH_UKMAR64, MASK_UKMAR64) +DECLARE_INSN(ukmsr64, MATCH_UKMSR64, MASK_UKMSR64) +DECLARE_INSN(ukstas16, MATCH_UKSTAS16, MASK_UKSTAS16) +DECLARE_INSN(ukstas32, MATCH_UKSTAS32, MASK_UKSTAS32) +DECLARE_INSN(ukstsa16, MATCH_UKSTSA16, MASK_UKSTSA16) +DECLARE_INSN(ukstsa32, MATCH_UKSTSA32, MASK_UKSTSA32) +DECLARE_INSN(uksub16, MATCH_UKSUB16, MASK_UKSUB16) +DECLARE_INSN(uksub32, MATCH_UKSUB32, MASK_UKSUB32) +DECLARE_INSN(uksub64, MATCH_UKSUB64, MASK_UKSUB64) +DECLARE_INSN(uksub8, MATCH_UKSUB8, MASK_UKSUB8) +DECLARE_INSN(uksubh, MATCH_UKSUBH, MASK_UKSUBH) +DECLARE_INSN(uksubw, MATCH_UKSUBW, MASK_UKSUBW) +DECLARE_INSN(umaqa, MATCH_UMAQA, MASK_UMAQA) +DECLARE_INSN(umar64, MATCH_UMAR64, MASK_UMAR64) +DECLARE_INSN(umax16, MATCH_UMAX16, MASK_UMAX16) +DECLARE_INSN(umax32, MATCH_UMAX32, MASK_UMAX32) +DECLARE_INSN(umax8, MATCH_UMAX8, MASK_UMAX8) +DECLARE_INSN(umin16, MATCH_UMIN16, MASK_UMIN16) +DECLARE_INSN(umin32, MATCH_UMIN32, MASK_UMIN32) +DECLARE_INSN(umin8, MATCH_UMIN8, MASK_UMIN8) +DECLARE_INSN(umsr64, MATCH_UMSR64, MASK_UMSR64) +DECLARE_INSN(umul16, MATCH_UMUL16, MASK_UMUL16) +DECLARE_INSN(umul8, MATCH_UMUL8, MASK_UMUL8) +DECLARE_INSN(umulx16, MATCH_UMULX16, MASK_UMULX16) +DECLARE_INSN(umulx8, MATCH_UMULX8, MASK_UMULX8) +DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL) +DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI) +DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW) +DECLARE_INSN(uradd16, MATCH_URADD16, MASK_URADD16) +DECLARE_INSN(uradd32, MATCH_URADD32, MASK_URADD32) +DECLARE_INSN(uradd64, MATCH_URADD64, MASK_URADD64) +DECLARE_INSN(uradd8, MATCH_URADD8, MASK_URADD8) +DECLARE_INSN(uraddw, MATCH_URADDW, MASK_URADDW) +DECLARE_INSN(urcras16, MATCH_URCRAS16, MASK_URCRAS16) +DECLARE_INSN(urcras32, MATCH_URCRAS32, MASK_URCRAS32) +DECLARE_INSN(urcrsa16, MATCH_URCRSA16, MASK_URCRSA16) +DECLARE_INSN(urcrsa32, MATCH_URCRSA32, MASK_URCRSA32) +DECLARE_INSN(urstas16, MATCH_URSTAS16, MASK_URSTAS16) +DECLARE_INSN(urstas32, MATCH_URSTAS32, MASK_URSTAS32) +DECLARE_INSN(urstsa16, MATCH_URSTSA16, MASK_URSTSA16) +DECLARE_INSN(urstsa32, MATCH_URSTSA32, MASK_URSTSA32) +DECLARE_INSN(ursub16, MATCH_URSUB16, MASK_URSUB16) +DECLARE_INSN(ursub32, MATCH_URSUB32, MASK_URSUB32) +DECLARE_INSN(ursub64, MATCH_URSUB64, MASK_URSUB64) +DECLARE_INSN(ursub8, MATCH_URSUB8, MASK_URSUB8) +DECLARE_INSN(ursubw, MATCH_URSUBW, MASK_URSUBW) +DECLARE_INSN(vaadd_vv, MATCH_VAADD_VV, MASK_VAADD_VV) +DECLARE_INSN(vaadd_vx, MATCH_VAADD_VX, MASK_VAADD_VX) +DECLARE_INSN(vaaddu_vv, MATCH_VAADDU_VV, MASK_VAADDU_VV) +DECLARE_INSN(vaaddu_vx, MATCH_VAADDU_VX, MASK_VAADDU_VX) +DECLARE_INSN(vadc_vim, MATCH_VADC_VIM, MASK_VADC_VIM) +DECLARE_INSN(vadc_vvm, MATCH_VADC_VVM, MASK_VADC_VVM) +DECLARE_INSN(vadc_vxm, MATCH_VADC_VXM, MASK_VADC_VXM) +DECLARE_INSN(vadd_vi, MATCH_VADD_VI, MASK_VADD_VI) +DECLARE_INSN(vadd_vv, MATCH_VADD_VV, MASK_VADD_VV) +DECLARE_INSN(vadd_vx, MATCH_VADD_VX, MASK_VADD_VX) +DECLARE_INSN(vamoaddei16_v, MATCH_VAMOADDEI16_V, MASK_VAMOADDEI16_V) +DECLARE_INSN(vamoaddei32_v, MATCH_VAMOADDEI32_V, MASK_VAMOADDEI32_V) +DECLARE_INSN(vamoaddei64_v, MATCH_VAMOADDEI64_V, MASK_VAMOADDEI64_V) +DECLARE_INSN(vamoaddei8_v, MATCH_VAMOADDEI8_V, MASK_VAMOADDEI8_V) +DECLARE_INSN(vamoandei16_v, MATCH_VAMOANDEI16_V, MASK_VAMOANDEI16_V) +DECLARE_INSN(vamoandei32_v, MATCH_VAMOANDEI32_V, MASK_VAMOANDEI32_V) +DECLARE_INSN(vamoandei64_v, MATCH_VAMOANDEI64_V, MASK_VAMOANDEI64_V) +DECLARE_INSN(vamoandei8_v, MATCH_VAMOANDEI8_V, MASK_VAMOANDEI8_V) +DECLARE_INSN(vamomaxei16_v, MATCH_VAMOMAXEI16_V, MASK_VAMOMAXEI16_V) +DECLARE_INSN(vamomaxei32_v, MATCH_VAMOMAXEI32_V, MASK_VAMOMAXEI32_V) +DECLARE_INSN(vamomaxei64_v, MATCH_VAMOMAXEI64_V, MASK_VAMOMAXEI64_V) +DECLARE_INSN(vamomaxei8_v, MATCH_VAMOMAXEI8_V, MASK_VAMOMAXEI8_V) +DECLARE_INSN(vamomaxuei16_v, MATCH_VAMOMAXUEI16_V, MASK_VAMOMAXUEI16_V) +DECLARE_INSN(vamomaxuei32_v, MATCH_VAMOMAXUEI32_V, MASK_VAMOMAXUEI32_V) +DECLARE_INSN(vamomaxuei64_v, MATCH_VAMOMAXUEI64_V, MASK_VAMOMAXUEI64_V) +DECLARE_INSN(vamomaxuei8_v, MATCH_VAMOMAXUEI8_V, MASK_VAMOMAXUEI8_V) +DECLARE_INSN(vamominei16_v, MATCH_VAMOMINEI16_V, MASK_VAMOMINEI16_V) +DECLARE_INSN(vamominei32_v, MATCH_VAMOMINEI32_V, MASK_VAMOMINEI32_V) +DECLARE_INSN(vamominei64_v, MATCH_VAMOMINEI64_V, MASK_VAMOMINEI64_V) +DECLARE_INSN(vamominei8_v, MATCH_VAMOMINEI8_V, MASK_VAMOMINEI8_V) +DECLARE_INSN(vamominuei16_v, MATCH_VAMOMINUEI16_V, MASK_VAMOMINUEI16_V) +DECLARE_INSN(vamominuei32_v, MATCH_VAMOMINUEI32_V, MASK_VAMOMINUEI32_V) +DECLARE_INSN(vamominuei64_v, MATCH_VAMOMINUEI64_V, MASK_VAMOMINUEI64_V) +DECLARE_INSN(vamominuei8_v, MATCH_VAMOMINUEI8_V, MASK_VAMOMINUEI8_V) +DECLARE_INSN(vamoorei16_v, MATCH_VAMOOREI16_V, MASK_VAMOOREI16_V) +DECLARE_INSN(vamoorei32_v, MATCH_VAMOOREI32_V, MASK_VAMOOREI32_V) +DECLARE_INSN(vamoorei64_v, MATCH_VAMOOREI64_V, MASK_VAMOOREI64_V) +DECLARE_INSN(vamoorei8_v, MATCH_VAMOOREI8_V, MASK_VAMOOREI8_V) +DECLARE_INSN(vamoswapei16_v, MATCH_VAMOSWAPEI16_V, MASK_VAMOSWAPEI16_V) +DECLARE_INSN(vamoswapei32_v, MATCH_VAMOSWAPEI32_V, MASK_VAMOSWAPEI32_V) +DECLARE_INSN(vamoswapei64_v, MATCH_VAMOSWAPEI64_V, MASK_VAMOSWAPEI64_V) +DECLARE_INSN(vamoswapei8_v, MATCH_VAMOSWAPEI8_V, MASK_VAMOSWAPEI8_V) +DECLARE_INSN(vamoxorei16_v, MATCH_VAMOXOREI16_V, MASK_VAMOXOREI16_V) +DECLARE_INSN(vamoxorei32_v, MATCH_VAMOXOREI32_V, MASK_VAMOXOREI32_V) +DECLARE_INSN(vamoxorei64_v, MATCH_VAMOXOREI64_V, MASK_VAMOXOREI64_V) +DECLARE_INSN(vamoxorei8_v, MATCH_VAMOXOREI8_V, MASK_VAMOXOREI8_V) +DECLARE_INSN(vand_vi, MATCH_VAND_VI, MASK_VAND_VI) +DECLARE_INSN(vand_vv, MATCH_VAND_VV, MASK_VAND_VV) +DECLARE_INSN(vand_vx, MATCH_VAND_VX, MASK_VAND_VX) +DECLARE_INSN(vasub_vv, MATCH_VASUB_VV, MASK_VASUB_VV) +DECLARE_INSN(vasub_vx, MATCH_VASUB_VX, MASK_VASUB_VX) +DECLARE_INSN(vasubu_vv, MATCH_VASUBU_VV, MASK_VASUBU_VV) +DECLARE_INSN(vasubu_vx, MATCH_VASUBU_VX, MASK_VASUBU_VX) +DECLARE_INSN(vcompress_vm, MATCH_VCOMPRESS_VM, MASK_VCOMPRESS_VM) +DECLARE_INSN(vcpop_m, MATCH_VCPOP_M, MASK_VCPOP_M) +DECLARE_INSN(vdiv_vv, MATCH_VDIV_VV, MASK_VDIV_VV) +DECLARE_INSN(vdiv_vx, MATCH_VDIV_VX, MASK_VDIV_VX) +DECLARE_INSN(vdivu_vv, MATCH_VDIVU_VV, MASK_VDIVU_VV) +DECLARE_INSN(vdivu_vx, MATCH_VDIVU_VX, MASK_VDIVU_VX) +DECLARE_INSN(vfadd_vf, MATCH_VFADD_VF, MASK_VFADD_VF) +DECLARE_INSN(vfadd_vv, MATCH_VFADD_VV, MASK_VFADD_VV) +DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V) +DECLARE_INSN(vfcvt_f_x_v, MATCH_VFCVT_F_X_V, MASK_VFCVT_F_X_V) +DECLARE_INSN(vfcvt_f_xu_v, MATCH_VFCVT_F_XU_V, MASK_VFCVT_F_XU_V) +DECLARE_INSN(vfcvt_rtz_x_f_v, MATCH_VFCVT_RTZ_X_F_V, MASK_VFCVT_RTZ_X_F_V) +DECLARE_INSN(vfcvt_rtz_xu_f_v, MATCH_VFCVT_RTZ_XU_F_V, MASK_VFCVT_RTZ_XU_F_V) +DECLARE_INSN(vfcvt_x_f_v, MATCH_VFCVT_X_F_V, MASK_VFCVT_X_F_V) +DECLARE_INSN(vfcvt_xu_f_v, MATCH_VFCVT_XU_F_V, MASK_VFCVT_XU_F_V) +DECLARE_INSN(vfdiv_vf, MATCH_VFDIV_VF, MASK_VFDIV_VF) +DECLARE_INSN(vfdiv_vv, MATCH_VFDIV_VV, MASK_VFDIV_VV) +DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M) +DECLARE_INSN(vfmacc_vf, MATCH_VFMACC_VF, MASK_VFMACC_VF) +DECLARE_INSN(vfmacc_vv, MATCH_VFMACC_VV, MASK_VFMACC_VV) +DECLARE_INSN(vfmadd_vf, MATCH_VFMADD_VF, MASK_VFMADD_VF) +DECLARE_INSN(vfmadd_vv, MATCH_VFMADD_VV, MASK_VFMADD_VV) +DECLARE_INSN(vfmax_vf, MATCH_VFMAX_VF, MASK_VFMAX_VF) +DECLARE_INSN(vfmax_vv, MATCH_VFMAX_VV, MASK_VFMAX_VV) +DECLARE_INSN(vfmerge_vfm, MATCH_VFMERGE_VFM, MASK_VFMERGE_VFM) +DECLARE_INSN(vfmin_vf, MATCH_VFMIN_VF, MASK_VFMIN_VF) +DECLARE_INSN(vfmin_vv, MATCH_VFMIN_VV, MASK_VFMIN_VV) +DECLARE_INSN(vfmsac_vf, MATCH_VFMSAC_VF, MASK_VFMSAC_VF) +DECLARE_INSN(vfmsac_vv, MATCH_VFMSAC_VV, MASK_VFMSAC_VV) +DECLARE_INSN(vfmsub_vf, MATCH_VFMSUB_VF, MASK_VFMSUB_VF) +DECLARE_INSN(vfmsub_vv, MATCH_VFMSUB_VV, MASK_VFMSUB_VV) +DECLARE_INSN(vfmul_vf, MATCH_VFMUL_VF, MASK_VFMUL_VF) +DECLARE_INSN(vfmul_vv, MATCH_VFMUL_VV, MASK_VFMUL_VV) +DECLARE_INSN(vfmv_f_s, MATCH_VFMV_F_S, MASK_VFMV_F_S) +DECLARE_INSN(vfmv_s_f, MATCH_VFMV_S_F, MASK_VFMV_S_F) +DECLARE_INSN(vfmv_v_f, MATCH_VFMV_V_F, MASK_VFMV_V_F) +DECLARE_INSN(vfncvt_f_f_w, MATCH_VFNCVT_F_F_W, MASK_VFNCVT_F_F_W) +DECLARE_INSN(vfncvt_f_x_w, MATCH_VFNCVT_F_X_W, MASK_VFNCVT_F_X_W) +DECLARE_INSN(vfncvt_f_xu_w, MATCH_VFNCVT_F_XU_W, MASK_VFNCVT_F_XU_W) +DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W) +DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W) +DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W) +DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W) +DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W) +DECLARE_INSN(vfnmacc_vf, MATCH_VFNMACC_VF, MASK_VFNMACC_VF) +DECLARE_INSN(vfnmacc_vv, MATCH_VFNMACC_VV, MASK_VFNMACC_VV) +DECLARE_INSN(vfnmadd_vf, MATCH_VFNMADD_VF, MASK_VFNMADD_VF) +DECLARE_INSN(vfnmadd_vv, MATCH_VFNMADD_VV, MASK_VFNMADD_VV) +DECLARE_INSN(vfnmsac_vf, MATCH_VFNMSAC_VF, MASK_VFNMSAC_VF) +DECLARE_INSN(vfnmsac_vv, MATCH_VFNMSAC_VV, MASK_VFNMSAC_VV) +DECLARE_INSN(vfnmsub_vf, MATCH_VFNMSUB_VF, MASK_VFNMSUB_VF) +DECLARE_INSN(vfnmsub_vv, MATCH_VFNMSUB_VV, MASK_VFNMSUB_VV) +DECLARE_INSN(vfrdiv_vf, MATCH_VFRDIV_VF, MASK_VFRDIV_VF) +DECLARE_INSN(vfrec7_v, MATCH_VFREC7_V, MASK_VFREC7_V) +DECLARE_INSN(vfredmax_vs, MATCH_VFREDMAX_VS, MASK_VFREDMAX_VS) +DECLARE_INSN(vfredmin_vs, MATCH_VFREDMIN_VS, MASK_VFREDMIN_VS) +DECLARE_INSN(vfredosum_vs, MATCH_VFREDOSUM_VS, MASK_VFREDOSUM_VS) +DECLARE_INSN(vfredusum_vs, MATCH_VFREDUSUM_VS, MASK_VFREDUSUM_VS) +DECLARE_INSN(vfrsqrt7_v, MATCH_VFRSQRT7_V, MASK_VFRSQRT7_V) +DECLARE_INSN(vfrsub_vf, MATCH_VFRSUB_VF, MASK_VFRSUB_VF) +DECLARE_INSN(vfsgnj_vf, MATCH_VFSGNJ_VF, MASK_VFSGNJ_VF) +DECLARE_INSN(vfsgnj_vv, MATCH_VFSGNJ_VV, MASK_VFSGNJ_VV) +DECLARE_INSN(vfsgnjn_vf, MATCH_VFSGNJN_VF, MASK_VFSGNJN_VF) +DECLARE_INSN(vfsgnjn_vv, MATCH_VFSGNJN_VV, MASK_VFSGNJN_VV) +DECLARE_INSN(vfsgnjx_vf, MATCH_VFSGNJX_VF, MASK_VFSGNJX_VF) +DECLARE_INSN(vfsgnjx_vv, MATCH_VFSGNJX_VV, MASK_VFSGNJX_VV) +DECLARE_INSN(vfslide1down_vf, MATCH_VFSLIDE1DOWN_VF, MASK_VFSLIDE1DOWN_VF) +DECLARE_INSN(vfslide1up_vf, MATCH_VFSLIDE1UP_VF, MASK_VFSLIDE1UP_VF) +DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V) +DECLARE_INSN(vfsub_vf, MATCH_VFSUB_VF, MASK_VFSUB_VF) +DECLARE_INSN(vfsub_vv, MATCH_VFSUB_VV, MASK_VFSUB_VV) +DECLARE_INSN(vfwadd_vf, MATCH_VFWADD_VF, MASK_VFWADD_VF) +DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV) +DECLARE_INSN(vfwadd_wf, MATCH_VFWADD_WF, MASK_VFWADD_WF) +DECLARE_INSN(vfwadd_wv, MATCH_VFWADD_WV, MASK_VFWADD_WV) +DECLARE_INSN(vfwcvt_f_f_v, MATCH_VFWCVT_F_F_V, MASK_VFWCVT_F_F_V) +DECLARE_INSN(vfwcvt_f_x_v, MATCH_VFWCVT_F_X_V, MASK_VFWCVT_F_X_V) +DECLARE_INSN(vfwcvt_f_xu_v, MATCH_VFWCVT_F_XU_V, MASK_VFWCVT_F_XU_V) +DECLARE_INSN(vfwcvt_rtz_x_f_v, MATCH_VFWCVT_RTZ_X_F_V, MASK_VFWCVT_RTZ_X_F_V) +DECLARE_INSN(vfwcvt_rtz_xu_f_v, MATCH_VFWCVT_RTZ_XU_F_V, MASK_VFWCVT_RTZ_XU_F_V) +DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V) +DECLARE_INSN(vfwcvt_xu_f_v, MATCH_VFWCVT_XU_F_V, MASK_VFWCVT_XU_F_V) +DECLARE_INSN(vfwmacc_vf, MATCH_VFWMACC_VF, MASK_VFWMACC_VF) +DECLARE_INSN(vfwmacc_vv, MATCH_VFWMACC_VV, MASK_VFWMACC_VV) +DECLARE_INSN(vfwmsac_vf, MATCH_VFWMSAC_VF, MASK_VFWMSAC_VF) +DECLARE_INSN(vfwmsac_vv, MATCH_VFWMSAC_VV, MASK_VFWMSAC_VV) +DECLARE_INSN(vfwmul_vf, MATCH_VFWMUL_VF, MASK_VFWMUL_VF) +DECLARE_INSN(vfwmul_vv, MATCH_VFWMUL_VV, MASK_VFWMUL_VV) +DECLARE_INSN(vfwnmacc_vf, MATCH_VFWNMACC_VF, MASK_VFWNMACC_VF) +DECLARE_INSN(vfwnmacc_vv, MATCH_VFWNMACC_VV, MASK_VFWNMACC_VV) +DECLARE_INSN(vfwnmsac_vf, MATCH_VFWNMSAC_VF, MASK_VFWNMSAC_VF) +DECLARE_INSN(vfwnmsac_vv, MATCH_VFWNMSAC_VV, MASK_VFWNMSAC_VV) +DECLARE_INSN(vfwredosum_vs, MATCH_VFWREDOSUM_VS, MASK_VFWREDOSUM_VS) +DECLARE_INSN(vfwredusum_vs, MATCH_VFWREDUSUM_VS, MASK_VFWREDUSUM_VS) +DECLARE_INSN(vfwsub_vf, MATCH_VFWSUB_VF, MASK_VFWSUB_VF) +DECLARE_INSN(vfwsub_vv, MATCH_VFWSUB_VV, MASK_VFWSUB_VV) +DECLARE_INSN(vfwsub_wf, MATCH_VFWSUB_WF, MASK_VFWSUB_WF) +DECLARE_INSN(vfwsub_wv, MATCH_VFWSUB_WV, MASK_VFWSUB_WV) +DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V) +DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M) +DECLARE_INSN(vl1re16_v, MATCH_VL1RE16_V, MASK_VL1RE16_V) +DECLARE_INSN(vl1re32_v, MATCH_VL1RE32_V, MASK_VL1RE32_V) +DECLARE_INSN(vl1re64_v, MATCH_VL1RE64_V, MASK_VL1RE64_V) +DECLARE_INSN(vl1re8_v, MATCH_VL1RE8_V, MASK_VL1RE8_V) +DECLARE_INSN(vl2re16_v, MATCH_VL2RE16_V, MASK_VL2RE16_V) +DECLARE_INSN(vl2re32_v, MATCH_VL2RE32_V, MASK_VL2RE32_V) +DECLARE_INSN(vl2re64_v, MATCH_VL2RE64_V, MASK_VL2RE64_V) +DECLARE_INSN(vl2re8_v, MATCH_VL2RE8_V, MASK_VL2RE8_V) +DECLARE_INSN(vl4re16_v, MATCH_VL4RE16_V, MASK_VL4RE16_V) +DECLARE_INSN(vl4re32_v, MATCH_VL4RE32_V, MASK_VL4RE32_V) +DECLARE_INSN(vl4re64_v, MATCH_VL4RE64_V, MASK_VL4RE64_V) +DECLARE_INSN(vl4re8_v, MATCH_VL4RE8_V, MASK_VL4RE8_V) +DECLARE_INSN(vl8re16_v, MATCH_VL8RE16_V, MASK_VL8RE16_V) +DECLARE_INSN(vl8re32_v, MATCH_VL8RE32_V, MASK_VL8RE32_V) +DECLARE_INSN(vl8re64_v, MATCH_VL8RE64_V, MASK_VL8RE64_V) +DECLARE_INSN(vl8re8_v, MATCH_VL8RE8_V, MASK_VL8RE8_V) +DECLARE_INSN(vle1024_v, MATCH_VLE1024_V, MASK_VLE1024_V) +DECLARE_INSN(vle1024ff_v, MATCH_VLE1024FF_V, MASK_VLE1024FF_V) +DECLARE_INSN(vle128_v, MATCH_VLE128_V, MASK_VLE128_V) +DECLARE_INSN(vle128ff_v, MATCH_VLE128FF_V, MASK_VLE128FF_V) +DECLARE_INSN(vle16_v, MATCH_VLE16_V, MASK_VLE16_V) +DECLARE_INSN(vle16ff_v, MATCH_VLE16FF_V, MASK_VLE16FF_V) +DECLARE_INSN(vle256_v, MATCH_VLE256_V, MASK_VLE256_V) +DECLARE_INSN(vle256ff_v, MATCH_VLE256FF_V, MASK_VLE256FF_V) +DECLARE_INSN(vle32_v, MATCH_VLE32_V, MASK_VLE32_V) +DECLARE_INSN(vle32ff_v, MATCH_VLE32FF_V, MASK_VLE32FF_V) +DECLARE_INSN(vle512_v, MATCH_VLE512_V, MASK_VLE512_V) +DECLARE_INSN(vle512ff_v, MATCH_VLE512FF_V, MASK_VLE512FF_V) +DECLARE_INSN(vle64_v, MATCH_VLE64_V, MASK_VLE64_V) +DECLARE_INSN(vle64ff_v, MATCH_VLE64FF_V, MASK_VLE64FF_V) +DECLARE_INSN(vle8_v, MATCH_VLE8_V, MASK_VLE8_V) +DECLARE_INSN(vle8ff_v, MATCH_VLE8FF_V, MASK_VLE8FF_V) +DECLARE_INSN(vlm_v, MATCH_VLM_V, MASK_VLM_V) +DECLARE_INSN(vloxei1024_v, MATCH_VLOXEI1024_V, MASK_VLOXEI1024_V) +DECLARE_INSN(vloxei128_v, MATCH_VLOXEI128_V, MASK_VLOXEI128_V) +DECLARE_INSN(vloxei16_v, MATCH_VLOXEI16_V, MASK_VLOXEI16_V) +DECLARE_INSN(vloxei256_v, MATCH_VLOXEI256_V, MASK_VLOXEI256_V) +DECLARE_INSN(vloxei32_v, MATCH_VLOXEI32_V, MASK_VLOXEI32_V) +DECLARE_INSN(vloxei512_v, MATCH_VLOXEI512_V, MASK_VLOXEI512_V) +DECLARE_INSN(vloxei64_v, MATCH_VLOXEI64_V, MASK_VLOXEI64_V) +DECLARE_INSN(vloxei8_v, MATCH_VLOXEI8_V, MASK_VLOXEI8_V) +DECLARE_INSN(vlse1024_v, MATCH_VLSE1024_V, MASK_VLSE1024_V) +DECLARE_INSN(vlse128_v, MATCH_VLSE128_V, MASK_VLSE128_V) +DECLARE_INSN(vlse16_v, MATCH_VLSE16_V, MASK_VLSE16_V) +DECLARE_INSN(vlse256_v, MATCH_VLSE256_V, MASK_VLSE256_V) +DECLARE_INSN(vlse32_v, MATCH_VLSE32_V, MASK_VLSE32_V) +DECLARE_INSN(vlse512_v, MATCH_VLSE512_V, MASK_VLSE512_V) +DECLARE_INSN(vlse64_v, MATCH_VLSE64_V, MASK_VLSE64_V) +DECLARE_INSN(vlse8_v, MATCH_VLSE8_V, MASK_VLSE8_V) +DECLARE_INSN(vluxei1024_v, MATCH_VLUXEI1024_V, MASK_VLUXEI1024_V) +DECLARE_INSN(vluxei128_v, MATCH_VLUXEI128_V, MASK_VLUXEI128_V) +DECLARE_INSN(vluxei16_v, MATCH_VLUXEI16_V, MASK_VLUXEI16_V) +DECLARE_INSN(vluxei256_v, MATCH_VLUXEI256_V, MASK_VLUXEI256_V) +DECLARE_INSN(vluxei32_v, MATCH_VLUXEI32_V, MASK_VLUXEI32_V) +DECLARE_INSN(vluxei512_v, MATCH_VLUXEI512_V, MASK_VLUXEI512_V) +DECLARE_INSN(vluxei64_v, MATCH_VLUXEI64_V, MASK_VLUXEI64_V) +DECLARE_INSN(vluxei8_v, MATCH_VLUXEI8_V, MASK_VLUXEI8_V) +DECLARE_INSN(vmacc_vv, MATCH_VMACC_VV, MASK_VMACC_VV) +DECLARE_INSN(vmacc_vx, MATCH_VMACC_VX, MASK_VMACC_VX) +DECLARE_INSN(vmadc_vi, MATCH_VMADC_VI, MASK_VMADC_VI) +DECLARE_INSN(vmadc_vim, MATCH_VMADC_VIM, MASK_VMADC_VIM) +DECLARE_INSN(vmadc_vv, MATCH_VMADC_VV, MASK_VMADC_VV) +DECLARE_INSN(vmadc_vvm, MATCH_VMADC_VVM, MASK_VMADC_VVM) +DECLARE_INSN(vmadc_vx, MATCH_VMADC_VX, MASK_VMADC_VX) +DECLARE_INSN(vmadc_vxm, MATCH_VMADC_VXM, MASK_VMADC_VXM) +DECLARE_INSN(vmadd_vv, MATCH_VMADD_VV, MASK_VMADD_VV) +DECLARE_INSN(vmadd_vx, MATCH_VMADD_VX, MASK_VMADD_VX) +DECLARE_INSN(vmand_mm, MATCH_VMAND_MM, MASK_VMAND_MM) +DECLARE_INSN(vmandn_mm, MATCH_VMANDN_MM, MASK_VMANDN_MM) +DECLARE_INSN(vmax_vv, MATCH_VMAX_VV, MASK_VMAX_VV) +DECLARE_INSN(vmax_vx, MATCH_VMAX_VX, MASK_VMAX_VX) +DECLARE_INSN(vmaxu_vv, MATCH_VMAXU_VV, MASK_VMAXU_VV) +DECLARE_INSN(vmaxu_vx, MATCH_VMAXU_VX, MASK_VMAXU_VX) +DECLARE_INSN(vmerge_vim, MATCH_VMERGE_VIM, MASK_VMERGE_VIM) +DECLARE_INSN(vmerge_vvm, MATCH_VMERGE_VVM, MASK_VMERGE_VVM) +DECLARE_INSN(vmerge_vxm, MATCH_VMERGE_VXM, MASK_VMERGE_VXM) +DECLARE_INSN(vmfeq_vf, MATCH_VMFEQ_VF, MASK_VMFEQ_VF) +DECLARE_INSN(vmfeq_vv, MATCH_VMFEQ_VV, MASK_VMFEQ_VV) +DECLARE_INSN(vmfge_vf, MATCH_VMFGE_VF, MASK_VMFGE_VF) +DECLARE_INSN(vmfgt_vf, MATCH_VMFGT_VF, MASK_VMFGT_VF) +DECLARE_INSN(vmfle_vf, MATCH_VMFLE_VF, MASK_VMFLE_VF) +DECLARE_INSN(vmfle_vv, MATCH_VMFLE_VV, MASK_VMFLE_VV) +DECLARE_INSN(vmflt_vf, MATCH_VMFLT_VF, MASK_VMFLT_VF) +DECLARE_INSN(vmflt_vv, MATCH_VMFLT_VV, MASK_VMFLT_VV) +DECLARE_INSN(vmfne_vf, MATCH_VMFNE_VF, MASK_VMFNE_VF) +DECLARE_INSN(vmfne_vv, MATCH_VMFNE_VV, MASK_VMFNE_VV) +DECLARE_INSN(vmin_vv, MATCH_VMIN_VV, MASK_VMIN_VV) +DECLARE_INSN(vmin_vx, MATCH_VMIN_VX, MASK_VMIN_VX) +DECLARE_INSN(vminu_vv, MATCH_VMINU_VV, MASK_VMINU_VV) +DECLARE_INSN(vminu_vx, MATCH_VMINU_VX, MASK_VMINU_VX) +DECLARE_INSN(vmnand_mm, MATCH_VMNAND_MM, MASK_VMNAND_MM) +DECLARE_INSN(vmnor_mm, MATCH_VMNOR_MM, MASK_VMNOR_MM) +DECLARE_INSN(vmor_mm, MATCH_VMOR_MM, MASK_VMOR_MM) +DECLARE_INSN(vmorn_mm, MATCH_VMORN_MM, MASK_VMORN_MM) +DECLARE_INSN(vmsbc_vv, MATCH_VMSBC_VV, MASK_VMSBC_VV) +DECLARE_INSN(vmsbc_vvm, MATCH_VMSBC_VVM, MASK_VMSBC_VVM) +DECLARE_INSN(vmsbc_vx, MATCH_VMSBC_VX, MASK_VMSBC_VX) +DECLARE_INSN(vmsbc_vxm, MATCH_VMSBC_VXM, MASK_VMSBC_VXM) +DECLARE_INSN(vmsbf_m, MATCH_VMSBF_M, MASK_VMSBF_M) +DECLARE_INSN(vmseq_vi, MATCH_VMSEQ_VI, MASK_VMSEQ_VI) +DECLARE_INSN(vmseq_vv, MATCH_VMSEQ_VV, MASK_VMSEQ_VV) +DECLARE_INSN(vmseq_vx, MATCH_VMSEQ_VX, MASK_VMSEQ_VX) +DECLARE_INSN(vmsgt_vi, MATCH_VMSGT_VI, MASK_VMSGT_VI) +DECLARE_INSN(vmsgt_vx, MATCH_VMSGT_VX, MASK_VMSGT_VX) +DECLARE_INSN(vmsgtu_vi, MATCH_VMSGTU_VI, MASK_VMSGTU_VI) +DECLARE_INSN(vmsgtu_vx, MATCH_VMSGTU_VX, MASK_VMSGTU_VX) +DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M) +DECLARE_INSN(vmsle_vi, MATCH_VMSLE_VI, MASK_VMSLE_VI) +DECLARE_INSN(vmsle_vv, MATCH_VMSLE_VV, MASK_VMSLE_VV) +DECLARE_INSN(vmsle_vx, MATCH_VMSLE_VX, MASK_VMSLE_VX) +DECLARE_INSN(vmsleu_vi, MATCH_VMSLEU_VI, MASK_VMSLEU_VI) +DECLARE_INSN(vmsleu_vv, MATCH_VMSLEU_VV, MASK_VMSLEU_VV) +DECLARE_INSN(vmsleu_vx, MATCH_VMSLEU_VX, MASK_VMSLEU_VX) +DECLARE_INSN(vmslt_vv, MATCH_VMSLT_VV, MASK_VMSLT_VV) +DECLARE_INSN(vmslt_vx, MATCH_VMSLT_VX, MASK_VMSLT_VX) +DECLARE_INSN(vmsltu_vv, MATCH_VMSLTU_VV, MASK_VMSLTU_VV) +DECLARE_INSN(vmsltu_vx, MATCH_VMSLTU_VX, MASK_VMSLTU_VX) +DECLARE_INSN(vmsne_vi, MATCH_VMSNE_VI, MASK_VMSNE_VI) +DECLARE_INSN(vmsne_vv, MATCH_VMSNE_VV, MASK_VMSNE_VV) +DECLARE_INSN(vmsne_vx, MATCH_VMSNE_VX, MASK_VMSNE_VX) +DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M) +DECLARE_INSN(vmul_vv, MATCH_VMUL_VV, MASK_VMUL_VV) +DECLARE_INSN(vmul_vx, MATCH_VMUL_VX, MASK_VMUL_VX) +DECLARE_INSN(vmulh_vv, MATCH_VMULH_VV, MASK_VMULH_VV) +DECLARE_INSN(vmulh_vx, MATCH_VMULH_VX, MASK_VMULH_VX) +DECLARE_INSN(vmulhsu_vv, MATCH_VMULHSU_VV, MASK_VMULHSU_VV) +DECLARE_INSN(vmulhsu_vx, MATCH_VMULHSU_VX, MASK_VMULHSU_VX) +DECLARE_INSN(vmulhu_vv, MATCH_VMULHU_VV, MASK_VMULHU_VV) +DECLARE_INSN(vmulhu_vx, MATCH_VMULHU_VX, MASK_VMULHU_VX) +DECLARE_INSN(vmv1r_v, MATCH_VMV1R_V, MASK_VMV1R_V) +DECLARE_INSN(vmv2r_v, MATCH_VMV2R_V, MASK_VMV2R_V) +DECLARE_INSN(vmv4r_v, MATCH_VMV4R_V, MASK_VMV4R_V) +DECLARE_INSN(vmv8r_v, MATCH_VMV8R_V, MASK_VMV8R_V) +DECLARE_INSN(vmv_s_x, MATCH_VMV_S_X, MASK_VMV_S_X) +DECLARE_INSN(vmv_v_i, MATCH_VMV_V_I, MASK_VMV_V_I) +DECLARE_INSN(vmv_v_v, MATCH_VMV_V_V, MASK_VMV_V_V) +DECLARE_INSN(vmv_v_x, MATCH_VMV_V_X, MASK_VMV_V_X) +DECLARE_INSN(vmv_x_s, MATCH_VMV_X_S, MASK_VMV_X_S) +DECLARE_INSN(vmxnor_mm, MATCH_VMXNOR_MM, MASK_VMXNOR_MM) +DECLARE_INSN(vmxor_mm, MATCH_VMXOR_MM, MASK_VMXOR_MM) +DECLARE_INSN(vnclip_wi, MATCH_VNCLIP_WI, MASK_VNCLIP_WI) +DECLARE_INSN(vnclip_wv, MATCH_VNCLIP_WV, MASK_VNCLIP_WV) +DECLARE_INSN(vnclip_wx, MATCH_VNCLIP_WX, MASK_VNCLIP_WX) +DECLARE_INSN(vnclipu_wi, MATCH_VNCLIPU_WI, MASK_VNCLIPU_WI) +DECLARE_INSN(vnclipu_wv, MATCH_VNCLIPU_WV, MASK_VNCLIPU_WV) +DECLARE_INSN(vnclipu_wx, MATCH_VNCLIPU_WX, MASK_VNCLIPU_WX) +DECLARE_INSN(vnmsac_vv, MATCH_VNMSAC_VV, MASK_VNMSAC_VV) +DECLARE_INSN(vnmsac_vx, MATCH_VNMSAC_VX, MASK_VNMSAC_VX) +DECLARE_INSN(vnmsub_vv, MATCH_VNMSUB_VV, MASK_VNMSUB_VV) +DECLARE_INSN(vnmsub_vx, MATCH_VNMSUB_VX, MASK_VNMSUB_VX) +DECLARE_INSN(vnsra_wi, MATCH_VNSRA_WI, MASK_VNSRA_WI) +DECLARE_INSN(vnsra_wv, MATCH_VNSRA_WV, MASK_VNSRA_WV) +DECLARE_INSN(vnsra_wx, MATCH_VNSRA_WX, MASK_VNSRA_WX) +DECLARE_INSN(vnsrl_wi, MATCH_VNSRL_WI, MASK_VNSRL_WI) +DECLARE_INSN(vnsrl_wv, MATCH_VNSRL_WV, MASK_VNSRL_WV) +DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX) +DECLARE_INSN(vor_vi, MATCH_VOR_VI, MASK_VOR_VI) +DECLARE_INSN(vor_vv, MATCH_VOR_VV, MASK_VOR_VV) +DECLARE_INSN(vor_vx, MATCH_VOR_VX, MASK_VOR_VX) +DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS) +DECLARE_INSN(vredmax_vs, MATCH_VREDMAX_VS, MASK_VREDMAX_VS) +DECLARE_INSN(vredmaxu_vs, MATCH_VREDMAXU_VS, MASK_VREDMAXU_VS) +DECLARE_INSN(vredmin_vs, MATCH_VREDMIN_VS, MASK_VREDMIN_VS) +DECLARE_INSN(vredminu_vs, MATCH_VREDMINU_VS, MASK_VREDMINU_VS) +DECLARE_INSN(vredor_vs, MATCH_VREDOR_VS, MASK_VREDOR_VS) +DECLARE_INSN(vredsum_vs, MATCH_VREDSUM_VS, MASK_VREDSUM_VS) +DECLARE_INSN(vredxor_vs, MATCH_VREDXOR_VS, MASK_VREDXOR_VS) +DECLARE_INSN(vrem_vv, MATCH_VREM_VV, MASK_VREM_VV) +DECLARE_INSN(vrem_vx, MATCH_VREM_VX, MASK_VREM_VX) +DECLARE_INSN(vremu_vv, MATCH_VREMU_VV, MASK_VREMU_VV) +DECLARE_INSN(vremu_vx, MATCH_VREMU_VX, MASK_VREMU_VX) +DECLARE_INSN(vrgather_vi, MATCH_VRGATHER_VI, MASK_VRGATHER_VI) +DECLARE_INSN(vrgather_vv, MATCH_VRGATHER_VV, MASK_VRGATHER_VV) +DECLARE_INSN(vrgather_vx, MATCH_VRGATHER_VX, MASK_VRGATHER_VX) +DECLARE_INSN(vrgatherei16_vv, MATCH_VRGATHEREI16_VV, MASK_VRGATHEREI16_VV) +DECLARE_INSN(vrsub_vi, MATCH_VRSUB_VI, MASK_VRSUB_VI) +DECLARE_INSN(vrsub_vx, MATCH_VRSUB_VX, MASK_VRSUB_VX) +DECLARE_INSN(vs1r_v, MATCH_VS1R_V, MASK_VS1R_V) +DECLARE_INSN(vs2r_v, MATCH_VS2R_V, MASK_VS2R_V) +DECLARE_INSN(vs4r_v, MATCH_VS4R_V, MASK_VS4R_V) +DECLARE_INSN(vs8r_v, MATCH_VS8R_V, MASK_VS8R_V) +DECLARE_INSN(vsadd_vi, MATCH_VSADD_VI, MASK_VSADD_VI) +DECLARE_INSN(vsadd_vv, MATCH_VSADD_VV, MASK_VSADD_VV) +DECLARE_INSN(vsadd_vx, MATCH_VSADD_VX, MASK_VSADD_VX) +DECLARE_INSN(vsaddu_vi, MATCH_VSADDU_VI, MASK_VSADDU_VI) +DECLARE_INSN(vsaddu_vv, MATCH_VSADDU_VV, MASK_VSADDU_VV) +DECLARE_INSN(vsaddu_vx, MATCH_VSADDU_VX, MASK_VSADDU_VX) +DECLARE_INSN(vsbc_vvm, MATCH_VSBC_VVM, MASK_VSBC_VVM) +DECLARE_INSN(vsbc_vxm, MATCH_VSBC_VXM, MASK_VSBC_VXM) +DECLARE_INSN(vse1024_v, MATCH_VSE1024_V, MASK_VSE1024_V) +DECLARE_INSN(vse128_v, MATCH_VSE128_V, MASK_VSE128_V) +DECLARE_INSN(vse16_v, MATCH_VSE16_V, MASK_VSE16_V) +DECLARE_INSN(vse256_v, MATCH_VSE256_V, MASK_VSE256_V) +DECLARE_INSN(vse32_v, MATCH_VSE32_V, MASK_VSE32_V) +DECLARE_INSN(vse512_v, MATCH_VSE512_V, MASK_VSE512_V) +DECLARE_INSN(vse64_v, MATCH_VSE64_V, MASK_VSE64_V) +DECLARE_INSN(vse8_v, MATCH_VSE8_V, MASK_VSE8_V) +DECLARE_INSN(vsetivli, MATCH_VSETIVLI, MASK_VSETIVLI) +DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL) +DECLARE_INSN(vsetvli, MATCH_VSETVLI, MASK_VSETVLI) +DECLARE_INSN(vsext_vf2, MATCH_VSEXT_VF2, MASK_VSEXT_VF2) +DECLARE_INSN(vsext_vf4, MATCH_VSEXT_VF4, MASK_VSEXT_VF4) +DECLARE_INSN(vsext_vf8, MATCH_VSEXT_VF8, MASK_VSEXT_VF8) +DECLARE_INSN(vslide1down_vx, MATCH_VSLIDE1DOWN_VX, MASK_VSLIDE1DOWN_VX) +DECLARE_INSN(vslide1up_vx, MATCH_VSLIDE1UP_VX, MASK_VSLIDE1UP_VX) +DECLARE_INSN(vslidedown_vi, MATCH_VSLIDEDOWN_VI, MASK_VSLIDEDOWN_VI) +DECLARE_INSN(vslidedown_vx, MATCH_VSLIDEDOWN_VX, MASK_VSLIDEDOWN_VX) +DECLARE_INSN(vslideup_vi, MATCH_VSLIDEUP_VI, MASK_VSLIDEUP_VI) +DECLARE_INSN(vslideup_vx, MATCH_VSLIDEUP_VX, MASK_VSLIDEUP_VX) +DECLARE_INSN(vsll_vi, MATCH_VSLL_VI, MASK_VSLL_VI) +DECLARE_INSN(vsll_vv, MATCH_VSLL_VV, MASK_VSLL_VV) +DECLARE_INSN(vsll_vx, MATCH_VSLL_VX, MASK_VSLL_VX) +DECLARE_INSN(vsm_v, MATCH_VSM_V, MASK_VSM_V) +DECLARE_INSN(vsmul_vv, MATCH_VSMUL_VV, MASK_VSMUL_VV) +DECLARE_INSN(vsmul_vx, MATCH_VSMUL_VX, MASK_VSMUL_VX) +DECLARE_INSN(vsoxei1024_v, MATCH_VSOXEI1024_V, MASK_VSOXEI1024_V) +DECLARE_INSN(vsoxei128_v, MATCH_VSOXEI128_V, MASK_VSOXEI128_V) +DECLARE_INSN(vsoxei16_v, MATCH_VSOXEI16_V, MASK_VSOXEI16_V) +DECLARE_INSN(vsoxei256_v, MATCH_VSOXEI256_V, MASK_VSOXEI256_V) +DECLARE_INSN(vsoxei32_v, MATCH_VSOXEI32_V, MASK_VSOXEI32_V) +DECLARE_INSN(vsoxei512_v, MATCH_VSOXEI512_V, MASK_VSOXEI512_V) +DECLARE_INSN(vsoxei64_v, MATCH_VSOXEI64_V, MASK_VSOXEI64_V) +DECLARE_INSN(vsoxei8_v, MATCH_VSOXEI8_V, MASK_VSOXEI8_V) +DECLARE_INSN(vsra_vi, MATCH_VSRA_VI, MASK_VSRA_VI) +DECLARE_INSN(vsra_vv, MATCH_VSRA_VV, MASK_VSRA_VV) +DECLARE_INSN(vsra_vx, MATCH_VSRA_VX, MASK_VSRA_VX) +DECLARE_INSN(vsrl_vi, MATCH_VSRL_VI, MASK_VSRL_VI) +DECLARE_INSN(vsrl_vv, MATCH_VSRL_VV, MASK_VSRL_VV) +DECLARE_INSN(vsrl_vx, MATCH_VSRL_VX, MASK_VSRL_VX) +DECLARE_INSN(vsse1024_v, MATCH_VSSE1024_V, MASK_VSSE1024_V) +DECLARE_INSN(vsse128_v, MATCH_VSSE128_V, MASK_VSSE128_V) +DECLARE_INSN(vsse16_v, MATCH_VSSE16_V, MASK_VSSE16_V) +DECLARE_INSN(vsse256_v, MATCH_VSSE256_V, MASK_VSSE256_V) +DECLARE_INSN(vsse32_v, MATCH_VSSE32_V, MASK_VSSE32_V) +DECLARE_INSN(vsse512_v, MATCH_VSSE512_V, MASK_VSSE512_V) +DECLARE_INSN(vsse64_v, MATCH_VSSE64_V, MASK_VSSE64_V) +DECLARE_INSN(vsse8_v, MATCH_VSSE8_V, MASK_VSSE8_V) +DECLARE_INSN(vssra_vi, MATCH_VSSRA_VI, MASK_VSSRA_VI) +DECLARE_INSN(vssra_vv, MATCH_VSSRA_VV, MASK_VSSRA_VV) +DECLARE_INSN(vssra_vx, MATCH_VSSRA_VX, MASK_VSSRA_VX) +DECLARE_INSN(vssrl_vi, MATCH_VSSRL_VI, MASK_VSSRL_VI) +DECLARE_INSN(vssrl_vv, MATCH_VSSRL_VV, MASK_VSSRL_VV) +DECLARE_INSN(vssrl_vx, MATCH_VSSRL_VX, MASK_VSSRL_VX) +DECLARE_INSN(vssub_vv, MATCH_VSSUB_VV, MASK_VSSUB_VV) +DECLARE_INSN(vssub_vx, MATCH_VSSUB_VX, MASK_VSSUB_VX) +DECLARE_INSN(vssubu_vv, MATCH_VSSUBU_VV, MASK_VSSUBU_VV) +DECLARE_INSN(vssubu_vx, MATCH_VSSUBU_VX, MASK_VSSUBU_VX) +DECLARE_INSN(vsub_vv, MATCH_VSUB_VV, MASK_VSUB_VV) +DECLARE_INSN(vsub_vx, MATCH_VSUB_VX, MASK_VSUB_VX) +DECLARE_INSN(vsuxei1024_v, MATCH_VSUXEI1024_V, MASK_VSUXEI1024_V) +DECLARE_INSN(vsuxei128_v, MATCH_VSUXEI128_V, MASK_VSUXEI128_V) +DECLARE_INSN(vsuxei16_v, MATCH_VSUXEI16_V, MASK_VSUXEI16_V) +DECLARE_INSN(vsuxei256_v, MATCH_VSUXEI256_V, MASK_VSUXEI256_V) +DECLARE_INSN(vsuxei32_v, MATCH_VSUXEI32_V, MASK_VSUXEI32_V) +DECLARE_INSN(vsuxei512_v, MATCH_VSUXEI512_V, MASK_VSUXEI512_V) +DECLARE_INSN(vsuxei64_v, MATCH_VSUXEI64_V, MASK_VSUXEI64_V) +DECLARE_INSN(vsuxei8_v, MATCH_VSUXEI8_V, MASK_VSUXEI8_V) +DECLARE_INSN(vwadd_vv, MATCH_VWADD_VV, MASK_VWADD_VV) +DECLARE_INSN(vwadd_vx, MATCH_VWADD_VX, MASK_VWADD_VX) +DECLARE_INSN(vwadd_wv, MATCH_VWADD_WV, MASK_VWADD_WV) +DECLARE_INSN(vwadd_wx, MATCH_VWADD_WX, MASK_VWADD_WX) +DECLARE_INSN(vwaddu_vv, MATCH_VWADDU_VV, MASK_VWADDU_VV) +DECLARE_INSN(vwaddu_vx, MATCH_VWADDU_VX, MASK_VWADDU_VX) +DECLARE_INSN(vwaddu_wv, MATCH_VWADDU_WV, MASK_VWADDU_WV) +DECLARE_INSN(vwaddu_wx, MATCH_VWADDU_WX, MASK_VWADDU_WX) +DECLARE_INSN(vwmacc_vv, MATCH_VWMACC_VV, MASK_VWMACC_VV) +DECLARE_INSN(vwmacc_vx, MATCH_VWMACC_VX, MASK_VWMACC_VX) +DECLARE_INSN(vwmaccsu_vv, MATCH_VWMACCSU_VV, MASK_VWMACCSU_VV) +DECLARE_INSN(vwmaccsu_vx, MATCH_VWMACCSU_VX, MASK_VWMACCSU_VX) +DECLARE_INSN(vwmaccu_vv, MATCH_VWMACCU_VV, MASK_VWMACCU_VV) +DECLARE_INSN(vwmaccu_vx, MATCH_VWMACCU_VX, MASK_VWMACCU_VX) +DECLARE_INSN(vwmaccus_vx, MATCH_VWMACCUS_VX, MASK_VWMACCUS_VX) +DECLARE_INSN(vwmul_vv, MATCH_VWMUL_VV, MASK_VWMUL_VV) +DECLARE_INSN(vwmul_vx, MATCH_VWMUL_VX, MASK_VWMUL_VX) +DECLARE_INSN(vwmulsu_vv, MATCH_VWMULSU_VV, MASK_VWMULSU_VV) +DECLARE_INSN(vwmulsu_vx, MATCH_VWMULSU_VX, MASK_VWMULSU_VX) +DECLARE_INSN(vwmulu_vv, MATCH_VWMULU_VV, MASK_VWMULU_VV) +DECLARE_INSN(vwmulu_vx, MATCH_VWMULU_VX, MASK_VWMULU_VX) +DECLARE_INSN(vwredsum_vs, MATCH_VWREDSUM_VS, MASK_VWREDSUM_VS) +DECLARE_INSN(vwredsumu_vs, MATCH_VWREDSUMU_VS, MASK_VWREDSUMU_VS) +DECLARE_INSN(vwsub_vv, MATCH_VWSUB_VV, MASK_VWSUB_VV) +DECLARE_INSN(vwsub_vx, MATCH_VWSUB_VX, MASK_VWSUB_VX) +DECLARE_INSN(vwsub_wv, MATCH_VWSUB_WV, MASK_VWSUB_WV) +DECLARE_INSN(vwsub_wx, MATCH_VWSUB_WX, MASK_VWSUB_WX) +DECLARE_INSN(vwsubu_vv, MATCH_VWSUBU_VV, MASK_VWSUBU_VV) +DECLARE_INSN(vwsubu_vx, MATCH_VWSUBU_VX, MASK_VWSUBU_VX) +DECLARE_INSN(vwsubu_wv, MATCH_VWSUBU_WV, MASK_VWSUBU_WV) +DECLARE_INSN(vwsubu_wx, MATCH_VWSUBU_WX, MASK_VWSUBU_WX) +DECLARE_INSN(vxor_vi, MATCH_VXOR_VI, MASK_VXOR_VI) +DECLARE_INSN(vxor_vv, MATCH_VXOR_VV, MASK_VXOR_VV) +DECLARE_INSN(vxor_vx, MATCH_VXOR_VX, MASK_VXOR_VX) +DECLARE_INSN(vzext_vf2, MATCH_VZEXT_VF2, MASK_VZEXT_VF2) +DECLARE_INSN(vzext_vf4, MATCH_VZEXT_VF4, MASK_VZEXT_VF4) +DECLARE_INSN(vzext_vf8, MATCH_VZEXT_VF8, MASK_VZEXT_VF8) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) +DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) +DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(xperm16, MATCH_XPERM16, MASK_XPERM16) +DECLARE_INSN(xperm32, MATCH_XPERM32, MASK_XPERM32) +DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4) +DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8) +DECLARE_INSN(zunpkd810, MATCH_ZUNPKD810, MASK_ZUNPKD810) +DECLARE_INSN(zunpkd820, MATCH_ZUNPKD820, MASK_ZUNPKD820) +DECLARE_INSN(zunpkd830, MATCH_ZUNPKD830, MASK_ZUNPKD830) +DECLARE_INSN(zunpkd831, MATCH_ZUNPKD831, MASK_ZUNPKD831) +DECLARE_INSN(zunpkd832, MATCH_ZUNPKD832, MASK_ZUNPKD832) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(vstart, CSR_VSTART) +DECLARE_CSR(vxsat, CSR_VXSAT) +DECLARE_CSR(vxrm, CSR_VXRM) +DECLARE_CSR(vcsr, CSR_VCSR) +DECLARE_CSR(seed, CSR_SEED) +DECLARE_CSR(jvt, CSR_JVT) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(vl, CSR_VL) +DECLARE_CSR(vtype, CSR_VTYPE) +DECLARE_CSR(vlenb, CSR_VLENB) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sedeleg, CSR_SEDELEG) +DECLARE_CSR(sideleg, CSR_SIDELEG) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(scounteren, CSR_SCOUNTEREN) +DECLARE_CSR(senvcfg, CSR_SENVCFG) +DECLARE_CSR(sstateen0, CSR_SSTATEEN0) +DECLARE_CSR(sstateen1, CSR_SSTATEEN1) +DECLARE_CSR(sstateen2, CSR_SSTATEEN2) +DECLARE_CSR(sstateen3, CSR_SSTATEEN3) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(stval, CSR_STVAL) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(stimecmp, CSR_STIMECMP) +DECLARE_CSR(siselect, CSR_SISELECT) +DECLARE_CSR(sireg, CSR_SIREG) +DECLARE_CSR(stopei, CSR_STOPEI) +DECLARE_CSR(satp, CSR_SATP) +DECLARE_CSR(scontext, CSR_SCONTEXT) +DECLARE_CSR(vsstatus, CSR_VSSTATUS) +DECLARE_CSR(vsie, CSR_VSIE) +DECLARE_CSR(vstvec, CSR_VSTVEC) +DECLARE_CSR(vsscratch, CSR_VSSCRATCH) +DECLARE_CSR(vsepc, CSR_VSEPC) +DECLARE_CSR(vscause, CSR_VSCAUSE) +DECLARE_CSR(vstval, CSR_VSTVAL) +DECLARE_CSR(vsip, CSR_VSIP) +DECLARE_CSR(vstimecmp, CSR_VSTIMECMP) +DECLARE_CSR(vsiselect, CSR_VSISELECT) +DECLARE_CSR(vsireg, CSR_VSIREG) +DECLARE_CSR(vstopei, CSR_VSTOPEI) +DECLARE_CSR(vsatp, CSR_VSATP) +DECLARE_CSR(hstatus, CSR_HSTATUS) +DECLARE_CSR(hedeleg, CSR_HEDELEG) +DECLARE_CSR(hideleg, CSR_HIDELEG) +DECLARE_CSR(hie, CSR_HIE) +DECLARE_CSR(htimedelta, CSR_HTIMEDELTA) +DECLARE_CSR(hcounteren, CSR_HCOUNTEREN) +DECLARE_CSR(hgeie, CSR_HGEIE) +DECLARE_CSR(hvien, CSR_HVIEN) +DECLARE_CSR(hvictl, CSR_HVICTL) +DECLARE_CSR(henvcfg, CSR_HENVCFG) +DECLARE_CSR(hstateen0, CSR_HSTATEEN0) +DECLARE_CSR(hstateen1, CSR_HSTATEEN1) +DECLARE_CSR(hstateen2, CSR_HSTATEEN2) +DECLARE_CSR(hstateen3, CSR_HSTATEEN3) +DECLARE_CSR(htval, CSR_HTVAL) +DECLARE_CSR(hip, CSR_HIP) +DECLARE_CSR(hvip, CSR_HVIP) +DECLARE_CSR(hviprio1, CSR_HVIPRIO1) +DECLARE_CSR(hviprio2, CSR_HVIPRIO2) +DECLARE_CSR(htinst, CSR_HTINST) +DECLARE_CSR(hgatp, CSR_HGATP) +DECLARE_CSR(hcontext, CSR_HCONTEXT) +DECLARE_CSR(hgeip, CSR_HGEIP) +DECLARE_CSR(vstopi, CSR_VSTOPI) +DECLARE_CSR(scountovf, CSR_SCOUNTOVF) +DECLARE_CSR(stopi, CSR_STOPI) +DECLARE_CSR(utvt, CSR_UTVT) +DECLARE_CSR(unxti, CSR_UNXTI) +DECLARE_CSR(uintstatus, CSR_UINTSTATUS) +DECLARE_CSR(uscratchcsw, CSR_USCRATCHCSW) +DECLARE_CSR(uscratchcswl, CSR_USCRATCHCSWL) +DECLARE_CSR(stvt, CSR_STVT) +DECLARE_CSR(snxti, CSR_SNXTI) +DECLARE_CSR(sintstatus, CSR_SINTSTATUS) +DECLARE_CSR(sscratchcsw, CSR_SSCRATCHCSW) +DECLARE_CSR(sscratchcswl, CSR_SSCRATCHCSWL) +DECLARE_CSR(mtvt, CSR_MTVT) +DECLARE_CSR(mnxti, CSR_MNXTI) +DECLARE_CSR(mintstatus, CSR_MINTSTATUS) +DECLARE_CSR(mscratchcsw, CSR_MSCRATCHCSW) +DECLARE_CSR(mscratchcswl, CSR_MSCRATCHCSWL) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) +DECLARE_CSR(mvien, CSR_MVIEN) +DECLARE_CSR(mvip, CSR_MVIP) +DECLARE_CSR(menvcfg, CSR_MENVCFG) +DECLARE_CSR(mstateen0, CSR_MSTATEEN0) +DECLARE_CSR(mstateen1, CSR_MSTATEEN1) +DECLARE_CSR(mstateen2, CSR_MSTATEEN2) +DECLARE_CSR(mstateen3, CSR_MSTATEEN3) +DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mtval, CSR_MTVAL) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(mtinst, CSR_MTINST) +DECLARE_CSR(mtval2, CSR_MTVAL2) +DECLARE_CSR(miselect, CSR_MISELECT) +DECLARE_CSR(mireg, CSR_MIREG) +DECLARE_CSR(mtopei, CSR_MTOPEI) +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) +DECLARE_CSR(pmpcfg4, CSR_PMPCFG4) +DECLARE_CSR(pmpcfg5, CSR_PMPCFG5) +DECLARE_CSR(pmpcfg6, CSR_PMPCFG6) +DECLARE_CSR(pmpcfg7, CSR_PMPCFG7) +DECLARE_CSR(pmpcfg8, CSR_PMPCFG8) +DECLARE_CSR(pmpcfg9, CSR_PMPCFG9) +DECLARE_CSR(pmpcfg10, CSR_PMPCFG10) +DECLARE_CSR(pmpcfg11, CSR_PMPCFG11) +DECLARE_CSR(pmpcfg12, CSR_PMPCFG12) +DECLARE_CSR(pmpcfg13, CSR_PMPCFG13) +DECLARE_CSR(pmpcfg14, CSR_PMPCFG14) +DECLARE_CSR(pmpcfg15, CSR_PMPCFG15) +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) +DECLARE_CSR(pmpaddr16, CSR_PMPADDR16) +DECLARE_CSR(pmpaddr17, CSR_PMPADDR17) +DECLARE_CSR(pmpaddr18, CSR_PMPADDR18) +DECLARE_CSR(pmpaddr19, CSR_PMPADDR19) +DECLARE_CSR(pmpaddr20, CSR_PMPADDR20) +DECLARE_CSR(pmpaddr21, CSR_PMPADDR21) +DECLARE_CSR(pmpaddr22, CSR_PMPADDR22) +DECLARE_CSR(pmpaddr23, CSR_PMPADDR23) +DECLARE_CSR(pmpaddr24, CSR_PMPADDR24) +DECLARE_CSR(pmpaddr25, CSR_PMPADDR25) +DECLARE_CSR(pmpaddr26, CSR_PMPADDR26) +DECLARE_CSR(pmpaddr27, CSR_PMPADDR27) +DECLARE_CSR(pmpaddr28, CSR_PMPADDR28) +DECLARE_CSR(pmpaddr29, CSR_PMPADDR29) +DECLARE_CSR(pmpaddr30, CSR_PMPADDR30) +DECLARE_CSR(pmpaddr31, CSR_PMPADDR31) +DECLARE_CSR(pmpaddr32, CSR_PMPADDR32) +DECLARE_CSR(pmpaddr33, CSR_PMPADDR33) +DECLARE_CSR(pmpaddr34, CSR_PMPADDR34) +DECLARE_CSR(pmpaddr35, CSR_PMPADDR35) +DECLARE_CSR(pmpaddr36, CSR_PMPADDR36) +DECLARE_CSR(pmpaddr37, CSR_PMPADDR37) +DECLARE_CSR(pmpaddr38, CSR_PMPADDR38) +DECLARE_CSR(pmpaddr39, CSR_PMPADDR39) +DECLARE_CSR(pmpaddr40, CSR_PMPADDR40) +DECLARE_CSR(pmpaddr41, CSR_PMPADDR41) +DECLARE_CSR(pmpaddr42, CSR_PMPADDR42) +DECLARE_CSR(pmpaddr43, CSR_PMPADDR43) +DECLARE_CSR(pmpaddr44, CSR_PMPADDR44) +DECLARE_CSR(pmpaddr45, CSR_PMPADDR45) +DECLARE_CSR(pmpaddr46, CSR_PMPADDR46) +DECLARE_CSR(pmpaddr47, CSR_PMPADDR47) +DECLARE_CSR(pmpaddr48, CSR_PMPADDR48) +DECLARE_CSR(pmpaddr49, CSR_PMPADDR49) +DECLARE_CSR(pmpaddr50, CSR_PMPADDR50) +DECLARE_CSR(pmpaddr51, CSR_PMPADDR51) +DECLARE_CSR(pmpaddr52, CSR_PMPADDR52) +DECLARE_CSR(pmpaddr53, CSR_PMPADDR53) +DECLARE_CSR(pmpaddr54, CSR_PMPADDR54) +DECLARE_CSR(pmpaddr55, CSR_PMPADDR55) +DECLARE_CSR(pmpaddr56, CSR_PMPADDR56) +DECLARE_CSR(pmpaddr57, CSR_PMPADDR57) +DECLARE_CSR(pmpaddr58, CSR_PMPADDR58) +DECLARE_CSR(pmpaddr59, CSR_PMPADDR59) +DECLARE_CSR(pmpaddr60, CSR_PMPADDR60) +DECLARE_CSR(pmpaddr61, CSR_PMPADDR61) +DECLARE_CSR(pmpaddr62, CSR_PMPADDR62) +DECLARE_CSR(pmpaddr63, CSR_PMPADDR63) +DECLARE_CSR(mseccfg, CSR_MSECCFG) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(tinfo, CSR_TINFO) +DECLARE_CSR(tcontrol, CSR_TCONTROL) +DECLARE_CSR(mcontext, CSR_MCONTEXT) +DECLARE_CSR(mscontext, CSR_MSCONTEXT) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch0, CSR_DSCRATCH0) +DECLARE_CSR(dscratch1, CSR_DSCRATCH1) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(mconfigptr, CSR_MCONFIGPTR) +DECLARE_CSR(mtopi, CSR_MTOPI) +DECLARE_CSR(sieh, CSR_SIEH) +DECLARE_CSR(siph, CSR_SIPH) +DECLARE_CSR(stimecmph, CSR_STIMECMPH) +DECLARE_CSR(vsieh, CSR_VSIEH) +DECLARE_CSR(vsiph, CSR_VSIPH) +DECLARE_CSR(vstimecmph, CSR_VSTIMECMPH) +DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH) +DECLARE_CSR(hidelegh, CSR_HIDELEGH) +DECLARE_CSR(hvienh, CSR_HVIENH) +DECLARE_CSR(henvcfgh, CSR_HENVCFGH) +DECLARE_CSR(hviph, CSR_HVIPH) +DECLARE_CSR(hviprio1h, CSR_HVIPRIO1H) +DECLARE_CSR(hviprio2h, CSR_HVIPRIO2H) +DECLARE_CSR(hstateen0h, CSR_HSTATEEN0H) +DECLARE_CSR(hstateen1h, CSR_HSTATEEN1H) +DECLARE_CSR(hstateen2h, CSR_HSTATEEN2H) +DECLARE_CSR(hstateen3h, CSR_HSTATEEN3H) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mstatush, CSR_MSTATUSH) +DECLARE_CSR(midelegh, CSR_MIDELEGH) +DECLARE_CSR(mieh, CSR_MIEH) +DECLARE_CSR(mvienh, CSR_MVIENH) +DECLARE_CSR(mviph, CSR_MVIPH) +DECLARE_CSR(menvcfgh, CSR_MENVCFGH) +DECLARE_CSR(mstateen0h, CSR_MSTATEEN0H) +DECLARE_CSR(mstateen1h, CSR_MSTATEEN1H) +DECLARE_CSR(mstateen2h, CSR_MSTATEEN2H) +DECLARE_CSR(mstateen3h, CSR_MSTATEEN3H) +DECLARE_CSR(miph, CSR_MIPH) +DECLARE_CSR(mhpmevent3h, CSR_MHPMEVENT3H) +DECLARE_CSR(mhpmevent4h, CSR_MHPMEVENT4H) +DECLARE_CSR(mhpmevent5h, CSR_MHPMEVENT5H) +DECLARE_CSR(mhpmevent6h, CSR_MHPMEVENT6H) +DECLARE_CSR(mhpmevent7h, CSR_MHPMEVENT7H) +DECLARE_CSR(mhpmevent8h, CSR_MHPMEVENT8H) +DECLARE_CSR(mhpmevent9h, CSR_MHPMEVENT9H) +DECLARE_CSR(mhpmevent10h, CSR_MHPMEVENT10H) +DECLARE_CSR(mhpmevent11h, CSR_MHPMEVENT11H) +DECLARE_CSR(mhpmevent12h, CSR_MHPMEVENT12H) +DECLARE_CSR(mhpmevent13h, CSR_MHPMEVENT13H) +DECLARE_CSR(mhpmevent14h, CSR_MHPMEVENT14H) +DECLARE_CSR(mhpmevent15h, CSR_MHPMEVENT15H) +DECLARE_CSR(mhpmevent16h, CSR_MHPMEVENT16H) +DECLARE_CSR(mhpmevent17h, CSR_MHPMEVENT17H) +DECLARE_CSR(mhpmevent18h, CSR_MHPMEVENT18H) +DECLARE_CSR(mhpmevent19h, CSR_MHPMEVENT19H) +DECLARE_CSR(mhpmevent20h, CSR_MHPMEVENT20H) +DECLARE_CSR(mhpmevent21h, CSR_MHPMEVENT21H) +DECLARE_CSR(mhpmevent22h, CSR_MHPMEVENT22H) +DECLARE_CSR(mhpmevent23h, CSR_MHPMEVENT23H) +DECLARE_CSR(mhpmevent24h, CSR_MHPMEVENT24H) +DECLARE_CSR(mhpmevent25h, CSR_MHPMEVENT25H) +DECLARE_CSR(mhpmevent26h, CSR_MHPMEVENT26H) +DECLARE_CSR(mhpmevent27h, CSR_MHPMEVENT27H) +DECLARE_CSR(mhpmevent28h, CSR_MHPMEVENT28H) +DECLARE_CSR(mhpmevent29h, CSR_MHPMEVENT29H) +DECLARE_CSR(mhpmevent30h, CSR_MHPMEVENT30H) +DECLARE_CSR(mhpmevent31h, CSR_MHPMEVENT31H) +DECLARE_CSR(mnscratch, CSR_MNSCRATCH) +DECLARE_CSR(mnepc, CSR_MNEPC) +DECLARE_CSR(mncause, CSR_MNCAUSE) +DECLARE_CSR(mnstatus, CSR_MNSTATUS) +DECLARE_CSR(mseccfgh, CSR_MSECCFGH) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("virtual_supervisor_ecall", CAUSE_VIRTUAL_SUPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) +DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) +DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) +DECLARE_CAUSE("fetch guest page fault", CAUSE_FETCH_GUEST_PAGE_FAULT) +DECLARE_CAUSE("load guest page fault", CAUSE_LOAD_GUEST_PAGE_FAULT) +DECLARE_CAUSE("virtual instruction", CAUSE_VIRTUAL_INSTRUCTION) +DECLARE_CAUSE("store guest page fault", CAUSE_STORE_GUEST_PAGE_FAULT) +#endif diff --git a/src/main/resources/applications_for_fpga/headers/syscalls.c b/src/main/resources/applications_for_fpga/headers/syscalls.c new file mode 100644 index 00000000..9c729656 --- /dev/null +++ b/src/main/resources/applications_for_fpga/headers/syscalls.c @@ -0,0 +1,156 @@ +// See LICENSE for license details. + +#include +#include +#include +#include +#include +#include +// #include "util.h" + +#define SYS_write 64 + +#undef strcmp + +#define TOHOST 0x10000000 + +#define PUTCHAR_TOHOST( ch ) do { *((volatile char*)TOHOST) = ch; } while(0); + +void clearCounters(void) { + asm volatile ("csrw minstret, x0; csrw mcycle, x0;"); + return; +} + +void getCounters(unsigned long* instret, unsigned long* cycle) { + asm volatile("rdinstret %0":"=r" (&instret)); + asm volatile("rdcycle %0":"=r" (&cycle)); + return; +} + +void __attribute__((noreturn)) exit(int ret) { + *((volatile int*)TOHOST) = ret; +_exit: + goto _exit; +} + +uintptr_t __attribute__((weak)) handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32]) +{ + exit((epc << 16) | cause); +} + +void __attribute__((weak)) thread_entry(int cid, int nc) +{ + // multi-threaded programs override this function. + // for the case of single-threaded programs, only let core 0 proceed. + while (cid != 0); +} + +int __attribute__((weak)) main(int argc, char** argv) +{ + // single-threaded programs override this function. + // printstr("Implement main(), foo!\n"); + return -1; +} + +void _init( +#ifdef MULTICORE + int cid, int nc +#else + void +#endif + ) +{ + // init_tls(); + // thread_entry(cid, nc); + + // only single-threaded programs should ever get here. + int ret = main(0, 0); + + exit(ret); +} + +void* memcpy(void* dest, const void* src, size_t len) +{ + if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) { + const uintptr_t* s = src; + uintptr_t *d = dest; + uintptr_t *end = dest + len; + while (d + 8 < end) { + uintptr_t reg[8] = {s[0], s[1], s[2], s[3], s[4], s[5], s[6], s[7]}; + d[0] = reg[0]; + d[1] = reg[1]; + d[2] = reg[2]; + d[3] = reg[3]; + d[4] = reg[4]; + d[5] = reg[5]; + d[6] = reg[6]; + d[7] = reg[7]; + d += 8; + s += 8; + } + while (d < end) + *d++ = *s++; + } else { + const char* s = src; + char *d = dest; + while (d < (char*)(dest + len)) + *d++ = *s++; + } + return dest; +} + +void* memset(void* dest, int byte, size_t len) +{ + if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) { + uintptr_t word = byte & 0xFF; + word |= word << 8; + word |= word << 16; + word |= word << 16 << 16; + + uintptr_t *d = dest; + while (d < (uintptr_t*)(dest + len)) + *d++ = word; + } else { + char *d = dest; + while (d < (char*)(dest + len)) + *d++ = byte; + } + return dest; +} + +size_t strlen(const char *s) +{ + const char *p = s; + while (*p) + p++; + return p - s; +} + +size_t strnlen(const char *s, size_t n) +{ + const char *p = s; + while (n-- && *p) + p++; + return p - s; +} + +int strcmp(const char* s1, const char* s2) +{ + unsigned char c1, c2; + + do { + c1 = *s1++; + c2 = *s2++; + } while (c1 != 0 && c1 == c2); + + return c1 - c2; +} + +char* strcpy(char* dest, const char* src) +{ + char* d = dest; + while ((*d++ = *src++)) + ; + return dest; +} + diff --git a/src/main/resources/applications_for_fpga/headers/test.ld b/src/main/resources/applications_for_fpga/headers/test.ld new file mode 100644 index 00000000..a7fe1f11 --- /dev/null +++ b/src/main/resources/applications_for_fpga/headers/test.ld @@ -0,0 +1,66 @@ +/*======================================================================*/ +/* Proxy kernel linker script */ +/*======================================================================*/ +/* This is the linker script used when building the proxy kernel. */ + +/*----------------------------------------------------------------------*/ +/* Setup */ +/*----------------------------------------------------------------------*/ + +/* The OUTPUT_ARCH command specifies the machine architecture where the + argument is one of the names used in the BFD library. More + specifically one of the entires in bfd/cpu-mips.c */ + +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +/*----------------------------------------------------------------------*/ +/* Sections */ +/*----------------------------------------------------------------------*/ + +SECTIONS +{ + + /* text: test code section */ + . = 0x00000000; + .text.init : { *(.text.init) } + .text : { *(.text) } + + /* data segment */ + . = ALIGN(0x4000); + .data : { *(.data) } + .rodata : { *(.rodata) } + + .sdata : { + __global_pointer$ = . + 0x800; + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + } + + /* bss segment */ + .sbss : { + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } + .bss : { *(.bss) } + + /* thread-local data segment */ + .tdata : + { + _tdata_begin = .; + *(.tdata) + _tdata_end = .; + } + .tbss : + { + *(.tbss) + _tbss_end = .; + } + + . = ALIGN(0x10000000); + .tohost : { *(.tohost) } + + /* End of uninitalized data segement */ + _end = .; +} + diff --git a/src/main/resources/build_helloworld_asm.sh b/src/main/resources/build_helloworld_asm.sh index 81a6d7ee..3e685443 100644 --- a/src/main/resources/build_helloworld_asm.sh +++ b/src/main/resources/build_helloworld_asm.sh @@ -1,9 +1,16 @@ #!/bin/bash #riscv64-unknown-elf-gcc -march=rv64i -mabi=lp64 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I ./headers/ -T link.ld ../../../submodule/riscv-tests/isa/rv64ui/addi.S -o addi.out -riscv64-unknown-elf-gcc -march=rv64i -mabi=lp64 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I ./headers/ -T link.ld helloworld_asm.S -o helloworld_asm.out -riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data helloworld_asm.out > helloworld_asm.dump -riscv64-unknown-elf-objcopy -O binary helloworld_asm.out helloworld_asm.bin -riscv64-unknown-elf-objcopy --dump-section .text.init=helloworld_asm_inst.bin helloworld_asm.out -hexdump -v -e '1/1 "%02x" "\n"' helloworld_asm_inst.bin > helloworld_asm_inst.hex +#riscv64-unknown-elf-gcc -march=rv64i -mabi=lp64 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I ./headers/ -T link.ld helloworld_asm.S -o helloworld_asm.out +#riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data helloworld_asm.out > helloworld_asm.dump +#riscv64-unknown-elf-objcopy -O binary helloworld_asm.out helloworld_asm.bin +#riscv64-unknown-elf-objcopy --dump-section .text.init=helloworld_asm_inst.bin helloworld_asm.out +#hexdump -v -e '1/1 "%02x" "\n"' helloworld_asm_inst.bin > helloworld_asm_inst.hex + +riscv64-unknown-elf-gcc -march=rv64i_zicsr -mabi=lp64 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I ./headers/ -T link.ld simpleTest.S -o simpleTest.out +riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data simpleTest.out > simpleTest.dump +riscv64-unknown-elf-objcopy -O binary simpleTest.out simpleTest.bin +riscv64-unknown-elf-objcopy --dump-section .text.init=simpleTest_inst.bin simpleTest.out +hexdump -v -e '1/4 "%08x" "\n"' simpleTest_inst.bin > simpleTest_inst.hex + rm *.out *.bin \ No newline at end of file diff --git a/src/main/resources/simpleTest.S b/src/main/resources/simpleTest.S new file mode 100644 index 00000000..06beeb09 --- /dev/null +++ b/src/main/resources/simpleTest.S @@ -0,0 +1,26 @@ +#include "riscv_test.h" +#include "test_macros.h" + +#define PUTCHAR(x) \ + li s1, x; \ + sb s1, 0(s0); + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + li s0, 0x10000000 + li s1, 0x114514 + sw s1, 0(s0) +loop: + j loop + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END \ No newline at end of file diff --git a/src/main/resources/simpleTest.dump b/src/main/resources/simpleTest.dump new file mode 100644 index 00000000..ecaefa66 --- /dev/null +++ b/src/main/resources/simpleTest.dump @@ -0,0 +1,106 @@ + +simpleTest.out: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000000000000 <_start>: + 0: 03c0006f j 3c + +0000000000000004 : + 4: 34202f73 csrr t5,mcause + 8: 00800f93 li t6,8 + c: 03ff0263 beq t5,t6,30 + 10: 00900f93 li t6,9 + 14: 01ff0e63 beq t5,t6,30 + 18: 00b00f93 li t6,11 + 1c: 01ff0a63 beq t5,t6,30 + 20: 34202f73 csrr t5,mcause + 24: 000f5463 bgez t5,2c + 28: 0040006f j 2c + +000000000000002c : + 2c: 5391e193 or gp,gp,1337 + +0000000000000030 : + 30: 10000f17 auipc t5,0x10000 + 34: fc3f2823 sw gp,-48(t5) # 10000000 + 38: 0000006f j 38 + +000000000000003c : + 3c: b0005073 csrw mcycle,0 + 40: b0205073 csrw minstret,0 + 44: 00000093 li ra,0 + 48: 00000113 li sp,0 + 4c: 00000193 li gp,0 + 50: 00000213 li tp,0 + 54: 00000293 li t0,0 + 58: 00000313 li t1,0 + 5c: 00000393 li t2,0 + 60: 00000413 li s0,0 + 64: 00000493 li s1,0 + 68: 00000513 li a0,0 + 6c: 00000593 li a1,0 + 70: 00000613 li a2,0 + 74: 00000693 li a3,0 + 78: 00000713 li a4,0 + 7c: 00000793 li a5,0 + 80: 00000813 li a6,0 + 84: 00000893 li a7,0 + 88: 00000913 li s2,0 + 8c: 00000993 li s3,0 + 90: 00000a13 li s4,0 + 94: 00000a93 li s5,0 + 98: 00000b13 li s6,0 + 9c: 00000b93 li s7,0 + a0: 00000c13 li s8,0 + a4: 00000c93 li s9,0 + a8: 00000d13 li s10,0 + ac: 00000d93 li s11,0 + b0: 00000e13 li t3,0 + b4: 00000e93 li t4,0 + b8: 00000f13 li t5,0 + bc: 00000f93 li t6,0 + c0: 00000193 li gp,0 + c4: 00000297 auipc t0,0x0 + c8: f4028293 add t0,t0,-192 # 4 + cc: 30529073 csrw mtvec,t0 + d0: 30005073 csrw mstatus,0 + d4: 00000297 auipc t0,0x0 + d8: 01428293 add t0,t0,20 # e8 + dc: 34129073 csrw mepc,t0 + e0: f1402573 csrr a0,mhartid + e4: 30200073 mret + e8: 10000437 lui s0,0x10000 + ec: 001144b7 lui s1,0x114 + f0: 5144849b addw s1,s1,1300 # 114514 + f4: 00942023 sw s1,0(s0) # 10000000 + +00000000000000f8 : + f8: 0000006f j f8 + fc: 02301063 bne zero,gp,11c + +0000000000000100 : + 100: 0ff0000f fence + 104: 00018063 beqz gp,104 + 108: 00119193 sll gp,gp,0x1 + 10c: 0011e193 or gp,gp,1 + 110: 05d00893 li a7,93 + 114: 00018513 mv a0,gp + 118: 00000073 ecall + +000000000000011c : + 11c: 0ff0000f fence + 120: 00100193 li gp,1 + 124: 05d00893 li a7,93 + 128: 00000513 li a0,0 + 12c: 00000073 ecall + 130: c0001073 unimp + 134: 0000 .2byte 0x0 + 136: 0000 .2byte 0x0 + 138: 0000 .2byte 0x0 + 13a: 0000 .2byte 0x0 + 13c: 0000 .2byte 0x0 + 13e: 0000 .2byte 0x0 + 140: 0000 .2byte 0x0 + 142: 0000 .2byte 0x0 diff --git a/src/main/resources/simpleTest_inst.hex b/src/main/resources/simpleTest_inst.hex new file mode 100644 index 00000000..2c1d9735 --- /dev/null +++ b/src/main/resources/simpleTest_inst.hex @@ -0,0 +1,81 @@ +03c0006f +34202f73 +00800f93 +03ff0263 +00900f93 +01ff0e63 +00b00f93 +01ff0a63 +34202f73 +000f5463 +0040006f +5391e193 +10000f17 +fc3f2823 +0000006f +b0005073 +b0205073 +00000093 +00000113 +00000193 +00000213 +00000293 +00000313 +00000393 +00000413 +00000493 +00000513 +00000593 +00000613 +00000693 +00000713 +00000793 +00000813 +00000893 +00000913 +00000993 +00000a13 +00000a93 +00000b13 +00000b93 +00000c13 +00000c93 +00000d13 +00000d93 +00000e13 +00000e93 +00000f13 +00000f93 +00000193 +00000297 +f4028293 +30529073 +30005073 +00000297 +01428293 +34129073 +f1402573 +30200073 +10000437 +001144b7 +5144849b +00942023 +0000006f +02301063 +0ff0000f +00018063 +00119193 +0011e193 +05d00893 +00018513 +00000073 +0ff0000f +00100193 +05d00893 +00000513 +00000073 +c0001073 +00000000 +00000000 +00000000 +00000000 diff --git a/src/main/scala/my_random_useful_programs/Data32To64.scala b/src/main/scala/my_random_useful_programs/Data32To64.scala new file mode 100644 index 00000000..dfe2f03b --- /dev/null +++ b/src/main/scala/my_random_useful_programs/Data32To64.scala @@ -0,0 +1,12 @@ +package my_random_useful_programs + +import scala.io._ + +object Data32To64 extends App { + val fileLines = Source.fromFile("src/main/resources/applications_vector/vector_matmul_data.hex").getLines().toSeq + val ls = fileLines ++ (if(fileLines.length % 2 != 0) Seq("00000000") else Nil) + val strList = for(i <- 0 until ls.length/2) yield { + ls(i*2+1) + ls(i*2) + } + strList.foreach(println) +} From 0fd14eb596b872e4ce0bba1894400da43f5a1b90 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Wed, 29 Nov 2023 18:10:08 +0900 Subject: [PATCH 04/13] remove unused file --- src/main/resources/build_helloworld_asm.sh | 7 ---- src/main/resources/helloworld_asm.S | 37 ---------------------- 2 files changed, 44 deletions(-) delete mode 100644 src/main/resources/helloworld_asm.S diff --git a/src/main/resources/build_helloworld_asm.sh b/src/main/resources/build_helloworld_asm.sh index 3e685443..2f95b1fa 100644 --- a/src/main/resources/build_helloworld_asm.sh +++ b/src/main/resources/build_helloworld_asm.sh @@ -1,12 +1,5 @@ #!/bin/bash -#riscv64-unknown-elf-gcc -march=rv64i -mabi=lp64 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I ./headers/ -T link.ld ../../../submodule/riscv-tests/isa/rv64ui/addi.S -o addi.out -#riscv64-unknown-elf-gcc -march=rv64i -mabi=lp64 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I ./headers/ -T link.ld helloworld_asm.S -o helloworld_asm.out -#riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data helloworld_asm.out > helloworld_asm.dump -#riscv64-unknown-elf-objcopy -O binary helloworld_asm.out helloworld_asm.bin -#riscv64-unknown-elf-objcopy --dump-section .text.init=helloworld_asm_inst.bin helloworld_asm.out -#hexdump -v -e '1/1 "%02x" "\n"' helloworld_asm_inst.bin > helloworld_asm_inst.hex - riscv64-unknown-elf-gcc -march=rv64i_zicsr -mabi=lp64 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I ./headers/ -T link.ld simpleTest.S -o simpleTest.out riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data simpleTest.out > simpleTest.dump riscv64-unknown-elf-objcopy -O binary simpleTest.out simpleTest.bin diff --git a/src/main/resources/helloworld_asm.S b/src/main/resources/helloworld_asm.S deleted file mode 100644 index 1389553e..00000000 --- a/src/main/resources/helloworld_asm.S +++ /dev/null @@ -1,37 +0,0 @@ -#include "riscv_test.h" -#include "test_macros.h" - -#define PUTCHAR(x) \ - li s1, x; \ - sb s1, 0(s0); - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - li s0, 0x1000 - PUTCHAR('H') - PUTCHAR('e') - PUTCHAR('l') - PUTCHAR('l') - PUTCHAR('o') - PUTCHAR(',') - PUTCHAR(' ') - PUTCHAR('W') - PUTCHAR('o') - PUTCHAR('r') - PUTCHAR('l') - PUTCHAR('d') - PUTCHAR('!') - PUTCHAR(0) - ret - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END \ No newline at end of file From 19c04c2eb65d9d29a2447983d1a8bcd2971d153c Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Wed, 29 Nov 2023 18:23:17 +0900 Subject: [PATCH 05/13] add FPGA files --- fpga/SEG_PUT.v | 109 ++++++++++++++++++++++++++++++++ fpga/nexys4.xdc | 28 ++++++++ fpga/sim.v | 46 ++++++++++++++ fpga/top.v | 165 ++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 348 insertions(+) create mode 100644 fpga/SEG_PUT.v create mode 100644 fpga/nexys4.xdc create mode 100644 fpga/sim.v create mode 100644 fpga/top.v diff --git a/fpga/SEG_PUT.v b/fpga/SEG_PUT.v new file mode 100644 index 00000000..d3263773 --- /dev/null +++ b/fpga/SEG_PUT.v @@ -0,0 +1,109 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: Nakajo lab. +// Engineer: Hironari Yoshiuchi +// +// Create Date: 16:56:03 05/12/2014 +// Design Name: +// Module Name: SEG_PUT +// Project Name: +// Target Devices: Nexys4 +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module SEG_PUT(CLK, reset, check, SEG, AN + ); + input CLK, reset; + input [31:0] check; + output [6:0] SEG; + output [7:0] AN; + + reg [2:0] SEG_state; + + wire SEG_CLK; + + SEG_CLK_GEN SEG_CLK_GEN(.CLK(CLK), .reset(reset), .SEG_CLK(SEG_CLK)); + + assign AN = (SEG_state == 0) ? 8'b11111110: + (SEG_state == 1) ? 8'b11111101: + (SEG_state == 2) ? 8'b11111011: + (SEG_state == 3) ? 8'b11110111: + (SEG_state == 4) ? 8'b11101111: + (SEG_state == 5) ? 8'b11011111: + (SEG_state == 6) ? 8'b10111111: + (SEG_state == 7) ? 8'b01111111: + /*�����Ȓl*/ 8'b11111111; + + assign SEG = (SEG_state == 0) ? hex7seg(check[3:0]): + (SEG_state == 1) ? hex7seg(check[7:4]): + (SEG_state == 2) ? hex7seg(check[11:8]): + (SEG_state == 3) ? hex7seg(check[15:12]): + (SEG_state == 4) ? hex7seg(check[19:16]): + (SEG_state == 5) ? hex7seg(check[23:20]): + (SEG_state == 6) ? hex7seg(check[27:24]): + (SEG_state == 7) ? hex7seg(check[31:28]): + /*�����Ȓl*/ 7'b0000000; + + + always@(posedge SEG_CLK or negedge reset) begin + if(!reset) begin + SEG_state <= 0; + end else begin + if(SEG_state == 7) SEG_state <= 0; + else SEG_state <= SEG_state + 1; + end + end + + + function [6:0] hex7seg; + input [3:0] hex; + begin + case (hex) + 0: hex7seg = 7'b1000000; + 1: hex7seg = 7'b1111001; + 2: hex7seg = 7'b0100100; + 3: hex7seg = 7'b0110000; + 4: hex7seg = 7'b0011001; + 5: hex7seg = 7'b0010010; + 6: hex7seg = 7'b0000010; + 7: hex7seg = 7'b1111000; + 8: hex7seg = 7'b0000000; + 9: hex7seg = 7'b0010000; + 10: hex7seg = 7'b0001000; + 11: hex7seg = 7'b0000011; + 12: hex7seg = 7'b1000110; + 13: hex7seg = 7'b0100001; + 14: hex7seg = 7'b0000110; + 15: hex7seg = 7'b0001110; + endcase + end + endfunction +endmodule + +module SEG_CLK_GEN(CLK, reset, SEG_CLK + ); + input CLK, reset; + output reg SEG_CLK; + + reg [16:0] cnt; + + always@(posedge CLK or negedge reset) begin + if(!reset) begin + cnt <= 0; + SEG_CLK <= 0; + end else if(cnt == 100000) begin + cnt <= 0; + SEG_CLK <= 1; + end else begin + cnt <= cnt + 1; + SEG_CLK <= 0; + end + end +endmodule \ No newline at end of file diff --git a/fpga/nexys4.xdc b/fpga/nexys4.xdc new file mode 100644 index 00000000..1e83669b --- /dev/null +++ b/fpga/nexys4.xdc @@ -0,0 +1,28 @@ +set_property PACKAGE_PIN E3 [get_ports clk_in1_0] +set_property IOSTANDARD LVCMOS33 [get_ports clk_in1_0] +create_clock -period 10.0 [get_ports clk_in1_0] + +set_property IOSTANDARD LVCMOS33 [get_ports RST_0] +set_property PACKAGE_PIN C12 [get_ports RST_0] + +# number of 7seg +set_property IOSTANDARD LVCMOS33 [get_ports {SEG_0[*]}] +set_property PACKAGE_PIN L3 [get_ports {SEG_0[0]}] +set_property PACKAGE_PIN N1 [get_ports {SEG_0[1]}] +set_property PACKAGE_PIN L5 [get_ports {SEG_0[2]}] +set_property PACKAGE_PIN L4 [get_ports {SEG_0[3]}] +set_property PACKAGE_PIN K3 [get_ports {SEG_0[4]}] +set_property PACKAGE_PIN M2 [get_ports {SEG_0[5]}] +set_property PACKAGE_PIN L6 [get_ports {SEG_0[6]}] + +# location of 7seg +set_property IOSTANDARD LVCMOS33 [get_ports {AN_0[*]}] +set_property PACKAGE_PIN N6 [get_ports {AN_0[0]}] +set_property PACKAGE_PIN M6 [get_ports {AN_0[1]}] +set_property PACKAGE_PIN M3 [get_ports {AN_0[2]}] +set_property PACKAGE_PIN N5 [get_ports {AN_0[3]}] +set_property PACKAGE_PIN N2 [get_ports {AN_0[4]}] +set_property PACKAGE_PIN N4 [get_ports {AN_0[5]}] +set_property PACKAGE_PIN L1 [get_ports {AN_0[6]}] +set_property PACKAGE_PIN M1 [get_ports {AN_0[7]}] + diff --git a/fpga/sim.v b/fpga/sim.v new file mode 100644 index 00000000..1ae1aadf --- /dev/null +++ b/fpga/sim.v @@ -0,0 +1,46 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11/28/2023 07:11:11 PM +// Design Name: +// Module Name: sim +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module sim(); + wire [31:0] tohost; + reg CLK, RST; + + top top( + .CLK(CLK), + .RST(RST), + .tohost(tohost) + ); + + initial begin + RST = 1; + CLK = 0; + + #256 RST = 0; + #256 RST = 1; + #1024 $finish; + end + + always begin + #2 CLK = ~CLK; + end + +endmodule diff --git a/fpga/top.v b/fpga/top.v new file mode 100644 index 00000000..7bb49756 --- /dev/null +++ b/fpga/top.v @@ -0,0 +1,165 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11/28/2023 03:04:21 PM +// Design Name: +// Module Name: top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module top( + input CLK, + input RST, + output [31:0] tohost + ); + wire io_icache_axi4lite_ar_ready; + wire io_icache_axi4lite_aw_ready; + wire io_icache_axi4lite_b_valid; + wire [2:0] io_icache_axi4lite_b_bits_resp; + wire io_icache_axi4lite_r_valid; + wire [31:0] io_icache_axi4lite_r_bits_data; + wire [2:0] io_icache_axi4lite_r_bits_resp; + wire io_icache_axi4lite_w_ready; + wire io_dcache_axi4lite_ar_ready; + wire io_dcache_axi4lite_aw_ready; + wire io_dcache_axi4lite_b_valid; + wire [2:0] io_dcache_axi4lite_b_bits_resp; + wire io_dcache_axi4lite_r_valid; + wire [63:0] io_dcache_axi4lite_r_bits_data; + wire [2:0] io_dcache_axi4lite_r_bits_resp; + wire io_dcache_axi4lite_w_ready; + wire [63:0] io_reset_vector; + wire io_hartid; + wire io_icache_axi4lite_ar_valid; + wire [63:0] io_icache_axi4lite_ar_bits_addr; + wire [2:0] io_icache_axi4lite_ar_bits_prot; + wire io_icache_axi4lite_aw_valid; + wire [63:0] io_icache_axi4lite_aw_bits_addr; + wire [2:0] io_icache_axi4lite_aw_bits_prot; + wire io_icache_axi4lite_b_ready; + wire io_icache_axi4lite_r_ready; + wire io_icache_axi4lite_w_valid; + wire [31:0] io_icache_axi4lite_w_bits_data; + wire [3:0] io_icache_axi4lite_w_bits_strb; + wire io_dcache_axi4lite_ar_valid; + wire [63:0] io_dcache_axi4lite_ar_bits_addr; + wire [2:0] io_dcache_axi4lite_ar_bits_prot; + wire io_dcache_axi4lite_aw_valid; + wire [63:0] io_dcache_axi4lite_aw_bits_addr; + wire [2:0] io_dcache_axi4lite_aw_bits_prot; + wire io_dcache_axi4lite_b_ready; + wire io_dcache_axi4lite_r_ready; + wire io_dcache_axi4lite_w_valid; + wire [63:0] io_dcache_axi4lite_w_bits_data; + wire [7:0] io_dcache_axi4lite_w_bits_strb; + // wire tohost_valid; + wire [31:0] tohost_bits; + + Core core( + .clock(CLK), + .reset(!RST), + .io_icache_axi4lite_ar_ready(io_icache_axi4lite_ar_ready), + .io_icache_axi4lite_aw_ready(io_icache_axi4lite_aw_ready), + .io_icache_axi4lite_b_valid(io_icache_axi4lite_b_valid), + .io_icache_axi4lite_b_bits_resp(io_icache_axi4lite_b_bits_resp), + .io_icache_axi4lite_r_valid(io_icache_axi4lite_r_valid), + .io_icache_axi4lite_r_bits_data(io_icache_axi4lite_r_bits_data), + .io_icache_axi4lite_r_bits_resp(io_icache_axi4lite_r_bits_resp), + .io_icache_axi4lite_w_ready(io_icache_axi4lite_w_ready), + .io_dcache_axi4lite_ar_ready(io_dcache_axi4lite_ar_ready), + .io_dcache_axi4lite_aw_ready(io_dcache_axi4lite_aw_ready), + .io_dcache_axi4lite_b_valid(io_dcache_axi4lite_b_valid), + .io_dcache_axi4lite_b_bits_resp(io_dcache_axi4lite_b_bits_resp), + .io_dcache_axi4lite_r_valid(io_dcache_axi4lite_r_valid), + .io_dcache_axi4lite_r_bits_data(io_dcache_axi4lite_r_bits_data), + .io_dcache_axi4lite_r_bits_resp(io_dcache_axi4lite_r_bits_resp), + .io_dcache_axi4lite_w_ready(io_dcache_axi4lite_w_ready), + .io_reset_vector(64'h0), + .io_hartid(64'h0), + .io_icache_axi4lite_ar_valid(io_icache_axi4lite_ar_valid), + .io_icache_axi4lite_ar_bits_addr(io_icache_axi4lite_ar_bits_addr), + .io_icache_axi4lite_ar_bits_prot(io_icache_axi4lite_ar_bits_prot), + .io_icache_axi4lite_aw_valid(io_icache_axi4lite_aw_valid), + .io_icache_axi4lite_aw_bits_addr(io_icache_axi4lite_aw_bits_addr), + .io_icache_axi4lite_aw_bits_prot(io_icache_axi4lite_aw_bits_prot), + .io_icache_axi4lite_b_ready(io_icache_axi4lite_b_ready), + .io_icache_axi4lite_r_ready(io_icache_axi4lite_r_ready), + .io_icache_axi4lite_w_valid(io_icache_axi4lite_w_valid), + .io_icache_axi4lite_w_bits_data(io_icache_axi4lite_w_bits_data), + .io_icache_axi4lite_w_bits_strb(io_icache_axi4lite_w_bits_strb), + .io_dcache_axi4lite_ar_valid(io_dcache_axi4lite_ar_valid), + .io_dcache_axi4lite_ar_bits_addr(io_dcache_axi4lite_ar_bits_addr), + .io_dcache_axi4lite_ar_bits_prot(io_dcache_axi4lite_ar_bits_prot), + .io_dcache_axi4lite_aw_valid(io_dcache_axi4lite_aw_valid), + .io_dcache_axi4lite_aw_bits_addr(io_dcache_axi4lite_aw_bits_addr), + .io_dcache_axi4lite_aw_bits_prot(io_dcache_axi4lite_aw_bits_prot), + .io_dcache_axi4lite_b_ready(io_dcache_axi4lite_b_ready), + .io_dcache_axi4lite_r_ready(io_dcache_axi4lite_r_ready), + .io_dcache_axi4lite_w_valid(io_dcache_axi4lite_w_valid), + .io_dcache_axi4lite_w_bits_data(io_dcache_axi4lite_w_bits_data), + .io_dcache_axi4lite_w_bits_strb(io_dcache_axi4lite_w_bits_strb) + ); + Icache_for_Verilator icache( + .clock(CLK), + .reset(!RST), + .io_ar_valid(io_icache_axi4lite_ar_valid), + .io_ar_bits_addr(io_icache_axi4lite_ar_bits_addr), + .io_ar_bits_prot(io_icache_axi4lite_ar_bits_prot), + .io_aw_valid(io_icache_axi4lite_aw_valid), + .io_aw_bits_addr(io_icache_axi4lite_aw_bits_addr), + .io_aw_bits_prot(io_icache_axi4lite_aw_bits_prot), + .io_b_ready(io_icache_axi4lite_b_ready), + .io_r_ready(io_icache_axi4lite_r_ready), + .io_w_valid(io_icache_axi4lite_w_valid), + .io_w_bits_data(io_icache_axi4lite_w_bits_data), + .io_w_bits_strb(io_icache_axi4lite_w_bits_strb), + .io_ar_ready(io_icache_axi4lite_ar_ready), + .io_aw_ready(io_icache_axi4lite_aw_ready), + .io_b_valid(io_icache_axi4lite_b_valid), + .io_b_bits_resp(io_icache_axi4lite_b_bits_resp), + .io_r_valid(io_icache_axi4lite_r_valid), + .io_r_bits_data(io_icache_axi4lite_r_bits_data), + .io_r_bits_resp(io_icache_axi4lite_r_bits_resp), + .io_w_ready() + ); + Dcache_for_Verilator dcache( + .clock(CLK), + .reset(!RST), + .io_ar_valid(io_dcache_axi4lite_ar_valid), + .io_ar_bits_addr(io_dcache_axi4lite_ar_bits_addr), + .io_ar_bits_prot(io_dcache_axi4lite_ar_bits_prot), + .io_aw_valid(io_dcache_axi4lite_aw_valid), + .io_aw_bits_addr(io_dcache_axi4lite_aw_bits_addr), + .io_aw_bits_prot(io_dcache_axi4lite_aw_bits_prot), + .io_b_ready(io_dcache_axi4lite_b_ready), + .io_r_ready(io_dcache_axi4lite_r_ready), + .io_w_valid(io_dcache_axi4lite_w_valid), + .io_w_bits_data(io_dcache_axi4lite_w_bits_data), + .io_w_bits_strb(io_dcache_axi4lite_w_bits_strb), + .io_ar_ready(io_dcache_axi4lite_ar_ready), + .io_aw_ready(io_dcache_axi4lite_aw_ready), + .io_b_valid(io_dcache_axi4lite_b_valid), + .io_b_bits_resp(io_dcache_axi4lite_b_bits_resp), + .io_r_valid(io_dcache_axi4lite_r_valid), + .io_r_bits_data(io_dcache_axi4lite_r_bits_data), + .io_r_bits_resp(io_dcache_axi4lite_r_bits_resp), + .io_w_ready(io_dcache_axi4lite_w_ready), + .debug_valid(), + .debug_bits(tohost_bits) + ); + + assign tohost = tohost_bits; +endmodule From 4aeec6a79802968c1bd09a3f64d9ef413fc1c16f Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Wed, 29 Nov 2023 18:25:36 +0900 Subject: [PATCH 06/13] a --- .gitignore | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 9b0e9ca2..b6f33998 100644 --- a/.gitignore +++ b/.gitignore @@ -132,7 +132,8 @@ local.properties # Chisel Outputs *.anno.json *.fir -*.v +# outputs only SystemVerilog +# *.v *.sv # Debug files From de85618addf262a5d5fb86aa432902d3f67f95c7 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Wed, 29 Nov 2023 18:38:22 +0900 Subject: [PATCH 07/13] a --- .../applications_for_fpga/headers/crt.S | 163 +- .../applications_for_fpga/headers/encoding.h | 5014 +---------------- .../applications_for_fpga/headers/test.ld | 67 +- 3 files changed, 3 insertions(+), 5241 deletions(-) mode change 100644 => 120000 src/main/resources/applications_for_fpga/headers/crt.S mode change 100644 => 120000 src/main/resources/applications_for_fpga/headers/encoding.h mode change 100644 => 120000 src/main/resources/applications_for_fpga/headers/test.ld diff --git a/src/main/resources/applications_for_fpga/headers/crt.S b/src/main/resources/applications_for_fpga/headers/crt.S deleted file mode 100644 index a2f8fca5..00000000 --- a/src/main/resources/applications_for_fpga/headers/crt.S +++ /dev/null @@ -1,162 +0,0 @@ -# See LICENSE for license details. - -#include "encoding.h" - -#if __riscv_xlen == 64 -# define LREG ld -# define SREG sd -# define REGBYTES 8 -#else -# define LREG lw -# define SREG sw -# define REGBYTES 4 -#endif - - .section ".text.init" - .globl _start -_start: - li x1, 0 - li x2, 0 - li x3, 0 - li x4, 0 - li x5, 0 - li x6, 0 - li x7, 0 - li x8, 0 - li x9, 0 - li x10,0 - li x11,0 - li x12,0 - li x13,0 - li x14,0 - li x15,0 - li x16,0 - li x17,0 - li x18,0 - li x19,0 - li x20,0 - li x21,0 - li x22,0 - li x23,0 - li x24,0 - li x25,0 - li x26,0 - li x27,0 - li x28,0 - li x29,0 - li x30,0 - li x31,0 - - # initialize trap vector - la t0, trap_entry - csrw mtvec, t0 - - # initialize global pointer -.option push -.option norelax - la gp, __global_pointer$ -.option pop - - la tp, _end + 63 - and tp, tp, -64 - - # get core id - csrr a0, mhartid - # for now, assume only 1 core - li a1, 1 -1:bgeu a0, a1, 1b - - # initialise stack pointer - li sp, 0x00005FF0 - - j _init - - .align 2 -trap_entry: - addi sp, sp, -272 - - SREG x1, 1*REGBYTES(sp) - SREG x2, 2*REGBYTES(sp) - SREG x3, 3*REGBYTES(sp) - SREG x4, 4*REGBYTES(sp) - SREG x5, 5*REGBYTES(sp) - SREG x6, 6*REGBYTES(sp) - SREG x7, 7*REGBYTES(sp) - SREG x8, 8*REGBYTES(sp) - SREG x9, 9*REGBYTES(sp) - SREG x10, 10*REGBYTES(sp) - SREG x11, 11*REGBYTES(sp) - SREG x12, 12*REGBYTES(sp) - SREG x13, 13*REGBYTES(sp) - SREG x14, 14*REGBYTES(sp) - SREG x15, 15*REGBYTES(sp) - SREG x16, 16*REGBYTES(sp) - SREG x17, 17*REGBYTES(sp) - SREG x18, 18*REGBYTES(sp) - SREG x19, 19*REGBYTES(sp) - SREG x20, 20*REGBYTES(sp) - SREG x21, 21*REGBYTES(sp) - SREG x22, 22*REGBYTES(sp) - SREG x23, 23*REGBYTES(sp) - SREG x24, 24*REGBYTES(sp) - SREG x25, 25*REGBYTES(sp) - SREG x26, 26*REGBYTES(sp) - SREG x27, 27*REGBYTES(sp) - SREG x28, 28*REGBYTES(sp) - SREG x29, 29*REGBYTES(sp) - SREG x30, 30*REGBYTES(sp) - SREG x31, 31*REGBYTES(sp) - - csrr a0, mcause - csrr a1, mepc - mv a2, sp - jal handle_trap - csrw mepc, a0 - - # Remain in M-mode after eret - # we can write to mstatus but core supports only M-mode and ignore this - li t0, MSTATUS_MPP - csrs mstatus, t0 - - LREG x1, 1*REGBYTES(sp) - LREG x2, 2*REGBYTES(sp) - LREG x3, 3*REGBYTES(sp) - LREG x4, 4*REGBYTES(sp) - LREG x5, 5*REGBYTES(sp) - LREG x6, 6*REGBYTES(sp) - LREG x7, 7*REGBYTES(sp) - LREG x8, 8*REGBYTES(sp) - LREG x9, 9*REGBYTES(sp) - LREG x10, 10*REGBYTES(sp) - LREG x11, 11*REGBYTES(sp) - LREG x12, 12*REGBYTES(sp) - LREG x13, 13*REGBYTES(sp) - LREG x14, 14*REGBYTES(sp) - LREG x15, 15*REGBYTES(sp) - LREG x16, 16*REGBYTES(sp) - LREG x17, 17*REGBYTES(sp) - LREG x18, 18*REGBYTES(sp) - LREG x19, 19*REGBYTES(sp) - LREG x20, 20*REGBYTES(sp) - LREG x21, 21*REGBYTES(sp) - LREG x22, 22*REGBYTES(sp) - LREG x23, 23*REGBYTES(sp) - LREG x24, 24*REGBYTES(sp) - LREG x25, 25*REGBYTES(sp) - LREG x26, 26*REGBYTES(sp) - LREG x27, 27*REGBYTES(sp) - LREG x28, 28*REGBYTES(sp) - LREG x29, 29*REGBYTES(sp) - LREG x30, 30*REGBYTES(sp) - LREG x31, 31*REGBYTES(sp) - - addi sp, sp, 272 - mret - -.section ".tohost","aw",@progbits -.align 6 -.globl tohost -tohost: .dword 0 -.align 6 -.globl fromhost -fromhost: .dword 0 diff --git a/src/main/resources/applications_for_fpga/headers/crt.S b/src/main/resources/applications_for_fpga/headers/crt.S new file mode 120000 index 00000000..eb05ab05 --- /dev/null +++ b/src/main/resources/applications_for_fpga/headers/crt.S @@ -0,0 +1 @@ +../../application_headers/crt.S \ No newline at end of file diff --git a/src/main/resources/applications_for_fpga/headers/encoding.h b/src/main/resources/applications_for_fpga/headers/encoding.h deleted file mode 100644 index 01889d1a..00000000 --- a/src/main/resources/applications_for_fpga/headers/encoding.h +++ /dev/null @@ -1,5013 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ - -/* Copyright (c) 2023 RISC-V International */ - -/* - * This file is auto-generated by running 'make' in - * https://github.com/riscv/riscv-opcodes (02b4866) - */ - -#ifndef RISCV_CSR_ENCODING_H -#define RISCV_CSR_ENCODING_H - -#define MSTATUS_UIE 0x00000001 -#define MSTATUS_SIE 0x00000002 -#define MSTATUS_HIE 0x00000004 -#define MSTATUS_MIE 0x00000008 -#define MSTATUS_UPIE 0x00000010 -#define MSTATUS_SPIE 0x00000020 -#define MSTATUS_UBE 0x00000040 -#define MSTATUS_MPIE 0x00000080 -#define MSTATUS_SPP 0x00000100 -#define MSTATUS_VS 0x00000600 -#define MSTATUS_MPP 0x00001800 -#define MSTATUS_FS 0x00006000 -#define MSTATUS_XS 0x00018000 -#define MSTATUS_MPRV 0x00020000 -#define MSTATUS_SUM 0x00040000 -#define MSTATUS_MXR 0x00080000 -#define MSTATUS_TVM 0x00100000 -#define MSTATUS_TW 0x00200000 -#define MSTATUS_TSR 0x00400000 -#define MSTATUS32_SD 0x80000000 -#define MSTATUS_UXL 0x0000000300000000 -#define MSTATUS_SXL 0x0000000C00000000 -#define MSTATUS_SBE 0x0000001000000000 -#define MSTATUS_MBE 0x0000002000000000 -#define MSTATUS_GVA 0x0000004000000000 -#define MSTATUS_MPV 0x0000008000000000 -#define MSTATUS64_SD 0x8000000000000000 - -#define MSTATUSH_SBE 0x00000010 -#define MSTATUSH_MBE 0x00000020 -#define MSTATUSH_GVA 0x00000040 -#define MSTATUSH_MPV 0x00000080 - -#define SSTATUS_UIE 0x00000001 -#define SSTATUS_SIE 0x00000002 -#define SSTATUS_UPIE 0x00000010 -#define SSTATUS_SPIE 0x00000020 -#define SSTATUS_UBE 0x00000040 -#define SSTATUS_SPP 0x00000100 -#define SSTATUS_VS 0x00000600 -#define SSTATUS_FS 0x00006000 -#define SSTATUS_XS 0x00018000 -#define SSTATUS_SUM 0x00040000 -#define SSTATUS_MXR 0x00080000 -#define SSTATUS32_SD 0x80000000 -#define SSTATUS_UXL 0x0000000300000000 -#define SSTATUS64_SD 0x8000000000000000 - -#define HSTATUS_VSXL 0x300000000 -#define HSTATUS_VTSR 0x00400000 -#define HSTATUS_VTW 0x00200000 -#define HSTATUS_VTVM 0x00100000 -#define HSTATUS_VGEIN 0x0003f000 -#define HSTATUS_HU 0x00000200 -#define HSTATUS_SPVP 0x00000100 -#define HSTATUS_SPV 0x00000080 -#define HSTATUS_GVA 0x00000040 -#define HSTATUS_VSBE 0x00000020 - -#define USTATUS_UIE 0x00000001 -#define USTATUS_UPIE 0x00000010 - -#define MNSTATUS_NMIE 0x00000008 -#define MNSTATUS_MNPP 0x00001800 -#define MNSTATUS_MNPV 0x00000080 - -#define DCSR_XDEBUGVER (3U<<30) -#define DCSR_NDRESET (1<<29) -#define DCSR_FULLRESET (1<<28) -#define DCSR_EBREAKM (1<<15) -#define DCSR_EBREAKH (1<<14) -#define DCSR_EBREAKS (1<<13) -#define DCSR_EBREAKU (1<<12) -#define DCSR_STOPCYCLE (1<<10) -#define DCSR_STOPTIME (1<<9) -#define DCSR_CAUSE (7<<6) -#define DCSR_DEBUGINT (1<<5) -#define DCSR_HALT (1<<3) -#define DCSR_STEP (1<<2) -#define DCSR_PRV (3<<0) - -#define DCSR_CAUSE_NONE 0 -#define DCSR_CAUSE_SWBP 1 -#define DCSR_CAUSE_HWBP 2 -#define DCSR_CAUSE_DEBUGINT 3 -#define DCSR_CAUSE_STEP 4 -#define DCSR_CAUSE_HALT 5 -#define DCSR_CAUSE_GROUP 6 - -#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) -#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) -#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) - -#define MCONTROL_SELECT (1<<19) -#define MCONTROL_TIMING (1<<18) -#define MCONTROL_ACTION (0x3f<<12) -#define MCONTROL_CHAIN (1<<11) -#define MCONTROL_MATCH (0xf<<7) -#define MCONTROL_M (1<<6) -#define MCONTROL_H (1<<5) -#define MCONTROL_S (1<<4) -#define MCONTROL_U (1<<3) -#define MCONTROL_EXECUTE (1<<2) -#define MCONTROL_STORE (1<<1) -#define MCONTROL_LOAD (1<<0) - -#define MCONTROL_TYPE_NONE 0 -#define MCONTROL_TYPE_MATCH 2 - -#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 -#define MCONTROL_ACTION_DEBUG_MODE 1 -#define MCONTROL_ACTION_TRACE_START 2 -#define MCONTROL_ACTION_TRACE_STOP 3 -#define MCONTROL_ACTION_TRACE_EMIT 4 - -#define MCONTROL_MATCH_EQUAL 0 -#define MCONTROL_MATCH_NAPOT 1 -#define MCONTROL_MATCH_GE 2 -#define MCONTROL_MATCH_LT 3 -#define MCONTROL_MATCH_MASK_LOW 4 -#define MCONTROL_MATCH_MASK_HIGH 5 - -#define MIP_USIP (1 << IRQ_U_SOFT) -#define MIP_SSIP (1 << IRQ_S_SOFT) -#define MIP_VSSIP (1 << IRQ_VS_SOFT) -#define MIP_MSIP (1 << IRQ_M_SOFT) -#define MIP_UTIP (1 << IRQ_U_TIMER) -#define MIP_STIP (1 << IRQ_S_TIMER) -#define MIP_VSTIP (1 << IRQ_VS_TIMER) -#define MIP_MTIP (1 << IRQ_M_TIMER) -#define MIP_UEIP (1 << IRQ_U_EXT) -#define MIP_SEIP (1 << IRQ_S_EXT) -#define MIP_VSEIP (1 << IRQ_VS_EXT) -#define MIP_MEIP (1 << IRQ_M_EXT) -#define MIP_SGEIP (1 << IRQ_S_GEXT) -#define MIP_LCOFIP (1 << IRQ_LCOF) - -#define MIP_S_MASK (MIP_SSIP | MIP_STIP | MIP_SEIP) -#define MIP_VS_MASK (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) -#define MIP_HS_MASK (MIP_VS_MASK | MIP_SGEIP) - -#define MIDELEG_FORCED_MASK MIP_HS_MASK - -#define SIP_SSIP MIP_SSIP -#define SIP_STIP MIP_STIP - -#define MENVCFG_FIOM 0x00000001 -#define MENVCFG_CBIE 0x00000030 -#define MENVCFG_CBCFE 0x00000040 -#define MENVCFG_CBZE 0x00000080 -#define MENVCFG_HADE 0x2000000000000000 -#define MENVCFG_PBMTE 0x4000000000000000 -#define MENVCFG_STCE 0x8000000000000000 - -#define MENVCFGH_HADE 0x20000000 -#define MENVCFGH_PBMTE 0x40000000 -#define MENVCFGH_STCE 0x80000000 - -#define MSTATEEN0_CS 0x00000001 -#define MSTATEEN0_FCSR 0x00000002 -#define MSTATEEN0_JVT 0x00000004 -#define MSTATEEN0_HCONTEXT 0x0200000000000000 -#define MSTATEEN0_HENVCFG 0x4000000000000000 -#define MSTATEEN_HSTATEEN 0x8000000000000000 - -#define MSTATEEN0H_HCONTEXT 0x02000000 -#define MSTATEEN0H_HENVCFG 0x40000000 -#define MSTATEENH_HSTATEEN 0x80000000 - -#define MHPMEVENT_VUINH 0x0400000000000000 -#define MHPMEVENT_VSINH 0x0800000000000000 -#define MHPMEVENT_UINH 0x1000000000000000 -#define MHPMEVENT_SINH 0x2000000000000000 -#define MHPMEVENT_MINH 0x4000000000000000 -#define MHPMEVENT_OF 0x8000000000000000 - -#define MHPMEVENTH_VUINH 0x04000000 -#define MHPMEVENTH_VSINH 0x08000000 -#define MHPMEVENTH_UINH 0x10000000 -#define MHPMEVENTH_SINH 0x20000000 -#define MHPMEVENTH_MINH 0x40000000 -#define MHPMEVENTH_OF 0x80000000 - -#define HENVCFG_FIOM 0x00000001 -#define HENVCFG_CBIE 0x00000030 -#define HENVCFG_CBCFE 0x00000040 -#define HENVCFG_CBZE 0x00000080 -#define HENVCFG_HADE 0x2000000000000000 -#define HENVCFG_PBMTE 0x4000000000000000 -#define HENVCFG_STCE 0x8000000000000000 - -#define HENVCFGH_HADE 0x20000000 -#define HENVCFGH_PBMTE 0x40000000 -#define HENVCFGH_STCE 0x80000000 - -#define HSTATEEN0_CS 0x00000001 -#define HSTATEEN0_FCSR 0x00000002 -#define HSTATEEN0_JVT 0x00000004 -#define HSTATEEN0_SCONTEXT 0x0200000000000000 -#define HSTATEEN0_SENVCFG 0x4000000000000000 -#define HSTATEEN_SSTATEEN 0x8000000000000000 - -#define HSTATEEN0H_SCONTEXT 0x02000000 -#define HSTATEEN0H_SENVCFG 0x40000000 -#define HSTATEENH_SSTATEEN 0x80000000 - -#define SENVCFG_FIOM 0x00000001 -#define SENVCFG_CBIE 0x00000030 -#define SENVCFG_CBCFE 0x00000040 -#define SENVCFG_CBZE 0x00000080 - -#define SSTATEEN0_CS 0x00000001 -#define SSTATEEN0_FCSR 0x00000002 -#define SSTATEEN0_JVT 0x00000004 - -#define MSECCFG_MML 0x00000001 -#define MSECCFG_MMWP 0x00000002 -#define MSECCFG_RLB 0x00000004 -#define MSECCFG_USEED 0x00000100 -#define MSECCFG_SSEED 0x00000200 - -/* jvt fields */ -#define JVT_MODE 0x3F -#define JVT_BASE (~0x3F) - -#define PRV_U 0 -#define PRV_S 1 -#define PRV_M 3 - -#define PRV_HS (PRV_S + 1) - -#define SATP32_MODE 0x80000000 -#define SATP32_ASID 0x7FC00000 -#define SATP32_PPN 0x003FFFFF -#define SATP64_MODE 0xF000000000000000 -#define SATP64_ASID 0x0FFFF00000000000 -#define SATP64_PPN 0x00000FFFFFFFFFFF - -#define SATP_MODE_OFF 0 -#define SATP_MODE_SV32 1 -#define SATP_MODE_SV39 8 -#define SATP_MODE_SV48 9 -#define SATP_MODE_SV57 10 -#define SATP_MODE_SV64 11 - -#define HGATP32_MODE 0x80000000 -#define HGATP32_VMID 0x1FC00000 -#define HGATP32_PPN 0x003FFFFF - -#define HGATP64_MODE 0xF000000000000000 -#define HGATP64_VMID 0x03FFF00000000000 -#define HGATP64_PPN 0x00000FFFFFFFFFFF - -#define HGATP_MODE_OFF 0 -#define HGATP_MODE_SV32X4 1 -#define HGATP_MODE_SV39X4 8 -#define HGATP_MODE_SV48X4 9 -#define HGATP_MODE_SV57X4 10 - -#define PMP_R 0x01 -#define PMP_W 0x02 -#define PMP_X 0x04 -#define PMP_A 0x18 -#define PMP_L 0x80 -#define PMP_SHIFT 2 - -#define PMP_TOR 0x08 -#define PMP_NA4 0x10 -#define PMP_NAPOT 0x18 - -#define IRQ_U_SOFT 0 -#define IRQ_S_SOFT 1 -#define IRQ_VS_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_U_TIMER 4 -#define IRQ_S_TIMER 5 -#define IRQ_VS_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_U_EXT 8 -#define IRQ_S_EXT 9 -#define IRQ_VS_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_S_GEXT 12 -#define IRQ_COP 12 -#define IRQ_LCOF 13 - -#define DEFAULT_RSTVEC 0x00001000 -#define CLINT_BASE 0x02000000 -#define CLINT_SIZE 0x000c0000 -#define EXT_IO_BASE 0x40000000 -#define DRAM_BASE 0x80000000 - -/* page table entry (PTE) fields */ -#define PTE_V 0x001 /* Valid */ -#define PTE_R 0x002 /* Read */ -#define PTE_W 0x004 /* Write */ -#define PTE_X 0x008 /* Execute */ -#define PTE_U 0x010 /* User */ -#define PTE_G 0x020 /* Global */ -#define PTE_A 0x040 /* Accessed */ -#define PTE_D 0x080 /* Dirty */ -#define PTE_SOFT 0x300 /* Reserved for Software */ -#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */ -#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */ -#define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */ -#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */ - -#define PTE_PPN_SHIFT 10 - -#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) - -#ifdef __riscv - -#if __riscv_xlen == 64 -# define MSTATUS_SD MSTATUS64_SD -# define SSTATUS_SD SSTATUS64_SD -# define RISCV_PGLEVEL_BITS 9 -# define SATP_MODE SATP64_MODE -#else -# define MSTATUS_SD MSTATUS32_SD -# define SSTATUS_SD SSTATUS32_SD -# define RISCV_PGLEVEL_BITS 10 -# define SATP_MODE SATP32_MODE -#endif -#define RISCV_PGSHIFT 12 -#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) - -#ifndef __ASSEMBLER__ - -#ifdef __GNUC__ - -#define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define write_csr(reg, val) ({ \ - asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) - -#define swap_csr(reg, val) ({ unsigned long __tmp; \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ - __tmp; }) - -#define set_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; }) - -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; }) - -#define rdtime() read_csr(time) -#define rdcycle() read_csr(cycle) -#define rdinstret() read_csr(instret) - -#endif - -#endif - -#endif - -#endif - -/* Automatically generated by parse_opcodes. */ -#ifndef RISCV_ENCODING_H -#define RISCV_ENCODING_H -#define MATCH_ADD 0x33 -#define MASK_ADD 0xfe00707f -#define MATCH_ADD16 0x40000077 -#define MASK_ADD16 0xfe00707f -#define MATCH_ADD32 0x40002077 -#define MASK_ADD32 0xfe00707f -#define MATCH_ADD64 0xc0001077 -#define MASK_ADD64 0xfe00707f -#define MATCH_ADD8 0x48000077 -#define MASK_ADD8 0xfe00707f -#define MATCH_ADD_UW 0x800003b -#define MASK_ADD_UW 0xfe00707f -#define MATCH_ADDI 0x13 -#define MASK_ADDI 0x707f -#define MATCH_ADDIW 0x1b -#define MASK_ADDIW 0x707f -#define MATCH_ADDW 0x3b -#define MASK_ADDW 0xfe00707f -#define MATCH_AES32DSI 0x2a000033 -#define MASK_AES32DSI 0x3e00707f -#define MATCH_AES32DSMI 0x2e000033 -#define MASK_AES32DSMI 0x3e00707f -#define MATCH_AES32ESI 0x22000033 -#define MASK_AES32ESI 0x3e00707f -#define MATCH_AES32ESMI 0x26000033 -#define MASK_AES32ESMI 0x3e00707f -#define MATCH_AES64DS 0x3a000033 -#define MASK_AES64DS 0xfe00707f -#define MATCH_AES64DSM 0x3e000033 -#define MASK_AES64DSM 0xfe00707f -#define MATCH_AES64ES 0x32000033 -#define MASK_AES64ES 0xfe00707f -#define MATCH_AES64ESM 0x36000033 -#define MASK_AES64ESM 0xfe00707f -#define MATCH_AES64IM 0x30001013 -#define MASK_AES64IM 0xfff0707f -#define MATCH_AES64KS1I 0x31001013 -#define MASK_AES64KS1I 0xff00707f -#define MATCH_AES64KS2 0x7e000033 -#define MASK_AES64KS2 0xfe00707f -#define MATCH_AMOADD_D 0x302f -#define MASK_AMOADD_D 0xf800707f -#define MATCH_AMOADD_W 0x202f -#define MASK_AMOADD_W 0xf800707f -#define MATCH_AMOAND_D 0x6000302f -#define MASK_AMOAND_D 0xf800707f -#define MATCH_AMOAND_W 0x6000202f -#define MASK_AMOAND_W 0xf800707f -#define MATCH_AMOMAX_D 0xa000302f -#define MASK_AMOMAX_D 0xf800707f -#define MATCH_AMOMAX_W 0xa000202f -#define MASK_AMOMAX_W 0xf800707f -#define MATCH_AMOMAXU_D 0xe000302f -#define MASK_AMOMAXU_D 0xf800707f -#define MATCH_AMOMAXU_W 0xe000202f -#define MASK_AMOMAXU_W 0xf800707f -#define MATCH_AMOMIN_D 0x8000302f -#define MASK_AMOMIN_D 0xf800707f -#define MATCH_AMOMIN_W 0x8000202f -#define MASK_AMOMIN_W 0xf800707f -#define MATCH_AMOMINU_D 0xc000302f -#define MASK_AMOMINU_D 0xf800707f -#define MATCH_AMOMINU_W 0xc000202f -#define MASK_AMOMINU_W 0xf800707f -#define MATCH_AMOOR_D 0x4000302f -#define MASK_AMOOR_D 0xf800707f -#define MATCH_AMOOR_W 0x4000202f -#define MASK_AMOOR_W 0xf800707f -#define MATCH_AMOSWAP_D 0x800302f -#define MASK_AMOSWAP_D 0xf800707f -#define MATCH_AMOSWAP_W 0x800202f -#define MASK_AMOSWAP_W 0xf800707f -#define MATCH_AMOXOR_D 0x2000302f -#define MASK_AMOXOR_D 0xf800707f -#define MATCH_AMOXOR_W 0x2000202f -#define MASK_AMOXOR_W 0xf800707f -#define MATCH_AND 0x7033 -#define MASK_AND 0xfe00707f -#define MATCH_ANDI 0x7013 -#define MASK_ANDI 0x707f -#define MATCH_ANDN 0x40007033 -#define MASK_ANDN 0xfe00707f -#define MATCH_AUIPC 0x17 -#define MASK_AUIPC 0x7f -#define MATCH_AVE 0xe0000077 -#define MASK_AVE 0xfe00707f -#define MATCH_BCLR 0x48001033 -#define MASK_BCLR 0xfe00707f -#define MATCH_BCLRI 0x48001013 -#define MASK_BCLRI 0xfc00707f -#define MATCH_BCOMPRESS 0x8006033 -#define MASK_BCOMPRESS 0xfe00707f -#define MATCH_BCOMPRESSW 0x800603b -#define MASK_BCOMPRESSW 0xfe00707f -#define MATCH_BDECOMPRESS 0x48006033 -#define MASK_BDECOMPRESS 0xfe00707f -#define MATCH_BDECOMPRESSW 0x4800603b -#define MASK_BDECOMPRESSW 0xfe00707f -#define MATCH_BEQ 0x63 -#define MASK_BEQ 0x707f -#define MATCH_BEXT 0x48005033 -#define MASK_BEXT 0xfe00707f -#define MATCH_BEXTI 0x48005013 -#define MASK_BEXTI 0xfc00707f -#define MATCH_BFP 0x48007033 -#define MASK_BFP 0xfe00707f -#define MATCH_BFPW 0x4800703b -#define MASK_BFPW 0xfe00707f -#define MATCH_BGE 0x5063 -#define MASK_BGE 0x707f -#define MATCH_BGEU 0x7063 -#define MASK_BGEU 0x707f -#define MATCH_BINV 0x68001033 -#define MASK_BINV 0xfe00707f -#define MATCH_BINVI 0x68001013 -#define MASK_BINVI 0xfc00707f -#define MATCH_BLT 0x4063 -#define MASK_BLT 0x707f -#define MATCH_BLTU 0x6063 -#define MASK_BLTU 0x707f -#define MATCH_BMATFLIP 0x60301013 -#define MASK_BMATFLIP 0xfff0707f -#define MATCH_BMATOR 0x8003033 -#define MASK_BMATOR 0xfe00707f -#define MATCH_BMATXOR 0x48003033 -#define MASK_BMATXOR 0xfe00707f -#define MATCH_BNE 0x1063 -#define MASK_BNE 0x707f -#define MATCH_BSET 0x28001033 -#define MASK_BSET 0xfe00707f -#define MATCH_BSETI 0x28001013 -#define MASK_BSETI 0xfc00707f -#define MATCH_C_ADD 0x9002 -#define MASK_C_ADD 0xf003 -#define MATCH_C_ADDI 0x1 -#define MASK_C_ADDI 0xe003 -#define MATCH_C_ADDI16SP 0x6101 -#define MASK_C_ADDI16SP 0xef83 -#define MATCH_C_ADDI4SPN 0x0 -#define MASK_C_ADDI4SPN 0xe003 -#define MATCH_C_ADDIW 0x2001 -#define MASK_C_ADDIW 0xe003 -#define MATCH_C_ADDW 0x9c21 -#define MASK_C_ADDW 0xfc63 -#define MATCH_C_AND 0x8c61 -#define MASK_C_AND 0xfc63 -#define MATCH_C_ANDI 0x8801 -#define MASK_C_ANDI 0xec03 -#define MATCH_C_BEQZ 0xc001 -#define MASK_C_BEQZ 0xe003 -#define MATCH_C_BNEZ 0xe001 -#define MASK_C_BNEZ 0xe003 -#define MATCH_C_EBREAK 0x9002 -#define MASK_C_EBREAK 0xffff -#define MATCH_C_FLD 0x2000 -#define MASK_C_FLD 0xe003 -#define MATCH_C_FLDSP 0x2002 -#define MASK_C_FLDSP 0xe003 -#define MATCH_C_FLW 0x6000 -#define MASK_C_FLW 0xe003 -#define MATCH_C_FLWSP 0x6002 -#define MASK_C_FLWSP 0xe003 -#define MATCH_C_FSD 0xa000 -#define MASK_C_FSD 0xe003 -#define MATCH_C_FSDSP 0xa002 -#define MASK_C_FSDSP 0xe003 -#define MATCH_C_FSW 0xe000 -#define MASK_C_FSW 0xe003 -#define MATCH_C_FSWSP 0xe002 -#define MASK_C_FSWSP 0xe003 -#define MATCH_C_J 0xa001 -#define MASK_C_J 0xe003 -#define MATCH_C_JAL 0x2001 -#define MASK_C_JAL 0xe003 -#define MATCH_C_JALR 0x9002 -#define MASK_C_JALR 0xf07f -#define MATCH_C_JR 0x8002 -#define MASK_C_JR 0xf07f -#define MATCH_C_LBU 0x8000 -#define MASK_C_LBU 0xfc03 -#define MATCH_C_LD 0x6000 -#define MASK_C_LD 0xe003 -#define MATCH_C_LDSP 0x6002 -#define MASK_C_LDSP 0xe003 -#define MATCH_C_LH 0x8440 -#define MASK_C_LH 0xfc43 -#define MATCH_C_LHU 0x8400 -#define MASK_C_LHU 0xfc43 -#define MATCH_C_LI 0x4001 -#define MASK_C_LI 0xe003 -#define MATCH_C_LUI 0x6001 -#define MASK_C_LUI 0xe003 -#define MATCH_C_LW 0x4000 -#define MASK_C_LW 0xe003 -#define MATCH_C_LWSP 0x4002 -#define MASK_C_LWSP 0xe003 -#define MATCH_C_MUL 0x9c41 -#define MASK_C_MUL 0xfc63 -#define MATCH_C_MV 0x8002 -#define MASK_C_MV 0xf003 -#define MATCH_C_NOP 0x1 -#define MASK_C_NOP 0xef83 -#define MATCH_C_NOT 0x9c75 -#define MASK_C_NOT 0xfc7f -#define MATCH_C_OR 0x8c41 -#define MASK_C_OR 0xfc63 -#define MATCH_C_SB 0x8800 -#define MASK_C_SB 0xfc03 -#define MATCH_C_SD 0xe000 -#define MASK_C_SD 0xe003 -#define MATCH_C_SDSP 0xe002 -#define MASK_C_SDSP 0xe003 -#define MATCH_C_SEXT_B 0x9c65 -#define MASK_C_SEXT_B 0xfc7f -#define MATCH_C_SEXT_H 0x9c6d -#define MASK_C_SEXT_H 0xfc7f -#define MATCH_C_SH 0x8c00 -#define MASK_C_SH 0xfc43 -#define MATCH_C_SLLI 0x2 -#define MASK_C_SLLI 0xe003 -#define MATCH_C_SRAI 0x8401 -#define MASK_C_SRAI 0xec03 -#define MATCH_C_SRLI 0x8001 -#define MASK_C_SRLI 0xec03 -#define MATCH_C_SUB 0x8c01 -#define MASK_C_SUB 0xfc63 -#define MATCH_C_SUBW 0x9c01 -#define MASK_C_SUBW 0xfc63 -#define MATCH_C_SW 0xc000 -#define MASK_C_SW 0xe003 -#define MATCH_C_SWSP 0xc002 -#define MASK_C_SWSP 0xe003 -#define MATCH_C_XOR 0x8c21 -#define MASK_C_XOR 0xfc63 -#define MATCH_C_ZEXT_B 0x9c61 -#define MASK_C_ZEXT_B 0xfc7f -#define MATCH_C_ZEXT_H 0x9c69 -#define MASK_C_ZEXT_H 0xfc7f -#define MATCH_C_ZEXT_W 0x9c71 -#define MASK_C_ZEXT_W 0xfc7f -#define MATCH_CBO_CLEAN 0x10200f -#define MASK_CBO_CLEAN 0xfff07fff -#define MATCH_CBO_FLUSH 0x20200f -#define MASK_CBO_FLUSH 0xfff07fff -#define MATCH_CBO_INVAL 0x200f -#define MASK_CBO_INVAL 0xfff07fff -#define MATCH_CBO_ZERO 0x40200f -#define MASK_CBO_ZERO 0xfff07fff -#define MATCH_CLMUL 0xa001033 -#define MASK_CLMUL 0xfe00707f -#define MATCH_CLMULH 0xa003033 -#define MASK_CLMULH 0xfe00707f -#define MATCH_CLMULR 0xa002033 -#define MASK_CLMULR 0xfe00707f -#define MATCH_CLRS16 0xae800077 -#define MASK_CLRS16 0xfff0707f -#define MATCH_CLRS32 0xaf800077 -#define MASK_CLRS32 0xfff0707f -#define MATCH_CLRS8 0xae000077 -#define MASK_CLRS8 0xfff0707f -#define MATCH_CLZ 0x60001013 -#define MASK_CLZ 0xfff0707f -#define MATCH_CLZ16 0xae900077 -#define MASK_CLZ16 0xfff0707f -#define MATCH_CLZ32 0xaf900077 -#define MASK_CLZ32 0xfff0707f -#define MATCH_CLZ8 0xae100077 -#define MASK_CLZ8 0xfff0707f -#define MATCH_CLZW 0x6000101b -#define MASK_CLZW 0xfff0707f -#define MATCH_CM_JALT 0xa002 -#define MASK_CM_JALT 0xfc03 -#define MATCH_CM_MVA01S 0xac62 -#define MASK_CM_MVA01S 0xfc63 -#define MATCH_CM_MVSA01 0xac22 -#define MASK_CM_MVSA01 0xfc63 -#define MATCH_CM_POP 0xba02 -#define MASK_CM_POP 0xff03 -#define MATCH_CM_POPRET 0xbe02 -#define MASK_CM_POPRET 0xff03 -#define MATCH_CM_POPRETZ 0xbc02 -#define MASK_CM_POPRETZ 0xff03 -#define MATCH_CM_PUSH 0xb802 -#define MASK_CM_PUSH 0xff03 -#define MATCH_CMIX 0x6001033 -#define MASK_CMIX 0x600707f -#define MATCH_CMOV 0x6005033 -#define MASK_CMOV 0x600707f -#define MATCH_CMPEQ16 0x4c000077 -#define MASK_CMPEQ16 0xfe00707f -#define MATCH_CMPEQ8 0x4e000077 -#define MASK_CMPEQ8 0xfe00707f -#define MATCH_CPOP 0x60201013 -#define MASK_CPOP 0xfff0707f -#define MATCH_CPOPW 0x6020101b -#define MASK_CPOPW 0xfff0707f -#define MATCH_CRAS16 0x44000077 -#define MASK_CRAS16 0xfe00707f -#define MATCH_CRAS32 0x44002077 -#define MASK_CRAS32 0xfe00707f -#define MATCH_CRC32_B 0x61001013 -#define MASK_CRC32_B 0xfff0707f -#define MATCH_CRC32_D 0x61301013 -#define MASK_CRC32_D 0xfff0707f -#define MATCH_CRC32_H 0x61101013 -#define MASK_CRC32_H 0xfff0707f -#define MATCH_CRC32_W 0x61201013 -#define MASK_CRC32_W 0xfff0707f -#define MATCH_CRC32C_B 0x61801013 -#define MASK_CRC32C_B 0xfff0707f -#define MATCH_CRC32C_D 0x61b01013 -#define MASK_CRC32C_D 0xfff0707f -#define MATCH_CRC32C_H 0x61901013 -#define MASK_CRC32C_H 0xfff0707f -#define MATCH_CRC32C_W 0x61a01013 -#define MASK_CRC32C_W 0xfff0707f -#define MATCH_CRSA16 0x46000077 -#define MASK_CRSA16 0xfe00707f -#define MATCH_CRSA32 0x46002077 -#define MASK_CRSA32 0xfe00707f -#define MATCH_CSRRC 0x3073 -#define MASK_CSRRC 0x707f -#define MATCH_CSRRCI 0x7073 -#define MASK_CSRRCI 0x707f -#define MATCH_CSRRS 0x2073 -#define MASK_CSRRS 0x707f -#define MATCH_CSRRSI 0x6073 -#define MASK_CSRRSI 0x707f -#define MATCH_CSRRW 0x1073 -#define MASK_CSRRW 0x707f -#define MATCH_CSRRWI 0x5073 -#define MASK_CSRRWI 0x707f -#define MATCH_CTZ 0x60101013 -#define MASK_CTZ 0xfff0707f -#define MATCH_CTZW 0x6010101b -#define MASK_CTZW 0xfff0707f -#define MATCH_CZERO_EQZ 0xe005033 -#define MASK_CZERO_EQZ 0xfe00707f -#define MATCH_CZERO_NEZ 0xe007033 -#define MASK_CZERO_NEZ 0xfe00707f -#define MATCH_DIV 0x2004033 -#define MASK_DIV 0xfe00707f -#define MATCH_DIVU 0x2005033 -#define MASK_DIVU 0xfe00707f -#define MATCH_DIVUW 0x200503b -#define MASK_DIVUW 0xfe00707f -#define MATCH_DIVW 0x200403b -#define MASK_DIVW 0xfe00707f -#define MATCH_DRET 0x7b200073 -#define MASK_DRET 0xffffffff -#define MATCH_EBREAK 0x100073 -#define MASK_EBREAK 0xffffffff -#define MATCH_ECALL 0x73 -#define MASK_ECALL 0xffffffff -#define MATCH_FADD_D 0x2000053 -#define MASK_FADD_D 0xfe00007f -#define MATCH_FADD_H 0x4000053 -#define MASK_FADD_H 0xfe00007f -#define MATCH_FADD_Q 0x6000053 -#define MASK_FADD_Q 0xfe00007f -#define MATCH_FADD_S 0x53 -#define MASK_FADD_S 0xfe00007f -#define MATCH_FCLASS_D 0xe2001053 -#define MASK_FCLASS_D 0xfff0707f -#define MATCH_FCLASS_H 0xe4001053 -#define MASK_FCLASS_H 0xfff0707f -#define MATCH_FCLASS_Q 0xe6001053 -#define MASK_FCLASS_Q 0xfff0707f -#define MATCH_FCLASS_S 0xe0001053 -#define MASK_FCLASS_S 0xfff0707f -#define MATCH_FCVT_D_H 0x42200053 -#define MASK_FCVT_D_H 0xfff0007f -#define MATCH_FCVT_D_L 0xd2200053 -#define MASK_FCVT_D_L 0xfff0007f -#define MATCH_FCVT_D_LU 0xd2300053 -#define MASK_FCVT_D_LU 0xfff0007f -#define MATCH_FCVT_D_Q 0x42300053 -#define MASK_FCVT_D_Q 0xfff0007f -#define MATCH_FCVT_D_S 0x42000053 -#define MASK_FCVT_D_S 0xfff0007f -#define MATCH_FCVT_D_W 0xd2000053 -#define MASK_FCVT_D_W 0xfff0007f -#define MATCH_FCVT_D_WU 0xd2100053 -#define MASK_FCVT_D_WU 0xfff0007f -#define MATCH_FCVT_H_D 0x44100053 -#define MASK_FCVT_H_D 0xfff0007f -#define MATCH_FCVT_H_L 0xd4200053 -#define MASK_FCVT_H_L 0xfff0007f -#define MATCH_FCVT_H_LU 0xd4300053 -#define MASK_FCVT_H_LU 0xfff0007f -#define MATCH_FCVT_H_Q 0x44300053 -#define MASK_FCVT_H_Q 0xfff0007f -#define MATCH_FCVT_H_S 0x44000053 -#define MASK_FCVT_H_S 0xfff0007f -#define MATCH_FCVT_H_W 0xd4000053 -#define MASK_FCVT_H_W 0xfff0007f -#define MATCH_FCVT_H_WU 0xd4100053 -#define MASK_FCVT_H_WU 0xfff0007f -#define MATCH_FCVT_L_D 0xc2200053 -#define MASK_FCVT_L_D 0xfff0007f -#define MATCH_FCVT_L_H 0xc4200053 -#define MASK_FCVT_L_H 0xfff0007f -#define MATCH_FCVT_L_Q 0xc6200053 -#define MASK_FCVT_L_Q 0xfff0007f -#define MATCH_FCVT_L_S 0xc0200053 -#define MASK_FCVT_L_S 0xfff0007f -#define MATCH_FCVT_LU_D 0xc2300053 -#define MASK_FCVT_LU_D 0xfff0007f -#define MATCH_FCVT_LU_H 0xc4300053 -#define MASK_FCVT_LU_H 0xfff0007f -#define MATCH_FCVT_LU_Q 0xc6300053 -#define MASK_FCVT_LU_Q 0xfff0007f -#define MATCH_FCVT_LU_S 0xc0300053 -#define MASK_FCVT_LU_S 0xfff0007f -#define MATCH_FCVT_Q_D 0x46100053 -#define MASK_FCVT_Q_D 0xfff0007f -#define MATCH_FCVT_Q_H 0x46200053 -#define MASK_FCVT_Q_H 0xfff0007f -#define MATCH_FCVT_Q_L 0xd6200053 -#define MASK_FCVT_Q_L 0xfff0007f -#define MATCH_FCVT_Q_LU 0xd6300053 -#define MASK_FCVT_Q_LU 0xfff0007f -#define MATCH_FCVT_Q_S 0x46000053 -#define MASK_FCVT_Q_S 0xfff0007f -#define MATCH_FCVT_Q_W 0xd6000053 -#define MASK_FCVT_Q_W 0xfff0007f -#define MATCH_FCVT_Q_WU 0xd6100053 -#define MASK_FCVT_Q_WU 0xfff0007f -#define MATCH_FCVT_S_D 0x40100053 -#define MASK_FCVT_S_D 0xfff0007f -#define MATCH_FCVT_S_H 0x40200053 -#define MASK_FCVT_S_H 0xfff0007f -#define MATCH_FCVT_S_L 0xd0200053 -#define MASK_FCVT_S_L 0xfff0007f -#define MATCH_FCVT_S_LU 0xd0300053 -#define MASK_FCVT_S_LU 0xfff0007f -#define MATCH_FCVT_S_Q 0x40300053 -#define MASK_FCVT_S_Q 0xfff0007f -#define MATCH_FCVT_S_W 0xd0000053 -#define MASK_FCVT_S_W 0xfff0007f -#define MATCH_FCVT_S_WU 0xd0100053 -#define MASK_FCVT_S_WU 0xfff0007f -#define MATCH_FCVT_W_D 0xc2000053 -#define MASK_FCVT_W_D 0xfff0007f -#define MATCH_FCVT_W_H 0xc4000053 -#define MASK_FCVT_W_H 0xfff0007f -#define MATCH_FCVT_W_Q 0xc6000053 -#define MASK_FCVT_W_Q 0xfff0007f -#define MATCH_FCVT_W_S 0xc0000053 -#define MASK_FCVT_W_S 0xfff0007f -#define MATCH_FCVT_WU_D 0xc2100053 -#define MASK_FCVT_WU_D 0xfff0007f -#define MATCH_FCVT_WU_H 0xc4100053 -#define MASK_FCVT_WU_H 0xfff0007f -#define MATCH_FCVT_WU_Q 0xc6100053 -#define MASK_FCVT_WU_Q 0xfff0007f -#define MATCH_FCVT_WU_S 0xc0100053 -#define MASK_FCVT_WU_S 0xfff0007f -#define MATCH_FDIV_D 0x1a000053 -#define MASK_FDIV_D 0xfe00007f -#define MATCH_FDIV_H 0x1c000053 -#define MASK_FDIV_H 0xfe00007f -#define MATCH_FDIV_Q 0x1e000053 -#define MASK_FDIV_Q 0xfe00007f -#define MATCH_FDIV_S 0x18000053 -#define MASK_FDIV_S 0xfe00007f -#define MATCH_FENCE 0xf -#define MASK_FENCE 0x707f -#define MATCH_FENCE_I 0x100f -#define MASK_FENCE_I 0x707f -#define MATCH_FEQ_D 0xa2002053 -#define MASK_FEQ_D 0xfe00707f -#define MATCH_FEQ_H 0xa4002053 -#define MASK_FEQ_H 0xfe00707f -#define MATCH_FEQ_Q 0xa6002053 -#define MASK_FEQ_Q 0xfe00707f -#define MATCH_FEQ_S 0xa0002053 -#define MASK_FEQ_S 0xfe00707f -#define MATCH_FLD 0x3007 -#define MASK_FLD 0x707f -#define MATCH_FLE_D 0xa2000053 -#define MASK_FLE_D 0xfe00707f -#define MATCH_FLE_H 0xa4000053 -#define MASK_FLE_H 0xfe00707f -#define MATCH_FLE_Q 0xa6000053 -#define MASK_FLE_Q 0xfe00707f -#define MATCH_FLE_S 0xa0000053 -#define MASK_FLE_S 0xfe00707f -#define MATCH_FLH 0x1007 -#define MASK_FLH 0x707f -#define MATCH_FLQ 0x4007 -#define MASK_FLQ 0x707f -#define MATCH_FLT_D 0xa2001053 -#define MASK_FLT_D 0xfe00707f -#define MATCH_FLT_H 0xa4001053 -#define MASK_FLT_H 0xfe00707f -#define MATCH_FLT_Q 0xa6001053 -#define MASK_FLT_Q 0xfe00707f -#define MATCH_FLT_S 0xa0001053 -#define MASK_FLT_S 0xfe00707f -#define MATCH_FLW 0x2007 -#define MASK_FLW 0x707f -#define MATCH_FMADD_D 0x2000043 -#define MASK_FMADD_D 0x600007f -#define MATCH_FMADD_H 0x4000043 -#define MASK_FMADD_H 0x600007f -#define MATCH_FMADD_Q 0x6000043 -#define MASK_FMADD_Q 0x600007f -#define MATCH_FMADD_S 0x43 -#define MASK_FMADD_S 0x600007f -#define MATCH_FMAX_D 0x2a001053 -#define MASK_FMAX_D 0xfe00707f -#define MATCH_FMAX_H 0x2c001053 -#define MASK_FMAX_H 0xfe00707f -#define MATCH_FMAX_Q 0x2e001053 -#define MASK_FMAX_Q 0xfe00707f -#define MATCH_FMAX_S 0x28001053 -#define MASK_FMAX_S 0xfe00707f -#define MATCH_FMIN_D 0x2a000053 -#define MASK_FMIN_D 0xfe00707f -#define MATCH_FMIN_H 0x2c000053 -#define MASK_FMIN_H 0xfe00707f -#define MATCH_FMIN_Q 0x2e000053 -#define MASK_FMIN_Q 0xfe00707f -#define MATCH_FMIN_S 0x28000053 -#define MASK_FMIN_S 0xfe00707f -#define MATCH_FMSUB_D 0x2000047 -#define MASK_FMSUB_D 0x600007f -#define MATCH_FMSUB_H 0x4000047 -#define MASK_FMSUB_H 0x600007f -#define MATCH_FMSUB_Q 0x6000047 -#define MASK_FMSUB_Q 0x600007f -#define MATCH_FMSUB_S 0x47 -#define MASK_FMSUB_S 0x600007f -#define MATCH_FMUL_D 0x12000053 -#define MASK_FMUL_D 0xfe00007f -#define MATCH_FMUL_H 0x14000053 -#define MASK_FMUL_H 0xfe00007f -#define MATCH_FMUL_Q 0x16000053 -#define MASK_FMUL_Q 0xfe00007f -#define MATCH_FMUL_S 0x10000053 -#define MASK_FMUL_S 0xfe00007f -#define MATCH_FMV_D_X 0xf2000053 -#define MASK_FMV_D_X 0xfff0707f -#define MATCH_FMV_H_X 0xf4000053 -#define MASK_FMV_H_X 0xfff0707f -#define MATCH_FMV_W_X 0xf0000053 -#define MASK_FMV_W_X 0xfff0707f -#define MATCH_FMV_X_D 0xe2000053 -#define MASK_FMV_X_D 0xfff0707f -#define MATCH_FMV_X_H 0xe4000053 -#define MASK_FMV_X_H 0xfff0707f -#define MATCH_FMV_X_W 0xe0000053 -#define MASK_FMV_X_W 0xfff0707f -#define MATCH_FNMADD_D 0x200004f -#define MASK_FNMADD_D 0x600007f -#define MATCH_FNMADD_H 0x400004f -#define MASK_FNMADD_H 0x600007f -#define MATCH_FNMADD_Q 0x600004f -#define MASK_FNMADD_Q 0x600007f -#define MATCH_FNMADD_S 0x4f -#define MASK_FNMADD_S 0x600007f -#define MATCH_FNMSUB_D 0x200004b -#define MASK_FNMSUB_D 0x600007f -#define MATCH_FNMSUB_H 0x400004b -#define MASK_FNMSUB_H 0x600007f -#define MATCH_FNMSUB_Q 0x600004b -#define MASK_FNMSUB_Q 0x600007f -#define MATCH_FNMSUB_S 0x4b -#define MASK_FNMSUB_S 0x600007f -#define MATCH_FSD 0x3027 -#define MASK_FSD 0x707f -#define MATCH_FSGNJ_D 0x22000053 -#define MASK_FSGNJ_D 0xfe00707f -#define MATCH_FSGNJ_H 0x24000053 -#define MASK_FSGNJ_H 0xfe00707f -#define MATCH_FSGNJ_Q 0x26000053 -#define MASK_FSGNJ_Q 0xfe00707f -#define MATCH_FSGNJ_S 0x20000053 -#define MASK_FSGNJ_S 0xfe00707f -#define MATCH_FSGNJN_D 0x22001053 -#define MASK_FSGNJN_D 0xfe00707f -#define MATCH_FSGNJN_H 0x24001053 -#define MASK_FSGNJN_H 0xfe00707f -#define MATCH_FSGNJN_Q 0x26001053 -#define MASK_FSGNJN_Q 0xfe00707f -#define MATCH_FSGNJN_S 0x20001053 -#define MASK_FSGNJN_S 0xfe00707f -#define MATCH_FSGNJX_D 0x22002053 -#define MASK_FSGNJX_D 0xfe00707f -#define MATCH_FSGNJX_H 0x24002053 -#define MASK_FSGNJX_H 0xfe00707f -#define MATCH_FSGNJX_Q 0x26002053 -#define MASK_FSGNJX_Q 0xfe00707f -#define MATCH_FSGNJX_S 0x20002053 -#define MASK_FSGNJX_S 0xfe00707f -#define MATCH_FSH 0x1027 -#define MASK_FSH 0x707f -#define MATCH_FSL 0x4001033 -#define MASK_FSL 0x600707f -#define MATCH_FSLW 0x400103b -#define MASK_FSLW 0x600707f -#define MATCH_FSQ 0x4027 -#define MASK_FSQ 0x707f -#define MATCH_FSQRT_D 0x5a000053 -#define MASK_FSQRT_D 0xfff0007f -#define MATCH_FSQRT_H 0x5c000053 -#define MASK_FSQRT_H 0xfff0007f -#define MATCH_FSQRT_Q 0x5e000053 -#define MASK_FSQRT_Q 0xfff0007f -#define MATCH_FSQRT_S 0x58000053 -#define MASK_FSQRT_S 0xfff0007f -#define MATCH_FSR 0x4005033 -#define MASK_FSR 0x600707f -#define MATCH_FSRI 0x4005013 -#define MASK_FSRI 0x400707f -#define MATCH_FSRIW 0x400501b -#define MASK_FSRIW 0x600707f -#define MATCH_FSRW 0x400503b -#define MASK_FSRW 0x600707f -#define MATCH_FSUB_D 0xa000053 -#define MASK_FSUB_D 0xfe00007f -#define MATCH_FSUB_H 0xc000053 -#define MASK_FSUB_H 0xfe00007f -#define MATCH_FSUB_Q 0xe000053 -#define MASK_FSUB_Q 0xfe00007f -#define MATCH_FSUB_S 0x8000053 -#define MASK_FSUB_S 0xfe00007f -#define MATCH_FSW 0x2027 -#define MASK_FSW 0x707f -#define MATCH_GORC 0x28005033 -#define MASK_GORC 0xfe00707f -#define MATCH_GORCI 0x28005013 -#define MASK_GORCI 0xfc00707f -#define MATCH_GORCIW 0x2800501b -#define MASK_GORCIW 0xfe00707f -#define MATCH_GORCW 0x2800503b -#define MASK_GORCW 0xfe00707f -#define MATCH_GREV 0x68005033 -#define MASK_GREV 0xfe00707f -#define MATCH_GREVI 0x68005013 -#define MASK_GREVI 0xfc00707f -#define MATCH_GREVIW 0x6800501b -#define MASK_GREVIW 0xfe00707f -#define MATCH_GREVW 0x6800503b -#define MASK_GREVW 0xfe00707f -#define MATCH_HFENCE_GVMA 0x62000073 -#define MASK_HFENCE_GVMA 0xfe007fff -#define MATCH_HFENCE_VVMA 0x22000073 -#define MASK_HFENCE_VVMA 0xfe007fff -#define MATCH_HINVAL_GVMA 0x66000073 -#define MASK_HINVAL_GVMA 0xfe007fff -#define MATCH_HINVAL_VVMA 0x26000073 -#define MASK_HINVAL_VVMA 0xfe007fff -#define MATCH_HLV_B 0x60004073 -#define MASK_HLV_B 0xfff0707f -#define MATCH_HLV_BU 0x60104073 -#define MASK_HLV_BU 0xfff0707f -#define MATCH_HLV_D 0x6c004073 -#define MASK_HLV_D 0xfff0707f -#define MATCH_HLV_H 0x64004073 -#define MASK_HLV_H 0xfff0707f -#define MATCH_HLV_HU 0x64104073 -#define MASK_HLV_HU 0xfff0707f -#define MATCH_HLV_W 0x68004073 -#define MASK_HLV_W 0xfff0707f -#define MATCH_HLV_WU 0x68104073 -#define MASK_HLV_WU 0xfff0707f -#define MATCH_HLVX_HU 0x64304073 -#define MASK_HLVX_HU 0xfff0707f -#define MATCH_HLVX_WU 0x68304073 -#define MASK_HLVX_WU 0xfff0707f -#define MATCH_HSV_B 0x62004073 -#define MASK_HSV_B 0xfe007fff -#define MATCH_HSV_D 0x6e004073 -#define MASK_HSV_D 0xfe007fff -#define MATCH_HSV_H 0x66004073 -#define MASK_HSV_H 0xfe007fff -#define MATCH_HSV_W 0x6a004073 -#define MASK_HSV_W 0xfe007fff -#define MATCH_INSB 0xac000077 -#define MASK_INSB 0xff80707f -#define MATCH_JAL 0x6f -#define MASK_JAL 0x7f -#define MATCH_JALR 0x67 -#define MASK_JALR 0x707f -#define MATCH_KABS16 0xad100077 -#define MASK_KABS16 0xfff0707f -#define MATCH_KABS32 0xad200077 -#define MASK_KABS32 0xfff0707f -#define MATCH_KABS8 0xad000077 -#define MASK_KABS8 0xfff0707f -#define MATCH_KABSW 0xad400077 -#define MASK_KABSW 0xfff0707f -#define MATCH_KADD16 0x10000077 -#define MASK_KADD16 0xfe00707f -#define MATCH_KADD32 0x10002077 -#define MASK_KADD32 0xfe00707f -#define MATCH_KADD64 0x90001077 -#define MASK_KADD64 0xfe00707f -#define MATCH_KADD8 0x18000077 -#define MASK_KADD8 0xfe00707f -#define MATCH_KADDH 0x4001077 -#define MASK_KADDH 0xfe00707f -#define MATCH_KADDW 0x1077 -#define MASK_KADDW 0xfe00707f -#define MATCH_KCRAS16 0x14000077 -#define MASK_KCRAS16 0xfe00707f -#define MATCH_KCRAS32 0x14002077 -#define MASK_KCRAS32 0xfe00707f -#define MATCH_KCRSA16 0x16000077 -#define MASK_KCRSA16 0xfe00707f -#define MATCH_KCRSA32 0x16002077 -#define MASK_KCRSA32 0xfe00707f -#define MATCH_KDMABB 0xd2001077 -#define MASK_KDMABB 0xfe00707f -#define MATCH_KDMABB16 0xd8001077 -#define MASK_KDMABB16 0xfe00707f -#define MATCH_KDMABT 0xe2001077 -#define MASK_KDMABT 0xfe00707f -#define MATCH_KDMABT16 0xe8001077 -#define MASK_KDMABT16 0xfe00707f -#define MATCH_KDMATT 0xf2001077 -#define MASK_KDMATT 0xfe00707f -#define MATCH_KDMATT16 0xf8001077 -#define MASK_KDMATT16 0xfe00707f -#define MATCH_KDMBB 0xa001077 -#define MASK_KDMBB 0xfe00707f -#define MATCH_KDMBB16 0xda001077 -#define MASK_KDMBB16 0xfe00707f -#define MATCH_KDMBT 0x1a001077 -#define MASK_KDMBT 0xfe00707f -#define MATCH_KDMBT16 0xea001077 -#define MASK_KDMBT16 0xfe00707f -#define MATCH_KDMTT 0x2a001077 -#define MASK_KDMTT 0xfe00707f -#define MATCH_KDMTT16 0xfa001077 -#define MASK_KDMTT16 0xfe00707f -#define MATCH_KHM16 0x86000077 -#define MASK_KHM16 0xfe00707f -#define MATCH_KHM8 0x8e000077 -#define MASK_KHM8 0xfe00707f -#define MATCH_KHMBB 0xc001077 -#define MASK_KHMBB 0xfe00707f -#define MATCH_KHMBB16 0xdc001077 -#define MASK_KHMBB16 0xfe00707f -#define MATCH_KHMBT 0x1c001077 -#define MASK_KHMBT 0xfe00707f -#define MATCH_KHMBT16 0xec001077 -#define MASK_KHMBT16 0xfe00707f -#define MATCH_KHMTT 0x2c001077 -#define MASK_KHMTT 0xfe00707f -#define MATCH_KHMTT16 0xfc001077 -#define MASK_KHMTT16 0xfe00707f -#define MATCH_KHMX16 0x96000077 -#define MASK_KHMX16 0xfe00707f -#define MATCH_KHMX8 0x9e000077 -#define MASK_KHMX8 0xfe00707f -#define MATCH_KMABB 0x5a001077 -#define MASK_KMABB 0xfe00707f -#define MATCH_KMABB32 0x5a002077 -#define MASK_KMABB32 0xfe00707f -#define MATCH_KMABT 0x6a001077 -#define MASK_KMABT 0xfe00707f -#define MATCH_KMABT32 0x6a002077 -#define MASK_KMABT32 0xfe00707f -#define MATCH_KMADA 0x48001077 -#define MASK_KMADA 0xfe00707f -#define MATCH_KMADRS 0x6c001077 -#define MASK_KMADRS 0xfe00707f -#define MATCH_KMADRS32 0x6c002077 -#define MASK_KMADRS32 0xfe00707f -#define MATCH_KMADS 0x5c001077 -#define MASK_KMADS 0xfe00707f -#define MATCH_KMADS32 0x5c002077 -#define MASK_KMADS32 0xfe00707f -#define MATCH_KMAR64 0x94001077 -#define MASK_KMAR64 0xfe00707f -#define MATCH_KMATT 0x7a001077 -#define MASK_KMATT 0xfe00707f -#define MATCH_KMATT32 0x7a002077 -#define MASK_KMATT32 0xfe00707f -#define MATCH_KMAXDA 0x4a001077 -#define MASK_KMAXDA 0xfe00707f -#define MATCH_KMAXDA32 0x4a002077 -#define MASK_KMAXDA32 0xfe00707f -#define MATCH_KMAXDS 0x7c001077 -#define MASK_KMAXDS 0xfe00707f -#define MATCH_KMAXDS32 0x7c002077 -#define MASK_KMAXDS32 0xfe00707f -#define MATCH_KMDA 0x38001077 -#define MASK_KMDA 0xfe00707f -#define MATCH_KMDA32 0x38002077 -#define MASK_KMDA32 0xfe00707f -#define MATCH_KMMAC 0x60001077 -#define MASK_KMMAC 0xfe00707f -#define MATCH_KMMAC_U 0x70001077 -#define MASK_KMMAC_U 0xfe00707f -#define MATCH_KMMAWB 0x46001077 -#define MASK_KMMAWB 0xfe00707f -#define MATCH_KMMAWB2 0xce001077 -#define MASK_KMMAWB2 0xfe00707f -#define MATCH_KMMAWB2_U 0xde001077 -#define MASK_KMMAWB2_U 0xfe00707f -#define MATCH_KMMAWB_U 0x56001077 -#define MASK_KMMAWB_U 0xfe00707f -#define MATCH_KMMAWT 0x66001077 -#define MASK_KMMAWT 0xfe00707f -#define MATCH_KMMAWT2 0xee001077 -#define MASK_KMMAWT2 0xfe00707f -#define MATCH_KMMAWT2_U 0xfe001077 -#define MASK_KMMAWT2_U 0xfe00707f -#define MATCH_KMMAWT_U 0x76001077 -#define MASK_KMMAWT_U 0xfe00707f -#define MATCH_KMMSB 0x42001077 -#define MASK_KMMSB 0xfe00707f -#define MATCH_KMMSB_U 0x52001077 -#define MASK_KMMSB_U 0xfe00707f -#define MATCH_KMMWB2 0x8e001077 -#define MASK_KMMWB2 0xfe00707f -#define MATCH_KMMWB2_U 0x9e001077 -#define MASK_KMMWB2_U 0xfe00707f -#define MATCH_KMMWT2 0xae001077 -#define MASK_KMMWT2 0xfe00707f -#define MATCH_KMMWT2_U 0xbe001077 -#define MASK_KMMWT2_U 0xfe00707f -#define MATCH_KMSDA 0x4c001077 -#define MASK_KMSDA 0xfe00707f -#define MATCH_KMSDA32 0x4c002077 -#define MASK_KMSDA32 0xfe00707f -#define MATCH_KMSR64 0x96001077 -#define MASK_KMSR64 0xfe00707f -#define MATCH_KMSXDA 0x4e001077 -#define MASK_KMSXDA 0xfe00707f -#define MATCH_KMSXDA32 0x4e002077 -#define MASK_KMSXDA32 0xfe00707f -#define MATCH_KMXDA 0x3a001077 -#define MASK_KMXDA 0xfe00707f -#define MATCH_KMXDA32 0x3a002077 -#define MASK_KMXDA32 0xfe00707f -#define MATCH_KSLL16 0x64000077 -#define MASK_KSLL16 0xfe00707f -#define MATCH_KSLL32 0x64002077 -#define MASK_KSLL32 0xfe00707f -#define MATCH_KSLL8 0x6c000077 -#define MASK_KSLL8 0xfe00707f -#define MATCH_KSLLI16 0x75000077 -#define MASK_KSLLI16 0xff00707f -#define MATCH_KSLLI32 0x84002077 -#define MASK_KSLLI32 0xfe00707f -#define MATCH_KSLLI8 0x7c800077 -#define MASK_KSLLI8 0xff80707f -#define MATCH_KSLLIW 0x36001077 -#define MASK_KSLLIW 0xfe00707f -#define MATCH_KSLLW 0x26001077 -#define MASK_KSLLW 0xfe00707f -#define MATCH_KSLRA16 0x56000077 -#define MASK_KSLRA16 0xfe00707f -#define MATCH_KSLRA16_U 0x66000077 -#define MASK_KSLRA16_U 0xfe00707f -#define MATCH_KSLRA32 0x56002077 -#define MASK_KSLRA32 0xfe00707f -#define MATCH_KSLRA32_U 0x66002077 -#define MASK_KSLRA32_U 0xfe00707f -#define MATCH_KSLRA8 0x5e000077 -#define MASK_KSLRA8 0xfe00707f -#define MATCH_KSLRA8_U 0x6e000077 -#define MASK_KSLRA8_U 0xfe00707f -#define MATCH_KSLRAW 0x6e001077 -#define MASK_KSLRAW 0xfe00707f -#define MATCH_KSLRAW_U 0x7e001077 -#define MASK_KSLRAW_U 0xfe00707f -#define MATCH_KSTAS16 0xc4002077 -#define MASK_KSTAS16 0xfe00707f -#define MATCH_KSTAS32 0xc0002077 -#define MASK_KSTAS32 0xfe00707f -#define MATCH_KSTSA16 0xc6002077 -#define MASK_KSTSA16 0xfe00707f -#define MATCH_KSTSA32 0xc2002077 -#define MASK_KSTSA32 0xfe00707f -#define MATCH_KSUB16 0x12000077 -#define MASK_KSUB16 0xfe00707f -#define MATCH_KSUB32 0x12002077 -#define MASK_KSUB32 0xfe00707f -#define MATCH_KSUB64 0x92001077 -#define MASK_KSUB64 0xfe00707f -#define MATCH_KSUB8 0x1a000077 -#define MASK_KSUB8 0xfe00707f -#define MATCH_KSUBH 0x6001077 -#define MASK_KSUBH 0xfe00707f -#define MATCH_KSUBW 0x2001077 -#define MASK_KSUBW 0xfe00707f -#define MATCH_KWMMUL 0x62001077 -#define MASK_KWMMUL 0xfe00707f -#define MATCH_KWMMUL_U 0x72001077 -#define MASK_KWMMUL_U 0xfe00707f -#define MATCH_LB 0x3 -#define MASK_LB 0x707f -#define MATCH_LBU 0x4003 -#define MASK_LBU 0x707f -#define MATCH_LD 0x3003 -#define MASK_LD 0x707f -#define MATCH_LH 0x1003 -#define MASK_LH 0x707f -#define MATCH_LHU 0x5003 -#define MASK_LHU 0x707f -#define MATCH_LR_D 0x1000302f -#define MASK_LR_D 0xf9f0707f -#define MATCH_LR_W 0x1000202f -#define MASK_LR_W 0xf9f0707f -#define MATCH_LUI 0x37 -#define MASK_LUI 0x7f -#define MATCH_LW 0x2003 -#define MASK_LW 0x707f -#define MATCH_LWU 0x6003 -#define MASK_LWU 0x707f -#define MATCH_MADDR32 0xc4001077 -#define MASK_MADDR32 0xfe00707f -#define MATCH_MAX 0xa006033 -#define MASK_MAX 0xfe00707f -#define MATCH_MAXU 0xa007033 -#define MASK_MAXU 0xfe00707f -#define MATCH_MIN 0xa004033 -#define MASK_MIN 0xfe00707f -#define MATCH_MINU 0xa005033 -#define MASK_MINU 0xfe00707f -#define MATCH_MNRET 0x70200073 -#define MASK_MNRET 0xffffffff -#define MATCH_MRET 0x30200073 -#define MASK_MRET 0xffffffff -#define MATCH_MSUBR32 0xc6001077 -#define MASK_MSUBR32 0xfe00707f -#define MATCH_MUL 0x2000033 -#define MASK_MUL 0xfe00707f -#define MATCH_MULH 0x2001033 -#define MASK_MULH 0xfe00707f -#define MATCH_MULHSU 0x2002033 -#define MASK_MULHSU 0xfe00707f -#define MATCH_MULHU 0x2003033 -#define MASK_MULHU 0xfe00707f -#define MATCH_MULR64 0xf0001077 -#define MASK_MULR64 0xfe00707f -#define MATCH_MULSR64 0xe0001077 -#define MASK_MULSR64 0xfe00707f -#define MATCH_MULW 0x200003b -#define MASK_MULW 0xfe00707f -#define MATCH_OR 0x6033 -#define MASK_OR 0xfe00707f -#define MATCH_ORI 0x6013 -#define MASK_ORI 0x707f -#define MATCH_ORN 0x40006033 -#define MASK_ORN 0xfe00707f -#define MATCH_PACK 0x8004033 -#define MASK_PACK 0xfe00707f -#define MATCH_PACKH 0x8007033 -#define MASK_PACKH 0xfe00707f -#define MATCH_PACKU 0x48004033 -#define MASK_PACKU 0xfe00707f -#define MATCH_PACKUW 0x4800403b -#define MASK_PACKUW 0xfe00707f -#define MATCH_PACKW 0x800403b -#define MASK_PACKW 0xfe00707f -#define MATCH_PAUSE 0x100000f -#define MASK_PAUSE 0xffffffff -#define MATCH_PBSAD 0xfc000077 -#define MASK_PBSAD 0xfe00707f -#define MATCH_PBSADA 0xfe000077 -#define MASK_PBSADA 0xfe00707f -#define MATCH_PKBB16 0xe001077 -#define MASK_PKBB16 0xfe00707f -#define MATCH_PKBT16 0x1e001077 -#define MASK_PKBT16 0xfe00707f -#define MATCH_PKBT32 0x1e002077 -#define MASK_PKBT32 0xfe00707f -#define MATCH_PKTB16 0x3e001077 -#define MASK_PKTB16 0xfe00707f -#define MATCH_PKTB32 0x3e002077 -#define MASK_PKTB32 0xfe00707f -#define MATCH_PKTT16 0x2e001077 -#define MASK_PKTT16 0xfe00707f -#define MATCH_PREFETCH_I 0x6013 -#define MASK_PREFETCH_I 0x1f07fff -#define MATCH_PREFETCH_R 0x106013 -#define MASK_PREFETCH_R 0x1f07fff -#define MATCH_PREFETCH_W 0x306013 -#define MASK_PREFETCH_W 0x1f07fff -#define MATCH_RADD16 0x77 -#define MASK_RADD16 0xfe00707f -#define MATCH_RADD32 0x2077 -#define MASK_RADD32 0xfe00707f -#define MATCH_RADD64 0x80001077 -#define MASK_RADD64 0xfe00707f -#define MATCH_RADD8 0x8000077 -#define MASK_RADD8 0xfe00707f -#define MATCH_RADDW 0x20001077 -#define MASK_RADDW 0xfe00707f -#define MATCH_RCRAS16 0x4000077 -#define MASK_RCRAS16 0xfe00707f -#define MATCH_RCRAS32 0x4002077 -#define MASK_RCRAS32 0xfe00707f -#define MATCH_RCRSA16 0x6000077 -#define MASK_RCRSA16 0xfe00707f -#define MATCH_RCRSA32 0x6002077 -#define MASK_RCRSA32 0xfe00707f -#define MATCH_REM 0x2006033 -#define MASK_REM 0xfe00707f -#define MATCH_REMU 0x2007033 -#define MASK_REMU 0xfe00707f -#define MATCH_REMUW 0x200703b -#define MASK_REMUW 0xfe00707f -#define MATCH_REMW 0x200603b -#define MASK_REMW 0xfe00707f -#define MATCH_ROL 0x60001033 -#define MASK_ROL 0xfe00707f -#define MATCH_ROLW 0x6000103b -#define MASK_ROLW 0xfe00707f -#define MATCH_ROR 0x60005033 -#define MASK_ROR 0xfe00707f -#define MATCH_RORI 0x60005013 -#define MASK_RORI 0xfc00707f -#define MATCH_RORIW 0x6000501b -#define MASK_RORIW 0xfe00707f -#define MATCH_RORW 0x6000503b -#define MASK_RORW 0xfe00707f -#define MATCH_RSTAS16 0xb4002077 -#define MASK_RSTAS16 0xfe00707f -#define MATCH_RSTAS32 0xb0002077 -#define MASK_RSTAS32 0xfe00707f -#define MATCH_RSTSA16 0xb6002077 -#define MASK_RSTSA16 0xfe00707f -#define MATCH_RSTSA32 0xb2002077 -#define MASK_RSTSA32 0xfe00707f -#define MATCH_RSUB16 0x2000077 -#define MASK_RSUB16 0xfe00707f -#define MATCH_RSUB32 0x2002077 -#define MASK_RSUB32 0xfe00707f -#define MATCH_RSUB64 0x82001077 -#define MASK_RSUB64 0xfe00707f -#define MATCH_RSUB8 0xa000077 -#define MASK_RSUB8 0xfe00707f -#define MATCH_RSUBW 0x22001077 -#define MASK_RSUBW 0xfe00707f -#define MATCH_SB 0x23 -#define MASK_SB 0x707f -#define MATCH_SC_D 0x1800302f -#define MASK_SC_D 0xf800707f -#define MATCH_SC_W 0x1800202f -#define MASK_SC_W 0xf800707f -#define MATCH_SCLIP16 0x84000077 -#define MASK_SCLIP16 0xff00707f -#define MATCH_SCLIP32 0xe4000077 -#define MASK_SCLIP32 0xfe00707f -#define MATCH_SCLIP8 0x8c000077 -#define MASK_SCLIP8 0xff80707f -#define MATCH_SCMPLE16 0x1c000077 -#define MASK_SCMPLE16 0xfe00707f -#define MATCH_SCMPLE8 0x1e000077 -#define MASK_SCMPLE8 0xfe00707f -#define MATCH_SCMPLT16 0xc000077 -#define MASK_SCMPLT16 0xfe00707f -#define MATCH_SCMPLT8 0xe000077 -#define MASK_SCMPLT8 0xfe00707f -#define MATCH_SD 0x3023 -#define MASK_SD 0x707f -#define MATCH_SEXT_B 0x60401013 -#define MASK_SEXT_B 0xfff0707f -#define MATCH_SEXT_H 0x60501013 -#define MASK_SEXT_H 0xfff0707f -#define MATCH_SFENCE_INVAL_IR 0x18100073 -#define MASK_SFENCE_INVAL_IR 0xffffffff -#define MATCH_SFENCE_VMA 0x12000073 -#define MASK_SFENCE_VMA 0xfe007fff -#define MATCH_SFENCE_W_INVAL 0x18000073 -#define MASK_SFENCE_W_INVAL 0xffffffff -#define MATCH_SH 0x1023 -#define MASK_SH 0x707f -#define MATCH_SH1ADD 0x20002033 -#define MASK_SH1ADD 0xfe00707f -#define MATCH_SH1ADD_UW 0x2000203b -#define MASK_SH1ADD_UW 0xfe00707f -#define MATCH_SH2ADD 0x20004033 -#define MASK_SH2ADD 0xfe00707f -#define MATCH_SH2ADD_UW 0x2000403b -#define MASK_SH2ADD_UW 0xfe00707f -#define MATCH_SH3ADD 0x20006033 -#define MASK_SH3ADD 0xfe00707f -#define MATCH_SH3ADD_UW 0x2000603b -#define MASK_SH3ADD_UW 0xfe00707f -#define MATCH_SHA256SIG0 0x10201013 -#define MASK_SHA256SIG0 0xfff0707f -#define MATCH_SHA256SIG1 0x10301013 -#define MASK_SHA256SIG1 0xfff0707f -#define MATCH_SHA256SUM0 0x10001013 -#define MASK_SHA256SUM0 0xfff0707f -#define MATCH_SHA256SUM1 0x10101013 -#define MASK_SHA256SUM1 0xfff0707f -#define MATCH_SHA512SIG0 0x10601013 -#define MASK_SHA512SIG0 0xfff0707f -#define MATCH_SHA512SIG0H 0x5c000033 -#define MASK_SHA512SIG0H 0xfe00707f -#define MATCH_SHA512SIG0L 0x54000033 -#define MASK_SHA512SIG0L 0xfe00707f -#define MATCH_SHA512SIG1 0x10701013 -#define MASK_SHA512SIG1 0xfff0707f -#define MATCH_SHA512SIG1H 0x5e000033 -#define MASK_SHA512SIG1H 0xfe00707f -#define MATCH_SHA512SIG1L 0x56000033 -#define MASK_SHA512SIG1L 0xfe00707f -#define MATCH_SHA512SUM0 0x10401013 -#define MASK_SHA512SUM0 0xfff0707f -#define MATCH_SHA512SUM0R 0x50000033 -#define MASK_SHA512SUM0R 0xfe00707f -#define MATCH_SHA512SUM1 0x10501013 -#define MASK_SHA512SUM1 0xfff0707f -#define MATCH_SHA512SUM1R 0x52000033 -#define MASK_SHA512SUM1R 0xfe00707f -#define MATCH_SHFL 0x8001033 -#define MASK_SHFL 0xfe00707f -#define MATCH_SHFLI 0x8001013 -#define MASK_SHFLI 0xfe00707f -#define MATCH_SHFLW 0x800103b -#define MASK_SHFLW 0xfe00707f -#define MATCH_SINVAL_VMA 0x16000073 -#define MASK_SINVAL_VMA 0xfe007fff -#define MATCH_SLL 0x1033 -#define MASK_SLL 0xfe00707f -#define MATCH_SLL16 0x54000077 -#define MASK_SLL16 0xfe00707f -#define MATCH_SLL32 0x54002077 -#define MASK_SLL32 0xfe00707f -#define MATCH_SLL8 0x5c000077 -#define MASK_SLL8 0xfe00707f -#define MATCH_SLLI 0x1013 -#define MASK_SLLI 0xfc00707f -#define MATCH_SLLI16 0x74000077 -#define MASK_SLLI16 0xff00707f -#define MATCH_SLLI32 0x74002077 -#define MASK_SLLI32 0xfe00707f -#define MATCH_SLLI8 0x7c000077 -#define MASK_SLLI8 0xff80707f -#define MATCH_SLLI_RV32 0x1013 -#define MASK_SLLI_RV32 0xfe00707f -#define MATCH_SLLI_UW 0x800101b -#define MASK_SLLI_UW 0xfc00707f -#define MATCH_SLLIW 0x101b -#define MASK_SLLIW 0xfe00707f -#define MATCH_SLLW 0x103b -#define MASK_SLLW 0xfe00707f -#define MATCH_SLO 0x20001033 -#define MASK_SLO 0xfe00707f -#define MATCH_SLOI 0x20001013 -#define MASK_SLOI 0xfc00707f -#define MATCH_SLOIW 0x2000101b -#define MASK_SLOIW 0xfe00707f -#define MATCH_SLOW 0x2000103b -#define MASK_SLOW 0xfe00707f -#define MATCH_SLT 0x2033 -#define MASK_SLT 0xfe00707f -#define MATCH_SLTI 0x2013 -#define MASK_SLTI 0x707f -#define MATCH_SLTIU 0x3013 -#define MASK_SLTIU 0x707f -#define MATCH_SLTU 0x3033 -#define MASK_SLTU 0xfe00707f -#define MATCH_SM3P0 0x10801013 -#define MASK_SM3P0 0xfff0707f -#define MATCH_SM3P1 0x10901013 -#define MASK_SM3P1 0xfff0707f -#define MATCH_SM4ED 0x30000033 -#define MASK_SM4ED 0x3e00707f -#define MATCH_SM4KS 0x34000033 -#define MASK_SM4KS 0x3e00707f -#define MATCH_SMAL 0x5e001077 -#define MASK_SMAL 0xfe00707f -#define MATCH_SMALBB 0x88001077 -#define MASK_SMALBB 0xfe00707f -#define MATCH_SMALBT 0x98001077 -#define MASK_SMALBT 0xfe00707f -#define MATCH_SMALDA 0x8c001077 -#define MASK_SMALDA 0xfe00707f -#define MATCH_SMALDRS 0x9a001077 -#define MASK_SMALDRS 0xfe00707f -#define MATCH_SMALDS 0x8a001077 -#define MASK_SMALDS 0xfe00707f -#define MATCH_SMALTT 0xa8001077 -#define MASK_SMALTT 0xfe00707f -#define MATCH_SMALXDA 0x9c001077 -#define MASK_SMALXDA 0xfe00707f -#define MATCH_SMALXDS 0xaa001077 -#define MASK_SMALXDS 0xfe00707f -#define MATCH_SMAQA 0xc8000077 -#define MASK_SMAQA 0xfe00707f -#define MATCH_SMAQA_SU 0xca000077 -#define MASK_SMAQA_SU 0xfe00707f -#define MATCH_SMAR64 0x84001077 -#define MASK_SMAR64 0xfe00707f -#define MATCH_SMAX16 0x82000077 -#define MASK_SMAX16 0xfe00707f -#define MATCH_SMAX32 0x92002077 -#define MASK_SMAX32 0xfe00707f -#define MATCH_SMAX8 0x8a000077 -#define MASK_SMAX8 0xfe00707f -#define MATCH_SMBB16 0x8001077 -#define MASK_SMBB16 0xfe00707f -#define MATCH_SMBT16 0x18001077 -#define MASK_SMBT16 0xfe00707f -#define MATCH_SMBT32 0x18002077 -#define MASK_SMBT32 0xfe00707f -#define MATCH_SMDRS 0x68001077 -#define MASK_SMDRS 0xfe00707f -#define MATCH_SMDRS32 0x68002077 -#define MASK_SMDRS32 0xfe00707f -#define MATCH_SMDS 0x58001077 -#define MASK_SMDS 0xfe00707f -#define MATCH_SMDS32 0x58002077 -#define MASK_SMDS32 0xfe00707f -#define MATCH_SMIN16 0x80000077 -#define MASK_SMIN16 0xfe00707f -#define MATCH_SMIN32 0x90002077 -#define MASK_SMIN32 0xfe00707f -#define MATCH_SMIN8 0x88000077 -#define MASK_SMIN8 0xfe00707f -#define MATCH_SMMUL 0x40001077 -#define MASK_SMMUL 0xfe00707f -#define MATCH_SMMUL_U 0x50001077 -#define MASK_SMMUL_U 0xfe00707f -#define MATCH_SMMWB 0x44001077 -#define MASK_SMMWB 0xfe00707f -#define MATCH_SMMWB_U 0x54001077 -#define MASK_SMMWB_U 0xfe00707f -#define MATCH_SMMWT 0x64001077 -#define MASK_SMMWT 0xfe00707f -#define MATCH_SMMWT_U 0x74001077 -#define MASK_SMMWT_U 0xfe00707f -#define MATCH_SMSLDA 0xac001077 -#define MASK_SMSLDA 0xfe00707f -#define MATCH_SMSLXDA 0xbc001077 -#define MASK_SMSLXDA 0xfe00707f -#define MATCH_SMSR64 0x86001077 -#define MASK_SMSR64 0xfe00707f -#define MATCH_SMTT16 0x28001077 -#define MASK_SMTT16 0xfe00707f -#define MATCH_SMTT32 0x28002077 -#define MASK_SMTT32 0xfe00707f -#define MATCH_SMUL16 0xa0000077 -#define MASK_SMUL16 0xfe00707f -#define MATCH_SMUL8 0xa8000077 -#define MASK_SMUL8 0xfe00707f -#define MATCH_SMULX16 0xa2000077 -#define MASK_SMULX16 0xfe00707f -#define MATCH_SMULX8 0xaa000077 -#define MASK_SMULX8 0xfe00707f -#define MATCH_SMXDS 0x78001077 -#define MASK_SMXDS 0xfe00707f -#define MATCH_SMXDS32 0x78002077 -#define MASK_SMXDS32 0xfe00707f -#define MATCH_SRA 0x40005033 -#define MASK_SRA 0xfe00707f -#define MATCH_SRA16 0x50000077 -#define MASK_SRA16 0xfe00707f -#define MATCH_SRA16_U 0x60000077 -#define MASK_SRA16_U 0xfe00707f -#define MATCH_SRA32 0x50002077 -#define MASK_SRA32 0xfe00707f -#define MATCH_SRA32_U 0x60002077 -#define MASK_SRA32_U 0xfe00707f -#define MATCH_SRA8 0x58000077 -#define MASK_SRA8 0xfe00707f -#define MATCH_SRA8_U 0x68000077 -#define MASK_SRA8_U 0xfe00707f -#define MATCH_SRA_U 0x24001077 -#define MASK_SRA_U 0xfe00707f -#define MATCH_SRAI 0x40005013 -#define MASK_SRAI 0xfc00707f -#define MATCH_SRAI16 0x70000077 -#define MASK_SRAI16 0xff00707f -#define MATCH_SRAI16_U 0x71000077 -#define MASK_SRAI16_U 0xff00707f -#define MATCH_SRAI32 0x70002077 -#define MASK_SRAI32 0xfe00707f -#define MATCH_SRAI32_U 0x80002077 -#define MASK_SRAI32_U 0xfe00707f -#define MATCH_SRAI8 0x78000077 -#define MASK_SRAI8 0xff80707f -#define MATCH_SRAI8_U 0x78800077 -#define MASK_SRAI8_U 0xff80707f -#define MATCH_SRAI_RV32 0x40005013 -#define MASK_SRAI_RV32 0xfe00707f -#define MATCH_SRAI_U 0xd4001077 -#define MASK_SRAI_U 0xfc00707f -#define MATCH_SRAIW 0x4000501b -#define MASK_SRAIW 0xfe00707f -#define MATCH_SRAIW_U 0x34001077 -#define MASK_SRAIW_U 0xfe00707f -#define MATCH_SRAW 0x4000503b -#define MASK_SRAW 0xfe00707f -#define MATCH_SRET 0x10200073 -#define MASK_SRET 0xffffffff -#define MATCH_SRL 0x5033 -#define MASK_SRL 0xfe00707f -#define MATCH_SRL16 0x52000077 -#define MASK_SRL16 0xfe00707f -#define MATCH_SRL16_U 0x62000077 -#define MASK_SRL16_U 0xfe00707f -#define MATCH_SRL32 0x52002077 -#define MASK_SRL32 0xfe00707f -#define MATCH_SRL32_U 0x62002077 -#define MASK_SRL32_U 0xfe00707f -#define MATCH_SRL8 0x5a000077 -#define MASK_SRL8 0xfe00707f -#define MATCH_SRL8_U 0x6a000077 -#define MASK_SRL8_U 0xfe00707f -#define MATCH_SRLI 0x5013 -#define MASK_SRLI 0xfc00707f -#define MATCH_SRLI16 0x72000077 -#define MASK_SRLI16 0xff00707f -#define MATCH_SRLI16_U 0x73000077 -#define MASK_SRLI16_U 0xff00707f -#define MATCH_SRLI32 0x72002077 -#define MASK_SRLI32 0xfe00707f -#define MATCH_SRLI32_U 0x82002077 -#define MASK_SRLI32_U 0xfe00707f -#define MATCH_SRLI8 0x7a000077 -#define MASK_SRLI8 0xff80707f -#define MATCH_SRLI8_U 0x7a800077 -#define MASK_SRLI8_U 0xff80707f -#define MATCH_SRLI_RV32 0x5013 -#define MASK_SRLI_RV32 0xfe00707f -#define MATCH_SRLIW 0x501b -#define MASK_SRLIW 0xfe00707f -#define MATCH_SRLW 0x503b -#define MASK_SRLW 0xfe00707f -#define MATCH_SRO 0x20005033 -#define MASK_SRO 0xfe00707f -#define MATCH_SROI 0x20005013 -#define MASK_SROI 0xfc00707f -#define MATCH_SROIW 0x2000501b -#define MASK_SROIW 0xfe00707f -#define MATCH_SROW 0x2000503b -#define MASK_SROW 0xfe00707f -#define MATCH_STAS16 0xf4002077 -#define MASK_STAS16 0xfe00707f -#define MATCH_STAS32 0xf0002077 -#define MASK_STAS32 0xfe00707f -#define MATCH_STSA16 0xf6002077 -#define MASK_STSA16 0xfe00707f -#define MATCH_STSA32 0xf2002077 -#define MASK_STSA32 0xfe00707f -#define MATCH_SUB 0x40000033 -#define MASK_SUB 0xfe00707f -#define MATCH_SUB16 0x42000077 -#define MASK_SUB16 0xfe00707f -#define MATCH_SUB32 0x42002077 -#define MASK_SUB32 0xfe00707f -#define MATCH_SUB64 0xc2001077 -#define MASK_SUB64 0xfe00707f -#define MATCH_SUB8 0x4a000077 -#define MASK_SUB8 0xfe00707f -#define MATCH_SUBW 0x4000003b -#define MASK_SUBW 0xfe00707f -#define MATCH_SUNPKD810 0xac800077 -#define MASK_SUNPKD810 0xfff0707f -#define MATCH_SUNPKD820 0xac900077 -#define MASK_SUNPKD820 0xfff0707f -#define MATCH_SUNPKD830 0xaca00077 -#define MASK_SUNPKD830 0xfff0707f -#define MATCH_SUNPKD831 0xacb00077 -#define MASK_SUNPKD831 0xfff0707f -#define MATCH_SUNPKD832 0xad300077 -#define MASK_SUNPKD832 0xfff0707f -#define MATCH_SW 0x2023 -#define MASK_SW 0x707f -#define MATCH_UCLIP16 0x85000077 -#define MASK_UCLIP16 0xff00707f -#define MATCH_UCLIP32 0xf4000077 -#define MASK_UCLIP32 0xfe00707f -#define MATCH_UCLIP8 0x8d000077 -#define MASK_UCLIP8 0xff80707f -#define MATCH_UCMPLE16 0x3c000077 -#define MASK_UCMPLE16 0xfe00707f -#define MATCH_UCMPLE8 0x3e000077 -#define MASK_UCMPLE8 0xfe00707f -#define MATCH_UCMPLT16 0x2c000077 -#define MASK_UCMPLT16 0xfe00707f -#define MATCH_UCMPLT8 0x2e000077 -#define MASK_UCMPLT8 0xfe00707f -#define MATCH_UKADD16 0x30000077 -#define MASK_UKADD16 0xfe00707f -#define MATCH_UKADD32 0x30002077 -#define MASK_UKADD32 0xfe00707f -#define MATCH_UKADD64 0xb0001077 -#define MASK_UKADD64 0xfe00707f -#define MATCH_UKADD8 0x38000077 -#define MASK_UKADD8 0xfe00707f -#define MATCH_UKADDH 0x14001077 -#define MASK_UKADDH 0xfe00707f -#define MATCH_UKADDW 0x10001077 -#define MASK_UKADDW 0xfe00707f -#define MATCH_UKCRAS16 0x34000077 -#define MASK_UKCRAS16 0xfe00707f -#define MATCH_UKCRAS32 0x34002077 -#define MASK_UKCRAS32 0xfe00707f -#define MATCH_UKCRSA16 0x36000077 -#define MASK_UKCRSA16 0xfe00707f -#define MATCH_UKCRSA32 0x36002077 -#define MASK_UKCRSA32 0xfe00707f -#define MATCH_UKMAR64 0xb4001077 -#define MASK_UKMAR64 0xfe00707f -#define MATCH_UKMSR64 0xb6001077 -#define MASK_UKMSR64 0xfe00707f -#define MATCH_UKSTAS16 0xe4002077 -#define MASK_UKSTAS16 0xfe00707f -#define MATCH_UKSTAS32 0xe0002077 -#define MASK_UKSTAS32 0xfe00707f -#define MATCH_UKSTSA16 0xe6002077 -#define MASK_UKSTSA16 0xfe00707f -#define MATCH_UKSTSA32 0xe2002077 -#define MASK_UKSTSA32 0xfe00707f -#define MATCH_UKSUB16 0x32000077 -#define MASK_UKSUB16 0xfe00707f -#define MATCH_UKSUB32 0x32002077 -#define MASK_UKSUB32 0xfe00707f -#define MATCH_UKSUB64 0xb2001077 -#define MASK_UKSUB64 0xfe00707f -#define MATCH_UKSUB8 0x3a000077 -#define MASK_UKSUB8 0xfe00707f -#define MATCH_UKSUBH 0x16001077 -#define MASK_UKSUBH 0xfe00707f -#define MATCH_UKSUBW 0x12001077 -#define MASK_UKSUBW 0xfe00707f -#define MATCH_UMAQA 0xcc000077 -#define MASK_UMAQA 0xfe00707f -#define MATCH_UMAR64 0xa4001077 -#define MASK_UMAR64 0xfe00707f -#define MATCH_UMAX16 0x92000077 -#define MASK_UMAX16 0xfe00707f -#define MATCH_UMAX32 0xa2002077 -#define MASK_UMAX32 0xfe00707f -#define MATCH_UMAX8 0x9a000077 -#define MASK_UMAX8 0xfe00707f -#define MATCH_UMIN16 0x90000077 -#define MASK_UMIN16 0xfe00707f -#define MATCH_UMIN32 0xa0002077 -#define MASK_UMIN32 0xfe00707f -#define MATCH_UMIN8 0x98000077 -#define MASK_UMIN8 0xfe00707f -#define MATCH_UMSR64 0xa6001077 -#define MASK_UMSR64 0xfe00707f -#define MATCH_UMUL16 0xb0000077 -#define MASK_UMUL16 0xfe00707f -#define MATCH_UMUL8 0xb8000077 -#define MASK_UMUL8 0xfe00707f -#define MATCH_UMULX16 0xb2000077 -#define MASK_UMULX16 0xfe00707f -#define MATCH_UMULX8 0xba000077 -#define MASK_UMULX8 0xfe00707f -#define MATCH_UNSHFL 0x8005033 -#define MASK_UNSHFL 0xfe00707f -#define MATCH_UNSHFLI 0x8005013 -#define MASK_UNSHFLI 0xfe00707f -#define MATCH_UNSHFLW 0x800503b -#define MASK_UNSHFLW 0xfe00707f -#define MATCH_URADD16 0x20000077 -#define MASK_URADD16 0xfe00707f -#define MATCH_URADD32 0x20002077 -#define MASK_URADD32 0xfe00707f -#define MATCH_URADD64 0xa0001077 -#define MASK_URADD64 0xfe00707f -#define MATCH_URADD8 0x28000077 -#define MASK_URADD8 0xfe00707f -#define MATCH_URADDW 0x30001077 -#define MASK_URADDW 0xfe00707f -#define MATCH_URCRAS16 0x24000077 -#define MASK_URCRAS16 0xfe00707f -#define MATCH_URCRAS32 0x24002077 -#define MASK_URCRAS32 0xfe00707f -#define MATCH_URCRSA16 0x26000077 -#define MASK_URCRSA16 0xfe00707f -#define MATCH_URCRSA32 0x26002077 -#define MASK_URCRSA32 0xfe00707f -#define MATCH_URSTAS16 0xd4002077 -#define MASK_URSTAS16 0xfe00707f -#define MATCH_URSTAS32 0xd0002077 -#define MASK_URSTAS32 0xfe00707f -#define MATCH_URSTSA16 0xd6002077 -#define MASK_URSTSA16 0xfe00707f -#define MATCH_URSTSA32 0xd2002077 -#define MASK_URSTSA32 0xfe00707f -#define MATCH_URSUB16 0x22000077 -#define MASK_URSUB16 0xfe00707f -#define MATCH_URSUB32 0x22002077 -#define MASK_URSUB32 0xfe00707f -#define MATCH_URSUB64 0xa2001077 -#define MASK_URSUB64 0xfe00707f -#define MATCH_URSUB8 0x2a000077 -#define MASK_URSUB8 0xfe00707f -#define MATCH_URSUBW 0x32001077 -#define MASK_URSUBW 0xfe00707f -#define MATCH_VAADD_VV 0x24002057 -#define MASK_VAADD_VV 0xfc00707f -#define MATCH_VAADD_VX 0x24006057 -#define MASK_VAADD_VX 0xfc00707f -#define MATCH_VAADDU_VV 0x20002057 -#define MASK_VAADDU_VV 0xfc00707f -#define MATCH_VAADDU_VX 0x20006057 -#define MASK_VAADDU_VX 0xfc00707f -#define MATCH_VADC_VIM 0x40003057 -#define MASK_VADC_VIM 0xfe00707f -#define MATCH_VADC_VVM 0x40000057 -#define MASK_VADC_VVM 0xfe00707f -#define MATCH_VADC_VXM 0x40004057 -#define MASK_VADC_VXM 0xfe00707f -#define MATCH_VADD_VI 0x3057 -#define MASK_VADD_VI 0xfc00707f -#define MATCH_VADD_VV 0x57 -#define MASK_VADD_VV 0xfc00707f -#define MATCH_VADD_VX 0x4057 -#define MASK_VADD_VX 0xfc00707f -#define MATCH_VAMOADDEI16_V 0x502f -#define MASK_VAMOADDEI16_V 0xf800707f -#define MATCH_VAMOADDEI32_V 0x602f -#define MASK_VAMOADDEI32_V 0xf800707f -#define MATCH_VAMOADDEI64_V 0x702f -#define MASK_VAMOADDEI64_V 0xf800707f -#define MATCH_VAMOADDEI8_V 0x2f -#define MASK_VAMOADDEI8_V 0xf800707f -#define MATCH_VAMOANDEI16_V 0x6000502f -#define MASK_VAMOANDEI16_V 0xf800707f -#define MATCH_VAMOANDEI32_V 0x6000602f -#define MASK_VAMOANDEI32_V 0xf800707f -#define MATCH_VAMOANDEI64_V 0x6000702f -#define MASK_VAMOANDEI64_V 0xf800707f -#define MATCH_VAMOANDEI8_V 0x6000002f -#define MASK_VAMOANDEI8_V 0xf800707f -#define MATCH_VAMOMAXEI16_V 0xa000502f -#define MASK_VAMOMAXEI16_V 0xf800707f -#define MATCH_VAMOMAXEI32_V 0xa000602f -#define MASK_VAMOMAXEI32_V 0xf800707f -#define MATCH_VAMOMAXEI64_V 0xa000702f -#define MASK_VAMOMAXEI64_V 0xf800707f -#define MATCH_VAMOMAXEI8_V 0xa000002f -#define MASK_VAMOMAXEI8_V 0xf800707f -#define MATCH_VAMOMAXUEI16_V 0xe000502f -#define MASK_VAMOMAXUEI16_V 0xf800707f -#define MATCH_VAMOMAXUEI32_V 0xe000602f -#define MASK_VAMOMAXUEI32_V 0xf800707f -#define MATCH_VAMOMAXUEI64_V 0xe000702f -#define MASK_VAMOMAXUEI64_V 0xf800707f -#define MATCH_VAMOMAXUEI8_V 0xe000002f -#define MASK_VAMOMAXUEI8_V 0xf800707f -#define MATCH_VAMOMINEI16_V 0x8000502f -#define MASK_VAMOMINEI16_V 0xf800707f -#define MATCH_VAMOMINEI32_V 0x8000602f -#define MASK_VAMOMINEI32_V 0xf800707f -#define MATCH_VAMOMINEI64_V 0x8000702f -#define MASK_VAMOMINEI64_V 0xf800707f -#define MATCH_VAMOMINEI8_V 0x8000002f -#define MASK_VAMOMINEI8_V 0xf800707f -#define MATCH_VAMOMINUEI16_V 0xc000502f -#define MASK_VAMOMINUEI16_V 0xf800707f -#define MATCH_VAMOMINUEI32_V 0xc000602f -#define MASK_VAMOMINUEI32_V 0xf800707f -#define MATCH_VAMOMINUEI64_V 0xc000702f -#define MASK_VAMOMINUEI64_V 0xf800707f -#define MATCH_VAMOMINUEI8_V 0xc000002f -#define MASK_VAMOMINUEI8_V 0xf800707f -#define MATCH_VAMOOREI16_V 0x4000502f -#define MASK_VAMOOREI16_V 0xf800707f -#define MATCH_VAMOOREI32_V 0x4000602f -#define MASK_VAMOOREI32_V 0xf800707f -#define MATCH_VAMOOREI64_V 0x4000702f -#define MASK_VAMOOREI64_V 0xf800707f -#define MATCH_VAMOOREI8_V 0x4000002f -#define MASK_VAMOOREI8_V 0xf800707f -#define MATCH_VAMOSWAPEI16_V 0x800502f -#define MASK_VAMOSWAPEI16_V 0xf800707f -#define MATCH_VAMOSWAPEI32_V 0x800602f -#define MASK_VAMOSWAPEI32_V 0xf800707f -#define MATCH_VAMOSWAPEI64_V 0x800702f -#define MASK_VAMOSWAPEI64_V 0xf800707f -#define MATCH_VAMOSWAPEI8_V 0x800002f -#define MASK_VAMOSWAPEI8_V 0xf800707f -#define MATCH_VAMOXOREI16_V 0x2000502f -#define MASK_VAMOXOREI16_V 0xf800707f -#define MATCH_VAMOXOREI32_V 0x2000602f -#define MASK_VAMOXOREI32_V 0xf800707f -#define MATCH_VAMOXOREI64_V 0x2000702f -#define MASK_VAMOXOREI64_V 0xf800707f -#define MATCH_VAMOXOREI8_V 0x2000002f -#define MASK_VAMOXOREI8_V 0xf800707f -#define MATCH_VAND_VI 0x24003057 -#define MASK_VAND_VI 0xfc00707f -#define MATCH_VAND_VV 0x24000057 -#define MASK_VAND_VV 0xfc00707f -#define MATCH_VAND_VX 0x24004057 -#define MASK_VAND_VX 0xfc00707f -#define MATCH_VASUB_VV 0x2c002057 -#define MASK_VASUB_VV 0xfc00707f -#define MATCH_VASUB_VX 0x2c006057 -#define MASK_VASUB_VX 0xfc00707f -#define MATCH_VASUBU_VV 0x28002057 -#define MASK_VASUBU_VV 0xfc00707f -#define MATCH_VASUBU_VX 0x28006057 -#define MASK_VASUBU_VX 0xfc00707f -#define MATCH_VCOMPRESS_VM 0x5e002057 -#define MASK_VCOMPRESS_VM 0xfe00707f -#define MATCH_VCPOP_M 0x40082057 -#define MASK_VCPOP_M 0xfc0ff07f -#define MATCH_VDIV_VV 0x84002057 -#define MASK_VDIV_VV 0xfc00707f -#define MATCH_VDIV_VX 0x84006057 -#define MASK_VDIV_VX 0xfc00707f -#define MATCH_VDIVU_VV 0x80002057 -#define MASK_VDIVU_VV 0xfc00707f -#define MATCH_VDIVU_VX 0x80006057 -#define MASK_VDIVU_VX 0xfc00707f -#define MATCH_VFADD_VF 0x5057 -#define MASK_VFADD_VF 0xfc00707f -#define MATCH_VFADD_VV 0x1057 -#define MASK_VFADD_VV 0xfc00707f -#define MATCH_VFCLASS_V 0x4c081057 -#define MASK_VFCLASS_V 0xfc0ff07f -#define MATCH_VFCVT_F_X_V 0x48019057 -#define MASK_VFCVT_F_X_V 0xfc0ff07f -#define MATCH_VFCVT_F_XU_V 0x48011057 -#define MASK_VFCVT_F_XU_V 0xfc0ff07f -#define MATCH_VFCVT_RTZ_X_F_V 0x48039057 -#define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f -#define MATCH_VFCVT_RTZ_XU_F_V 0x48031057 -#define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f -#define MATCH_VFCVT_X_F_V 0x48009057 -#define MASK_VFCVT_X_F_V 0xfc0ff07f -#define MATCH_VFCVT_XU_F_V 0x48001057 -#define MASK_VFCVT_XU_F_V 0xfc0ff07f -#define MATCH_VFDIV_VF 0x80005057 -#define MASK_VFDIV_VF 0xfc00707f -#define MATCH_VFDIV_VV 0x80001057 -#define MASK_VFDIV_VV 0xfc00707f -#define MATCH_VFIRST_M 0x4008a057 -#define MASK_VFIRST_M 0xfc0ff07f -#define MATCH_VFMACC_VF 0xb0005057 -#define MASK_VFMACC_VF 0xfc00707f -#define MATCH_VFMACC_VV 0xb0001057 -#define MASK_VFMACC_VV 0xfc00707f -#define MATCH_VFMADD_VF 0xa0005057 -#define MASK_VFMADD_VF 0xfc00707f -#define MATCH_VFMADD_VV 0xa0001057 -#define MASK_VFMADD_VV 0xfc00707f -#define MATCH_VFMAX_VF 0x18005057 -#define MASK_VFMAX_VF 0xfc00707f -#define MATCH_VFMAX_VV 0x18001057 -#define MASK_VFMAX_VV 0xfc00707f -#define MATCH_VFMERGE_VFM 0x5c005057 -#define MASK_VFMERGE_VFM 0xfe00707f -#define MATCH_VFMIN_VF 0x10005057 -#define MASK_VFMIN_VF 0xfc00707f -#define MATCH_VFMIN_VV 0x10001057 -#define MASK_VFMIN_VV 0xfc00707f -#define MATCH_VFMSAC_VF 0xb8005057 -#define MASK_VFMSAC_VF 0xfc00707f -#define MATCH_VFMSAC_VV 0xb8001057 -#define MASK_VFMSAC_VV 0xfc00707f -#define MATCH_VFMSUB_VF 0xa8005057 -#define MASK_VFMSUB_VF 0xfc00707f -#define MATCH_VFMSUB_VV 0xa8001057 -#define MASK_VFMSUB_VV 0xfc00707f -#define MATCH_VFMUL_VF 0x90005057 -#define MASK_VFMUL_VF 0xfc00707f -#define MATCH_VFMUL_VV 0x90001057 -#define MASK_VFMUL_VV 0xfc00707f -#define MATCH_VFMV_F_S 0x42001057 -#define MASK_VFMV_F_S 0xfe0ff07f -#define MATCH_VFMV_S_F 0x42005057 -#define MASK_VFMV_S_F 0xfff0707f -#define MATCH_VFMV_V_F 0x5e005057 -#define MASK_VFMV_V_F 0xfff0707f -#define MATCH_VFNCVT_F_F_W 0x480a1057 -#define MASK_VFNCVT_F_F_W 0xfc0ff07f -#define MATCH_VFNCVT_F_X_W 0x48099057 -#define MASK_VFNCVT_F_X_W 0xfc0ff07f -#define MATCH_VFNCVT_F_XU_W 0x48091057 -#define MASK_VFNCVT_F_XU_W 0xfc0ff07f -#define MATCH_VFNCVT_ROD_F_F_W 0x480a9057 -#define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f -#define MATCH_VFNCVT_RTZ_X_F_W 0x480b9057 -#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f -#define MATCH_VFNCVT_RTZ_XU_F_W 0x480b1057 -#define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f -#define MATCH_VFNCVT_X_F_W 0x48089057 -#define MASK_VFNCVT_X_F_W 0xfc0ff07f -#define MATCH_VFNCVT_XU_F_W 0x48081057 -#define MASK_VFNCVT_XU_F_W 0xfc0ff07f -#define MATCH_VFNMACC_VF 0xb4005057 -#define MASK_VFNMACC_VF 0xfc00707f -#define MATCH_VFNMACC_VV 0xb4001057 -#define MASK_VFNMACC_VV 0xfc00707f -#define MATCH_VFNMADD_VF 0xa4005057 -#define MASK_VFNMADD_VF 0xfc00707f -#define MATCH_VFNMADD_VV 0xa4001057 -#define MASK_VFNMADD_VV 0xfc00707f -#define MATCH_VFNMSAC_VF 0xbc005057 -#define MASK_VFNMSAC_VF 0xfc00707f -#define MATCH_VFNMSAC_VV 0xbc001057 -#define MASK_VFNMSAC_VV 0xfc00707f -#define MATCH_VFNMSUB_VF 0xac005057 -#define MASK_VFNMSUB_VF 0xfc00707f -#define MATCH_VFNMSUB_VV 0xac001057 -#define MASK_VFNMSUB_VV 0xfc00707f -#define MATCH_VFRDIV_VF 0x84005057 -#define MASK_VFRDIV_VF 0xfc00707f -#define MATCH_VFREC7_V 0x4c029057 -#define MASK_VFREC7_V 0xfc0ff07f -#define MATCH_VFREDMAX_VS 0x1c001057 -#define MASK_VFREDMAX_VS 0xfc00707f -#define MATCH_VFREDMIN_VS 0x14001057 -#define MASK_VFREDMIN_VS 0xfc00707f -#define MATCH_VFREDOSUM_VS 0xc001057 -#define MASK_VFREDOSUM_VS 0xfc00707f -#define MATCH_VFREDUSUM_VS 0x4001057 -#define MASK_VFREDUSUM_VS 0xfc00707f -#define MATCH_VFRSQRT7_V 0x4c021057 -#define MASK_VFRSQRT7_V 0xfc0ff07f -#define MATCH_VFRSUB_VF 0x9c005057 -#define MASK_VFRSUB_VF 0xfc00707f -#define MATCH_VFSGNJ_VF 0x20005057 -#define MASK_VFSGNJ_VF 0xfc00707f -#define MATCH_VFSGNJ_VV 0x20001057 -#define MASK_VFSGNJ_VV 0xfc00707f -#define MATCH_VFSGNJN_VF 0x24005057 -#define MASK_VFSGNJN_VF 0xfc00707f -#define MATCH_VFSGNJN_VV 0x24001057 -#define MASK_VFSGNJN_VV 0xfc00707f -#define MATCH_VFSGNJX_VF 0x28005057 -#define MASK_VFSGNJX_VF 0xfc00707f -#define MATCH_VFSGNJX_VV 0x28001057 -#define MASK_VFSGNJX_VV 0xfc00707f -#define MATCH_VFSLIDE1DOWN_VF 0x3c005057 -#define MASK_VFSLIDE1DOWN_VF 0xfc00707f -#define MATCH_VFSLIDE1UP_VF 0x38005057 -#define MASK_VFSLIDE1UP_VF 0xfc00707f -#define MATCH_VFSQRT_V 0x4c001057 -#define MASK_VFSQRT_V 0xfc0ff07f -#define MATCH_VFSUB_VF 0x8005057 -#define MASK_VFSUB_VF 0xfc00707f -#define MATCH_VFSUB_VV 0x8001057 -#define MASK_VFSUB_VV 0xfc00707f -#define MATCH_VFWADD_VF 0xc0005057 -#define MASK_VFWADD_VF 0xfc00707f -#define MATCH_VFWADD_VV 0xc0001057 -#define MASK_VFWADD_VV 0xfc00707f -#define MATCH_VFWADD_WF 0xd0005057 -#define MASK_VFWADD_WF 0xfc00707f -#define MATCH_VFWADD_WV 0xd0001057 -#define MASK_VFWADD_WV 0xfc00707f -#define MATCH_VFWCVT_F_F_V 0x48061057 -#define MASK_VFWCVT_F_F_V 0xfc0ff07f -#define MATCH_VFWCVT_F_X_V 0x48059057 -#define MASK_VFWCVT_F_X_V 0xfc0ff07f -#define MATCH_VFWCVT_F_XU_V 0x48051057 -#define MASK_VFWCVT_F_XU_V 0xfc0ff07f -#define MATCH_VFWCVT_RTZ_X_F_V 0x48079057 -#define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f -#define MATCH_VFWCVT_RTZ_XU_F_V 0x48071057 -#define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f -#define MATCH_VFWCVT_X_F_V 0x48049057 -#define MASK_VFWCVT_X_F_V 0xfc0ff07f -#define MATCH_VFWCVT_XU_F_V 0x48041057 -#define MASK_VFWCVT_XU_F_V 0xfc0ff07f -#define MATCH_VFWMACC_VF 0xf0005057 -#define MASK_VFWMACC_VF 0xfc00707f -#define MATCH_VFWMACC_VV 0xf0001057 -#define MASK_VFWMACC_VV 0xfc00707f -#define MATCH_VFWMSAC_VF 0xf8005057 -#define MASK_VFWMSAC_VF 0xfc00707f -#define MATCH_VFWMSAC_VV 0xf8001057 -#define MASK_VFWMSAC_VV 0xfc00707f -#define MATCH_VFWMUL_VF 0xe0005057 -#define MASK_VFWMUL_VF 0xfc00707f -#define MATCH_VFWMUL_VV 0xe0001057 -#define MASK_VFWMUL_VV 0xfc00707f -#define MATCH_VFWNMACC_VF 0xf4005057 -#define MASK_VFWNMACC_VF 0xfc00707f -#define MATCH_VFWNMACC_VV 0xf4001057 -#define MASK_VFWNMACC_VV 0xfc00707f -#define MATCH_VFWNMSAC_VF 0xfc005057 -#define MASK_VFWNMSAC_VF 0xfc00707f -#define MATCH_VFWNMSAC_VV 0xfc001057 -#define MASK_VFWNMSAC_VV 0xfc00707f -#define MATCH_VFWREDOSUM_VS 0xcc001057 -#define MASK_VFWREDOSUM_VS 0xfc00707f -#define MATCH_VFWREDUSUM_VS 0xc4001057 -#define MASK_VFWREDUSUM_VS 0xfc00707f -#define MATCH_VFWSUB_VF 0xc8005057 -#define MASK_VFWSUB_VF 0xfc00707f -#define MATCH_VFWSUB_VV 0xc8001057 -#define MASK_VFWSUB_VV 0xfc00707f -#define MATCH_VFWSUB_WF 0xd8005057 -#define MASK_VFWSUB_WF 0xfc00707f -#define MATCH_VFWSUB_WV 0xd8001057 -#define MASK_VFWSUB_WV 0xfc00707f -#define MATCH_VID_V 0x5008a057 -#define MASK_VID_V 0xfdfff07f -#define MATCH_VIOTA_M 0x50082057 -#define MASK_VIOTA_M 0xfc0ff07f -#define MATCH_VL1RE16_V 0x2805007 -#define MASK_VL1RE16_V 0xfff0707f -#define MATCH_VL1RE32_V 0x2806007 -#define MASK_VL1RE32_V 0xfff0707f -#define MATCH_VL1RE64_V 0x2807007 -#define MASK_VL1RE64_V 0xfff0707f -#define MATCH_VL1RE8_V 0x2800007 -#define MASK_VL1RE8_V 0xfff0707f -#define MATCH_VL2RE16_V 0x22805007 -#define MASK_VL2RE16_V 0xfff0707f -#define MATCH_VL2RE32_V 0x22806007 -#define MASK_VL2RE32_V 0xfff0707f -#define MATCH_VL2RE64_V 0x22807007 -#define MASK_VL2RE64_V 0xfff0707f -#define MATCH_VL2RE8_V 0x22800007 -#define MASK_VL2RE8_V 0xfff0707f -#define MATCH_VL4RE16_V 0x62805007 -#define MASK_VL4RE16_V 0xfff0707f -#define MATCH_VL4RE32_V 0x62806007 -#define MASK_VL4RE32_V 0xfff0707f -#define MATCH_VL4RE64_V 0x62807007 -#define MASK_VL4RE64_V 0xfff0707f -#define MATCH_VL4RE8_V 0x62800007 -#define MASK_VL4RE8_V 0xfff0707f -#define MATCH_VL8RE16_V 0xe2805007 -#define MASK_VL8RE16_V 0xfff0707f -#define MATCH_VL8RE32_V 0xe2806007 -#define MASK_VL8RE32_V 0xfff0707f -#define MATCH_VL8RE64_V 0xe2807007 -#define MASK_VL8RE64_V 0xfff0707f -#define MATCH_VL8RE8_V 0xe2800007 -#define MASK_VL8RE8_V 0xfff0707f -#define MATCH_VLE1024_V 0x10007007 -#define MASK_VLE1024_V 0x1df0707f -#define MATCH_VLE1024FF_V 0x11007007 -#define MASK_VLE1024FF_V 0x1df0707f -#define MATCH_VLE128_V 0x10000007 -#define MASK_VLE128_V 0x1df0707f -#define MATCH_VLE128FF_V 0x11000007 -#define MASK_VLE128FF_V 0x1df0707f -#define MATCH_VLE16_V 0x5007 -#define MASK_VLE16_V 0x1df0707f -#define MATCH_VLE16FF_V 0x1005007 -#define MASK_VLE16FF_V 0x1df0707f -#define MATCH_VLE256_V 0x10005007 -#define MASK_VLE256_V 0x1df0707f -#define MATCH_VLE256FF_V 0x11005007 -#define MASK_VLE256FF_V 0x1df0707f -#define MATCH_VLE32_V 0x6007 -#define MASK_VLE32_V 0x1df0707f -#define MATCH_VLE32FF_V 0x1006007 -#define MASK_VLE32FF_V 0x1df0707f -#define MATCH_VLE512_V 0x10006007 -#define MASK_VLE512_V 0x1df0707f -#define MATCH_VLE512FF_V 0x11006007 -#define MASK_VLE512FF_V 0x1df0707f -#define MATCH_VLE64_V 0x7007 -#define MASK_VLE64_V 0x1df0707f -#define MATCH_VLE64FF_V 0x1007007 -#define MASK_VLE64FF_V 0x1df0707f -#define MATCH_VLE8_V 0x7 -#define MASK_VLE8_V 0x1df0707f -#define MATCH_VLE8FF_V 0x1000007 -#define MASK_VLE8FF_V 0x1df0707f -#define MATCH_VLM_V 0x2b00007 -#define MASK_VLM_V 0xfff0707f -#define MATCH_VLOXEI1024_V 0x1c007007 -#define MASK_VLOXEI1024_V 0x1c00707f -#define MATCH_VLOXEI128_V 0x1c000007 -#define MASK_VLOXEI128_V 0x1c00707f -#define MATCH_VLOXEI16_V 0xc005007 -#define MASK_VLOXEI16_V 0x1c00707f -#define MATCH_VLOXEI256_V 0x1c005007 -#define MASK_VLOXEI256_V 0x1c00707f -#define MATCH_VLOXEI32_V 0xc006007 -#define MASK_VLOXEI32_V 0x1c00707f -#define MATCH_VLOXEI512_V 0x1c006007 -#define MASK_VLOXEI512_V 0x1c00707f -#define MATCH_VLOXEI64_V 0xc007007 -#define MASK_VLOXEI64_V 0x1c00707f -#define MATCH_VLOXEI8_V 0xc000007 -#define MASK_VLOXEI8_V 0x1c00707f -#define MATCH_VLSE1024_V 0x18007007 -#define MASK_VLSE1024_V 0x1c00707f -#define MATCH_VLSE128_V 0x18000007 -#define MASK_VLSE128_V 0x1c00707f -#define MATCH_VLSE16_V 0x8005007 -#define MASK_VLSE16_V 0x1c00707f -#define MATCH_VLSE256_V 0x18005007 -#define MASK_VLSE256_V 0x1c00707f -#define MATCH_VLSE32_V 0x8006007 -#define MASK_VLSE32_V 0x1c00707f -#define MATCH_VLSE512_V 0x18006007 -#define MASK_VLSE512_V 0x1c00707f -#define MATCH_VLSE64_V 0x8007007 -#define MASK_VLSE64_V 0x1c00707f -#define MATCH_VLSE8_V 0x8000007 -#define MASK_VLSE8_V 0x1c00707f -#define MATCH_VLUXEI1024_V 0x14007007 -#define MASK_VLUXEI1024_V 0x1c00707f -#define MATCH_VLUXEI128_V 0x14000007 -#define MASK_VLUXEI128_V 0x1c00707f -#define MATCH_VLUXEI16_V 0x4005007 -#define MASK_VLUXEI16_V 0x1c00707f -#define MATCH_VLUXEI256_V 0x14005007 -#define MASK_VLUXEI256_V 0x1c00707f -#define MATCH_VLUXEI32_V 0x4006007 -#define MASK_VLUXEI32_V 0x1c00707f -#define MATCH_VLUXEI512_V 0x14006007 -#define MASK_VLUXEI512_V 0x1c00707f -#define MATCH_VLUXEI64_V 0x4007007 -#define MASK_VLUXEI64_V 0x1c00707f -#define MATCH_VLUXEI8_V 0x4000007 -#define MASK_VLUXEI8_V 0x1c00707f -#define MATCH_VMACC_VV 0xb4002057 -#define MASK_VMACC_VV 0xfc00707f -#define MATCH_VMACC_VX 0xb4006057 -#define MASK_VMACC_VX 0xfc00707f -#define MATCH_VMADC_VI 0x46003057 -#define MASK_VMADC_VI 0xfe00707f -#define MATCH_VMADC_VIM 0x44003057 -#define MASK_VMADC_VIM 0xfe00707f -#define MATCH_VMADC_VV 0x46000057 -#define MASK_VMADC_VV 0xfe00707f -#define MATCH_VMADC_VVM 0x44000057 -#define MASK_VMADC_VVM 0xfe00707f -#define MATCH_VMADC_VX 0x46004057 -#define MASK_VMADC_VX 0xfe00707f -#define MATCH_VMADC_VXM 0x44004057 -#define MASK_VMADC_VXM 0xfe00707f -#define MATCH_VMADD_VV 0xa4002057 -#define MASK_VMADD_VV 0xfc00707f -#define MATCH_VMADD_VX 0xa4006057 -#define MASK_VMADD_VX 0xfc00707f -#define MATCH_VMAND_MM 0x64002057 -#define MASK_VMAND_MM 0xfc00707f -#define MATCH_VMANDN_MM 0x60002057 -#define MASK_VMANDN_MM 0xfc00707f -#define MATCH_VMAX_VV 0x1c000057 -#define MASK_VMAX_VV 0xfc00707f -#define MATCH_VMAX_VX 0x1c004057 -#define MASK_VMAX_VX 0xfc00707f -#define MATCH_VMAXU_VV 0x18000057 -#define MASK_VMAXU_VV 0xfc00707f -#define MATCH_VMAXU_VX 0x18004057 -#define MASK_VMAXU_VX 0xfc00707f -#define MATCH_VMERGE_VIM 0x5c003057 -#define MASK_VMERGE_VIM 0xfe00707f -#define MATCH_VMERGE_VVM 0x5c000057 -#define MASK_VMERGE_VVM 0xfe00707f -#define MATCH_VMERGE_VXM 0x5c004057 -#define MASK_VMERGE_VXM 0xfe00707f -#define MATCH_VMFEQ_VF 0x60005057 -#define MASK_VMFEQ_VF 0xfc00707f -#define MATCH_VMFEQ_VV 0x60001057 -#define MASK_VMFEQ_VV 0xfc00707f -#define MATCH_VMFGE_VF 0x7c005057 -#define MASK_VMFGE_VF 0xfc00707f -#define MATCH_VMFGT_VF 0x74005057 -#define MASK_VMFGT_VF 0xfc00707f -#define MATCH_VMFLE_VF 0x64005057 -#define MASK_VMFLE_VF 0xfc00707f -#define MATCH_VMFLE_VV 0x64001057 -#define MASK_VMFLE_VV 0xfc00707f -#define MATCH_VMFLT_VF 0x6c005057 -#define MASK_VMFLT_VF 0xfc00707f -#define MATCH_VMFLT_VV 0x6c001057 -#define MASK_VMFLT_VV 0xfc00707f -#define MATCH_VMFNE_VF 0x70005057 -#define MASK_VMFNE_VF 0xfc00707f -#define MATCH_VMFNE_VV 0x70001057 -#define MASK_VMFNE_VV 0xfc00707f -#define MATCH_VMIN_VV 0x14000057 -#define MASK_VMIN_VV 0xfc00707f -#define MATCH_VMIN_VX 0x14004057 -#define MASK_VMIN_VX 0xfc00707f -#define MATCH_VMINU_VV 0x10000057 -#define MASK_VMINU_VV 0xfc00707f -#define MATCH_VMINU_VX 0x10004057 -#define MASK_VMINU_VX 0xfc00707f -#define MATCH_VMNAND_MM 0x74002057 -#define MASK_VMNAND_MM 0xfc00707f -#define MATCH_VMNOR_MM 0x78002057 -#define MASK_VMNOR_MM 0xfc00707f -#define MATCH_VMOR_MM 0x68002057 -#define MASK_VMOR_MM 0xfc00707f -#define MATCH_VMORN_MM 0x70002057 -#define MASK_VMORN_MM 0xfc00707f -#define MATCH_VMSBC_VV 0x4e000057 -#define MASK_VMSBC_VV 0xfe00707f -#define MATCH_VMSBC_VVM 0x4c000057 -#define MASK_VMSBC_VVM 0xfe00707f -#define MATCH_VMSBC_VX 0x4e004057 -#define MASK_VMSBC_VX 0xfe00707f -#define MATCH_VMSBC_VXM 0x4c004057 -#define MASK_VMSBC_VXM 0xfe00707f -#define MATCH_VMSBF_M 0x5000a057 -#define MASK_VMSBF_M 0xfc0ff07f -#define MATCH_VMSEQ_VI 0x60003057 -#define MASK_VMSEQ_VI 0xfc00707f -#define MATCH_VMSEQ_VV 0x60000057 -#define MASK_VMSEQ_VV 0xfc00707f -#define MATCH_VMSEQ_VX 0x60004057 -#define MASK_VMSEQ_VX 0xfc00707f -#define MATCH_VMSGT_VI 0x7c003057 -#define MASK_VMSGT_VI 0xfc00707f -#define MATCH_VMSGT_VX 0x7c004057 -#define MASK_VMSGT_VX 0xfc00707f -#define MATCH_VMSGTU_VI 0x78003057 -#define MASK_VMSGTU_VI 0xfc00707f -#define MATCH_VMSGTU_VX 0x78004057 -#define MASK_VMSGTU_VX 0xfc00707f -#define MATCH_VMSIF_M 0x5001a057 -#define MASK_VMSIF_M 0xfc0ff07f -#define MATCH_VMSLE_VI 0x74003057 -#define MASK_VMSLE_VI 0xfc00707f -#define MATCH_VMSLE_VV 0x74000057 -#define MASK_VMSLE_VV 0xfc00707f -#define MATCH_VMSLE_VX 0x74004057 -#define MASK_VMSLE_VX 0xfc00707f -#define MATCH_VMSLEU_VI 0x70003057 -#define MASK_VMSLEU_VI 0xfc00707f -#define MATCH_VMSLEU_VV 0x70000057 -#define MASK_VMSLEU_VV 0xfc00707f -#define MATCH_VMSLEU_VX 0x70004057 -#define MASK_VMSLEU_VX 0xfc00707f -#define MATCH_VMSLT_VV 0x6c000057 -#define MASK_VMSLT_VV 0xfc00707f -#define MATCH_VMSLT_VX 0x6c004057 -#define MASK_VMSLT_VX 0xfc00707f -#define MATCH_VMSLTU_VV 0x68000057 -#define MASK_VMSLTU_VV 0xfc00707f -#define MATCH_VMSLTU_VX 0x68004057 -#define MASK_VMSLTU_VX 0xfc00707f -#define MATCH_VMSNE_VI 0x64003057 -#define MASK_VMSNE_VI 0xfc00707f -#define MATCH_VMSNE_VV 0x64000057 -#define MASK_VMSNE_VV 0xfc00707f -#define MATCH_VMSNE_VX 0x64004057 -#define MASK_VMSNE_VX 0xfc00707f -#define MATCH_VMSOF_M 0x50012057 -#define MASK_VMSOF_M 0xfc0ff07f -#define MATCH_VMUL_VV 0x94002057 -#define MASK_VMUL_VV 0xfc00707f -#define MATCH_VMUL_VX 0x94006057 -#define MASK_VMUL_VX 0xfc00707f -#define MATCH_VMULH_VV 0x9c002057 -#define MASK_VMULH_VV 0xfc00707f -#define MATCH_VMULH_VX 0x9c006057 -#define MASK_VMULH_VX 0xfc00707f -#define MATCH_VMULHSU_VV 0x98002057 -#define MASK_VMULHSU_VV 0xfc00707f -#define MATCH_VMULHSU_VX 0x98006057 -#define MASK_VMULHSU_VX 0xfc00707f -#define MATCH_VMULHU_VV 0x90002057 -#define MASK_VMULHU_VV 0xfc00707f -#define MATCH_VMULHU_VX 0x90006057 -#define MASK_VMULHU_VX 0xfc00707f -#define MATCH_VMV1R_V 0x9e003057 -#define MASK_VMV1R_V 0xfe0ff07f -#define MATCH_VMV2R_V 0x9e00b057 -#define MASK_VMV2R_V 0xfe0ff07f -#define MATCH_VMV4R_V 0x9e01b057 -#define MASK_VMV4R_V 0xfe0ff07f -#define MATCH_VMV8R_V 0x9e03b057 -#define MASK_VMV8R_V 0xfe0ff07f -#define MATCH_VMV_S_X 0x42006057 -#define MASK_VMV_S_X 0xfff0707f -#define MATCH_VMV_V_I 0x5e003057 -#define MASK_VMV_V_I 0xfff0707f -#define MATCH_VMV_V_V 0x5e000057 -#define MASK_VMV_V_V 0xfff0707f -#define MATCH_VMV_V_X 0x5e004057 -#define MASK_VMV_V_X 0xfff0707f -#define MATCH_VMV_X_S 0x42002057 -#define MASK_VMV_X_S 0xfe0ff07f -#define MATCH_VMXNOR_MM 0x7c002057 -#define MASK_VMXNOR_MM 0xfc00707f -#define MATCH_VMXOR_MM 0x6c002057 -#define MASK_VMXOR_MM 0xfc00707f -#define MATCH_VNCLIP_WI 0xbc003057 -#define MASK_VNCLIP_WI 0xfc00707f -#define MATCH_VNCLIP_WV 0xbc000057 -#define MASK_VNCLIP_WV 0xfc00707f -#define MATCH_VNCLIP_WX 0xbc004057 -#define MASK_VNCLIP_WX 0xfc00707f -#define MATCH_VNCLIPU_WI 0xb8003057 -#define MASK_VNCLIPU_WI 0xfc00707f -#define MATCH_VNCLIPU_WV 0xb8000057 -#define MASK_VNCLIPU_WV 0xfc00707f -#define MATCH_VNCLIPU_WX 0xb8004057 -#define MASK_VNCLIPU_WX 0xfc00707f -#define MATCH_VNMSAC_VV 0xbc002057 -#define MASK_VNMSAC_VV 0xfc00707f -#define MATCH_VNMSAC_VX 0xbc006057 -#define MASK_VNMSAC_VX 0xfc00707f -#define MATCH_VNMSUB_VV 0xac002057 -#define MASK_VNMSUB_VV 0xfc00707f -#define MATCH_VNMSUB_VX 0xac006057 -#define MASK_VNMSUB_VX 0xfc00707f -#define MATCH_VNSRA_WI 0xb4003057 -#define MASK_VNSRA_WI 0xfc00707f -#define MATCH_VNSRA_WV 0xb4000057 -#define MASK_VNSRA_WV 0xfc00707f -#define MATCH_VNSRA_WX 0xb4004057 -#define MASK_VNSRA_WX 0xfc00707f -#define MATCH_VNSRL_WI 0xb0003057 -#define MASK_VNSRL_WI 0xfc00707f -#define MATCH_VNSRL_WV 0xb0000057 -#define MASK_VNSRL_WV 0xfc00707f -#define MATCH_VNSRL_WX 0xb0004057 -#define MASK_VNSRL_WX 0xfc00707f -#define MATCH_VOR_VI 0x28003057 -#define MASK_VOR_VI 0xfc00707f -#define MATCH_VOR_VV 0x28000057 -#define MASK_VOR_VV 0xfc00707f -#define MATCH_VOR_VX 0x28004057 -#define MASK_VOR_VX 0xfc00707f -#define MATCH_VREDAND_VS 0x4002057 -#define MASK_VREDAND_VS 0xfc00707f -#define MATCH_VREDMAX_VS 0x1c002057 -#define MASK_VREDMAX_VS 0xfc00707f -#define MATCH_VREDMAXU_VS 0x18002057 -#define MASK_VREDMAXU_VS 0xfc00707f -#define MATCH_VREDMIN_VS 0x14002057 -#define MASK_VREDMIN_VS 0xfc00707f -#define MATCH_VREDMINU_VS 0x10002057 -#define MASK_VREDMINU_VS 0xfc00707f -#define MATCH_VREDOR_VS 0x8002057 -#define MASK_VREDOR_VS 0xfc00707f -#define MATCH_VREDSUM_VS 0x2057 -#define MASK_VREDSUM_VS 0xfc00707f -#define MATCH_VREDXOR_VS 0xc002057 -#define MASK_VREDXOR_VS 0xfc00707f -#define MATCH_VREM_VV 0x8c002057 -#define MASK_VREM_VV 0xfc00707f -#define MATCH_VREM_VX 0x8c006057 -#define MASK_VREM_VX 0xfc00707f -#define MATCH_VREMU_VV 0x88002057 -#define MASK_VREMU_VV 0xfc00707f -#define MATCH_VREMU_VX 0x88006057 -#define MASK_VREMU_VX 0xfc00707f -#define MATCH_VRGATHER_VI 0x30003057 -#define MASK_VRGATHER_VI 0xfc00707f -#define MATCH_VRGATHER_VV 0x30000057 -#define MASK_VRGATHER_VV 0xfc00707f -#define MATCH_VRGATHER_VX 0x30004057 -#define MASK_VRGATHER_VX 0xfc00707f -#define MATCH_VRGATHEREI16_VV 0x38000057 -#define MASK_VRGATHEREI16_VV 0xfc00707f -#define MATCH_VRSUB_VI 0xc003057 -#define MASK_VRSUB_VI 0xfc00707f -#define MATCH_VRSUB_VX 0xc004057 -#define MASK_VRSUB_VX 0xfc00707f -#define MATCH_VS1R_V 0x2800027 -#define MASK_VS1R_V 0xfff0707f -#define MATCH_VS2R_V 0x22800027 -#define MASK_VS2R_V 0xfff0707f -#define MATCH_VS4R_V 0x62800027 -#define MASK_VS4R_V 0xfff0707f -#define MATCH_VS8R_V 0xe2800027 -#define MASK_VS8R_V 0xfff0707f -#define MATCH_VSADD_VI 0x84003057 -#define MASK_VSADD_VI 0xfc00707f -#define MATCH_VSADD_VV 0x84000057 -#define MASK_VSADD_VV 0xfc00707f -#define MATCH_VSADD_VX 0x84004057 -#define MASK_VSADD_VX 0xfc00707f -#define MATCH_VSADDU_VI 0x80003057 -#define MASK_VSADDU_VI 0xfc00707f -#define MATCH_VSADDU_VV 0x80000057 -#define MASK_VSADDU_VV 0xfc00707f -#define MATCH_VSADDU_VX 0x80004057 -#define MASK_VSADDU_VX 0xfc00707f -#define MATCH_VSBC_VVM 0x48000057 -#define MASK_VSBC_VVM 0xfe00707f -#define MATCH_VSBC_VXM 0x48004057 -#define MASK_VSBC_VXM 0xfe00707f -#define MATCH_VSE1024_V 0x10007027 -#define MASK_VSE1024_V 0x1df0707f -#define MATCH_VSE128_V 0x10000027 -#define MASK_VSE128_V 0x1df0707f -#define MATCH_VSE16_V 0x5027 -#define MASK_VSE16_V 0x1df0707f -#define MATCH_VSE256_V 0x10005027 -#define MASK_VSE256_V 0x1df0707f -#define MATCH_VSE32_V 0x6027 -#define MASK_VSE32_V 0x1df0707f -#define MATCH_VSE512_V 0x10006027 -#define MASK_VSE512_V 0x1df0707f -#define MATCH_VSE64_V 0x7027 -#define MASK_VSE64_V 0x1df0707f -#define MATCH_VSE8_V 0x27 -#define MASK_VSE8_V 0x1df0707f -#define MATCH_VSETIVLI 0xc0007057 -#define MASK_VSETIVLI 0xc000707f -#define MATCH_VSETVL 0x80007057 -#define MASK_VSETVL 0xfe00707f -#define MATCH_VSETVLI 0x7057 -#define MASK_VSETVLI 0x8000707f -#define MATCH_VSEXT_VF2 0x4803a057 -#define MASK_VSEXT_VF2 0xfc0ff07f -#define MATCH_VSEXT_VF4 0x4802a057 -#define MASK_VSEXT_VF4 0xfc0ff07f -#define MATCH_VSEXT_VF8 0x4801a057 -#define MASK_VSEXT_VF8 0xfc0ff07f -#define MATCH_VSLIDE1DOWN_VX 0x3c006057 -#define MASK_VSLIDE1DOWN_VX 0xfc00707f -#define MATCH_VSLIDE1UP_VX 0x38006057 -#define MASK_VSLIDE1UP_VX 0xfc00707f -#define MATCH_VSLIDEDOWN_VI 0x3c003057 -#define MASK_VSLIDEDOWN_VI 0xfc00707f -#define MATCH_VSLIDEDOWN_VX 0x3c004057 -#define MASK_VSLIDEDOWN_VX 0xfc00707f -#define MATCH_VSLIDEUP_VI 0x38003057 -#define MASK_VSLIDEUP_VI 0xfc00707f -#define MATCH_VSLIDEUP_VX 0x38004057 -#define MASK_VSLIDEUP_VX 0xfc00707f -#define MATCH_VSLL_VI 0x94003057 -#define MASK_VSLL_VI 0xfc00707f -#define MATCH_VSLL_VV 0x94000057 -#define MASK_VSLL_VV 0xfc00707f -#define MATCH_VSLL_VX 0x94004057 -#define MASK_VSLL_VX 0xfc00707f -#define MATCH_VSM_V 0x2b00027 -#define MASK_VSM_V 0xfff0707f -#define MATCH_VSMUL_VV 0x9c000057 -#define MASK_VSMUL_VV 0xfc00707f -#define MATCH_VSMUL_VX 0x9c004057 -#define MASK_VSMUL_VX 0xfc00707f -#define MATCH_VSOXEI1024_V 0x1c007027 -#define MASK_VSOXEI1024_V 0x1c00707f -#define MATCH_VSOXEI128_V 0x1c000027 -#define MASK_VSOXEI128_V 0x1c00707f -#define MATCH_VSOXEI16_V 0xc005027 -#define MASK_VSOXEI16_V 0x1c00707f -#define MATCH_VSOXEI256_V 0x1c005027 -#define MASK_VSOXEI256_V 0x1c00707f -#define MATCH_VSOXEI32_V 0xc006027 -#define MASK_VSOXEI32_V 0x1c00707f -#define MATCH_VSOXEI512_V 0x1c006027 -#define MASK_VSOXEI512_V 0x1c00707f -#define MATCH_VSOXEI64_V 0xc007027 -#define MASK_VSOXEI64_V 0x1c00707f -#define MATCH_VSOXEI8_V 0xc000027 -#define MASK_VSOXEI8_V 0x1c00707f -#define MATCH_VSRA_VI 0xa4003057 -#define MASK_VSRA_VI 0xfc00707f -#define MATCH_VSRA_VV 0xa4000057 -#define MASK_VSRA_VV 0xfc00707f -#define MATCH_VSRA_VX 0xa4004057 -#define MASK_VSRA_VX 0xfc00707f -#define MATCH_VSRL_VI 0xa0003057 -#define MASK_VSRL_VI 0xfc00707f -#define MATCH_VSRL_VV 0xa0000057 -#define MASK_VSRL_VV 0xfc00707f -#define MATCH_VSRL_VX 0xa0004057 -#define MASK_VSRL_VX 0xfc00707f -#define MATCH_VSSE1024_V 0x18007027 -#define MASK_VSSE1024_V 0x1c00707f -#define MATCH_VSSE128_V 0x18000027 -#define MASK_VSSE128_V 0x1c00707f -#define MATCH_VSSE16_V 0x8005027 -#define MASK_VSSE16_V 0x1c00707f -#define MATCH_VSSE256_V 0x18005027 -#define MASK_VSSE256_V 0x1c00707f -#define MATCH_VSSE32_V 0x8006027 -#define MASK_VSSE32_V 0x1c00707f -#define MATCH_VSSE512_V 0x18006027 -#define MASK_VSSE512_V 0x1c00707f -#define MATCH_VSSE64_V 0x8007027 -#define MASK_VSSE64_V 0x1c00707f -#define MATCH_VSSE8_V 0x8000027 -#define MASK_VSSE8_V 0x1c00707f -#define MATCH_VSSRA_VI 0xac003057 -#define MASK_VSSRA_VI 0xfc00707f -#define MATCH_VSSRA_VV 0xac000057 -#define MASK_VSSRA_VV 0xfc00707f -#define MATCH_VSSRA_VX 0xac004057 -#define MASK_VSSRA_VX 0xfc00707f -#define MATCH_VSSRL_VI 0xa8003057 -#define MASK_VSSRL_VI 0xfc00707f -#define MATCH_VSSRL_VV 0xa8000057 -#define MASK_VSSRL_VV 0xfc00707f -#define MATCH_VSSRL_VX 0xa8004057 -#define MASK_VSSRL_VX 0xfc00707f -#define MATCH_VSSUB_VV 0x8c000057 -#define MASK_VSSUB_VV 0xfc00707f -#define MATCH_VSSUB_VX 0x8c004057 -#define MASK_VSSUB_VX 0xfc00707f -#define MATCH_VSSUBU_VV 0x88000057 -#define MASK_VSSUBU_VV 0xfc00707f -#define MATCH_VSSUBU_VX 0x88004057 -#define MASK_VSSUBU_VX 0xfc00707f -#define MATCH_VSUB_VV 0x8000057 -#define MASK_VSUB_VV 0xfc00707f -#define MATCH_VSUB_VX 0x8004057 -#define MASK_VSUB_VX 0xfc00707f -#define MATCH_VSUXEI1024_V 0x14007027 -#define MASK_VSUXEI1024_V 0x1c00707f -#define MATCH_VSUXEI128_V 0x14000027 -#define MASK_VSUXEI128_V 0x1c00707f -#define MATCH_VSUXEI16_V 0x4005027 -#define MASK_VSUXEI16_V 0x1c00707f -#define MATCH_VSUXEI256_V 0x14005027 -#define MASK_VSUXEI256_V 0x1c00707f -#define MATCH_VSUXEI32_V 0x4006027 -#define MASK_VSUXEI32_V 0x1c00707f -#define MATCH_VSUXEI512_V 0x14006027 -#define MASK_VSUXEI512_V 0x1c00707f -#define MATCH_VSUXEI64_V 0x4007027 -#define MASK_VSUXEI64_V 0x1c00707f -#define MATCH_VSUXEI8_V 0x4000027 -#define MASK_VSUXEI8_V 0x1c00707f -#define MATCH_VWADD_VV 0xc4002057 -#define MASK_VWADD_VV 0xfc00707f -#define MATCH_VWADD_VX 0xc4006057 -#define MASK_VWADD_VX 0xfc00707f -#define MATCH_VWADD_WV 0xd4002057 -#define MASK_VWADD_WV 0xfc00707f -#define MATCH_VWADD_WX 0xd4006057 -#define MASK_VWADD_WX 0xfc00707f -#define MATCH_VWADDU_VV 0xc0002057 -#define MASK_VWADDU_VV 0xfc00707f -#define MATCH_VWADDU_VX 0xc0006057 -#define MASK_VWADDU_VX 0xfc00707f -#define MATCH_VWADDU_WV 0xd0002057 -#define MASK_VWADDU_WV 0xfc00707f -#define MATCH_VWADDU_WX 0xd0006057 -#define MASK_VWADDU_WX 0xfc00707f -#define MATCH_VWMACC_VV 0xf4002057 -#define MASK_VWMACC_VV 0xfc00707f -#define MATCH_VWMACC_VX 0xf4006057 -#define MASK_VWMACC_VX 0xfc00707f -#define MATCH_VWMACCSU_VV 0xfc002057 -#define MASK_VWMACCSU_VV 0xfc00707f -#define MATCH_VWMACCSU_VX 0xfc006057 -#define MASK_VWMACCSU_VX 0xfc00707f -#define MATCH_VWMACCU_VV 0xf0002057 -#define MASK_VWMACCU_VV 0xfc00707f -#define MATCH_VWMACCU_VX 0xf0006057 -#define MASK_VWMACCU_VX 0xfc00707f -#define MATCH_VWMACCUS_VX 0xf8006057 -#define MASK_VWMACCUS_VX 0xfc00707f -#define MATCH_VWMUL_VV 0xec002057 -#define MASK_VWMUL_VV 0xfc00707f -#define MATCH_VWMUL_VX 0xec006057 -#define MASK_VWMUL_VX 0xfc00707f -#define MATCH_VWMULSU_VV 0xe8002057 -#define MASK_VWMULSU_VV 0xfc00707f -#define MATCH_VWMULSU_VX 0xe8006057 -#define MASK_VWMULSU_VX 0xfc00707f -#define MATCH_VWMULU_VV 0xe0002057 -#define MASK_VWMULU_VV 0xfc00707f -#define MATCH_VWMULU_VX 0xe0006057 -#define MASK_VWMULU_VX 0xfc00707f -#define MATCH_VWREDSUM_VS 0xc4000057 -#define MASK_VWREDSUM_VS 0xfc00707f -#define MATCH_VWREDSUMU_VS 0xc0000057 -#define MASK_VWREDSUMU_VS 0xfc00707f -#define MATCH_VWSUB_VV 0xcc002057 -#define MASK_VWSUB_VV 0xfc00707f -#define MATCH_VWSUB_VX 0xcc006057 -#define MASK_VWSUB_VX 0xfc00707f -#define MATCH_VWSUB_WV 0xdc002057 -#define MASK_VWSUB_WV 0xfc00707f -#define MATCH_VWSUB_WX 0xdc006057 -#define MASK_VWSUB_WX 0xfc00707f -#define MATCH_VWSUBU_VV 0xc8002057 -#define MASK_VWSUBU_VV 0xfc00707f -#define MATCH_VWSUBU_VX 0xc8006057 -#define MASK_VWSUBU_VX 0xfc00707f -#define MATCH_VWSUBU_WV 0xd8002057 -#define MASK_VWSUBU_WV 0xfc00707f -#define MATCH_VWSUBU_WX 0xd8006057 -#define MASK_VWSUBU_WX 0xfc00707f -#define MATCH_VXOR_VI 0x2c003057 -#define MASK_VXOR_VI 0xfc00707f -#define MATCH_VXOR_VV 0x2c000057 -#define MASK_VXOR_VV 0xfc00707f -#define MATCH_VXOR_VX 0x2c004057 -#define MASK_VXOR_VX 0xfc00707f -#define MATCH_VZEXT_VF2 0x48032057 -#define MASK_VZEXT_VF2 0xfc0ff07f -#define MATCH_VZEXT_VF4 0x48022057 -#define MASK_VZEXT_VF4 0xfc0ff07f -#define MATCH_VZEXT_VF8 0x48012057 -#define MASK_VZEXT_VF8 0xfc0ff07f -#define MATCH_WFI 0x10500073 -#define MASK_WFI 0xffffffff -#define MATCH_WRS_NTO 0xd00073 -#define MASK_WRS_NTO 0xffffffff -#define MATCH_WRS_STO 0x1d00073 -#define MASK_WRS_STO 0xffffffff -#define MATCH_XNOR 0x40004033 -#define MASK_XNOR 0xfe00707f -#define MATCH_XOR 0x4033 -#define MASK_XOR 0xfe00707f -#define MATCH_XORI 0x4013 -#define MASK_XORI 0x707f -#define MATCH_XPERM16 0x28006033 -#define MASK_XPERM16 0xfe00707f -#define MATCH_XPERM32 0x28000033 -#define MASK_XPERM32 0xfe00707f -#define MATCH_XPERM4 0x28002033 -#define MASK_XPERM4 0xfe00707f -#define MATCH_XPERM8 0x28004033 -#define MASK_XPERM8 0xfe00707f -#define MATCH_ZUNPKD810 0xacc00077 -#define MASK_ZUNPKD810 0xfff0707f -#define MATCH_ZUNPKD820 0xacd00077 -#define MASK_ZUNPKD820 0xfff0707f -#define MATCH_ZUNPKD830 0xace00077 -#define MASK_ZUNPKD830 0xfff0707f -#define MATCH_ZUNPKD831 0xacf00077 -#define MASK_ZUNPKD831 0xfff0707f -#define MATCH_ZUNPKD832 0xad700077 -#define MASK_ZUNPKD832 0xfff0707f - -#define CSR_FFLAGS 0x1 -#define CSR_FRM 0x2 -#define CSR_FCSR 0x3 -#define CSR_VSTART 0x8 -#define CSR_VXSAT 0x9 -#define CSR_VXRM 0xa -#define CSR_VCSR 0xf -#define CSR_SEED 0x15 -#define CSR_JVT 0x17 -#define CSR_CYCLE 0xc00 -#define CSR_TIME 0xc01 -#define CSR_INSTRET 0xc02 -#define CSR_HPMCOUNTER3 0xc03 -#define CSR_HPMCOUNTER4 0xc04 -#define CSR_HPMCOUNTER5 0xc05 -#define CSR_HPMCOUNTER6 0xc06 -#define CSR_HPMCOUNTER7 0xc07 -#define CSR_HPMCOUNTER8 0xc08 -#define CSR_HPMCOUNTER9 0xc09 -#define CSR_HPMCOUNTER10 0xc0a -#define CSR_HPMCOUNTER11 0xc0b -#define CSR_HPMCOUNTER12 0xc0c -#define CSR_HPMCOUNTER13 0xc0d -#define CSR_HPMCOUNTER14 0xc0e -#define CSR_HPMCOUNTER15 0xc0f -#define CSR_HPMCOUNTER16 0xc10 -#define CSR_HPMCOUNTER17 0xc11 -#define CSR_HPMCOUNTER18 0xc12 -#define CSR_HPMCOUNTER19 0xc13 -#define CSR_HPMCOUNTER20 0xc14 -#define CSR_HPMCOUNTER21 0xc15 -#define CSR_HPMCOUNTER22 0xc16 -#define CSR_HPMCOUNTER23 0xc17 -#define CSR_HPMCOUNTER24 0xc18 -#define CSR_HPMCOUNTER25 0xc19 -#define CSR_HPMCOUNTER26 0xc1a -#define CSR_HPMCOUNTER27 0xc1b -#define CSR_HPMCOUNTER28 0xc1c -#define CSR_HPMCOUNTER29 0xc1d -#define CSR_HPMCOUNTER30 0xc1e -#define CSR_HPMCOUNTER31 0xc1f -#define CSR_VL 0xc20 -#define CSR_VTYPE 0xc21 -#define CSR_VLENB 0xc22 -#define CSR_SSTATUS 0x100 -#define CSR_SEDELEG 0x102 -#define CSR_SIDELEG 0x103 -#define CSR_SIE 0x104 -#define CSR_STVEC 0x105 -#define CSR_SCOUNTEREN 0x106 -#define CSR_SENVCFG 0x10a -#define CSR_SSTATEEN0 0x10c -#define CSR_SSTATEEN1 0x10d -#define CSR_SSTATEEN2 0x10e -#define CSR_SSTATEEN3 0x10f -#define CSR_SSCRATCH 0x140 -#define CSR_SEPC 0x141 -#define CSR_SCAUSE 0x142 -#define CSR_STVAL 0x143 -#define CSR_SIP 0x144 -#define CSR_STIMECMP 0x14d -#define CSR_SISELECT 0x150 -#define CSR_SIREG 0x151 -#define CSR_STOPEI 0x15c -#define CSR_SATP 0x180 -#define CSR_SCONTEXT 0x5a8 -#define CSR_VSSTATUS 0x200 -#define CSR_VSIE 0x204 -#define CSR_VSTVEC 0x205 -#define CSR_VSSCRATCH 0x240 -#define CSR_VSEPC 0x241 -#define CSR_VSCAUSE 0x242 -#define CSR_VSTVAL 0x243 -#define CSR_VSIP 0x244 -#define CSR_VSTIMECMP 0x24d -#define CSR_VSISELECT 0x250 -#define CSR_VSIREG 0x251 -#define CSR_VSTOPEI 0x25c -#define CSR_VSATP 0x280 -#define CSR_HSTATUS 0x600 -#define CSR_HEDELEG 0x602 -#define CSR_HIDELEG 0x603 -#define CSR_HIE 0x604 -#define CSR_HTIMEDELTA 0x605 -#define CSR_HCOUNTEREN 0x606 -#define CSR_HGEIE 0x607 -#define CSR_HVIEN 0x608 -#define CSR_HVICTL 0x609 -#define CSR_HENVCFG 0x60a -#define CSR_HSTATEEN0 0x60c -#define CSR_HSTATEEN1 0x60d -#define CSR_HSTATEEN2 0x60e -#define CSR_HSTATEEN3 0x60f -#define CSR_HTVAL 0x643 -#define CSR_HIP 0x644 -#define CSR_HVIP 0x645 -#define CSR_HVIPRIO1 0x646 -#define CSR_HVIPRIO2 0x647 -#define CSR_HTINST 0x64a -#define CSR_HGATP 0x680 -#define CSR_HCONTEXT 0x6a8 -#define CSR_HGEIP 0xe12 -#define CSR_VSTOPI 0xeb0 -#define CSR_SCOUNTOVF 0xda0 -#define CSR_STOPI 0xdb0 -#define CSR_UTVT 0x7 -#define CSR_UNXTI 0x45 -#define CSR_UINTSTATUS 0x46 -#define CSR_USCRATCHCSW 0x48 -#define CSR_USCRATCHCSWL 0x49 -#define CSR_STVT 0x107 -#define CSR_SNXTI 0x145 -#define CSR_SINTSTATUS 0x146 -#define CSR_SSCRATCHCSW 0x148 -#define CSR_SSCRATCHCSWL 0x149 -#define CSR_MTVT 0x307 -#define CSR_MNXTI 0x345 -#define CSR_MINTSTATUS 0x346 -#define CSR_MSCRATCHCSW 0x348 -#define CSR_MSCRATCHCSWL 0x349 -#define CSR_MSTATUS 0x300 -#define CSR_MISA 0x301 -#define CSR_MEDELEG 0x302 -#define CSR_MIDELEG 0x303 -#define CSR_MIE 0x304 -#define CSR_MTVEC 0x305 -#define CSR_MCOUNTEREN 0x306 -#define CSR_MVIEN 0x308 -#define CSR_MVIP 0x309 -#define CSR_MENVCFG 0x30a -#define CSR_MSTATEEN0 0x30c -#define CSR_MSTATEEN1 0x30d -#define CSR_MSTATEEN2 0x30e -#define CSR_MSTATEEN3 0x30f -#define CSR_MCOUNTINHIBIT 0x320 -#define CSR_MSCRATCH 0x340 -#define CSR_MEPC 0x341 -#define CSR_MCAUSE 0x342 -#define CSR_MTVAL 0x343 -#define CSR_MIP 0x344 -#define CSR_MTINST 0x34a -#define CSR_MTVAL2 0x34b -#define CSR_MISELECT 0x350 -#define CSR_MIREG 0x351 -#define CSR_MTOPEI 0x35c -#define CSR_PMPCFG0 0x3a0 -#define CSR_PMPCFG1 0x3a1 -#define CSR_PMPCFG2 0x3a2 -#define CSR_PMPCFG3 0x3a3 -#define CSR_PMPCFG4 0x3a4 -#define CSR_PMPCFG5 0x3a5 -#define CSR_PMPCFG6 0x3a6 -#define CSR_PMPCFG7 0x3a7 -#define CSR_PMPCFG8 0x3a8 -#define CSR_PMPCFG9 0x3a9 -#define CSR_PMPCFG10 0x3aa -#define CSR_PMPCFG11 0x3ab -#define CSR_PMPCFG12 0x3ac -#define CSR_PMPCFG13 0x3ad -#define CSR_PMPCFG14 0x3ae -#define CSR_PMPCFG15 0x3af -#define CSR_PMPADDR0 0x3b0 -#define CSR_PMPADDR1 0x3b1 -#define CSR_PMPADDR2 0x3b2 -#define CSR_PMPADDR3 0x3b3 -#define CSR_PMPADDR4 0x3b4 -#define CSR_PMPADDR5 0x3b5 -#define CSR_PMPADDR6 0x3b6 -#define CSR_PMPADDR7 0x3b7 -#define CSR_PMPADDR8 0x3b8 -#define CSR_PMPADDR9 0x3b9 -#define CSR_PMPADDR10 0x3ba -#define CSR_PMPADDR11 0x3bb -#define CSR_PMPADDR12 0x3bc -#define CSR_PMPADDR13 0x3bd -#define CSR_PMPADDR14 0x3be -#define CSR_PMPADDR15 0x3bf -#define CSR_PMPADDR16 0x3c0 -#define CSR_PMPADDR17 0x3c1 -#define CSR_PMPADDR18 0x3c2 -#define CSR_PMPADDR19 0x3c3 -#define CSR_PMPADDR20 0x3c4 -#define CSR_PMPADDR21 0x3c5 -#define CSR_PMPADDR22 0x3c6 -#define CSR_PMPADDR23 0x3c7 -#define CSR_PMPADDR24 0x3c8 -#define CSR_PMPADDR25 0x3c9 -#define CSR_PMPADDR26 0x3ca -#define CSR_PMPADDR27 0x3cb -#define CSR_PMPADDR28 0x3cc -#define CSR_PMPADDR29 0x3cd -#define CSR_PMPADDR30 0x3ce -#define CSR_PMPADDR31 0x3cf -#define CSR_PMPADDR32 0x3d0 -#define CSR_PMPADDR33 0x3d1 -#define CSR_PMPADDR34 0x3d2 -#define CSR_PMPADDR35 0x3d3 -#define CSR_PMPADDR36 0x3d4 -#define CSR_PMPADDR37 0x3d5 -#define CSR_PMPADDR38 0x3d6 -#define CSR_PMPADDR39 0x3d7 -#define CSR_PMPADDR40 0x3d8 -#define CSR_PMPADDR41 0x3d9 -#define CSR_PMPADDR42 0x3da -#define CSR_PMPADDR43 0x3db -#define CSR_PMPADDR44 0x3dc -#define CSR_PMPADDR45 0x3dd -#define CSR_PMPADDR46 0x3de -#define CSR_PMPADDR47 0x3df -#define CSR_PMPADDR48 0x3e0 -#define CSR_PMPADDR49 0x3e1 -#define CSR_PMPADDR50 0x3e2 -#define CSR_PMPADDR51 0x3e3 -#define CSR_PMPADDR52 0x3e4 -#define CSR_PMPADDR53 0x3e5 -#define CSR_PMPADDR54 0x3e6 -#define CSR_PMPADDR55 0x3e7 -#define CSR_PMPADDR56 0x3e8 -#define CSR_PMPADDR57 0x3e9 -#define CSR_PMPADDR58 0x3ea -#define CSR_PMPADDR59 0x3eb -#define CSR_PMPADDR60 0x3ec -#define CSR_PMPADDR61 0x3ed -#define CSR_PMPADDR62 0x3ee -#define CSR_PMPADDR63 0x3ef -#define CSR_MSECCFG 0x747 -#define CSR_TSELECT 0x7a0 -#define CSR_TDATA1 0x7a1 -#define CSR_TDATA2 0x7a2 -#define CSR_TDATA3 0x7a3 -#define CSR_TINFO 0x7a4 -#define CSR_TCONTROL 0x7a5 -#define CSR_MCONTEXT 0x7a8 -#define CSR_MSCONTEXT 0x7aa -#define CSR_DCSR 0x7b0 -#define CSR_DPC 0x7b1 -#define CSR_DSCRATCH0 0x7b2 -#define CSR_DSCRATCH1 0x7b3 -#define CSR_MCYCLE 0xb00 -#define CSR_MINSTRET 0xb02 -#define CSR_MHPMCOUNTER3 0xb03 -#define CSR_MHPMCOUNTER4 0xb04 -#define CSR_MHPMCOUNTER5 0xb05 -#define CSR_MHPMCOUNTER6 0xb06 -#define CSR_MHPMCOUNTER7 0xb07 -#define CSR_MHPMCOUNTER8 0xb08 -#define CSR_MHPMCOUNTER9 0xb09 -#define CSR_MHPMCOUNTER10 0xb0a -#define CSR_MHPMCOUNTER11 0xb0b -#define CSR_MHPMCOUNTER12 0xb0c -#define CSR_MHPMCOUNTER13 0xb0d -#define CSR_MHPMCOUNTER14 0xb0e -#define CSR_MHPMCOUNTER15 0xb0f -#define CSR_MHPMCOUNTER16 0xb10 -#define CSR_MHPMCOUNTER17 0xb11 -#define CSR_MHPMCOUNTER18 0xb12 -#define CSR_MHPMCOUNTER19 0xb13 -#define CSR_MHPMCOUNTER20 0xb14 -#define CSR_MHPMCOUNTER21 0xb15 -#define CSR_MHPMCOUNTER22 0xb16 -#define CSR_MHPMCOUNTER23 0xb17 -#define CSR_MHPMCOUNTER24 0xb18 -#define CSR_MHPMCOUNTER25 0xb19 -#define CSR_MHPMCOUNTER26 0xb1a -#define CSR_MHPMCOUNTER27 0xb1b -#define CSR_MHPMCOUNTER28 0xb1c -#define CSR_MHPMCOUNTER29 0xb1d -#define CSR_MHPMCOUNTER30 0xb1e -#define CSR_MHPMCOUNTER31 0xb1f -#define CSR_MHPMEVENT3 0x323 -#define CSR_MHPMEVENT4 0x324 -#define CSR_MHPMEVENT5 0x325 -#define CSR_MHPMEVENT6 0x326 -#define CSR_MHPMEVENT7 0x327 -#define CSR_MHPMEVENT8 0x328 -#define CSR_MHPMEVENT9 0x329 -#define CSR_MHPMEVENT10 0x32a -#define CSR_MHPMEVENT11 0x32b -#define CSR_MHPMEVENT12 0x32c -#define CSR_MHPMEVENT13 0x32d -#define CSR_MHPMEVENT14 0x32e -#define CSR_MHPMEVENT15 0x32f -#define CSR_MHPMEVENT16 0x330 -#define CSR_MHPMEVENT17 0x331 -#define CSR_MHPMEVENT18 0x332 -#define CSR_MHPMEVENT19 0x333 -#define CSR_MHPMEVENT20 0x334 -#define CSR_MHPMEVENT21 0x335 -#define CSR_MHPMEVENT22 0x336 -#define CSR_MHPMEVENT23 0x337 -#define CSR_MHPMEVENT24 0x338 -#define CSR_MHPMEVENT25 0x339 -#define CSR_MHPMEVENT26 0x33a -#define CSR_MHPMEVENT27 0x33b -#define CSR_MHPMEVENT28 0x33c -#define CSR_MHPMEVENT29 0x33d -#define CSR_MHPMEVENT30 0x33e -#define CSR_MHPMEVENT31 0x33f -#define CSR_MVENDORID 0xf11 -#define CSR_MARCHID 0xf12 -#define CSR_MIMPID 0xf13 -#define CSR_MHARTID 0xf14 -#define CSR_MCONFIGPTR 0xf15 -#define CSR_MTOPI 0xfb0 -#define CSR_SIEH 0x114 -#define CSR_SIPH 0x154 -#define CSR_STIMECMPH 0x15d -#define CSR_VSIEH 0x214 -#define CSR_VSIPH 0x254 -#define CSR_VSTIMECMPH 0x25d -#define CSR_HTIMEDELTAH 0x615 -#define CSR_HIDELEGH 0x613 -#define CSR_HVIENH 0x618 -#define CSR_HENVCFGH 0x61a -#define CSR_HVIPH 0x655 -#define CSR_HVIPRIO1H 0x656 -#define CSR_HVIPRIO2H 0x657 -#define CSR_HSTATEEN0H 0x61c -#define CSR_HSTATEEN1H 0x61d -#define CSR_HSTATEEN2H 0x61e -#define CSR_HSTATEEN3H 0x61f -#define CSR_CYCLEH 0xc80 -#define CSR_TIMEH 0xc81 -#define CSR_INSTRETH 0xc82 -#define CSR_HPMCOUNTER3H 0xc83 -#define CSR_HPMCOUNTER4H 0xc84 -#define CSR_HPMCOUNTER5H 0xc85 -#define CSR_HPMCOUNTER6H 0xc86 -#define CSR_HPMCOUNTER7H 0xc87 -#define CSR_HPMCOUNTER8H 0xc88 -#define CSR_HPMCOUNTER9H 0xc89 -#define CSR_HPMCOUNTER10H 0xc8a -#define CSR_HPMCOUNTER11H 0xc8b -#define CSR_HPMCOUNTER12H 0xc8c -#define CSR_HPMCOUNTER13H 0xc8d -#define CSR_HPMCOUNTER14H 0xc8e -#define CSR_HPMCOUNTER15H 0xc8f -#define CSR_HPMCOUNTER16H 0xc90 -#define CSR_HPMCOUNTER17H 0xc91 -#define CSR_HPMCOUNTER18H 0xc92 -#define CSR_HPMCOUNTER19H 0xc93 -#define CSR_HPMCOUNTER20H 0xc94 -#define CSR_HPMCOUNTER21H 0xc95 -#define CSR_HPMCOUNTER22H 0xc96 -#define CSR_HPMCOUNTER23H 0xc97 -#define CSR_HPMCOUNTER24H 0xc98 -#define CSR_HPMCOUNTER25H 0xc99 -#define CSR_HPMCOUNTER26H 0xc9a -#define CSR_HPMCOUNTER27H 0xc9b -#define CSR_HPMCOUNTER28H 0xc9c -#define CSR_HPMCOUNTER29H 0xc9d -#define CSR_HPMCOUNTER30H 0xc9e -#define CSR_HPMCOUNTER31H 0xc9f -#define CSR_MSTATUSH 0x310 -#define CSR_MIDELEGH 0x313 -#define CSR_MIEH 0x314 -#define CSR_MVIENH 0x318 -#define CSR_MVIPH 0x319 -#define CSR_MENVCFGH 0x31a -#define CSR_MSTATEEN0H 0x31c -#define CSR_MSTATEEN1H 0x31d -#define CSR_MSTATEEN2H 0x31e -#define CSR_MSTATEEN3H 0x31f -#define CSR_MIPH 0x354 -#define CSR_MHPMEVENT3H 0x723 -#define CSR_MHPMEVENT4H 0x724 -#define CSR_MHPMEVENT5H 0x725 -#define CSR_MHPMEVENT6H 0x726 -#define CSR_MHPMEVENT7H 0x727 -#define CSR_MHPMEVENT8H 0x728 -#define CSR_MHPMEVENT9H 0x729 -#define CSR_MHPMEVENT10H 0x72a -#define CSR_MHPMEVENT11H 0x72b -#define CSR_MHPMEVENT12H 0x72c -#define CSR_MHPMEVENT13H 0x72d -#define CSR_MHPMEVENT14H 0x72e -#define CSR_MHPMEVENT15H 0x72f -#define CSR_MHPMEVENT16H 0x730 -#define CSR_MHPMEVENT17H 0x731 -#define CSR_MHPMEVENT18H 0x732 -#define CSR_MHPMEVENT19H 0x733 -#define CSR_MHPMEVENT20H 0x734 -#define CSR_MHPMEVENT21H 0x735 -#define CSR_MHPMEVENT22H 0x736 -#define CSR_MHPMEVENT23H 0x737 -#define CSR_MHPMEVENT24H 0x738 -#define CSR_MHPMEVENT25H 0x739 -#define CSR_MHPMEVENT26H 0x73a -#define CSR_MHPMEVENT27H 0x73b -#define CSR_MHPMEVENT28H 0x73c -#define CSR_MHPMEVENT29H 0x73d -#define CSR_MHPMEVENT30H 0x73e -#define CSR_MHPMEVENT31H 0x73f -#define CSR_MNSCRATCH 0x740 -#define CSR_MNEPC 0x741 -#define CSR_MNCAUSE 0x742 -#define CSR_MNSTATUS 0x744 -#define CSR_MSECCFGH 0x757 -#define CSR_MCYCLEH 0xb80 -#define CSR_MINSTRETH 0xb82 -#define CSR_MHPMCOUNTER3H 0xb83 -#define CSR_MHPMCOUNTER4H 0xb84 -#define CSR_MHPMCOUNTER5H 0xb85 -#define CSR_MHPMCOUNTER6H 0xb86 -#define CSR_MHPMCOUNTER7H 0xb87 -#define CSR_MHPMCOUNTER8H 0xb88 -#define CSR_MHPMCOUNTER9H 0xb89 -#define CSR_MHPMCOUNTER10H 0xb8a -#define CSR_MHPMCOUNTER11H 0xb8b -#define CSR_MHPMCOUNTER12H 0xb8c -#define CSR_MHPMCOUNTER13H 0xb8d -#define CSR_MHPMCOUNTER14H 0xb8e -#define CSR_MHPMCOUNTER15H 0xb8f -#define CSR_MHPMCOUNTER16H 0xb90 -#define CSR_MHPMCOUNTER17H 0xb91 -#define CSR_MHPMCOUNTER18H 0xb92 -#define CSR_MHPMCOUNTER19H 0xb93 -#define CSR_MHPMCOUNTER20H 0xb94 -#define CSR_MHPMCOUNTER21H 0xb95 -#define CSR_MHPMCOUNTER22H 0xb96 -#define CSR_MHPMCOUNTER23H 0xb97 -#define CSR_MHPMCOUNTER24H 0xb98 -#define CSR_MHPMCOUNTER25H 0xb99 -#define CSR_MHPMCOUNTER26H 0xb9a -#define CSR_MHPMCOUNTER27H 0xb9b -#define CSR_MHPMCOUNTER28H 0xb9c -#define CSR_MHPMCOUNTER29H 0xb9d -#define CSR_MHPMCOUNTER30H 0xb9e -#define CSR_MHPMCOUNTER31H 0xb9f - -#define CAUSE_MISALIGNED_FETCH 0x0 -#define CAUSE_FETCH_ACCESS 0x1 -#define CAUSE_ILLEGAL_INSTRUCTION 0x2 -#define CAUSE_BREAKPOINT 0x3 -#define CAUSE_MISALIGNED_LOAD 0x4 -#define CAUSE_LOAD_ACCESS 0x5 -#define CAUSE_MISALIGNED_STORE 0x6 -#define CAUSE_STORE_ACCESS 0x7 -#define CAUSE_USER_ECALL 0x8 -#define CAUSE_SUPERVISOR_ECALL 0x9 -#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa -#define CAUSE_MACHINE_ECALL 0xb -#define CAUSE_FETCH_PAGE_FAULT 0xc -#define CAUSE_LOAD_PAGE_FAULT 0xd -#define CAUSE_STORE_PAGE_FAULT 0xf -#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 -#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 -#define CAUSE_VIRTUAL_INSTRUCTION 0x16 -#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 - -#define INSN_FIELD_RD 0xf80 -#define INSN_FIELD_RT 0xf8000 -#define INSN_FIELD_RS1 0xf8000 -#define INSN_FIELD_RS2 0x1f00000 -#define INSN_FIELD_RS3 0xf8000000 -#define INSN_FIELD_AQRL 0x6000000 -#define INSN_FIELD_AQ 0x4000000 -#define INSN_FIELD_RL 0x2000000 -#define INSN_FIELD_FM 0xf0000000 -#define INSN_FIELD_PRED 0xf000000 -#define INSN_FIELD_SUCC 0xf00000 -#define INSN_FIELD_RM 0x7000 -#define INSN_FIELD_FUNCT3 0x7000 -#define INSN_FIELD_FUNCT2 0x6000000 -#define INSN_FIELD_IMM20 0xfffff000 -#define INSN_FIELD_JIMM20 0xfffff000 -#define INSN_FIELD_IMM12 0xfff00000 -#define INSN_FIELD_CSR 0xfff00000 -#define INSN_FIELD_IMM12HI 0xfe000000 -#define INSN_FIELD_BIMM12HI 0xfe000000 -#define INSN_FIELD_IMM12LO 0xf80 -#define INSN_FIELD_BIMM12LO 0xf80 -#define INSN_FIELD_ZIMM 0xf8000 -#define INSN_FIELD_SHAMTQ 0x7f00000 -#define INSN_FIELD_SHAMTW 0x1f00000 -#define INSN_FIELD_SHAMTW4 0xf00000 -#define INSN_FIELD_SHAMTD 0x3f00000 -#define INSN_FIELD_BS 0xc0000000 -#define INSN_FIELD_RNUM 0xf00000 -#define INSN_FIELD_RC 0x3e000000 -#define INSN_FIELD_IMM2 0x300000 -#define INSN_FIELD_IMM3 0x700000 -#define INSN_FIELD_IMM4 0xf00000 -#define INSN_FIELD_IMM5 0x1f00000 -#define INSN_FIELD_IMM6 0x3f00000 -#define INSN_FIELD_OPCODE 0x7f -#define INSN_FIELD_FUNCT7 0xfe000000 -#define INSN_FIELD_VD 0xf80 -#define INSN_FIELD_VS3 0xf80 -#define INSN_FIELD_VS1 0xf8000 -#define INSN_FIELD_VS2 0x1f00000 -#define INSN_FIELD_VM 0x2000000 -#define INSN_FIELD_WD 0x4000000 -#define INSN_FIELD_AMOOP 0xf8000000 -#define INSN_FIELD_NF 0xe0000000 -#define INSN_FIELD_SIMM5 0xf8000 -#define INSN_FIELD_ZIMM10 0x3ff00000 -#define INSN_FIELD_ZIMM11 0x7ff00000 -#define INSN_FIELD_C_NZUIMM10 0x1fe0 -#define INSN_FIELD_C_UIMM7LO 0x60 -#define INSN_FIELD_C_UIMM7HI 0x1c00 -#define INSN_FIELD_C_UIMM8LO 0x60 -#define INSN_FIELD_C_UIMM8HI 0x1c00 -#define INSN_FIELD_C_UIMM9LO 0x60 -#define INSN_FIELD_C_UIMM9HI 0x1c00 -#define INSN_FIELD_C_NZIMM6LO 0x7c -#define INSN_FIELD_C_NZIMM6HI 0x1000 -#define INSN_FIELD_C_IMM6LO 0x7c -#define INSN_FIELD_C_IMM6HI 0x1000 -#define INSN_FIELD_C_NZIMM10HI 0x1000 -#define INSN_FIELD_C_NZIMM10LO 0x7c -#define INSN_FIELD_C_NZIMM18HI 0x1000 -#define INSN_FIELD_C_NZIMM18LO 0x7c -#define INSN_FIELD_C_IMM12 0x1ffc -#define INSN_FIELD_C_BIMM9LO 0x7c -#define INSN_FIELD_C_BIMM9HI 0x1c00 -#define INSN_FIELD_C_NZUIMM5 0x7c -#define INSN_FIELD_C_NZUIMM6LO 0x7c -#define INSN_FIELD_C_NZUIMM6HI 0x1000 -#define INSN_FIELD_C_UIMM8SPLO 0x7c -#define INSN_FIELD_C_UIMM8SPHI 0x1000 -#define INSN_FIELD_C_UIMM8SP_S 0x1f80 -#define INSN_FIELD_C_UIMM10SPLO 0x7c -#define INSN_FIELD_C_UIMM10SPHI 0x1000 -#define INSN_FIELD_C_UIMM9SPLO 0x7c -#define INSN_FIELD_C_UIMM9SPHI 0x1000 -#define INSN_FIELD_C_UIMM10SP_S 0x1f80 -#define INSN_FIELD_C_UIMM9SP_S 0x1f80 -#define INSN_FIELD_C_UIMM2 0x60 -#define INSN_FIELD_C_UIMM1 0x20 -#define INSN_FIELD_C_RLIST 0xf0 -#define INSN_FIELD_C_SPIMM 0xc -#define INSN_FIELD_C_INDEX 0x3fc -#define INSN_FIELD_RS1_P 0x380 -#define INSN_FIELD_RS2_P 0x1c -#define INSN_FIELD_RD_P 0x1c -#define INSN_FIELD_RD_RS1_N0 0xf80 -#define INSN_FIELD_RD_RS1_P 0x380 -#define INSN_FIELD_RD_RS1 0xf80 -#define INSN_FIELD_RD_N2 0xf80 -#define INSN_FIELD_RD_N0 0xf80 -#define INSN_FIELD_RS1_N0 0xf80 -#define INSN_FIELD_C_RS2_N0 0x7c -#define INSN_FIELD_C_RS1_N0 0xf80 -#define INSN_FIELD_C_RS2 0x7c -#define INSN_FIELD_C_SREG1 0x380 -#define INSN_FIELD_C_SREG2 0x1c -#endif -#ifdef DECLARE_INSN -DECLARE_INSN(add, MATCH_ADD, MASK_ADD) -DECLARE_INSN(add16, MATCH_ADD16, MASK_ADD16) -DECLARE_INSN(add32, MATCH_ADD32, MASK_ADD32) -DECLARE_INSN(add64, MATCH_ADD64, MASK_ADD64) -DECLARE_INSN(add8, MATCH_ADD8, MASK_ADD8) -DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW) -DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) -DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) -DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) -DECLARE_INSN(aes32dsi, MATCH_AES32DSI, MASK_AES32DSI) -DECLARE_INSN(aes32dsmi, MATCH_AES32DSMI, MASK_AES32DSMI) -DECLARE_INSN(aes32esi, MATCH_AES32ESI, MASK_AES32ESI) -DECLARE_INSN(aes32esmi, MATCH_AES32ESMI, MASK_AES32ESMI) -DECLARE_INSN(aes64ds, MATCH_AES64DS, MASK_AES64DS) -DECLARE_INSN(aes64dsm, MATCH_AES64DSM, MASK_AES64DSM) -DECLARE_INSN(aes64es, MATCH_AES64ES, MASK_AES64ES) -DECLARE_INSN(aes64esm, MATCH_AES64ESM, MASK_AES64ESM) -DECLARE_INSN(aes64im, MATCH_AES64IM, MASK_AES64IM) -DECLARE_INSN(aes64ks1i, MATCH_AES64KS1I, MASK_AES64KS1I) -DECLARE_INSN(aes64ks2, MATCH_AES64KS2, MASK_AES64KS2) -DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) -DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) -DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) -DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) -DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) -DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) -DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) -DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) -DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) -DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) -DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) -DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) -DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) -DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) -DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) -DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) -DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) -DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) -DECLARE_INSN(and, MATCH_AND, MASK_AND) -DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) -DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN) -DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) -DECLARE_INSN(ave, MATCH_AVE, MASK_AVE) -DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR) -DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI) -DECLARE_INSN(bcompress, MATCH_BCOMPRESS, MASK_BCOMPRESS) -DECLARE_INSN(bcompressw, MATCH_BCOMPRESSW, MASK_BCOMPRESSW) -DECLARE_INSN(bdecompress, MATCH_BDECOMPRESS, MASK_BDECOMPRESS) -DECLARE_INSN(bdecompressw, MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW) -DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) -DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT) -DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI) -DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP) -DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW) -DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) -DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) -DECLARE_INSN(binv, MATCH_BINV, MASK_BINV) -DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI) -DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) -DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) -DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP) -DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR) -DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR) -DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) -DECLARE_INSN(bset, MATCH_BSET, MASK_BSET) -DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI) -DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) -DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) -DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) -DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) -DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) -DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) -DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) -DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) -DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) -DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) -DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) -DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) -DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) -DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) -DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) -DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) -DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) -DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) -DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) -DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) -DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) -DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) -DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) -DECLARE_INSN(c_lbu, MATCH_C_LBU, MASK_C_LBU) -DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) -DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) -DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH) -DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU) -DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) -DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) -DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) -DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) -DECLARE_INSN(c_mul, MATCH_C_MUL, MASK_C_MUL) -DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) -DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) -DECLARE_INSN(c_not, MATCH_C_NOT, MASK_C_NOT) -DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) -DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB) -DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) -DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) -DECLARE_INSN(c_sext_b, MATCH_C_SEXT_B, MASK_C_SEXT_B) -DECLARE_INSN(c_sext_h, MATCH_C_SEXT_H, MASK_C_SEXT_H) -DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH) -DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) -DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) -DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) -DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) -DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) -DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) -DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) -DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) -DECLARE_INSN(c_zext_b, MATCH_C_ZEXT_B, MASK_C_ZEXT_B) -DECLARE_INSN(c_zext_h, MATCH_C_ZEXT_H, MASK_C_ZEXT_H) -DECLARE_INSN(c_zext_w, MATCH_C_ZEXT_W, MASK_C_ZEXT_W) -DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN) -DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH) -DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL) -DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO) -DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL) -DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH) -DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR) -DECLARE_INSN(clrs16, MATCH_CLRS16, MASK_CLRS16) -DECLARE_INSN(clrs32, MATCH_CLRS32, MASK_CLRS32) -DECLARE_INSN(clrs8, MATCH_CLRS8, MASK_CLRS8) -DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ) -DECLARE_INSN(clz16, MATCH_CLZ16, MASK_CLZ16) -DECLARE_INSN(clz32, MATCH_CLZ32, MASK_CLZ32) -DECLARE_INSN(clz8, MATCH_CLZ8, MASK_CLZ8) -DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW) -DECLARE_INSN(cm_jalt, MATCH_CM_JALT, MASK_CM_JALT) -DECLARE_INSN(cm_mva01s, MATCH_CM_MVA01S, MASK_CM_MVA01S) -DECLARE_INSN(cm_mvsa01, MATCH_CM_MVSA01, MASK_CM_MVSA01) -DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP) -DECLARE_INSN(cm_popret, MATCH_CM_POPRET, MASK_CM_POPRET) -DECLARE_INSN(cm_popretz, MATCH_CM_POPRETZ, MASK_CM_POPRETZ) -DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH) -DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX) -DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV) -DECLARE_INSN(cmpeq16, MATCH_CMPEQ16, MASK_CMPEQ16) -DECLARE_INSN(cmpeq8, MATCH_CMPEQ8, MASK_CMPEQ8) -DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP) -DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW) -DECLARE_INSN(cras16, MATCH_CRAS16, MASK_CRAS16) -DECLARE_INSN(cras32, MATCH_CRAS32, MASK_CRAS32) -DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B) -DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D) -DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H) -DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W) -DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B) -DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D) -DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H) -DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W) -DECLARE_INSN(crsa16, MATCH_CRSA16, MASK_CRSA16) -DECLARE_INSN(crsa32, MATCH_CRSA32, MASK_CRSA32) -DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) -DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) -DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) -DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) -DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) -DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) -DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ) -DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW) -DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ) -DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ) -DECLARE_INSN(div, MATCH_DIV, MASK_DIV) -DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) -DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) -DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) -DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) -DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) -DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) -DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) -DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H) -DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) -DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) -DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) -DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H) -DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) -DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) -DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H) -DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) -DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) -DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) -DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) -DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) -DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) -DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D) -DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L) -DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU) -DECLARE_INSN(fcvt_h_q, MATCH_FCVT_H_Q, MASK_FCVT_H_Q) -DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S) -DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W) -DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU) -DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) -DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H) -DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) -DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) -DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) -DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H) -DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) -DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) -DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) -DECLARE_INSN(fcvt_q_h, MATCH_FCVT_Q_H, MASK_FCVT_Q_H) -DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) -DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) -DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) -DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) -DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) -DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) -DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H) -DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) -DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) -DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) -DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) -DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) -DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) -DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H) -DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) -DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) -DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) -DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H) -DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) -DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) -DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) -DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H) -DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) -DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) -DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) -DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) -DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) -DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H) -DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) -DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) -DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) -DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) -DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H) -DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) -DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) -DECLARE_INSN(flh, MATCH_FLH, MASK_FLH) -DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) -DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) -DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H) -DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) -DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) -DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) -DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) -DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H) -DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) -DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) -DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) -DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H) -DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) -DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) -DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) -DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H) -DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) -DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) -DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) -DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H) -DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) -DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) -DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) -DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H) -DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) -DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) -DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) -DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X) -DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) -DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) -DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H) -DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) -DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) -DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H) -DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) -DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) -DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) -DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H) -DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) -DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) -DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) -DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) -DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H) -DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) -DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) -DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) -DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H) -DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) -DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) -DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) -DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H) -DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) -DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) -DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH) -DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL) -DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW) -DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) -DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) -DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H) -DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) -DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) -DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR) -DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI) -DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW) -DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW) -DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) -DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H) -DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) -DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) -DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) -DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC) -DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI) -DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW) -DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW) -DECLARE_INSN(grev, MATCH_GREV, MASK_GREV) -DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI) -DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW) -DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW) -DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA) -DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA) -DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA) -DECLARE_INSN(hinval_vvma, MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA) -DECLARE_INSN(hlv_b, MATCH_HLV_B, MASK_HLV_B) -DECLARE_INSN(hlv_bu, MATCH_HLV_BU, MASK_HLV_BU) -DECLARE_INSN(hlv_d, MATCH_HLV_D, MASK_HLV_D) -DECLARE_INSN(hlv_h, MATCH_HLV_H, MASK_HLV_H) -DECLARE_INSN(hlv_hu, MATCH_HLV_HU, MASK_HLV_HU) -DECLARE_INSN(hlv_w, MATCH_HLV_W, MASK_HLV_W) -DECLARE_INSN(hlv_wu, MATCH_HLV_WU, MASK_HLV_WU) -DECLARE_INSN(hlvx_hu, MATCH_HLVX_HU, MASK_HLVX_HU) -DECLARE_INSN(hlvx_wu, MATCH_HLVX_WU, MASK_HLVX_WU) -DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B) -DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D) -DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H) -DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W) -DECLARE_INSN(insb, MATCH_INSB, MASK_INSB) -DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) -DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) -DECLARE_INSN(kabs16, MATCH_KABS16, MASK_KABS16) -DECLARE_INSN(kabs32, MATCH_KABS32, MASK_KABS32) -DECLARE_INSN(kabs8, MATCH_KABS8, MASK_KABS8) -DECLARE_INSN(kabsw, MATCH_KABSW, MASK_KABSW) -DECLARE_INSN(kadd16, MATCH_KADD16, MASK_KADD16) -DECLARE_INSN(kadd32, MATCH_KADD32, MASK_KADD32) -DECLARE_INSN(kadd64, MATCH_KADD64, MASK_KADD64) -DECLARE_INSN(kadd8, MATCH_KADD8, MASK_KADD8) -DECLARE_INSN(kaddh, MATCH_KADDH, MASK_KADDH) -DECLARE_INSN(kaddw, MATCH_KADDW, MASK_KADDW) -DECLARE_INSN(kcras16, MATCH_KCRAS16, MASK_KCRAS16) -DECLARE_INSN(kcras32, MATCH_KCRAS32, MASK_KCRAS32) -DECLARE_INSN(kcrsa16, MATCH_KCRSA16, MASK_KCRSA16) -DECLARE_INSN(kcrsa32, MATCH_KCRSA32, MASK_KCRSA32) -DECLARE_INSN(kdmabb, MATCH_KDMABB, MASK_KDMABB) -DECLARE_INSN(kdmabb16, MATCH_KDMABB16, MASK_KDMABB16) -DECLARE_INSN(kdmabt, MATCH_KDMABT, MASK_KDMABT) -DECLARE_INSN(kdmabt16, MATCH_KDMABT16, MASK_KDMABT16) -DECLARE_INSN(kdmatt, MATCH_KDMATT, MASK_KDMATT) -DECLARE_INSN(kdmatt16, MATCH_KDMATT16, MASK_KDMATT16) -DECLARE_INSN(kdmbb, MATCH_KDMBB, MASK_KDMBB) -DECLARE_INSN(kdmbb16, MATCH_KDMBB16, MASK_KDMBB16) -DECLARE_INSN(kdmbt, MATCH_KDMBT, MASK_KDMBT) -DECLARE_INSN(kdmbt16, MATCH_KDMBT16, MASK_KDMBT16) -DECLARE_INSN(kdmtt, MATCH_KDMTT, MASK_KDMTT) -DECLARE_INSN(kdmtt16, MATCH_KDMTT16, MASK_KDMTT16) -DECLARE_INSN(khm16, MATCH_KHM16, MASK_KHM16) -DECLARE_INSN(khm8, MATCH_KHM8, MASK_KHM8) -DECLARE_INSN(khmbb, MATCH_KHMBB, MASK_KHMBB) -DECLARE_INSN(khmbb16, MATCH_KHMBB16, MASK_KHMBB16) -DECLARE_INSN(khmbt, MATCH_KHMBT, MASK_KHMBT) -DECLARE_INSN(khmbt16, MATCH_KHMBT16, MASK_KHMBT16) -DECLARE_INSN(khmtt, MATCH_KHMTT, MASK_KHMTT) -DECLARE_INSN(khmtt16, MATCH_KHMTT16, MASK_KHMTT16) -DECLARE_INSN(khmx16, MATCH_KHMX16, MASK_KHMX16) -DECLARE_INSN(khmx8, MATCH_KHMX8, MASK_KHMX8) -DECLARE_INSN(kmabb, MATCH_KMABB, MASK_KMABB) -DECLARE_INSN(kmabb32, MATCH_KMABB32, MASK_KMABB32) -DECLARE_INSN(kmabt, MATCH_KMABT, MASK_KMABT) -DECLARE_INSN(kmabt32, MATCH_KMABT32, MASK_KMABT32) -DECLARE_INSN(kmada, MATCH_KMADA, MASK_KMADA) -DECLARE_INSN(kmadrs, MATCH_KMADRS, MASK_KMADRS) -DECLARE_INSN(kmadrs32, MATCH_KMADRS32, MASK_KMADRS32) -DECLARE_INSN(kmads, MATCH_KMADS, MASK_KMADS) -DECLARE_INSN(kmads32, MATCH_KMADS32, MASK_KMADS32) -DECLARE_INSN(kmar64, MATCH_KMAR64, MASK_KMAR64) -DECLARE_INSN(kmatt, MATCH_KMATT, MASK_KMATT) -DECLARE_INSN(kmatt32, MATCH_KMATT32, MASK_KMATT32) -DECLARE_INSN(kmaxda, MATCH_KMAXDA, MASK_KMAXDA) -DECLARE_INSN(kmaxda32, MATCH_KMAXDA32, MASK_KMAXDA32) -DECLARE_INSN(kmaxds, MATCH_KMAXDS, MASK_KMAXDS) -DECLARE_INSN(kmaxds32, MATCH_KMAXDS32, MASK_KMAXDS32) -DECLARE_INSN(kmda, MATCH_KMDA, MASK_KMDA) -DECLARE_INSN(kmda32, MATCH_KMDA32, MASK_KMDA32) -DECLARE_INSN(kmmac, MATCH_KMMAC, MASK_KMMAC) -DECLARE_INSN(kmmac_u, MATCH_KMMAC_U, MASK_KMMAC_U) -DECLARE_INSN(kmmawb, MATCH_KMMAWB, MASK_KMMAWB) -DECLARE_INSN(kmmawb2, MATCH_KMMAWB2, MASK_KMMAWB2) -DECLARE_INSN(kmmawb2_u, MATCH_KMMAWB2_U, MASK_KMMAWB2_U) -DECLARE_INSN(kmmawb_u, MATCH_KMMAWB_U, MASK_KMMAWB_U) -DECLARE_INSN(kmmawt, MATCH_KMMAWT, MASK_KMMAWT) -DECLARE_INSN(kmmawt2, MATCH_KMMAWT2, MASK_KMMAWT2) -DECLARE_INSN(kmmawt2_u, MATCH_KMMAWT2_U, MASK_KMMAWT2_U) -DECLARE_INSN(kmmawt_u, MATCH_KMMAWT_U, MASK_KMMAWT_U) -DECLARE_INSN(kmmsb, MATCH_KMMSB, MASK_KMMSB) -DECLARE_INSN(kmmsb_u, MATCH_KMMSB_U, MASK_KMMSB_U) -DECLARE_INSN(kmmwb2, MATCH_KMMWB2, MASK_KMMWB2) -DECLARE_INSN(kmmwb2_u, MATCH_KMMWB2_U, MASK_KMMWB2_U) -DECLARE_INSN(kmmwt2, MATCH_KMMWT2, MASK_KMMWT2) -DECLARE_INSN(kmmwt2_u, MATCH_KMMWT2_U, MASK_KMMWT2_U) -DECLARE_INSN(kmsda, MATCH_KMSDA, MASK_KMSDA) -DECLARE_INSN(kmsda32, MATCH_KMSDA32, MASK_KMSDA32) -DECLARE_INSN(kmsr64, MATCH_KMSR64, MASK_KMSR64) -DECLARE_INSN(kmsxda, MATCH_KMSXDA, MASK_KMSXDA) -DECLARE_INSN(kmsxda32, MATCH_KMSXDA32, MASK_KMSXDA32) -DECLARE_INSN(kmxda, MATCH_KMXDA, MASK_KMXDA) -DECLARE_INSN(kmxda32, MATCH_KMXDA32, MASK_KMXDA32) -DECLARE_INSN(ksll16, MATCH_KSLL16, MASK_KSLL16) -DECLARE_INSN(ksll32, MATCH_KSLL32, MASK_KSLL32) -DECLARE_INSN(ksll8, MATCH_KSLL8, MASK_KSLL8) -DECLARE_INSN(kslli16, MATCH_KSLLI16, MASK_KSLLI16) -DECLARE_INSN(kslli32, MATCH_KSLLI32, MASK_KSLLI32) -DECLARE_INSN(kslli8, MATCH_KSLLI8, MASK_KSLLI8) -DECLARE_INSN(kslliw, MATCH_KSLLIW, MASK_KSLLIW) -DECLARE_INSN(ksllw, MATCH_KSLLW, MASK_KSLLW) -DECLARE_INSN(kslra16, MATCH_KSLRA16, MASK_KSLRA16) -DECLARE_INSN(kslra16_u, MATCH_KSLRA16_U, MASK_KSLRA16_U) -DECLARE_INSN(kslra32, MATCH_KSLRA32, MASK_KSLRA32) -DECLARE_INSN(kslra32_u, MATCH_KSLRA32_U, MASK_KSLRA32_U) -DECLARE_INSN(kslra8, MATCH_KSLRA8, MASK_KSLRA8) -DECLARE_INSN(kslra8_u, MATCH_KSLRA8_U, MASK_KSLRA8_U) -DECLARE_INSN(kslraw, MATCH_KSLRAW, MASK_KSLRAW) -DECLARE_INSN(kslraw_u, MATCH_KSLRAW_U, MASK_KSLRAW_U) -DECLARE_INSN(kstas16, MATCH_KSTAS16, MASK_KSTAS16) -DECLARE_INSN(kstas32, MATCH_KSTAS32, MASK_KSTAS32) -DECLARE_INSN(kstsa16, MATCH_KSTSA16, MASK_KSTSA16) -DECLARE_INSN(kstsa32, MATCH_KSTSA32, MASK_KSTSA32) -DECLARE_INSN(ksub16, MATCH_KSUB16, MASK_KSUB16) -DECLARE_INSN(ksub32, MATCH_KSUB32, MASK_KSUB32) -DECLARE_INSN(ksub64, MATCH_KSUB64, MASK_KSUB64) -DECLARE_INSN(ksub8, MATCH_KSUB8, MASK_KSUB8) -DECLARE_INSN(ksubh, MATCH_KSUBH, MASK_KSUBH) -DECLARE_INSN(ksubw, MATCH_KSUBW, MASK_KSUBW) -DECLARE_INSN(kwmmul, MATCH_KWMMUL, MASK_KWMMUL) -DECLARE_INSN(kwmmul_u, MATCH_KWMMUL_U, MASK_KWMMUL_U) -DECLARE_INSN(lb, MATCH_LB, MASK_LB) -DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) -DECLARE_INSN(ld, MATCH_LD, MASK_LD) -DECLARE_INSN(lh, MATCH_LH, MASK_LH) -DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) -DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) -DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) -DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) -DECLARE_INSN(lw, MATCH_LW, MASK_LW) -DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) -DECLARE_INSN(maddr32, MATCH_MADDR32, MASK_MADDR32) -DECLARE_INSN(max, MATCH_MAX, MASK_MAX) -DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU) -DECLARE_INSN(min, MATCH_MIN, MASK_MIN) -DECLARE_INSN(minu, MATCH_MINU, MASK_MINU) -DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET) -DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) -DECLARE_INSN(msubr32, MATCH_MSUBR32, MASK_MSUBR32) -DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) -DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) -DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) -DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) -DECLARE_INSN(mulr64, MATCH_MULR64, MASK_MULR64) -DECLARE_INSN(mulsr64, MATCH_MULSR64, MASK_MULSR64) -DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) -DECLARE_INSN(or, MATCH_OR, MASK_OR) -DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) -DECLARE_INSN(orn, MATCH_ORN, MASK_ORN) -DECLARE_INSN(pack, MATCH_PACK, MASK_PACK) -DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH) -DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU) -DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW) -DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW) -DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE) -DECLARE_INSN(pbsad, MATCH_PBSAD, MASK_PBSAD) -DECLARE_INSN(pbsada, MATCH_PBSADA, MASK_PBSADA) -DECLARE_INSN(pkbb16, MATCH_PKBB16, MASK_PKBB16) -DECLARE_INSN(pkbt16, MATCH_PKBT16, MASK_PKBT16) -DECLARE_INSN(pkbt32, MATCH_PKBT32, MASK_PKBT32) -DECLARE_INSN(pktb16, MATCH_PKTB16, MASK_PKTB16) -DECLARE_INSN(pktb32, MATCH_PKTB32, MASK_PKTB32) -DECLARE_INSN(pktt16, MATCH_PKTT16, MASK_PKTT16) -DECLARE_INSN(prefetch_i, MATCH_PREFETCH_I, MASK_PREFETCH_I) -DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R) -DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W) -DECLARE_INSN(radd16, MATCH_RADD16, MASK_RADD16) -DECLARE_INSN(radd32, MATCH_RADD32, MASK_RADD32) -DECLARE_INSN(radd64, MATCH_RADD64, MASK_RADD64) -DECLARE_INSN(radd8, MATCH_RADD8, MASK_RADD8) -DECLARE_INSN(raddw, MATCH_RADDW, MASK_RADDW) -DECLARE_INSN(rcras16, MATCH_RCRAS16, MASK_RCRAS16) -DECLARE_INSN(rcras32, MATCH_RCRAS32, MASK_RCRAS32) -DECLARE_INSN(rcrsa16, MATCH_RCRSA16, MASK_RCRSA16) -DECLARE_INSN(rcrsa32, MATCH_RCRSA32, MASK_RCRSA32) -DECLARE_INSN(rem, MATCH_REM, MASK_REM) -DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) -DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) -DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) -DECLARE_INSN(rol, MATCH_ROL, MASK_ROL) -DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW) -DECLARE_INSN(ror, MATCH_ROR, MASK_ROR) -DECLARE_INSN(rori, MATCH_RORI, MASK_RORI) -DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW) -DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW) -DECLARE_INSN(rstas16, MATCH_RSTAS16, MASK_RSTAS16) -DECLARE_INSN(rstas32, MATCH_RSTAS32, MASK_RSTAS32) -DECLARE_INSN(rstsa16, MATCH_RSTSA16, MASK_RSTSA16) -DECLARE_INSN(rstsa32, MATCH_RSTSA32, MASK_RSTSA32) -DECLARE_INSN(rsub16, MATCH_RSUB16, MASK_RSUB16) -DECLARE_INSN(rsub32, MATCH_RSUB32, MASK_RSUB32) -DECLARE_INSN(rsub64, MATCH_RSUB64, MASK_RSUB64) -DECLARE_INSN(rsub8, MATCH_RSUB8, MASK_RSUB8) -DECLARE_INSN(rsubw, MATCH_RSUBW, MASK_RSUBW) -DECLARE_INSN(sb, MATCH_SB, MASK_SB) -DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) -DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) -DECLARE_INSN(sclip16, MATCH_SCLIP16, MASK_SCLIP16) -DECLARE_INSN(sclip32, MATCH_SCLIP32, MASK_SCLIP32) -DECLARE_INSN(sclip8, MATCH_SCLIP8, MASK_SCLIP8) -DECLARE_INSN(scmple16, MATCH_SCMPLE16, MASK_SCMPLE16) -DECLARE_INSN(scmple8, MATCH_SCMPLE8, MASK_SCMPLE8) -DECLARE_INSN(scmplt16, MATCH_SCMPLT16, MASK_SCMPLT16) -DECLARE_INSN(scmplt8, MATCH_SCMPLT8, MASK_SCMPLT8) -DECLARE_INSN(sd, MATCH_SD, MASK_SD) -DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B) -DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H) -DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR) -DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) -DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL) -DECLARE_INSN(sh, MATCH_SH, MASK_SH) -DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD) -DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW) -DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD) -DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW) -DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD) -DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW) -DECLARE_INSN(sha256sig0, MATCH_SHA256SIG0, MASK_SHA256SIG0) -DECLARE_INSN(sha256sig1, MATCH_SHA256SIG1, MASK_SHA256SIG1) -DECLARE_INSN(sha256sum0, MATCH_SHA256SUM0, MASK_SHA256SUM0) -DECLARE_INSN(sha256sum1, MATCH_SHA256SUM1, MASK_SHA256SUM1) -DECLARE_INSN(sha512sig0, MATCH_SHA512SIG0, MASK_SHA512SIG0) -DECLARE_INSN(sha512sig0h, MATCH_SHA512SIG0H, MASK_SHA512SIG0H) -DECLARE_INSN(sha512sig0l, MATCH_SHA512SIG0L, MASK_SHA512SIG0L) -DECLARE_INSN(sha512sig1, MATCH_SHA512SIG1, MASK_SHA512SIG1) -DECLARE_INSN(sha512sig1h, MATCH_SHA512SIG1H, MASK_SHA512SIG1H) -DECLARE_INSN(sha512sig1l, MATCH_SHA512SIG1L, MASK_SHA512SIG1L) -DECLARE_INSN(sha512sum0, MATCH_SHA512SUM0, MASK_SHA512SUM0) -DECLARE_INSN(sha512sum0r, MATCH_SHA512SUM0R, MASK_SHA512SUM0R) -DECLARE_INSN(sha512sum1, MATCH_SHA512SUM1, MASK_SHA512SUM1) -DECLARE_INSN(sha512sum1r, MATCH_SHA512SUM1R, MASK_SHA512SUM1R) -DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL) -DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI) -DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW) -DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA) -DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) -DECLARE_INSN(sll16, MATCH_SLL16, MASK_SLL16) -DECLARE_INSN(sll32, MATCH_SLL32, MASK_SLL32) -DECLARE_INSN(sll8, MATCH_SLL8, MASK_SLL8) -DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) -DECLARE_INSN(slli16, MATCH_SLLI16, MASK_SLLI16) -DECLARE_INSN(slli32, MATCH_SLLI32, MASK_SLLI32) -DECLARE_INSN(slli8, MATCH_SLLI8, MASK_SLLI8) -DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) -DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW) -DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) -DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) -DECLARE_INSN(slo, MATCH_SLO, MASK_SLO) -DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI) -DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW) -DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW) -DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) -DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) -DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) -DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) -DECLARE_INSN(sm3p0, MATCH_SM3P0, MASK_SM3P0) -DECLARE_INSN(sm3p1, MATCH_SM3P1, MASK_SM3P1) -DECLARE_INSN(sm4ed, MATCH_SM4ED, MASK_SM4ED) -DECLARE_INSN(sm4ks, MATCH_SM4KS, MASK_SM4KS) -DECLARE_INSN(smal, MATCH_SMAL, MASK_SMAL) -DECLARE_INSN(smalbb, MATCH_SMALBB, MASK_SMALBB) -DECLARE_INSN(smalbt, MATCH_SMALBT, MASK_SMALBT) -DECLARE_INSN(smalda, MATCH_SMALDA, MASK_SMALDA) -DECLARE_INSN(smaldrs, MATCH_SMALDRS, MASK_SMALDRS) -DECLARE_INSN(smalds, MATCH_SMALDS, MASK_SMALDS) -DECLARE_INSN(smaltt, MATCH_SMALTT, MASK_SMALTT) -DECLARE_INSN(smalxda, MATCH_SMALXDA, MASK_SMALXDA) -DECLARE_INSN(smalxds, MATCH_SMALXDS, MASK_SMALXDS) -DECLARE_INSN(smaqa, MATCH_SMAQA, MASK_SMAQA) -DECLARE_INSN(smaqa_su, MATCH_SMAQA_SU, MASK_SMAQA_SU) -DECLARE_INSN(smar64, MATCH_SMAR64, MASK_SMAR64) -DECLARE_INSN(smax16, MATCH_SMAX16, MASK_SMAX16) -DECLARE_INSN(smax32, MATCH_SMAX32, MASK_SMAX32) -DECLARE_INSN(smax8, MATCH_SMAX8, MASK_SMAX8) -DECLARE_INSN(smbb16, MATCH_SMBB16, MASK_SMBB16) -DECLARE_INSN(smbt16, MATCH_SMBT16, MASK_SMBT16) -DECLARE_INSN(smbt32, MATCH_SMBT32, MASK_SMBT32) -DECLARE_INSN(smdrs, MATCH_SMDRS, MASK_SMDRS) -DECLARE_INSN(smdrs32, MATCH_SMDRS32, MASK_SMDRS32) -DECLARE_INSN(smds, MATCH_SMDS, MASK_SMDS) -DECLARE_INSN(smds32, MATCH_SMDS32, MASK_SMDS32) -DECLARE_INSN(smin16, MATCH_SMIN16, MASK_SMIN16) -DECLARE_INSN(smin32, MATCH_SMIN32, MASK_SMIN32) -DECLARE_INSN(smin8, MATCH_SMIN8, MASK_SMIN8) -DECLARE_INSN(smmul, MATCH_SMMUL, MASK_SMMUL) -DECLARE_INSN(smmul_u, MATCH_SMMUL_U, MASK_SMMUL_U) -DECLARE_INSN(smmwb, MATCH_SMMWB, MASK_SMMWB) -DECLARE_INSN(smmwb_u, MATCH_SMMWB_U, MASK_SMMWB_U) -DECLARE_INSN(smmwt, MATCH_SMMWT, MASK_SMMWT) -DECLARE_INSN(smmwt_u, MATCH_SMMWT_U, MASK_SMMWT_U) -DECLARE_INSN(smslda, MATCH_SMSLDA, MASK_SMSLDA) -DECLARE_INSN(smslxda, MATCH_SMSLXDA, MASK_SMSLXDA) -DECLARE_INSN(smsr64, MATCH_SMSR64, MASK_SMSR64) -DECLARE_INSN(smtt16, MATCH_SMTT16, MASK_SMTT16) -DECLARE_INSN(smtt32, MATCH_SMTT32, MASK_SMTT32) -DECLARE_INSN(smul16, MATCH_SMUL16, MASK_SMUL16) -DECLARE_INSN(smul8, MATCH_SMUL8, MASK_SMUL8) -DECLARE_INSN(smulx16, MATCH_SMULX16, MASK_SMULX16) -DECLARE_INSN(smulx8, MATCH_SMULX8, MASK_SMULX8) -DECLARE_INSN(smxds, MATCH_SMXDS, MASK_SMXDS) -DECLARE_INSN(smxds32, MATCH_SMXDS32, MASK_SMXDS32) -DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) -DECLARE_INSN(sra16, MATCH_SRA16, MASK_SRA16) -DECLARE_INSN(sra16_u, MATCH_SRA16_U, MASK_SRA16_U) -DECLARE_INSN(sra32, MATCH_SRA32, MASK_SRA32) -DECLARE_INSN(sra32_u, MATCH_SRA32_U, MASK_SRA32_U) -DECLARE_INSN(sra8, MATCH_SRA8, MASK_SRA8) -DECLARE_INSN(sra8_u, MATCH_SRA8_U, MASK_SRA8_U) -DECLARE_INSN(sra_u, MATCH_SRA_U, MASK_SRA_U) -DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) -DECLARE_INSN(srai16, MATCH_SRAI16, MASK_SRAI16) -DECLARE_INSN(srai16_u, MATCH_SRAI16_U, MASK_SRAI16_U) -DECLARE_INSN(srai32, MATCH_SRAI32, MASK_SRAI32) -DECLARE_INSN(srai32_u, MATCH_SRAI32_U, MASK_SRAI32_U) -DECLARE_INSN(srai8, MATCH_SRAI8, MASK_SRAI8) -DECLARE_INSN(srai8_u, MATCH_SRAI8_U, MASK_SRAI8_U) -DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) -DECLARE_INSN(srai_u, MATCH_SRAI_U, MASK_SRAI_U) -DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) -DECLARE_INSN(sraiw_u, MATCH_SRAIW_U, MASK_SRAIW_U) -DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) -DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) -DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) -DECLARE_INSN(srl16, MATCH_SRL16, MASK_SRL16) -DECLARE_INSN(srl16_u, MATCH_SRL16_U, MASK_SRL16_U) -DECLARE_INSN(srl32, MATCH_SRL32, MASK_SRL32) -DECLARE_INSN(srl32_u, MATCH_SRL32_U, MASK_SRL32_U) -DECLARE_INSN(srl8, MATCH_SRL8, MASK_SRL8) -DECLARE_INSN(srl8_u, MATCH_SRL8_U, MASK_SRL8_U) -DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) -DECLARE_INSN(srli16, MATCH_SRLI16, MASK_SRLI16) -DECLARE_INSN(srli16_u, MATCH_SRLI16_U, MASK_SRLI16_U) -DECLARE_INSN(srli32, MATCH_SRLI32, MASK_SRLI32) -DECLARE_INSN(srli32_u, MATCH_SRLI32_U, MASK_SRLI32_U) -DECLARE_INSN(srli8, MATCH_SRLI8, MASK_SRLI8) -DECLARE_INSN(srli8_u, MATCH_SRLI8_U, MASK_SRLI8_U) -DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) -DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) -DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) -DECLARE_INSN(sro, MATCH_SRO, MASK_SRO) -DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI) -DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW) -DECLARE_INSN(srow, MATCH_SROW, MASK_SROW) -DECLARE_INSN(stas16, MATCH_STAS16, MASK_STAS16) -DECLARE_INSN(stas32, MATCH_STAS32, MASK_STAS32) -DECLARE_INSN(stsa16, MATCH_STSA16, MASK_STSA16) -DECLARE_INSN(stsa32, MATCH_STSA32, MASK_STSA32) -DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) -DECLARE_INSN(sub16, MATCH_SUB16, MASK_SUB16) -DECLARE_INSN(sub32, MATCH_SUB32, MASK_SUB32) -DECLARE_INSN(sub64, MATCH_SUB64, MASK_SUB64) -DECLARE_INSN(sub8, MATCH_SUB8, MASK_SUB8) -DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) -DECLARE_INSN(sunpkd810, MATCH_SUNPKD810, MASK_SUNPKD810) -DECLARE_INSN(sunpkd820, MATCH_SUNPKD820, MASK_SUNPKD820) -DECLARE_INSN(sunpkd830, MATCH_SUNPKD830, MASK_SUNPKD830) -DECLARE_INSN(sunpkd831, MATCH_SUNPKD831, MASK_SUNPKD831) -DECLARE_INSN(sunpkd832, MATCH_SUNPKD832, MASK_SUNPKD832) -DECLARE_INSN(sw, MATCH_SW, MASK_SW) -DECLARE_INSN(uclip16, MATCH_UCLIP16, MASK_UCLIP16) -DECLARE_INSN(uclip32, MATCH_UCLIP32, MASK_UCLIP32) -DECLARE_INSN(uclip8, MATCH_UCLIP8, MASK_UCLIP8) -DECLARE_INSN(ucmple16, MATCH_UCMPLE16, MASK_UCMPLE16) -DECLARE_INSN(ucmple8, MATCH_UCMPLE8, MASK_UCMPLE8) -DECLARE_INSN(ucmplt16, MATCH_UCMPLT16, MASK_UCMPLT16) -DECLARE_INSN(ucmplt8, MATCH_UCMPLT8, MASK_UCMPLT8) -DECLARE_INSN(ukadd16, MATCH_UKADD16, MASK_UKADD16) -DECLARE_INSN(ukadd32, MATCH_UKADD32, MASK_UKADD32) -DECLARE_INSN(ukadd64, MATCH_UKADD64, MASK_UKADD64) -DECLARE_INSN(ukadd8, MATCH_UKADD8, MASK_UKADD8) -DECLARE_INSN(ukaddh, MATCH_UKADDH, MASK_UKADDH) -DECLARE_INSN(ukaddw, MATCH_UKADDW, MASK_UKADDW) -DECLARE_INSN(ukcras16, MATCH_UKCRAS16, MASK_UKCRAS16) -DECLARE_INSN(ukcras32, MATCH_UKCRAS32, MASK_UKCRAS32) -DECLARE_INSN(ukcrsa16, MATCH_UKCRSA16, MASK_UKCRSA16) -DECLARE_INSN(ukcrsa32, MATCH_UKCRSA32, MASK_UKCRSA32) -DECLARE_INSN(ukmar64, MATCH_UKMAR64, MASK_UKMAR64) -DECLARE_INSN(ukmsr64, MATCH_UKMSR64, MASK_UKMSR64) -DECLARE_INSN(ukstas16, MATCH_UKSTAS16, MASK_UKSTAS16) -DECLARE_INSN(ukstas32, MATCH_UKSTAS32, MASK_UKSTAS32) -DECLARE_INSN(ukstsa16, MATCH_UKSTSA16, MASK_UKSTSA16) -DECLARE_INSN(ukstsa32, MATCH_UKSTSA32, MASK_UKSTSA32) -DECLARE_INSN(uksub16, MATCH_UKSUB16, MASK_UKSUB16) -DECLARE_INSN(uksub32, MATCH_UKSUB32, MASK_UKSUB32) -DECLARE_INSN(uksub64, MATCH_UKSUB64, MASK_UKSUB64) -DECLARE_INSN(uksub8, MATCH_UKSUB8, MASK_UKSUB8) -DECLARE_INSN(uksubh, MATCH_UKSUBH, MASK_UKSUBH) -DECLARE_INSN(uksubw, MATCH_UKSUBW, MASK_UKSUBW) -DECLARE_INSN(umaqa, MATCH_UMAQA, MASK_UMAQA) -DECLARE_INSN(umar64, MATCH_UMAR64, MASK_UMAR64) -DECLARE_INSN(umax16, MATCH_UMAX16, MASK_UMAX16) -DECLARE_INSN(umax32, MATCH_UMAX32, MASK_UMAX32) -DECLARE_INSN(umax8, MATCH_UMAX8, MASK_UMAX8) -DECLARE_INSN(umin16, MATCH_UMIN16, MASK_UMIN16) -DECLARE_INSN(umin32, MATCH_UMIN32, MASK_UMIN32) -DECLARE_INSN(umin8, MATCH_UMIN8, MASK_UMIN8) -DECLARE_INSN(umsr64, MATCH_UMSR64, MASK_UMSR64) -DECLARE_INSN(umul16, MATCH_UMUL16, MASK_UMUL16) -DECLARE_INSN(umul8, MATCH_UMUL8, MASK_UMUL8) -DECLARE_INSN(umulx16, MATCH_UMULX16, MASK_UMULX16) -DECLARE_INSN(umulx8, MATCH_UMULX8, MASK_UMULX8) -DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL) -DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI) -DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW) -DECLARE_INSN(uradd16, MATCH_URADD16, MASK_URADD16) -DECLARE_INSN(uradd32, MATCH_URADD32, MASK_URADD32) -DECLARE_INSN(uradd64, MATCH_URADD64, MASK_URADD64) -DECLARE_INSN(uradd8, MATCH_URADD8, MASK_URADD8) -DECLARE_INSN(uraddw, MATCH_URADDW, MASK_URADDW) -DECLARE_INSN(urcras16, MATCH_URCRAS16, MASK_URCRAS16) -DECLARE_INSN(urcras32, MATCH_URCRAS32, MASK_URCRAS32) -DECLARE_INSN(urcrsa16, MATCH_URCRSA16, MASK_URCRSA16) -DECLARE_INSN(urcrsa32, MATCH_URCRSA32, MASK_URCRSA32) -DECLARE_INSN(urstas16, MATCH_URSTAS16, MASK_URSTAS16) -DECLARE_INSN(urstas32, MATCH_URSTAS32, MASK_URSTAS32) -DECLARE_INSN(urstsa16, MATCH_URSTSA16, MASK_URSTSA16) -DECLARE_INSN(urstsa32, MATCH_URSTSA32, MASK_URSTSA32) -DECLARE_INSN(ursub16, MATCH_URSUB16, MASK_URSUB16) -DECLARE_INSN(ursub32, MATCH_URSUB32, MASK_URSUB32) -DECLARE_INSN(ursub64, MATCH_URSUB64, MASK_URSUB64) -DECLARE_INSN(ursub8, MATCH_URSUB8, MASK_URSUB8) -DECLARE_INSN(ursubw, MATCH_URSUBW, MASK_URSUBW) -DECLARE_INSN(vaadd_vv, MATCH_VAADD_VV, MASK_VAADD_VV) -DECLARE_INSN(vaadd_vx, MATCH_VAADD_VX, MASK_VAADD_VX) -DECLARE_INSN(vaaddu_vv, MATCH_VAADDU_VV, MASK_VAADDU_VV) -DECLARE_INSN(vaaddu_vx, MATCH_VAADDU_VX, MASK_VAADDU_VX) -DECLARE_INSN(vadc_vim, MATCH_VADC_VIM, MASK_VADC_VIM) -DECLARE_INSN(vadc_vvm, MATCH_VADC_VVM, MASK_VADC_VVM) -DECLARE_INSN(vadc_vxm, MATCH_VADC_VXM, MASK_VADC_VXM) -DECLARE_INSN(vadd_vi, MATCH_VADD_VI, MASK_VADD_VI) -DECLARE_INSN(vadd_vv, MATCH_VADD_VV, MASK_VADD_VV) -DECLARE_INSN(vadd_vx, MATCH_VADD_VX, MASK_VADD_VX) -DECLARE_INSN(vamoaddei16_v, MATCH_VAMOADDEI16_V, MASK_VAMOADDEI16_V) -DECLARE_INSN(vamoaddei32_v, MATCH_VAMOADDEI32_V, MASK_VAMOADDEI32_V) -DECLARE_INSN(vamoaddei64_v, MATCH_VAMOADDEI64_V, MASK_VAMOADDEI64_V) -DECLARE_INSN(vamoaddei8_v, MATCH_VAMOADDEI8_V, MASK_VAMOADDEI8_V) -DECLARE_INSN(vamoandei16_v, MATCH_VAMOANDEI16_V, MASK_VAMOANDEI16_V) -DECLARE_INSN(vamoandei32_v, MATCH_VAMOANDEI32_V, MASK_VAMOANDEI32_V) -DECLARE_INSN(vamoandei64_v, MATCH_VAMOANDEI64_V, MASK_VAMOANDEI64_V) -DECLARE_INSN(vamoandei8_v, MATCH_VAMOANDEI8_V, MASK_VAMOANDEI8_V) -DECLARE_INSN(vamomaxei16_v, MATCH_VAMOMAXEI16_V, MASK_VAMOMAXEI16_V) -DECLARE_INSN(vamomaxei32_v, MATCH_VAMOMAXEI32_V, MASK_VAMOMAXEI32_V) -DECLARE_INSN(vamomaxei64_v, MATCH_VAMOMAXEI64_V, MASK_VAMOMAXEI64_V) -DECLARE_INSN(vamomaxei8_v, MATCH_VAMOMAXEI8_V, MASK_VAMOMAXEI8_V) -DECLARE_INSN(vamomaxuei16_v, MATCH_VAMOMAXUEI16_V, MASK_VAMOMAXUEI16_V) -DECLARE_INSN(vamomaxuei32_v, MATCH_VAMOMAXUEI32_V, MASK_VAMOMAXUEI32_V) -DECLARE_INSN(vamomaxuei64_v, MATCH_VAMOMAXUEI64_V, MASK_VAMOMAXUEI64_V) -DECLARE_INSN(vamomaxuei8_v, MATCH_VAMOMAXUEI8_V, MASK_VAMOMAXUEI8_V) -DECLARE_INSN(vamominei16_v, MATCH_VAMOMINEI16_V, MASK_VAMOMINEI16_V) -DECLARE_INSN(vamominei32_v, MATCH_VAMOMINEI32_V, MASK_VAMOMINEI32_V) -DECLARE_INSN(vamominei64_v, MATCH_VAMOMINEI64_V, MASK_VAMOMINEI64_V) -DECLARE_INSN(vamominei8_v, MATCH_VAMOMINEI8_V, MASK_VAMOMINEI8_V) -DECLARE_INSN(vamominuei16_v, MATCH_VAMOMINUEI16_V, MASK_VAMOMINUEI16_V) -DECLARE_INSN(vamominuei32_v, MATCH_VAMOMINUEI32_V, MASK_VAMOMINUEI32_V) -DECLARE_INSN(vamominuei64_v, MATCH_VAMOMINUEI64_V, MASK_VAMOMINUEI64_V) -DECLARE_INSN(vamominuei8_v, MATCH_VAMOMINUEI8_V, MASK_VAMOMINUEI8_V) -DECLARE_INSN(vamoorei16_v, MATCH_VAMOOREI16_V, MASK_VAMOOREI16_V) -DECLARE_INSN(vamoorei32_v, MATCH_VAMOOREI32_V, MASK_VAMOOREI32_V) -DECLARE_INSN(vamoorei64_v, MATCH_VAMOOREI64_V, MASK_VAMOOREI64_V) -DECLARE_INSN(vamoorei8_v, MATCH_VAMOOREI8_V, MASK_VAMOOREI8_V) -DECLARE_INSN(vamoswapei16_v, MATCH_VAMOSWAPEI16_V, MASK_VAMOSWAPEI16_V) -DECLARE_INSN(vamoswapei32_v, MATCH_VAMOSWAPEI32_V, MASK_VAMOSWAPEI32_V) -DECLARE_INSN(vamoswapei64_v, MATCH_VAMOSWAPEI64_V, MASK_VAMOSWAPEI64_V) -DECLARE_INSN(vamoswapei8_v, MATCH_VAMOSWAPEI8_V, MASK_VAMOSWAPEI8_V) -DECLARE_INSN(vamoxorei16_v, MATCH_VAMOXOREI16_V, MASK_VAMOXOREI16_V) -DECLARE_INSN(vamoxorei32_v, MATCH_VAMOXOREI32_V, MASK_VAMOXOREI32_V) -DECLARE_INSN(vamoxorei64_v, MATCH_VAMOXOREI64_V, MASK_VAMOXOREI64_V) -DECLARE_INSN(vamoxorei8_v, MATCH_VAMOXOREI8_V, MASK_VAMOXOREI8_V) -DECLARE_INSN(vand_vi, MATCH_VAND_VI, MASK_VAND_VI) -DECLARE_INSN(vand_vv, MATCH_VAND_VV, MASK_VAND_VV) -DECLARE_INSN(vand_vx, MATCH_VAND_VX, MASK_VAND_VX) -DECLARE_INSN(vasub_vv, MATCH_VASUB_VV, MASK_VASUB_VV) -DECLARE_INSN(vasub_vx, MATCH_VASUB_VX, MASK_VASUB_VX) -DECLARE_INSN(vasubu_vv, MATCH_VASUBU_VV, MASK_VASUBU_VV) -DECLARE_INSN(vasubu_vx, MATCH_VASUBU_VX, MASK_VASUBU_VX) -DECLARE_INSN(vcompress_vm, MATCH_VCOMPRESS_VM, MASK_VCOMPRESS_VM) -DECLARE_INSN(vcpop_m, MATCH_VCPOP_M, MASK_VCPOP_M) -DECLARE_INSN(vdiv_vv, MATCH_VDIV_VV, MASK_VDIV_VV) -DECLARE_INSN(vdiv_vx, MATCH_VDIV_VX, MASK_VDIV_VX) -DECLARE_INSN(vdivu_vv, MATCH_VDIVU_VV, MASK_VDIVU_VV) -DECLARE_INSN(vdivu_vx, MATCH_VDIVU_VX, MASK_VDIVU_VX) -DECLARE_INSN(vfadd_vf, MATCH_VFADD_VF, MASK_VFADD_VF) -DECLARE_INSN(vfadd_vv, MATCH_VFADD_VV, MASK_VFADD_VV) -DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V) -DECLARE_INSN(vfcvt_f_x_v, MATCH_VFCVT_F_X_V, MASK_VFCVT_F_X_V) -DECLARE_INSN(vfcvt_f_xu_v, MATCH_VFCVT_F_XU_V, MASK_VFCVT_F_XU_V) -DECLARE_INSN(vfcvt_rtz_x_f_v, MATCH_VFCVT_RTZ_X_F_V, MASK_VFCVT_RTZ_X_F_V) -DECLARE_INSN(vfcvt_rtz_xu_f_v, MATCH_VFCVT_RTZ_XU_F_V, MASK_VFCVT_RTZ_XU_F_V) -DECLARE_INSN(vfcvt_x_f_v, MATCH_VFCVT_X_F_V, MASK_VFCVT_X_F_V) -DECLARE_INSN(vfcvt_xu_f_v, MATCH_VFCVT_XU_F_V, MASK_VFCVT_XU_F_V) -DECLARE_INSN(vfdiv_vf, MATCH_VFDIV_VF, MASK_VFDIV_VF) -DECLARE_INSN(vfdiv_vv, MATCH_VFDIV_VV, MASK_VFDIV_VV) -DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M) -DECLARE_INSN(vfmacc_vf, MATCH_VFMACC_VF, MASK_VFMACC_VF) -DECLARE_INSN(vfmacc_vv, MATCH_VFMACC_VV, MASK_VFMACC_VV) -DECLARE_INSN(vfmadd_vf, MATCH_VFMADD_VF, MASK_VFMADD_VF) -DECLARE_INSN(vfmadd_vv, MATCH_VFMADD_VV, MASK_VFMADD_VV) -DECLARE_INSN(vfmax_vf, MATCH_VFMAX_VF, MASK_VFMAX_VF) -DECLARE_INSN(vfmax_vv, MATCH_VFMAX_VV, MASK_VFMAX_VV) -DECLARE_INSN(vfmerge_vfm, MATCH_VFMERGE_VFM, MASK_VFMERGE_VFM) -DECLARE_INSN(vfmin_vf, MATCH_VFMIN_VF, MASK_VFMIN_VF) -DECLARE_INSN(vfmin_vv, MATCH_VFMIN_VV, MASK_VFMIN_VV) -DECLARE_INSN(vfmsac_vf, MATCH_VFMSAC_VF, MASK_VFMSAC_VF) -DECLARE_INSN(vfmsac_vv, MATCH_VFMSAC_VV, MASK_VFMSAC_VV) -DECLARE_INSN(vfmsub_vf, MATCH_VFMSUB_VF, MASK_VFMSUB_VF) -DECLARE_INSN(vfmsub_vv, MATCH_VFMSUB_VV, MASK_VFMSUB_VV) -DECLARE_INSN(vfmul_vf, MATCH_VFMUL_VF, MASK_VFMUL_VF) -DECLARE_INSN(vfmul_vv, MATCH_VFMUL_VV, MASK_VFMUL_VV) -DECLARE_INSN(vfmv_f_s, MATCH_VFMV_F_S, MASK_VFMV_F_S) -DECLARE_INSN(vfmv_s_f, MATCH_VFMV_S_F, MASK_VFMV_S_F) -DECLARE_INSN(vfmv_v_f, MATCH_VFMV_V_F, MASK_VFMV_V_F) -DECLARE_INSN(vfncvt_f_f_w, MATCH_VFNCVT_F_F_W, MASK_VFNCVT_F_F_W) -DECLARE_INSN(vfncvt_f_x_w, MATCH_VFNCVT_F_X_W, MASK_VFNCVT_F_X_W) -DECLARE_INSN(vfncvt_f_xu_w, MATCH_VFNCVT_F_XU_W, MASK_VFNCVT_F_XU_W) -DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W) -DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W) -DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W) -DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W) -DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W) -DECLARE_INSN(vfnmacc_vf, MATCH_VFNMACC_VF, MASK_VFNMACC_VF) -DECLARE_INSN(vfnmacc_vv, MATCH_VFNMACC_VV, MASK_VFNMACC_VV) -DECLARE_INSN(vfnmadd_vf, MATCH_VFNMADD_VF, MASK_VFNMADD_VF) -DECLARE_INSN(vfnmadd_vv, MATCH_VFNMADD_VV, MASK_VFNMADD_VV) -DECLARE_INSN(vfnmsac_vf, MATCH_VFNMSAC_VF, MASK_VFNMSAC_VF) -DECLARE_INSN(vfnmsac_vv, MATCH_VFNMSAC_VV, MASK_VFNMSAC_VV) -DECLARE_INSN(vfnmsub_vf, MATCH_VFNMSUB_VF, MASK_VFNMSUB_VF) -DECLARE_INSN(vfnmsub_vv, MATCH_VFNMSUB_VV, MASK_VFNMSUB_VV) -DECLARE_INSN(vfrdiv_vf, MATCH_VFRDIV_VF, MASK_VFRDIV_VF) -DECLARE_INSN(vfrec7_v, MATCH_VFREC7_V, MASK_VFREC7_V) -DECLARE_INSN(vfredmax_vs, MATCH_VFREDMAX_VS, MASK_VFREDMAX_VS) -DECLARE_INSN(vfredmin_vs, MATCH_VFREDMIN_VS, MASK_VFREDMIN_VS) -DECLARE_INSN(vfredosum_vs, MATCH_VFREDOSUM_VS, MASK_VFREDOSUM_VS) -DECLARE_INSN(vfredusum_vs, MATCH_VFREDUSUM_VS, MASK_VFREDUSUM_VS) -DECLARE_INSN(vfrsqrt7_v, MATCH_VFRSQRT7_V, MASK_VFRSQRT7_V) -DECLARE_INSN(vfrsub_vf, MATCH_VFRSUB_VF, MASK_VFRSUB_VF) -DECLARE_INSN(vfsgnj_vf, MATCH_VFSGNJ_VF, MASK_VFSGNJ_VF) -DECLARE_INSN(vfsgnj_vv, MATCH_VFSGNJ_VV, MASK_VFSGNJ_VV) -DECLARE_INSN(vfsgnjn_vf, MATCH_VFSGNJN_VF, MASK_VFSGNJN_VF) -DECLARE_INSN(vfsgnjn_vv, MATCH_VFSGNJN_VV, MASK_VFSGNJN_VV) -DECLARE_INSN(vfsgnjx_vf, MATCH_VFSGNJX_VF, MASK_VFSGNJX_VF) -DECLARE_INSN(vfsgnjx_vv, MATCH_VFSGNJX_VV, MASK_VFSGNJX_VV) -DECLARE_INSN(vfslide1down_vf, MATCH_VFSLIDE1DOWN_VF, MASK_VFSLIDE1DOWN_VF) -DECLARE_INSN(vfslide1up_vf, MATCH_VFSLIDE1UP_VF, MASK_VFSLIDE1UP_VF) -DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V) -DECLARE_INSN(vfsub_vf, MATCH_VFSUB_VF, MASK_VFSUB_VF) -DECLARE_INSN(vfsub_vv, MATCH_VFSUB_VV, MASK_VFSUB_VV) -DECLARE_INSN(vfwadd_vf, MATCH_VFWADD_VF, MASK_VFWADD_VF) -DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV) -DECLARE_INSN(vfwadd_wf, MATCH_VFWADD_WF, MASK_VFWADD_WF) -DECLARE_INSN(vfwadd_wv, MATCH_VFWADD_WV, MASK_VFWADD_WV) -DECLARE_INSN(vfwcvt_f_f_v, MATCH_VFWCVT_F_F_V, MASK_VFWCVT_F_F_V) -DECLARE_INSN(vfwcvt_f_x_v, MATCH_VFWCVT_F_X_V, MASK_VFWCVT_F_X_V) -DECLARE_INSN(vfwcvt_f_xu_v, MATCH_VFWCVT_F_XU_V, MASK_VFWCVT_F_XU_V) -DECLARE_INSN(vfwcvt_rtz_x_f_v, MATCH_VFWCVT_RTZ_X_F_V, MASK_VFWCVT_RTZ_X_F_V) -DECLARE_INSN(vfwcvt_rtz_xu_f_v, MATCH_VFWCVT_RTZ_XU_F_V, MASK_VFWCVT_RTZ_XU_F_V) -DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V) -DECLARE_INSN(vfwcvt_xu_f_v, MATCH_VFWCVT_XU_F_V, MASK_VFWCVT_XU_F_V) -DECLARE_INSN(vfwmacc_vf, MATCH_VFWMACC_VF, MASK_VFWMACC_VF) -DECLARE_INSN(vfwmacc_vv, MATCH_VFWMACC_VV, MASK_VFWMACC_VV) -DECLARE_INSN(vfwmsac_vf, MATCH_VFWMSAC_VF, MASK_VFWMSAC_VF) -DECLARE_INSN(vfwmsac_vv, MATCH_VFWMSAC_VV, MASK_VFWMSAC_VV) -DECLARE_INSN(vfwmul_vf, MATCH_VFWMUL_VF, MASK_VFWMUL_VF) -DECLARE_INSN(vfwmul_vv, MATCH_VFWMUL_VV, MASK_VFWMUL_VV) -DECLARE_INSN(vfwnmacc_vf, MATCH_VFWNMACC_VF, MASK_VFWNMACC_VF) -DECLARE_INSN(vfwnmacc_vv, MATCH_VFWNMACC_VV, MASK_VFWNMACC_VV) -DECLARE_INSN(vfwnmsac_vf, MATCH_VFWNMSAC_VF, MASK_VFWNMSAC_VF) -DECLARE_INSN(vfwnmsac_vv, MATCH_VFWNMSAC_VV, MASK_VFWNMSAC_VV) -DECLARE_INSN(vfwredosum_vs, MATCH_VFWREDOSUM_VS, MASK_VFWREDOSUM_VS) -DECLARE_INSN(vfwredusum_vs, MATCH_VFWREDUSUM_VS, MASK_VFWREDUSUM_VS) -DECLARE_INSN(vfwsub_vf, MATCH_VFWSUB_VF, MASK_VFWSUB_VF) -DECLARE_INSN(vfwsub_vv, MATCH_VFWSUB_VV, MASK_VFWSUB_VV) -DECLARE_INSN(vfwsub_wf, MATCH_VFWSUB_WF, MASK_VFWSUB_WF) -DECLARE_INSN(vfwsub_wv, MATCH_VFWSUB_WV, MASK_VFWSUB_WV) -DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V) -DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M) -DECLARE_INSN(vl1re16_v, MATCH_VL1RE16_V, MASK_VL1RE16_V) -DECLARE_INSN(vl1re32_v, MATCH_VL1RE32_V, MASK_VL1RE32_V) -DECLARE_INSN(vl1re64_v, MATCH_VL1RE64_V, MASK_VL1RE64_V) -DECLARE_INSN(vl1re8_v, MATCH_VL1RE8_V, MASK_VL1RE8_V) -DECLARE_INSN(vl2re16_v, MATCH_VL2RE16_V, MASK_VL2RE16_V) -DECLARE_INSN(vl2re32_v, MATCH_VL2RE32_V, MASK_VL2RE32_V) -DECLARE_INSN(vl2re64_v, MATCH_VL2RE64_V, MASK_VL2RE64_V) -DECLARE_INSN(vl2re8_v, MATCH_VL2RE8_V, MASK_VL2RE8_V) -DECLARE_INSN(vl4re16_v, MATCH_VL4RE16_V, MASK_VL4RE16_V) -DECLARE_INSN(vl4re32_v, MATCH_VL4RE32_V, MASK_VL4RE32_V) -DECLARE_INSN(vl4re64_v, MATCH_VL4RE64_V, MASK_VL4RE64_V) -DECLARE_INSN(vl4re8_v, MATCH_VL4RE8_V, MASK_VL4RE8_V) -DECLARE_INSN(vl8re16_v, MATCH_VL8RE16_V, MASK_VL8RE16_V) -DECLARE_INSN(vl8re32_v, MATCH_VL8RE32_V, MASK_VL8RE32_V) -DECLARE_INSN(vl8re64_v, MATCH_VL8RE64_V, MASK_VL8RE64_V) -DECLARE_INSN(vl8re8_v, MATCH_VL8RE8_V, MASK_VL8RE8_V) -DECLARE_INSN(vle1024_v, MATCH_VLE1024_V, MASK_VLE1024_V) -DECLARE_INSN(vle1024ff_v, MATCH_VLE1024FF_V, MASK_VLE1024FF_V) -DECLARE_INSN(vle128_v, MATCH_VLE128_V, MASK_VLE128_V) -DECLARE_INSN(vle128ff_v, MATCH_VLE128FF_V, MASK_VLE128FF_V) -DECLARE_INSN(vle16_v, MATCH_VLE16_V, MASK_VLE16_V) -DECLARE_INSN(vle16ff_v, MATCH_VLE16FF_V, MASK_VLE16FF_V) -DECLARE_INSN(vle256_v, MATCH_VLE256_V, MASK_VLE256_V) -DECLARE_INSN(vle256ff_v, MATCH_VLE256FF_V, MASK_VLE256FF_V) -DECLARE_INSN(vle32_v, MATCH_VLE32_V, MASK_VLE32_V) -DECLARE_INSN(vle32ff_v, MATCH_VLE32FF_V, MASK_VLE32FF_V) -DECLARE_INSN(vle512_v, MATCH_VLE512_V, MASK_VLE512_V) -DECLARE_INSN(vle512ff_v, MATCH_VLE512FF_V, MASK_VLE512FF_V) -DECLARE_INSN(vle64_v, MATCH_VLE64_V, MASK_VLE64_V) -DECLARE_INSN(vle64ff_v, MATCH_VLE64FF_V, MASK_VLE64FF_V) -DECLARE_INSN(vle8_v, MATCH_VLE8_V, MASK_VLE8_V) -DECLARE_INSN(vle8ff_v, MATCH_VLE8FF_V, MASK_VLE8FF_V) -DECLARE_INSN(vlm_v, MATCH_VLM_V, MASK_VLM_V) -DECLARE_INSN(vloxei1024_v, MATCH_VLOXEI1024_V, MASK_VLOXEI1024_V) -DECLARE_INSN(vloxei128_v, MATCH_VLOXEI128_V, MASK_VLOXEI128_V) -DECLARE_INSN(vloxei16_v, MATCH_VLOXEI16_V, MASK_VLOXEI16_V) -DECLARE_INSN(vloxei256_v, MATCH_VLOXEI256_V, MASK_VLOXEI256_V) -DECLARE_INSN(vloxei32_v, MATCH_VLOXEI32_V, MASK_VLOXEI32_V) -DECLARE_INSN(vloxei512_v, MATCH_VLOXEI512_V, MASK_VLOXEI512_V) -DECLARE_INSN(vloxei64_v, MATCH_VLOXEI64_V, MASK_VLOXEI64_V) -DECLARE_INSN(vloxei8_v, MATCH_VLOXEI8_V, MASK_VLOXEI8_V) -DECLARE_INSN(vlse1024_v, MATCH_VLSE1024_V, MASK_VLSE1024_V) -DECLARE_INSN(vlse128_v, MATCH_VLSE128_V, MASK_VLSE128_V) -DECLARE_INSN(vlse16_v, MATCH_VLSE16_V, MASK_VLSE16_V) -DECLARE_INSN(vlse256_v, MATCH_VLSE256_V, MASK_VLSE256_V) -DECLARE_INSN(vlse32_v, MATCH_VLSE32_V, MASK_VLSE32_V) -DECLARE_INSN(vlse512_v, MATCH_VLSE512_V, MASK_VLSE512_V) -DECLARE_INSN(vlse64_v, MATCH_VLSE64_V, MASK_VLSE64_V) -DECLARE_INSN(vlse8_v, MATCH_VLSE8_V, MASK_VLSE8_V) -DECLARE_INSN(vluxei1024_v, MATCH_VLUXEI1024_V, MASK_VLUXEI1024_V) -DECLARE_INSN(vluxei128_v, MATCH_VLUXEI128_V, MASK_VLUXEI128_V) -DECLARE_INSN(vluxei16_v, MATCH_VLUXEI16_V, MASK_VLUXEI16_V) -DECLARE_INSN(vluxei256_v, MATCH_VLUXEI256_V, MASK_VLUXEI256_V) -DECLARE_INSN(vluxei32_v, MATCH_VLUXEI32_V, MASK_VLUXEI32_V) -DECLARE_INSN(vluxei512_v, MATCH_VLUXEI512_V, MASK_VLUXEI512_V) -DECLARE_INSN(vluxei64_v, MATCH_VLUXEI64_V, MASK_VLUXEI64_V) -DECLARE_INSN(vluxei8_v, MATCH_VLUXEI8_V, MASK_VLUXEI8_V) -DECLARE_INSN(vmacc_vv, MATCH_VMACC_VV, MASK_VMACC_VV) -DECLARE_INSN(vmacc_vx, MATCH_VMACC_VX, MASK_VMACC_VX) -DECLARE_INSN(vmadc_vi, MATCH_VMADC_VI, MASK_VMADC_VI) -DECLARE_INSN(vmadc_vim, MATCH_VMADC_VIM, MASK_VMADC_VIM) -DECLARE_INSN(vmadc_vv, MATCH_VMADC_VV, MASK_VMADC_VV) -DECLARE_INSN(vmadc_vvm, MATCH_VMADC_VVM, MASK_VMADC_VVM) -DECLARE_INSN(vmadc_vx, MATCH_VMADC_VX, MASK_VMADC_VX) -DECLARE_INSN(vmadc_vxm, MATCH_VMADC_VXM, MASK_VMADC_VXM) -DECLARE_INSN(vmadd_vv, MATCH_VMADD_VV, MASK_VMADD_VV) -DECLARE_INSN(vmadd_vx, MATCH_VMADD_VX, MASK_VMADD_VX) -DECLARE_INSN(vmand_mm, MATCH_VMAND_MM, MASK_VMAND_MM) -DECLARE_INSN(vmandn_mm, MATCH_VMANDN_MM, MASK_VMANDN_MM) -DECLARE_INSN(vmax_vv, MATCH_VMAX_VV, MASK_VMAX_VV) -DECLARE_INSN(vmax_vx, MATCH_VMAX_VX, MASK_VMAX_VX) -DECLARE_INSN(vmaxu_vv, MATCH_VMAXU_VV, MASK_VMAXU_VV) -DECLARE_INSN(vmaxu_vx, MATCH_VMAXU_VX, MASK_VMAXU_VX) -DECLARE_INSN(vmerge_vim, MATCH_VMERGE_VIM, MASK_VMERGE_VIM) -DECLARE_INSN(vmerge_vvm, MATCH_VMERGE_VVM, MASK_VMERGE_VVM) -DECLARE_INSN(vmerge_vxm, MATCH_VMERGE_VXM, MASK_VMERGE_VXM) -DECLARE_INSN(vmfeq_vf, MATCH_VMFEQ_VF, MASK_VMFEQ_VF) -DECLARE_INSN(vmfeq_vv, MATCH_VMFEQ_VV, MASK_VMFEQ_VV) -DECLARE_INSN(vmfge_vf, MATCH_VMFGE_VF, MASK_VMFGE_VF) -DECLARE_INSN(vmfgt_vf, MATCH_VMFGT_VF, MASK_VMFGT_VF) -DECLARE_INSN(vmfle_vf, MATCH_VMFLE_VF, MASK_VMFLE_VF) -DECLARE_INSN(vmfle_vv, MATCH_VMFLE_VV, MASK_VMFLE_VV) -DECLARE_INSN(vmflt_vf, MATCH_VMFLT_VF, MASK_VMFLT_VF) -DECLARE_INSN(vmflt_vv, MATCH_VMFLT_VV, MASK_VMFLT_VV) -DECLARE_INSN(vmfne_vf, MATCH_VMFNE_VF, MASK_VMFNE_VF) -DECLARE_INSN(vmfne_vv, MATCH_VMFNE_VV, MASK_VMFNE_VV) -DECLARE_INSN(vmin_vv, MATCH_VMIN_VV, MASK_VMIN_VV) -DECLARE_INSN(vmin_vx, MATCH_VMIN_VX, MASK_VMIN_VX) -DECLARE_INSN(vminu_vv, MATCH_VMINU_VV, MASK_VMINU_VV) -DECLARE_INSN(vminu_vx, MATCH_VMINU_VX, MASK_VMINU_VX) -DECLARE_INSN(vmnand_mm, MATCH_VMNAND_MM, MASK_VMNAND_MM) -DECLARE_INSN(vmnor_mm, MATCH_VMNOR_MM, MASK_VMNOR_MM) -DECLARE_INSN(vmor_mm, MATCH_VMOR_MM, MASK_VMOR_MM) -DECLARE_INSN(vmorn_mm, MATCH_VMORN_MM, MASK_VMORN_MM) -DECLARE_INSN(vmsbc_vv, MATCH_VMSBC_VV, MASK_VMSBC_VV) -DECLARE_INSN(vmsbc_vvm, MATCH_VMSBC_VVM, MASK_VMSBC_VVM) -DECLARE_INSN(vmsbc_vx, MATCH_VMSBC_VX, MASK_VMSBC_VX) -DECLARE_INSN(vmsbc_vxm, MATCH_VMSBC_VXM, MASK_VMSBC_VXM) -DECLARE_INSN(vmsbf_m, MATCH_VMSBF_M, MASK_VMSBF_M) -DECLARE_INSN(vmseq_vi, MATCH_VMSEQ_VI, MASK_VMSEQ_VI) -DECLARE_INSN(vmseq_vv, MATCH_VMSEQ_VV, MASK_VMSEQ_VV) -DECLARE_INSN(vmseq_vx, MATCH_VMSEQ_VX, MASK_VMSEQ_VX) -DECLARE_INSN(vmsgt_vi, MATCH_VMSGT_VI, MASK_VMSGT_VI) -DECLARE_INSN(vmsgt_vx, MATCH_VMSGT_VX, MASK_VMSGT_VX) -DECLARE_INSN(vmsgtu_vi, MATCH_VMSGTU_VI, MASK_VMSGTU_VI) -DECLARE_INSN(vmsgtu_vx, MATCH_VMSGTU_VX, MASK_VMSGTU_VX) -DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M) -DECLARE_INSN(vmsle_vi, MATCH_VMSLE_VI, MASK_VMSLE_VI) -DECLARE_INSN(vmsle_vv, MATCH_VMSLE_VV, MASK_VMSLE_VV) -DECLARE_INSN(vmsle_vx, MATCH_VMSLE_VX, MASK_VMSLE_VX) -DECLARE_INSN(vmsleu_vi, MATCH_VMSLEU_VI, MASK_VMSLEU_VI) -DECLARE_INSN(vmsleu_vv, MATCH_VMSLEU_VV, MASK_VMSLEU_VV) -DECLARE_INSN(vmsleu_vx, MATCH_VMSLEU_VX, MASK_VMSLEU_VX) -DECLARE_INSN(vmslt_vv, MATCH_VMSLT_VV, MASK_VMSLT_VV) -DECLARE_INSN(vmslt_vx, MATCH_VMSLT_VX, MASK_VMSLT_VX) -DECLARE_INSN(vmsltu_vv, MATCH_VMSLTU_VV, MASK_VMSLTU_VV) -DECLARE_INSN(vmsltu_vx, MATCH_VMSLTU_VX, MASK_VMSLTU_VX) -DECLARE_INSN(vmsne_vi, MATCH_VMSNE_VI, MASK_VMSNE_VI) -DECLARE_INSN(vmsne_vv, MATCH_VMSNE_VV, MASK_VMSNE_VV) -DECLARE_INSN(vmsne_vx, MATCH_VMSNE_VX, MASK_VMSNE_VX) -DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M) -DECLARE_INSN(vmul_vv, MATCH_VMUL_VV, MASK_VMUL_VV) -DECLARE_INSN(vmul_vx, MATCH_VMUL_VX, MASK_VMUL_VX) -DECLARE_INSN(vmulh_vv, MATCH_VMULH_VV, MASK_VMULH_VV) -DECLARE_INSN(vmulh_vx, MATCH_VMULH_VX, MASK_VMULH_VX) -DECLARE_INSN(vmulhsu_vv, MATCH_VMULHSU_VV, MASK_VMULHSU_VV) -DECLARE_INSN(vmulhsu_vx, MATCH_VMULHSU_VX, MASK_VMULHSU_VX) -DECLARE_INSN(vmulhu_vv, MATCH_VMULHU_VV, MASK_VMULHU_VV) -DECLARE_INSN(vmulhu_vx, MATCH_VMULHU_VX, MASK_VMULHU_VX) -DECLARE_INSN(vmv1r_v, MATCH_VMV1R_V, MASK_VMV1R_V) -DECLARE_INSN(vmv2r_v, MATCH_VMV2R_V, MASK_VMV2R_V) -DECLARE_INSN(vmv4r_v, MATCH_VMV4R_V, MASK_VMV4R_V) -DECLARE_INSN(vmv8r_v, MATCH_VMV8R_V, MASK_VMV8R_V) -DECLARE_INSN(vmv_s_x, MATCH_VMV_S_X, MASK_VMV_S_X) -DECLARE_INSN(vmv_v_i, MATCH_VMV_V_I, MASK_VMV_V_I) -DECLARE_INSN(vmv_v_v, MATCH_VMV_V_V, MASK_VMV_V_V) -DECLARE_INSN(vmv_v_x, MATCH_VMV_V_X, MASK_VMV_V_X) -DECLARE_INSN(vmv_x_s, MATCH_VMV_X_S, MASK_VMV_X_S) -DECLARE_INSN(vmxnor_mm, MATCH_VMXNOR_MM, MASK_VMXNOR_MM) -DECLARE_INSN(vmxor_mm, MATCH_VMXOR_MM, MASK_VMXOR_MM) -DECLARE_INSN(vnclip_wi, MATCH_VNCLIP_WI, MASK_VNCLIP_WI) -DECLARE_INSN(vnclip_wv, MATCH_VNCLIP_WV, MASK_VNCLIP_WV) -DECLARE_INSN(vnclip_wx, MATCH_VNCLIP_WX, MASK_VNCLIP_WX) -DECLARE_INSN(vnclipu_wi, MATCH_VNCLIPU_WI, MASK_VNCLIPU_WI) -DECLARE_INSN(vnclipu_wv, MATCH_VNCLIPU_WV, MASK_VNCLIPU_WV) -DECLARE_INSN(vnclipu_wx, MATCH_VNCLIPU_WX, MASK_VNCLIPU_WX) -DECLARE_INSN(vnmsac_vv, MATCH_VNMSAC_VV, MASK_VNMSAC_VV) -DECLARE_INSN(vnmsac_vx, MATCH_VNMSAC_VX, MASK_VNMSAC_VX) -DECLARE_INSN(vnmsub_vv, MATCH_VNMSUB_VV, MASK_VNMSUB_VV) -DECLARE_INSN(vnmsub_vx, MATCH_VNMSUB_VX, MASK_VNMSUB_VX) -DECLARE_INSN(vnsra_wi, MATCH_VNSRA_WI, MASK_VNSRA_WI) -DECLARE_INSN(vnsra_wv, MATCH_VNSRA_WV, MASK_VNSRA_WV) -DECLARE_INSN(vnsra_wx, MATCH_VNSRA_WX, MASK_VNSRA_WX) -DECLARE_INSN(vnsrl_wi, MATCH_VNSRL_WI, MASK_VNSRL_WI) -DECLARE_INSN(vnsrl_wv, MATCH_VNSRL_WV, MASK_VNSRL_WV) -DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX) -DECLARE_INSN(vor_vi, MATCH_VOR_VI, MASK_VOR_VI) -DECLARE_INSN(vor_vv, MATCH_VOR_VV, MASK_VOR_VV) -DECLARE_INSN(vor_vx, MATCH_VOR_VX, MASK_VOR_VX) -DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS) -DECLARE_INSN(vredmax_vs, MATCH_VREDMAX_VS, MASK_VREDMAX_VS) -DECLARE_INSN(vredmaxu_vs, MATCH_VREDMAXU_VS, MASK_VREDMAXU_VS) -DECLARE_INSN(vredmin_vs, MATCH_VREDMIN_VS, MASK_VREDMIN_VS) -DECLARE_INSN(vredminu_vs, MATCH_VREDMINU_VS, MASK_VREDMINU_VS) -DECLARE_INSN(vredor_vs, MATCH_VREDOR_VS, MASK_VREDOR_VS) -DECLARE_INSN(vredsum_vs, MATCH_VREDSUM_VS, MASK_VREDSUM_VS) -DECLARE_INSN(vredxor_vs, MATCH_VREDXOR_VS, MASK_VREDXOR_VS) -DECLARE_INSN(vrem_vv, MATCH_VREM_VV, MASK_VREM_VV) -DECLARE_INSN(vrem_vx, MATCH_VREM_VX, MASK_VREM_VX) -DECLARE_INSN(vremu_vv, MATCH_VREMU_VV, MASK_VREMU_VV) -DECLARE_INSN(vremu_vx, MATCH_VREMU_VX, MASK_VREMU_VX) -DECLARE_INSN(vrgather_vi, MATCH_VRGATHER_VI, MASK_VRGATHER_VI) -DECLARE_INSN(vrgather_vv, MATCH_VRGATHER_VV, MASK_VRGATHER_VV) -DECLARE_INSN(vrgather_vx, MATCH_VRGATHER_VX, MASK_VRGATHER_VX) -DECLARE_INSN(vrgatherei16_vv, MATCH_VRGATHEREI16_VV, MASK_VRGATHEREI16_VV) -DECLARE_INSN(vrsub_vi, MATCH_VRSUB_VI, MASK_VRSUB_VI) -DECLARE_INSN(vrsub_vx, MATCH_VRSUB_VX, MASK_VRSUB_VX) -DECLARE_INSN(vs1r_v, MATCH_VS1R_V, MASK_VS1R_V) -DECLARE_INSN(vs2r_v, MATCH_VS2R_V, MASK_VS2R_V) -DECLARE_INSN(vs4r_v, MATCH_VS4R_V, MASK_VS4R_V) -DECLARE_INSN(vs8r_v, MATCH_VS8R_V, MASK_VS8R_V) -DECLARE_INSN(vsadd_vi, MATCH_VSADD_VI, MASK_VSADD_VI) -DECLARE_INSN(vsadd_vv, MATCH_VSADD_VV, MASK_VSADD_VV) -DECLARE_INSN(vsadd_vx, MATCH_VSADD_VX, MASK_VSADD_VX) -DECLARE_INSN(vsaddu_vi, MATCH_VSADDU_VI, MASK_VSADDU_VI) -DECLARE_INSN(vsaddu_vv, MATCH_VSADDU_VV, MASK_VSADDU_VV) -DECLARE_INSN(vsaddu_vx, MATCH_VSADDU_VX, MASK_VSADDU_VX) -DECLARE_INSN(vsbc_vvm, MATCH_VSBC_VVM, MASK_VSBC_VVM) -DECLARE_INSN(vsbc_vxm, MATCH_VSBC_VXM, MASK_VSBC_VXM) -DECLARE_INSN(vse1024_v, MATCH_VSE1024_V, MASK_VSE1024_V) -DECLARE_INSN(vse128_v, MATCH_VSE128_V, MASK_VSE128_V) -DECLARE_INSN(vse16_v, MATCH_VSE16_V, MASK_VSE16_V) -DECLARE_INSN(vse256_v, MATCH_VSE256_V, MASK_VSE256_V) -DECLARE_INSN(vse32_v, MATCH_VSE32_V, MASK_VSE32_V) -DECLARE_INSN(vse512_v, MATCH_VSE512_V, MASK_VSE512_V) -DECLARE_INSN(vse64_v, MATCH_VSE64_V, MASK_VSE64_V) -DECLARE_INSN(vse8_v, MATCH_VSE8_V, MASK_VSE8_V) -DECLARE_INSN(vsetivli, MATCH_VSETIVLI, MASK_VSETIVLI) -DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL) -DECLARE_INSN(vsetvli, MATCH_VSETVLI, MASK_VSETVLI) -DECLARE_INSN(vsext_vf2, MATCH_VSEXT_VF2, MASK_VSEXT_VF2) -DECLARE_INSN(vsext_vf4, MATCH_VSEXT_VF4, MASK_VSEXT_VF4) -DECLARE_INSN(vsext_vf8, MATCH_VSEXT_VF8, MASK_VSEXT_VF8) -DECLARE_INSN(vslide1down_vx, MATCH_VSLIDE1DOWN_VX, MASK_VSLIDE1DOWN_VX) -DECLARE_INSN(vslide1up_vx, MATCH_VSLIDE1UP_VX, MASK_VSLIDE1UP_VX) -DECLARE_INSN(vslidedown_vi, MATCH_VSLIDEDOWN_VI, MASK_VSLIDEDOWN_VI) -DECLARE_INSN(vslidedown_vx, MATCH_VSLIDEDOWN_VX, MASK_VSLIDEDOWN_VX) -DECLARE_INSN(vslideup_vi, MATCH_VSLIDEUP_VI, MASK_VSLIDEUP_VI) -DECLARE_INSN(vslideup_vx, MATCH_VSLIDEUP_VX, MASK_VSLIDEUP_VX) -DECLARE_INSN(vsll_vi, MATCH_VSLL_VI, MASK_VSLL_VI) -DECLARE_INSN(vsll_vv, MATCH_VSLL_VV, MASK_VSLL_VV) -DECLARE_INSN(vsll_vx, MATCH_VSLL_VX, MASK_VSLL_VX) -DECLARE_INSN(vsm_v, MATCH_VSM_V, MASK_VSM_V) -DECLARE_INSN(vsmul_vv, MATCH_VSMUL_VV, MASK_VSMUL_VV) -DECLARE_INSN(vsmul_vx, MATCH_VSMUL_VX, MASK_VSMUL_VX) -DECLARE_INSN(vsoxei1024_v, MATCH_VSOXEI1024_V, MASK_VSOXEI1024_V) -DECLARE_INSN(vsoxei128_v, MATCH_VSOXEI128_V, MASK_VSOXEI128_V) -DECLARE_INSN(vsoxei16_v, MATCH_VSOXEI16_V, MASK_VSOXEI16_V) -DECLARE_INSN(vsoxei256_v, MATCH_VSOXEI256_V, MASK_VSOXEI256_V) -DECLARE_INSN(vsoxei32_v, MATCH_VSOXEI32_V, MASK_VSOXEI32_V) -DECLARE_INSN(vsoxei512_v, MATCH_VSOXEI512_V, MASK_VSOXEI512_V) -DECLARE_INSN(vsoxei64_v, MATCH_VSOXEI64_V, MASK_VSOXEI64_V) -DECLARE_INSN(vsoxei8_v, MATCH_VSOXEI8_V, MASK_VSOXEI8_V) -DECLARE_INSN(vsra_vi, MATCH_VSRA_VI, MASK_VSRA_VI) -DECLARE_INSN(vsra_vv, MATCH_VSRA_VV, MASK_VSRA_VV) -DECLARE_INSN(vsra_vx, MATCH_VSRA_VX, MASK_VSRA_VX) -DECLARE_INSN(vsrl_vi, MATCH_VSRL_VI, MASK_VSRL_VI) -DECLARE_INSN(vsrl_vv, MATCH_VSRL_VV, MASK_VSRL_VV) -DECLARE_INSN(vsrl_vx, MATCH_VSRL_VX, MASK_VSRL_VX) -DECLARE_INSN(vsse1024_v, MATCH_VSSE1024_V, MASK_VSSE1024_V) -DECLARE_INSN(vsse128_v, MATCH_VSSE128_V, MASK_VSSE128_V) -DECLARE_INSN(vsse16_v, MATCH_VSSE16_V, MASK_VSSE16_V) -DECLARE_INSN(vsse256_v, MATCH_VSSE256_V, MASK_VSSE256_V) -DECLARE_INSN(vsse32_v, MATCH_VSSE32_V, MASK_VSSE32_V) -DECLARE_INSN(vsse512_v, MATCH_VSSE512_V, MASK_VSSE512_V) -DECLARE_INSN(vsse64_v, MATCH_VSSE64_V, MASK_VSSE64_V) -DECLARE_INSN(vsse8_v, MATCH_VSSE8_V, MASK_VSSE8_V) -DECLARE_INSN(vssra_vi, MATCH_VSSRA_VI, MASK_VSSRA_VI) -DECLARE_INSN(vssra_vv, MATCH_VSSRA_VV, MASK_VSSRA_VV) -DECLARE_INSN(vssra_vx, MATCH_VSSRA_VX, MASK_VSSRA_VX) -DECLARE_INSN(vssrl_vi, MATCH_VSSRL_VI, MASK_VSSRL_VI) -DECLARE_INSN(vssrl_vv, MATCH_VSSRL_VV, MASK_VSSRL_VV) -DECLARE_INSN(vssrl_vx, MATCH_VSSRL_VX, MASK_VSSRL_VX) -DECLARE_INSN(vssub_vv, MATCH_VSSUB_VV, MASK_VSSUB_VV) -DECLARE_INSN(vssub_vx, MATCH_VSSUB_VX, MASK_VSSUB_VX) -DECLARE_INSN(vssubu_vv, MATCH_VSSUBU_VV, MASK_VSSUBU_VV) -DECLARE_INSN(vssubu_vx, MATCH_VSSUBU_VX, MASK_VSSUBU_VX) -DECLARE_INSN(vsub_vv, MATCH_VSUB_VV, MASK_VSUB_VV) -DECLARE_INSN(vsub_vx, MATCH_VSUB_VX, MASK_VSUB_VX) -DECLARE_INSN(vsuxei1024_v, MATCH_VSUXEI1024_V, MASK_VSUXEI1024_V) -DECLARE_INSN(vsuxei128_v, MATCH_VSUXEI128_V, MASK_VSUXEI128_V) -DECLARE_INSN(vsuxei16_v, MATCH_VSUXEI16_V, MASK_VSUXEI16_V) -DECLARE_INSN(vsuxei256_v, MATCH_VSUXEI256_V, MASK_VSUXEI256_V) -DECLARE_INSN(vsuxei32_v, MATCH_VSUXEI32_V, MASK_VSUXEI32_V) -DECLARE_INSN(vsuxei512_v, MATCH_VSUXEI512_V, MASK_VSUXEI512_V) -DECLARE_INSN(vsuxei64_v, MATCH_VSUXEI64_V, MASK_VSUXEI64_V) -DECLARE_INSN(vsuxei8_v, MATCH_VSUXEI8_V, MASK_VSUXEI8_V) -DECLARE_INSN(vwadd_vv, MATCH_VWADD_VV, MASK_VWADD_VV) -DECLARE_INSN(vwadd_vx, MATCH_VWADD_VX, MASK_VWADD_VX) -DECLARE_INSN(vwadd_wv, MATCH_VWADD_WV, MASK_VWADD_WV) -DECLARE_INSN(vwadd_wx, MATCH_VWADD_WX, MASK_VWADD_WX) -DECLARE_INSN(vwaddu_vv, MATCH_VWADDU_VV, MASK_VWADDU_VV) -DECLARE_INSN(vwaddu_vx, MATCH_VWADDU_VX, MASK_VWADDU_VX) -DECLARE_INSN(vwaddu_wv, MATCH_VWADDU_WV, MASK_VWADDU_WV) -DECLARE_INSN(vwaddu_wx, MATCH_VWADDU_WX, MASK_VWADDU_WX) -DECLARE_INSN(vwmacc_vv, MATCH_VWMACC_VV, MASK_VWMACC_VV) -DECLARE_INSN(vwmacc_vx, MATCH_VWMACC_VX, MASK_VWMACC_VX) -DECLARE_INSN(vwmaccsu_vv, MATCH_VWMACCSU_VV, MASK_VWMACCSU_VV) -DECLARE_INSN(vwmaccsu_vx, MATCH_VWMACCSU_VX, MASK_VWMACCSU_VX) -DECLARE_INSN(vwmaccu_vv, MATCH_VWMACCU_VV, MASK_VWMACCU_VV) -DECLARE_INSN(vwmaccu_vx, MATCH_VWMACCU_VX, MASK_VWMACCU_VX) -DECLARE_INSN(vwmaccus_vx, MATCH_VWMACCUS_VX, MASK_VWMACCUS_VX) -DECLARE_INSN(vwmul_vv, MATCH_VWMUL_VV, MASK_VWMUL_VV) -DECLARE_INSN(vwmul_vx, MATCH_VWMUL_VX, MASK_VWMUL_VX) -DECLARE_INSN(vwmulsu_vv, MATCH_VWMULSU_VV, MASK_VWMULSU_VV) -DECLARE_INSN(vwmulsu_vx, MATCH_VWMULSU_VX, MASK_VWMULSU_VX) -DECLARE_INSN(vwmulu_vv, MATCH_VWMULU_VV, MASK_VWMULU_VV) -DECLARE_INSN(vwmulu_vx, MATCH_VWMULU_VX, MASK_VWMULU_VX) -DECLARE_INSN(vwredsum_vs, MATCH_VWREDSUM_VS, MASK_VWREDSUM_VS) -DECLARE_INSN(vwredsumu_vs, MATCH_VWREDSUMU_VS, MASK_VWREDSUMU_VS) -DECLARE_INSN(vwsub_vv, MATCH_VWSUB_VV, MASK_VWSUB_VV) -DECLARE_INSN(vwsub_vx, MATCH_VWSUB_VX, MASK_VWSUB_VX) -DECLARE_INSN(vwsub_wv, MATCH_VWSUB_WV, MASK_VWSUB_WV) -DECLARE_INSN(vwsub_wx, MATCH_VWSUB_WX, MASK_VWSUB_WX) -DECLARE_INSN(vwsubu_vv, MATCH_VWSUBU_VV, MASK_VWSUBU_VV) -DECLARE_INSN(vwsubu_vx, MATCH_VWSUBU_VX, MASK_VWSUBU_VX) -DECLARE_INSN(vwsubu_wv, MATCH_VWSUBU_WV, MASK_VWSUBU_WV) -DECLARE_INSN(vwsubu_wx, MATCH_VWSUBU_WX, MASK_VWSUBU_WX) -DECLARE_INSN(vxor_vi, MATCH_VXOR_VI, MASK_VXOR_VI) -DECLARE_INSN(vxor_vv, MATCH_VXOR_VV, MASK_VXOR_VV) -DECLARE_INSN(vxor_vx, MATCH_VXOR_VX, MASK_VXOR_VX) -DECLARE_INSN(vzext_vf2, MATCH_VZEXT_VF2, MASK_VZEXT_VF2) -DECLARE_INSN(vzext_vf4, MATCH_VZEXT_VF4, MASK_VZEXT_VF4) -DECLARE_INSN(vzext_vf8, MATCH_VZEXT_VF8, MASK_VZEXT_VF8) -DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) -DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) -DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) -DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR) -DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) -DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) -DECLARE_INSN(xperm16, MATCH_XPERM16, MASK_XPERM16) -DECLARE_INSN(xperm32, MATCH_XPERM32, MASK_XPERM32) -DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4) -DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8) -DECLARE_INSN(zunpkd810, MATCH_ZUNPKD810, MASK_ZUNPKD810) -DECLARE_INSN(zunpkd820, MATCH_ZUNPKD820, MASK_ZUNPKD820) -DECLARE_INSN(zunpkd830, MATCH_ZUNPKD830, MASK_ZUNPKD830) -DECLARE_INSN(zunpkd831, MATCH_ZUNPKD831, MASK_ZUNPKD831) -DECLARE_INSN(zunpkd832, MATCH_ZUNPKD832, MASK_ZUNPKD832) -#endif -#ifdef DECLARE_CSR -DECLARE_CSR(fflags, CSR_FFLAGS) -DECLARE_CSR(frm, CSR_FRM) -DECLARE_CSR(fcsr, CSR_FCSR) -DECLARE_CSR(vstart, CSR_VSTART) -DECLARE_CSR(vxsat, CSR_VXSAT) -DECLARE_CSR(vxrm, CSR_VXRM) -DECLARE_CSR(vcsr, CSR_VCSR) -DECLARE_CSR(seed, CSR_SEED) -DECLARE_CSR(jvt, CSR_JVT) -DECLARE_CSR(cycle, CSR_CYCLE) -DECLARE_CSR(time, CSR_TIME) -DECLARE_CSR(instret, CSR_INSTRET) -DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) -DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) -DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) -DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) -DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) -DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) -DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) -DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) -DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) -DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) -DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) -DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) -DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) -DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) -DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) -DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) -DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) -DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) -DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) -DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) -DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) -DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) -DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) -DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) -DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) -DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) -DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) -DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) -DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) -DECLARE_CSR(vl, CSR_VL) -DECLARE_CSR(vtype, CSR_VTYPE) -DECLARE_CSR(vlenb, CSR_VLENB) -DECLARE_CSR(sstatus, CSR_SSTATUS) -DECLARE_CSR(sedeleg, CSR_SEDELEG) -DECLARE_CSR(sideleg, CSR_SIDELEG) -DECLARE_CSR(sie, CSR_SIE) -DECLARE_CSR(stvec, CSR_STVEC) -DECLARE_CSR(scounteren, CSR_SCOUNTEREN) -DECLARE_CSR(senvcfg, CSR_SENVCFG) -DECLARE_CSR(sstateen0, CSR_SSTATEEN0) -DECLARE_CSR(sstateen1, CSR_SSTATEEN1) -DECLARE_CSR(sstateen2, CSR_SSTATEEN2) -DECLARE_CSR(sstateen3, CSR_SSTATEEN3) -DECLARE_CSR(sscratch, CSR_SSCRATCH) -DECLARE_CSR(sepc, CSR_SEPC) -DECLARE_CSR(scause, CSR_SCAUSE) -DECLARE_CSR(stval, CSR_STVAL) -DECLARE_CSR(sip, CSR_SIP) -DECLARE_CSR(stimecmp, CSR_STIMECMP) -DECLARE_CSR(siselect, CSR_SISELECT) -DECLARE_CSR(sireg, CSR_SIREG) -DECLARE_CSR(stopei, CSR_STOPEI) -DECLARE_CSR(satp, CSR_SATP) -DECLARE_CSR(scontext, CSR_SCONTEXT) -DECLARE_CSR(vsstatus, CSR_VSSTATUS) -DECLARE_CSR(vsie, CSR_VSIE) -DECLARE_CSR(vstvec, CSR_VSTVEC) -DECLARE_CSR(vsscratch, CSR_VSSCRATCH) -DECLARE_CSR(vsepc, CSR_VSEPC) -DECLARE_CSR(vscause, CSR_VSCAUSE) -DECLARE_CSR(vstval, CSR_VSTVAL) -DECLARE_CSR(vsip, CSR_VSIP) -DECLARE_CSR(vstimecmp, CSR_VSTIMECMP) -DECLARE_CSR(vsiselect, CSR_VSISELECT) -DECLARE_CSR(vsireg, CSR_VSIREG) -DECLARE_CSR(vstopei, CSR_VSTOPEI) -DECLARE_CSR(vsatp, CSR_VSATP) -DECLARE_CSR(hstatus, CSR_HSTATUS) -DECLARE_CSR(hedeleg, CSR_HEDELEG) -DECLARE_CSR(hideleg, CSR_HIDELEG) -DECLARE_CSR(hie, CSR_HIE) -DECLARE_CSR(htimedelta, CSR_HTIMEDELTA) -DECLARE_CSR(hcounteren, CSR_HCOUNTEREN) -DECLARE_CSR(hgeie, CSR_HGEIE) -DECLARE_CSR(hvien, CSR_HVIEN) -DECLARE_CSR(hvictl, CSR_HVICTL) -DECLARE_CSR(henvcfg, CSR_HENVCFG) -DECLARE_CSR(hstateen0, CSR_HSTATEEN0) -DECLARE_CSR(hstateen1, CSR_HSTATEEN1) -DECLARE_CSR(hstateen2, CSR_HSTATEEN2) -DECLARE_CSR(hstateen3, CSR_HSTATEEN3) -DECLARE_CSR(htval, CSR_HTVAL) -DECLARE_CSR(hip, CSR_HIP) -DECLARE_CSR(hvip, CSR_HVIP) -DECLARE_CSR(hviprio1, CSR_HVIPRIO1) -DECLARE_CSR(hviprio2, CSR_HVIPRIO2) -DECLARE_CSR(htinst, CSR_HTINST) -DECLARE_CSR(hgatp, CSR_HGATP) -DECLARE_CSR(hcontext, CSR_HCONTEXT) -DECLARE_CSR(hgeip, CSR_HGEIP) -DECLARE_CSR(vstopi, CSR_VSTOPI) -DECLARE_CSR(scountovf, CSR_SCOUNTOVF) -DECLARE_CSR(stopi, CSR_STOPI) -DECLARE_CSR(utvt, CSR_UTVT) -DECLARE_CSR(unxti, CSR_UNXTI) -DECLARE_CSR(uintstatus, CSR_UINTSTATUS) -DECLARE_CSR(uscratchcsw, CSR_USCRATCHCSW) -DECLARE_CSR(uscratchcswl, CSR_USCRATCHCSWL) -DECLARE_CSR(stvt, CSR_STVT) -DECLARE_CSR(snxti, CSR_SNXTI) -DECLARE_CSR(sintstatus, CSR_SINTSTATUS) -DECLARE_CSR(sscratchcsw, CSR_SSCRATCHCSW) -DECLARE_CSR(sscratchcswl, CSR_SSCRATCHCSWL) -DECLARE_CSR(mtvt, CSR_MTVT) -DECLARE_CSR(mnxti, CSR_MNXTI) -DECLARE_CSR(mintstatus, CSR_MINTSTATUS) -DECLARE_CSR(mscratchcsw, CSR_MSCRATCHCSW) -DECLARE_CSR(mscratchcswl, CSR_MSCRATCHCSWL) -DECLARE_CSR(mstatus, CSR_MSTATUS) -DECLARE_CSR(misa, CSR_MISA) -DECLARE_CSR(medeleg, CSR_MEDELEG) -DECLARE_CSR(mideleg, CSR_MIDELEG) -DECLARE_CSR(mie, CSR_MIE) -DECLARE_CSR(mtvec, CSR_MTVEC) -DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) -DECLARE_CSR(mvien, CSR_MVIEN) -DECLARE_CSR(mvip, CSR_MVIP) -DECLARE_CSR(menvcfg, CSR_MENVCFG) -DECLARE_CSR(mstateen0, CSR_MSTATEEN0) -DECLARE_CSR(mstateen1, CSR_MSTATEEN1) -DECLARE_CSR(mstateen2, CSR_MSTATEEN2) -DECLARE_CSR(mstateen3, CSR_MSTATEEN3) -DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT) -DECLARE_CSR(mscratch, CSR_MSCRATCH) -DECLARE_CSR(mepc, CSR_MEPC) -DECLARE_CSR(mcause, CSR_MCAUSE) -DECLARE_CSR(mtval, CSR_MTVAL) -DECLARE_CSR(mip, CSR_MIP) -DECLARE_CSR(mtinst, CSR_MTINST) -DECLARE_CSR(mtval2, CSR_MTVAL2) -DECLARE_CSR(miselect, CSR_MISELECT) -DECLARE_CSR(mireg, CSR_MIREG) -DECLARE_CSR(mtopei, CSR_MTOPEI) -DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) -DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) -DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) -DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) -DECLARE_CSR(pmpcfg4, CSR_PMPCFG4) -DECLARE_CSR(pmpcfg5, CSR_PMPCFG5) -DECLARE_CSR(pmpcfg6, CSR_PMPCFG6) -DECLARE_CSR(pmpcfg7, CSR_PMPCFG7) -DECLARE_CSR(pmpcfg8, CSR_PMPCFG8) -DECLARE_CSR(pmpcfg9, CSR_PMPCFG9) -DECLARE_CSR(pmpcfg10, CSR_PMPCFG10) -DECLARE_CSR(pmpcfg11, CSR_PMPCFG11) -DECLARE_CSR(pmpcfg12, CSR_PMPCFG12) -DECLARE_CSR(pmpcfg13, CSR_PMPCFG13) -DECLARE_CSR(pmpcfg14, CSR_PMPCFG14) -DECLARE_CSR(pmpcfg15, CSR_PMPCFG15) -DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) -DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) -DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) -DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) -DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) -DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) -DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) -DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) -DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) -DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) -DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) -DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) -DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) -DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) -DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) -DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) -DECLARE_CSR(pmpaddr16, CSR_PMPADDR16) -DECLARE_CSR(pmpaddr17, CSR_PMPADDR17) -DECLARE_CSR(pmpaddr18, CSR_PMPADDR18) -DECLARE_CSR(pmpaddr19, CSR_PMPADDR19) -DECLARE_CSR(pmpaddr20, CSR_PMPADDR20) -DECLARE_CSR(pmpaddr21, CSR_PMPADDR21) -DECLARE_CSR(pmpaddr22, CSR_PMPADDR22) -DECLARE_CSR(pmpaddr23, CSR_PMPADDR23) -DECLARE_CSR(pmpaddr24, CSR_PMPADDR24) -DECLARE_CSR(pmpaddr25, CSR_PMPADDR25) -DECLARE_CSR(pmpaddr26, CSR_PMPADDR26) -DECLARE_CSR(pmpaddr27, CSR_PMPADDR27) -DECLARE_CSR(pmpaddr28, CSR_PMPADDR28) -DECLARE_CSR(pmpaddr29, CSR_PMPADDR29) -DECLARE_CSR(pmpaddr30, CSR_PMPADDR30) -DECLARE_CSR(pmpaddr31, CSR_PMPADDR31) -DECLARE_CSR(pmpaddr32, CSR_PMPADDR32) -DECLARE_CSR(pmpaddr33, CSR_PMPADDR33) -DECLARE_CSR(pmpaddr34, CSR_PMPADDR34) -DECLARE_CSR(pmpaddr35, CSR_PMPADDR35) -DECLARE_CSR(pmpaddr36, CSR_PMPADDR36) -DECLARE_CSR(pmpaddr37, CSR_PMPADDR37) -DECLARE_CSR(pmpaddr38, CSR_PMPADDR38) -DECLARE_CSR(pmpaddr39, CSR_PMPADDR39) -DECLARE_CSR(pmpaddr40, CSR_PMPADDR40) -DECLARE_CSR(pmpaddr41, CSR_PMPADDR41) -DECLARE_CSR(pmpaddr42, CSR_PMPADDR42) -DECLARE_CSR(pmpaddr43, CSR_PMPADDR43) -DECLARE_CSR(pmpaddr44, CSR_PMPADDR44) -DECLARE_CSR(pmpaddr45, CSR_PMPADDR45) -DECLARE_CSR(pmpaddr46, CSR_PMPADDR46) -DECLARE_CSR(pmpaddr47, CSR_PMPADDR47) -DECLARE_CSR(pmpaddr48, CSR_PMPADDR48) -DECLARE_CSR(pmpaddr49, CSR_PMPADDR49) -DECLARE_CSR(pmpaddr50, CSR_PMPADDR50) -DECLARE_CSR(pmpaddr51, CSR_PMPADDR51) -DECLARE_CSR(pmpaddr52, CSR_PMPADDR52) -DECLARE_CSR(pmpaddr53, CSR_PMPADDR53) -DECLARE_CSR(pmpaddr54, CSR_PMPADDR54) -DECLARE_CSR(pmpaddr55, CSR_PMPADDR55) -DECLARE_CSR(pmpaddr56, CSR_PMPADDR56) -DECLARE_CSR(pmpaddr57, CSR_PMPADDR57) -DECLARE_CSR(pmpaddr58, CSR_PMPADDR58) -DECLARE_CSR(pmpaddr59, CSR_PMPADDR59) -DECLARE_CSR(pmpaddr60, CSR_PMPADDR60) -DECLARE_CSR(pmpaddr61, CSR_PMPADDR61) -DECLARE_CSR(pmpaddr62, CSR_PMPADDR62) -DECLARE_CSR(pmpaddr63, CSR_PMPADDR63) -DECLARE_CSR(mseccfg, CSR_MSECCFG) -DECLARE_CSR(tselect, CSR_TSELECT) -DECLARE_CSR(tdata1, CSR_TDATA1) -DECLARE_CSR(tdata2, CSR_TDATA2) -DECLARE_CSR(tdata3, CSR_TDATA3) -DECLARE_CSR(tinfo, CSR_TINFO) -DECLARE_CSR(tcontrol, CSR_TCONTROL) -DECLARE_CSR(mcontext, CSR_MCONTEXT) -DECLARE_CSR(mscontext, CSR_MSCONTEXT) -DECLARE_CSR(dcsr, CSR_DCSR) -DECLARE_CSR(dpc, CSR_DPC) -DECLARE_CSR(dscratch0, CSR_DSCRATCH0) -DECLARE_CSR(dscratch1, CSR_DSCRATCH1) -DECLARE_CSR(mcycle, CSR_MCYCLE) -DECLARE_CSR(minstret, CSR_MINSTRET) -DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) -DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) -DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) -DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) -DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) -DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) -DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) -DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) -DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) -DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) -DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) -DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) -DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) -DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) -DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) -DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) -DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) -DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) -DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) -DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) -DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) -DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) -DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) -DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) -DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) -DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) -DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) -DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) -DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) -DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) -DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) -DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) -DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) -DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) -DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) -DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) -DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) -DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) -DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) -DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) -DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) -DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) -DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) -DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) -DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) -DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) -DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) -DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) -DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) -DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) -DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) -DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) -DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) -DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) -DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) -DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) -DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) -DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) -DECLARE_CSR(mvendorid, CSR_MVENDORID) -DECLARE_CSR(marchid, CSR_MARCHID) -DECLARE_CSR(mimpid, CSR_MIMPID) -DECLARE_CSR(mhartid, CSR_MHARTID) -DECLARE_CSR(mconfigptr, CSR_MCONFIGPTR) -DECLARE_CSR(mtopi, CSR_MTOPI) -DECLARE_CSR(sieh, CSR_SIEH) -DECLARE_CSR(siph, CSR_SIPH) -DECLARE_CSR(stimecmph, CSR_STIMECMPH) -DECLARE_CSR(vsieh, CSR_VSIEH) -DECLARE_CSR(vsiph, CSR_VSIPH) -DECLARE_CSR(vstimecmph, CSR_VSTIMECMPH) -DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH) -DECLARE_CSR(hidelegh, CSR_HIDELEGH) -DECLARE_CSR(hvienh, CSR_HVIENH) -DECLARE_CSR(henvcfgh, CSR_HENVCFGH) -DECLARE_CSR(hviph, CSR_HVIPH) -DECLARE_CSR(hviprio1h, CSR_HVIPRIO1H) -DECLARE_CSR(hviprio2h, CSR_HVIPRIO2H) -DECLARE_CSR(hstateen0h, CSR_HSTATEEN0H) -DECLARE_CSR(hstateen1h, CSR_HSTATEEN1H) -DECLARE_CSR(hstateen2h, CSR_HSTATEEN2H) -DECLARE_CSR(hstateen3h, CSR_HSTATEEN3H) -DECLARE_CSR(cycleh, CSR_CYCLEH) -DECLARE_CSR(timeh, CSR_TIMEH) -DECLARE_CSR(instreth, CSR_INSTRETH) -DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) -DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) -DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) -DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) -DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) -DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) -DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) -DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) -DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) -DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) -DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) -DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) -DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) -DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) -DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) -DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) -DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) -DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) -DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) -DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) -DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) -DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) -DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) -DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) -DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) -DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) -DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) -DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) -DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) -DECLARE_CSR(mstatush, CSR_MSTATUSH) -DECLARE_CSR(midelegh, CSR_MIDELEGH) -DECLARE_CSR(mieh, CSR_MIEH) -DECLARE_CSR(mvienh, CSR_MVIENH) -DECLARE_CSR(mviph, CSR_MVIPH) -DECLARE_CSR(menvcfgh, CSR_MENVCFGH) -DECLARE_CSR(mstateen0h, CSR_MSTATEEN0H) -DECLARE_CSR(mstateen1h, CSR_MSTATEEN1H) -DECLARE_CSR(mstateen2h, CSR_MSTATEEN2H) -DECLARE_CSR(mstateen3h, CSR_MSTATEEN3H) -DECLARE_CSR(miph, CSR_MIPH) -DECLARE_CSR(mhpmevent3h, CSR_MHPMEVENT3H) -DECLARE_CSR(mhpmevent4h, CSR_MHPMEVENT4H) -DECLARE_CSR(mhpmevent5h, CSR_MHPMEVENT5H) -DECLARE_CSR(mhpmevent6h, CSR_MHPMEVENT6H) -DECLARE_CSR(mhpmevent7h, CSR_MHPMEVENT7H) -DECLARE_CSR(mhpmevent8h, CSR_MHPMEVENT8H) -DECLARE_CSR(mhpmevent9h, CSR_MHPMEVENT9H) -DECLARE_CSR(mhpmevent10h, CSR_MHPMEVENT10H) -DECLARE_CSR(mhpmevent11h, CSR_MHPMEVENT11H) -DECLARE_CSR(mhpmevent12h, CSR_MHPMEVENT12H) -DECLARE_CSR(mhpmevent13h, CSR_MHPMEVENT13H) -DECLARE_CSR(mhpmevent14h, CSR_MHPMEVENT14H) -DECLARE_CSR(mhpmevent15h, CSR_MHPMEVENT15H) -DECLARE_CSR(mhpmevent16h, CSR_MHPMEVENT16H) -DECLARE_CSR(mhpmevent17h, CSR_MHPMEVENT17H) -DECLARE_CSR(mhpmevent18h, CSR_MHPMEVENT18H) -DECLARE_CSR(mhpmevent19h, CSR_MHPMEVENT19H) -DECLARE_CSR(mhpmevent20h, CSR_MHPMEVENT20H) -DECLARE_CSR(mhpmevent21h, CSR_MHPMEVENT21H) -DECLARE_CSR(mhpmevent22h, CSR_MHPMEVENT22H) -DECLARE_CSR(mhpmevent23h, CSR_MHPMEVENT23H) -DECLARE_CSR(mhpmevent24h, CSR_MHPMEVENT24H) -DECLARE_CSR(mhpmevent25h, CSR_MHPMEVENT25H) -DECLARE_CSR(mhpmevent26h, CSR_MHPMEVENT26H) -DECLARE_CSR(mhpmevent27h, CSR_MHPMEVENT27H) -DECLARE_CSR(mhpmevent28h, CSR_MHPMEVENT28H) -DECLARE_CSR(mhpmevent29h, CSR_MHPMEVENT29H) -DECLARE_CSR(mhpmevent30h, CSR_MHPMEVENT30H) -DECLARE_CSR(mhpmevent31h, CSR_MHPMEVENT31H) -DECLARE_CSR(mnscratch, CSR_MNSCRATCH) -DECLARE_CSR(mnepc, CSR_MNEPC) -DECLARE_CSR(mncause, CSR_MNCAUSE) -DECLARE_CSR(mnstatus, CSR_MNSTATUS) -DECLARE_CSR(mseccfgh, CSR_MSECCFGH) -DECLARE_CSR(mcycleh, CSR_MCYCLEH) -DECLARE_CSR(minstreth, CSR_MINSTRETH) -DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) -DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) -DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) -DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) -DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) -DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) -DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) -DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) -DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) -DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) -DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) -DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) -DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) -DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) -DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) -DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) -DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) -DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) -DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) -DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) -DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) -DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) -DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) -DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) -DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) -DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) -DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) -DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) -DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) -#endif -#ifdef DECLARE_CAUSE -DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) -DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) -DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) -DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) -DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) -DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) -DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) -DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) -DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) -DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) -DECLARE_CAUSE("virtual_supervisor_ecall", CAUSE_VIRTUAL_SUPERVISOR_ECALL) -DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) -DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) -DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) -DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) -DECLARE_CAUSE("fetch guest page fault", CAUSE_FETCH_GUEST_PAGE_FAULT) -DECLARE_CAUSE("load guest page fault", CAUSE_LOAD_GUEST_PAGE_FAULT) -DECLARE_CAUSE("virtual instruction", CAUSE_VIRTUAL_INSTRUCTION) -DECLARE_CAUSE("store guest page fault", CAUSE_STORE_GUEST_PAGE_FAULT) -#endif diff --git a/src/main/resources/applications_for_fpga/headers/encoding.h b/src/main/resources/applications_for_fpga/headers/encoding.h new file mode 120000 index 00000000..bce748a4 --- /dev/null +++ b/src/main/resources/applications_for_fpga/headers/encoding.h @@ -0,0 +1 @@ +../../../../../../HAJIME_Core/submodule/riscv-tests/env/encoding.h \ No newline at end of file diff --git a/src/main/resources/applications_for_fpga/headers/test.ld b/src/main/resources/applications_for_fpga/headers/test.ld deleted file mode 100644 index a7fe1f11..00000000 --- a/src/main/resources/applications_for_fpga/headers/test.ld +++ /dev/null @@ -1,66 +0,0 @@ -/*======================================================================*/ -/* Proxy kernel linker script */ -/*======================================================================*/ -/* This is the linker script used when building the proxy kernel. */ - -/*----------------------------------------------------------------------*/ -/* Setup */ -/*----------------------------------------------------------------------*/ - -/* The OUTPUT_ARCH command specifies the machine architecture where the - argument is one of the names used in the BFD library. More - specifically one of the entires in bfd/cpu-mips.c */ - -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -/*----------------------------------------------------------------------*/ -/* Sections */ -/*----------------------------------------------------------------------*/ - -SECTIONS -{ - - /* text: test code section */ - . = 0x00000000; - .text.init : { *(.text.init) } - .text : { *(.text) } - - /* data segment */ - . = ALIGN(0x4000); - .data : { *(.data) } - .rodata : { *(.rodata) } - - .sdata : { - __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) - *(.sdata .sdata.* .gnu.linkonce.s.*) - } - - /* bss segment */ - .sbss : { - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - } - .bss : { *(.bss) } - - /* thread-local data segment */ - .tdata : - { - _tdata_begin = .; - *(.tdata) - _tdata_end = .; - } - .tbss : - { - *(.tbss) - _tbss_end = .; - } - - . = ALIGN(0x10000000); - .tohost : { *(.tohost) } - - /* End of uninitalized data segement */ - _end = .; -} - diff --git a/src/main/resources/applications_for_fpga/headers/test.ld b/src/main/resources/applications_for_fpga/headers/test.ld new file mode 120000 index 00000000..c6573788 --- /dev/null +++ b/src/main/resources/applications_for_fpga/headers/test.ld @@ -0,0 +1 @@ +../../application_headers/test.ld \ No newline at end of file From 5115b459c95c67f4052687738584f16cf4f5d820 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Thu, 30 Nov 2023 12:27:37 +0900 Subject: [PATCH 08/13] a --- .../applications_vector/vector_matmul.dump | 18 +++++++++--------- .../vector_matmul/vector_matmul.c | 5 ++++- .../applications_vector/vector_matmul_inst.hex | 16 ++++++++-------- 3 files changed, 21 insertions(+), 18 deletions(-) diff --git a/src/main/resources/applications_vector/vector_matmul.dump b/src/main/resources/applications_vector/vector_matmul.dump index cbf19d96..5b5d954c 100644 --- a/src/main/resources/applications_vector/vector_matmul.dump +++ b/src/main/resources/applications_vector/vector_matmul.dump @@ -719,16 +719,16 @@ Disassembly of section .text.startup: a6c: 01e888b3 add a7,a7,t5 a70: 000e8813 mv a6,t4 a74: c0050713 add a4,a0,-1024 - a78: 00088613 mv a2,a7 - a7c: 00000793 li a5,0 - a80: 00064683 lbu a3,0(a2) + a78: 00088693 mv a3,a7 + a7c: 00000613 li a2,0 + a80: 0006c783 lbu a5,0(a3) a84: 00074583 lbu a1,0(a4) - a88: 02070713 add a4,a4,32 - a8c: 00160613 add a2,a2,1 - a90: 02b686bb mulw a3,a3,a1 - a94: 00f687bb addw a5,a3,a5 - a98: 0187979b sllw a5,a5,0x18 - a9c: 4187d79b sraw a5,a5,0x18 + a88: 02b787bb mulw a5,a5,a1 + a8c: 00f607bb addw a5,a2,a5 + a90: 0187961b sllw a2,a5,0x18 + a94: 02070713 add a4,a4,32 + a98: 4186561b sraw a2,a2,0x18 + a9c: 00168693 add a3,a3,1 aa0: fea710e3 bne a4,a0,a80 aa4: 00f80023 sb a5,0(a6) aa8: 00170513 add a0,a4,1 diff --git a/src/main/resources/applications_vector/vector_matmul/vector_matmul.c b/src/main/resources/applications_vector/vector_matmul/vector_matmul.c index 65a8ae77..2bd4bfa9 100644 --- a/src/main/resources/applications_vector/vector_matmul/vector_matmul.c +++ b/src/main/resources/applications_vector/vector_matmul/vector_matmul.c @@ -163,7 +163,10 @@ int main(int argc, char** argv) { for(j=0; j<32; j++) { signed char sum = 0; for(k=0; k<32; k++) { - sum += array1[i][k] * array2[k][j]; + signed char temp; + asm volatile ("mulw %0, %1, %2":"=r"(temp):"r"(array1[i][k]), "r"(array2[k][j])); + asm volatile ("addw %0, %1, %2":"=r"(sum):"r"(sum), "r"(temp)); + // sum += array1[i][k] * array2[k][j]; } answerArray[i][j] = sum; } diff --git a/src/main/resources/applications_vector/vector_matmul_inst.hex b/src/main/resources/applications_vector/vector_matmul_inst.hex index 5597ef20..f0d878f8 100644 --- a/src/main/resources/applications_vector/vector_matmul_inst.hex +++ b/src/main/resources/applications_vector/vector_matmul_inst.hex @@ -668,16 +668,16 @@ c0818413 01e888b3 000e8813 c0050713 -00088613 -00000793 -00064683 +00088693 +00000613 +0006c783 00074583 +02b787bb +00f607bb +0187961b 02070713 -00160613 -02b686bb -00f687bb -0187979b -4187d79b +4186561b +00168693 fea710e3 00f80023 00170513 From 5a4e4f5fafd8fb75e349096fab6f6a6992388c34 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Fri, 1 Dec 2023 19:22:25 +0900 Subject: [PATCH 09/13] a --- fpga/fpga.v | 49 + fpga/sim.v | 2 +- fpga/top.v | 8 +- fpga/vector_matmul_data.mem | 257 ++++ fpga/vector_matmul_inst.mem | 352 +++++ .../resources/applications_for_fpga/build.sh | 0 src/main/resources/applications_fpga/build.sh | 33 + .../headers/crt.S | 0 .../headers/encoding.h | 0 .../headers/syscalls.c | 4 +- .../headers/test.ld | 0 .../applications_fpga/printTo7Seg.dump | 379 +++++ .../printTo7Seg/printTo7Seg.c | 3 + .../applications_fpga/printTo7Seg_data.mem | 1 + .../applications_fpga/printTo7Seg_inst.mem | 266 ++++ .../applications_fpga/vector_matmul.dump | 1339 +++++++++++++++++ .../vector_matmul/vector_matmul.c | 160 ++ .../applications_fpga/vector_matmul_data.mem | 514 +++++++ .../applications_fpga/vector_matmul_inst.mem | 352 +++++ .../scala/hajime/common/RISCV_Consts.scala | 2 +- src/main/scala/hajime/simple4Stage/Core.scala | 2 +- .../hajime/vectormodules/VectorExecUnit.scala | 2 + .../hajime/vectormodules/VectorCpuSpec.scala | 26 +- 23 files changed, 3741 insertions(+), 10 deletions(-) create mode 100644 fpga/fpga.v create mode 100644 fpga/vector_matmul_data.mem create mode 100644 fpga/vector_matmul_inst.mem delete mode 100644 src/main/resources/applications_for_fpga/build.sh create mode 100644 src/main/resources/applications_fpga/build.sh rename src/main/resources/{applications_for_fpga => applications_fpga}/headers/crt.S (100%) rename src/main/resources/{applications_for_fpga => applications_fpga}/headers/encoding.h (100%) rename src/main/resources/{applications_for_fpga => applications_fpga}/headers/syscalls.c (96%) rename src/main/resources/{applications_for_fpga => applications_fpga}/headers/test.ld (100%) create mode 100644 src/main/resources/applications_fpga/printTo7Seg.dump create mode 100644 src/main/resources/applications_fpga/printTo7Seg/printTo7Seg.c create mode 100644 src/main/resources/applications_fpga/printTo7Seg_data.mem create mode 100644 src/main/resources/applications_fpga/printTo7Seg_inst.mem create mode 100644 src/main/resources/applications_fpga/vector_matmul.dump create mode 100644 src/main/resources/applications_fpga/vector_matmul/vector_matmul.c create mode 100644 src/main/resources/applications_fpga/vector_matmul_data.mem create mode 100644 src/main/resources/applications_fpga/vector_matmul_inst.mem diff --git a/fpga/fpga.v b/fpga/fpga.v new file mode 100644 index 00000000..e95d52d7 --- /dev/null +++ b/fpga/fpga.v @@ -0,0 +1,49 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 12/01/2023 04:05:10 PM +// Design Name: +// Module Name: fpga +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module fpga( + input clk_in1_0, + input RST_0, + output [6:0] SEG_0, + output [7:0] AN_0 + ); + wire [31:0] check; + wire CLK_top; + + design_1_wrapper clk_wiz( + .clk_in1_0(clk_in1_0), + .clk_out1_0(CLK_top) + ); + + top top( + .CLK(CLK_top), + .RST(RST_0), + .tohost(check) + ); + SEG_PUT seg_put( + .CLK(clk_in1_0), + .reset(RST_0), + .check(check), + .SEG(SEG_0), + .AN(AN_0) + ); +endmodule diff --git a/fpga/sim.v b/fpga/sim.v index 1ae1aadf..d16766da 100644 --- a/fpga/sim.v +++ b/fpga/sim.v @@ -36,7 +36,7 @@ module sim(); #256 RST = 0; #256 RST = 1; - #1024 $finish; + #1048576 $finish; end always begin diff --git a/fpga/top.v b/fpga/top.v index 7bb49756..5da13859 100644 --- a/fpga/top.v +++ b/fpga/top.v @@ -32,7 +32,7 @@ module top( wire io_icache_axi4lite_r_valid; wire [31:0] io_icache_axi4lite_r_bits_data; wire [2:0] io_icache_axi4lite_r_bits_resp; - wire io_icache_axi4lite_w_ready; + // wire io_icache_axi4lite_w_ready; wire io_dcache_axi4lite_ar_ready; wire io_dcache_axi4lite_aw_ready; wire io_dcache_axi4lite_b_valid; @@ -41,8 +41,8 @@ module top( wire [63:0] io_dcache_axi4lite_r_bits_data; wire [2:0] io_dcache_axi4lite_r_bits_resp; wire io_dcache_axi4lite_w_ready; - wire [63:0] io_reset_vector; - wire io_hartid; + // wire [63:0] io_reset_vector; + // wire io_hartid; wire io_icache_axi4lite_ar_valid; wire [63:0] io_icache_axi4lite_ar_bits_addr; wire [2:0] io_icache_axi4lite_ar_bits_prot; @@ -78,7 +78,7 @@ module top( .io_icache_axi4lite_r_valid(io_icache_axi4lite_r_valid), .io_icache_axi4lite_r_bits_data(io_icache_axi4lite_r_bits_data), .io_icache_axi4lite_r_bits_resp(io_icache_axi4lite_r_bits_resp), - .io_icache_axi4lite_w_ready(io_icache_axi4lite_w_ready), + .io_icache_axi4lite_w_ready(), .io_dcache_axi4lite_ar_ready(io_dcache_axi4lite_ar_ready), .io_dcache_axi4lite_aw_ready(io_dcache_axi4lite_aw_ready), .io_dcache_axi4lite_b_valid(io_dcache_axi4lite_b_valid), diff --git a/fpga/vector_matmul_data.mem b/fpga/vector_matmul_data.mem new file mode 100644 index 00000000..7ca5dae9 --- /dev/null +++ b/fpga/vector_matmul_data.mem @@ -0,0 +1,257 @@ +fcfe0501fd04fdff +0305fffafd0406fa +fafdfefc02f80600 +0206fa02fb0304f8 +00fe0302ff02fdfc +05f9fa03fe0401fe +03fdfefc060106f8 +fb01fc04ff050101 +04fe00050505fcff +fa06f902fcfc0406 +05fd06fdf9fbfdf8 +fd0505fc04030105 +fb0204050605f905 +fbf9fafcf8030000 +05fbfef8020403fd +fbfa06fefff8f902 +04040106fafdfa06 +01fcfa00f8fb05fc +0304fdfc03fafc00 +0202f8f800faf802 +fbfffc01fb02f803 +020503020506f9fe +fefa030402f9ff01 +01fb01fc0405fd05 +f9fb0200fdff0300 +ff06ff02fbfa0602 +03fbf8fa04000405 +fbfa030203ff01fc +faf803f8fff9fffd +fbfcf9030104ffff +fc000204f903fffc +fc0204fa06fffb01 +01fefafef8050106 +fe05f8ff04fd0302 +fffd03fffbfcfefb +fb01fbfc02fd01fd +0203fbfdfcff0500 +04ff00f905fe04fb +06fbff060203fbfc +f901fdfe01f8f804 +fe0404000505f801 +fe00fcf9fbfbfc05 +020501fefafc0500 +0604fe0503050602 +0604f9fa03010600 +fc0603f80506faf9 +03f8fcfcfb040203 +06fd04fefcfa04fc +00fa00f8fafdf805 +06fdf804fb0503fc +fa00fc030302fa06 +01fb00fc0406fdfd +fdfaf801ffff05f8 +fcf902fcfafd00fb +fafdfbfc06020305 +fa04fa05020205fb +06fe040403fdfb03 +f9f8f8fffa01fc04 +fcfffd01f8fdfdfb +fc020606fc0300fa +fe010205fdf800fa +00010300f90106f8 +0101fe030503f8ff +0402fcfa05fefb00 +fd01f8f8fe0504ff +fa01060102fa0501 +f8fdfe0503f805ff +0402fa04fffdf800 +06060504fdfef903 +06fcf8faf9fb0003 +0304f9fafa0502fa +02fefefb0601fc01 +05f90602fcfe0301 +03fffbf8faf8fe01 +05f9fe02fd03fbf8 +04fb02fc00fd05ff +0206fa05fa050102 +01fbff01fa06f804 +f90205fc0206fffb +0301fc01ff060101 +faf8f9fffe06fb01 +fb05fb00fafb06f9 +f8020202fe02fbfa +020505ff0401fcfc +0401fb0606030103 +020104fa03f8fa06 +00f804fefa05fdfb +06fafc00fafc0405 +00fa05fcfff80404 +f806fdfb04fdff01 +02f801f905f80004 +050103fffbf804fe +fc03f903fffcf900 +fcf9fc0106f8ffff +020603fcff03fafd +f9fcfefc05050205 +fe0104fcfdfc0506 +02ff0103fa0203fa +f800fafef9f803f9 +f906fd03fbfa0405 +0502fbfe010205fc +0003f80403050604 +050406fa00f90205 +00fc01010500fb06 +0402fefc0003fffe +fa05fffdfc01f9fc +f806020201f9fd00 +fffcfafbfe000400 +f903fffefdfdfb02 +fd0400f8050102fb +f804fdf8f8fbfdfe +feff0303f80206ff +00fe00fff9fe02fb +fbfbf806fcfe0505 +06fcff06fd0100fd +feffff04f9fa0106 +0000030004030103 +01faff06fffff9fa +0102f9fa0201fafb +fffdfd0003fcf906 +02fdfff8fe06fef8 +f901f905f8fafffc +f8fe06fafdf9f906 +05fafe02fdfffafc +ffff01fc060401fd +fdfe0203fcfd06fa +f901fb06fe05fefa +0605fd0301fffefd +04f8fffafefe00fe +0000fe0002f806fb +fbfc00020505fbf8 +fefa010100f9f904 +fafbfc03fd02f9f9 +05fefdfefc00f9fe +fcfff9f9040400fe +ff01f9fffef8fbfb +0200fbfcf9060204 +fef901fb01030300 +fbf806fffef9faf9 +0505000100040106 +03fa0404fa01f806 +f900f9fff9fffbfa +fbfefffafafc0005 +0403060004f90405 +0302f80205f9f803 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+04030205fcf801f8 +0101010101010101 diff --git a/fpga/vector_matmul_inst.mem b/fpga/vector_matmul_inst.mem new file mode 100644 index 00000000..630ca45f --- /dev/null +++ b/fpga/vector_matmul_inst.mem @@ -0,0 +1,352 @@ +00000093 +00000113 +00000193 +00000213 +00000293 +00000313 +00000393 +00000413 +00000493 +00000513 +00000593 +00000613 +00000693 +00000713 +00000793 +00000813 +00000893 +00000913 +00000993 +00000a13 +00000a93 +00000b13 +00000b93 +00000c13 +00000c93 +00000d13 +00000d93 +00000e13 +00000e93 +00000f13 +00000f93 +00000297 +03828293 +30529073 +00005197 +f7818193 +10000217 +ff720213 +fc027213 +f1402573 +00100593 +00b57063 +00006137 +ff01011b +1d00006f +ef010113 +00113423 +00213823 +00313c23 +02413023 +02513423 +02613823 +02713c23 +04813023 +04913423 +04a13823 +04b13c23 +06c13023 +06d13423 +06e13823 +06f13c23 +09013023 +09113423 +09213823 +09313c23 +0b413023 +0b513423 +0b613823 +0b713c23 +0d813023 +0d913423 +0da13823 +0db13c23 +0fc13023 +0fd13423 +0fe13823 +0ff13c23 +34202573 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+0005c703 +00178793 +00158593 +fee78fa3 +fe0718e3 +00008067 +ff010113 +00004617 +39460613 +00004597 +b8458593 +00004517 +f7c50513 +00113423 +d49ff0ef +c0818e13 +000e0f13 +00000e93 +00004f97 +f60f8f93 +00004317 +f7830313 +02000293 +005e9893 +000f8513 +01f888b3 +000f0813 +c0050713 +00088693 +00000613 +0006c783 +00074583 +02b787bb +00f607bb +0187961b +02070713 +4186561b +00168693 +fea710e3 +00f80023 +00170513 +00180813 +fca312e3 +001e8e93 +020f0f13 +fa5e94e3 +00004617 +31860613 +c2818513 +00100793 +fe060713 +000e0693 +00078a63 +00070783 +00068583 +40b787b3 +0017b793 +00170713 +00168693 +fec712e3 +02070613 +020e0e13 +fca618e3 +00078c63 +00114537 +51450513 +00813083 +01010113 +00008067 +deadc537 +eef50513 +fedff06f +fff00513 +00008067 diff --git a/src/main/resources/applications_for_fpga/build.sh b/src/main/resources/applications_for_fpga/build.sh deleted file mode 100644 index e69de29b..00000000 diff --git a/src/main/resources/applications_fpga/build.sh b/src/main/resources/applications_fpga/build.sh new file mode 100644 index 00000000..1d342c15 --- /dev/null +++ b/src/main/resources/applications_fpga/build.sh @@ -0,0 +1,33 @@ +#!/bin/bash + +riscv64-unknown-elf-gcc -I ./headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o printTo7Seg.riscv ./printTo7Seg/printTo7Seg.c ./headers/syscalls.c ./headers/crt.S -static -nostdlib -nostartfiles -T ./headers/test.ld +riscv64-unknown-elf-objdump --disassemble-all printTo7Seg.riscv > printTo7Seg.dump +riscv64-unknown-elf-objcopy --dump-section .sdata=printTo7Seg_sdata.bin printTo7Seg.riscv +riscv64-unknown-elf-objcopy --dump-section .text.init=printTo7Seg_text_init.bin printTo7Seg.riscv +riscv64-unknown-elf-objcopy --dump-section .text=printTo7Seg_text.bin printTo7Seg.riscv +riscv64-unknown-elf-objcopy --dump-section .text.startup=printTo7Seg_text_startup.bin printTo7Seg.riscv +hexdump -v -e '1/8 "%016x" "\n"' printTo7Seg_sdata.bin > printTo7Seg_sdata.temp +hexdump -v -e '1/4 "%08x" "\n"' printTo7Seg_text_init.bin > printTo7Seg_text_init.temp +hexdump -v -e '1/4 "%08x" "\n"' printTo7Seg_text.bin > printTo7Seg_text.temp +hexdump -v -e '1/4 "%08x" "\n"' printTo7Seg_text_startup.bin > printTo7Seg_text_startup.temp +cat printTo7Seg_sdata.temp > printTo7Seg_data.mem +cat printTo7Seg_text_init.temp printTo7Seg_text.temp printTo7Seg_text_startup.temp > printTo7Seg_inst.mem + +riscv64-unknown-elf-gcc -I ./headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vector_matmul.riscv ./vector_matmul/vector_matmul.c ./headers/syscalls.c ./headers/crt.S -static -nostdlib -nostartfiles -T ./headers/test.ld +riscv64-unknown-elf-objdump --disassemble-all vector_matmul.riscv > vector_matmul.dump +riscv64-unknown-elf-objcopy --dump-section .rodata=vector_matmul_rodata.bin vector_matmul.riscv +riscv64-unknown-elf-objcopy --dump-section .sdata=vector_matmul_sdata.bin vector_matmul.riscv +riscv64-unknown-elf-objcopy --dump-section .text.init=vector_matmul_text_init.bin vector_matmul.riscv +riscv64-unknown-elf-objcopy --dump-section .text=vector_matmul_text.bin vector_matmul.riscv +riscv64-unknown-elf-objcopy --dump-section .text.startup=vector_matmul_text_startup.bin vector_matmul.riscv +#hexdump -v -e '1/8 "%016x" "\n"' vector_matmul_rodata.bin > vector_matmul_rodata.temp +#hexdump -v -e '1/8 "%016x" "\n"' vector_matmul_sdata.bin > vector_matmul_sdata.temp +hexdump -v -e '1/4 "%08x" "\n"' vector_matmul_rodata.bin > vector_matmul_rodata.temp +hexdump -v -e '1/4 "%08x" "\n"' vector_matmul_sdata.bin > vector_matmul_sdata.temp +hexdump -v -e '1/4 "%08x" "\n"' vector_matmul_text_init.bin > vector_matmul_text_init.temp +hexdump -v -e '1/4 "%08x" "\n"' vector_matmul_text.bin > vector_matmul_text.temp +hexdump -v -e '1/4 "%08x" "\n"' vector_matmul_text_startup.bin > vector_matmul_text_startup.temp +cat vector_matmul_rodata.temp vector_matmul_sdata.temp > vector_matmul_data.mem +cat vector_matmul_text_init.temp vector_matmul_text.temp vector_matmul_text_startup.temp > vector_matmul_inst.mem + +rm *.riscv *.bin *.temp \ No newline at end of file diff --git a/src/main/resources/applications_for_fpga/headers/crt.S b/src/main/resources/applications_fpga/headers/crt.S similarity index 100% rename from src/main/resources/applications_for_fpga/headers/crt.S rename to src/main/resources/applications_fpga/headers/crt.S diff --git a/src/main/resources/applications_for_fpga/headers/encoding.h b/src/main/resources/applications_fpga/headers/encoding.h similarity index 100% rename from src/main/resources/applications_for_fpga/headers/encoding.h rename to src/main/resources/applications_fpga/headers/encoding.h diff --git a/src/main/resources/applications_for_fpga/headers/syscalls.c b/src/main/resources/applications_fpga/headers/syscalls.c similarity index 96% rename from src/main/resources/applications_for_fpga/headers/syscalls.c rename to src/main/resources/applications_fpga/headers/syscalls.c index 9c729656..7f781f70 100644 --- a/src/main/resources/applications_for_fpga/headers/syscalls.c +++ b/src/main/resources/applications_fpga/headers/syscalls.c @@ -22,8 +22,8 @@ void clearCounters(void) { } void getCounters(unsigned long* instret, unsigned long* cycle) { - asm volatile("rdinstret %0":"=r" (&instret)); - asm volatile("rdcycle %0":"=r" (&cycle)); + asm volatile("rdinstret %0":"=r" (*instret)); + asm volatile("rdcycle %0":"=r" (*cycle)); return; } diff --git a/src/main/resources/applications_for_fpga/headers/test.ld b/src/main/resources/applications_fpga/headers/test.ld similarity index 100% rename from src/main/resources/applications_for_fpga/headers/test.ld rename to src/main/resources/applications_fpga/headers/test.ld diff --git a/src/main/resources/applications_fpga/printTo7Seg.dump b/src/main/resources/applications_fpga/printTo7Seg.dump new file mode 100644 index 00000000..fcb4518c --- /dev/null +++ b/src/main/resources/applications_fpga/printTo7Seg.dump @@ -0,0 +1,379 @@ + +printTo7Seg.riscv: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000000000000 <_start>: + 0: 00000093 li ra,0 + 4: 00000113 li sp,0 + 8: 00000193 li gp,0 + c: 00000213 li tp,0 + 10: 00000293 li t0,0 + 14: 00000313 li t1,0 + 18: 00000393 li t2,0 + 1c: 00000413 li s0,0 + 20: 00000493 li s1,0 + 24: 00000513 li a0,0 + 28: 00000593 li a1,0 + 2c: 00000613 li a2,0 + 30: 00000693 li a3,0 + 34: 00000713 li a4,0 + 38: 00000793 li a5,0 + 3c: 00000813 li a6,0 + 40: 00000893 li a7,0 + 44: 00000913 li s2,0 + 48: 00000993 li s3,0 + 4c: 00000a13 li s4,0 + 50: 00000a93 li s5,0 + 54: 00000b13 li s6,0 + 58: 00000b93 li s7,0 + 5c: 00000c13 li s8,0 + 60: 00000c93 li s9,0 + 64: 00000d13 li s10,0 + 68: 00000d93 li s11,0 + 6c: 00000e13 li t3,0 + 70: 00000e93 li t4,0 + 74: 00000f13 li t5,0 + 78: 00000f93 li t6,0 + 7c: 00000297 auipc t0,0x0 + 80: 03828293 add t0,t0,56 # b4 + 84: 30529073 csrw mtvec,t0 + 88: 00004197 auipc gp,0x4 + 8c: 77818193 add gp,gp,1912 # 4800 <__global_pointer$> + 90: 10000217 auipc tp,0x10000 + 94: ff720213 add tp,tp,-9 # 10000087 <_end+0x3f> + 98: fc027213 and tp,tp,-64 + 9c: f1402573 csrr a0,mhartid + a0: 00100593 li a1,1 + a4: 00b57063 bgeu a0,a1,a4 <_start+0xa4> + a8: 00006137 lui sp,0x6 + ac: ff01011b addw sp,sp,-16 # 5ff0 <__global_pointer$+0x17f0> + b0: 1740006f j 224 <_init> + +00000000000000b4 : + b4: ef010113 add sp,sp,-272 + b8: 00113423 sd ra,8(sp) + bc: 00213823 sd sp,16(sp) + c0: 00313c23 sd gp,24(sp) + c4: 02413023 sd tp,32(sp) + c8: 02513423 sd t0,40(sp) + cc: 02613823 sd t1,48(sp) + d0: 02713c23 sd t2,56(sp) + d4: 04813023 sd s0,64(sp) + d8: 04913423 sd s1,72(sp) + dc: 04a13823 sd a0,80(sp) + e0: 04b13c23 sd a1,88(sp) + e4: 06c13023 sd a2,96(sp) + e8: 06d13423 sd a3,104(sp) + ec: 06e13823 sd a4,112(sp) + f0: 06f13c23 sd a5,120(sp) + f4: 09013023 sd a6,128(sp) + f8: 09113423 sd a7,136(sp) + fc: 09213823 sd s2,144(sp) + 100: 09313c23 sd s3,152(sp) + 104: 0b413023 sd s4,160(sp) + 108: 0b513423 sd s5,168(sp) + 10c: 0b613823 sd s6,176(sp) + 110: 0b713c23 sd s7,184(sp) + 114: 0d813023 sd s8,192(sp) + 118: 0d913423 sd s9,200(sp) + 11c: 0da13823 sd s10,208(sp) + 120: 0db13c23 sd s11,216(sp) + 124: 0fc13023 sd t3,224(sp) + 128: 0fd13423 sd t4,232(sp) + 12c: 0fe13823 sd t5,240(sp) + 130: 0ff13c23 sd t6,248(sp) + 134: 34202573 csrr a0,mcause + 138: 341025f3 csrr a1,mepc + 13c: 00010613 mv a2,sp + 140: 0c4000ef jal 204 + 144: 34151073 csrw mepc,a0 + 148: 000022b7 lui t0,0x2 + 14c: 8002829b addw t0,t0,-2048 # 1800 + 150: 3002a073 csrs mstatus,t0 + 154: 00813083 ld ra,8(sp) + 158: 01013103 ld sp,16(sp) + 15c: 01813183 ld gp,24(sp) + 160: 02013203 ld tp,32(sp) + 164: 02813283 ld t0,40(sp) + 168: 03013303 ld t1,48(sp) + 16c: 03813383 ld t2,56(sp) + 170: 04013403 ld s0,64(sp) + 174: 04813483 ld s1,72(sp) + 178: 05013503 ld a0,80(sp) + 17c: 05813583 ld a1,88(sp) + 180: 06013603 ld a2,96(sp) + 184: 06813683 ld a3,104(sp) + 188: 07013703 ld a4,112(sp) + 18c: 07813783 ld a5,120(sp) + 190: 08013803 ld a6,128(sp) + 194: 08813883 ld a7,136(sp) + 198: 09013903 ld s2,144(sp) + 19c: 09813983 ld s3,152(sp) + 1a0: 0a013a03 ld s4,160(sp) + 1a4: 0a813a83 ld s5,168(sp) + 1a8: 0b013b03 ld s6,176(sp) + 1ac: 0b813b83 ld s7,184(sp) + 1b0: 0c013c03 ld s8,192(sp) + 1b4: 0c813c83 ld s9,200(sp) + 1b8: 0d013d03 ld s10,208(sp) + 1bc: 0d813d83 ld s11,216(sp) + 1c0: 0e013e03 ld t3,224(sp) + 1c4: 0e813e83 ld t4,232(sp) + 1c8: 0f013f03 ld t5,240(sp) + 1cc: 0f813f83 ld t6,248(sp) + 1d0: 11010113 add sp,sp,272 + 1d4: 30200073 mret + +Disassembly of section .text: + +00000000000001d8 : + 1d8: b0201073 csrw minstret,zero + 1dc: b0001073 csrw mcycle,zero + 1e0: 00008067 ret + +00000000000001e4 : + 1e4: c02027f3 rdinstret a5 + 1e8: 00f53023 sd a5,0(a0) + 1ec: c00027f3 rdcycle a5 + 1f0: 00f5b023 sd a5,0(a1) + 1f4: 00008067 ret + +00000000000001f8 : + 1f8: 100007b7 lui a5,0x10000 + 1fc: 00a7a023 sw a0,0(a5) # 10000000 + 200: 0000006f j 200 + +0000000000000204 : + 204: 0105959b sllw a1,a1,0x10 + 208: 00b567b3 or a5,a0,a1 + 20c: 0007879b sext.w a5,a5 + 210: 10000737 lui a4,0x10000 + 214: 00f72023 sw a5,0(a4) # 10000000 + 218: 0000006f j 218 + +000000000000021c : + 21c: 00051063 bnez a0,21c + 220: 00008067 ret + +0000000000000224 <_init>: + 224: ff010113 add sp,sp,-16 + 228: 00000593 li a1,0 + 22c: 00000513 li a0,0 + 230: 00113423 sd ra,8(sp) + 234: 1e0000ef jal 414
+ 238: 100007b7 lui a5,0x10000 + 23c: 00a7a023 sw a0,0(a5) # 10000000 + 240: 0000006f j 240 <_init+0x1c> + +0000000000000244 : + 244: 00b567b3 or a5,a0,a1 + 248: 00c7e7b3 or a5,a5,a2 + 24c: 0077f793 and a5,a5,7 + 250: 00c50833 add a6,a0,a2 + 254: 02078463 beqz a5,27c + 258: 00c58633 add a2,a1,a2 + 25c: 00050793 mv a5,a0 + 260: 0b057663 bgeu a0,a6,30c + 264: 0005c703 lbu a4,0(a1) + 268: 00158593 add a1,a1,1 + 26c: 00178793 add a5,a5,1 + 270: fee78fa3 sb a4,-1(a5) + 274: fec598e3 bne a1,a2,264 + 278: 00008067 ret + 27c: 04050693 add a3,a0,64 + 280: 0906f863 bgeu a3,a6,310 + 284: 00058713 mv a4,a1 + 288: 00068793 mv a5,a3 + 28c: 00073383 ld t2,0(a4) + 290: 00873283 ld t0,8(a4) + 294: 01073f83 ld t6,16(a4) + 298: 01873f03 ld t5,24(a4) + 29c: 02073e83 ld t4,32(a4) + 2a0: 02873e03 ld t3,40(a4) + 2a4: 03073303 ld t1,48(a4) + 2a8: 03873883 ld a7,56(a4) + 2ac: 04078793 add a5,a5,64 + 2b0: f877b023 sd t2,-128(a5) + 2b4: f857b423 sd t0,-120(a5) + 2b8: f9f7b823 sd t6,-112(a5) + 2bc: f9e7bc23 sd t5,-104(a5) + 2c0: fbd7b023 sd t4,-96(a5) + 2c4: fbc7b423 sd t3,-88(a5) + 2c8: fa67b823 sd t1,-80(a5) + 2cc: fb17bc23 sd a7,-72(a5) + 2d0: 04070713 add a4,a4,64 + 2d4: fb07ece3 bltu a5,a6,28c + 2d8: fbf60613 add a2,a2,-65 + 2dc: fc067793 and a5,a2,-64 + 2e0: 04078793 add a5,a5,64 + 2e4: fc067613 and a2,a2,-64 + 2e8: 00f585b3 add a1,a1,a5 + 2ec: 00c687b3 add a5,a3,a2 + 2f0: f907f4e3 bgeu a5,a6,278 + 2f4: 0005b703 ld a4,0(a1) + 2f8: 00878793 add a5,a5,8 + 2fc: 00858593 add a1,a1,8 + 300: fee7bc23 sd a4,-8(a5) + 304: ff07e8e3 bltu a5,a6,2f4 + 308: 00008067 ret + 30c: 00008067 ret + 310: 00050793 mv a5,a0 + 314: fddff06f j 2f0 + +0000000000000318 : + 318: 00c567b3 or a5,a0,a2 + 31c: 0077f793 and a5,a5,7 + 320: 00c50633 add a2,a0,a2 + 324: 0ff5f713 zext.b a4,a1 + 328: 00078e63 beqz a5,344 + 32c: 00050793 mv a5,a0 + 330: 02c57c63 bgeu a0,a2,368 + 334: 00178793 add a5,a5,1 + 338: fee78fa3 sb a4,-1(a5) + 33c: fef61ce3 bne a2,a5,334 + 340: 00008067 ret + 344: 00004797 auipc a5,0x4 + 348: cbc7b783 ld a5,-836(a5) # 4000 + 34c: 02f70733 mul a4,a4,a5 + 350: fec578e3 bgeu a0,a2,340 + 354: 00050793 mv a5,a0 + 358: 00878793 add a5,a5,8 + 35c: fee7bc23 sd a4,-8(a5) + 360: fec7ece3 bltu a5,a2,358 + 364: 00008067 ret + 368: 00008067 ret + +000000000000036c : + 36c: 00054783 lbu a5,0(a0) + 370: 00078e63 beqz a5,38c + 374: 00050793 mv a5,a0 + 378: 0017c703 lbu a4,1(a5) + 37c: 00178793 add a5,a5,1 + 380: fe071ce3 bnez a4,378 + 384: 40a78533 sub a0,a5,a0 + 388: 00008067 ret + 38c: 00000513 li a0,0 + 390: 00008067 ret + +0000000000000394 : + 394: 00b506b3 add a3,a0,a1 + 398: 00050793 mv a5,a0 + 39c: 00059863 bnez a1,3ac + 3a0: 0240006f j 3c4 + 3a4: 00178793 add a5,a5,1 + 3a8: 00f68a63 beq a3,a5,3bc + 3ac: 0007c703 lbu a4,0(a5) + 3b0: fe071ae3 bnez a4,3a4 + 3b4: 40a78533 sub a0,a5,a0 + 3b8: 00008067 ret + 3bc: 40a68533 sub a0,a3,a0 + 3c0: 00008067 ret + 3c4: 00000513 li a0,0 + 3c8: 00008067 ret + +00000000000003cc : + 3cc: 00054783 lbu a5,0(a0) + 3d0: 00158593 add a1,a1,1 + 3d4: 00150513 add a0,a0,1 + 3d8: fff5c703 lbu a4,-1(a1) + 3dc: 00078a63 beqz a5,3f0 + 3e0: fee786e3 beq a5,a4,3cc + 3e4: 0007851b sext.w a0,a5 + 3e8: 40e5053b subw a0,a0,a4 + 3ec: 00008067 ret + 3f0: 00000513 li a0,0 + 3f4: ff5ff06f j 3e8 + +00000000000003f8 : + 3f8: 00050793 mv a5,a0 + 3fc: 0005c703 lbu a4,0(a1) + 400: 00178793 add a5,a5,1 + 404: 00158593 add a1,a1,1 + 408: fee78fa3 sb a4,-1(a5) + 40c: fe0718e3 bnez a4,3fc + 410: 00008067 ret + +Disassembly of section .text.startup: + +0000000000000414
: + 414: 07214537 lui a0,0x7214 + 418: 54550513 add a0,a0,1349 # 7214545 <__global_pointer$+0x720fd45> + 41c: 00008067 ret + 420: fff00513 li a0,-1 + 424: 00008067 ret + +Disassembly of section .sdata: + +0000000000004000 <__global_pointer$-0x800>: + 4000: 0101 vmsge.vx v2,v0,zero,v0.t + 4002: 0101 vmsge.vx v2,v0,zero,v0.t + 4004: 0101 vmsge.vx v2,v0,zero,v0.t + 4006: 0101 vmsge.vx v2,v0,zero,v0.t + +Disassembly of section .tohost: + +0000000010000000 : + ... + +0000000010000040 : + ... + +Disassembly of section .comment: + +0000000000000000 <.comment>: + 0: 3a434347 .4byte 0x3a434347 + 4: 2820 vmsge.vx v16,v0,zero,v0.t + 6: 65653267 .4byte 0x65653267 + a: 6535 .2byte 0x6535 + c: 3334 .2byte 0x3334 + e: 3030 .2byte 0x3030 + 10: 3831 .2byte 0x3831 + 12: 2029 .2byte 0x2029 + 14: 3231 .2byte 0x3231 + 16: 322e .2byte 0x322e + 18: 302e .2byte 0x302e + ... + +Disassembly of section .riscv.attributes: + +0000000000000000 <.riscv.attributes>: + 0: 5e41 vmsge.vx v28,v0,zero,v0.t + 2: 0000 vmsge.vx v0,v0,zero,v0.t + 4: 7200 vmsge.vx v4,v0,zero,v0.t + 6: 7369 .2byte 0x7369 + 8: 01007663 bgeu zero,a6,14 <_start+0x14> + c: 0054 .2byte 0x54 + e: 0000 vmsge.vx v0,v0,zero,v0.t + 10: 1004 .2byte 0x1004 + 12: 7205 .2byte 0x7205 + 14: 3676 .2byte 0x3676 + 16: 6934 .2byte 0x6934 + 18: 7032 .2byte 0x7032 + 1a: 5f31 .2byte 0x5f31 + 1c: 326d .2byte 0x326d + 1e: 3070 .2byte 0x3070 + 20: 7a5f 6369 7273 .byte 0x5f, 0x7a, 0x69, 0x63, 0x73, 0x72 + 26: 7032 .2byte 0x7032 + 28: 5f30 .2byte 0x5f30 + 2a: 6d7a .2byte 0x6d7a + 2c: 756d .2byte 0x756d + 2e: 316c .2byte 0x316c + 30: 3070 .2byte 0x3070 + 32: 7a5f 6576 3233 .byte 0x5f, 0x7a, 0x76, 0x65, 0x33, 0x32 + 38: 3178 .2byte 0x3178 + 3a: 3070 .2byte 0x3070 + 3c: 7a5f 6576 3436 .byte 0x5f, 0x7a, 0x76, 0x65, 0x36, 0x34 + 42: 3178 .2byte 0x3178 + 44: 3070 .2byte 0x3070 + 46: 7a5f 6c76 3233 .byte 0x5f, 0x7a, 0x76, 0x6c, 0x33, 0x32 + 4c: 3162 vmsge.vx v2,v0,zero,v0.t + 4e: 3070 .2byte 0x3070 + 50: 7a5f 6c76 3436 .byte 0x5f, 0x7a, 0x76, 0x6c, 0x36, 0x34 + 56: 3162 vmsge.vx v2,v0,zero,v0.t + 58: 3070 .2byte 0x3070 + 5a: 0800 vmsge.vx v16,v0,zero,v0.t + 5c: 0a01 vmsge.vx v20,v0,zero,v0.t + 5e: 0b Address 0x5e is out of bounds. + diff --git a/src/main/resources/applications_fpga/printTo7Seg/printTo7Seg.c b/src/main/resources/applications_fpga/printTo7Seg/printTo7Seg.c new file mode 100644 index 00000000..2c8471f3 --- /dev/null +++ b/src/main/resources/applications_fpga/printTo7Seg/printTo7Seg.c @@ -0,0 +1,3 @@ +int main(int argc, char** argv) { + return 0x07214545; +} \ No newline at end of file diff --git a/src/main/resources/applications_fpga/printTo7Seg_data.mem b/src/main/resources/applications_fpga/printTo7Seg_data.mem new file mode 100644 index 00000000..a0e0c83a --- /dev/null +++ b/src/main/resources/applications_fpga/printTo7Seg_data.mem @@ -0,0 +1 @@ +0101010101010101 diff --git a/src/main/resources/applications_fpga/printTo7Seg_inst.mem b/src/main/resources/applications_fpga/printTo7Seg_inst.mem new file mode 100644 index 00000000..e0f91ad2 --- /dev/null +++ b/src/main/resources/applications_fpga/printTo7Seg_inst.mem @@ -0,0 +1,266 @@ +00000093 +00000113 +00000193 +00000213 +00000293 +00000313 +00000393 +00000413 +00000493 +00000513 +00000593 +00000613 +00000693 +00000713 +00000793 +00000813 +00000893 +00000913 +00000993 +00000a13 +00000a93 +00000b13 +00000b93 +00000c13 +00000c93 +00000d13 +00000d93 +00000e13 +00000e93 +00000f13 +00000f93 +00000297 +03828293 +30529073 +00004197 +77818193 +10000217 +ff720213 +fc027213 +f1402573 +00100593 +00b57063 +00006137 +ff01011b +1740006f +ef010113 +00113423 +00213823 +00313c23 +02413023 +02513423 +02613823 +02713c23 +04813023 +04913423 +04a13823 +04b13c23 +06c13023 +06d13423 +06e13823 +06f13c23 +09013023 +09113423 +09213823 +09313c23 +0b413023 +0b513423 +0b613823 +0b713c23 +0d813023 +0d913423 +0da13823 +0db13c23 +0fc13023 +0fd13423 +0fe13823 +0ff13c23 +34202573 +341025f3 +00010613 +0c4000ef +34151073 +000022b7 +8002829b +3002a073 +00813083 +01013103 +01813183 +02013203 +02813283 +03013303 +03813383 +04013403 +04813483 +05013503 +05813583 +06013603 +06813683 +07013703 +07813783 +08013803 +08813883 +09013903 +09813983 +0a013a03 +0a813a83 +0b013b03 +0b813b83 +0c013c03 +0c813c83 +0d013d03 +0d813d83 +0e013e03 +0e813e83 +0f013f03 +0f813f83 +11010113 +30200073 +b0201073 +b0001073 +00008067 +c02027f3 +00f53023 +c00027f3 +00f5b023 +00008067 +100007b7 +00a7a023 +0000006f +0105959b +00b567b3 +0007879b +10000737 +00f72023 +0000006f +00051063 +00008067 +ff010113 +00000593 +00000513 +00113423 +1e0000ef +100007b7 +00a7a023 +0000006f +00b567b3 +00c7e7b3 +0077f793 +00c50833 +02078463 +00c58633 +00050793 +0b057663 +0005c703 +00158593 +00178793 +fee78fa3 +fec598e3 +00008067 +04050693 +0906f863 +00058713 +00068793 +00073383 +00873283 +01073f83 +01873f03 +02073e83 +02873e03 +03073303 +03873883 +04078793 +f877b023 +f857b423 +f9f7b823 +f9e7bc23 +fbd7b023 +fbc7b423 +fa67b823 +fb17bc23 +04070713 +fb07ece3 +fbf60613 +fc067793 +04078793 +fc067613 +00f585b3 +00c687b3 +f907f4e3 +0005b703 +00878793 +00858593 +fee7bc23 +ff07e8e3 +00008067 +00008067 +00050793 +fddff06f +00c567b3 +0077f793 +00c50633 +0ff5f713 +00078e63 +00050793 +02c57c63 +00178793 +fee78fa3 +fef61ce3 +00008067 +00004797 +cbc7b783 +02f70733 +fec578e3 +00050793 +00878793 +fee7bc23 +fec7ece3 +00008067 +00008067 +00054783 +00078e63 +00050793 +0017c703 +00178793 +fe071ce3 +40a78533 +00008067 +00000513 +00008067 +00b506b3 +00050793 +00059863 +0240006f +00178793 +00f68a63 +0007c703 +fe071ae3 +40a78533 +00008067 +40a68533 +00008067 +00000513 +00008067 +00054783 +00158593 +00150513 +fff5c703 +00078a63 +fee786e3 +0007851b +40e5053b +00008067 +00000513 +ff5ff06f +00050793 +0005c703 +00178793 +00158593 +fee78fa3 +fe0718e3 +00008067 +07214537 +54550513 +00008067 +fff00513 +00008067 diff --git a/src/main/resources/applications_fpga/vector_matmul.dump b/src/main/resources/applications_fpga/vector_matmul.dump new file mode 100644 index 00000000..fa4987f8 --- /dev/null +++ b/src/main/resources/applications_fpga/vector_matmul.dump @@ -0,0 +1,1339 @@ + +vector_matmul.riscv: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000000000000 <_start>: + 0: 00000093 li ra,0 + 4: 00000113 li sp,0 + 8: 00000193 li gp,0 + c: 00000213 li tp,0 + 10: 00000293 li t0,0 + 14: 00000313 li t1,0 + 18: 00000393 li t2,0 + 1c: 00000413 li s0,0 + 20: 00000493 li s1,0 + 24: 00000513 li a0,0 + 28: 00000593 li a1,0 + 2c: 00000613 li a2,0 + 30: 00000693 li a3,0 + 34: 00000713 li a4,0 + 38: 00000793 li a5,0 + 3c: 00000813 li a6,0 + 40: 00000893 li a7,0 + 44: 00000913 li s2,0 + 48: 00000993 li s3,0 + 4c: 00000a13 li s4,0 + 50: 00000a93 li s5,0 + 54: 00000b13 li s6,0 + 58: 00000b93 li s7,0 + 5c: 00000c13 li s8,0 + 60: 00000c93 li s9,0 + 64: 00000d13 li s10,0 + 68: 00000d93 li s11,0 + 6c: 00000e13 li t3,0 + 70: 00000e93 li t4,0 + 74: 00000f13 li t5,0 + 78: 00000f93 li t6,0 + 7c: 00000297 auipc t0,0x0 + 80: 03828293 add t0,t0,56 # b4 + 84: 30529073 csrw mtvec,t0 + 88: 00005197 auipc gp,0x5 + 8c: f7818193 add gp,gp,-136 # 5000 <__global_pointer$> + 90: 10000217 auipc tp,0x10000 + 94: ff720213 add tp,tp,-9 # 10000087 <_end+0x3f> + 98: fc027213 and tp,tp,-64 + 9c: f1402573 csrr a0,mhartid + a0: 00100593 li a1,1 + a4: 00b57063 bgeu a0,a1,a4 <_start+0xa4> + a8: 00006137 lui sp,0x6 + ac: ff01011b addw sp,sp,-16 # 5ff0 <_tbss_end+0xfe8> + b0: 1d00006f j 280 <_init> + +00000000000000b4 : + b4: ef010113 add sp,sp,-272 + b8: 00113423 sd ra,8(sp) + bc: 00213823 sd sp,16(sp) + c0: 00313c23 sd gp,24(sp) + c4: 02413023 sd tp,32(sp) + c8: 02513423 sd t0,40(sp) + cc: 02613823 sd t1,48(sp) + d0: 02713c23 sd t2,56(sp) + d4: 04813023 sd s0,64(sp) + d8: 04913423 sd s1,72(sp) + dc: 04a13823 sd a0,80(sp) + e0: 04b13c23 sd a1,88(sp) + e4: 06c13023 sd a2,96(sp) + e8: 06d13423 sd a3,104(sp) + ec: 06e13823 sd a4,112(sp) + f0: 06f13c23 sd a5,120(sp) + f4: 09013023 sd a6,128(sp) + f8: 09113423 sd a7,136(sp) + fc: 09213823 sd s2,144(sp) + 100: 09313c23 sd s3,152(sp) + 104: 0b413023 sd s4,160(sp) + 108: 0b513423 sd s5,168(sp) + 10c: 0b613823 sd s6,176(sp) + 110: 0b713c23 sd s7,184(sp) + 114: 0d813023 sd s8,192(sp) + 118: 0d913423 sd s9,200(sp) + 11c: 0da13823 sd s10,208(sp) + 120: 0db13c23 sd s11,216(sp) + 124: 0fc13023 sd t3,224(sp) + 128: 0fd13423 sd t4,232(sp) + 12c: 0fe13823 sd t5,240(sp) + 130: 0ff13c23 sd t6,248(sp) + 134: 34202573 csrr a0,mcause + 138: 341025f3 csrr a1,mepc + 13c: 00010613 mv a2,sp + 140: 120000ef jal 260 + 144: 34151073 csrw mepc,a0 + 148: 000022b7 lui t0,0x2 + 14c: 8002829b addw t0,t0,-2048 # 1800 + 150: 3002a073 csrs mstatus,t0 + 154: 00813083 ld ra,8(sp) + 158: 01013103 ld sp,16(sp) + 15c: 01813183 ld gp,24(sp) + 160: 02013203 ld tp,32(sp) + 164: 02813283 ld t0,40(sp) + 168: 03013303 ld t1,48(sp) + 16c: 03813383 ld t2,56(sp) + 170: 04013403 ld s0,64(sp) + 174: 04813483 ld s1,72(sp) + 178: 05013503 ld a0,80(sp) + 17c: 05813583 ld a1,88(sp) + 180: 06013603 ld a2,96(sp) + 184: 06813683 ld a3,104(sp) + 188: 07013703 ld a4,112(sp) + 18c: 07813783 ld a5,120(sp) + 190: 08013803 ld a6,128(sp) + 194: 08813883 ld a7,136(sp) + 198: 09013903 ld s2,144(sp) + 19c: 09813983 ld s3,152(sp) + 1a0: 0a013a03 ld s4,160(sp) + 1a4: 0a813a83 ld s5,168(sp) + 1a8: 0b013b03 ld s6,176(sp) + 1ac: 0b813b83 ld s7,184(sp) + 1b0: 0c013c03 ld s8,192(sp) + 1b4: 0c813c83 ld s9,200(sp) + 1b8: 0d013d03 ld s10,208(sp) + 1bc: 0d813d83 ld s11,216(sp) + 1c0: 0e013e03 ld t3,224(sp) + 1c4: 0e813e83 ld t4,232(sp) + 1c8: 0f013f03 ld t5,240(sp) + 1cc: 0f813f83 ld t6,248(sp) + 1d0: 11010113 add sp,sp,272 + 1d4: 30200073 mret + +Disassembly of section .text: + +00000000000001d8 <_e8_32x32_matmul>: + 1d8: 02000793 li a5,32 + 1dc: 0c07f057 vsetvli zero,a5,e8,m1,ta,ma + 1e0: 02000813 li a6,32 + 1e4: 00050893 mv a7,a0 + 1e8: 40050313 add t1,a0,1024 + 1ec: 02000513 li a0,32 + 1f0: 02088087 vle8.v v1,(a7) + 1f4: 42006257 vmv.s.x v4,zero + 1f8: 00000793 li a5,0 + 1fc: 00f58733 add a4,a1,a5 + 200: 0b070107 vlse8.v v2,(a4),a6 + 204: 961121d7 vmul.vv v3,v1,v2 + 208: 023221d7 vredsum.vs v3,v3,v4 + 20c: 423026d7 vmv.x.s a3,v3 + 210: 0007871b sext.w a4,a5 + 214: 00e60733 add a4,a2,a4 + 218: 00d70023 sb a3,0(a4) + 21c: 00178793 add a5,a5,1 + 220: fca79ee3 bne a5,a0,1fc <_e8_32x32_matmul+0x24> + 224: 02088893 add a7,a7,32 + 228: 02060613 add a2,a2,32 + 22c: fc6892e3 bne a7,t1,1f0 <_e8_32x32_matmul+0x18> + 230: 00008067 ret + +0000000000000234 : + 234: b0201073 csrw minstret,zero + 238: b0001073 csrw mcycle,zero + 23c: 00008067 ret + +0000000000000240 : + 240: c02027f3 rdinstret a5 + 244: 00f53023 sd a5,0(a0) + 248: c00027f3 rdcycle a5 + 24c: 00f5b023 sd a5,0(a1) + 250: 00008067 ret + +0000000000000254 : + 254: 100007b7 lui a5,0x10000 + 258: 00a7a023 sw a0,0(a5) # 10000000 + 25c: 0000006f j 25c + +0000000000000260 : + 260: 0105959b sllw a1,a1,0x10 + 264: 00b567b3 or a5,a0,a1 + 268: 0007879b sext.w a5,a5 + 26c: 10000737 lui a4,0x10000 + 270: 00f72023 sw a5,0(a4) # 10000000 + 274: 0000006f j 274 + +0000000000000278 : + 278: 00051063 bnez a0,278 + 27c: 00008067 ret + +0000000000000280 <_init>: + 280: ff010113 add sp,sp,-16 + 284: 00000593 li a1,0 + 288: 00000513 li a0,0 + 28c: 00113423 sd ra,8(sp) + 290: 1e0000ef jal 470
+ 294: 100007b7 lui a5,0x10000 + 298: 00a7a023 sw a0,0(a5) # 10000000 + 29c: 0000006f j 29c <_init+0x1c> + +00000000000002a0 : + 2a0: 00b567b3 or a5,a0,a1 + 2a4: 00c7e7b3 or a5,a5,a2 + 2a8: 0077f793 and a5,a5,7 + 2ac: 00c50833 add a6,a0,a2 + 2b0: 02078463 beqz a5,2d8 + 2b4: 00c58633 add a2,a1,a2 + 2b8: 00050793 mv a5,a0 + 2bc: 0b057663 bgeu a0,a6,368 + 2c0: 0005c703 lbu a4,0(a1) + 2c4: 00158593 add a1,a1,1 + 2c8: 00178793 add a5,a5,1 + 2cc: fee78fa3 sb a4,-1(a5) + 2d0: fec598e3 bne a1,a2,2c0 + 2d4: 00008067 ret + 2d8: 04050693 add a3,a0,64 + 2dc: 0906f863 bgeu a3,a6,36c + 2e0: 00058713 mv a4,a1 + 2e4: 00068793 mv a5,a3 + 2e8: 00073383 ld t2,0(a4) + 2ec: 00873283 ld t0,8(a4) + 2f0: 01073f83 ld t6,16(a4) + 2f4: 01873f03 ld t5,24(a4) + 2f8: 02073e83 ld t4,32(a4) + 2fc: 02873e03 ld t3,40(a4) + 300: 03073303 ld t1,48(a4) + 304: 03873883 ld a7,56(a4) + 308: 04078793 add a5,a5,64 + 30c: f877b023 sd t2,-128(a5) + 310: f857b423 sd t0,-120(a5) + 314: f9f7b823 sd t6,-112(a5) + 318: f9e7bc23 sd t5,-104(a5) + 31c: fbd7b023 sd t4,-96(a5) + 320: fbc7b423 sd t3,-88(a5) + 324: fa67b823 sd t1,-80(a5) + 328: fb17bc23 sd a7,-72(a5) + 32c: 04070713 add a4,a4,64 + 330: fb07ece3 bltu a5,a6,2e8 + 334: fbf60613 add a2,a2,-65 + 338: fc067793 and a5,a2,-64 + 33c: 04078793 add a5,a5,64 + 340: fc067613 and a2,a2,-64 + 344: 00f585b3 add a1,a1,a5 + 348: 00c687b3 add a5,a3,a2 + 34c: f907f4e3 bgeu a5,a6,2d4 + 350: 0005b703 ld a4,0(a1) + 354: 00878793 add a5,a5,8 + 358: 00858593 add a1,a1,8 + 35c: fee7bc23 sd a4,-8(a5) + 360: ff07e8e3 bltu a5,a6,350 + 364: 00008067 ret + 368: 00008067 ret + 36c: 00050793 mv a5,a0 + 370: fddff06f j 34c + +0000000000000374 : + 374: 00c567b3 or a5,a0,a2 + 378: 0077f793 and a5,a5,7 + 37c: 00c50633 add a2,a0,a2 + 380: 0ff5f713 zext.b a4,a1 + 384: 00078e63 beqz a5,3a0 + 388: 00050793 mv a5,a0 + 38c: 02c57c63 bgeu a0,a2,3c4 + 390: 00178793 add a5,a5,1 + 394: fee78fa3 sb a4,-1(a5) + 398: fef61ce3 bne a2,a5,390 + 39c: 00008067 ret + 3a0: 00004797 auipc a5,0x4 + 3a4: 4607b783 ld a5,1120(a5) # 4800 + 3a8: 02f70733 mul a4,a4,a5 + 3ac: fec578e3 bgeu a0,a2,39c + 3b0: 00050793 mv a5,a0 + 3b4: 00878793 add a5,a5,8 + 3b8: fee7bc23 sd a4,-8(a5) + 3bc: fec7ece3 bltu a5,a2,3b4 + 3c0: 00008067 ret + 3c4: 00008067 ret + +00000000000003c8 : + 3c8: 00054783 lbu a5,0(a0) + 3cc: 00078e63 beqz a5,3e8 + 3d0: 00050793 mv a5,a0 + 3d4: 0017c703 lbu a4,1(a5) + 3d8: 00178793 add a5,a5,1 + 3dc: fe071ce3 bnez a4,3d4 + 3e0: 40a78533 sub a0,a5,a0 + 3e4: 00008067 ret + 3e8: 00000513 li a0,0 + 3ec: 00008067 ret + +00000000000003f0 : + 3f0: 00b506b3 add a3,a0,a1 + 3f4: 00050793 mv a5,a0 + 3f8: 00059863 bnez a1,408 + 3fc: 0240006f j 420 + 400: 00178793 add a5,a5,1 + 404: 00f68a63 beq a3,a5,418 + 408: 0007c703 lbu a4,0(a5) + 40c: fe071ae3 bnez a4,400 + 410: 40a78533 sub a0,a5,a0 + 414: 00008067 ret + 418: 40a68533 sub a0,a3,a0 + 41c: 00008067 ret + 420: 00000513 li a0,0 + 424: 00008067 ret + +0000000000000428 : + 428: 00054783 lbu a5,0(a0) + 42c: 00158593 add a1,a1,1 + 430: 00150513 add a0,a0,1 + 434: fff5c703 lbu a4,-1(a1) + 438: 00078a63 beqz a5,44c + 43c: fee786e3 beq a5,a4,428 + 440: 0007851b sext.w a0,a5 + 444: 40e5053b subw a0,a0,a4 + 448: 00008067 ret + 44c: 00000513 li a0,0 + 450: ff5ff06f j 444 + +0000000000000454 : + 454: 00050793 mv a5,a0 + 458: 0005c703 lbu a4,0(a1) + 45c: 00178793 add a5,a5,1 + 460: 00158593 add a1,a1,1 + 464: fee78fa3 sb a4,-1(a5) + 468: fe0718e3 bnez a4,458 + 46c: 00008067 ret + +Disassembly of section .text.startup: + +0000000000000470
: + 470: ff010113 add sp,sp,-16 + 474: 00004617 auipc a2,0x4 + 478: 39460613 add a2,a2,916 # 4808 + 47c: 00004597 auipc a1,0x4 + 480: b8458593 add a1,a1,-1148 # 4000 + 484: 00004517 auipc a0,0x4 + 488: f7c50513 add a0,a0,-132 # 4400 + 48c: 00113423 sd ra,8(sp) + 490: d49ff0ef jal 1d8 <_e8_32x32_matmul> + 494: c0818e13 add t3,gp,-1016 # 4c08 + 498: 000e0f13 mv t5,t3 + 49c: 00000e93 li t4,0 + 4a0: 00004f97 auipc t6,0x4 + 4a4: f60f8f93 add t6,t6,-160 # 4400 + 4a8: 00004317 auipc t1,0x4 + 4ac: f7830313 add t1,t1,-136 # 4420 + 4b0: 02000293 li t0,32 + 4b4: 005e9893 sll a7,t4,0x5 + 4b8: 000f8513 mv a0,t6 + 4bc: 01f888b3 add a7,a7,t6 + 4c0: 000f0813 mv a6,t5 + 4c4: c0050713 add a4,a0,-1024 + 4c8: 00088693 mv a3,a7 + 4cc: 00000613 li a2,0 + 4d0: 0006c783 lbu a5,0(a3) + 4d4: 00074583 lbu a1,0(a4) + 4d8: 02b787bb mulw a5,a5,a1 + 4dc: 00f607bb addw a5,a2,a5 + 4e0: 0187961b sllw a2,a5,0x18 + 4e4: 02070713 add a4,a4,32 + 4e8: 4186561b sraw a2,a2,0x18 + 4ec: 00168693 add a3,a3,1 + 4f0: fea710e3 bne a4,a0,4d0 + 4f4: 00f80023 sb a5,0(a6) + 4f8: 00170513 add a0,a4,1 + 4fc: 00180813 add a6,a6,1 + 500: fca312e3 bne t1,a0,4c4 + 504: 001e8e93 add t4,t4,1 + 508: 020f0f13 add t5,t5,32 + 50c: fa5e94e3 bne t4,t0,4b4 + 510: 00004617 auipc a2,0x4 + 514: 31860613 add a2,a2,792 # 4828 + 518: c2818513 add a0,gp,-984 # 4c28 + 51c: 00100793 li a5,1 + 520: fe060713 add a4,a2,-32 + 524: 000e0693 mv a3,t3 + 528: 00078a63 beqz a5,53c + 52c: 00070783 lb a5,0(a4) + 530: 00068583 lb a1,0(a3) + 534: 40b787b3 sub a5,a5,a1 + 538: 0017b793 seqz a5,a5 + 53c: 00170713 add a4,a4,1 + 540: 00168693 add a3,a3,1 + 544: fec712e3 bne a4,a2,528 + 548: 02070613 add a2,a4,32 + 54c: 020e0e13 add t3,t3,32 + 550: fca618e3 bne a2,a0,520 + 554: 00078c63 beqz a5,56c + 558: 00114537 lui a0,0x114 + 55c: 51450513 add a0,a0,1300 # 114514 <_tbss_end+0x10f50c> + 560: 00813083 ld ra,8(sp) + 564: 01010113 add sp,sp,16 + 568: 00008067 ret + 56c: deadc537 lui a0,0xdeadc + 570: eef50513 add a0,a0,-273 # ffffffffdeadbeef <_end+0xffffffffceadbea7> + 574: fedff06f j 560 + 578: fff00513 li a0,-1 + 57c: 00008067 ret + +Disassembly of section .rodata: + +0000000000004000 : + 4000: fdff .2byte 0xfdff + 4002: fd04 .2byte 0xfd04 + 4004: 0501 vmsge.vx v10,v0,zero,v0.t + 4006: fcfe .2byte 0xfcfe + 4008: 06fa .2byte 0x6fa + 400a: fd04 .2byte 0xfd04 + 400c: fffa .2byte 0xfffa + 400e: 0305 .2byte 0x305 + 4010: 0600 vmsge.vx v12,v0,zero,v0.t + 4012: 02f8 .2byte 0x2f8 + 4014: fefc .2byte 0xfefc + 4016: fafd .2byte 0xfafd + 4018: 04f8 .2byte 0x4f8 + 401a: fa02fb03 vmsge.vx v22,v0,t0 + 401e: 0206 .2byte 0x206 + 4020: fdfc .2byte 0xfdfc + 4022: ff02 vmsge.vx v30,v0,ra,v0.t + 4024: 0302 vmsge.vx v6,v0,zero,v0.t + 4026: 00fe .2byte 0xfe + 4028: 01fe .2byte 0x1fe + 402a: fe04 .2byte 0xfe04 + 402c: 05f9fa03 vmsge.vx v20,v31,s3,v0.t + 4030: 06f8 .2byte 0x6f8 + 4032: 0601 vmsge.vx v12,v0,zero,v0.t + 4034: fefc .2byte 0xfefc + 4036: 03fd .2byte 0x3fd + 4038: 0101 vmsge.vx v2,v0,zero,v0.t + 403a: ff05 .2byte 0xff05 + 403c: fc04 .2byte 0xfc04 + 403e: fb01 vmsge.vx v22,v0,ra,v0.t + 4040: fcff .2byte 0xfcff + 4042: 0505 .2byte 0x505 + 4044: 0005 .2byte 0x5 + 4046: 04fe .2byte 0x4fe + 4048: 0406 .2byte 0x406 + 404a: fcfc .2byte 0xfcfc + 404c: f902 vmsge.vx v18,v0,ra,v0.t + 404e: fa06 .2byte 0xfa06 + 4050: fdf8 .2byte 0xfdf8 + 4052: 06fdf9fb .4byte 0x6fdf9fb + 4056: 05fd .2byte 0x5fd + 4058: 0105 .2byte 0x105 + 405a: 05fc0403 lb s0,95(s8) + 405e: fd05 .2byte 0xfd05 + 4060: f905 .2byte 0xf905 + 4062: 0605 .2byte 0x605 + 4064: 0405 .2byte 0x405 + 4066: fb02 vmsge.vx v22,v0,ra,v0.t + 4068: 0000 vmsge.vx v0,v0,zero,v0.t + 406a: fafcf803 vmsge.vx v16,v15,s9 + 406e: fbf9 .2byte 0xfbf9 + 4070: 03fd .2byte 0x3fd + 4072: 0204 .2byte 0x204 + 4074: fef8 .2byte 0xfef8 + 4076: f90205fb .4byte 0xf90205fb + 407a: fff8 .2byte 0xfff8 + 407c: 06fe .2byte 0x6fe + 407e: fbfa .2byte 0xfbfa + 4080: fa06 .2byte 0xfa06 + 4082: fafd .2byte 0xfafd + 4084: 0106 .2byte 0x106 + 4086: 0404 .2byte 0x404 + 4088: 05fc .2byte 0x5fc + 408a: fa00f8fb .4byte 0xfa00f8fb + 408e: 01fc .2byte 0x1fc + 4090: fc00 vmsge.vx v24,v0,ra,v0.t + 4092: 03fa .2byte 0x3fa + 4094: fdfc .2byte 0xfdfc + 4096: 0304 .2byte 0x304 + 4098: f802 vmsge.vx v16,v0,ra,v0.t + 409a: 00fa .2byte 0xfa + 409c: f8f8 .2byte 0xf8f8 + 409e: 0202 vmsge.vx v4,v0,zero,v0.t + 40a0: fb02f803 vmsge.vx v16,v16,t0 + 40a4: fc01 vmsge.vx v24,v0,ra,v0.t + 40a6: fbff .2byte 0xfbff + 40a8: f9fe .2byte 0xf9fe + 40aa: 0506 .2byte 0x506 + 40ac: 0302 vmsge.vx v6,v0,zero,v0.t + 40ae: 0205 .2byte 0x205 + 40b0: ff01 vmsge.vx v30,v0,ra,v0.t + 40b2: 02f9 .2byte 0x2f9 + 40b4: 0304 .2byte 0x304 + 40b6: fefa .2byte 0xfefa + 40b8: fd05 .2byte 0xfd05 + 40ba: 0405 .2byte 0x405 + 40bc: 01fc .2byte 0x1fc + 40be: 030001fb .4byte 0x30001fb + 40c2: fdff .2byte 0xfdff + 40c4: 0200 vmsge.vx v4,v0,zero,v0.t + 40c6: 0602f9fb .4byte 0x602f9fb + 40ca: fbfa .2byte 0xfbfa + 40cc: ff02 vmsge.vx v30,v0,ra,v0.t + 40ce: ff06 .2byte 0xff06 + 40d0: 0405 .2byte 0x405 + 40d2: 0400 vmsge.vx v8,v0,zero,v0.t + 40d4: f8fa .2byte 0xf8fa + 40d6: 01fc03fb .4byte 0x1fc03fb + 40da: 03ff 0302 fbfa fffd .byte 0xff, 0x03, 0x02, 0x03, 0xfa, 0xfb, 0xfd, 0xff, 0xf9, 0xff + 40e2: fff9 + 40e4: 03f8 .2byte 0x3f8 + 40e6: faf8 .2byte 0xfaf8 + 40e8: ffff .2byte 0xffff + 40ea: 0104 .2byte 0x104 + 40ec: fbfcf903 vmsge.vx v18,v31,s9 + 40f0: fffc .2byte 0xfffc + 40f2: 0204f903 vmsge.vx v18,v0,s1 + 40f6: fc00 vmsge.vx v24,v0,ra,v0.t + 40f8: fb01 vmsge.vx v22,v0,ra,v0.t + 40fa: 06ff 04fa fc02 0106 .byte 0xff, 0x06, 0xfa, 0x04, 0x02, 0xfc, 0x06, 0x01, 0x05, 0xf8 + 4102: f805 + 4104: fafe .2byte 0xfafe + 4106: 01fe .2byte 0x1fe + 4108: 0302 vmsge.vx v6,v0,zero,v0.t + 410a: 04fd .2byte 0x4fd + 410c: f8ff .2byte 0xf8ff + 410e: fe05 .2byte 0xfe05 + 4110: fbfcfefb .4byte 0xfbfcfefb + 4114: 03ff fffd 01fd 02fd .byte 0xff, 0x03, 0xfd, 0xff, 0xfd, 0x01, 0xfd, 0x02, 0xfc, 0xfb + 411c: fbfc + 411e: fb01 vmsge.vx v22,v0,ra,v0.t + 4120: 0500 vmsge.vx v10,v0,zero,v0.t + 4122: fcff .2byte 0xfcff + 4124: fbfd .2byte 0xfbfd + 4126: 04fb0203 lb tp,79(s6) + 412a: 05fe .2byte 0x5fe + 412c: 00f9 .2byte 0xf9 + 412e: 04ff fbfc 0203 ff06 .byte 0xff, 0x04, 0xfc, 0xfb, 0x03, 0x02, 0x06, 0xff, 0xfb, 0x06 + 4136: 06fb + 4138: f804 .2byte 0xf804 + 413a: 01f8 .2byte 0x1f8 + 413c: fdfe .2byte 0xfdfe + 413e: f901 vmsge.vx v18,v0,ra,v0.t + 4140: f801 vmsge.vx v16,v0,ra,v0.t + 4142: 0505 .2byte 0x505 + 4144: 0400 vmsge.vx v8,v0,zero,v0.t + 4146: fe04 .2byte 0xfe04 + 4148: fc05 .2byte 0xfc05 + 414a: fcf9fbfb .4byte 0xfcf9fbfb + 414e: fe00 vmsge.vx v28,v0,ra,v0.t + 4150: 0500 vmsge.vx v10,v0,zero,v0.t + 4152: fafc .2byte 0xfafc + 4154: 01fe .2byte 0x1fe + 4156: 0205 .2byte 0x205 + 4158: 0602 vmsge.vx v12,v0,zero,v0.t + 415a: 0305 .2byte 0x305 + 415c: fe05 .2byte 0xfe05 + 415e: 0604 .2byte 0x604 + 4160: 0600 vmsge.vx v12,v0,zero,v0.t + 4162: 0301 vmsge.vx v6,v0,zero,v0.t + 4164: f9fa .2byte 0xf9fa + 4166: 0604 .2byte 0x604 + 4168: faf9 .2byte 0xfaf9 + 416a: 0506 .2byte 0x506 + 416c: 03f8 .2byte 0x3f8 + 416e: fc06 .2byte 0xfc06 + 4170: fb040203 lb tp,-80(s0) + 4174: fcfc .2byte 0xfcfc + 4176: 03f8 .2byte 0x3f8 + 4178: 04fc .2byte 0x4fc + 417a: fcfa .2byte 0xfcfa + 417c: 04fe .2byte 0x4fe + 417e: 06fd .2byte 0x6fd + 4180: f805 .2byte 0xf805 + 4182: fafd .2byte 0xfafd + 4184: 00f8 .2byte 0xf8 + 4186: 00fa .2byte 0xfa + 4188: 03fc .2byte 0x3fc + 418a: fb05 .2byte 0xfb05 + 418c: f804 .2byte 0xf804 + 418e: 06fd .2byte 0x6fd + 4190: fa06 .2byte 0xfa06 + 4192: 0302 vmsge.vx v6,v0,zero,v0.t + 4194: fa00fc03 vmsge.vx v24,v0,ra + 4198: fdfd .2byte 0xfdfd + 419a: 0406 .2byte 0x406 + 419c: 00fc .2byte 0xfc + 419e: 05f801fb .4byte 0x5f801fb + 41a2: ffff .2byte 0xffff + 41a4: f801 vmsge.vx v16,v0,ra,v0.t + 41a6: fdfa .2byte 0xfdfa + 41a8: fafd00fb .4byte 0xfafd00fb + 41ac: 02fc .2byte 0x2fc + 41ae: fcf9 .2byte 0xfcf9 + 41b0: 0305 .2byte 0x305 + 41b2: 0602 vmsge.vx v12,v0,zero,v0.t + 41b4: fbfc .2byte 0xfbfc + 41b6: fafd .2byte 0xfafd + 41b8: 020205fb .4byte 0x20205fb + 41bc: fa05 .2byte 0xfa05 + 41be: fa04 .2byte 0xfa04 + 41c0: 03fdfb03 vmsge.vx v22,v31,s11 + 41c4: 0404 .2byte 0x404 + 41c6: 06fe .2byte 0x6fe + 41c8: fc04 .2byte 0xfc04 + 41ca: fa01 vmsge.vx v20,v0,ra,v0.t + 41cc: f8ff .2byte 0xf8ff + 41ce: f9f8 .2byte 0xf9f8 + 41d0: f8fdfdfb .4byte 0xf8fdfdfb + 41d4: fd01 vmsge.vx v26,v0,ra,v0.t + 41d6: fcff .2byte 0xfcff + 41d8: 00fa .2byte 0xfa + 41da: 0606fc03 vmsge.vx v24,v0,a3 + 41de: fc02 vmsge.vx v24,v0,ra,v0.t + 41e0: 00fa .2byte 0xfa + 41e2: fdf8 .2byte 0xfdf8 + 41e4: 0205 .2byte 0x205 + 41e6: fe01 vmsge.vx v28,v0,ra,v0.t + 41e8: 06f8 .2byte 0x6f8 + 41ea: f901 vmsge.vx v18,v0,ra,v0.t + 41ec: 0300 vmsge.vx v6,v0,zero,v0.t + 41ee: 0001 vmsge.vx v0,v0,zero,v0.t + 41f0: f8ff .2byte 0xf8ff + 41f2: fe030503 lb a0,-32(t1) + 41f6: 0101 vmsge.vx v2,v0,zero,v0.t + 41f8: fb00 vmsge.vx v22,v0,ra,v0.t + 41fa: 05fe .2byte 0x5fe + 41fc: fcfa .2byte 0xfcfa + 41fe: 0402 vmsge.vx v8,v0,zero,v0.t + 4200: 04ff fe05 f8f8 fd01 .byte 0xff, 0x04, 0x05, 0xfe, 0xf8, 0xf8, 0x01, 0xfd, 0x01, 0x05 + 4208: 0501 + 420a: 02fa .2byte 0x2fa + 420c: 0601 vmsge.vx v12,v0,zero,v0.t + 420e: fa01 vmsge.vx v20,v0,ra,v0.t + 4210: 05ff 03f8 fe05 f8fd .byte 0xff, 0x05, 0xf8, 0x03, 0x05, 0xfe, 0xfd, 0xf8, 0x00, 0xf8 + 4218: f800 + 421a: fffd .2byte 0xfffd + 421c: fa04 .2byte 0xfa04 + 421e: 0402 vmsge.vx v8,v0,zero,v0.t + 4220: fdfef903 vmsge.vx v18,v31,t4,v0.t + 4224: 0504 .2byte 0x504 + 4226: 0606 .2byte 0x606 + 4228: f9fb0003 lb zero,-97(s6) + 422c: f8fa .2byte 0xf8fa + 422e: 06fc .2byte 0x6fc + 4230: 02fa .2byte 0x2fa + 4232: fa05 .2byte 0xfa05 + 4234: f9fa .2byte 0xf9fa + 4236: 0304 .2byte 0x304 + 4238: fc01 vmsge.vx v24,v0,ra,v0.t + 423a: 0601 vmsge.vx v12,v0,zero,v0.t + 423c: 02fefefb .4byte 0x2fefefb + 4240: 0301 vmsge.vx v6,v0,zero,v0.t + 4242: fcfe .2byte 0xfcfe + 4244: 0602 vmsge.vx v12,v0,zero,v0.t + 4246: 05f9 .2byte 0x5f9 + 4248: fe01 vmsge.vx v28,v0,ra,v0.t + 424a: faf8 .2byte 0xfaf8 + 424c: fbf8 .2byte 0xfbf8 + 424e: 03ff fbf8 fd03 fe02 .byte 0xff, 0x03, 0xf8, 0xfb, 0x03, 0xfd, 0x02, 0xfe, 0xf9, 0x05 + 4256: 05f9 + 4258: 05ff 00fd 02fc 04fb .byte 0xff, 0x05, 0xfd, 0x00, 0xfc, 0x02, 0xfb, 0x04, 0x02, 0x01 + 4260: 0102 + 4262: fa05 .2byte 0xfa05 + 4264: fa05 .2byte 0xfa05 + 4266: 0206 .2byte 0x206 + 4268: f804 .2byte 0xf804 + 426a: fa06 .2byte 0xfa06 + 426c: ff01 vmsge.vx v30,v0,ra,v0.t + 426e: fffb01fb .4byte 0xfffb01fb + 4272: 0206 .2byte 0x206 + 4274: 05fc .2byte 0x5fc + 4276: f902 vmsge.vx v18,v0,ra,v0.t + 4278: 0101 vmsge.vx v2,v0,zero,v0.t + 427a: ff06 .2byte 0xff06 + 427c: fc01 vmsge.vx v24,v0,ra,v0.t + 427e: 0301 vmsge.vx v6,v0,zero,v0.t + 4280: fb01 vmsge.vx v22,v0,ra,v0.t + 4282: fe06 .2byte 0xfe06 + 4284: f9ff .2byte 0xf9ff + 4286: faf8 .2byte 0xfaf8 + 4288: 06f9 .2byte 0x6f9 + 428a: fb00fafb .4byte 0xfb00fafb + 428e: fb05 .2byte 0xfb05 + 4290: fbfa .2byte 0xfbfa + 4292: fe02 vmsge.vx v28,v0,ra,v0.t + 4294: 0202 vmsge.vx v4,v0,zero,v0.t + 4296: f802 vmsge.vx v16,v0,ra,v0.t + 4298: fcfc .2byte 0xfcfc + 429a: 0401 vmsge.vx v8,v0,zero,v0.t + 429c: 05ff 0205 0103 0603 .byte 0xff, 0x05, 0x05, 0x02, 0x03, 0x01, 0x03, 0x06, 0x06, 0xfb + 42a4: fb06 + 42a6: 0401 vmsge.vx v8,v0,zero,v0.t + 42a8: fa06 .2byte 0xfa06 + 42aa: 03f8 .2byte 0x3f8 + 42ac: 04fa .2byte 0x4fa + 42ae: 0201 vmsge.vx v4,v0,zero,v0.t + 42b0: fa05fdfb .4byte 0xfa05fdfb + 42b4: 04fe .2byte 0x4fe + 42b6: 00f8 .2byte 0xf8 + 42b8: 0405 .2byte 0x405 + 42ba: fafc .2byte 0xfafc + 42bc: fc00 vmsge.vx v24,v0,ra,v0.t + 42be: 06fa .2byte 0x6fa + 42c0: 0404 .2byte 0x404 + 42c2: fff8 .2byte 0xfff8 + 42c4: 05fc .2byte 0x5fc + 42c6: 00fa .2byte 0xfa + 42c8: ff01 vmsge.vx v30,v0,ra,v0.t + 42ca: 04fd .2byte 0x4fd + 42cc: f806fdfb .4byte 0xf806fdfb + 42d0: 0004 .2byte 0x4 + 42d2: 05f8 .2byte 0x5f8 + 42d4: 01f9 .2byte 0x1f9 + 42d6: 02f8 .2byte 0x2f8 + 42d8: 04fe .2byte 0x4fe + 42da: fbf8 .2byte 0xfbf8 + 42dc: 03ff 0501 f900 fffc .byte 0xff, 0x03, 0x01, 0x05, 0x00, 0xf9, 0xfc, 0xff, 0x03, 0xf9 + 42e4: f903 + 42e6: fffffc03 vmsge.vx v24,v31,t6 + 42ea: 06f8 .2byte 0x6f8 + 42ec: fc01 vmsge.vx v24,v0,ra,v0.t + 42ee: fcf9 .2byte 0xfcf9 + 42f0: fafd .2byte 0xfafd + 42f2: 03fcff03 vmsge.vx v30,v31,s9 + 42f6: 0206 .2byte 0x206 + 42f8: 0205 .2byte 0x205 + 42fa: 0505 .2byte 0x505 + 42fc: fefc .2byte 0xfefc + 42fe: f9fc .2byte 0xf9fc + 4300: 0506 .2byte 0x506 + 4302: fdfc .2byte 0xfdfc + 4304: 04fc .2byte 0x4fc + 4306: fe01 vmsge.vx v28,v0,ra,v0.t + 4308: 03fa .2byte 0x3fa + 430a: fa02 vmsge.vx v20,v0,ra,v0.t + 430c: 02ff0103 lb sp,47(t5) + 4310: 03f9 .2byte 0x3f9 + 4312: f9f8 .2byte 0xf9f8 + 4314: fafe .2byte 0xfafe + 4316: f800 vmsge.vx v16,v0,ra,v0.t + 4318: 0405 .2byte 0x405 + 431a: fbfa .2byte 0xfbfa + 431c: f906fd03 vmsge.vx v26,v16,a3,v0.t + 4320: 05fc .2byte 0x5fc + 4322: 0102 vmsge.vx v2,v0,zero,v0.t + 4324: fbfe .2byte 0xfbfe + 4326: 0502 vmsge.vx v10,v0,zero,v0.t + 4328: 0604 .2byte 0x604 + 432a: 0305 .2byte 0x305 + 432c: f804 .2byte 0xf804 + 432e: 02050003 lb zero,32(a0) + 4332: 00f9 .2byte 0xf9 + 4334: 06fa .2byte 0x6fa + 4336: 0504 .2byte 0x504 + 4338: fb06 .2byte 0xfb06 + 433a: 0500 vmsge.vx v10,v0,zero,v0.t + 433c: 0101 vmsge.vx v2,v0,zero,v0.t + 433e: 00fc .2byte 0xfc + 4340: fffe .2byte 0xfffe + 4342: fefc0003 lb zero,-17(s8) + 4346: 0402 vmsge.vx v8,v0,zero,v0.t + 4348: f9fc .2byte 0xf9fc + 434a: fc01 vmsge.vx v24,v0,ra,v0.t + 434c: fffd .2byte 0xfffd + 434e: fa05 .2byte 0xfa05 + 4350: fd00 vmsge.vx v26,v0,ra,v0.t + 4352: 01f9 .2byte 0x1f9 + 4354: 0202 vmsge.vx v4,v0,zero,v0.t + 4356: f806 .2byte 0xf806 + 4358: 0400 vmsge.vx v8,v0,zero,v0.t + 435a: fe00 vmsge.vx v28,v0,ra,v0.t + 435c: fffcfafb .4byte 0xfffcfafb + 4360: fb02 vmsge.vx v22,v0,ra,v0.t + 4362: fdfd .2byte 0xfdfd + 4364: fffe .2byte 0xfffe + 4366: 02fbf903 vmsge.vx v18,v15,s7 + 436a: 0501 vmsge.vx v10,v0,zero,v0.t + 436c: 00f8 .2byte 0xf8 + 436e: fd04 .2byte 0xfd04 + 4370: fdfe .2byte 0xfdfe + 4372: fdf8f8fb .4byte 0xfdf8f8fb + 4376: f804 .2byte 0xf804 + 4378: 06ff f802 0303 feff .byte 0xff, 0x06, 0x02, 0xf8, 0x03, 0x03, 0xff, 0xfe, 0xfb, 0x02 + 4380: 02fb + 4382: f9fe .2byte 0xf9fe + 4384: 00ff 00fe 0505 fcfe .byte 0xff, 0x00, 0xfe, 0x00, 0x05, 0x05, 0xfe, 0xfc, 0x06, 0xf8 + 438c: f806 + 438e: 00fdfbfb .4byte 0xfdfbfb + 4392: fd01 vmsge.vx v26,v0,ra,v0.t + 4394: ff06 .2byte 0xff06 + 4396: 06fc .2byte 0x6fc + 4398: 0106 .2byte 0x106 + 439a: f9fa .2byte 0xf9fa + 439c: ff04 .2byte 0xff04 + 439e: feff .2byte 0xfeff + 43a0: 04030103 lb sp,64(t1) + 43a4: 0300 vmsge.vx v6,v0,zero,v0.t + 43a6: 0000 vmsge.vx v0,v0,zero,v0.t + 43a8: f9fa .2byte 0xf9fa + 43aa: ffff .2byte 0xffff + 43ac: ff06 .2byte 0xff06 + 43ae: 01fa .2byte 0x1fa + 43b0: 0201fafb .4byte 0x201fafb + 43b4: f9fa .2byte 0xf9fa + 43b6: 0102 vmsge.vx v2,v0,zero,v0.t + 43b8: f906 .2byte 0xf906 + 43ba: 03fc .2byte 0x3fc + 43bc: fd00 vmsge.vx v26,v0,ra,v0.t + 43be: fffd .2byte 0xfffd + 43c0: fef8 .2byte 0xfef8 + 43c2: fe06 .2byte 0xfe06 + 43c4: fff8 .2byte 0xfff8 + 43c6: 02fd .2byte 0x2fd + 43c8: fffc .2byte 0xfffc + 43ca: f8fa .2byte 0xf8fa + 43cc: f905 .2byte 0xf905 + 43ce: f901 vmsge.vx v18,v0,ra,v0.t + 43d0: f906 .2byte 0xf906 + 43d2: fdf9 .2byte 0xfdf9 + 43d4: 06fa .2byte 0x6fa + 43d6: f8fe .2byte 0xf8fe + 43d8: fafc .2byte 0xfafc + 43da: fdff .2byte 0xfdff + 43dc: fe02 vmsge.vx v28,v0,ra,v0.t + 43de: 05fa .2byte 0x5fa + 43e0: 01fd .2byte 0x1fd + 43e2: 0604 .2byte 0x604 + 43e4: 01fc .2byte 0x1fc + 43e6: ffff .2byte 0xffff + 43e8: 06fa .2byte 0x6fa + 43ea: fcfd .2byte 0xfcfd + 43ec: fdfe0203 lb tp,-33(t3) + 43f0: fefa .2byte 0xfefa + 43f2: fe05 .2byte 0xfe05 + 43f4: fb06 .2byte 0xfb06 + 43f6: f901 vmsge.vx v18,v0,ra,v0.t + 43f8: fefd .2byte 0xfefd + 43fa: 01ff fd03 0605 .byte 0xff, 0x01, 0x03, 0xfd, 0x05, 0x06, 0xfe, 0x00, 0xfe, 0xfe + 4402: + +0000000000004400 : + 4400: 00fe .2byte 0xfe + 4402: fefe .2byte 0xfefe + 4404: fffa .2byte 0xfffa + 4406: 04f8 .2byte 0x4f8 + 4408: 02f806fb .4byte 0x2f806fb + 440c: fe00 vmsge.vx v28,v0,ra,v0.t + 440e: 0000 vmsge.vx v0,v0,zero,v0.t + 4410: fbf8 .2byte 0xfbf8 + 4412: 0505 .2byte 0x505 + 4414: 0002 vmsge.vx v0,v0,zero,v0.t + 4416: fbfc .2byte 0xfbfc + 4418: f904 .2byte 0xf904 + 441a: 00f9 .2byte 0xf9 + 441c: 0101 vmsge.vx v2,v0,zero,v0.t + 441e: fefa .2byte 0xfefa + 4420: f9f9 .2byte 0xf9f9 + 4422: fd02 vmsge.vx v26,v0,ra,v0.t + 4424: fafbfc03 vmsge.vx v24,v15,s7 + 4428: f9fe .2byte 0xf9fe + 442a: fc00 vmsge.vx v24,v0,ra,v0.t + 442c: fdfe .2byte 0xfdfe + 442e: 05fe .2byte 0x5fe + 4430: 00fe .2byte 0xfe + 4432: 0404 .2byte 0x404 + 4434: f9f9 .2byte 0xf9f9 + 4436: fcff .2byte 0xfcff + 4438: fef8fbfb .4byte 0xfef8fbfb + 443c: f9ff .2byte 0xf9ff + 443e: ff01 vmsge.vx v30,v0,ra,v0.t + 4440: 0204 .2byte 0x204 + 4442: f906 .2byte 0xf906 + 4444: fbfc .2byte 0xfbfc + 4446: 0200 vmsge.vx v4,v0,zero,v0.t + 4448: 0300 vmsge.vx v6,v0,zero,v0.t + 444a: 01fb0103 lb sp,31(s6) + 444e: fef9 .2byte 0xfef9 + 4450: faf9 .2byte 0xfaf9 + 4452: fef9 .2byte 0xfef9 + 4454: 06ff fbf8 0106 0004 .byte 0xff, 0x06, 0xf8, 0xfb, 0x06, 0x01, 0x04, 0x00, 0x01, 0x00 + 445c: 0001 + 445e: 0505 .2byte 0x505 + 4460: f806 .2byte 0xf806 + 4462: fa01 vmsge.vx v20,v0,ra,v0.t + 4464: 0404 .2byte 0x404 + 4466: 03fa .2byte 0x3fa + 4468: fbfa .2byte 0xfbfa + 446a: f9ff .2byte 0xf9ff + 446c: f9ff .2byte 0xf9ff + 446e: f900 vmsge.vx v18,v0,ra,v0.t + 4470: 0005 .2byte 0x5 + 4472: fafc .2byte 0xfafc + 4474: fffa .2byte 0xfffa + 4476: fbfe .2byte 0xfbfe + 4478: 0405 .2byte 0x405 + 447a: 04f9 .2byte 0x4f9 + 447c: 0600 vmsge.vx v12,v0,zero,v0.t + 447e: f8030403 lb s0,-128(t1) + 4482: 05f9 .2byte 0x5f9 + 4484: f802 vmsge.vx v16,v0,ra,v0.t + 4486: 0302 vmsge.vx v6,v0,zero,v0.t + 4488: 0606fe03 vmsge.vx v28,v0,a3 + 448c: 06f9 .2byte 0x6f9 + 448e: 0106 .2byte 0x106 + 4490: 02fdf903 vmsge.vx v18,v15,s11 + 4494: f901 vmsge.vx v18,v0,ra,v0.t + 4496: ffff .2byte 0xffff + 4498: f8fe .2byte 0xf8fe + 449a: fd02 vmsge.vx v26,v0,ra,v0.t + 449c: fbff .2byte 0xfbff + 449e: fc04 .2byte 0xfc04 + 44a0: 02ff 06fa 01fc fe03 .byte 0xff, 0x02, 0xfa, 0x06, 0xfc, 0x01, 0x03, 0xfe, 0x05, 0x05 + 44a8: 0505 + 44aa: 03fc .2byte 0x3fc + 44ac: faff .2byte 0xfaff + 44ae: f8fa .2byte 0xf8fa + 44b0: 0201 vmsge.vx v4,v0,zero,v0.t + 44b2: ff01 vmsge.vx v30,v0,ra,v0.t + 44b4: 01ff 0301 0306 fb00 .byte 0xff, 0x01, 0x01, 0x03, 0x06, 0x03, 0x00, 0xfb, 0xf9, 0xfe + 44bc: fef9 + 44be: fe01 vmsge.vx v28,v0,ra,v0.t + 44c0: fdfc .2byte 0xfdfc + 44c2: f8f8 .2byte 0xf8f8 + 44c4: 04f8 .2byte 0x4f8 + 44c6: f805 .2byte 0xf805 + 44c8: f9fc .2byte 0xf9fc + 44ca: 05fdfc03 vmsge.vx v24,v31,s11,v0.t + 44ce: 06fc .2byte 0x6fc + 44d0: 0302 vmsge.vx v6,v0,zero,v0.t + 44d2: fdfd .2byte 0xfdfd + 44d4: f9f8 .2byte 0xf9f8 + 44d6: 060400fb .4byte 0x60400fb + 44da: 0305 .2byte 0x305 + 44dc: fdf9 .2byte 0xfdf9 + 44de: f804 .2byte 0xf804 + 44e0: 03fb0403 lb s0,63(s6) + 44e4: fc00 vmsge.vx v24,v0,ra,v0.t + 44e6: fdf9 .2byte 0xfdf9 + 44e8: 00ff 01fd 02fd 0204 .byte 0xff, 0x00, 0xfd, 0x01, 0xfd, 0x02, 0x04, 0x02, 0xfc, 0xf9 + 44f0: f9fc + 44f2: 04f9 .2byte 0x4f9 + 44f4: fb01 vmsge.vx v22,v0,ra,v0.t + 44f6: fa04 .2byte 0xfa04 + 44f8: 00060303 lb t1,0(a2) + 44fc: fcff .2byte 0xfcff + 44fe: f9f9 .2byte 0xf9f9 + 4500: 0506fc03 vmsge.vx v24,v16,a3,v0.t + 4504: f8f8 .2byte 0xf8f8 + 4506: fd05 .2byte 0xfd05 + 4508: 04fd .2byte 0x4fd + 450a: 03fd .2byte 0x3fd + 450c: fe02 vmsge.vx v28,v0,ra,v0.t + 450e: fdfbfafb .4byte 0xfdfbfafb + 4512: 03fe .2byte 0x3fe + 4514: fa00 vmsge.vx v20,v0,ra,v0.t + 4516: f8f8 .2byte 0xf8f8 + 4518: fdfc .2byte 0xfdfc + 451a: fd02 vmsge.vx v26,v0,ra,v0.t + 451c: f906 .2byte 0xf906 + 451e: fdfd .2byte 0xfdfd + 4520: 0502 vmsge.vx v10,v0,zero,v0.t + 4522: fb01 vmsge.vx v22,v0,ra,v0.t + 4524: 05f8 .2byte 0x5f8 + 4526: fe020003 lb zero,-32(tp) # ffffffffffffffe0 <_end+0xffffffffefffff98> + 452a: fffe00fb .4byte 0xfffe00fb + 452e: fd03f9fb .4byte 0xfd03f9fb + 4532: ffff .2byte 0xffff + 4534: 0205 .2byte 0x205 + 4536: 03fe .2byte 0x3fe + 4538: 0305 .2byte 0x305 + 453a: fbff0103 lb sp,-65(t5) + 453e: f906 .2byte 0xf906 + 4540: 0204 .2byte 0x204 + 4542: 0306 .2byte 0x306 + 4544: fb00 vmsge.vx v22,v0,ra,v0.t + 4546: faff .2byte 0xfaff + 4548: fdff .2byte 0xfdff + 454a: f8ff .2byte 0xf8ff + 454c: f8fc .2byte 0xf8fc + 454e: fff9 .2byte 0xfff9 + 4550: 06fa .2byte 0x6fa + 4552: fc04 .2byte 0xfc04 + 4554: 04f9 .2byte 0x4f9 + 4556: 0206 .2byte 0x206 + 4558: fbfa .2byte 0xfbfa + 455a: f902 vmsge.vx v18,v0,ra,v0.t + 455c: fcfc .2byte 0xfcfc + 455e: 0500 vmsge.vx v10,v0,zero,v0.t + 4560: 04fc .2byte 0x4fc + 4562: 0000 vmsge.vx v0,v0,zero,v0.t + 4564: fd05 .2byte 0xfd05 + 4566: 0004 .2byte 0x4 + 4568: 06fe .2byte 0x6fe + 456a: fcfa .2byte 0xfcfa + 456c: fb00 vmsge.vx v22,v0,ra,v0.t + 456e: f9fa .2byte 0xf9fa + 4570: faff .2byte 0xfaff + 4572: fdfd .2byte 0xfdfd + 4574: 0101 vmsge.vx v2,v0,zero,v0.t + 4576: fbfc0403 lb s0,-65(s8) + 457a: fb06 .2byte 0xfb06 + 457c: 05fe .2byte 0x5fe + 457e: 0005 .2byte 0x5 + 4580: fdf8 .2byte 0xfdf8 + 4582: 06f8 .2byte 0x6f8 + 4584: 03ff 05fb fcfb f8fa .byte 0xff, 0x03, 0xfb, 0x05, 0xfb, 0xfc, 0xfa, 0xf8, 0xf9, 0xf9 + 458c: f9f9 + 458e: f9fcfa03 vmsge.vx v20,v31,s9,v0.t + 4592: 0201 vmsge.vx v4,v0,zero,v0.t + 4594: fbf8 .2byte 0xfbf8 + 4596: ff02 vmsge.vx v30,v0,ra,v0.t + 4598: ff01 vmsge.vx v30,v0,ra,v0.t + 459a: 05fa .2byte 0x5fa + 459c: 05fa .2byte 0x5fa + 459e: fa05 .2byte 0xfa05 + 45a0: fd05 .2byte 0xfd05 + 45a2: fafa .2byte 0xfafa + 45a4: fffd .2byte 0xfffd + 45a6: fcf8 .2byte 0xfcf8 + 45a8: fd02 vmsge.vx v26,v0,ra,v0.t + 45aa: 05fb05fb .4byte 0x5fb05fb + 45ae: f8fc .2byte 0xf8fc + 45b0: 01f9 .2byte 0x1f9 + 45b2: fd00 vmsge.vx v26,v0,ra,v0.t + 45b4: 0601 vmsge.vx v12,v0,zero,v0.t + 45b6: ff02 vmsge.vx v30,v0,ra,v0.t + 45b8: 0501 vmsge.vx v10,v0,zero,v0.t + 45ba: 0402 vmsge.vx v8,v0,zero,v0.t + 45bc: fe04 .2byte 0xfe04 + 45be: 0301 vmsge.vx v6,v0,zero,v0.t + 45c0: 02fe .2byte 0x2fe + 45c2: fbff .2byte 0xfbff + 45c4: 06f904fb .4byte 0x6f904fb + 45c8: 01fc .2byte 0x1fc + 45ca: f801 vmsge.vx v16,v0,ra,v0.t + 45cc: 0602 vmsge.vx v12,v0,zero,v0.t + 45ce: fff9 .2byte 0xfff9 + 45d0: 05fcfb03 vmsge.vx v22,v31,s9,v0.t + 45d4: 01f9 .2byte 0x1f9 + 45d6: 01fc .2byte 0x1fc + 45d8: 03fd .2byte 0x3fd + 45da: 01fc .2byte 0x1fc + 45dc: 0605 .2byte 0x605 + 45de: 04fd .2byte 0x4fd + 45e0: 00fa .2byte 0xfa + 45e2: 06040203 lb tp,96(s0) + 45e6: 04f8 .2byte 0x4f8 + 45e8: f9ff .2byte 0xf9ff + 45ea: fdfc .2byte 0xfdfc + 45ec: fefc .2byte 0xfefc + 45ee: ff000103 lb sp,-16(zero) # fffffffffffffff0 <_end+0xffffffffefffffa8> + 45f2: f802 vmsge.vx v16,v0,ra,v0.t + 45f4: 06f903fb .4byte 0x6f903fb + 45f8: f905 .2byte 0xf905 + 45fa: ff02 vmsge.vx v30,v0,ra,v0.t + 45fc: fff8 .2byte 0xfff8 + 45fe: fbfc .2byte 0xfbfc + 4600: fb06 .2byte 0xfb06 + 4602: fd00 vmsge.vx v26,v0,ra,v0.t + 4604: 0302 vmsge.vx v6,v0,zero,v0.t + 4606: fbff .2byte 0xfbff + 4608: 00ff 03fd f9f9 fbf9 .byte 0xff, 0x00, 0xfd, 0x03, 0xf9, 0xf9, 0xf9, 0xfb, 0x00, 0xf8 + 4610: f800 + 4612: 01fe .2byte 0x1fe + 4614: 06fd .2byte 0x6fd + 4616: fefe .2byte 0xfefe + 4618: f8ff .2byte 0xf8ff + 461a: 01fa .2byte 0x1fa + 461c: 0501 vmsge.vx v10,v0,zero,v0.t + 461e: 0205 .2byte 0x205 + 4620: fd00 vmsge.vx v26,v0,ra,v0.t + 4622: fafc .2byte 0xfafc + 4624: 06ff 01f8 f803 f9f9 .byte 0xff, 0x06, 0xf8, 0x01, 0x03, 0xf8, 0xf9, 0xf9, 0xff, 0xfb + 462c: fbff + 462e: fc02fcfb .4byte 0xfc02fcfb + 4632: 01fbfc03 vmsge.vx v24,v31,s7,v0.t + 4636: 05ff 00fe 03f8 f8fe .byte 0xff, 0x05, 0xfe, 0x00, 0xf8, 0x03, 0xfe, 0xf8, 0xfb, 0x01 + 463e: 01fb + 4640: fffa .2byte 0xfffa + 4642: 0501 vmsge.vx v10,v0,zero,v0.t + 4644: ff06 .2byte 0xff06 + 4646: f9fd .2byte 0xf9fd + 4648: 0106 .2byte 0x106 + 464a: 0606 .2byte 0x606 + 464c: f8f8 .2byte 0xf8f8 + 464e: fefa .2byte 0xfefa + 4650: fe01 vmsge.vx v28,v0,ra,v0.t + 4652: 06ff0103 lb sp,111(t5) + 4656: fe02f803 vmsge.vx v16,v0,t0 + 465a: 0601 vmsge.vx v12,v0,zero,v0.t + 465c: 00ff fcf8 05fb 04ff .byte 0xff, 0x00, 0xf8, 0xfc, 0xfb, 0x05, 0xff, 0x04, 0x04, 0x02 + 4664: 0204 + 4666: 06f8 .2byte 0x6f8 + 4668: f800 vmsge.vx v16,v0,ra,v0.t + 466a: fbfd .2byte 0xfbfd + 466c: fbff .2byte 0xfbff + 466e: 05f9 .2byte 0x5f9 + 4670: fc04 .2byte 0xfc04 + 4672: 0505 .2byte 0x505 + 4674: fafd .2byte 0xfafd + 4676: 0301 vmsge.vx v6,v0,zero,v0.t + 4678: fbfc .2byte 0xfbfc + 467a: 06f8 .2byte 0x6f8 + 467c: fafc0203 lb tp,-81(s8) + 4680: f8000203 lb tp,-128(zero) # ffffffffffffff80 <_end+0xffffffffefffff38> + 4684: 0102 vmsge.vx v2,v0,zero,v0.t + 4686: 06fc .2byte 0x6fc + 4688: 0306 .2byte 0x306 + 468a: ff01 vmsge.vx v30,v0,ra,v0.t + 468c: fd06 .2byte 0xfd06 + 468e: 04fe .2byte 0x4fe + 4690: f9fa .2byte 0xf9fa + 4692: f8f8 .2byte 0xf8f8 + 4694: fcfa .2byte 0xfcfa + 4696: 04f8 .2byte 0x4f8 + 4698: 0100 vmsge.vx v2,v0,zero,v0.t + 469a: fa00 vmsge.vx v20,v0,ra,v0.t + 469c: fd02 vmsge.vx v26,v0,ra,v0.t + 469e: f900 vmsge.vx v18,v0,ra,v0.t + 46a0: 03fa .2byte 0x3fa + 46a2: 01fc .2byte 0x1fc + 46a4: 0001 vmsge.vx v0,v0,zero,v0.t + 46a6: 04fc .2byte 0x4fc + 46a8: f806 .2byte 0xf806 + 46aa: f804 .2byte 0xf804 + 46ac: f8fe .2byte 0xf8fe + 46ae: 00fa .2byte 0xfa + 46b0: 03fa .2byte 0x3fa + 46b2: 06f8 .2byte 0x6f8 + 46b4: 0301 vmsge.vx v6,v0,zero,v0.t + 46b6: fc00 vmsge.vx v24,v0,ra,v0.t + 46b8: fafc .2byte 0xfafc + 46ba: 0002 vmsge.vx v0,v0,zero,v0.t + 46bc: f904 .2byte 0xf904 + 46be: ff06 .2byte 0xff06 + 46c0: 01f9 .2byte 0x1f9 + 46c2: f8fc .2byte 0xf8fc + 46c4: 05f9 .2byte 0x5f9 + 46c6: 03f9fdfb .4byte 0x3f9fdfb + 46ca: 00f9 .2byte 0xf9 + 46cc: 0602 vmsge.vx v12,v0,zero,v0.t + 46ce: fbfa .2byte 0xfbfa + 46d0: fafc .2byte 0xfafc + 46d2: 0300 vmsge.vx v6,v0,zero,v0.t + 46d4: fb02 vmsge.vx v22,v0,ra,v0.t + 46d6: 010504fb .4byte 0x10504fb + 46da: 06fe .2byte 0x6fe + 46dc: f901 vmsge.vx v18,v0,ra,v0.t + 46de: fe02 vmsge.vx v28,v0,ra,v0.t + 46e0: fb04 .2byte 0xfb04 + 46e2: fc03fffb .4byte 0xfc03fffb + 46e6: fa06 .2byte 0xfa06 + 46e8: fc06 .2byte 0xfc06 + 46ea: fdff .2byte 0xfdff + 46ec: 05fd .2byte 0x5fd + 46ee: 06f8 .2byte 0x6f8 + 46f0: 03fc .2byte 0x3fc + 46f2: 03fd .2byte 0x3fd + 46f4: 04f8 .2byte 0x4f8 + 46f6: 0404 .2byte 0x404 + 46f8: fc00 vmsge.vx v24,v0,ra,v0.t + 46fa: fffa0203 lb tp,-1(s4) + 46fe: 0405 .2byte 0x405 + 4700: fd04 .2byte 0xfd04 + 4702: 05f9 .2byte 0x5f9 + 4704: 05040203 lb tp,80(s0) + 4708: 0300 vmsge.vx v6,v0,zero,v0.t + 470a: 0105fefb .4byte 0x105fefb + 470e: fcfa .2byte 0xfcfa + 4710: 01fe0603 lb a2,31(t3) + 4714: 0406 .2byte 0x406 + 4716: faf9 .2byte 0xfaf9 + 4718: f9fe .2byte 0xf9fe + 471a: f900 vmsge.vx v18,v0,ra,v0.t + 471c: fcfd .2byte 0xfcfd + 471e: fcfc .2byte 0xfcfc + 4720: f801 vmsge.vx v16,v0,ra,v0.t + 4722: 01fe .2byte 0x1fe + 4724: fef9 .2byte 0xfef9 + 4726: 01fa .2byte 0x1fa + 4728: 0104 .2byte 0x104 + 472a: 00f90203 lb tp,15(s2) + 472e: ff02 vmsge.vx v30,v0,ra,v0.t + 4730: 0501f803 vmsge.vx v16,v16,gp,v0.t + 4734: 0001 vmsge.vx v0,v0,zero,v0.t + 4736: 06fa .2byte 0x6fa + 4738: fef9 .2byte 0xfef9 + 473a: fdf8 .2byte 0xfdf8 + 473c: 0200fc03 vmsge.vx v24,v0,ra + 4740: fd01 vmsge.vx v26,v0,ra,v0.t + 4742: 02fd .2byte 0x2fd + 4744: fa04 .2byte 0xfa04 + 4746: fc01 vmsge.vx v24,v0,ra,v0.t + 4748: f9f9 .2byte 0xf9f9 + 474a: ff00 vmsge.vx v30,v0,ra,v0.t + 474c: f904 .2byte 0xf904 + 474e: fd00 vmsge.vx v26,v0,ra,v0.t + 4750: f8fbfe03 vmsge.vx v28,v15,s7,v0.t + 4754: 0305 .2byte 0x305 + 4756: 05fc .2byte 0x5fc + 4758: 0004fb03 vmsge.vx v22,v0,s1,v0.t + 475c: fbfd .2byte 0xfbfd + 475e: fd01 vmsge.vx v26,v0,ra,v0.t + 4760: 0406 .2byte 0x406 + 4762: fbf8 .2byte 0xfbf8 + 4764: fb01 vmsge.vx v22,v0,ra,v0.t + 4766: 03fa .2byte 0x3fa + 4768: fef9 .2byte 0xfef9 + 476a: 0100 vmsge.vx v2,v0,zero,v0.t + 476c: 03fc .2byte 0x3fc + 476e: 05f8 .2byte 0x5f8 + 4770: fe02 vmsge.vx v28,v0,ra,v0.t + 4772: 0100 vmsge.vx v2,v0,zero,v0.t + 4774: fbfe .2byte 0xfbfe + 4776: fe06 .2byte 0xfe06 + 4778: fffc01fb .4byte 0xfffc01fb + 477c: 0104 .2byte 0x104 + 477e: f9fc .2byte 0xf9fc + 4780: f804 .2byte 0xf804 + 4782: 00fe .2byte 0xfe + 4784: fe06f9fb .4byte 0xfe06f9fb + 4788: fa00 vmsge.vx v20,v0,ra,v0.t + 478a: 0402 vmsge.vx v8,v0,zero,v0.t + 478c: fef9 .2byte 0xfef9 + 478e: 0400 vmsge.vx v8,v0,zero,v0.t + 4790: ff01 vmsge.vx v30,v0,ra,v0.t + 4792: 0005 .2byte 0x5 + 4794: 0400f903 vmsge.vx v18,v0,ra,v0.t + 4798: 04f9 .2byte 0x4f9 + 479a: f900 vmsge.vx v18,v0,ra,v0.t + 479c: 0300 vmsge.vx v6,v0,zero,v0.t + 479e: fdf9 .2byte 0xfdf9 + 47a0: 03030103 lb sp,48(t1) + 47a4: f9fb0603 lb a2,-97(s6) + 47a8: faf9 .2byte 0xfaf9 + 47aa: 05f8 .2byte 0x5f8 + 47ac: 01ff 0503 0201 fe03 .byte 0xff, 0x01, 0x03, 0x05, 0x01, 0x02, 0x03, 0xfe, 0xfb, 0x01 + 47b4: 01fb + 47b6: ffff .2byte 0xffff + 47b8: fc04 .2byte 0xfc04 + 47ba: fc06 .2byte 0xfc06 + 47bc: fd05 .2byte 0xfd05 + 47be: 05fe .2byte 0x5fe + 47c0: fbfe .2byte 0xfbfe + 47c2: 0000 vmsge.vx v0,v0,zero,v0.t + 47c4: fff9 .2byte 0xfff9 + 47c6: ffff .2byte 0xffff + 47c8: fc01 vmsge.vx v24,v0,ra,v0.t + 47ca: fb00 vmsge.vx v22,v0,ra,v0.t + 47cc: fd05 .2byte 0xfd05 + 47ce: fefa .2byte 0xfefa + 47d0: 05ff f800 f801 fbfe .byte 0xff, 0x05, 0x00, 0xf8, 0x01, 0xf8, 0xfe, 0xfb, 0xf9, 0xfa + 47d8: faf9 + 47da: f802 vmsge.vx v16,v0,ra,v0.t + 47dc: 04fe .2byte 0x4fe + 47de: 01ff 00f8 fb03 fbff .byte 0xff, 0x01, 0xf8, 0x00, 0x03, 0xfb, 0xff, 0xfb, 0x01, 0xfc + 47e6: fc01 + 47e8: fe06 .2byte 0xfe06 + 47ea: 03fd .2byte 0x3fd + 47ec: fdf9 .2byte 0xfdf9 + 47ee: fa00 vmsge.vx v20,v0,ra,v0.t + 47f0: fd02fb03 vmsge.vx v22,v16,t0,v0.t + 47f4: fef9 .2byte 0xfef9 + 47f6: 06fe .2byte 0x6fe + 47f8: 01f8 .2byte 0x1f8 + 47fa: fcf8 .2byte 0xfcf8 + 47fc: 0205 .2byte 0x205 + 47fe: 03 04 Address 0x47fe is out of bounds. + + +Disassembly of section .sdata: + +0000000000004800 <__global_pointer$-0x800>: + 4800: 0101 vmsge.vx v2,v0,zero,v0.t + 4802: 0101 vmsge.vx v2,v0,zero,v0.t + 4804: 0101 vmsge.vx v2,v0,zero,v0.t + 4806: 0101 vmsge.vx v2,v0,zero,v0.t + +Disassembly of section .bss: + +0000000000004808 : + ... + +0000000000004c08 : + ... + +Disassembly of section .tohost: + +0000000010000000 : + ... + +0000000010000040 : + ... + +Disassembly of section .comment: + +0000000000000000 <.comment>: + 0: 3a434347 .4byte 0x3a434347 + 4: 2820 vmsge.vx v16,v0,zero,v0.t + 6: 65653267 .4byte 0x65653267 + a: 6535 .2byte 0x6535 + c: 3334 .2byte 0x3334 + e: 3030 .2byte 0x3030 + 10: 3831 .2byte 0x3831 + 12: 2029 .2byte 0x2029 + 14: 3231 .2byte 0x3231 + 16: 322e .2byte 0x322e + 18: 302e .2byte 0x302e + ... + +Disassembly of section .riscv.attributes: + +0000000000000000 <.riscv.attributes>: + 0: 5e41 vmsge.vx v28,v0,zero,v0.t + 2: 0000 vmsge.vx v0,v0,zero,v0.t + 4: 7200 vmsge.vx v4,v0,zero,v0.t + 6: 7369 .2byte 0x7369 + 8: 01007663 bgeu zero,a6,14 <_start+0x14> + c: 0054 .2byte 0x54 + e: 0000 vmsge.vx v0,v0,zero,v0.t + 10: 1004 .2byte 0x1004 + 12: 7205 .2byte 0x7205 + 14: 3676 .2byte 0x3676 + 16: 6934 .2byte 0x6934 + 18: 7032 .2byte 0x7032 + 1a: 5f31 .2byte 0x5f31 + 1c: 326d .2byte 0x326d + 1e: 3070 .2byte 0x3070 + 20: 7a5f 6369 7273 .byte 0x5f, 0x7a, 0x69, 0x63, 0x73, 0x72 + 26: 7032 .2byte 0x7032 + 28: 5f30 .2byte 0x5f30 + 2a: 6d7a .2byte 0x6d7a + 2c: 756d .2byte 0x756d + 2e: 316c .2byte 0x316c + 30: 3070 .2byte 0x3070 + 32: 7a5f 6576 3233 .byte 0x5f, 0x7a, 0x76, 0x65, 0x33, 0x32 + 38: 3178 .2byte 0x3178 + 3a: 3070 .2byte 0x3070 + 3c: 7a5f 6576 3436 .byte 0x5f, 0x7a, 0x76, 0x65, 0x36, 0x34 + 42: 3178 .2byte 0x3178 + 44: 3070 .2byte 0x3070 + 46: 7a5f 6c76 3233 .byte 0x5f, 0x7a, 0x76, 0x6c, 0x33, 0x32 + 4c: 3162 vmsge.vx v2,v0,zero,v0.t + 4e: 3070 .2byte 0x3070 + 50: 7a5f 6c76 3436 .byte 0x5f, 0x7a, 0x76, 0x6c, 0x36, 0x34 + 56: 3162 vmsge.vx v2,v0,zero,v0.t + 58: 3070 .2byte 0x3070 + 5a: 0800 vmsge.vx v16,v0,zero,v0.t + 5c: 0a01 vmsge.vx v20,v0,zero,v0.t + 5e: 0b Address 0x5e is out of bounds. + diff --git a/src/main/resources/applications_fpga/vector_matmul/vector_matmul.c b/src/main/resources/applications_fpga/vector_matmul/vector_matmul.c new file mode 100644 index 00000000..8bd7726c --- /dev/null +++ b/src/main/resources/applications_fpga/vector_matmul/vector_matmul.c @@ -0,0 +1,160 @@ +// #include "util.h" + +#define size_t long +#define N 32 + +const signed char array1[32][32] = {{-2, 0, -2, -2, -6, -1, -8, 4, -5, 6, -8, 2, 0, -2, 0, 0, -8, -5, 5, 5, 2, 0, -4, -5, 4, -7, -7, 0, 1, 1, -6, -2}, + {-7, -7, 2, -3, 3, -4, -5, -6, -2, -7, 0, -4, -2, -3, -2, 5, -2, 0, 4, 4, -7, -7, -1, -4, -5, -5, -8, -2, -1, -7, 1, -1}, + {4, 2, 6, -7, -4, -5, 0, 2, 0, 3, 3, 1, -5, 1, -7, -2, -7, -6, -7, -2, -1, 6, -8, -5, 6, 1, 4, 0, 1, 0, 5, 5}, + {6, -8, 1, -6, 4, 4, -6, 3, -6, -5, -1, -7, -1, -7, 0, -7, 5, 0, -4, -6, -6, -1, -2, -5, 5, 4, -7, 4, 0, 6, 3, 4}, + {3, -8, -7, 5, 2, -8, 2, 3, 3, -2, 6, 6, -7, 6, 6, 1, 3, -7, -3, 2, 1, -7, -1, -1, -2, -8, 2, -3, -1, -5, 4, -4}, + {-1, 2, -6, 6, -4, 1, 3, -2, 5, 5, -4, 3, -1, -6, -6, -8, 1, 2, 1, -1, -1, 1, 1, 3, 6, 3, 0, -5, -7, -2, 1, -2}, + {-4, -3, -8, -8, -8, 4, 5, -8, -4, -7, 3, -4, -3, 5, -4, 6, 2, 3, -3, -3, -8, -7, -5, 0, 4, 6, 5, 3, -7, -3, 4, -8}, + {3, 4, -5, 3, 0, -4, -7, -3, -1, 0, -3, 1, -3, 2, 4, 2, -4, -7, -7, 4, 1, -5, 4, -6, 3, 3, 6, 0, -1, -4, -7, -7}, + {3, -4, 6, 5, -8, -8, 5, -3, -3, 4, -3, 3, 2, -2, -5, -6, -5, -3, -2, 3, 0, -6, -8, -8, -4, -3, 2, -3, 6, -7, -3, -3}, + {2, 5, 1, -5, -8, 5, 3, 0, 2, -2, -5, 0, -2, -1, -5, -7, 3, -3, -1, -1, 5, 2, -2, 3, 5, 3, 3, 1, -1, -5, 6, -7}, + {4, 2, 6, 3, 0, -5, -1, -6, -1, -3, -1, -8, -4, -8, -7, -1, -6, 6, 4, -4, -7, 4, 6, 2, -6, -5, 2, -7, -4, -4, 0, 5}, + {-4, 4, 0, 0, 5, -3, 4, 0, -2, 6, -6, -4, 0, -5, -6, -7, -1, -6, -3, -3, 1, 1, 3, 4, -4, -5, 6, -5, -2, 5, 5, 0}, + {-8, -3, -8, 6, -1, 3, -5, 5, -5, -4, -6, -8, -7, -7, 3, -6, -4, -7, 1, 2, -8, -5, 2, -1, 1, -1, -6, 5, -6, 5, 5, -6}, + {5, -3, -6, -6, -3, -1, -8, -4, 2, -3, -5, 5, -5, 5, -4, -8, -7, 1, 0, -3, 1, 6, 2, -1, 1, 5, 2, 4, 4, -2, 1, 3}, + {-2, 2, -1, -5, -5, 4, -7, 6, -4, 1, 1, -8, 2, 6, -7, -1, 3, -5, -4, 5, -7, 1, -4, 1, -3, 3, -4, 1, 5, 6, -3, 4}, + {-6, 0, 3, 2, 4, 6, -8, 4, -1, -7, -4, -3, -4, -2, 3, 1, 0, -1, 2, -8, -5, 3, -7, 6, 5, -7, 2, -1, -8, -1, -4, -5}, + {6, -5, 0, -3, 2, 3, -1, -5, -1, 0, -3, 3, -7, -7, -7, -5, 0, -8, -2, 1, -3, 6, -2, -2, -1, -8, -6, 1, 1, 5, 5, 2}, + {0, -3, -4, -6, -1, 6, -8, 1, 3, -8, -7, -7, -1, -5, -5, -4, 2, -4, 3, -4, -5, 1, -1, 5, -2, 0, -8, 3, -2, -8, -5, 1}, + {-6, -1, 1, 5, 6, -1, -3, -7, 6, 1, 6, 6, -8, -8, -6, -2, 1, -2, 3, 1, -1, 6, 3, -8, 2, -2, 1, 6, -1, 0, -8, -4}, + {-5, 5, -1, 4, 4, 2, -8, 6, 0, -8, -3, -5, -1, -5, -7, 5, 4, -4, 5, 5, -3, -6, 1, 3, -4, -5, -8, 6, 3, 2, -4, -6}, + {3, 2, 0, -8, 2, 1, -4, 6, 6, 3, 1, -1, 6, -3, -2, 4, -6, -7, -8, -8, -6, -4, -8, 4, 0, 1, 0, -6, 2, -3, 0, -7}, + {-6, 3, -4, 1, 1, 0, -4, 4, 6, -8, 4, -8, -2, -8, -6, 0, -6, 3, -8, 6, 1, 3, 0, -4, -4, -6, 2, 0, 4, -7, 6, -1}, + {-7, 1, -4, -8, -7, 5, -5, -3, -7, 3, -7, 0, 2, 6, -6, -5, -4, -6, 0, 3, 2, -5, -5, 4, 5, 1, -2, 6, 1, -7, 2, -2}, + {4, -5, -5, -1, 3, -4, 6, -6, 6, -4, -1, -3, -3, 5, -8, 6, -4, 3, -3, 3, -8, 4, 4, 4, 0, -4, 3, 2, -6, -1, 5, 4}, + {4, -3, -7, 5, 3, 2, 4, 5, 0, 3, -5, -2, 5, 1, -6, -4, 3, 6, -2, 1, 6, 4, -7, -6, -2, -7, 0, -7, -3, -4, -4, -4}, + {1, -8, -2, 1, -7, -2, -6, 1, 4, 1, 3, 2, -7, 0, 2, -1, 3, -8, 1, 5, 1, 0, -6, 6, -7, -2, -8, -3, 3, -4, 0, 2}, + {1, -3, -3, 2, 4, -6, 1, -4, -7, -7, 0, -1, 4, -7, 0, -3, 3, -2, -5, -8, 5, 3, -4, 5, 3, -5, 4, 0, -3, -5, 1, -3}, + {6, 4, -8, -5, 1, -5, -6, 3, -7, -2, 0, 1, -4, 3, -8, 5, 2, -2, 0, 1, -2, -5, 6, -2, -5, 1, -4, -1, 4, 1, -4, -7}, + {4, -8, -2, 0, -5, -7, 6, -2, 0, -6, 2, 4, -7, -2, 0, 4, 1, -1, 5, 0, 3, -7, 0, 4, -7, 4, 0, -7, 0, 3, -7, -3}, + {3, 1, 3, 3, 3, 6, -5, -7, -7, -6, -8, 5, -1, 1, 3, 5, 1, 2, 3, -2, -5, 1, -1, -1, 4, -4, 6, -4, 5, -3, -2, 5}, + {-2, -5, 0, 0, -7, -1, -1, -1, 1, -4, 0, -5, 5, -3, -6, -2, -1, 5, 0, -8, 1, -8, -2, -5, -7, -6, 2, -8, -2, 4, -1, 1}, + {-8, 0, 3, -5, -1, -5, 1, -4, 6, -2, -3, 3, -7, -3, 0, -6, 3, -5, 2, -3, -7, -2, -2, 6, -8, 1, -8, -4, 5, 2, 3, 4}}; +const signed char array2[32][32] = {{-1, -3, 4, -3, 1, 5, -2, -4, -6, 6, 4, -3, -6, -1, 5, 3, 0, 6, -8, 2, -4, -2, -3, -6, -8, 4, 3, -5, 2, -6, 6, 2}, + {-4, -3, 2, -1, 2, 3, -2, 0, -2, 1, 4, -2, 3, -6, -7, 5, -8, 6, 1, 6, -4, -2, -3, 3, 1, 1, 5, -1, 4, -4, 1, -5}, + {-1, -4, 5, 5, 5, 0, -2, 4, 6, 4, -4, -4, 2, -7, 6, -6, -8, -3, -5, -7, -3, 6, -3, 5, 5, 1, 3, 4, -4, 5, 5, -3}, + {5, -7, 5, 6, 5, 4, 2, -5, 0, 0, 3, -8, -4, -6, -7, -5, -3, 3, 4, 2, -8, -2, -5, 5, 2, -7, -8, -1, -2, 6, -6, -5}, + {6, -6, -3, -6, 6, 1, 4, 4, -4, 5, -5, -8, 0, -6, -4, 1, 0, -4, -6, 3, -4, -3, 4, 3, 2, -8, -6, 0, -8, -8, 2, 2}, + {3, -8, 2, -5, 1, -4, -1, -5, -2, -7, 6, 5, 2, 3, 5, 2, 1, -1, -7, 2, 4, 3, -6, -2, 5, -3, 5, 4, -4, 1, -5, 1}, + {0, 3, -1, -3, 0, 2, -5, -7, 2, 6, -6, -5, 2, -1, 6, -1, 5, 4, 0, 4, -6, -8, -5, 3, -4, 1, -1, 3, 2, 3, -6, -5}, + {-3, -1, -7, -1, -8, 3, -8, -6, -1, -1, 4, 1, 3, -7, -4, -5, -4, -1, 3, -7, 4, 2, 0, -4, 1, -5, -1, 6, -6, 4, 2, -4}, + {6, 1, 5, -8, -2, -6, -2, 1, 2, 3, -3, 4, -1, -8, 5, -2, -5, -2, -4, -5, -1, 3, -3, -1, -3, 1, -3, 2, -4, -5, 1, -5}, + {0, 5, -1, -4, -3, -5, 3, 2, -5, 4, -2, 5, -7, 0, -1, 4, -4, -5, 3, 2, 6, -1, -5, 6, 4, -8, -8, 1, -2, -3, 1, -7}, + {1, -8, 5, 5, 0, 4, 4, -2, 5, -4, -5, -5, -7, -4, 0, -2, 0, 5, -4, -6, -2, 1, 5, 2, 2, 6, 5, 3, 5, -2, 4, 6}, + {0, 6, 1, 3, -6, -7, 4, 6, -7, -6, 6, 5, -8, 3, 6, -4, 3, 2, 4, -5, -4, -4, -8, 3, -4, 4, -6, -4, -2, 4, -3, 6}, + {5, -8, -3, -6, -8, 0, -6, 0, -4, 3, 5, -5, 4, -8, -3, 6, 6, -6, 2, 3, 3, -4, 0, -6, -3, -3, 6, 4, -4, 0, -5, 1}, + {-8, 5, -1, -1, 1, -8, -6, -3, -5, 0, -3, -6, -4, 2, -7, -4, 5, 3, 2, 6, -4, -5, -3, -6, -5, 5, 2, 2, 5, -6, 4, -6}, + {3, -5, -3, 3, 4, 4, -2, 6, 4, -4, 1, -6, -1, -8, -8, -7, -5, -3, -3, -8, 1, -3, -1, -4, -6, 0, 3, -4, 6, 6, 2, -4}, + {-6, 0, -8, -3, 5, 2, 1, -2, -8, 6, 1, -7, 0, 3, 1, 0, -1, -8, 3, 5, 3, -2, 1, 1, 0, -5, -2, 5, -6, -4, 2, 4}, + {-1, 4, 5, -2, -8, -8, 1, -3, 1, 5, -6, 2, 1, 6, 1, -6, -1, 5, -8, 3, 5, -2, -3, -8, 0, -8, -3, -1, 4, -6, 2, 4}, + {3, -7, -2, -3, 4, 5, 6, 6, 3, 0, -5, -7, -6, -8, -4, 6, -6, 2, 5, -6, -6, -7, 4, 3, 1, -4, 1, 6, -5, -2, -2, 2}, + {1, 3, -2, -4, 2, 6, -7, 5, 1, -2, -8, -6, -8, -5, -1, 3, -8, -5, 3, -3, 2, -2, -7, 5, -1, 5, -3, 0, -4, 2, -5, 4}, + {2, 1, 5, -6, 5, -6, 6, 2, 4, -8, 6, -6, 1, -1, -5, 1, -5, -1, 6, 2, -4, 5, 2, -7, 1, 1, 6, -1, 1, -4, 1, 3}, + {1, -5, 6, -2, -1, -7, -8, -6, -7, 6, -5, -6, 0, -5, 5, -5, -6, -5, 2, -2, 2, 2, 2, -8, -4, -4, 1, 4, -1, 5, 5, 2}, + {3, 1, 3, 6, 6, -5, 1, 4, 6, -6, -8, 3, -6, 4, 1, 2, -5, -3, 5, -6, -2, 4, -8, 0, 5, 4, -4, -6, 0, -4, -6, 6}, + {4, 4, -8, -1, -4, 5, -6, 0, 1, -1, -3, 4, -5, -3, 6, -8, 4, 0, -8, 5, -7, 1, -8, 2, -2, 4, -8, -5, -1, 3, 1, 5}, + {0, -7, -4, -1, 3, -7, 3, -4, -1, -1, -8, 6, 1, -4, -7, -4, -3, -6, 3, -1, -4, 3, 6, 2, 5, 2, 5, 5, -4, -2, -4, -7}, + {6, 5, -4, -3, -4, 4, 1, -2, -6, 3, 2, -6, 3, 1, -1, 2, -7, 3, -8, -7, -2, -6, 0, -8, 5, 4, -6, -5, 3, -3, 6, -7}, + {-4, 5, 2, 1, -2, -5, 2, 5, 4, 6, 5, 3, 4, -8, 3, 0, 5, 2, -7, 0, -6, 6, 4, 5, 6, -5, 0, 5, 1, 1, -4, 0}, + {-2, -1, 3, 0, -4, -2, 2, 4, -4, -7, 1, -4, -3, -1, 5, -6, 0, -3, -7, 1, 2, 2, 6, -8, 0, 4, 0, -2, -5, -6, -4, -1}, + {2, -5, -3, -3, -2, -1, 3, -7, -5, 2, 1, 5, -8, 0, 4, -3, -2, -3, -5, -8, -8, -3, 4, -8, -1, 6, 2, -8, 3, 3, -1, -2}, + {-5, 2, -2, -7, -1, 0, -2, 0, 5, 5, -2, -4, 6, -8, -5, -5, -3, 0, 1, -3, 6, -1, -4, 6, 6, 1, -6, -7, 4, -1, -1, -2}, + {3, 1, 3, 4, 0, 3, 0, 0, -6, -7, -1, -1, 6, -1, -6, 1, -5, -6, 1, 2, -6, -7, 2, 1, 6, -7, -4, 3, 0, -3, -3, -1}, + {-8, -2, 6, -2, -8, -1, -3, 2, -4, -1, -6, -8, 5, -7, 1, -7, 6, -7, -7, -3, -6, 6, -2, -8, -4, -6, -1, -3, 2, -2, -6, 5}, + {-3, 1, 4, 6, -4, 1, -1, -1, -6, 6, -3, -4, 3, 2, -2, -3, -6, -2, 5, -2, 6, -5, 1, -7, -3, -2, -1, 1, 3, -3, 5, 6}}; +signed char resultArray[32][32] = {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}; +signed char answerArray[32][32] = {0}; + +/// @brief 8bit幅の32*32行列乗算 +/// @param array1 +/// @param array2 +/// @param resultArray +void _e8_32x32_matmul(const signed char array1[32][32], const signed char array2[32][32], signed char resultArray[32][32]) { + asm volatile ("vsetvli zero, %0, e8, m1, ta, ma"::"r"(32)); + int i=0, j=0; + for(i=0; i<32; i++) { + // array1の横ベクトルをロード + // v1 = array1[i][*] + asm volatile ("vle8.v v1, (%0)"::"r"(&(array1[i][0]))); + asm volatile ("vmv.s.x v4, zero"); + for(j=0; j<32; j++) { + // array2の縦ベクトルをロード + // v2 = array2[*][j] + asm volatile ("vlse8.v v2, (%0), %1"::"r"(&(array2[0][j])), "r"(32)); + asm volatile ("vmul.vv v3, v1, v2"); + asm volatile ("vredsum.vs v3, v3, v4"); + asm volatile ("vmv.x.s %0, v3":"=r"(resultArray[i][j])); + // resultArray[i*32+j] = tmp; + } + } +} + +int main(int argc, char** argv) { + int i, j, k; + + // clrCounters(); + _e8_32x32_matmul(array1, array2, resultArray); + // showCounters(); + + // clrCounters(); + for(i=0; i<32; i++) { + for(j=0; j<32; j++) { + signed char sum = 0; + for(k=0; k<32; k++) { + signed char temp; + asm volatile ("mulw %0, %1, %2":"=r"(temp):"r"(array1[i][k]), "r"(array2[k][j])); + asm volatile ("addw %0, %1, %2":"=r"(sum):"r"(sum), "r"(temp)); + // sum += array1[i][k] * array2[k][j]; + } + answerArray[i][j] = sum; + } + } + // showCounters(); + _Bool correct = 1; + for(i=0; i<32; i++) { + for(j=0; j<32; j++) { + correct = correct && (resultArray[i][j] == answerArray[i][j]); + } + } + if(correct) { + return 0x00114514; + } else { + return 0xDEADBEEF; + } +} \ No newline at end of file diff --git a/src/main/resources/applications_fpga/vector_matmul_data.mem b/src/main/resources/applications_fpga/vector_matmul_data.mem new file mode 100644 index 00000000..44cf88c6 --- /dev/null +++ b/src/main/resources/applications_fpga/vector_matmul_data.mem @@ -0,0 +1,514 @@ +fd04fdff +fcfe0501 +fd0406fa +0305fffa +02f80600 +fafdfefc +fb0304f8 +0206fa02 +ff02fdfc +00fe0302 +fe0401fe +05f9fa03 +060106f8 +03fdfefc +ff050101 +fb01fc04 +0505fcff +04fe0005 +fcfc0406 +fa06f902 +f9fbfdf8 +05fd06fd +04030105 +fd0505fc +0605f905 +fb020405 +f8030000 +fbf9fafc +020403fd +05fbfef8 +fff8f902 +fbfa06fe +fafdfa06 +04040106 +f8fb05fc +01fcfa00 +03fafc00 +0304fdfc +00faf802 +0202f8f8 +fb02f803 +fbfffc01 +0506f9fe +02050302 +02f9ff01 +fefa0304 +0405fd05 +01fb01fc +fdff0300 +f9fb0200 +fbfa0602 +ff06ff02 +04000405 +03fbf8fa +03ff01fc +fbfa0302 +fff9fffd +faf803f8 +0104ffff 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--git a/src/main/scala/hajime/simple4Stage/Core.scala b/src/main/scala/hajime/simple4Stage/Core.scala index b0df1974..dfd701d2 100644 --- a/src/main/scala/hajime/simple4Stage/Core.scala +++ b/src/main/scala/hajime/simple4Stage/Core.scala @@ -47,7 +47,7 @@ class Core[T <: CpuModule](cpu: Class[T])(implicit params: HajimeCoreParams) ext } object Core extends App { - implicit val params = HajimeCoreParams(useException = false, useVector = true, debug = false) + implicit val params = HajimeCoreParams(useException = false, useVector = true, debug = false, fpga = true) def apply[T <: CpuModule](cpu: Class[T])(implicit params: HajimeCoreParams): Core[T] = { if(cpu == classOf[VectorCpu] && !params.useVector) { throw new Exception("useVector is false") diff --git a/src/main/scala/hajime/vectormodules/VectorExecUnit.scala b/src/main/scala/hajime/vectormodules/VectorExecUnit.scala index 9f6c5144..8dfaa975 100644 --- a/src/main/scala/hajime/vectormodules/VectorExecUnit.scala +++ b/src/main/scala/hajime/vectormodules/VectorExecUnit.scala @@ -71,6 +71,8 @@ abstract class VectorExecUnit(implicit params: HajimeCoreParams) extends Module instInfoReg := instInfoReg } + assert(!(instInfoReg.valid && instInfoReg.bits.vecConf.vl === 0.U), "Zero vl instruction in VectorExecUnit") + import VEU_FUN._ // TODO: vs1Outの判定はMVVではなくベクトルマスク命令か否かで io.readVrf.req.idx := Mux(instInfoReg.bits.vectorDecode.vSource === VSOURCE.MVV.asUInt, idx.head(idx.getWidth-3), idx) diff --git a/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala b/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala index ea0740c6..2d3b573a 100644 --- a/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala +++ b/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala @@ -144,7 +144,7 @@ class Zve64xAppTestForVecCpu extends AnyFlatSpec with ChiselScalatestTester { "vredsum", ) val applicationTest = Seq( - "vector_median", "vector_matmul" + "vector_median", // "vector_matmul" ) val zve64xTestList: Seq[String] = ldstTest ++ arithmeticTest ++ applicationTest for (e <- zve64xTestList) { @@ -154,4 +154,28 @@ class Zve64xAppTestForVecCpu extends AnyFlatSpec with ChiselScalatestTester { } } } +} + +class FpgaTestForVecCpu extends AnyFlatSpec with ChiselScalatestTester { + def _executeTest[T <: CpuModule](dut: Core_and_cache[T], testName: String, testType: String): Unit = { + println(s"test $testName:") + fork { + initialiseMemWithAxi(s"src/main/resources/applications_${testType}/${testName}_inst.mem", dut.io.imem_initialiseAXI, dut.io.icache_initialising, dut.clock, 0) + }.fork { + initialiseMemWithAxi(s"src/main/resources/applications_${testType}/${testName}_data.mem", dut.io.dmem_initialiseAXI, dut.io.dcache_initialising, dut.clock, 0x4000) + }.join() + dut.clock.setTimeout(0) + dut.io.reset_vector.poke(0.U) + dut.io.hartid.poke(0.U) + + for(_ <- 0 until 1048576) { + dut.clock.step() + } + println(dut.io.toHost.bits.peekInt()) + } + it should "Vector CPU execute matmul for FPGA" in { + test(new Core_and_cache(useVector = true, cpu = classOf[VectorCpu])).withAnnotations(Seq(WriteVcdAnnotation, IcarusBackendAnnotation)) { dut => + _executeTest(dut, "vector_matmul", "fpga") + } + } } \ No newline at end of file From 403d4c6c275ee474e359ad9b2da5ee2e6cf94cf9 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Fri, 1 Dec 2023 19:23:10 +0900 Subject: [PATCH 10/13] a --- fpga/Core.sv | 11822 +++++++++++++++++++++++++++++++++ fpga/Dcache_for_Verilator.sv | 155 + fpga/Icache_for_Verilator.sv | 120 + fpga/fpga.v | 58 +- 4 files changed, 12150 insertions(+), 5 deletions(-) create mode 100644 fpga/Core.sv create mode 100644 fpga/Dcache_for_Verilator.sv create mode 100644 fpga/Icache_for_Verilator.sv diff --git a/fpga/Core.sv b/fpga/Core.sv new file mode 100644 index 00000000..5bc431b1 --- /dev/null +++ b/fpga/Core.sv @@ -0,0 +1,11822 @@ +// Generated by CIRCT firtool-1.38.0 +// Standard header to adapt well known macros to our needs. + +// Users can define 'PRINTF_COND' to add an extra gate to prints. +`ifndef PRINTF_COND_ + `ifdef PRINTF_COND + `define PRINTF_COND_ (`PRINTF_COND) + `else // PRINTF_COND + `define PRINTF_COND_ 1 + `endif // PRINTF_COND +`endif // not def PRINTF_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// VCS coverage exclude_file +module vrf_combMem( + input [4:0] R0_addr, + input R0_en, + R0_clk, + input [4:0] R1_addr, + input R1_en, + R1_clk, + input [4:0] R2_addr, + input R2_en, + R2_clk, + input [4:0] R3_addr, + input R3_en, + R3_clk, + input [4:0] R4_addr, + input R4_en, + R4_clk, + input [4:0] R5_addr, + input R5_en, + R5_clk, + input [4:0] R6_addr, + input R6_en, + R6_clk, + input [4:0] R7_addr, + input R7_en, + R7_clk, + input [4:0] R8_addr, + input R8_en, + R8_clk, + input [4:0] R9_addr, + input R9_en, + R9_clk, + input [4:0] R10_addr, + input R10_en, + R10_clk, + input [4:0] R11_addr, + input R11_en, + R11_clk, + input [4:0] W0_addr, + input W0_en, + W0_clk, + input [255:0] W0_data, + input [31:0] W0_mask, + input [4:0] W1_addr, + input W1_en, + W1_clk, + input [255:0] W1_data, + input [31:0] W1_mask, + input [4:0] W2_addr, + input W2_en, + W2_clk, + input [255:0] W2_data, + input [31:0] W2_mask, + output [255:0] R0_data, + R1_data, + R2_data, + R3_data, + R4_data, + R5_data, + R6_data, + R7_data, + R8_data, + R9_data, + R10_data, + R11_data +); + + (* ram_style = "distributed" *) + reg [255:0] Memory[0:31]; + always @(posedge W0_clk) begin + if (W0_en & W0_mask[0]) + Memory[W0_addr][32'h0 +: 8] <= W0_data[7:0]; + if (W0_en & W0_mask[1]) + Memory[W0_addr][32'h8 +: 8] <= W0_data[15:8]; + if (W0_en & W0_mask[2]) + Memory[W0_addr][32'h10 +: 8] <= W0_data[23:16]; + if (W0_en & W0_mask[3]) + Memory[W0_addr][32'h18 +: 8] <= W0_data[31:24]; + if (W0_en & W0_mask[4]) + Memory[W0_addr][32'h20 +: 8] <= W0_data[39:32]; + if (W0_en & W0_mask[5]) + Memory[W0_addr][32'h28 +: 8] <= W0_data[47:40]; + if (W0_en & W0_mask[6]) + Memory[W0_addr][32'h30 +: 8] <= W0_data[55:48]; + if (W0_en & W0_mask[7]) + Memory[W0_addr][32'h38 +: 8] <= W0_data[63:56]; + if (W0_en & W0_mask[8]) + Memory[W0_addr][32'h40 +: 8] <= W0_data[71:64]; + if (W0_en & W0_mask[9]) + Memory[W0_addr][32'h48 +: 8] <= W0_data[79:72]; + if (W0_en & W0_mask[10]) + Memory[W0_addr][32'h50 +: 8] <= W0_data[87:80]; + if (W0_en & W0_mask[11]) + Memory[W0_addr][32'h58 +: 8] <= W0_data[95:88]; + if (W0_en & W0_mask[12]) + Memory[W0_addr][32'h60 +: 8] <= W0_data[103:96]; + if (W0_en & W0_mask[13]) + Memory[W0_addr][32'h68 +: 8] <= W0_data[111:104]; + if (W0_en & W0_mask[14]) + Memory[W0_addr][32'h70 +: 8] <= W0_data[119:112]; + if (W0_en & W0_mask[15]) + Memory[W0_addr][32'h78 +: 8] <= W0_data[127:120]; + if (W0_en & W0_mask[16]) + Memory[W0_addr][32'h80 +: 8] <= W0_data[135:128]; + if (W0_en & W0_mask[17]) + Memory[W0_addr][32'h88 +: 8] <= W0_data[143:136]; + if (W0_en & W0_mask[18]) + Memory[W0_addr][32'h90 +: 8] <= W0_data[151:144]; + if (W0_en & W0_mask[19]) + Memory[W0_addr][32'h98 +: 8] <= W0_data[159:152]; + if (W0_en & W0_mask[20]) + Memory[W0_addr][32'hA0 +: 8] <= W0_data[167:160]; + if (W0_en & W0_mask[21]) + Memory[W0_addr][32'hA8 +: 8] <= W0_data[175:168]; + if (W0_en & W0_mask[22]) + Memory[W0_addr][32'hB0 +: 8] <= W0_data[183:176]; + if (W0_en & W0_mask[23]) + Memory[W0_addr][32'hB8 +: 8] <= W0_data[191:184]; + if (W0_en & W0_mask[24]) + Memory[W0_addr][32'hC0 +: 8] <= W0_data[199:192]; + if (W0_en & W0_mask[25]) + Memory[W0_addr][32'hC8 +: 8] <= W0_data[207:200]; + if (W0_en & W0_mask[26]) + Memory[W0_addr][32'hD0 +: 8] <= W0_data[215:208]; + if (W0_en & W0_mask[27]) + Memory[W0_addr][32'hD8 +: 8] <= W0_data[223:216]; + if (W0_en & W0_mask[28]) + Memory[W0_addr][32'hE0 +: 8] <= W0_data[231:224]; + if (W0_en & W0_mask[29]) + Memory[W0_addr][32'hE8 +: 8] <= W0_data[239:232]; + if (W0_en & W0_mask[30]) + Memory[W0_addr][32'hF0 +: 8] <= W0_data[247:240]; + if (W0_en & W0_mask[31]) + Memory[W0_addr][32'hF8 +: 8] <= W0_data[255:248]; + if (W1_en & W1_mask[0]) + Memory[W1_addr][32'h0 +: 8] <= W1_data[7:0]; + if (W1_en & W1_mask[1]) + Memory[W1_addr][32'h8 +: 8] <= W1_data[15:8]; + if (W1_en & W1_mask[2]) + Memory[W1_addr][32'h10 +: 8] <= W1_data[23:16]; + if (W1_en & W1_mask[3]) + Memory[W1_addr][32'h18 +: 8] <= W1_data[31:24]; + if (W1_en & W1_mask[4]) + Memory[W1_addr][32'h20 +: 8] <= W1_data[39:32]; + if (W1_en & W1_mask[5]) + Memory[W1_addr][32'h28 +: 8] <= W1_data[47:40]; + if (W1_en & W1_mask[6]) + Memory[W1_addr][32'h30 +: 8] <= W1_data[55:48]; + if (W1_en & W1_mask[7]) + Memory[W1_addr][32'h38 +: 8] <= W1_data[63:56]; + if (W1_en & W1_mask[8]) + Memory[W1_addr][32'h40 +: 8] <= W1_data[71:64]; + if (W1_en & W1_mask[9]) + Memory[W1_addr][32'h48 +: 8] <= W1_data[79:72]; + if (W1_en & W1_mask[10]) + Memory[W1_addr][32'h50 +: 8] <= W1_data[87:80]; + if (W1_en & W1_mask[11]) + Memory[W1_addr][32'h58 +: 8] <= W1_data[95:88]; + if (W1_en & W1_mask[12]) + Memory[W1_addr][32'h60 +: 8] <= W1_data[103:96]; + if (W1_en & W1_mask[13]) + Memory[W1_addr][32'h68 +: 8] <= W1_data[111:104]; + if (W1_en & W1_mask[14]) + Memory[W1_addr][32'h70 +: 8] <= W1_data[119:112]; + if (W1_en & W1_mask[15]) + Memory[W1_addr][32'h78 +: 8] <= W1_data[127:120]; + if (W1_en & W1_mask[16]) + Memory[W1_addr][32'h80 +: 8] <= W1_data[135:128]; + if (W1_en & W1_mask[17]) + Memory[W1_addr][32'h88 +: 8] <= W1_data[143:136]; + if (W1_en & W1_mask[18]) + Memory[W1_addr][32'h90 +: 8] <= W1_data[151:144]; + if (W1_en & W1_mask[19]) + Memory[W1_addr][32'h98 +: 8] <= W1_data[159:152]; + if (W1_en & W1_mask[20]) + Memory[W1_addr][32'hA0 +: 8] <= W1_data[167:160]; + if (W1_en & W1_mask[21]) + Memory[W1_addr][32'hA8 +: 8] <= W1_data[175:168]; + if (W1_en & W1_mask[22]) + Memory[W1_addr][32'hB0 +: 8] <= W1_data[183:176]; + if (W1_en & W1_mask[23]) + Memory[W1_addr][32'hB8 +: 8] <= W1_data[191:184]; + if (W1_en & W1_mask[24]) + Memory[W1_addr][32'hC0 +: 8] <= W1_data[199:192]; + if (W1_en & W1_mask[25]) + Memory[W1_addr][32'hC8 +: 8] <= W1_data[207:200]; + if (W1_en & W1_mask[26]) + Memory[W1_addr][32'hD0 +: 8] <= W1_data[215:208]; + if (W1_en & W1_mask[27]) + Memory[W1_addr][32'hD8 +: 8] <= W1_data[223:216]; + if (W1_en & W1_mask[28]) + Memory[W1_addr][32'hE0 +: 8] <= W1_data[231:224]; + if (W1_en & W1_mask[29]) + Memory[W1_addr][32'hE8 +: 8] <= W1_data[239:232]; + if (W1_en & W1_mask[30]) + Memory[W1_addr][32'hF0 +: 8] <= W1_data[247:240]; + if (W1_en & W1_mask[31]) + Memory[W1_addr][32'hF8 +: 8] <= W1_data[255:248]; + if (W2_en & W2_mask[0]) + Memory[W2_addr][32'h0 +: 8] <= W2_data[7:0]; + if (W2_en & W2_mask[1]) + Memory[W2_addr][32'h8 +: 8] <= W2_data[15:8]; + if (W2_en & W2_mask[2]) + Memory[W2_addr][32'h10 +: 8] <= W2_data[23:16]; + if (W2_en & W2_mask[3]) + Memory[W2_addr][32'h18 +: 8] <= W2_data[31:24]; + if (W2_en & W2_mask[4]) + Memory[W2_addr][32'h20 +: 8] <= W2_data[39:32]; + if (W2_en & W2_mask[5]) + Memory[W2_addr][32'h28 +: 8] <= W2_data[47:40]; + if (W2_en & W2_mask[6]) + Memory[W2_addr][32'h30 +: 8] <= W2_data[55:48]; + if (W2_en & W2_mask[7]) + Memory[W2_addr][32'h38 +: 8] <= W2_data[63:56]; + if (W2_en & W2_mask[8]) + Memory[W2_addr][32'h40 +: 8] <= W2_data[71:64]; + if (W2_en & W2_mask[9]) + Memory[W2_addr][32'h48 +: 8] <= W2_data[79:72]; + if (W2_en & W2_mask[10]) + Memory[W2_addr][32'h50 +: 8] <= W2_data[87:80]; + if (W2_en & W2_mask[11]) + Memory[W2_addr][32'h58 +: 8] <= W2_data[95:88]; + if (W2_en & W2_mask[12]) + Memory[W2_addr][32'h60 +: 8] <= W2_data[103:96]; + if (W2_en & W2_mask[13]) + Memory[W2_addr][32'h68 +: 8] <= W2_data[111:104]; + if (W2_en & W2_mask[14]) + Memory[W2_addr][32'h70 +: 8] <= W2_data[119:112]; + if (W2_en & W2_mask[15]) + Memory[W2_addr][32'h78 +: 8] <= W2_data[127:120]; + if (W2_en & W2_mask[16]) + Memory[W2_addr][32'h80 +: 8] <= W2_data[135:128]; + if (W2_en & W2_mask[17]) + Memory[W2_addr][32'h88 +: 8] <= W2_data[143:136]; + if (W2_en & W2_mask[18]) + Memory[W2_addr][32'h90 +: 8] <= W2_data[151:144]; + if (W2_en & W2_mask[19]) + Memory[W2_addr][32'h98 +: 8] <= W2_data[159:152]; + if (W2_en & W2_mask[20]) + Memory[W2_addr][32'hA0 +: 8] <= W2_data[167:160]; + if (W2_en & W2_mask[21]) + Memory[W2_addr][32'hA8 +: 8] <= W2_data[175:168]; + if (W2_en & W2_mask[22]) + Memory[W2_addr][32'hB0 +: 8] <= W2_data[183:176]; + if (W2_en & W2_mask[23]) + Memory[W2_addr][32'hB8 +: 8] <= W2_data[191:184]; + if (W2_en & W2_mask[24]) + Memory[W2_addr][32'hC0 +: 8] <= W2_data[199:192]; + if (W2_en & W2_mask[25]) + Memory[W2_addr][32'hC8 +: 8] <= W2_data[207:200]; + if (W2_en & W2_mask[26]) + Memory[W2_addr][32'hD0 +: 8] <= W2_data[215:208]; + if (W2_en & W2_mask[27]) + Memory[W2_addr][32'hD8 +: 8] <= W2_data[223:216]; + if (W2_en & W2_mask[28]) + Memory[W2_addr][32'hE0 +: 8] <= W2_data[231:224]; + if (W2_en & W2_mask[29]) + Memory[W2_addr][32'hE8 +: 8] <= W2_data[239:232]; + if (W2_en & W2_mask[30]) + Memory[W2_addr][32'hF0 +: 8] <= W2_data[247:240]; + if (W2_en & W2_mask[31]) + Memory[W2_addr][32'hF8 +: 8] <= W2_data[255:248]; + end // always @(posedge) + assign R0_data = R0_en ? Memory[R0_addr] : 256'bx; + assign R1_data = R1_en ? Memory[R1_addr] : 256'bx; + assign R2_data = R2_en ? Memory[R2_addr] : 256'bx; + assign R3_data = R3_en ? Memory[R3_addr] : 256'bx; + assign R4_data = R4_en ? Memory[R4_addr] : 256'bx; + assign R5_data = R5_en ? Memory[R5_addr] : 256'bx; + assign R6_data = R6_en ? Memory[R6_addr] : 256'bx; + assign R7_data = R7_en ? Memory[R7_addr] : 256'bx; + assign R8_data = R8_en ? Memory[R8_addr] : 256'bx; + assign R9_data = R9_en ? Memory[R9_addr] : 256'bx; + assign R10_data = R10_en ? Memory[R10_addr] : 256'bx; + assign R11_data = R11_en ? Memory[R11_addr] : 256'bx; +endmodule + +module Frontend( + input clock, + reset, + io_cpu_req_valid, + input [63:0] io_cpu_req_bits_pc, + input io_cpu_resp_ready, + io_icache_axi4lite_ar_ready, + io_icache_axi4lite_r_valid, + input [31:0] io_icache_axi4lite_r_bits_data, + input [63:0] io_reset_vector, + output io_cpu_resp_valid, + output [63:0] io_cpu_resp_bits_pc_addr, + output [31:0] io_cpu_resp_bits_inst_bits, + output io_cpu_resp_bits_exceptionSignals_valid, + output [63:0] io_cpu_resp_bits_exceptionSignals_bits, + output io_icache_axi4lite_ar_valid, + output [63:0] io_icache_axi4lite_ar_bits_addr, + output io_icache_axi4lite_r_ready +); + + reg [63:0] pc_reg_addr; + wire [63:0] _addr_req_to_axi_ar_T_1 = pc_reg_addr + 64'h4; + wire _GEN = + io_icache_axi4lite_ar_ready & io_icache_axi4lite_r_valid & io_cpu_resp_ready; + wire instAccessFault = pc_reg_addr > 64'h1FFC; + always @(posedge clock) begin + if (reset) + pc_reg_addr <= io_reset_vector; + else if (io_icache_axi4lite_r_valid | io_cpu_resp_ready) begin + if (io_cpu_req_valid) + pc_reg_addr <= io_cpu_req_bits_pc; + else if (_GEN) + pc_reg_addr <= _addr_req_to_axi_ar_T_1; + end + end // always @(posedge) + assign io_cpu_resp_valid = io_icache_axi4lite_r_valid; + assign io_cpu_resp_bits_pc_addr = pc_reg_addr; + assign io_cpu_resp_bits_inst_bits = io_icache_axi4lite_r_bits_data; + assign io_cpu_resp_bits_exceptionSignals_valid = + instAccessFault | (|(pc_reg_addr[1:0])); + assign io_cpu_resp_bits_exceptionSignals_bits = {63'h0, instAccessFault}; + assign io_icache_axi4lite_ar_valid = io_cpu_resp_ready; + assign io_icache_axi4lite_ar_bits_addr = + io_cpu_req_valid ? io_cpu_req_bits_pc : _GEN ? _addr_req_to_axi_ar_T_1 : pc_reg_addr; + assign io_icache_axi4lite_r_ready = io_cpu_resp_ready; +endmodule + +module Decoder( + input [31:0] io_inst_bits, + output io_out_valid, + output [3:0] io_out_bits_branch, + output [1:0] io_out_bits_value1, + output [2:0] io_out_bits_value2, + output [3:0] io_out_bits_arithmetic_funct, + output io_out_bits_alu_flag, + io_out_bits_op32, + output [2:0] io_out_bits_writeback_selector, + output [1:0] io_out_bits_memory_function, + io_out_bits_memory_length, + output io_out_bits_mem_sext, + output [2:0] io_out_bits_csr_funct, + output io_out_bits_fence, + io_out_bits_vector +); + + wire [16:0] _GEN = {io_inst_bits[31:25], io_inst_bits[14:12], io_inst_bits[6:0]}; + wire _csignals_T_15 = _GEN == 17'h33; + wire _csignals_T_17 = _GEN == 17'h8033; + wire _csignals_T_19 = _GEN == 17'hB3; + wire _csignals_T_21 = _GEN == 17'h133; + wire _csignals_T_23 = _GEN == 17'h1B3; + wire _csignals_T_25 = _GEN == 17'h233; + wire _csignals_T_27 = _GEN == 17'h2B3; + wire _csignals_T_29 = _GEN == 17'h82B3; + wire _csignals_T_31 = _GEN == 17'h333; + wire _csignals_T_33 = _GEN == 17'h3B3; + wire [9:0] _GEN_0 = {io_inst_bits[14:12], io_inst_bits[6:0]}; + wire _csignals_T_35 = _GEN_0 == 10'h13; + wire _csignals_T_37 = _GEN_0 == 10'h113; + wire _csignals_T_39 = _GEN_0 == 10'h193; + wire _csignals_T_41 = _GEN_0 == 10'h213; + wire _csignals_T_43 = _GEN_0 == 10'h313; + wire _csignals_T_45 = _GEN_0 == 10'h393; + wire [15:0] _GEN_1 = {io_inst_bits[31:26], io_inst_bits[14:12], io_inst_bits[6:0]}; + wire _csignals_T_47 = _GEN_1 == 16'h93; + wire _csignals_T_49 = _GEN_1 == 16'h293; + wire _csignals_T_51 = _GEN_1 == 16'h4293; + wire _csignals_T_53 = _GEN_0 == 10'h3; + wire _csignals_T_55 = _GEN_0 == 10'h83; + wire _csignals_T_57 = _GEN_0 == 10'h103; + wire _csignals_T_59 = _GEN_0 == 10'h203; + wire _csignals_T_61 = _GEN_0 == 10'h283; + wire _csignals_T_63 = _GEN_0 == 10'h67; + wire _csignals_T_65 = _GEN_0 == 10'h23; + wire _csignals_T_67 = _GEN_0 == 10'hA3; + wire _csignals_T_69 = _GEN_0 == 10'h123; + wire _csignals_T_71 = _GEN_0 == 10'h63; + wire _csignals_T_73 = _GEN_0 == 10'hE3; + wire _csignals_T_75 = _GEN_0 == 10'h263; + wire _csignals_T_77 = _GEN_0 == 10'h2E3; + wire _csignals_T_79 = _GEN_0 == 10'h363; + wire _csignals_T_81 = _GEN_0 == 10'h3E3; + wire _csignals_T_83 = io_inst_bits[6:0] == 7'h37; + wire _csignals_T_85 = io_inst_bits[6:0] == 7'h17; + wire _csignals_T_87 = io_inst_bits[6:0] == 7'h6F; + wire _csignals_T_2589 = _GEN_0 == 10'hF; + wire _csignals_T_91 = io_inst_bits == 32'h73; + wire _csignals_T_93 = io_inst_bits == 32'h30200073; + wire _csignals_T_95 = io_inst_bits == 32'h100073; + wire _csignals_T_97 = _GEN == 17'h3B; + wire _csignals_T_99 = _GEN == 17'h803B; + wire _csignals_T_101 = _GEN == 17'hBB; + wire _csignals_T_103 = _GEN == 17'h2BB; + wire _csignals_T_105 = _GEN == 17'h82BB; + wire _csignals_T_107 = _GEN_0 == 10'h1B; + wire _csignals_T_109 = _GEN == 17'h9B; + wire _csignals_T_111 = _GEN == 17'h29B; + wire _csignals_T_1359 = _GEN == 17'h829B; + wire _csignals_T_2228 = _GEN_0 == 10'h183; + wire _csignals_T_117 = _GEN_0 == 10'h303; + wire _csignals_T_119 = _GEN_0 == 10'h1A3; + wire _csignals_T_121 = _GEN_0 == 10'hF3; + wire _csignals_T_123 = _GEN_0 == 10'h173; + wire _csignals_T_125 = _GEN_0 == 10'h1F3; + wire _csignals_T_127 = _GEN_0 == 10'h2F3; + wire _csignals_T_129 = _GEN_0 == 10'h373; + wire _csignals_T_2394 = _GEN_0 == 10'h3F3; + wire _csignals_T_133 = _GEN == 17'h433; + wire _csignals_T_135 = _GEN == 17'h4B3; + wire _csignals_T_137 = _GEN == 17'h533; + wire _csignals_T_139 = _GEN == 17'h5B3; + wire _csignals_T_1519 = _GEN == 17'h43B; + wire _csignals_T_143 = + {io_inst_bits[31], io_inst_bits[14:12], io_inst_bits[6:0]} == 11'h3D7; + wire _csignals_T_145 = + {io_inst_bits[31:30], io_inst_bits[14:12], io_inst_bits[6:0]} == 12'hFD7; + wire _csignals_T_147 = _GEN == 17'h103D7; + wire [20:0] _GEN_2 = + {io_inst_bits[31:26], io_inst_bits[24:20], io_inst_bits[14:12], io_inst_bits[6:0]}; + wire _csignals_T_149 = _GEN_2 == 21'h7; + wire _csignals_T_151 = _GEN_2 == 21'h287; + wire _csignals_T_153 = _GEN_2 == 21'h307; + wire _csignals_T_155 = _GEN_2 == 21'h387; + wire _csignals_T_157 = _GEN_2 == 21'h27; + wire _csignals_T_159 = _GEN_2 == 21'h2A7; + wire _csignals_T_161 = _GEN_2 == 21'h327; + wire _csignals_T_163 = _GEN_2 == 21'h3A7; + wire _csignals_T_165 = _GEN_1 == 16'h807; + wire _csignals_T_167 = _GEN_1 == 16'hA87; + wire _csignals_T_169 = _GEN_1 == 16'hB07; + wire _csignals_T_171 = _GEN_1 == 16'hB87; + wire _csignals_T_173 = _GEN_1 == 16'h827; + wire _csignals_T_175 = _GEN_1 == 16'hAA7; + wire _csignals_T_177 = _GEN_1 == 16'hB27; + wire _csignals_T_978 = _GEN_1 == 16'hBA7; + wire _csignals_T_181 = _GEN_1 == 16'hC07; + wire _csignals_T_183 = _GEN_1 == 16'hE87; + wire _csignals_T_185 = _GEN_1 == 16'hF07; + wire _csignals_T_187 = _GEN_1 == 16'hF87; + wire _csignals_T_189 = _GEN_1 == 16'hC27; + wire _csignals_T_191 = _GEN_1 == 16'hEA7; + wire _csignals_T_193 = _GEN_1 == 16'hF27; + wire _csignals_T_1144 = _GEN_1 == 16'hFA7; + wire _csignals_T_197 = _GEN_1 == 16'h57; + wire _csignals_T_199 = _GEN_1 == 16'h257; + wire _csignals_T_201 = _GEN_1 == 16'h1D7; + wire _csignals_T_203 = _GEN_1 == 16'h857; + wire _csignals_T_205 = _GEN_1 == 16'hA57; + wire _csignals_T_207 = _GEN_1 == 16'hE57; + wire _csignals_T_209 = _GEN_1 == 16'hDD7; + wire _csignals_T_211 = _GEN_1 == 16'h2457; + wire _csignals_T_213 = _GEN_1 == 16'h2657; + wire _csignals_T_215 = _GEN_1 == 16'h25D7; + wire _csignals_T_217 = _GEN_1 == 16'h2857; + wire _csignals_T_219 = _GEN_1 == 16'h2A57; + wire _csignals_T_221 = _GEN_1 == 16'h29D7; + wire _csignals_T_223 = _GEN_1 == 16'h2C57; + wire _csignals_T_225 = _GEN_1 == 16'h2E57; + wire _csignals_T_227 = _GEN_1 == 16'h2DD7; + wire _csignals_T_229 = _GEN_1 == 16'h6057; + wire _csignals_T_231 = _GEN_1 == 16'h6257; + wire _csignals_T_233 = _GEN_1 == 16'h61D7; + wire _csignals_T_235 = _GEN_1 == 16'h6457; + wire _csignals_T_237 = _GEN_1 == 16'h6657; + wire _csignals_T_239 = _GEN_1 == 16'h65D7; + wire _csignals_T_241 = _GEN_1 == 16'h6857; + wire _csignals_T_243 = _GEN_1 == 16'h6A57; + wire _csignals_T_245 = _GEN_1 == 16'h6C57; + wire _csignals_T_247 = _GEN_1 == 16'h6E57; + wire _csignals_T_249 = _GEN_1 == 16'h7057; + wire _csignals_T_251 = _GEN_1 == 16'h7257; + wire _csignals_T_253 = _GEN_1 == 16'h71D7; + wire _csignals_T_255 = _GEN_1 == 16'h7457; + wire _csignals_T_257 = _GEN_1 == 16'h7657; + wire _csignals_T_259 = _GEN_1 == 16'h75D7; + wire _csignals_T_261 = _GEN_1 == 16'h7A57; + wire _csignals_T_263 = _GEN_1 == 16'h79D7; + wire _csignals_T_265 = _GEN_1 == 16'h7E57; + wire _csignals_T_267 = _GEN_1 == 16'h7DD7; + wire _csignals_T_269 = _GEN_1 == 16'h1057; + wire _csignals_T_271 = _GEN_1 == 16'h1257; + wire _csignals_T_273 = _GEN_1 == 16'h1457; + wire _csignals_T_275 = _GEN_1 == 16'h1657; + wire _csignals_T_277 = _GEN_1 == 16'h1857; + wire _csignals_T_279 = _GEN_1 == 16'h1A57; + wire _csignals_T_281 = _GEN_1 == 16'h1C57; + wire _csignals_T_283 = _GEN_1 == 16'h1E57; + wire _csignals_T_285 = _GEN == 17'hB857; + wire _csignals_T_287 = _GEN == 17'hBA57; + wire _csignals_T_289 = _GEN == 17'hB9D7; + wire [21:0] _GEN_3 = {io_inst_bits[31:20], io_inst_bits[14:12], io_inst_bits[6:0]}; + wire _csignals_T_291 = _GEN_3 == 22'h178057; + wire _csignals_T_293 = _GEN_3 == 22'h178257; + wire _csignals_T_295 = _GEN_3 == 22'h1781D7; + wire _csignals_T_297 = _GEN == 17'hCD57; + wire _csignals_T_299 = _GEN == 17'hED57; + wire _csignals_T_301 = _GEN == 17'hC557; + wire _csignals_T_303 = _GEN == 17'hDD57; + wire _csignals_T_305 = _GEN == 17'hD557; + wire _csignals_T_307 = _GEN == 17'hF557; + wire _csignals_T_309 = _GEN == 17'hE557; + wire _csignals_T_311 = _GEN == 17'hFD57; + wire _csignals_T_313 = _GEN_1 == 16'h9557; + wire _csignals_T_315 = _GEN_1 == 16'h9757; + wire _csignals_T_317 = _GEN_1 == 16'h9D57; + wire _csignals_T_319 = _GEN_1 == 16'h9F57; + wire _csignals_T_321 = _GEN_1 == 16'h9157; + wire _csignals_T_323 = _GEN_1 == 16'h9357; + wire _csignals_T_325 = _GEN_1 == 16'h9957; + wire _csignals_T_327 = _GEN_1 == 16'h9B57; + wire _csignals_T_329 = _GEN_1 == 16'hB557; + wire _csignals_T_331 = _GEN_1 == 16'hB757; + wire _csignals_T_333 = _GEN_1 == 16'hBD57; + wire _csignals_T_335 = _GEN_1 == 16'hBF57; + wire _csignals_T_337 = _GEN_1 == 16'hA557; + wire _csignals_T_339 = _GEN_1 == 16'hA757; + wire _csignals_T_341 = _GEN_1 == 16'hAD57; + wire _csignals_T_343 = _GEN_1 == 16'hAF57; + wire _csignals_T_345 = _GEN_1 == 16'h157; + wire _csignals_T_347 = _GEN_1 == 16'h1957; + wire _csignals_T_349 = _GEN_1 == 16'h1D57; + wire _csignals_T_351 = _GEN_1 == 16'h1157; + wire _csignals_T_353 = _GEN_1 == 16'h1557; + wire _csignals_T_355 = _GEN_1 == 16'h557; + wire _csignals_T_357 = _GEN_1 == 16'h957; + wire _csignals_T_359 = _GEN_1 == 16'hD57; + wire _csignals_T_361 = + {io_inst_bits[31:25], io_inst_bits[19:12], io_inst_bits[6:0]} == 22'h108157; + wire _csignals_T_2626 = _GEN_3 == 22'h108357; + wire _GEN_4 = + _csignals_T_345 | _csignals_T_347 | _csignals_T_349 | _csignals_T_351 + | _csignals_T_353 | _csignals_T_355 | _csignals_T_357 | _csignals_T_359 + | _csignals_T_361; + wire _GEN_5 = + _csignals_T_143 | _csignals_T_145 | _csignals_T_147 | _csignals_T_149 + | _csignals_T_151 | _csignals_T_153 | _csignals_T_155 | _csignals_T_157 + | _csignals_T_159 | _csignals_T_161 | _csignals_T_163 | _csignals_T_165 + | _csignals_T_167 | _csignals_T_169 | _csignals_T_171 | _csignals_T_173 + | _csignals_T_175 | _csignals_T_177 | _csignals_T_978 | _csignals_T_181 + | _csignals_T_183 | _csignals_T_185 | _csignals_T_187 | _csignals_T_189 + | _csignals_T_191 | _csignals_T_193 | _csignals_T_1144 | _csignals_T_197 + | _csignals_T_199 | _csignals_T_201 | _csignals_T_203 | _csignals_T_205 + | _csignals_T_207 | _csignals_T_209 | _csignals_T_211 | _csignals_T_213 + | _csignals_T_215 | _csignals_T_217 | _csignals_T_219 | _csignals_T_221 + | _csignals_T_223 | _csignals_T_225 | _csignals_T_227 | _csignals_T_229 + | _csignals_T_231 | _csignals_T_233 | _csignals_T_235 | _csignals_T_237 + | _csignals_T_239 | _csignals_T_241 | _csignals_T_243 | _csignals_T_245 + | _csignals_T_247 | _csignals_T_249 | _csignals_T_251 | _csignals_T_253 + | _csignals_T_255 | _csignals_T_257 | _csignals_T_259 | _csignals_T_261 + | _csignals_T_263 | _csignals_T_265 | _csignals_T_267 | _csignals_T_269 + | _csignals_T_271 | _csignals_T_273 | _csignals_T_275 | _csignals_T_277 + | _csignals_T_279 | _csignals_T_281 | _csignals_T_283 | _csignals_T_285 + | _csignals_T_287 | _csignals_T_289 | _csignals_T_291 | _csignals_T_293 + | _csignals_T_295 | _csignals_T_297 | _csignals_T_299 | _csignals_T_301 + | _csignals_T_303 | _csignals_T_305 | _csignals_T_307 | _csignals_T_309 + | _csignals_T_311 | _csignals_T_313 | _csignals_T_315 | _csignals_T_317 + | _csignals_T_319 | _csignals_T_321 | _csignals_T_323 | _csignals_T_325 + | _csignals_T_327 | _csignals_T_329 | _csignals_T_331 | _csignals_T_333 + | _csignals_T_335 | _csignals_T_337 | _csignals_T_339 | _csignals_T_341 + | _csignals_T_343 | _GEN_4; + wire _GEN_6 = _csignals_T_83 | _csignals_T_85; + wire _GEN_7 = _csignals_T_65 | _csignals_T_67 | _csignals_T_69; + wire _GEN_8 = + _csignals_T_53 | _csignals_T_55 | _csignals_T_57 | _csignals_T_59 | _csignals_T_61; + wire _GEN_9 = + _csignals_T_189 | _csignals_T_191 | _csignals_T_193 | _csignals_T_1144; + wire _GEN_10 = _csignals_T_127 | _csignals_T_129 | _csignals_T_2394; + wire _GEN_11 = + _csignals_T_2589 | _csignals_T_91 | _csignals_T_93 | _csignals_T_95; + wire _GEN_12 = _csignals_T_87 | _GEN_11; + wire _GEN_13 = _csignals_T_79 | _csignals_T_81; + wire _GEN_14 = + _csignals_T_71 | _csignals_T_73 | _csignals_T_75 | _csignals_T_77 | _GEN_13; + wire _GEN_15 = _csignals_T_65 | _csignals_T_67 | _csignals_T_69 | _GEN_14; + wire _GEN_16 = + _csignals_T_157 | _csignals_T_159 | _csignals_T_161 | _csignals_T_163; + wire _GEN_17 = + _csignals_T_133 | _csignals_T_135 | _csignals_T_137 | _csignals_T_139 + | _csignals_T_1519; + wire _GEN_18 = _csignals_T_121 | _csignals_T_123 | _csignals_T_125 | _GEN_10; + wire _GEN_19 = _csignals_T_2228 | _csignals_T_117; + wire _GEN_20 = _csignals_T_103 | _csignals_T_105; + wire _GEN_21 = _csignals_T_143 | _csignals_T_145 | _csignals_T_147; + wire _GEN_22 = _csignals_T_2228 | _csignals_T_117 | _csignals_T_119; + wire _GEN_23 = _csignals_T_111 | _csignals_T_1359; + wire _GEN_24 = _csignals_T_49 | _csignals_T_51; + wire _GEN_25 = + _csignals_T_97 | _csignals_T_99 | _csignals_T_101 | _csignals_T_103 | _csignals_T_105 + | _csignals_T_107 | _csignals_T_109 | _GEN_23; + wire _GEN_26 = + _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21 | _csignals_T_23 + | _csignals_T_25 | _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33 + | _csignals_T_35 | _csignals_T_37 | _csignals_T_39 | _csignals_T_41 | _csignals_T_43 + | _csignals_T_45 | _csignals_T_47 | _GEN_24; + wire _GEN_27 = + _csignals_T_71 | _csignals_T_73 | _csignals_T_75 | _csignals_T_77 | _csignals_T_79 + | _csignals_T_81 | _csignals_T_83 | _csignals_T_85 | _csignals_T_87 | _csignals_T_2589 + | _csignals_T_91 | _csignals_T_93 | _csignals_T_95 | _GEN_25; + assign io_out_valid = + _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21 | _csignals_T_23 + | _csignals_T_25 | _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33 + | _csignals_T_35 | _csignals_T_37 | _csignals_T_39 | _csignals_T_41 | _csignals_T_43 + | _csignals_T_45 | _csignals_T_47 | _csignals_T_49 | _csignals_T_51 | _csignals_T_53 + | _csignals_T_55 | _csignals_T_57 | _csignals_T_59 | _csignals_T_61 | _csignals_T_63 + | _csignals_T_65 | _csignals_T_67 | _csignals_T_69 | _csignals_T_71 | _csignals_T_73 + | _csignals_T_75 | _csignals_T_77 | _csignals_T_79 | _csignals_T_81 | _csignals_T_83 + | _csignals_T_85 | _csignals_T_87 | _csignals_T_2589 | _csignals_T_91 | _csignals_T_93 + | _csignals_T_95 | _csignals_T_97 | _csignals_T_99 | _csignals_T_101 | _csignals_T_103 + | _csignals_T_105 | _csignals_T_107 | _csignals_T_109 | _csignals_T_111 + | _csignals_T_1359 | _csignals_T_2228 | _csignals_T_117 | _csignals_T_119 + | _csignals_T_121 | _csignals_T_123 | _csignals_T_125 | _csignals_T_127 + | _csignals_T_129 | _csignals_T_2394 | _csignals_T_133 | _csignals_T_135 + | _csignals_T_137 | _csignals_T_139 | _csignals_T_1519 | _GEN_5 | _csignals_T_2626; + assign io_out_bits_branch = + _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21 | _csignals_T_23 + | _csignals_T_25 | _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33 + | _csignals_T_35 | _csignals_T_37 | _csignals_T_39 | _csignals_T_41 | _csignals_T_43 + | _csignals_T_45 | _csignals_T_47 | _csignals_T_49 | _csignals_T_51 | _GEN_8 + ? 4'h0 + : _csignals_T_63 + ? 4'h8 + : _GEN_7 + ? 4'h0 + : _csignals_T_71 + ? 4'h1 + : _csignals_T_73 + ? 4'h2 + : _csignals_T_75 + ? 4'h3 + : _csignals_T_77 + ? 4'h4 + : _csignals_T_79 + ? 4'h5 + : _csignals_T_81 + ? 4'h6 + : _GEN_6 + ? 4'h0 + : _csignals_T_87 + ? 4'h7 + : _csignals_T_2589 + ? 4'h0 + : _csignals_T_91 + ? 4'h9 + : _csignals_T_93 ? 4'hA : 4'h0; + assign io_out_bits_value1 = + _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21 | _csignals_T_23 + | _csignals_T_25 | _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33 + | _csignals_T_35 | _csignals_T_37 | _csignals_T_39 | _csignals_T_41 | _csignals_T_43 + | _csignals_T_45 | _csignals_T_47 | _csignals_T_49 | _csignals_T_51 | _csignals_T_53 + | _csignals_T_55 | _csignals_T_57 | _csignals_T_59 | _csignals_T_61 | _csignals_T_63 + | _GEN_15 + ? 2'h1 + : _GEN_6 + ? 2'h2 + : _GEN_12 + ? 2'h0 + : _csignals_T_97 | _csignals_T_99 | _csignals_T_101 | _csignals_T_103 + | _csignals_T_105 | _csignals_T_107 | _csignals_T_109 | _csignals_T_111 + | _csignals_T_1359 | _csignals_T_2228 | _csignals_T_117 | _csignals_T_119 + | _csignals_T_121 | _csignals_T_123 | _csignals_T_125 + ? 2'h1 + : _GEN_10 + ? 2'h3 + : _csignals_T_133 | _csignals_T_135 | _csignals_T_137 + | _csignals_T_139 | _csignals_T_1519 | _csignals_T_143 + ? 2'h1 + : _csignals_T_145 + ? 2'h3 + : _csignals_T_147 | _csignals_T_149 | _csignals_T_151 + | _csignals_T_153 | _csignals_T_155 | _csignals_T_157 + | _csignals_T_159 | _csignals_T_161 | _csignals_T_163 + | _csignals_T_165 | _csignals_T_167 | _csignals_T_169 + | _csignals_T_171 | _csignals_T_173 | _csignals_T_175 + | _csignals_T_177 | _csignals_T_978 | _csignals_T_181 + | _csignals_T_183 | _csignals_T_185 | _csignals_T_187 + | _GEN_9 + ? 2'h1 + : _csignals_T_197 + ? 2'h0 + : _csignals_T_199 + ? 2'h1 + : _csignals_T_201 + ? 2'h3 + : _csignals_T_203 + ? 2'h0 + : _csignals_T_205 | _csignals_T_207 + ? 2'h1 + : _csignals_T_209 + ? 2'h3 + : _csignals_T_211 + ? 2'h0 + : _csignals_T_213 + ? 2'h1 + : _csignals_T_215 + ? 2'h3 + : _csignals_T_217 + ? 2'h0 + : _csignals_T_219 + ? 2'h1 + : _csignals_T_221 + ? 2'h3 + : _csignals_T_223 + ? 2'h0 + : _csignals_T_225 + ? 2'h1 + : _csignals_T_227 + ? 2'h3 + : _csignals_T_229 + ? 2'h0 + : _csignals_T_231 + ? 2'h1 + : _csignals_T_233 + ? 2'h3 + : _csignals_T_235 + ? 2'h0 + : _csignals_T_237 + ? 2'h1 + : _csignals_T_239 + ? 2'h3 + : _csignals_T_241 + ? 2'h0 + : _csignals_T_243 + ? 2'h1 + : _csignals_T_245 + ? 2'h0 + : _csignals_T_247 + ? 2'h1 + : _csignals_T_249 + ? 2'h0 + : _csignals_T_251 + ? 2'h1 + : _csignals_T_253 + ? 2'h3 + : _csignals_T_255 + ? 2'h0 + : _csignals_T_257 + ? 2'h1 + : _csignals_T_259 + ? 2'h3 + : _csignals_T_261 + ? 2'h1 + : _csignals_T_263 + ? 2'h3 + : _csignals_T_265 + ? 2'h1 + : _csignals_T_267 + ? 2'h3 + : _csignals_T_269 + ? 2'h0 + : _csignals_T_271 + ? 2'h1 + : _csignals_T_273 + ? 2'h0 + : _csignals_T_275 + ? 2'h1 + : _csignals_T_277 + ? 2'h0 + : _csignals_T_279 + ? 2'h1 + : _csignals_T_281 + ? 2'h0 + : _csignals_T_283 + ? 2'h1 + : _csignals_T_285 + ? 2'h0 + : _csignals_T_287 + ? 2'h1 + : _csignals_T_289 + ? 2'h3 + : _csignals_T_291 + ? 2'h0 + : _csignals_T_293 + ? 2'h1 + : _csignals_T_295 + ? 2'h3 + : {1'h0, + ~(_csignals_T_297 + | _csignals_T_299 + | _csignals_T_301 + | _csignals_T_303 + | _csignals_T_305 + | _csignals_T_307 + | _csignals_T_309 + | _csignals_T_311 + | _csignals_T_313) + & (_csignals_T_315 + | ~_csignals_T_317 + & (_csignals_T_319 + | ~_csignals_T_321 + & (_csignals_T_323 + | ~_csignals_T_325 + & (_csignals_T_327 + | ~_csignals_T_329 + & (_csignals_T_331 + | ~_csignals_T_333 + & (_csignals_T_335 + | ~_csignals_T_337 + & (_csignals_T_339 + | ~_csignals_T_341 + & (_csignals_T_343 + | ~_GEN_4 + & _csignals_T_2626))))))))}; + assign io_out_bits_value2 = + _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21 | _csignals_T_23 + | _csignals_T_25 | _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33 + ? 3'h1 + : _csignals_T_35 | _csignals_T_37 | _csignals_T_39 | _csignals_T_41 | _csignals_T_43 + | _csignals_T_45 | _csignals_T_47 | _csignals_T_49 | _csignals_T_51 + | _csignals_T_53 | _csignals_T_55 | _csignals_T_57 | _csignals_T_59 + | _csignals_T_61 | _csignals_T_63 + ? 3'h2 + : _GEN_7 + ? 3'h3 + : _GEN_14 + ? 3'h1 + : _csignals_T_83 + ? 3'h0 + : _csignals_T_85 + ? 3'h4 + : {1'h0, + _GEN_12 + ? 2'h0 + : _csignals_T_97 | _csignals_T_99 | _csignals_T_101 + | _GEN_20 + ? 2'h1 + : _csignals_T_107 | _csignals_T_109 | _csignals_T_111 + | _csignals_T_1359 | _GEN_19 + ? 2'h2 + : _csignals_T_119 + ? 2'h3 + : _GEN_18 + ? 2'h0 + : _GEN_17 + ? 2'h1 + : _csignals_T_143 | _csignals_T_145 + ? 2'h0 + : _csignals_T_147 + ? 2'h1 + : _csignals_T_149 + | _csignals_T_151 + | _csignals_T_153 + | _csignals_T_155 | _GEN_16 + ? 2'h2 + : {1'h0, + _csignals_T_165 + | _csignals_T_167 + | _csignals_T_169 + | _csignals_T_171 + | _csignals_T_173 + | _csignals_T_175 + | _csignals_T_177 + | _csignals_T_978}}; + assign io_out_bits_arithmetic_funct = + _csignals_T_15 | _csignals_T_17 + ? 4'h1 + : _csignals_T_19 + ? 4'h2 + : _csignals_T_21 + ? 4'h3 + : _csignals_T_23 + ? 4'h4 + : _csignals_T_25 + ? 4'h5 + : _csignals_T_27 | _csignals_T_29 + ? 4'h6 + : _csignals_T_31 + ? 4'h7 + : _csignals_T_33 + ? 4'h8 + : _csignals_T_35 + ? 4'h1 + : _csignals_T_37 + ? 4'h3 + : _csignals_T_39 + ? 4'h4 + : _csignals_T_41 + ? 4'h5 + : _csignals_T_43 + ? 4'h7 + : _csignals_T_45 + ? 4'h8 + : _csignals_T_47 + ? 4'h2 + : _GEN_24 + ? 4'h6 + : _csignals_T_53 + | _csignals_T_55 + | _csignals_T_57 + | _csignals_T_59 + | _csignals_T_61 + | _csignals_T_63 + | _GEN_7 + ? 4'h1 + : _csignals_T_71 + | _csignals_T_73 + ? 4'h5 + : _csignals_T_75 + | _csignals_T_77 + ? 4'h3 + : _GEN_13 + ? 4'h4 + : _GEN_6 + ? 4'h1 + : _GEN_12 + ? 4'h0 + : _csignals_T_97 + | _csignals_T_99 + ? 4'h1 + : _csignals_T_101 + ? 4'h2 + : _GEN_20 + ? 4'h6 + : _csignals_T_107 + ? 4'h1 + : _csignals_T_109 + ? 4'h2 + : _GEN_23 + ? 4'h6 + : _GEN_22 + ? 4'h1 + : _GEN_18 + ? 4'h0 + : _csignals_T_133 + ? 4'h9 + : _csignals_T_135 + ? 4'hA + : _csignals_T_137 + ? 4'hB + : _csignals_T_139 + ? 4'hC + : _csignals_T_1519 + ? 4'h9 + : {3'h0, + ~_GEN_21 + & (_csignals_T_149 + | _csignals_T_151 + | _csignals_T_153 + | _csignals_T_155 + | _csignals_T_157 + | _csignals_T_159 + | _csignals_T_161 + | _csignals_T_163 + | _csignals_T_165 + | _csignals_T_167 + | _csignals_T_169 + | _csignals_T_171 + | _csignals_T_173 + | _csignals_T_175 + | _csignals_T_177 + | _csignals_T_978 + | _csignals_T_181 + | _csignals_T_183 + | _csignals_T_185 + | _csignals_T_187 + | _csignals_T_189 + | _csignals_T_191 + | _csignals_T_193 + | _csignals_T_1144)}; + assign io_out_bits_alu_flag = + ~_csignals_T_15 + & (_csignals_T_17 + | ~(_csignals_T_19 | _csignals_T_21 | _csignals_T_23 | _csignals_T_25 + | _csignals_T_27) + & (_csignals_T_29 + | ~(_csignals_T_31 | _csignals_T_33 | _csignals_T_35 | _csignals_T_37 + | _csignals_T_39 | _csignals_T_41 | _csignals_T_43 | _csignals_T_45 + | _csignals_T_47 | _csignals_T_49) + & (_csignals_T_51 + | ~(_csignals_T_53 | _csignals_T_55 | _csignals_T_57 | _csignals_T_59 + | _csignals_T_61 | _csignals_T_63 | _csignals_T_65 | _csignals_T_67 + | _csignals_T_69 | _csignals_T_71 | _csignals_T_73 | _csignals_T_75 + | _csignals_T_77 | _csignals_T_79 | _csignals_T_81 | _csignals_T_83 + | _csignals_T_85 | _csignals_T_87 | _csignals_T_2589 | _csignals_T_91 + | _csignals_T_93 | _csignals_T_95 | _csignals_T_97) + & (_csignals_T_99 | ~(_csignals_T_101 | _csignals_T_103) + & (_csignals_T_105 + | ~(_csignals_T_107 | _csignals_T_109 | _csignals_T_111) + & _csignals_T_1359))))); + assign io_out_bits_op32 = + ~(_csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21 | _csignals_T_23 + | _csignals_T_25 | _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33 + | _csignals_T_35 | _csignals_T_37 | _csignals_T_39 | _csignals_T_41 | _csignals_T_43 + | _csignals_T_45 | _csignals_T_47 | _csignals_T_49 | _csignals_T_51 | _csignals_T_53 + | _csignals_T_55 | _csignals_T_57 | _csignals_T_59 | _csignals_T_61 | _csignals_T_63 + | _csignals_T_65 | _csignals_T_67 | _csignals_T_69 | _csignals_T_71 | _csignals_T_73 + | _csignals_T_75 | _csignals_T_77 | _csignals_T_79 | _csignals_T_81 | _csignals_T_83 + | _csignals_T_85 | _GEN_12) + & (_GEN_25 + | ~(_csignals_T_2228 | _csignals_T_117 | _csignals_T_119 | _csignals_T_121 + | _csignals_T_123 | _csignals_T_125 | _csignals_T_127 | _csignals_T_129 + | _csignals_T_2394 | _csignals_T_133 | _csignals_T_135 | _csignals_T_137 + | _csignals_T_139) & _csignals_T_1519); + assign io_out_bits_writeback_selector = + _GEN_26 + ? 3'h2 + : _GEN_8 + ? 3'h4 + : _csignals_T_63 + ? 3'h1 + : _GEN_15 + ? 3'h0 + : _GEN_6 + ? 3'h2 + : _csignals_T_87 + ? 3'h1 + : _GEN_11 + ? 3'h0 + : _GEN_25 + ? 3'h2 + : _GEN_19 + ? 3'h4 + : _csignals_T_119 + ? 3'h0 + : _GEN_18 + ? 3'h3 + : _GEN_17 + ? 3'h2 + : _GEN_21 + | ~(_csignals_T_149 | _csignals_T_151 + | _csignals_T_153 + | _csignals_T_155 + | _csignals_T_157 + | _csignals_T_159 + | _csignals_T_161 + | _csignals_T_163 + | _csignals_T_165 + | _csignals_T_167 + | _csignals_T_169 + | _csignals_T_171 + | _csignals_T_173 + | _csignals_T_175 + | _csignals_T_177 + | _csignals_T_978 + | _csignals_T_181 + | _csignals_T_183 + | _csignals_T_185 + | _csignals_T_187 + | _csignals_T_189 + | _csignals_T_191 + | _csignals_T_193 + | _csignals_T_1144 + | _csignals_T_197 + | _csignals_T_199 + | _csignals_T_201 + | _csignals_T_203 + | _csignals_T_205 + | _csignals_T_207 + | _csignals_T_209 + | _csignals_T_211 + | _csignals_T_213 + | _csignals_T_215 + | _csignals_T_217 + | _csignals_T_219 + | _csignals_T_221 + | _csignals_T_223 + | _csignals_T_225 + | _csignals_T_227 + | _csignals_T_229 + | _csignals_T_231 + | _csignals_T_233 + | _csignals_T_235 + | _csignals_T_237 + | _csignals_T_239 + | _csignals_T_241 + | _csignals_T_243 + | _csignals_T_245 + | _csignals_T_247 + | _csignals_T_249 + | _csignals_T_251 + | _csignals_T_253 + | _csignals_T_255 + | _csignals_T_257 + | _csignals_T_259 + | _csignals_T_261 + | _csignals_T_263 + | _csignals_T_265 + | _csignals_T_267 + | _csignals_T_269 + | _csignals_T_271 + | _csignals_T_273 + | _csignals_T_275 + | _csignals_T_277 + | _csignals_T_279 + | _csignals_T_281 + | _csignals_T_283 + | _csignals_T_285 + | _csignals_T_287 + | _csignals_T_289 + | _csignals_T_291 + | _csignals_T_293 + | _csignals_T_295 + | _csignals_T_297 + | _csignals_T_299 + | _csignals_T_301 + | _csignals_T_303 + | _csignals_T_305 + | _csignals_T_307 + | _csignals_T_309 + | _csignals_T_311 + | _csignals_T_313 + | _csignals_T_315 + | _csignals_T_317 + | _csignals_T_319 + | _csignals_T_321 + | _csignals_T_323 + | _csignals_T_325 + | _csignals_T_327 + | _csignals_T_329 + | _csignals_T_331 + | _csignals_T_333 + | _csignals_T_335 + | _csignals_T_337 + | _csignals_T_339 + | _csignals_T_341 + | _csignals_T_343 + | _csignals_T_345 + | _csignals_T_347 + | _csignals_T_349 + | _csignals_T_351 + | _csignals_T_353 + | _csignals_T_355 + | _csignals_T_357 + | _csignals_T_359 + | ~_csignals_T_361) + ? 3'h5 + : 3'h0; + assign io_out_bits_memory_function = + _GEN_26 + ? 2'h0 + : _GEN_8 + ? 2'h1 + : _csignals_T_63 + ? 2'h0 + : _GEN_7 + ? 2'h2 + : _GEN_27 + ? 2'h0 + : _GEN_19 + ? 2'h1 + : _csignals_T_119 + ? 2'h2 + : _csignals_T_121 | _csignals_T_123 | _csignals_T_125 + | _csignals_T_127 | _csignals_T_129 | _csignals_T_2394 + | _csignals_T_133 | _csignals_T_135 | _csignals_T_137 + | _csignals_T_139 | _csignals_T_1519 | _GEN_21 + ? 2'h0 + : _csignals_T_149 | _csignals_T_151 | _csignals_T_153 + | _csignals_T_155 + ? 2'h1 + : _GEN_16 + ? 2'h2 + : _csignals_T_165 | _csignals_T_167 + | _csignals_T_169 | _csignals_T_171 + ? 2'h1 + : _csignals_T_173 | _csignals_T_175 + | _csignals_T_177 | _csignals_T_978 + ? 2'h2 + : _csignals_T_181 | _csignals_T_183 + | _csignals_T_185 | _csignals_T_187 + ? 2'h1 + : {_GEN_9, 1'h0}; + assign io_out_bits_memory_length = + _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21 | _csignals_T_23 + | _csignals_T_25 | _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33 + | _csignals_T_35 | _csignals_T_37 | _csignals_T_39 | _csignals_T_41 | _csignals_T_43 + | _csignals_T_45 | _csignals_T_47 | _csignals_T_49 | _csignals_T_51 | _csignals_T_53 + ? 2'h0 + : _csignals_T_55 + ? 2'h1 + : _csignals_T_57 + ? 2'h2 + : _csignals_T_59 + ? 2'h0 + : _csignals_T_61 + ? 2'h1 + : _csignals_T_63 | _csignals_T_65 + ? 2'h0 + : _csignals_T_67 + ? 2'h1 + : _csignals_T_69 + ? 2'h2 + : _GEN_27 + ? 2'h0 + : _csignals_T_2228 + ? 2'h3 + : _csignals_T_117 + ? 2'h2 + : _csignals_T_119 + ? 2'h3 + : _csignals_T_121 | _csignals_T_123 + | _csignals_T_125 | _csignals_T_127 + | _csignals_T_129 | _csignals_T_2394 + | _csignals_T_133 | _csignals_T_135 + | _csignals_T_137 | _csignals_T_139 + | _csignals_T_1519 | _csignals_T_143 + | _csignals_T_145 | _csignals_T_147 + | _csignals_T_149 + ? 2'h0 + : _csignals_T_151 + ? 2'h1 + : _csignals_T_153 + ? 2'h2 + : _csignals_T_155 + ? 2'h3 + : _csignals_T_157 + ? 2'h0 + : _csignals_T_159 + ? 2'h1 + : _csignals_T_161 + ? 2'h2 + : _csignals_T_163 + ? 2'h3 + : _csignals_T_165 + ? 2'h0 + : _csignals_T_167 + ? 2'h1 + : _csignals_T_169 + ? 2'h2 + : _csignals_T_171 + ? 2'h3 + : _csignals_T_173 + ? 2'h0 + : _csignals_T_175 + ? 2'h1 + : _csignals_T_177 + ? 2'h2 + : _csignals_T_978 + ? 2'h3 + : _csignals_T_181 + ? 2'h0 + : _csignals_T_183 + ? 2'h1 + : _csignals_T_185 + ? 2'h2 + : _csignals_T_187 + ? 2'h3 + : _csignals_T_189 + ? 2'h0 + : _csignals_T_191 + ? 2'h1 + : _csignals_T_193 + ? 2'h2 + : {2{_csignals_T_1144}}; + assign io_out_bits_mem_sext = + ~_GEN_26 + & (_csignals_T_53 | _csignals_T_55 | _csignals_T_57 + | ~(_csignals_T_59 | _csignals_T_61 | _csignals_T_63 | _csignals_T_65 + | _csignals_T_67 | _csignals_T_69 | _GEN_27) & _csignals_T_2228); + assign io_out_bits_csr_funct = + _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21 | _csignals_T_23 + | _csignals_T_25 | _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33 + | _csignals_T_35 | _csignals_T_37 | _csignals_T_39 | _csignals_T_41 | _csignals_T_43 + | _csignals_T_45 | _csignals_T_47 | _csignals_T_49 | _csignals_T_51 | _csignals_T_53 + | _csignals_T_55 | _csignals_T_57 | _csignals_T_59 | _csignals_T_61 | _csignals_T_63 + | _csignals_T_65 | _csignals_T_67 | _csignals_T_69 | _csignals_T_71 | _csignals_T_73 + | _csignals_T_75 | _csignals_T_77 | _csignals_T_79 | _csignals_T_81 | _csignals_T_83 + | _csignals_T_85 | _csignals_T_87 | _csignals_T_2589 + ? 3'h0 + : _csignals_T_91 + ? 3'h5 + : _csignals_T_93 + ? 3'h4 + : {1'h0, + _csignals_T_95 | _csignals_T_97 | _csignals_T_99 | _csignals_T_101 + | _csignals_T_103 | _csignals_T_105 | _csignals_T_107 | _csignals_T_109 + | _csignals_T_111 | _csignals_T_1359 | _GEN_22 + ? 2'h0 + : _csignals_T_121 + ? 2'h3 + : _csignals_T_123 + ? 2'h2 + : _csignals_T_125 + ? 2'h1 + : _csignals_T_127 + ? 2'h3 + : _csignals_T_129 ? 2'h2 : {1'h0, _csignals_T_2394}}; + assign io_out_bits_fence = + ~(_csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21 | _csignals_T_23 + | _csignals_T_25 | _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33 + | _csignals_T_35 | _csignals_T_37 | _csignals_T_39 | _csignals_T_41 | _csignals_T_43 + | _csignals_T_45 | _csignals_T_47 | _csignals_T_49 | _csignals_T_51 | _csignals_T_53 + | _csignals_T_55 | _csignals_T_57 | _csignals_T_59 | _csignals_T_61 | _csignals_T_63 + | _csignals_T_65 | _csignals_T_67 | _csignals_T_69 | _csignals_T_71 | _csignals_T_73 + | _csignals_T_75 | _csignals_T_77 | _csignals_T_79 | _csignals_T_81 | _csignals_T_83 + | _csignals_T_85 | _csignals_T_87) & _csignals_T_2589; + assign io_out_bits_vector = + ~(_csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21 | _csignals_T_23 + | _csignals_T_25 | _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33 + | _csignals_T_35 | _csignals_T_37 | _csignals_T_39 | _csignals_T_41 | _csignals_T_43 + | _csignals_T_45 | _csignals_T_47 | _csignals_T_49 | _csignals_T_51 | _csignals_T_53 + | _csignals_T_55 | _csignals_T_57 | _csignals_T_59 | _csignals_T_61 | _csignals_T_63 + | _csignals_T_65 | _csignals_T_67 | _csignals_T_69 | _csignals_T_71 | _csignals_T_73 + | _csignals_T_75 | _csignals_T_77 | _csignals_T_79 | _csignals_T_81 | _csignals_T_83 + | _csignals_T_85 | _csignals_T_87 | _csignals_T_2589 | _csignals_T_91 + | _csignals_T_93 | _csignals_T_95 | _csignals_T_97 | _csignals_T_99 + | _csignals_T_101 | _csignals_T_103 | _csignals_T_105 | _csignals_T_107 + | _csignals_T_109 | _csignals_T_111 | _csignals_T_1359 | _csignals_T_2228 + | _csignals_T_117 | _csignals_T_119 | _csignals_T_121 | _csignals_T_123 + | _csignals_T_125 | _csignals_T_127 | _csignals_T_129 | _csignals_T_2394 | _GEN_17) + & (_GEN_5 | _csignals_T_2626); +endmodule + +module BranchPredictor( + input clock, + reset, + input [63:0] io_pc_addr, + io_imm, + input [3:0] io_BranchType, + output io_out_valid, + output [63:0] io_out_bits_pc +); + + reg [63:0] RAS_0; + reg [63:0] RAS_1; + reg [63:0] RAS_2; + reg [63:0] RAS_3; + reg [63:0] RAS_4; + reg [63:0] RAS_5; + reg [63:0] RAS_6; + reg [63:0] RAS_7; + reg [2:0] RAS_ptr; + wire [7:0][63:0] _GEN = + {{RAS_7}, {RAS_6}, {RAS_5}, {RAS_4}, {RAS_3}, {RAS_2}, {RAS_1}, {RAS_0}}; + always @(posedge clock) begin + if (reset) begin + RAS_0 <= 64'h0; + RAS_1 <= 64'h0; + RAS_2 <= 64'h0; + RAS_3 <= 64'h0; + RAS_4 <= 64'h0; + RAS_5 <= 64'h0; + RAS_6 <= 64'h0; + RAS_7 <= 64'h0; + RAS_ptr <= 3'h0; + end + else begin + automatic logic _T_1 = io_BranchType == 4'h7; + automatic logic [63:0] _T_3; + _T_3 = io_pc_addr + 64'h4; + if (_T_1 & ~(|RAS_ptr)) + RAS_0 <= _T_3; + if (_T_1 & RAS_ptr == 3'h1) + RAS_1 <= _T_3; + if (_T_1 & RAS_ptr == 3'h2) + RAS_2 <= _T_3; + if (_T_1 & RAS_ptr == 3'h3) + RAS_3 <= _T_3; + if (_T_1 & RAS_ptr == 3'h4) + RAS_4 <= _T_3; + if (_T_1 & RAS_ptr == 3'h5) + RAS_5 <= _T_3; + if (_T_1 & RAS_ptr == 3'h6) + RAS_6 <= _T_3; + if (_T_1 & (&RAS_ptr)) + RAS_7 <= _T_3; + if (|RAS_ptr) + RAS_ptr <= RAS_ptr - 3'h1; + else + RAS_ptr <= 3'h0; + end + end // always @(posedge) + assign io_out_valid = + io_BranchType == 4'h8 | io_BranchType == 4'h7 + | (io_BranchType == 4'h6 + ? $signed(io_imm) < 64'sh0 + : io_BranchType == 4'h5 + ? $signed(io_imm) < 64'sh0 + : io_BranchType == 4'h4 + ? $signed(io_imm) < 64'sh0 + : io_BranchType == 4'h3 + ? $signed(io_imm) < 64'sh0 + : io_BranchType == 4'h2 + ? $signed(io_imm) < 64'sh0 + : io_BranchType == 4'h1 & $signed(io_imm) < 64'sh0); + assign io_out_bits_pc = io_BranchType == 4'h8 ? _GEN[RAS_ptr] : io_pc_addr + io_imm; +endmodule + +module RegFile( + input clock, + input [4:0] io_rs1, + io_rs2, + input io_req_valid, + input [4:0] io_req_bits_rd, + input [63:0] io_req_bits_data, + output [63:0] io_rs1_out, + io_rs2_out +); + + reg [63:0] regfile_0; + reg [63:0] regfile_1; + reg [63:0] regfile_2; + reg [63:0] regfile_3; + reg [63:0] regfile_4; + reg [63:0] regfile_5; + reg [63:0] regfile_6; + reg [63:0] regfile_7; + reg [63:0] regfile_8; + reg [63:0] regfile_9; + reg [63:0] regfile_10; + reg [63:0] regfile_11; + reg [63:0] regfile_12; + reg [63:0] regfile_13; + reg [63:0] regfile_14; + reg [63:0] regfile_15; + reg [63:0] regfile_16; + reg [63:0] regfile_17; + reg [63:0] regfile_18; + reg [63:0] regfile_19; + reg [63:0] regfile_20; + reg [63:0] regfile_21; + reg [63:0] regfile_22; + reg [63:0] regfile_23; + reg [63:0] regfile_24; + reg [63:0] regfile_25; + reg [63:0] regfile_26; + reg [63:0] regfile_27; + reg [63:0] regfile_28; + reg [63:0] regfile_29; + reg [63:0] regfile_30; + wire [31:0][63:0] _GEN = + {{regfile_30}, + {regfile_29}, + {regfile_28}, + {regfile_27}, + {regfile_26}, + {regfile_25}, + {regfile_24}, + {regfile_23}, + {regfile_22}, + {regfile_21}, + {regfile_20}, + {regfile_19}, + {regfile_18}, + {regfile_17}, + {regfile_16}, + {regfile_15}, + {regfile_14}, + {regfile_13}, + {regfile_12}, + {regfile_11}, + {regfile_10}, + {regfile_9}, + {regfile_8}, + {regfile_7}, + {regfile_6}, + {regfile_5}, + {regfile_4}, + {regfile_3}, + {regfile_2}, + {regfile_1}, + {regfile_0}, + {64'h0}}; + always @(posedge clock) begin + if (io_req_valid & io_req_bits_rd == 5'h1) + regfile_0 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h2) + regfile_1 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h3) + regfile_2 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h4) + regfile_3 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h5) + regfile_4 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h6) + regfile_5 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h7) + regfile_6 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h8) + regfile_7 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h9) + regfile_8 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'hA) + regfile_9 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'hB) + regfile_10 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'hC) + regfile_11 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'hD) + regfile_12 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'hE) + regfile_13 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'hF) + regfile_14 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h10) + regfile_15 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h11) + regfile_16 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h12) + regfile_17 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h13) + regfile_18 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h14) + regfile_19 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h15) + regfile_20 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h16) + regfile_21 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h17) + regfile_22 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h18) + regfile_23 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h19) + regfile_24 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h1A) + regfile_25 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h1B) + regfile_26 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h1C) + regfile_27 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h1D) + regfile_28 <= io_req_bits_data; + if (io_req_valid & io_req_bits_rd == 5'h1E) + regfile_29 <= io_req_bits_data; + if (io_req_valid & (&io_req_bits_rd)) + regfile_30 <= io_req_bits_data; + end // always @(posedge) + assign io_rs1_out = _GEN[io_rs1]; + assign io_rs2_out = _GEN[io_rs2]; +endmodule + +module BarrelShifter( + input [64:0] io_in, + input [5:0] io_shamt, + output [64:0] io_out +); + + wire [64:0] ans_seq_5 = io_shamt[5] ? {{32{io_in[64]}}, io_in[64:32]} : io_in; + wire [64:0] ans_seq_4 = + io_shamt[4] ? {{16{ans_seq_5[64]}}, ans_seq_5[64:16]} : ans_seq_5; + wire [64:0] ans_seq_3 = io_shamt[3] ? {{8{ans_seq_4[64]}}, ans_seq_4[64:8]} : ans_seq_4; + wire [64:0] ans_seq_2 = io_shamt[2] ? {{4{ans_seq_3[64]}}, ans_seq_3[64:4]} : ans_seq_3; + wire [64:0] ans_seq_1 = io_shamt[1] ? {{2{ans_seq_2[64]}}, ans_seq_2[64:2]} : ans_seq_2; + assign io_out = io_shamt[0] ? {ans_seq_1[64], ans_seq_1[64:1]} : ans_seq_1; +endmodule + +module ALU( + input [3:0] io_funct_arithmetic_funct, + input io_funct_alu_flag, + io_funct_op32, + input [63:0] io_in1, + io_in2, + output [63:0] io_out +); + + wire [64:0] _right_barrel_shifter_io_out; + wire [63:0] in1_record = + io_funct_op32 + ? {io_funct_arithmetic_funct == 4'h6 & ~io_funct_alu_flag + ? 32'h0 + : {32{io_in1[31]}}, + io_in1[31:0]} + : io_in1; + wire [63:0] in2_record = io_funct_op32 ? {{32{io_in2[31]}}, io_in2[31:0]} : io_in2; + wire [15:0] _GEN = + {{in1_record[23:16], in1_record[31:28]} & 12'hF0F, 4'h0} + | {in1_record[31:24], in1_record[39:32]} & 16'hF0F; + wire [37:0] _GEN_0 = + {in1_record[11:8], + in1_record[15:12], + in1_record[19:16], + _GEN, + in1_record[39:36], + in1_record[43:40], + in1_record[47:46]} & 38'h3333333333; + wire [7:0] _GEN_1 = _GEN_0[37:30] | {in1_record[15:12], in1_record[19:16]} & 8'h33; + wire [15:0] _GEN_2 = _GEN_0[29:14] | _GEN & 16'h3333; + wire [1:0] _GEN_3 = _GEN_0[11:10] | in1_record[37:36]; + wire [7:0] _GEN_4 = + {_GEN_0[5:0], 2'h0} | {in1_record[47:44], in1_record[51:48]} & 8'h33; + wire [50:0] _GEN_5 = + {in1_record[5:4], + in1_record[7:6], + in1_record[9:8], + _GEN_1, + _GEN_2, + _GEN[3:2], + _GEN_3, + in1_record[39:38], + in1_record[41:40], + _GEN_4, + in1_record[51:50], + in1_record[53:52], + in1_record[55]} & 51'h5555555555555; + wire [63:0] shin = + io_funct_arithmetic_funct == 4'h6 + ? in1_record + : {in1_record[0], + in1_record[1], + in1_record[2], + in1_record[3], + in1_record[4], + _GEN_5[50:47] | {in1_record[7:6], in1_record[9:8]} & 4'h5, + _GEN_5[46:39] | _GEN_1 & 8'h55, + _GEN_5[38:23] | _GEN_2 & 16'h5555, + _GEN_2[1], + _GEN_5[21] | _GEN[2], + {_GEN[3], 1'h0} | _GEN_3 & 2'h1, + _GEN_5[18:15] | {in1_record[39:38], in1_record[41:40]} & 4'h5, + _GEN_5[14:7] | _GEN_4 & 8'h55, + _GEN_4[1], + _GEN_5[5] | in1_record[50], + in1_record[51], + in1_record[52], + {_GEN_5[2:0], 1'h0} | {in1_record[55:54], in1_record[57:56]} & 4'h5, + in1_record[57], + in1_record[58], + in1_record[59], + in1_record[60], + in1_record[61], + in1_record[62], + in1_record[63]}; + wire [15:0] _GEN_6 = + {{_right_barrel_shifter_io_out[23:16], _right_barrel_shifter_io_out[31:28]} & 12'hF0F, + 4'h0} | {_right_barrel_shifter_io_out[31:24], _right_barrel_shifter_io_out[39:32]} + & 16'hF0F; + wire [37:0] _GEN_7 = + {_right_barrel_shifter_io_out[11:8], + _right_barrel_shifter_io_out[15:12], + _right_barrel_shifter_io_out[19:16], + _GEN_6, + _right_barrel_shifter_io_out[39:36], + _right_barrel_shifter_io_out[43:40], + _right_barrel_shifter_io_out[47:46]} & 38'h3333333333; + wire [7:0] _GEN_8 = + _GEN_7[37:30] + | {_right_barrel_shifter_io_out[15:12], _right_barrel_shifter_io_out[19:16]} & 8'h33; + wire [15:0] _GEN_9 = _GEN_7[29:14] | _GEN_6 & 16'h3333; + wire [1:0] _GEN_10 = _GEN_7[11:10] | _right_barrel_shifter_io_out[37:36]; + wire [7:0] _GEN_11 = + {_GEN_7[5:0], 2'h0} + | {_right_barrel_shifter_io_out[47:44], _right_barrel_shifter_io_out[51:48]} & 8'h33; + wire [50:0] _GEN_12 = + {_right_barrel_shifter_io_out[5:4], + _right_barrel_shifter_io_out[7:6], + _right_barrel_shifter_io_out[9:8], + _GEN_8, + _GEN_9, + _GEN_6[3:2], + _GEN_10, + _right_barrel_shifter_io_out[39:38], + _right_barrel_shifter_io_out[41:40], + _GEN_11, + _right_barrel_shifter_io_out[51:50], + _right_barrel_shifter_io_out[53:52], + _right_barrel_shifter_io_out[55]} & 51'h5555555555555; + wire [15:0] _GEN_13 = _GEN_12[38:23] | _GEN_9 & 16'h5555; + wire [63:0] addsub_record = + io_funct_alu_flag ? in1_record - in2_record : in1_record + in2_record; + BarrelShifter right_barrel_shifter ( + .io_in ({io_funct_alu_flag & shin[63], shin}), + .io_shamt (io_funct_op32 ? {1'h0, in2_record[4:0]} : in2_record[5:0]), + .io_out (_right_barrel_shifter_io_out) + ); + assign io_out = + io_funct_arithmetic_funct == 4'h8 + ? io_in1 & io_in2 + : io_funct_arithmetic_funct == 4'h7 + ? io_in1 | io_in2 + : io_funct_arithmetic_funct == 4'h6 + ? (io_funct_op32 + ? {{32{_right_barrel_shifter_io_out[31]}}, + _right_barrel_shifter_io_out[31:0]} + : _right_barrel_shifter_io_out[63:0]) + : io_funct_arithmetic_funct == 4'h5 + ? io_in1 ^ io_in2 + : io_funct_arithmetic_funct == 4'h4 + ? {63'h0, io_in1 < io_in2} + : io_funct_arithmetic_funct == 4'h3 + ? {63'h0, $signed(io_in1) < $signed(io_in2)} + : io_funct_arithmetic_funct == 4'h2 + ? {io_funct_op32 + ? {{32{_GEN_13[0]}}, _GEN_13[0]} + : {_right_barrel_shifter_io_out[0], + _right_barrel_shifter_io_out[1], + _right_barrel_shifter_io_out[2], + _right_barrel_shifter_io_out[3], + _right_barrel_shifter_io_out[4], + _GEN_12[50:47] + | {_right_barrel_shifter_io_out[7:6], + _right_barrel_shifter_io_out[9:8]} & 4'h5, + _GEN_12[46:39] | _GEN_8 & 8'h55, + _GEN_13}, + _GEN_9[1], + _GEN_12[21] | _GEN_6[2], + {_GEN_6[3], 1'h0} | _GEN_10 & 2'h1, + _GEN_12[18:15] + | {_right_barrel_shifter_io_out[39:38], + _right_barrel_shifter_io_out[41:40]} & 4'h5, + _GEN_12[14:7] | _GEN_11 & 8'h55, + _GEN_11[1], + _GEN_12[5] | _right_barrel_shifter_io_out[50], + _right_barrel_shifter_io_out[51], + _right_barrel_shifter_io_out[52], + {_GEN_12[2:0], 1'h0} + | {_right_barrel_shifter_io_out[55:54], + _right_barrel_shifter_io_out[57:56]} & 4'h5, + _right_barrel_shifter_io_out[57], + _right_barrel_shifter_io_out[58], + _right_barrel_shifter_io_out[59], + _right_barrel_shifter_io_out[60], + _right_barrel_shifter_io_out[61], + _right_barrel_shifter_io_out[62], + _right_barrel_shifter_io_out[63]} + : io_funct_arithmetic_funct == 4'h1 + ? (io_funct_op32 + ? {{32{addsub_record[31]}}, addsub_record[31:0]} + : addsub_record) + : 64'h0; +endmodule + +module BranchEvaluator( + input io_req_valid, + input [63:0] io_req_bits_ALU_Result, + input [3:0] io_req_bits_BranchType, + input [63:0] io_req_bits_destPC, + io_req_bits_pc_addr, + input io_req_bits_bp_taken, + output io_out_valid, + output [63:0] io_out_bits_pc +); + + wire branch_taken = + io_req_bits_BranchType == 4'h6 + ? ~(io_req_bits_ALU_Result[0]) + : io_req_bits_BranchType == 4'h4 + ? ~(io_req_bits_ALU_Result[0]) + : io_req_bits_BranchType == 4'h5 | io_req_bits_BranchType == 4'h3 + ? io_req_bits_ALU_Result[0] + : io_req_bits_BranchType == 4'h2 + ? (|io_req_bits_ALU_Result) + : io_req_bits_BranchType == 4'h1 & ~(|io_req_bits_ALU_Result); + assign io_out_valid = + io_req_valid + & (io_req_bits_BranchType == 4'h6 | io_req_bits_BranchType == 4'h5 + | io_req_bits_BranchType == 4'h4 | io_req_bits_BranchType == 4'h3 + | io_req_bits_BranchType == 4'h2 | io_req_bits_BranchType == 4'h1 + ? io_req_bits_bp_taken != branch_taken + : io_req_bits_BranchType == 4'h8 & io_req_bits_destPC != io_req_bits_ALU_Result); + assign io_out_bits_pc = + io_req_bits_BranchType == 4'h8 + ? {io_req_bits_ALU_Result[63:1], 1'h0} + : branch_taken ? io_req_bits_destPC : io_req_bits_pc_addr + 64'h4; +endmodule + +module BypassingUnit( + input io_ID_in_rs1_index_valid, + input [4:0] io_ID_in_rs1_index_bits, + input io_ID_in_rs2_index_valid, + input [4:0] io_ID_in_rs2_index_bits, + input io_EX_in_valid, + io_EX_in_bits_rd_valid, + input [4:0] io_EX_in_bits_rd_bits_index, + input [63:0] io_EX_in_bits_rd_bits_value, + input io_WB_in_valid, + io_WB_in_bits_rd_valid, + input [4:0] io_WB_in_bits_rd_bits_index, + input [63:0] io_WB_in_bits_rd_bits_value, + output io_ID_out_rs1_value_valid, + output [63:0] io_ID_out_rs1_value_bits, + output io_ID_out_rs1_bypassMatchAtEX, + io_ID_out_rs1_bypassMatchAtWB, + io_ID_out_rs2_value_valid, + output [63:0] io_ID_out_rs2_value_bits, + output io_ID_out_rs2_bypassMatchAtEX, + io_ID_out_rs2_bypassMatchAtWB +); + + wire WB_rd_and_ID_rs1_matches_not_zero = + (|io_ID_in_rs1_index_bits) & io_ID_in_rs1_index_bits == io_WB_in_bits_rd_bits_index + & io_ID_in_rs1_index_valid & io_WB_in_valid; + wire EX_rd_and_ID_rs1_matches_not_zero = + (|io_ID_in_rs1_index_bits) & io_ID_in_rs1_index_bits == io_EX_in_bits_rd_bits_index + & io_ID_in_rs1_index_valid & io_EX_in_valid; + wire WB_rd_and_ID_rs2_matches_not_zero = + (|io_ID_in_rs2_index_bits) & io_ID_in_rs2_index_bits == io_WB_in_bits_rd_bits_index + & io_ID_in_rs2_index_valid & io_WB_in_valid; + wire EX_rd_and_ID_rs2_matches_not_zero = + (|io_ID_in_rs2_index_bits) & io_ID_in_rs2_index_bits == io_EX_in_bits_rd_bits_index + & io_ID_in_rs2_index_valid & io_EX_in_valid; + assign io_ID_out_rs1_value_valid = + EX_rd_and_ID_rs1_matches_not_zero + ? io_EX_in_bits_rd_valid + : WB_rd_and_ID_rs1_matches_not_zero & io_WB_in_bits_rd_valid; + assign io_ID_out_rs1_value_bits = + EX_rd_and_ID_rs1_matches_not_zero + ? io_EX_in_bits_rd_bits_value + : io_WB_in_bits_rd_bits_value; + assign io_ID_out_rs1_bypassMatchAtEX = EX_rd_and_ID_rs1_matches_not_zero; + assign io_ID_out_rs1_bypassMatchAtWB = WB_rd_and_ID_rs1_matches_not_zero; + assign io_ID_out_rs2_value_valid = + EX_rd_and_ID_rs2_matches_not_zero + ? io_EX_in_bits_rd_valid + : WB_rd_and_ID_rs2_matches_not_zero & io_WB_in_bits_rd_valid; + assign io_ID_out_rs2_value_bits = + EX_rd_and_ID_rs2_matches_not_zero + ? io_EX_in_bits_rd_bits_value + : io_WB_in_bits_rd_bits_value; + assign io_ID_out_rs2_bypassMatchAtEX = EX_rd_and_ID_rs2_matches_not_zero; + assign io_ID_out_rs2_bypassMatchAtWB = WB_rd_and_ID_rs2_matches_not_zero; +endmodule + +module VectorLdstUnit( + input clock, + reset, + io_signalIn_valid, + input [63:0] io_signalIn_bits_scalar_rs2Value, + io_signalIn_bits_scalar_immediate, + input [4:0] io_signalIn_bits_scalar_rdIndex, + io_signalIn_bits_vector_vs2, + io_signalIn_bits_vector_vd, + input [63:0] io_signalIn_bits_vector_scalarVal, + input [2:0] io_signalIn_bits_vector_vectorDecode_mop, + input io_signalIn_bits_vector_vectorDecode_vm, + input [3:0] io_signalIn_bits_vector_scalarDecode_branch, + input [2:0] io_signalIn_bits_vector_scalarDecode_writeback_selector, + input [1:0] io_signalIn_bits_vector_scalarDecode_memory_function, + io_signalIn_bits_vector_scalarDecode_memory_length, + input io_signalIn_bits_vector_scalarDecode_mem_sext, + input [2:0] io_signalIn_bits_vector_scalarDecode_csr_funct, + input io_signalIn_bits_vector_scalarDecode_fence, + io_signalIn_bits_vector_scalarDecode_vector, + io_signalIn_bits_vector_vecConf_vtype_vill, + io_signalIn_bits_vector_vecConf_vtype_vma, + io_signalIn_bits_vector_vecConf_vtype_vta, + input [2:0] io_signalIn_bits_vector_vecConf_vtype_vsew, + io_signalIn_bits_vector_vecConf_vtype_vlmul, + input [5:0] io_signalIn_bits_vector_vecConf_vl, + input [63:0] io_signalIn_bits_vector_pc_addr, + io_readVrf_resp_vs2Out, + io_readVrf_resp_vdOut, + input io_readVrf_resp_vm, + io_dcache_ar_ready, + io_dcache_aw_ready, + io_dcache_b_valid, + io_dcache_r_valid, + input [63:0] io_dcache_r_bits_data, + input io_dcache_w_ready, + output io_signalIn_ready, + output [2:0] io_readVrf_req_sew, + output [4:0] io_readVrf_req_idx, + io_readVrf_req_vs2, + io_readVrf_req_vd, + output io_scalarResp_valid, + output [63:0] io_scalarResp_bits_data, + output io_vectorResp_toVRF_valid, + output [4:0] io_vectorResp_toVRF_bits_vd, + output [2:0] io_vectorResp_toVRF_bits_vtype_vsew, + output [4:0] io_vectorResp_toVRF_bits_index, + output io_vectorResp_toVRF_bits_last, + output [63:0] io_vectorResp_toVRF_bits_data, + output io_vectorResp_toVRF_bits_writeReq, + io_dcache_ar_valid, + output [63:0] io_dcache_ar_bits_addr, + output io_dcache_aw_valid, + output [63:0] io_dcache_aw_bits_addr, + output io_dcache_w_valid, + output [63:0] io_dcache_w_bits_data, + output [7:0] io_dcache_w_bits_strb, + output io_toExWbReg_valid, + output [63:0] io_toExWbReg_bits_dataSignals_pc_addr, + output [3:0] io_toExWbReg_bits_ctrlSignals_decode_branch, + output [2:0] io_toExWbReg_bits_ctrlSignals_decode_writeback_selector, + output [1:0] io_toExWbReg_bits_ctrlSignals_decode_memory_function, + output [2:0] io_toExWbReg_bits_ctrlSignals_decode_csr_funct, + output io_toExWbReg_bits_ctrlSignals_decode_fence, + output [4:0] io_toExWbReg_bits_ctrlSignals_rd_index, + output io_toExWbReg_bits_vectorCsrPorts_vtype_vill, + io_toExWbReg_bits_vectorCsrPorts_vtype_vma, + io_toExWbReg_bits_vectorCsrPorts_vtype_vta, + output [2:0] io_toExWbReg_bits_vectorCsrPorts_vtype_vsew, + io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul, + output [5:0] io_toExWbReg_bits_vectorCsrPorts_vl, + output io_toExWbReg_bits_vectorExecNum_valid, + output [4:0] io_toExWbReg_bits_vectorExecNum_bits +); + + reg scalarReqReg_valid; + reg [63:0] scalarReqReg_bits_rs2Value; + reg [63:0] scalarReqReg_bits_immediate; + reg [4:0] scalarReqReg_bits_rdIndex; + reg scalarReqRegNext_valid; + reg [4:0] vectorReqReg_vs2; + reg [4:0] vectorReqReg_vd; + reg [63:0] vectorReqReg_scalarVal; + reg [2:0] vectorReqReg_vectorDecode_mop; + reg vectorReqReg_vectorDecode_vm; + reg [3:0] vectorReqReg_scalarDecode_branch; + reg [2:0] vectorReqReg_scalarDecode_writeback_selector; + reg [1:0] vectorReqReg_scalarDecode_memory_function; + reg [1:0] vectorReqReg_scalarDecode_memory_length; + reg vectorReqReg_scalarDecode_mem_sext; + reg [2:0] vectorReqReg_scalarDecode_csr_funct; + reg vectorReqReg_scalarDecode_fence; + reg vectorReqReg_scalarDecode_vector; + reg vectorReqReg_vecConf_vtype_vill; + reg vectorReqReg_vecConf_vtype_vma; + reg vectorReqReg_vecConf_vtype_vta; + reg [2:0] vectorReqReg_vecConf_vtype_vsew; + reg [2:0] vectorReqReg_vecConf_vtype_vlmul; + reg [5:0] vectorReqReg_vecConf_vl; + reg [63:0] vectorReqReg_pc_addr; + reg hasVectorInst; + reg [4:0] vectorReqRegNext_vd; + reg [1:0] vectorReqRegNext_scalarDecode_memory_function; + reg [1:0] vectorReqRegNext_scalarDecode_memory_length; + reg vectorReqRegNext_scalarDecode_mem_sext; + reg [2:0] vectorReqRegNext_vecConf_vtype_vsew; + reg hasVectorInstNext; + reg [4:0] vecIdx; + reg [4:0] executedNum; + reg [4:0] vecIdxToVrfWrite; + reg [63:0] accumulator; + wire vecMemAccessLast = + hasVectorInst & {1'h0, vecIdx} == vectorReqReg_vecConf_vl - 6'h1; + `ifndef SYNTHESIS + always @(posedge clock) begin + if (~reset & ~(scalarReqReg_valid | ~hasVectorInst)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: scalarReq false and vectorReq true\n at VectorLdstUnit.scala:76 assert(scalarReqReg.valid || !hasVectorInst, \"scalarReq false and vectorReq true\")\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS + wire _io_toExWbReg_valid_T_4 = io_dcache_aw_ready & io_dcache_w_ready; + wire _io_signalIn_ready_output = + ~scalarReqReg_valid + | (vectorReqReg_scalarDecode_memory_function == 2'h1 + ? io_dcache_ar_ready + : vectorReqReg_scalarDecode_memory_function == 2'h2 & _io_toExWbReg_valid_T_4) + & (~hasVectorInst | vecMemAccessLast); + wire [3:0][63:0] _GEN = + {{{io_readVrf_resp_vs2Out[60:0], 3'h0}}, + {{io_readVrf_resp_vs2Out[61:0], 2'h0}}, + {{io_readVrf_resp_vs2Out[62:0], 1'h0}}, + {io_readVrf_resp_vs2Out}}; + wire [63:0] _GEN_0 = _GEN[vectorReqReg_scalarDecode_memory_length]; + wire [7:0][63:0] _GEN_1 = + {{vectorReqReg_scalarVal}, + {vectorReqReg_scalarVal}, + {vectorReqReg_scalarVal}, + {_GEN_0}, + {accumulator}, + {_GEN_0}, + {accumulator}, + {scalarReqReg_bits_immediate}}; + wire [63:0] _GEN_2 = + vectorReqReg_scalarVal + _GEN_1[vectorReqReg_vectorDecode_mop]; + wire [3:0][7:0] _GEN_3 = + {{8'hFF}, {8'hF}, {8'h3}, {{7'h0, vectorReqReg_scalarDecode_memory_length == 2'h0}}}; + wire [3:0][63:0] _GEN_4 = + {{io_dcache_r_bits_data}, + {{vectorReqRegNext_scalarDecode_mem_sext ? {32{io_dcache_r_bits_data[31]}} : 32'h0, + io_dcache_r_bits_data[31:0]}}, + {{vectorReqRegNext_scalarDecode_mem_sext ? {48{io_dcache_r_bits_data[15]}} : 48'h0, + io_dcache_r_bits_data[15:0]}}, + {(|vectorReqRegNext_scalarDecode_memory_length) + ? io_dcache_r_bits_data + : {vectorReqRegNext_scalarDecode_mem_sext + ? {56{io_dcache_r_bits_data[7]}} + : 56'h0, + io_dcache_r_bits_data[7:0]}}}; + reg io_scalarResp_valid_REG; + wire _io_vectorResp_toVRF_valid_output = + scalarReqRegNext_valid & hasVectorInstNext; + reg io_vectorResp_toVRF_bits_last_REG; + wire [3:0][63:0] _GEN_5 = + {{io_dcache_r_bits_data}, + {{32'h0, io_dcache_r_bits_data[31:0]}}, + {{48'h0, io_dcache_r_bits_data[15:0]}}, + {(|vectorReqRegNext_scalarDecode_memory_length) + ? io_dcache_r_bits_data + : {56'h0, io_dcache_r_bits_data[7:0]}}}; + wire _io_toExWbReg_bits_vectorExecNum_bits_T = + vectorReqReg_vectorDecode_vm | io_readVrf_resp_vm; + reg io_vectorResp_toVRF_bits_writeReq_REG; + wire _io_toExWbReg_valid_output = + scalarReqReg_valid + & (vectorReqReg_scalarDecode_memory_function == 2'h1 + ? io_dcache_ar_ready + : vectorReqReg_scalarDecode_memory_function != 2'h2 | _io_toExWbReg_valid_T_4) + & (~vectorReqReg_scalarDecode_vector | vecMemAccessLast); + always @(posedge clock) begin + automatic logic _T_9; + _T_9 = io_signalIn_valid & _io_signalIn_ready_output; + if (reset) begin + scalarReqReg_valid <= 1'h0; + hasVectorInst <= 1'h0; + vecIdx <= 5'h0; + executedNum <= 5'h0; + accumulator <= 64'h0; + end + else begin + automatic logic _T_3; + _T_3 = scalarReqReg_valid & (~hasVectorInst | vecMemAccessLast); + scalarReqReg_valid <= _T_9 | ~_T_3 & scalarReqReg_valid; + if (_T_9) + hasVectorInst <= + io_signalIn_bits_vector_scalarDecode_vector + & (|io_signalIn_bits_vector_vectorDecode_mop); + else + hasVectorInst <= ~(_T_3 & hasVectorInst) & hasVectorInst; + if (_T_9 | vecMemAccessLast | ~hasVectorInst) begin + vecIdx <= 5'h0; + executedNum <= 5'h0; + accumulator <= 64'h0; + end + else begin + vecIdx <= vecIdx + 5'h1; + executedNum <= + executedNum + {4'h0, vectorReqReg_vectorDecode_vm | io_readVrf_resp_vm}; + accumulator <= + accumulator + + (vectorReqReg_vectorDecode_mop == 3'h1 + ? {60'h0, + vectorReqReg_vecConf_vtype_vsew == 3'h3 + ? 4'h8 + : {1'h0, + vectorReqReg_vecConf_vtype_vsew == 3'h2 + ? 3'h4 + : {1'h0, vectorReqReg_vecConf_vtype_vsew == 3'h1 ? 2'h2 : 2'h1}}} + : scalarReqReg_bits_rs2Value); + end + end + if (_T_9) begin + scalarReqReg_bits_rs2Value <= io_signalIn_bits_scalar_rs2Value; + scalarReqReg_bits_immediate <= io_signalIn_bits_scalar_immediate; + scalarReqReg_bits_rdIndex <= io_signalIn_bits_scalar_rdIndex; + vectorReqReg_vs2 <= io_signalIn_bits_vector_vs2; + vectorReqReg_vd <= io_signalIn_bits_vector_vd; + vectorReqReg_scalarVal <= io_signalIn_bits_vector_scalarVal; + vectorReqReg_vectorDecode_mop <= io_signalIn_bits_vector_vectorDecode_mop; + vectorReqReg_vectorDecode_vm <= io_signalIn_bits_vector_vectorDecode_vm; + vectorReqReg_scalarDecode_branch <= io_signalIn_bits_vector_scalarDecode_branch; + vectorReqReg_scalarDecode_writeback_selector <= + io_signalIn_bits_vector_scalarDecode_writeback_selector; + vectorReqReg_scalarDecode_memory_function <= + io_signalIn_bits_vector_scalarDecode_memory_function; + vectorReqReg_scalarDecode_memory_length <= + io_signalIn_bits_vector_scalarDecode_memory_length; + vectorReqReg_scalarDecode_mem_sext <= io_signalIn_bits_vector_scalarDecode_mem_sext; + vectorReqReg_scalarDecode_csr_funct <= + io_signalIn_bits_vector_scalarDecode_csr_funct; + vectorReqReg_scalarDecode_fence <= io_signalIn_bits_vector_scalarDecode_fence; + vectorReqReg_scalarDecode_vector <= io_signalIn_bits_vector_scalarDecode_vector; + vectorReqReg_vecConf_vtype_vill <= io_signalIn_bits_vector_vecConf_vtype_vill; + vectorReqReg_vecConf_vtype_vma <= io_signalIn_bits_vector_vecConf_vtype_vma; + vectorReqReg_vecConf_vtype_vta <= io_signalIn_bits_vector_vecConf_vtype_vta; + vectorReqReg_vecConf_vtype_vsew <= io_signalIn_bits_vector_vecConf_vtype_vsew; + vectorReqReg_vecConf_vtype_vlmul <= io_signalIn_bits_vector_vecConf_vtype_vlmul; + vectorReqReg_vecConf_vl <= io_signalIn_bits_vector_vecConf_vl; + vectorReqReg_pc_addr <= io_signalIn_bits_vector_pc_addr; + end + scalarReqRegNext_valid <= scalarReqReg_valid; + vectorReqRegNext_vd <= vectorReqReg_vd; + vectorReqRegNext_scalarDecode_memory_function <= + vectorReqReg_scalarDecode_memory_function; + vectorReqRegNext_scalarDecode_memory_length <= + vectorReqReg_scalarDecode_memory_length; + vectorReqRegNext_scalarDecode_mem_sext <= vectorReqReg_scalarDecode_mem_sext; + vectorReqRegNext_vecConf_vtype_vsew <= vectorReqReg_vecConf_vtype_vsew; + hasVectorInstNext <= hasVectorInst; + vecIdxToVrfWrite <= vecIdx; + io_scalarResp_valid_REG <= vecMemAccessLast; + io_vectorResp_toVRF_bits_last_REG <= vecMemAccessLast; + io_vectorResp_toVRF_bits_writeReq_REG <= _io_toExWbReg_bits_vectorExecNum_bits_T; + end // always @(posedge) + assign io_signalIn_ready = _io_signalIn_ready_output; + assign io_readVrf_req_sew = vectorReqReg_vecConf_vtype_vsew; + assign io_readVrf_req_idx = vecIdx; + assign io_readVrf_req_vs2 = vectorReqReg_vs2; + assign io_readVrf_req_vd = vectorReqReg_vd; + assign io_scalarResp_valid = + (vectorReqRegNext_scalarDecode_memory_function == 2'h1 + ? io_dcache_r_valid + : vectorReqRegNext_scalarDecode_memory_function == 2'h2 & io_dcache_b_valid) + & scalarReqRegNext_valid & (~hasVectorInstNext | io_scalarResp_valid_REG); + assign io_scalarResp_bits_data = _GEN_4[vectorReqRegNext_scalarDecode_memory_length]; + assign io_vectorResp_toVRF_valid = _io_vectorResp_toVRF_valid_output; + assign io_vectorResp_toVRF_bits_vd = vectorReqRegNext_vd; + assign io_vectorResp_toVRF_bits_vtype_vsew = vectorReqRegNext_vecConf_vtype_vsew; + assign io_vectorResp_toVRF_bits_index = vecIdxToVrfWrite; + assign io_vectorResp_toVRF_bits_last = io_vectorResp_toVRF_bits_last_REG; + assign io_vectorResp_toVRF_bits_data = + _GEN_5[vectorReqRegNext_scalarDecode_memory_length]; + assign io_vectorResp_toVRF_bits_writeReq = + _io_vectorResp_toVRF_valid_output & io_vectorResp_toVRF_bits_writeReq_REG + & vectorReqRegNext_scalarDecode_memory_function == 2'h1; + assign io_dcache_ar_valid = + scalarReqReg_valid & vectorReqReg_scalarDecode_memory_function == 2'h1; + assign io_dcache_ar_bits_addr = _GEN_2; + assign io_dcache_aw_valid = + scalarReqReg_valid & vectorReqReg_scalarDecode_memory_function == 2'h2 + & (~hasVectorInst | vectorReqReg_vectorDecode_vm | io_readVrf_resp_vm); + assign io_dcache_aw_bits_addr = _GEN_2; + assign io_dcache_w_valid = + scalarReqReg_valid & vectorReqReg_scalarDecode_memory_function == 2'h2 + & (~hasVectorInst | vectorReqReg_vectorDecode_vm | io_readVrf_resp_vm); + assign io_dcache_w_bits_data = + hasVectorInst ? io_readVrf_resp_vdOut : scalarReqReg_bits_rs2Value; + assign io_dcache_w_bits_strb = _GEN_3[vectorReqReg_scalarDecode_memory_length]; + assign io_toExWbReg_valid = _io_toExWbReg_valid_output; + assign io_toExWbReg_bits_dataSignals_pc_addr = vectorReqReg_pc_addr; + assign io_toExWbReg_bits_ctrlSignals_decode_branch = vectorReqReg_scalarDecode_branch; + assign io_toExWbReg_bits_ctrlSignals_decode_writeback_selector = + vectorReqReg_scalarDecode_writeback_selector; + assign io_toExWbReg_bits_ctrlSignals_decode_memory_function = + vectorReqReg_scalarDecode_memory_function; + assign io_toExWbReg_bits_ctrlSignals_decode_csr_funct = + vectorReqReg_scalarDecode_csr_funct; + assign io_toExWbReg_bits_ctrlSignals_decode_fence = vectorReqReg_scalarDecode_fence; + assign io_toExWbReg_bits_ctrlSignals_rd_index = scalarReqReg_bits_rdIndex; + assign io_toExWbReg_bits_vectorCsrPorts_vtype_vill = vectorReqReg_vecConf_vtype_vill; + assign io_toExWbReg_bits_vectorCsrPorts_vtype_vma = vectorReqReg_vecConf_vtype_vma; + assign io_toExWbReg_bits_vectorCsrPorts_vtype_vta = vectorReqReg_vecConf_vtype_vta; + assign io_toExWbReg_bits_vectorCsrPorts_vtype_vsew = vectorReqReg_vecConf_vtype_vsew; + assign io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul = vectorReqReg_vecConf_vtype_vlmul; + assign io_toExWbReg_bits_vectorCsrPorts_vl = vectorReqReg_vecConf_vl; + assign io_toExWbReg_bits_vectorExecNum_valid = + _io_toExWbReg_valid_output & vectorReqReg_scalarDecode_vector + & (vectorReqReg_scalarDecode_memory_function == 2'h1 + | vectorReqReg_scalarDecode_memory_function == 2'h2); + assign io_toExWbReg_bits_vectorExecNum_bits = + executedNum + {4'h0, _io_toExWbReg_bits_vectorExecNum_bits_T}; +endmodule + +module CSRFile( + input clock, + reset, + input [11:0] io_csr_addr, + input io_writeReq_valid, + input [63:0] io_writeReq_bits_data, + input io_fromCPU_cpu_operating, + io_fromCPU_inst_retire, + input [63:0] io_fromCPU_hartid, + input io_fromCPU_vectorExecNum_valid, + input [4:0] io_fromCPU_vectorExecNum_bits, + input io_exception_valid, + input [63:0] io_exception_bits_mepc_write, + io_exception_bits_mcause_write, + input io_vectorCsrPorts_vtype_vill, + io_vectorCsrPorts_vtype_vma, + io_vectorCsrPorts_vtype_vta, + input [2:0] io_vectorCsrPorts_vtype_vsew, + io_vectorCsrPorts_vtype_vlmul, + input [5:0] io_vectorCsrPorts_vl, + output [63:0] io_readResp_data +); + + reg [63:0] cycle; + reg [25:0] counterWrap_c_value; + reg [63:0] time_0; + reg [63:0] instret; + reg [63:0] mhpmcounter3; + reg [63:0] mstatus; + reg [63:0] misa; + reg [63:0] medeleg; + reg [63:0] mideleg; + reg [63:0] mie; + reg [63:0] mtvec; + reg [63:0] mcounteren; + reg [63:0] mscratch; + reg [63:0] mepc; + reg [63:0] mcause; + reg [63:0] mtval; + reg [63:0] mip; + reg [63:0] mtinst; + reg [63:0] mtval2; + wire _T_5 = io_csr_addr == 12'h300; + wire _T_6 = io_csr_addr == 12'h301; + wire _T_7 = io_csr_addr == 12'h302; + wire _T_8 = io_csr_addr == 12'h303; + wire _T_9 = io_csr_addr == 12'h304; + wire _T_10 = io_csr_addr == 12'h305; + wire _T_11 = io_csr_addr == 12'h306; + wire _T_12 = io_csr_addr == 12'h340; + wire _T_13 = io_csr_addr == 12'h341; + wire _T_14 = io_csr_addr == 12'h342; + wire _T_15 = io_csr_addr == 12'h343; + wire _T_16 = io_csr_addr == 12'h344; + wire _T_17 = io_csr_addr == 12'h34A; + wire _T_18 = io_csr_addr == 12'h34B; + wire _T_19 = io_csr_addr == 12'hB00; + wire _T_20 = io_csr_addr == 12'hB02; + wire _T_21 = io_csr_addr == 12'hB03; + always @(posedge clock) begin + if (reset) begin + cycle <= 64'h0; + counterWrap_c_value <= 26'h0; + time_0 <= 64'h0; + instret <= 64'h0; + mhpmcounter3 <= 64'h0; + mstatus <= 64'h0; + misa <= 64'h8000000000201100; + medeleg <= 64'h0; + mideleg <= 64'h0; + mie <= 64'h0; + mtvec <= 64'h0; + mcounteren <= 64'h0; + mscratch <= 64'h0; + mepc <= 64'h0; + mcause <= 64'h0; + mtval <= 64'h0; + mip <= 64'h0; + mtinst <= 64'h0; + mtval2 <= 64'h0; + end + else begin + automatic logic _T_4; + _T_4 = io_writeReq_valid & ~io_exception_valid; + if (_T_4 & _T_19) + cycle <= io_writeReq_bits_data; + else if (io_fromCPU_cpu_operating) + cycle <= cycle + 64'h1; + if (counterWrap_c_value == 26'h2FAF07F) begin + counterWrap_c_value <= 26'h0; + time_0 <= time_0 + 64'h1; + end + else + counterWrap_c_value <= counterWrap_c_value + 26'h1; + if (_T_4 & _T_20) + instret <= io_writeReq_bits_data; + else if (io_fromCPU_inst_retire) + instret <= instret + 64'h1; + if (_T_4 & _T_21) + mhpmcounter3 <= io_writeReq_bits_data; + else if (io_fromCPU_inst_retire) + mhpmcounter3 <= + mhpmcounter3 + + {59'h0, + io_fromCPU_vectorExecNum_valid ? io_fromCPU_vectorExecNum_bits : 5'h1}; + if (_T_4 & _T_5) + mstatus <= io_writeReq_bits_data; + if (_T_4 & _T_6) + misa <= io_writeReq_bits_data; + if (_T_4 & _T_7) + medeleg <= io_writeReq_bits_data; + if (_T_4 & _T_8) + mideleg <= io_writeReq_bits_data; + if (_T_4 & _T_9) + mie <= io_writeReq_bits_data; + if (_T_4 & _T_10) + mtvec <= io_writeReq_bits_data; + if (_T_4 & _T_11) + mcounteren <= io_writeReq_bits_data; + if (_T_4 & _T_12) + mscratch <= io_writeReq_bits_data; + if (io_exception_valid) begin + mepc <= io_exception_bits_mepc_write; + mcause <= io_exception_bits_mcause_write; + end + else begin + if (_T_4 & _T_13) + mepc <= {io_writeReq_bits_data[63:2], 2'h0}; + if (_T_4 & _T_14) + mcause <= io_writeReq_bits_data; + end + if (_T_4 & _T_15) + mtval <= io_writeReq_bits_data; + if (_T_4 & _T_16) + mip <= io_writeReq_bits_data; + if (_T_4 & _T_17) + mtinst <= io_writeReq_bits_data; + if (_T_4 & _T_18) + mtval2 <= io_writeReq_bits_data; + end + end // always @(posedge) + assign io_readResp_data = + io_exception_valid + ? {mtvec[63:2], 2'h0} + : _T_21 + ? mhpmcounter3 + : _T_20 + ? instret + : _T_19 + ? cycle + : _T_18 + ? mtval2 + : _T_17 + ? mtinst + : _T_16 + ? mip + : _T_15 + ? mtval + : _T_14 + ? mcause + : _T_13 + ? mepc + : _T_12 + ? mscratch + : _T_11 + ? mcounteren + : _T_10 + ? mtvec + : _T_9 + ? mie + : _T_8 + ? mideleg + : _T_7 + ? medeleg + : _T_6 + ? misa + : _T_5 + ? mstatus + : io_csr_addr == 12'hC22 + ? 64'h20 + : io_csr_addr == 12'hC21 + ? (io_vectorCsrPorts_vtype_vill + ? 64'h8000000000000000 + : {56'h0, + io_vectorCsrPorts_vtype_vma, + io_vectorCsrPorts_vtype_vta, + io_vectorCsrPorts_vtype_vsew, + io_vectorCsrPorts_vtype_vlmul}) + : io_csr_addr == 12'hC20 + ? {58'h0, + io_vectorCsrPorts_vl} + : io_csr_addr == 12'hF15 + ? 64'h0 + : io_csr_addr == 12'hF14 + ? io_fromCPU_hartid + : io_csr_addr == 12'hF13 + ? 64'h1145141919810 + : io_csr_addr == 12'hF12 + ? 64'h53686F7461636F6E + : io_csr_addr == 12'hF11 + ? 64'h426F79734C6F7665 + : io_csr_addr == 12'hC02 + ? instret + : io_csr_addr == 12'hC01 + ? time_0 + : io_csr_addr == 12'hC00 + ? cycle + : 64'h0; +endmodule + +module CSRUnit( + input clock, + reset, + input [3:0] io_req_bits_funct_branch, + input [2:0] io_req_bits_funct_csr_funct, + input [63:0] io_req_bits_data, + input [11:0] io_req_bits_csr_addr, + input io_fromCPU_cpu_operating, + io_fromCPU_inst_retire, + input [63:0] io_fromCPU_hartid, + input io_fromCPU_vectorExecNum_valid, + input [4:0] io_fromCPU_vectorExecNum_bits, + input io_exception_valid, + input [63:0] io_exception_bits_mepc_write, + io_exception_bits_mcause_write, + input io_vectorCsrPorts_vtype_vill, + io_vectorCsrPorts_vtype_vma, + io_vectorCsrPorts_vtype_vta, + input [2:0] io_vectorCsrPorts_vtype_vsew, + io_vectorCsrPorts_vtype_vlmul, + input [5:0] io_vectorCsrPorts_vl, + output [63:0] io_resp_data +); + + wire [63:0] _csrFile_io_readResp_data; + CSRFile csrFile ( + .clock (clock), + .reset (reset), + .io_csr_addr + (io_req_bits_funct_branch == 4'hA ? 12'h341 : io_req_bits_csr_addr), + .io_writeReq_valid + (~(io_req_bits_funct_csr_funct == 3'h5 | io_req_bits_funct_csr_funct == 3'h4) + & (io_req_bits_funct_csr_funct == 3'h3 | io_req_bits_funct_csr_funct == 3'h2 + | io_req_bits_funct_csr_funct == 3'h1)), + .io_writeReq_bits_data + (io_req_bits_funct_csr_funct == 3'h3 + ? io_req_bits_data + : io_req_bits_funct_csr_funct == 3'h2 + ? _csrFile_io_readResp_data | io_req_bits_data + : io_req_bits_funct_csr_funct == 3'h1 + ? _csrFile_io_readResp_data & ~io_req_bits_data + : io_req_bits_data), + .io_fromCPU_cpu_operating (io_fromCPU_cpu_operating), + .io_fromCPU_inst_retire (io_fromCPU_inst_retire), + .io_fromCPU_hartid (io_fromCPU_hartid), + .io_fromCPU_vectorExecNum_valid (io_fromCPU_vectorExecNum_valid), + .io_fromCPU_vectorExecNum_bits (io_fromCPU_vectorExecNum_bits), + .io_exception_valid (io_exception_valid), + .io_exception_bits_mepc_write (io_exception_bits_mepc_write), + .io_exception_bits_mcause_write (io_exception_bits_mcause_write), + .io_vectorCsrPorts_vtype_vill (io_vectorCsrPorts_vtype_vill), + .io_vectorCsrPorts_vtype_vma (io_vectorCsrPorts_vtype_vma), + .io_vectorCsrPorts_vtype_vta (io_vectorCsrPorts_vtype_vta), + .io_vectorCsrPorts_vtype_vsew (io_vectorCsrPorts_vtype_vsew), + .io_vectorCsrPorts_vtype_vlmul (io_vectorCsrPorts_vtype_vlmul), + .io_vectorCsrPorts_vl (io_vectorCsrPorts_vl), + .io_readResp_data (_csrFile_io_readResp_data) + ); + assign io_resp_data = _csrFile_io_readResp_data; +endmodule + +module Multiplier_nxn( + input [7:0] io_multiplicand, + io_multiplier, + output [15:0] io_out +); + + assign io_out = + {8'h0, {8{io_multiplier[0]}} & io_multiplicand} + + {7'h0, {8{io_multiplier[1]}} & io_multiplicand, 1'h0} + + {6'h0, {8{io_multiplier[2]}} & io_multiplicand, 2'h0} + + {5'h0, {8{io_multiplier[3]}} & io_multiplicand, 3'h0} + + {4'h0, {8{io_multiplier[4]}} & io_multiplicand, 4'h0} + + {3'h0, {8{io_multiplier[5]}} & io_multiplicand, 5'h0} + + {2'h0, {8{io_multiplier[6]}} & io_multiplicand, 6'h0} + + {1'h0, {8{io_multiplier[7]}} & io_multiplicand, 7'h0}; +endmodule + +module Multiplier_64x8( + input [63:0] io_multiplicand, + input [7:0] io_multiplier, + output [71:0] io_out +); + + wire [15:0] _subMultipliers_7_io_out; + wire [15:0] _subMultipliers_6_io_out; + wire [15:0] _subMultipliers_5_io_out; + wire [15:0] _subMultipliers_4_io_out; + wire [15:0] _subMultipliers_3_io_out; + wire [15:0] _subMultipliers_2_io_out; + wire [15:0] _subMultipliers_1_io_out; + wire [15:0] _subMultipliers_0_io_out; + Multiplier_nxn subMultipliers_0 ( + .io_multiplicand (io_multiplicand[7:0]), + .io_multiplier (io_multiplier), + .io_out (_subMultipliers_0_io_out) + ); + Multiplier_nxn subMultipliers_1 ( + .io_multiplicand (io_multiplicand[15:8]), + .io_multiplier (io_multiplier), + .io_out (_subMultipliers_1_io_out) + ); + Multiplier_nxn subMultipliers_2 ( + .io_multiplicand (io_multiplicand[23:16]), + .io_multiplier (io_multiplier), + .io_out (_subMultipliers_2_io_out) + ); + Multiplier_nxn subMultipliers_3 ( + .io_multiplicand (io_multiplicand[31:24]), + .io_multiplier (io_multiplier), + .io_out (_subMultipliers_3_io_out) + ); + Multiplier_nxn subMultipliers_4 ( + .io_multiplicand (io_multiplicand[39:32]), + .io_multiplier (io_multiplier), + .io_out (_subMultipliers_4_io_out) + ); + Multiplier_nxn subMultipliers_5 ( + .io_multiplicand (io_multiplicand[47:40]), + .io_multiplier (io_multiplier), + .io_out (_subMultipliers_5_io_out) + ); + Multiplier_nxn subMultipliers_6 ( + .io_multiplicand (io_multiplicand[55:48]), + .io_multiplier (io_multiplier), + .io_out (_subMultipliers_6_io_out) + ); + Multiplier_nxn subMultipliers_7 ( + .io_multiplicand (io_multiplicand[63:56]), + .io_multiplier (io_multiplier), + .io_out (_subMultipliers_7_io_out) + ); + assign io_out = + {56'h0, _subMultipliers_0_io_out} + {48'h0, _subMultipliers_1_io_out, 8'h0} + + {40'h0, _subMultipliers_2_io_out, 16'h0} + {32'h0, _subMultipliers_3_io_out, 24'h0} + + {24'h0, _subMultipliers_4_io_out, 32'h0} + {16'h0, _subMultipliers_5_io_out, 40'h0} + + {8'h0, _subMultipliers_6_io_out, 48'h0} + {_subMultipliers_7_io_out, 56'h0}; +endmodule + +module NonPipelinedMultiplier( + input clock, + reset, + io_req_valid, + input [63:0] io_req_bits_multiplicand_bits, + io_req_bits_multiplier_bits, + input io_req_bits_sign, + input [3:0] io_req_bits_decode_arithmetic_funct, + input io_req_bits_decode_op32, + output io_resp_valid, + output [127:0] io_resp_bits_result, + output io_resp_bits_sign, + output [3:0] io_resp_bits_decode_arithmetic_funct, + output io_resp_bits_decode_op32 +); + + wire _io_req_ready_T; + wire [71:0] _multiplier_64x8_io_out; + reg internalReg_valid; + reg internalReg_bits_sign; + reg [127:0] internalReg_bits_result; + reg [63:0] internalReg_bits_multiplicand; + reg [63:0] internalReg_bits_multiplier; + reg [2:0] internalReg_bits_stage; + reg [3:0] internalReg_bits_decode_arithmetic_funct; + reg internalReg_bits_decode_op32; + wire multiplicand_greater_than_multiplier = + io_req_bits_multiplicand_bits > io_req_bits_multiplier_bits; + wire accept_current_request = io_req_valid & _io_req_ready_T; + wire [63:0] executor_multiplier = + accept_current_request + ? (multiplicand_greater_than_multiplier + ? io_req_bits_multiplier_bits + : io_req_bits_multiplicand_bits) + : internalReg_bits_multiplier; + wire [2:0] _executor_stage_T_1 = internalReg_bits_stage + 3'h1; + wire [2:0] executor_stage = accept_current_request ? 3'h0 : _executor_stage_T_1; + wire executor_valid = accept_current_request | internalReg_valid; + assign _io_req_ready_T = ~internalReg_valid; + wire _io_resp_valid_output = + executor_valid & (executor_multiplier[63:8] == 56'h0 | (&executor_stage)); + wire [127:0] _io_resp_bits_result_output = + (accept_current_request ? 128'h0 : internalReg_bits_result) + + ((&executor_stage) + ? {_multiplier_64x8_io_out, 56'h0} + : {8'h0, + executor_stage == 3'h6 + ? {_multiplier_64x8_io_out, 48'h0} + : {8'h0, + executor_stage == 3'h5 + ? {_multiplier_64x8_io_out, 40'h0} + : {8'h0, + executor_stage == 3'h4 + ? {_multiplier_64x8_io_out, 32'h0} + : {8'h0, + executor_stage == 3'h3 + ? {_multiplier_64x8_io_out, 24'h0} + : {8'h0, + executor_stage == 3'h2 + ? {_multiplier_64x8_io_out, 16'h0} + : {8'h0, + executor_stage == 3'h1 + ? {_multiplier_64x8_io_out, 8'h0} + : {8'h0, _multiplier_64x8_io_out}}}}}}}); + always @(posedge clock) begin + if (reset) begin + internalReg_valid <= 1'h0; + internalReg_bits_sign <= 1'h0; + internalReg_bits_result <= 128'h0; + internalReg_bits_multiplicand <= 64'h0; + internalReg_bits_multiplier <= 64'h0; + internalReg_bits_stage <= 3'h0; + internalReg_bits_decode_arithmetic_funct <= 4'h0; + internalReg_bits_decode_op32 <= 1'h0; + end + else begin + automatic logic _T_8 = accept_current_request | internalReg_valid; + internalReg_valid <= _T_8 & ~_io_resp_valid_output & executor_valid; + if (_T_8 & accept_current_request) begin + internalReg_bits_sign <= io_req_bits_sign; + if (multiplicand_greater_than_multiplier) + internalReg_bits_multiplicand <= io_req_bits_multiplicand_bits; + else + internalReg_bits_multiplicand <= io_req_bits_multiplier_bits; + internalReg_bits_decode_arithmetic_funct <= io_req_bits_decode_arithmetic_funct; + internalReg_bits_decode_op32 <= io_req_bits_decode_op32; + end + if (_T_8) begin + internalReg_bits_result <= _io_resp_bits_result_output; + internalReg_bits_multiplier <= {8'h0, executor_multiplier[63:8]}; + if (accept_current_request) + internalReg_bits_stage <= 3'h0; + else + internalReg_bits_stage <= _executor_stage_T_1; + end + end + end // always @(posedge) + Multiplier_64x8 multiplier_64x8 ( + .io_multiplicand + (accept_current_request + ? (multiplicand_greater_than_multiplier + ? io_req_bits_multiplicand_bits + : io_req_bits_multiplier_bits) + : internalReg_bits_multiplicand), + .io_multiplier (executor_multiplier[7:0]), + .io_out (_multiplier_64x8_io_out) + ); + assign io_resp_valid = _io_resp_valid_output; + assign io_resp_bits_result = _io_resp_bits_result_output; + assign io_resp_bits_sign = + accept_current_request ? io_req_bits_sign : internalReg_bits_sign; + assign io_resp_bits_decode_arithmetic_funct = + accept_current_request + ? io_req_bits_decode_arithmetic_funct + : internalReg_bits_decode_arithmetic_funct; + assign io_resp_bits_decode_op32 = + accept_current_request ? io_req_bits_decode_op32 : internalReg_bits_decode_op32; +endmodule + +module NonPipelinedMultiplierWrap( + input clock, + reset, + io_req_valid, + input [63:0] io_req_bits_rs1, + io_req_bits_rs2, + input [3:0] io_req_bits_funct_arithmetic_funct, + input io_req_bits_funct_op32, + output io_resp_valid, + output [63:0] io_resp_bits +); + + wire [127:0] _nonPipelinedMultiplier_io_resp_bits_result; + wire _nonPipelinedMultiplier_io_resp_bits_sign; + wire [3:0] _nonPipelinedMultiplier_io_resp_bits_decode_arithmetic_funct; + wire _nonPipelinedMultiplier_io_resp_bits_decode_op32; + wire rs1_inverted = + io_req_bits_rs1[63] + & (io_req_bits_funct_arithmetic_funct == 4'hA + | io_req_bits_funct_arithmetic_funct == 4'hB); + wire rs2_inverted = + io_req_bits_rs2[63] & io_req_bits_funct_arithmetic_funct == 4'hA; + wire [127:0] result128 = + _nonPipelinedMultiplier_io_resp_bits_sign + ? 128'h0 - _nonPipelinedMultiplier_io_resp_bits_result + : _nonPipelinedMultiplier_io_resp_bits_result; + NonPipelinedMultiplier nonPipelinedMultiplier ( + .clock (clock), + .reset (reset), + .io_req_valid (io_req_valid), + .io_req_bits_multiplicand_bits + (rs1_inverted + ? 64'h0 - io_req_bits_rs1 + : io_req_bits_funct_op32 ? {32'h0, io_req_bits_rs1[31:0]} : io_req_bits_rs1), + .io_req_bits_multiplier_bits + (rs2_inverted + ? 64'h0 - io_req_bits_rs2 + : io_req_bits_funct_op32 ? {32'h0, io_req_bits_rs2[31:0]} : io_req_bits_rs2), + .io_req_bits_sign (rs1_inverted ^ rs2_inverted), + .io_req_bits_decode_arithmetic_funct (io_req_bits_funct_arithmetic_funct), + .io_req_bits_decode_op32 (io_req_bits_funct_op32), + .io_resp_valid (io_resp_valid), + .io_resp_bits_result (_nonPipelinedMultiplier_io_resp_bits_result), + .io_resp_bits_sign (_nonPipelinedMultiplier_io_resp_bits_sign), + .io_resp_bits_decode_arithmetic_funct + (_nonPipelinedMultiplier_io_resp_bits_decode_arithmetic_funct), + .io_resp_bits_decode_op32 + (_nonPipelinedMultiplier_io_resp_bits_decode_op32) + ); + assign io_resp_bits = + _nonPipelinedMultiplier_io_resp_bits_decode_op32 + ? {{32{result128[31]}}, result128[31:0]} + : _nonPipelinedMultiplier_io_resp_bits_decode_arithmetic_funct == 4'h9 + ? result128[63:0] + : result128[127:64]; +endmodule + +module VectorDecoder( + input [31:0] io_inst_bits, + output io_out_isConfsetInst, + output [1:0] io_out_avl_sel, + io_out_vtype_sel, + output [2:0] io_out_mop, + output [5:0] io_out_veuFun, + output [2:0] io_out_vSource, + output io_out_vm +); + + wire _csignals_T_9 = + {io_inst_bits[31], io_inst_bits[14:12], io_inst_bits[6:0]} == 11'h3D7; + wire _csignals_T_11 = + {io_inst_bits[31:30], io_inst_bits[14:12], io_inst_bits[6:0]} == 12'hFD7; + wire [16:0] _GEN = {io_inst_bits[31:25], io_inst_bits[14:12], io_inst_bits[6:0]}; + wire _csignals_T_448 = _GEN == 17'h103D7; + wire [20:0] _GEN_0 = + {io_inst_bits[31:26], io_inst_bits[24:20], io_inst_bits[14:12], io_inst_bits[6:0]}; + wire _csignals_T_15 = _GEN_0 == 21'h7; + wire _csignals_T_17 = _GEN_0 == 21'h287; + wire _csignals_T_19 = _GEN_0 == 21'h307; + wire _csignals_T_21 = _GEN_0 == 21'h387; + wire _csignals_T_23 = _GEN_0 == 21'h27; + wire _csignals_T_25 = _GEN_0 == 21'h2A7; + wire _csignals_T_27 = _GEN_0 == 21'h327; + wire _csignals_T_29 = _GEN_0 == 21'h3A7; + wire [15:0] _GEN_1 = {io_inst_bits[31:26], io_inst_bits[14:12], io_inst_bits[6:0]}; + wire _csignals_T_31 = _GEN_1 == 16'h807; + wire _csignals_T_33 = _GEN_1 == 16'hA87; + wire _csignals_T_35 = _GEN_1 == 16'hB07; + wire _csignals_T_37 = _GEN_1 == 16'hB87; + wire _csignals_T_39 = _GEN_1 == 16'h827; + wire _csignals_T_41 = _GEN_1 == 16'hAA7; + wire _csignals_T_43 = _GEN_1 == 16'hB27; + wire _csignals_T_45 = _GEN_1 == 16'hBA7; + wire _csignals_T_47 = _GEN_1 == 16'hC07; + wire _csignals_T_49 = _GEN_1 == 16'hE87; + wire _csignals_T_51 = _GEN_1 == 16'hF07; + wire _csignals_T_53 = _GEN_1 == 16'hF87; + wire _csignals_T_55 = _GEN_1 == 16'hC27; + wire _csignals_T_57 = _GEN_1 == 16'hEA7; + wire _csignals_T_59 = _GEN_1 == 16'hF27; + wire _csignals_T_61 = _GEN_1 == 16'hFA7; + wire _csignals_T_63 = _GEN_1 == 16'h57; + wire _csignals_T_65 = _GEN_1 == 16'h257; + wire _csignals_T_67 = _GEN_1 == 16'h1D7; + wire _csignals_T_69 = _GEN_1 == 16'h857; + wire _csignals_T_71 = _GEN_1 == 16'hA57; + wire _csignals_T_73 = _GEN_1 == 16'hE57; + wire _csignals_T_75 = _GEN_1 == 16'hDD7; + wire _csignals_T_77 = _GEN_1 == 16'h2457; + wire _csignals_T_79 = _GEN_1 == 16'h2657; + wire _csignals_T_81 = _GEN_1 == 16'h25D7; + wire _csignals_T_83 = _GEN_1 == 16'h2857; + wire _csignals_T_85 = _GEN_1 == 16'h2A57; + wire _csignals_T_87 = _GEN_1 == 16'h29D7; + wire _csignals_T_89 = _GEN_1 == 16'h2C57; + wire _csignals_T_91 = _GEN_1 == 16'h2E57; + wire _csignals_T_93 = _GEN_1 == 16'h2DD7; + wire _csignals_T_95 = _GEN_1 == 16'h6057; + wire _csignals_T_97 = _GEN_1 == 16'h6257; + wire _csignals_T_99 = _GEN_1 == 16'h61D7; + wire _csignals_T_101 = _GEN_1 == 16'h6457; + wire _csignals_T_103 = _GEN_1 == 16'h6657; + wire _csignals_T_105 = _GEN_1 == 16'h65D7; + wire _csignals_T_107 = _GEN_1 == 16'h6857; + wire _csignals_T_109 = _GEN_1 == 16'h6A57; + wire _csignals_T_111 = _GEN_1 == 16'h6C57; + wire _csignals_T_113 = _GEN_1 == 16'h6E57; + wire _csignals_T_115 = _GEN_1 == 16'h7057; + wire _csignals_T_117 = _GEN_1 == 16'h7257; + wire _csignals_T_119 = _GEN_1 == 16'h71D7; + wire _csignals_T_121 = _GEN_1 == 16'h7457; + wire _csignals_T_123 = _GEN_1 == 16'h7657; + wire _csignals_T_125 = _GEN_1 == 16'h75D7; + wire _csignals_T_127 = _GEN_1 == 16'h7A57; + wire _csignals_T_129 = _GEN_1 == 16'h79D7; + wire _csignals_T_131 = _GEN_1 == 16'h7E57; + wire _csignals_T_133 = _GEN_1 == 16'h7DD7; + wire _csignals_T_135 = _GEN_1 == 16'h1057; + wire _csignals_T_137 = _GEN_1 == 16'h1257; + wire _csignals_T_139 = _GEN_1 == 16'h1457; + wire _csignals_T_141 = _GEN_1 == 16'h1657; + wire _csignals_T_143 = _GEN_1 == 16'h1857; + wire _csignals_T_145 = _GEN_1 == 16'h1A57; + wire _csignals_T_147 = _GEN_1 == 16'h1C57; + wire _csignals_T_149 = _GEN_1 == 16'h1E57; + wire _csignals_T_151 = _GEN == 17'hB857; + wire _csignals_T_153 = _GEN == 17'hBA57; + wire _csignals_T_155 = _GEN == 17'hB9D7; + wire [21:0] _GEN_2 = {io_inst_bits[31:20], io_inst_bits[14:12], io_inst_bits[6:0]}; + wire _csignals_T_157 = _GEN_2 == 22'h178057; + wire _csignals_T_159 = _GEN_2 == 22'h178257; + wire _csignals_T_161 = _GEN_2 == 22'h1781D7; + wire _csignals_T_163 = _GEN == 17'hCD57; + wire _csignals_T_165 = _GEN == 17'hED57; + wire _csignals_T_167 = _GEN == 17'hC557; + wire _csignals_T_169 = _GEN == 17'hDD57; + wire _csignals_T_171 = _GEN == 17'hD557; + wire _csignals_T_173 = _GEN == 17'hF557; + wire _csignals_T_175 = _GEN == 17'hE557; + wire _csignals_T_177 = _GEN == 17'hFD57; + wire _csignals_T_179 = _GEN_1 == 16'h9557; + wire _csignals_T_181 = _GEN_1 == 16'h9757; + wire _csignals_T_183 = _GEN_1 == 16'h9D57; + wire _csignals_T_185 = _GEN_1 == 16'h9F57; + wire _csignals_T_187 = _GEN_1 == 16'h9157; + wire _csignals_T_189 = _GEN_1 == 16'h9357; + wire _csignals_T_191 = _GEN_1 == 16'h9957; + wire _csignals_T_193 = _GEN_1 == 16'h9B57; + wire _csignals_T_195 = _GEN_1 == 16'hB557; + wire _csignals_T_197 = _GEN_1 == 16'hB757; + wire _csignals_T_199 = _GEN_1 == 16'hBD57; + wire _csignals_T_201 = _GEN_1 == 16'hBF57; + wire _csignals_T_203 = _GEN_1 == 16'hA557; + wire _csignals_T_205 = _GEN_1 == 16'hA757; + wire _csignals_T_207 = _GEN_1 == 16'hAD57; + wire _csignals_T_209 = _GEN_1 == 16'hAF57; + wire _csignals_T_211 = _GEN_1 == 16'h157; + wire _csignals_T_213 = _GEN_1 == 16'h1957; + wire _csignals_T_215 = _GEN_1 == 16'h1D57; + wire _csignals_T_217 = _GEN_1 == 16'h1157; + wire _csignals_T_219 = _GEN_1 == 16'h1557; + wire _csignals_T_221 = _GEN_1 == 16'h557; + wire _csignals_T_223 = _GEN_1 == 16'h957; + wire _csignals_T_225 = _GEN_1 == 16'hD57; + wire _csignals_T_227 = + {io_inst_bits[31:25], io_inst_bits[19:12], io_inst_bits[6:0]} == 22'h108157; + wire _csignals_T_1000 = _GEN_2 == 22'h108357; + assign io_out_isConfsetInst = _csignals_T_9 | _csignals_T_11 | _csignals_T_448; + assign io_out_avl_sel = + _csignals_T_9 ? 2'h1 : _csignals_T_11 ? 2'h2 : {1'h0, _csignals_T_448}; + assign io_out_vtype_sel = + _csignals_T_9 ? 2'h1 : _csignals_T_11 ? 2'h2 : {2{_csignals_T_448}}; + assign io_out_mop = + _csignals_T_9 | _csignals_T_11 | _csignals_T_448 + ? 3'h0 + : _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21 | _csignals_T_23 + | _csignals_T_25 | _csignals_T_27 | _csignals_T_29 + ? 3'h1 + : _csignals_T_31 | _csignals_T_33 | _csignals_T_35 | _csignals_T_37 + | _csignals_T_39 | _csignals_T_41 | _csignals_T_43 | _csignals_T_45 + ? 3'h3 + : {_csignals_T_47 | _csignals_T_49 | _csignals_T_51 | _csignals_T_53 + | _csignals_T_55 | _csignals_T_57 | _csignals_T_59 | _csignals_T_61, + 2'h0}; + assign io_out_veuFun = + _csignals_T_9 | _csignals_T_11 | _csignals_T_448 | _csignals_T_15 | _csignals_T_17 + | _csignals_T_19 | _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _csignals_T_27 + | _csignals_T_29 | _csignals_T_31 | _csignals_T_33 | _csignals_T_35 | _csignals_T_37 + | _csignals_T_39 | _csignals_T_41 | _csignals_T_43 | _csignals_T_45 | _csignals_T_47 + | _csignals_T_49 | _csignals_T_51 | _csignals_T_53 | _csignals_T_55 | _csignals_T_57 + | _csignals_T_59 | _csignals_T_61 | _csignals_T_63 | _csignals_T_65 | _csignals_T_67 + ? 6'h1 + : _csignals_T_69 | _csignals_T_71 + ? 6'h2 + : _csignals_T_73 | _csignals_T_75 + ? 6'h3 + : _csignals_T_77 | _csignals_T_79 | _csignals_T_81 + ? 6'h16 + : _csignals_T_83 | _csignals_T_85 | _csignals_T_87 + ? 6'h17 + : _csignals_T_89 | _csignals_T_91 | _csignals_T_93 + ? 6'h18 + : _csignals_T_95 | _csignals_T_97 | _csignals_T_99 + ? 6'h8 + : _csignals_T_101 | _csignals_T_103 | _csignals_T_105 + ? 6'h9 + : _csignals_T_107 | _csignals_T_109 + ? 6'hA + : _csignals_T_111 | _csignals_T_113 + ? 6'hB + : _csignals_T_115 | _csignals_T_117 + | _csignals_T_119 + ? 6'hC + : _csignals_T_121 | _csignals_T_123 + | _csignals_T_125 + ? 6'hD + : _csignals_T_127 | _csignals_T_129 + ? 6'hE + : _csignals_T_131 | _csignals_T_133 + ? 6'hF + : _csignals_T_135 + | _csignals_T_137 + ? 6'h10 + : _csignals_T_139 + | _csignals_T_141 + ? 6'h11 + : _csignals_T_143 + | _csignals_T_145 + ? 6'h12 + : _csignals_T_147 + | _csignals_T_149 + ? 6'h13 + : _csignals_T_151 + | _csignals_T_153 + | _csignals_T_155 + ? 6'h14 + : _csignals_T_157 + | _csignals_T_159 + | _csignals_T_161 + ? 6'h15 + : _csignals_T_163 + ? 6'h19 + : _csignals_T_165 + ? 6'h1A + : _csignals_T_167 + ? 6'h1B + : _csignals_T_169 + ? 6'h1C + : _csignals_T_171 + ? 6'h1D + : _csignals_T_173 + ? 6'h1E + : _csignals_T_175 + ? 6'h1F + : _csignals_T_177 + ? 6'h20 + : _csignals_T_179 + | _csignals_T_181 + ? 6'h21 + : _csignals_T_183 + | _csignals_T_185 + ? 6'h22 + : _csignals_T_187 + | _csignals_T_189 + ? 6'h23 + : _csignals_T_191 + | _csignals_T_193 + ? 6'h24 + : _csignals_T_195 + | _csignals_T_197 + ? 6'h25 + : _csignals_T_199 + | _csignals_T_201 + ? 6'h26 + : _csignals_T_203 + | _csignals_T_205 + ? 6'h27 + : _csignals_T_207 + | _csignals_T_209 + ? 6'h28 + : _csignals_T_211 + ? 6'h29 + : _csignals_T_213 + ? 6'h2A + : _csignals_T_215 + ? 6'h2B + : _csignals_T_217 + ? 6'h2C + : _csignals_T_219 + ? 6'h2D + : _csignals_T_221 + ? 6'h2E + : _csignals_T_223 + ? 6'h2F + : _csignals_T_225 + ? 6'h30 + : _csignals_T_227 + ? 6'h31 + : _csignals_T_1000 + ? 6'h32 + : 6'h1; + assign io_out_vSource = + {1'h0, + _csignals_T_9 | _csignals_T_11 | _csignals_T_448 | _csignals_T_15 | _csignals_T_17 + | _csignals_T_19 | _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _csignals_T_27 + | _csignals_T_29 | _csignals_T_31 | _csignals_T_33 | _csignals_T_35 | _csignals_T_37 + | _csignals_T_39 | _csignals_T_41 | _csignals_T_43 | _csignals_T_45 | _csignals_T_47 + | _csignals_T_49 | _csignals_T_51 | _csignals_T_53 | _csignals_T_55 | _csignals_T_57 + | _csignals_T_59 | _csignals_T_61 | _csignals_T_63 + ? 2'h0 + : _csignals_T_65 + ? 2'h1 + : _csignals_T_67 + ? 2'h2 + : _csignals_T_69 + ? 2'h0 + : _csignals_T_71 | _csignals_T_73 + ? 2'h1 + : _csignals_T_75 + ? 2'h2 + : _csignals_T_77 + ? 2'h0 + : _csignals_T_79 + ? 2'h1 + : _csignals_T_81 + ? 2'h2 + : _csignals_T_83 + ? 2'h0 + : _csignals_T_85 + ? 2'h1 + : _csignals_T_87 + ? 2'h2 + : _csignals_T_89 + ? 2'h0 + : _csignals_T_91 + ? 2'h1 + : _csignals_T_93 + ? 2'h2 + : _csignals_T_95 + ? 2'h0 + : _csignals_T_97 + ? 2'h1 + : _csignals_T_99 + ? 2'h2 + : _csignals_T_101 + ? 2'h0 + : _csignals_T_103 + ? 2'h1 + : _csignals_T_105 + ? 2'h2 + : _csignals_T_107 + ? 2'h0 + : _csignals_T_109 + ? 2'h1 + : _csignals_T_111 + ? 2'h0 + : _csignals_T_113 + ? 2'h1 + : _csignals_T_115 + ? 2'h0 + : _csignals_T_117 + ? 2'h1 + : _csignals_T_119 + ? 2'h2 + : _csignals_T_121 + ? 2'h0 + : _csignals_T_123 + ? 2'h1 + : _csignals_T_125 + ? 2'h2 + : _csignals_T_127 + ? 2'h1 + : _csignals_T_129 + ? 2'h2 + : _csignals_T_131 + ? 2'h1 + : _csignals_T_133 + ? 2'h2 + : _csignals_T_135 + ? 2'h0 + : _csignals_T_137 + ? 2'h1 + : _csignals_T_139 + ? 2'h0 + : _csignals_T_141 + ? 2'h1 + : _csignals_T_143 + ? 2'h0 + : _csignals_T_145 + ? 2'h1 + : _csignals_T_147 + ? 2'h0 + : _csignals_T_149 + ? 2'h1 + : _csignals_T_151 + ? 2'h0 + : _csignals_T_153 + ? 2'h1 + : _csignals_T_155 + ? 2'h2 + : _csignals_T_157 + ? 2'h0 + : _csignals_T_159 + ? 2'h1 + : _csignals_T_161 + ? 2'h2 + : _csignals_T_163 + | _csignals_T_165 + | _csignals_T_167 + | _csignals_T_169 + | _csignals_T_171 + | _csignals_T_173 + | _csignals_T_175 + | _csignals_T_177 + ? 2'h3 + : {1'h0, + ~_csignals_T_179 + & (_csignals_T_181 + | ~_csignals_T_183 + & (_csignals_T_185 + | ~_csignals_T_187 + & (_csignals_T_189 + | ~_csignals_T_191 + & (_csignals_T_193 + | ~_csignals_T_195 + & (_csignals_T_197 + | ~_csignals_T_199 + & (_csignals_T_201 + | ~_csignals_T_203 + & (_csignals_T_205 + | ~_csignals_T_207 + & (_csignals_T_209 + | ~(_csignals_T_211 + | _csignals_T_213 + | _csignals_T_215 + | _csignals_T_217 + | _csignals_T_219 + | _csignals_T_221 + | _csignals_T_223 + | _csignals_T_225 + | _csignals_T_227) + & _csignals_T_1000))))))))}}; + assign io_out_vm = io_inst_bits[25]; +endmodule + +module VecCtrlUnit( + input io_req_valid, + input [1:0] io_req_bits_vDecode_avl_sel, + io_req_bits_vDecode_vtype_sel, + input [63:0] io_req_bits_rs1_value, + io_req_bits_rs2_value, + io_req_bits_zimm, + io_req_bits_uimm, + output io_resp_valid, + io_resp_bits_vtype_vill, + io_resp_bits_vtype_vma, + io_resp_bits_vtype_vta, + output [2:0] io_resp_bits_vtype_vsew, + io_resp_bits_vtype_vlmul, + output [5:0] io_resp_bits_vl +); + + wire [63:0] avl = + io_req_bits_vDecode_avl_sel == 2'h1 ? io_req_bits_rs1_value : io_req_bits_uimm; + wire [63:0] _T_12 = + (&io_req_bits_vDecode_vtype_sel) + ? io_req_bits_rs2_value + : {52'h0, + io_req_bits_vDecode_vtype_sel == 2'h2 + ? {2'h0, io_req_bits_zimm[9:0]} + : io_req_bits_vDecode_vtype_sel == 2'h1 + ? {1'h0, io_req_bits_zimm[10:0]} + : 12'h0}; + wire [5:0] maxVl = + _T_12[5:3] == 3'h3 + ? 6'h4 + : _T_12[5:3] == 3'h2 + ? 6'h8 + : _T_12[5:3] == 3'h1 ? 6'h10 : {_T_12[5:3] == 3'h0, 5'h0}; + assign io_resp_valid = io_req_valid; + assign io_resp_bits_vtype_vill = + _T_12[63] | (|(_T_12[62:8])) | _T_12[5] | (|(_T_12[2:0])); + assign io_resp_bits_vtype_vma = _T_12[7]; + assign io_resp_bits_vtype_vta = _T_12[6]; + assign io_resp_bits_vtype_vsew = _T_12[5:3]; + assign io_resp_bits_vtype_vlmul = _T_12[2:0]; + assign io_resp_bits_vl = avl >= {58'h0, maxVl} ? maxVl : avl[5:0]; +endmodule + +module VecRegFile( + input clock, + input [2:0] io_readReq_0_req_sew, + input [4:0] io_readReq_0_req_idx, + io_readReq_0_req_vs2, + io_readReq_0_req_vd, + input [2:0] io_readReq_1_req_sew, + input io_readReq_1_req_readVdAsMaskSource, + input [4:0] io_readReq_1_req_idx, + io_readReq_1_req_vs1, + io_readReq_1_req_vs2, + io_readReq_1_req_vd, + input [2:0] io_readReq_2_req_sew, + input io_readReq_2_req_readVdAsMaskSource, + input [4:0] io_readReq_2_req_idx, + io_readReq_2_req_vs1, + io_readReq_2_req_vs2, + io_readReq_2_req_vd, + input io_writeReq_0_valid, + input [4:0] io_writeReq_0_bits_vd, + input [2:0] io_writeReq_0_bits_vtype_vsew, + input [4:0] io_writeReq_0_bits_index, + input [63:0] io_writeReq_0_bits_data, + input io_writeReq_0_bits_writeReq, + io_writeReq_1_valid, + input [4:0] io_writeReq_1_bits_vd, + input [2:0] io_writeReq_1_bits_vtype_vsew, + input [4:0] io_writeReq_1_bits_index, + input [63:0] io_writeReq_1_bits_data, + input io_writeReq_1_bits_writeReq, + io_writeReq_2_valid, + input [4:0] io_writeReq_2_bits_vd, + input [2:0] io_writeReq_2_bits_vtype_vsew, + input [4:0] io_writeReq_2_bits_index, + input [63:0] io_writeReq_2_bits_data, + input io_writeReq_2_bits_writeReq, + output [63:0] io_readReq_0_resp_vs2Out, + io_readReq_0_resp_vdOut, + output io_readReq_0_resp_vm, + output [63:0] io_readReq_1_resp_vs1Out, + io_readReq_1_resp_vs2Out, + io_readReq_1_resp_vdOut, + output io_readReq_1_resp_vm, + output [63:0] io_readReq_2_resp_vs1Out, + io_readReq_2_resp_vs2Out, + io_readReq_2_resp_vdOut, + output io_readReq_2_resp_vm +); + + wire internalWriteMask_2_31; + wire internalWriteMask_2_30; + wire internalWriteMask_2_29; + wire internalWriteMask_2_28; + wire internalWriteMask_2_27; + wire internalWriteMask_2_26; + wire internalWriteMask_2_25; + wire internalWriteMask_2_24; + wire internalWriteMask_2_23; + wire internalWriteMask_2_22; + wire internalWriteMask_2_21; + wire internalWriteMask_2_20; + wire internalWriteMask_2_19; + wire internalWriteMask_2_18; + wire internalWriteMask_2_17; + wire internalWriteMask_2_16; + wire internalWriteMask_2_15; + wire internalWriteMask_2_14; + wire internalWriteMask_2_13; + wire internalWriteMask_2_12; + wire internalWriteMask_2_11; + wire internalWriteMask_2_10; + wire internalWriteMask_2_9; + wire internalWriteMask_2_8; + wire internalWriteMask_2_7; + wire internalWriteMask_2_6; + wire internalWriteMask_2_5; + wire internalWriteMask_2_4; + wire internalWriteMask_2_3; + wire internalWriteMask_2_2; + wire internalWriteMask_2_1; + wire internalWriteMask_2_0; + wire [7:0] internalWriteData_2_31; + wire [7:0] internalWriteData_2_30; + wire [7:0] internalWriteData_2_29; + wire [7:0] internalWriteData_2_28; + wire [7:0] internalWriteData_2_27; + wire [7:0] internalWriteData_2_26; + wire [7:0] internalWriteData_2_25; + wire [7:0] internalWriteData_2_24; + wire [7:0] internalWriteData_2_23; + wire [7:0] internalWriteData_2_22; + wire [7:0] internalWriteData_2_21; + wire [7:0] internalWriteData_2_20; + wire [7:0] internalWriteData_2_19; + wire [7:0] internalWriteData_2_18; + wire [7:0] internalWriteData_2_17; + wire [7:0] internalWriteData_2_16; + wire [7:0] internalWriteData_2_15; + wire [7:0] internalWriteData_2_14; + wire [7:0] internalWriteData_2_13; + wire [7:0] internalWriteData_2_12; + wire [7:0] internalWriteData_2_11; + wire [7:0] internalWriteData_2_10; + wire [7:0] internalWriteData_2_9; + wire [7:0] internalWriteData_2_8; + wire [7:0] internalWriteData_2_7; + wire [7:0] internalWriteData_2_6; + wire [7:0] internalWriteData_2_5; + wire [7:0] internalWriteData_2_4; + wire [7:0] internalWriteData_2_3; + wire [7:0] internalWriteData_2_2; + wire [7:0] internalWriteData_2_1; + wire [7:0] internalWriteData_2_0; + wire internalWriteMask_1_31; + wire internalWriteMask_1_30; + wire internalWriteMask_1_29; + wire internalWriteMask_1_28; + wire internalWriteMask_1_27; + wire internalWriteMask_1_26; + wire internalWriteMask_1_25; + wire internalWriteMask_1_24; + wire internalWriteMask_1_23; + wire internalWriteMask_1_22; + wire internalWriteMask_1_21; + wire internalWriteMask_1_20; + wire internalWriteMask_1_19; + wire internalWriteMask_1_18; + wire internalWriteMask_1_17; + wire internalWriteMask_1_16; + wire internalWriteMask_1_15; + wire internalWriteMask_1_14; + wire internalWriteMask_1_13; + wire internalWriteMask_1_12; + wire internalWriteMask_1_11; + wire internalWriteMask_1_10; + wire internalWriteMask_1_9; + wire internalWriteMask_1_8; + wire internalWriteMask_1_7; + wire internalWriteMask_1_6; + wire internalWriteMask_1_5; + wire internalWriteMask_1_4; + wire internalWriteMask_1_3; + wire internalWriteMask_1_2; + wire internalWriteMask_1_1; + wire internalWriteMask_1_0; + wire [7:0] internalWriteData_1_31; + wire [7:0] internalWriteData_1_30; + wire [7:0] internalWriteData_1_29; + wire [7:0] internalWriteData_1_28; + wire [7:0] internalWriteData_1_27; + wire [7:0] internalWriteData_1_26; + wire [7:0] internalWriteData_1_25; + wire [7:0] internalWriteData_1_24; + wire [7:0] internalWriteData_1_23; + wire [7:0] internalWriteData_1_22; + wire [7:0] internalWriteData_1_21; + wire [7:0] internalWriteData_1_20; + wire [7:0] internalWriteData_1_19; + wire [7:0] internalWriteData_1_18; + wire [7:0] internalWriteData_1_17; + wire [7:0] internalWriteData_1_16; + wire [7:0] internalWriteData_1_15; + wire [7:0] internalWriteData_1_14; + wire [7:0] internalWriteData_1_13; + wire [7:0] internalWriteData_1_12; + wire [7:0] internalWriteData_1_11; + wire [7:0] internalWriteData_1_10; + wire [7:0] internalWriteData_1_9; + wire [7:0] internalWriteData_1_8; + wire [7:0] internalWriteData_1_7; + wire [7:0] internalWriteData_1_6; + wire [7:0] internalWriteData_1_5; + wire [7:0] internalWriteData_1_4; + wire [7:0] internalWriteData_1_3; + wire [7:0] internalWriteData_1_2; + wire [7:0] internalWriteData_1_1; + wire [7:0] internalWriteData_1_0; + wire internalWriteMask_31; + wire internalWriteMask_30; + wire internalWriteMask_29; + wire internalWriteMask_28; + wire internalWriteMask_27; + wire internalWriteMask_26; + wire internalWriteMask_25; + wire internalWriteMask_24; + wire internalWriteMask_23; + wire internalWriteMask_22; + wire internalWriteMask_21; + wire internalWriteMask_20; + wire internalWriteMask_19; + wire internalWriteMask_18; + wire internalWriteMask_17; + wire internalWriteMask_16; + wire internalWriteMask_15; + wire internalWriteMask_14; + wire internalWriteMask_13; + wire internalWriteMask_12; + wire internalWriteMask_11; + wire internalWriteMask_10; + wire internalWriteMask_9; + wire internalWriteMask_8; + wire internalWriteMask_7; + wire internalWriteMask_6; + wire internalWriteMask_5; + wire internalWriteMask_4; + wire internalWriteMask_3; + wire internalWriteMask_2; + wire internalWriteMask_1; + wire internalWriteMask_0; + wire [7:0] internalWriteData_31; + wire [7:0] internalWriteData_30; + wire [7:0] internalWriteData_29; + wire [7:0] internalWriteData_28; + wire [7:0] internalWriteData_27; + wire [7:0] internalWriteData_26; + wire [7:0] internalWriteData_25; + wire [7:0] internalWriteData_24; + wire [7:0] internalWriteData_23; + wire [7:0] internalWriteData_22; + wire [7:0] internalWriteData_21; + wire [7:0] internalWriteData_20; + wire [7:0] internalWriteData_19; + wire [7:0] internalWriteData_18; + wire [7:0] internalWriteData_17; + wire [7:0] internalWriteData_16; + wire [7:0] internalWriteData_15; + wire [7:0] internalWriteData_14; + wire [7:0] internalWriteData_13; + wire [7:0] internalWriteData_12; + wire [7:0] internalWriteData_11; + wire [7:0] internalWriteData_10; + wire [7:0] internalWriteData_9; + wire [7:0] internalWriteData_8; + wire [7:0] internalWriteData_7; + wire [7:0] internalWriteData_6; + wire [7:0] internalWriteData_5; + wire [7:0] internalWriteData_4; + wire [7:0] internalWriteData_3; + wire [7:0] internalWriteData_2; + wire [7:0] internalWriteData_1; + wire [7:0] internalWriteData_0; + wire [255:0] _vrf_ext_R0_data; + wire [255:0] _vrf_ext_R1_data; + wire [255:0] _vrf_ext_R3_data; + wire [255:0] _vrf_ext_R4_data; + wire [255:0] _vrf_ext_R5_data; + wire [255:0] _vrf_ext_R6_data; + wire [255:0] _vrf_ext_R7_data; + wire [255:0] _vrf_ext_R8_data; + wire [255:0] _vrf_ext_R9_data; + wire [255:0] _vrf_ext_R10_data; + wire [255:0] _vrf_ext_R11_data; + wire _io_readReq_0_resp_res_vdOut_nonVmRes_T_74 = + io_readReq_0_req_sew == 3'h0; + wire _io_readReq_0_resp_res_vdOut_nonVmRes_T_76 = + io_readReq_0_req_sew == 3'h1; + wire _io_readReq_0_resp_res_vdOut_nonVmRes_T_78 = + io_readReq_0_req_sew == 3'h2; + wire _io_readReq_0_resp_res_vdOut_nonVmRes_T_80 = + io_readReq_0_req_sew == 3'h3; + wire [31:0][7:0] _GEN = + {{_vrf_ext_R3_data[255:248]}, + {_vrf_ext_R3_data[247:240]}, + {_vrf_ext_R3_data[239:232]}, + {_vrf_ext_R3_data[231:224]}, + {_vrf_ext_R3_data[223:216]}, + {_vrf_ext_R3_data[215:208]}, + {_vrf_ext_R3_data[207:200]}, + {_vrf_ext_R3_data[199:192]}, + {_vrf_ext_R3_data[191:184]}, + {_vrf_ext_R3_data[183:176]}, + {_vrf_ext_R3_data[175:168]}, + {_vrf_ext_R3_data[167:160]}, + {_vrf_ext_R3_data[159:152]}, + {_vrf_ext_R3_data[151:144]}, + {_vrf_ext_R3_data[143:136]}, + {_vrf_ext_R3_data[135:128]}, + {_vrf_ext_R3_data[127:120]}, + {_vrf_ext_R3_data[119:112]}, + {_vrf_ext_R3_data[111:104]}, + {_vrf_ext_R3_data[103:96]}, + {_vrf_ext_R3_data[95:88]}, + {_vrf_ext_R3_data[87:80]}, + {_vrf_ext_R3_data[79:72]}, + {_vrf_ext_R3_data[71:64]}, + {_vrf_ext_R3_data[63:56]}, + {_vrf_ext_R3_data[55:48]}, + {_vrf_ext_R3_data[47:40]}, + {_vrf_ext_R3_data[39:32]}, + {_vrf_ext_R3_data[31:24]}, + {_vrf_ext_R3_data[23:16]}, + {_vrf_ext_R3_data[15:8]}, + {_vrf_ext_R3_data[7:0]}}; + wire [4:0] _GEN_0 = {io_readReq_0_req_idx[3:0], 1'h0}; + wire [7:0] _GEN_1 = _GEN[_GEN_0 + 5'h1]; + wire [4:0] _GEN_2 = {io_readReq_0_req_idx[2:0], 2'h0}; + wire [7:0] _GEN_3 = _GEN[_GEN_2 + 5'h3]; + wire [4:0] _GEN_4 = {io_readReq_0_req_idx[1:0], 3'h0}; + wire [31:0][7:0] _GEN_5 = + {{_vrf_ext_R1_data[255:248]}, + {_vrf_ext_R1_data[247:240]}, + {_vrf_ext_R1_data[239:232]}, + {_vrf_ext_R1_data[231:224]}, + {_vrf_ext_R1_data[223:216]}, + {_vrf_ext_R1_data[215:208]}, + {_vrf_ext_R1_data[207:200]}, + {_vrf_ext_R1_data[199:192]}, + {_vrf_ext_R1_data[191:184]}, + {_vrf_ext_R1_data[183:176]}, + {_vrf_ext_R1_data[175:168]}, + {_vrf_ext_R1_data[167:160]}, + {_vrf_ext_R1_data[159:152]}, + {_vrf_ext_R1_data[151:144]}, + {_vrf_ext_R1_data[143:136]}, + {_vrf_ext_R1_data[135:128]}, + {_vrf_ext_R1_data[127:120]}, + {_vrf_ext_R1_data[119:112]}, + {_vrf_ext_R1_data[111:104]}, + {_vrf_ext_R1_data[103:96]}, + {_vrf_ext_R1_data[95:88]}, + {_vrf_ext_R1_data[87:80]}, + {_vrf_ext_R1_data[79:72]}, + {_vrf_ext_R1_data[71:64]}, + {_vrf_ext_R1_data[63:56]}, + {_vrf_ext_R1_data[55:48]}, + {_vrf_ext_R1_data[47:40]}, + {_vrf_ext_R1_data[39:32]}, + {_vrf_ext_R1_data[31:24]}, + {_vrf_ext_R1_data[23:16]}, + {_vrf_ext_R1_data[15:8]}, + {_vrf_ext_R1_data[7:0]}}; + wire [7:0] _GEN_6 = _GEN_5[_GEN_0 + 5'h1]; + wire [7:0] _GEN_7 = _GEN_5[_GEN_2 + 5'h3]; + wire [31:0][7:0] _GEN_8 = + {{_vrf_ext_R0_data[255:248]}, + {_vrf_ext_R0_data[247:240]}, + {_vrf_ext_R0_data[239:232]}, + {_vrf_ext_R0_data[231:224]}, + {_vrf_ext_R0_data[223:216]}, + {_vrf_ext_R0_data[215:208]}, + {_vrf_ext_R0_data[207:200]}, + {_vrf_ext_R0_data[199:192]}, + {_vrf_ext_R0_data[191:184]}, + {_vrf_ext_R0_data[183:176]}, + {_vrf_ext_R0_data[175:168]}, + {_vrf_ext_R0_data[167:160]}, + {_vrf_ext_R0_data[159:152]}, + {_vrf_ext_R0_data[151:144]}, + {_vrf_ext_R0_data[143:136]}, + {_vrf_ext_R0_data[135:128]}, + {_vrf_ext_R0_data[127:120]}, + {_vrf_ext_R0_data[119:112]}, + {_vrf_ext_R0_data[111:104]}, + {_vrf_ext_R0_data[103:96]}, + {_vrf_ext_R0_data[95:88]}, + {_vrf_ext_R0_data[87:80]}, + {_vrf_ext_R0_data[79:72]}, + {_vrf_ext_R0_data[71:64]}, + {_vrf_ext_R0_data[63:56]}, + {_vrf_ext_R0_data[55:48]}, + {_vrf_ext_R0_data[47:40]}, + {_vrf_ext_R0_data[39:32]}, + {_vrf_ext_R0_data[31:24]}, + {_vrf_ext_R0_data[23:16]}, + {_vrf_ext_R0_data[15:8]}, + {_vrf_ext_R0_data[7:0]}}; + wire [7:0] _io_readReq_0_resp_res_vm_T_2 = + _GEN_8[{3'h0, io_readReq_0_req_idx[4:3]}] >> io_readReq_0_req_idx[2:0]; + wire [31:0][7:0] _GEN_9 = + {{_vrf_ext_R6_data[255:248]}, + {_vrf_ext_R6_data[247:240]}, + {_vrf_ext_R6_data[239:232]}, + {_vrf_ext_R6_data[231:224]}, + {_vrf_ext_R6_data[223:216]}, + {_vrf_ext_R6_data[215:208]}, + {_vrf_ext_R6_data[207:200]}, + {_vrf_ext_R6_data[199:192]}, + {_vrf_ext_R6_data[191:184]}, + {_vrf_ext_R6_data[183:176]}, + {_vrf_ext_R6_data[175:168]}, + {_vrf_ext_R6_data[167:160]}, + {_vrf_ext_R6_data[159:152]}, + {_vrf_ext_R6_data[151:144]}, + {_vrf_ext_R6_data[143:136]}, + {_vrf_ext_R6_data[135:128]}, + {_vrf_ext_R6_data[127:120]}, + {_vrf_ext_R6_data[119:112]}, + {_vrf_ext_R6_data[111:104]}, + {_vrf_ext_R6_data[103:96]}, + {_vrf_ext_R6_data[95:88]}, + {_vrf_ext_R6_data[87:80]}, + {_vrf_ext_R6_data[79:72]}, + {_vrf_ext_R6_data[71:64]}, + {_vrf_ext_R6_data[63:56]}, + {_vrf_ext_R6_data[55:48]}, + {_vrf_ext_R6_data[47:40]}, + {_vrf_ext_R6_data[39:32]}, + {_vrf_ext_R6_data[31:24]}, + {_vrf_ext_R6_data[23:16]}, + {_vrf_ext_R6_data[15:8]}, + {_vrf_ext_R6_data[7:0]}}; + wire [4:0] _GEN_10 = {io_readReq_1_req_idx[3:0], 1'h0}; + wire [7:0] _GEN_11 = _GEN_9[_GEN_10 + 5'h1]; + wire [4:0] _GEN_12 = {io_readReq_1_req_idx[2:0], 2'h0}; + wire [7:0] _GEN_13 = _GEN_9[_GEN_12 + 5'h3]; + wire [4:0] _GEN_14 = {io_readReq_1_req_idx[1:0], 3'h0}; + wire _io_readReq_1_resp_res_vdOut_nonVmRes_T_74 = + io_readReq_1_req_sew == 3'h0; + wire _io_readReq_1_resp_res_vdOut_nonVmRes_T_76 = + io_readReq_1_req_sew == 3'h1; + wire _io_readReq_1_resp_res_vdOut_nonVmRes_T_78 = + io_readReq_1_req_sew == 3'h2; + wire _io_readReq_1_resp_res_vdOut_nonVmRes_T_80 = + io_readReq_1_req_sew == 3'h3; + wire [31:0][7:0] _GEN_15 = + {{_vrf_ext_R7_data[255:248]}, + {_vrf_ext_R7_data[247:240]}, + {_vrf_ext_R7_data[239:232]}, + {_vrf_ext_R7_data[231:224]}, + {_vrf_ext_R7_data[223:216]}, + {_vrf_ext_R7_data[215:208]}, + {_vrf_ext_R7_data[207:200]}, + {_vrf_ext_R7_data[199:192]}, + {_vrf_ext_R7_data[191:184]}, + {_vrf_ext_R7_data[183:176]}, + {_vrf_ext_R7_data[175:168]}, + {_vrf_ext_R7_data[167:160]}, + {_vrf_ext_R7_data[159:152]}, + {_vrf_ext_R7_data[151:144]}, + {_vrf_ext_R7_data[143:136]}, + {_vrf_ext_R7_data[135:128]}, + {_vrf_ext_R7_data[127:120]}, + {_vrf_ext_R7_data[119:112]}, + {_vrf_ext_R7_data[111:104]}, + {_vrf_ext_R7_data[103:96]}, + {_vrf_ext_R7_data[95:88]}, + {_vrf_ext_R7_data[87:80]}, + {_vrf_ext_R7_data[79:72]}, + {_vrf_ext_R7_data[71:64]}, + {_vrf_ext_R7_data[63:56]}, + {_vrf_ext_R7_data[55:48]}, + {_vrf_ext_R7_data[47:40]}, + {_vrf_ext_R7_data[39:32]}, + {_vrf_ext_R7_data[31:24]}, + {_vrf_ext_R7_data[23:16]}, + {_vrf_ext_R7_data[15:8]}, + {_vrf_ext_R7_data[7:0]}}; + wire [7:0] _GEN_16 = _GEN_15[_GEN_10 + 5'h1]; + wire [7:0] _GEN_17 = _GEN_15[_GEN_12 + 5'h3]; + wire [31:0][7:0] _GEN_18 = + {{_vrf_ext_R5_data[255:248]}, + {_vrf_ext_R5_data[247:240]}, + {_vrf_ext_R5_data[239:232]}, + {_vrf_ext_R5_data[231:224]}, + {_vrf_ext_R5_data[223:216]}, + {_vrf_ext_R5_data[215:208]}, + {_vrf_ext_R5_data[207:200]}, + {_vrf_ext_R5_data[199:192]}, + {_vrf_ext_R5_data[191:184]}, + {_vrf_ext_R5_data[183:176]}, + {_vrf_ext_R5_data[175:168]}, + {_vrf_ext_R5_data[167:160]}, + {_vrf_ext_R5_data[159:152]}, + {_vrf_ext_R5_data[151:144]}, + {_vrf_ext_R5_data[143:136]}, + {_vrf_ext_R5_data[135:128]}, + {_vrf_ext_R5_data[127:120]}, + {_vrf_ext_R5_data[119:112]}, + {_vrf_ext_R5_data[111:104]}, + {_vrf_ext_R5_data[103:96]}, + {_vrf_ext_R5_data[95:88]}, + {_vrf_ext_R5_data[87:80]}, + {_vrf_ext_R5_data[79:72]}, + {_vrf_ext_R5_data[71:64]}, + {_vrf_ext_R5_data[63:56]}, + {_vrf_ext_R5_data[55:48]}, + {_vrf_ext_R5_data[47:40]}, + {_vrf_ext_R5_data[39:32]}, + {_vrf_ext_R5_data[31:24]}, + {_vrf_ext_R5_data[23:16]}, + {_vrf_ext_R5_data[15:8]}, + {_vrf_ext_R5_data[7:0]}}; + wire [7:0] _GEN_19 = _GEN_18[_GEN_10 + 5'h1]; + wire [7:0] _GEN_20 = _GEN_18[_GEN_12 + 5'h3]; + wire [4:0] _GEN_21 = {3'h0, io_readReq_1_req_idx[4:3]}; + wire [31:0][7:0] _GEN_22 = + {{_vrf_ext_R4_data[255:248]}, + {_vrf_ext_R4_data[247:240]}, + {_vrf_ext_R4_data[239:232]}, + {_vrf_ext_R4_data[231:224]}, + {_vrf_ext_R4_data[223:216]}, + {_vrf_ext_R4_data[215:208]}, + {_vrf_ext_R4_data[207:200]}, + {_vrf_ext_R4_data[199:192]}, + {_vrf_ext_R4_data[191:184]}, + {_vrf_ext_R4_data[183:176]}, + {_vrf_ext_R4_data[175:168]}, + {_vrf_ext_R4_data[167:160]}, + {_vrf_ext_R4_data[159:152]}, + {_vrf_ext_R4_data[151:144]}, + {_vrf_ext_R4_data[143:136]}, + {_vrf_ext_R4_data[135:128]}, + {_vrf_ext_R4_data[127:120]}, + {_vrf_ext_R4_data[119:112]}, + {_vrf_ext_R4_data[111:104]}, + {_vrf_ext_R4_data[103:96]}, + {_vrf_ext_R4_data[95:88]}, + {_vrf_ext_R4_data[87:80]}, + {_vrf_ext_R4_data[79:72]}, + {_vrf_ext_R4_data[71:64]}, + {_vrf_ext_R4_data[63:56]}, + {_vrf_ext_R4_data[55:48]}, + {_vrf_ext_R4_data[47:40]}, + {_vrf_ext_R4_data[39:32]}, + {_vrf_ext_R4_data[31:24]}, + {_vrf_ext_R4_data[23:16]}, + {_vrf_ext_R4_data[15:8]}, + {_vrf_ext_R4_data[7:0]}}; + wire [7:0] _io_readReq_1_resp_res_vm_T_2 = + _GEN_22[_GEN_21] >> io_readReq_1_req_idx[2:0]; + wire [31:0][7:0] _GEN_23 = + {{_vrf_ext_R10_data[255:248]}, + {_vrf_ext_R10_data[247:240]}, + {_vrf_ext_R10_data[239:232]}, + {_vrf_ext_R10_data[231:224]}, + {_vrf_ext_R10_data[223:216]}, + {_vrf_ext_R10_data[215:208]}, + {_vrf_ext_R10_data[207:200]}, + {_vrf_ext_R10_data[199:192]}, + {_vrf_ext_R10_data[191:184]}, + {_vrf_ext_R10_data[183:176]}, + {_vrf_ext_R10_data[175:168]}, + {_vrf_ext_R10_data[167:160]}, + {_vrf_ext_R10_data[159:152]}, + {_vrf_ext_R10_data[151:144]}, + {_vrf_ext_R10_data[143:136]}, + {_vrf_ext_R10_data[135:128]}, + {_vrf_ext_R10_data[127:120]}, + {_vrf_ext_R10_data[119:112]}, + {_vrf_ext_R10_data[111:104]}, + {_vrf_ext_R10_data[103:96]}, + {_vrf_ext_R10_data[95:88]}, + {_vrf_ext_R10_data[87:80]}, + {_vrf_ext_R10_data[79:72]}, + {_vrf_ext_R10_data[71:64]}, + {_vrf_ext_R10_data[63:56]}, + {_vrf_ext_R10_data[55:48]}, + {_vrf_ext_R10_data[47:40]}, + {_vrf_ext_R10_data[39:32]}, + {_vrf_ext_R10_data[31:24]}, + {_vrf_ext_R10_data[23:16]}, + {_vrf_ext_R10_data[15:8]}, + {_vrf_ext_R10_data[7:0]}}; + wire [4:0] _GEN_24 = {io_readReq_2_req_idx[3:0], 1'h0}; + wire [7:0] _GEN_25 = _GEN_23[_GEN_24 + 5'h1]; + wire [4:0] _GEN_26 = {io_readReq_2_req_idx[2:0], 2'h0}; + wire [7:0] _GEN_27 = _GEN_23[_GEN_26 + 5'h3]; + wire [4:0] _GEN_28 = {io_readReq_2_req_idx[1:0], 3'h0}; + wire _io_readReq_2_resp_res_vdOut_nonVmRes_T_74 = + io_readReq_2_req_sew == 3'h0; + wire _io_readReq_2_resp_res_vdOut_nonVmRes_T_76 = + io_readReq_2_req_sew == 3'h1; + wire _io_readReq_2_resp_res_vdOut_nonVmRes_T_78 = + io_readReq_2_req_sew == 3'h2; + wire _io_readReq_2_resp_res_vdOut_nonVmRes_T_80 = + io_readReq_2_req_sew == 3'h3; + wire [31:0][7:0] _GEN_29 = + {{_vrf_ext_R11_data[255:248]}, + {_vrf_ext_R11_data[247:240]}, + {_vrf_ext_R11_data[239:232]}, + {_vrf_ext_R11_data[231:224]}, + {_vrf_ext_R11_data[223:216]}, + {_vrf_ext_R11_data[215:208]}, + {_vrf_ext_R11_data[207:200]}, + {_vrf_ext_R11_data[199:192]}, + {_vrf_ext_R11_data[191:184]}, + {_vrf_ext_R11_data[183:176]}, + {_vrf_ext_R11_data[175:168]}, + {_vrf_ext_R11_data[167:160]}, + {_vrf_ext_R11_data[159:152]}, + {_vrf_ext_R11_data[151:144]}, + {_vrf_ext_R11_data[143:136]}, + {_vrf_ext_R11_data[135:128]}, + {_vrf_ext_R11_data[127:120]}, + {_vrf_ext_R11_data[119:112]}, + {_vrf_ext_R11_data[111:104]}, + {_vrf_ext_R11_data[103:96]}, + {_vrf_ext_R11_data[95:88]}, + {_vrf_ext_R11_data[87:80]}, + {_vrf_ext_R11_data[79:72]}, + {_vrf_ext_R11_data[71:64]}, + {_vrf_ext_R11_data[63:56]}, + {_vrf_ext_R11_data[55:48]}, + {_vrf_ext_R11_data[47:40]}, + {_vrf_ext_R11_data[39:32]}, + {_vrf_ext_R11_data[31:24]}, + {_vrf_ext_R11_data[23:16]}, + {_vrf_ext_R11_data[15:8]}, + {_vrf_ext_R11_data[7:0]}}; + wire [7:0] _GEN_30 = _GEN_29[_GEN_24 + 5'h1]; + wire [7:0] _GEN_31 = _GEN_29[_GEN_26 + 5'h3]; + wire [31:0][7:0] _GEN_32 = + {{_vrf_ext_R9_data[255:248]}, + {_vrf_ext_R9_data[247:240]}, + {_vrf_ext_R9_data[239:232]}, + {_vrf_ext_R9_data[231:224]}, + {_vrf_ext_R9_data[223:216]}, + {_vrf_ext_R9_data[215:208]}, + {_vrf_ext_R9_data[207:200]}, + {_vrf_ext_R9_data[199:192]}, + {_vrf_ext_R9_data[191:184]}, + {_vrf_ext_R9_data[183:176]}, + {_vrf_ext_R9_data[175:168]}, + {_vrf_ext_R9_data[167:160]}, + {_vrf_ext_R9_data[159:152]}, + {_vrf_ext_R9_data[151:144]}, + {_vrf_ext_R9_data[143:136]}, + {_vrf_ext_R9_data[135:128]}, + {_vrf_ext_R9_data[127:120]}, + {_vrf_ext_R9_data[119:112]}, + {_vrf_ext_R9_data[111:104]}, + {_vrf_ext_R9_data[103:96]}, + {_vrf_ext_R9_data[95:88]}, + {_vrf_ext_R9_data[87:80]}, + {_vrf_ext_R9_data[79:72]}, + {_vrf_ext_R9_data[71:64]}, + {_vrf_ext_R9_data[63:56]}, + {_vrf_ext_R9_data[55:48]}, + {_vrf_ext_R9_data[47:40]}, + {_vrf_ext_R9_data[39:32]}, + {_vrf_ext_R9_data[31:24]}, + {_vrf_ext_R9_data[23:16]}, + {_vrf_ext_R9_data[15:8]}, + {_vrf_ext_R9_data[7:0]}}; + wire [7:0] _GEN_33 = _GEN_32[_GEN_24 + 5'h1]; + wire [7:0] _GEN_34 = _GEN_32[_GEN_26 + 5'h3]; + wire [4:0] _GEN_35 = {3'h0, io_readReq_2_req_idx[4:3]}; + wire [31:0][7:0] _GEN_36 = + {{_vrf_ext_R8_data[255:248]}, + {_vrf_ext_R8_data[247:240]}, + {_vrf_ext_R8_data[239:232]}, + {_vrf_ext_R8_data[231:224]}, + {_vrf_ext_R8_data[223:216]}, + {_vrf_ext_R8_data[215:208]}, + {_vrf_ext_R8_data[207:200]}, + {_vrf_ext_R8_data[199:192]}, + {_vrf_ext_R8_data[191:184]}, + {_vrf_ext_R8_data[183:176]}, + {_vrf_ext_R8_data[175:168]}, + {_vrf_ext_R8_data[167:160]}, + {_vrf_ext_R8_data[159:152]}, + {_vrf_ext_R8_data[151:144]}, + {_vrf_ext_R8_data[143:136]}, + {_vrf_ext_R8_data[135:128]}, + {_vrf_ext_R8_data[127:120]}, + {_vrf_ext_R8_data[119:112]}, + {_vrf_ext_R8_data[111:104]}, + {_vrf_ext_R8_data[103:96]}, + {_vrf_ext_R8_data[95:88]}, + {_vrf_ext_R8_data[87:80]}, + {_vrf_ext_R8_data[79:72]}, + {_vrf_ext_R8_data[71:64]}, + {_vrf_ext_R8_data[63:56]}, + {_vrf_ext_R8_data[55:48]}, + {_vrf_ext_R8_data[47:40]}, + {_vrf_ext_R8_data[39:32]}, + {_vrf_ext_R8_data[31:24]}, + {_vrf_ext_R8_data[23:16]}, + {_vrf_ext_R8_data[15:8]}, + {_vrf_ext_R8_data[7:0]}}; + wire [7:0] _io_readReq_2_resp_res_vm_T_2 = + _GEN_36[_GEN_35] >> io_readReq_2_req_idx[2:0]; + wire _T_1 = io_writeReq_0_bits_vtype_vsew == 3'h0; + wire _GEN_37 = io_writeReq_0_bits_index == 5'h0; + wire [7:0] _GEN_38 = _T_1 & _GEN_37 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire _GEN_39 = io_writeReq_0_bits_index == 5'h1; + wire _GEN_40 = io_writeReq_0_bits_index == 5'h2; + wire [7:0] _GEN_41 = _T_1 & _GEN_40 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire _GEN_42 = io_writeReq_0_bits_index == 5'h3; + wire _GEN_43 = io_writeReq_0_bits_index == 5'h4; + wire [7:0] _GEN_44 = _T_1 & _GEN_43 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire _GEN_45 = io_writeReq_0_bits_index == 5'h5; + wire _GEN_46 = io_writeReq_0_bits_index == 5'h6; + wire [7:0] _GEN_47 = _T_1 & _GEN_46 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire _GEN_48 = io_writeReq_0_bits_index == 5'h7; + wire _GEN_49 = io_writeReq_0_bits_index == 5'h8; + wire [7:0] _GEN_50 = _T_1 & _GEN_49 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire _GEN_51 = io_writeReq_0_bits_index == 5'h9; + wire _GEN_52 = io_writeReq_0_bits_index == 5'hA; + wire [7:0] _GEN_53 = _T_1 & _GEN_52 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire _GEN_54 = io_writeReq_0_bits_index == 5'hB; + wire _GEN_55 = io_writeReq_0_bits_index == 5'hC; + wire [7:0] _GEN_56 = _T_1 & _GEN_55 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire _GEN_57 = io_writeReq_0_bits_index == 5'hD; + wire _GEN_58 = io_writeReq_0_bits_index == 5'hE; + wire [7:0] _GEN_59 = _T_1 & _GEN_58 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire _GEN_60 = io_writeReq_0_bits_index == 5'hF; + wire _GEN_61 = io_writeReq_0_bits_index == 5'h10; + wire [7:0] _GEN_62 = _T_1 & _GEN_61 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire _GEN_63 = io_writeReq_0_bits_index == 5'h11; + wire _GEN_64 = io_writeReq_0_bits_index == 5'h12; + wire [7:0] _GEN_65 = _T_1 & _GEN_64 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire _GEN_66 = io_writeReq_0_bits_index == 5'h13; + wire _GEN_67 = io_writeReq_0_bits_index == 5'h14; + wire [7:0] _GEN_68 = _T_1 & _GEN_67 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire _GEN_69 = io_writeReq_0_bits_index == 5'h15; + wire _GEN_70 = io_writeReq_0_bits_index == 5'h16; + wire [7:0] _GEN_71 = _T_1 & _GEN_70 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire _GEN_72 = io_writeReq_0_bits_index == 5'h17; + wire _GEN_73 = io_writeReq_0_bits_index == 5'h18; + wire [7:0] _GEN_74 = _T_1 & _GEN_73 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire _GEN_75 = io_writeReq_0_bits_index == 5'h19; + wire _GEN_76 = io_writeReq_0_bits_index == 5'h1A; + wire [7:0] _GEN_77 = _T_1 & _GEN_76 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire _GEN_78 = io_writeReq_0_bits_index == 5'h1B; + wire _GEN_79 = io_writeReq_0_bits_index == 5'h1C; + wire [7:0] _GEN_80 = _T_1 & _GEN_79 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire _GEN_81 = io_writeReq_0_bits_index == 5'h1D; + wire _GEN_82 = io_writeReq_0_bits_index == 5'h1E; + wire [7:0] _GEN_83 = _T_1 & _GEN_82 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire _GEN_84 = _T_1 & _GEN_37; + wire _GEN_85 = _T_1 & _GEN_39; + wire _GEN_86 = _T_1 & _GEN_40; + wire _GEN_87 = _T_1 & _GEN_42; + wire _GEN_88 = _T_1 & _GEN_43; + wire _GEN_89 = _T_1 & _GEN_45; + wire _GEN_90 = _T_1 & _GEN_46; + wire _GEN_91 = _T_1 & _GEN_48; + wire _GEN_92 = _T_1 & _GEN_49; + wire _GEN_93 = _T_1 & _GEN_51; + wire _GEN_94 = _T_1 & _GEN_52; + wire _GEN_95 = _T_1 & _GEN_54; + wire _GEN_96 = _T_1 & _GEN_55; + wire _GEN_97 = _T_1 & _GEN_57; + wire _GEN_98 = _T_1 & _GEN_58; + wire _GEN_99 = _T_1 & _GEN_60; + wire _GEN_100 = _T_1 & _GEN_61; + wire _GEN_101 = _T_1 & _GEN_63; + wire _GEN_102 = _T_1 & _GEN_64; + wire _GEN_103 = _T_1 & _GEN_66; + wire _GEN_104 = _T_1 & _GEN_67; + wire _GEN_105 = _T_1 & _GEN_69; + wire _GEN_106 = _T_1 & _GEN_70; + wire _GEN_107 = _T_1 & _GEN_72; + wire _GEN_108 = _T_1 & _GEN_73; + wire _GEN_109 = _T_1 & _GEN_75; + wire _GEN_110 = _T_1 & _GEN_76; + wire _GEN_111 = _T_1 & _GEN_78; + wire _GEN_112 = _T_1 & _GEN_79; + wire _GEN_113 = _T_1 & _GEN_81; + wire _GEN_114 = _T_1 & _GEN_82; + wire _GEN_115 = _T_1 & (&io_writeReq_0_bits_index); + wire _T_8 = io_writeReq_0_bits_vtype_vsew == 3'h1; + wire _GEN_116 = io_writeReq_0_bits_index[3:0] == 4'h0; + wire _GEN_117 = io_writeReq_0_bits_index[3:0] == 4'h1; + wire _GEN_118 = io_writeReq_0_bits_index[3:0] == 4'h2; + wire _GEN_119 = io_writeReq_0_bits_index[3:0] == 4'h3; + wire _GEN_120 = io_writeReq_0_bits_index[3:0] == 4'h4; + wire _GEN_121 = io_writeReq_0_bits_index[3:0] == 4'h5; + wire _GEN_122 = io_writeReq_0_bits_index[3:0] == 4'h6; + wire _GEN_123 = io_writeReq_0_bits_index[3:0] == 4'h7; + wire _GEN_124 = io_writeReq_0_bits_index[3:0] == 4'h8; + wire _GEN_125 = io_writeReq_0_bits_index[3:0] == 4'h9; + wire _GEN_126 = io_writeReq_0_bits_index[3:0] == 4'hA; + wire _GEN_127 = io_writeReq_0_bits_index[3:0] == 4'hB; + wire _GEN_128 = io_writeReq_0_bits_index[3:0] == 4'hC; + wire _GEN_129 = io_writeReq_0_bits_index[3:0] == 4'hD; + wire _GEN_130 = io_writeReq_0_bits_index[3:0] == 4'hE; + wire [4:0] _GEN_131 = {io_writeReq_0_bits_index[3:0], 1'h0}; + wire [4:0] _T_20 = _GEN_131 + 5'h1; + wire [7:0] _GEN_132 = + _T_8 + ? (_T_20 == 5'h0 + ? io_writeReq_0_bits_data[15:8] + : _GEN_116 ? io_writeReq_0_bits_data[7:0] : _GEN_38) + : _GEN_38; + wire [7:0] _GEN_133 = + _T_8 & _T_20 == 5'h1 + ? io_writeReq_0_bits_data[15:8] + : _T_1 & _GEN_39 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_134 = + _T_8 + ? (_T_20 == 5'h2 + ? io_writeReq_0_bits_data[15:8] + : _GEN_117 ? io_writeReq_0_bits_data[7:0] : _GEN_41) + : _GEN_41; + wire [7:0] _GEN_135 = + _T_8 & _T_20 == 5'h3 + ? io_writeReq_0_bits_data[15:8] + : _T_1 & _GEN_42 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_136 = + _T_8 + ? (_T_20 == 5'h4 + ? io_writeReq_0_bits_data[15:8] + : _GEN_118 ? io_writeReq_0_bits_data[7:0] : _GEN_44) + : _GEN_44; + wire [7:0] _GEN_137 = + _T_8 & _T_20 == 5'h5 + ? io_writeReq_0_bits_data[15:8] + : _T_1 & _GEN_45 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_138 = + _T_8 + ? (_T_20 == 5'h6 + ? io_writeReq_0_bits_data[15:8] + : _GEN_119 ? io_writeReq_0_bits_data[7:0] : _GEN_47) + : _GEN_47; + wire [7:0] _GEN_139 = + _T_8 & _T_20 == 5'h7 + ? io_writeReq_0_bits_data[15:8] + : _T_1 & _GEN_48 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_140 = + _T_8 + ? (_T_20 == 5'h8 + ? io_writeReq_0_bits_data[15:8] + : _GEN_120 ? io_writeReq_0_bits_data[7:0] : _GEN_50) + : _GEN_50; + wire [7:0] _GEN_141 = + _T_8 & _T_20 == 5'h9 + ? io_writeReq_0_bits_data[15:8] + : _T_1 & _GEN_51 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_142 = + _T_8 + ? (_T_20 == 5'hA + ? io_writeReq_0_bits_data[15:8] + : _GEN_121 ? io_writeReq_0_bits_data[7:0] : _GEN_53) + : _GEN_53; + wire [7:0] _GEN_143 = + _T_8 & _T_20 == 5'hB + ? io_writeReq_0_bits_data[15:8] + : _T_1 & _GEN_54 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_144 = + _T_8 + ? (_T_20 == 5'hC + ? io_writeReq_0_bits_data[15:8] + : _GEN_122 ? io_writeReq_0_bits_data[7:0] : _GEN_56) + : _GEN_56; + wire [7:0] _GEN_145 = + _T_8 & _T_20 == 5'hD + ? io_writeReq_0_bits_data[15:8] + : _T_1 & _GEN_57 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_146 = + _T_8 + ? (_T_20 == 5'hE + ? io_writeReq_0_bits_data[15:8] + : _GEN_123 ? io_writeReq_0_bits_data[7:0] : _GEN_59) + : _GEN_59; + wire [7:0] _GEN_147 = + _T_8 & _T_20 == 5'hF + ? io_writeReq_0_bits_data[15:8] + : _T_1 & _GEN_60 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_148 = + _T_8 + ? (_T_20 == 5'h10 + ? io_writeReq_0_bits_data[15:8] + : _GEN_124 ? io_writeReq_0_bits_data[7:0] : _GEN_62) + : _GEN_62; + wire [7:0] _GEN_149 = + _T_8 & _T_20 == 5'h11 + ? io_writeReq_0_bits_data[15:8] + : _T_1 & _GEN_63 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_150 = + _T_8 + ? (_T_20 == 5'h12 + ? io_writeReq_0_bits_data[15:8] + : _GEN_125 ? io_writeReq_0_bits_data[7:0] : _GEN_65) + : _GEN_65; + wire [7:0] _GEN_151 = + _T_8 & _T_20 == 5'h13 + ? io_writeReq_0_bits_data[15:8] + : _T_1 & _GEN_66 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_152 = + _T_8 + ? (_T_20 == 5'h14 + ? io_writeReq_0_bits_data[15:8] + : _GEN_126 ? io_writeReq_0_bits_data[7:0] : _GEN_68) + : _GEN_68; + wire [7:0] _GEN_153 = + _T_8 & _T_20 == 5'h15 + ? io_writeReq_0_bits_data[15:8] + : _T_1 & _GEN_69 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_154 = + _T_8 + ? (_T_20 == 5'h16 + ? io_writeReq_0_bits_data[15:8] + : _GEN_127 ? io_writeReq_0_bits_data[7:0] : _GEN_71) + : _GEN_71; + wire [7:0] _GEN_155 = + _T_8 & _T_20 == 5'h17 + ? io_writeReq_0_bits_data[15:8] + : _T_1 & _GEN_72 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_156 = + _T_8 + ? (_T_20 == 5'h18 + ? io_writeReq_0_bits_data[15:8] + : _GEN_128 ? io_writeReq_0_bits_data[7:0] : _GEN_74) + : _GEN_74; + wire [7:0] _GEN_157 = + _T_8 & _T_20 == 5'h19 + ? io_writeReq_0_bits_data[15:8] + : _T_1 & _GEN_75 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_158 = + _T_8 + ? (_T_20 == 5'h1A + ? io_writeReq_0_bits_data[15:8] + : _GEN_129 ? io_writeReq_0_bits_data[7:0] : _GEN_77) + : _GEN_77; + wire [7:0] _GEN_159 = + _T_8 & _T_20 == 5'h1B + ? io_writeReq_0_bits_data[15:8] + : _T_1 & _GEN_78 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_160 = + _T_8 + ? (_T_20 == 5'h1C + ? io_writeReq_0_bits_data[15:8] + : _GEN_130 ? io_writeReq_0_bits_data[7:0] : _GEN_80) + : _GEN_80; + wire [7:0] _GEN_161 = + _T_8 & _T_20 == 5'h1D + ? io_writeReq_0_bits_data[15:8] + : _T_1 & _GEN_81 ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_162 = + _T_8 + ? (_T_20 == 5'h1E + ? io_writeReq_0_bits_data[15:8] + : (&(io_writeReq_0_bits_index[3:0])) ? io_writeReq_0_bits_data[7:0] : _GEN_83) + : _GEN_83; + wire [7:0] _GEN_163 = + _T_8 & (&_T_20) + ? io_writeReq_0_bits_data[15:8] + : _T_1 & (&io_writeReq_0_bits_index) ? io_writeReq_0_bits_data[7:0] : 8'h0; + wire [4:0] _T_24 = _GEN_131 + 5'h1; + wire _GEN_164 = _T_8 & (_T_24 == 5'h0 | _GEN_116); + wire _GEN_165 = _T_8 & _T_24 == 5'h1; + wire _GEN_166 = _T_8 & (_T_24 == 5'h2 | _GEN_117); + wire _GEN_167 = _T_8 & _T_24 == 5'h3; + wire _GEN_168 = _T_8 & (_T_24 == 5'h4 | _GEN_118); + wire _GEN_169 = _T_8 & _T_24 == 5'h5; + wire _GEN_170 = _T_8 & (_T_24 == 5'h6 | _GEN_119); + wire _GEN_171 = _T_8 & _T_24 == 5'h7; + wire _GEN_172 = _T_8 & (_T_24 == 5'h8 | _GEN_120); + wire _GEN_173 = _T_8 & _T_24 == 5'h9; + wire _GEN_174 = _T_8 & (_T_24 == 5'hA | _GEN_121); + wire _GEN_175 = _T_8 & _T_24 == 5'hB; + wire _GEN_176 = _T_8 & (_T_24 == 5'hC | _GEN_122); + wire _GEN_177 = _T_8 & _T_24 == 5'hD; + wire _GEN_178 = _T_8 & (_T_24 == 5'hE | _GEN_123); + wire _GEN_179 = _T_8 & _T_24 == 5'hF; + wire _GEN_180 = _T_8 & (_T_24 == 5'h10 | _GEN_124); + wire _GEN_181 = _T_8 & _T_24 == 5'h11; + wire _GEN_182 = _T_8 & (_T_24 == 5'h12 | _GEN_125); + wire _GEN_183 = _T_8 & _T_24 == 5'h13; + wire _GEN_184 = _T_8 & (_T_24 == 5'h14 | _GEN_126); + wire _GEN_185 = _T_8 & _T_24 == 5'h15; + wire _GEN_186 = _T_8 & (_T_24 == 5'h16 | _GEN_127); + wire _GEN_187 = _T_8 & _T_24 == 5'h17; + wire _GEN_188 = _T_8 & (_T_24 == 5'h18 | _GEN_128); + wire _GEN_189 = _T_8 & _T_24 == 5'h19; + wire _GEN_190 = _T_8 & (_T_24 == 5'h1A | _GEN_129); + wire _GEN_191 = _T_8 & _T_24 == 5'h1B; + wire _GEN_192 = _T_8 & (_T_24 == 5'h1C | _GEN_130); + wire _GEN_193 = _T_8 & _T_24 == 5'h1D; + wire _GEN_194 = + _T_8 & (_T_24 == 5'h1E | (&(io_writeReq_0_bits_index[3:0]))); + wire _GEN_195 = _T_8 & (&_T_24); + wire _T_25 = io_writeReq_0_bits_vtype_vsew == 3'h2; + wire _GEN_196 = io_writeReq_0_bits_index[2:0] == 3'h0; + wire _GEN_197 = io_writeReq_0_bits_index[2:0] == 3'h1; + wire _GEN_198 = io_writeReq_0_bits_index[2:0] == 3'h2; + wire _GEN_199 = io_writeReq_0_bits_index[2:0] == 3'h3; + wire _GEN_200 = io_writeReq_0_bits_index[2:0] == 3'h4; + wire _GEN_201 = io_writeReq_0_bits_index[2:0] == 3'h5; + wire _GEN_202 = io_writeReq_0_bits_index[2:0] == 3'h6; + wire [4:0] _GEN_203 = {io_writeReq_0_bits_index[2:0], 2'h0}; + wire [4:0] _T_37 = _GEN_203 + 5'h1; + wire [4:0] _T_41 = _GEN_203 + 5'h1; + wire [4:0] _T_45 = _GEN_203 + 5'h2; + wire [4:0] _T_49 = _GEN_203 + 5'h2; + wire [4:0] _T_53 = _GEN_203 + 5'h3; + wire [7:0] _GEN_204 = + _T_25 + ? (_T_53 == 5'h0 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h0 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h0 + ? io_writeReq_0_bits_data[15:8] + : _GEN_196 ? io_writeReq_0_bits_data[7:0] : _GEN_132) + : _GEN_132; + wire [7:0] _GEN_205 = + _T_25 + ? (_T_53 == 5'h1 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h1 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h1 ? io_writeReq_0_bits_data[15:8] : _GEN_133) + : _GEN_133; + wire [7:0] _GEN_206 = + _T_25 + ? (_T_53 == 5'h2 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h2 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h2 ? io_writeReq_0_bits_data[15:8] : _GEN_134) + : _GEN_134; + wire [7:0] _GEN_207 = + _T_25 + ? (_T_53 == 5'h3 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h3 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h3 ? io_writeReq_0_bits_data[15:8] : _GEN_135) + : _GEN_135; + wire [7:0] _GEN_208 = + _T_25 + ? (_T_53 == 5'h4 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h4 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h4 + ? io_writeReq_0_bits_data[15:8] + : _GEN_197 ? io_writeReq_0_bits_data[7:0] : _GEN_136) + : _GEN_136; + wire [7:0] _GEN_209 = + _T_25 + ? (_T_53 == 5'h5 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h5 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h5 ? io_writeReq_0_bits_data[15:8] : _GEN_137) + : _GEN_137; + wire [7:0] _GEN_210 = + _T_25 + ? (_T_53 == 5'h6 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h6 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h6 ? io_writeReq_0_bits_data[15:8] : _GEN_138) + : _GEN_138; + wire [7:0] _GEN_211 = + _T_25 + ? (_T_53 == 5'h7 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h7 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h7 ? io_writeReq_0_bits_data[15:8] : _GEN_139) + : _GEN_139; + wire [7:0] _GEN_212 = + _T_25 + ? (_T_53 == 5'h8 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h8 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h8 + ? io_writeReq_0_bits_data[15:8] + : _GEN_198 ? io_writeReq_0_bits_data[7:0] : _GEN_140) + : _GEN_140; + wire [7:0] _GEN_213 = + _T_25 + ? (_T_53 == 5'h9 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h9 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h9 ? io_writeReq_0_bits_data[15:8] : _GEN_141) + : _GEN_141; + wire [7:0] _GEN_214 = + _T_25 + ? (_T_53 == 5'hA + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'hA + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'hA ? io_writeReq_0_bits_data[15:8] : _GEN_142) + : _GEN_142; + wire [7:0] _GEN_215 = + _T_25 + ? (_T_53 == 5'hB + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'hB + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'hB ? io_writeReq_0_bits_data[15:8] : _GEN_143) + : _GEN_143; + wire [7:0] _GEN_216 = + _T_25 + ? (_T_53 == 5'hC + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'hC + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'hC + ? io_writeReq_0_bits_data[15:8] + : _GEN_199 ? io_writeReq_0_bits_data[7:0] : _GEN_144) + : _GEN_144; + wire [7:0] _GEN_217 = + _T_25 + ? (_T_53 == 5'hD + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'hD + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'hD ? io_writeReq_0_bits_data[15:8] : _GEN_145) + : _GEN_145; + wire [7:0] _GEN_218 = + _T_25 + ? (_T_53 == 5'hE + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'hE + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'hE ? io_writeReq_0_bits_data[15:8] : _GEN_146) + : _GEN_146; + wire [7:0] _GEN_219 = + _T_25 + ? (_T_53 == 5'hF + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'hF + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'hF ? io_writeReq_0_bits_data[15:8] : _GEN_147) + : _GEN_147; + wire [7:0] _GEN_220 = + _T_25 + ? (_T_53 == 5'h10 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h10 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h10 + ? io_writeReq_0_bits_data[15:8] + : _GEN_200 ? io_writeReq_0_bits_data[7:0] : _GEN_148) + : _GEN_148; + wire [7:0] _GEN_221 = + _T_25 + ? (_T_53 == 5'h11 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h11 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h11 ? io_writeReq_0_bits_data[15:8] : _GEN_149) + : _GEN_149; + wire [7:0] _GEN_222 = + _T_25 + ? (_T_53 == 5'h12 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h12 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h12 ? io_writeReq_0_bits_data[15:8] : _GEN_150) + : _GEN_150; + wire [7:0] _GEN_223 = + _T_25 + ? (_T_53 == 5'h13 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h13 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h13 ? io_writeReq_0_bits_data[15:8] : _GEN_151) + : _GEN_151; + wire [7:0] _GEN_224 = + _T_25 + ? (_T_53 == 5'h14 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h14 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h14 + ? io_writeReq_0_bits_data[15:8] + : _GEN_201 ? io_writeReq_0_bits_data[7:0] : _GEN_152) + : _GEN_152; + wire [7:0] _GEN_225 = + _T_25 + ? (_T_53 == 5'h15 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h15 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h15 ? io_writeReq_0_bits_data[15:8] : _GEN_153) + : _GEN_153; + wire [7:0] _GEN_226 = + _T_25 + ? (_T_53 == 5'h16 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h16 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h16 ? io_writeReq_0_bits_data[15:8] : _GEN_154) + : _GEN_154; + wire [7:0] _GEN_227 = + _T_25 + ? (_T_53 == 5'h17 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h17 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h17 ? io_writeReq_0_bits_data[15:8] : _GEN_155) + : _GEN_155; + wire [7:0] _GEN_228 = + _T_25 + ? (_T_53 == 5'h18 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h18 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h18 + ? io_writeReq_0_bits_data[15:8] + : _GEN_202 ? io_writeReq_0_bits_data[7:0] : _GEN_156) + : _GEN_156; + wire [7:0] _GEN_229 = + _T_25 + ? (_T_53 == 5'h19 + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h19 + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h19 ? io_writeReq_0_bits_data[15:8] : _GEN_157) + : _GEN_157; + wire [7:0] _GEN_230 = + _T_25 + ? (_T_53 == 5'h1A + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h1A + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h1A ? io_writeReq_0_bits_data[15:8] : _GEN_158) + : _GEN_158; + wire [7:0] _GEN_231 = + _T_25 + ? (_T_53 == 5'h1B + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h1B + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h1B ? io_writeReq_0_bits_data[15:8] : _GEN_159) + : _GEN_159; + wire [7:0] _GEN_232 = + _T_25 + ? (_T_53 == 5'h1C + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h1C + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h1C + ? io_writeReq_0_bits_data[15:8] + : (&(io_writeReq_0_bits_index[2:0])) + ? io_writeReq_0_bits_data[7:0] + : _GEN_160) + : _GEN_160; + wire [7:0] _GEN_233 = + _T_25 + ? (_T_53 == 5'h1D + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h1D + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h1D ? io_writeReq_0_bits_data[15:8] : _GEN_161) + : _GEN_161; + wire [7:0] _GEN_234 = + _T_25 + ? (_T_53 == 5'h1E + ? io_writeReq_0_bits_data[31:24] + : _T_45 == 5'h1E + ? io_writeReq_0_bits_data[23:16] + : _T_37 == 5'h1E ? io_writeReq_0_bits_data[15:8] : _GEN_162) + : _GEN_162; + wire [7:0] _GEN_235 = + _T_25 + ? ((&_T_53) + ? io_writeReq_0_bits_data[31:24] + : (&_T_45) + ? io_writeReq_0_bits_data[23:16] + : (&_T_37) ? io_writeReq_0_bits_data[15:8] : _GEN_163) + : _GEN_163; + wire [4:0] _T_57 = _GEN_203 + 5'h3; + wire _T_58 = io_writeReq_0_bits_vtype_vsew == 3'h3; + wire _GEN_236 = io_writeReq_0_bits_index[1:0] == 2'h0; + wire _GEN_237 = io_writeReq_0_bits_index[1:0] == 2'h1; + wire _GEN_238 = io_writeReq_0_bits_index[1:0] == 2'h2; + wire [4:0] _GEN_239 = {io_writeReq_0_bits_index[1:0], 3'h0}; + wire [4:0] _T_70 = _GEN_239 + 5'h1; + wire [4:0] _T_74 = _GEN_239 + 5'h1; + wire [4:0] _T_78 = _GEN_239 + 5'h2; + wire [4:0] _T_82 = _GEN_239 + 5'h2; + wire [4:0] _T_86 = _GEN_239 + 5'h3; + wire [4:0] _T_90 = _GEN_239 + 5'h3; + wire [4:0] _T_94 = _GEN_239 + 5'h4; + wire [4:0] _T_98 = _GEN_239 + 5'h4; + wire [4:0] _T_102 = _GEN_239 + 5'h5; + wire [4:0] _T_106 = _GEN_239 + 5'h5; + wire [4:0] _T_110 = _GEN_239 + 5'h6; + wire [4:0] _T_114 = _GEN_239 + 5'h6; + wire [4:0] _T_118 = _GEN_239 + 5'h7; + assign internalWriteData_0 = + _T_58 + ? (_T_118 == 5'h0 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h0 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h0 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h0 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h0 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h0 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h0 + ? io_writeReq_0_bits_data[15:8] + : _GEN_236 ? io_writeReq_0_bits_data[7:0] : _GEN_204) + : _GEN_204; + assign internalWriteData_1 = + _T_58 + ? (_T_118 == 5'h1 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h1 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h1 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h1 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h1 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h1 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h1 ? io_writeReq_0_bits_data[15:8] : _GEN_205) + : _GEN_205; + assign internalWriteData_2 = + _T_58 + ? (_T_118 == 5'h2 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h2 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h2 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h2 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h2 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h2 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h2 ? io_writeReq_0_bits_data[15:8] : _GEN_206) + : _GEN_206; + assign internalWriteData_3 = + _T_58 + ? (_T_118 == 5'h3 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h3 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h3 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h3 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h3 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h3 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h3 ? io_writeReq_0_bits_data[15:8] : _GEN_207) + : _GEN_207; + assign internalWriteData_4 = + _T_58 + ? (_T_118 == 5'h4 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h4 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h4 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h4 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h4 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h4 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h4 ? io_writeReq_0_bits_data[15:8] : _GEN_208) + : _GEN_208; + assign internalWriteData_5 = + _T_58 + ? (_T_118 == 5'h5 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h5 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h5 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h5 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h5 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h5 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h5 ? io_writeReq_0_bits_data[15:8] : _GEN_209) + : _GEN_209; + assign internalWriteData_6 = + _T_58 + ? (_T_118 == 5'h6 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h6 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h6 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h6 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h6 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h6 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h6 ? io_writeReq_0_bits_data[15:8] : _GEN_210) + : _GEN_210; + assign internalWriteData_7 = + _T_58 + ? (_T_118 == 5'h7 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h7 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h7 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h7 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h7 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h7 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h7 ? io_writeReq_0_bits_data[15:8] : _GEN_211) + : _GEN_211; + assign internalWriteData_8 = + _T_58 + ? (_T_118 == 5'h8 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h8 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h8 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h8 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h8 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h8 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h8 + ? io_writeReq_0_bits_data[15:8] + : _GEN_237 ? io_writeReq_0_bits_data[7:0] : _GEN_212) + : _GEN_212; + assign internalWriteData_9 = + _T_58 + ? (_T_118 == 5'h9 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h9 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h9 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h9 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h9 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h9 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h9 ? io_writeReq_0_bits_data[15:8] : _GEN_213) + : _GEN_213; + assign internalWriteData_10 = + _T_58 + ? (_T_118 == 5'hA + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'hA + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'hA + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'hA + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'hA + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'hA + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'hA ? io_writeReq_0_bits_data[15:8] : _GEN_214) + : _GEN_214; + assign internalWriteData_11 = + _T_58 + ? (_T_118 == 5'hB + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'hB + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'hB + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'hB + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'hB + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'hB + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'hB ? io_writeReq_0_bits_data[15:8] : _GEN_215) + : _GEN_215; + assign internalWriteData_12 = + _T_58 + ? (_T_118 == 5'hC + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'hC + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'hC + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'hC + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'hC + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'hC + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'hC ? io_writeReq_0_bits_data[15:8] : _GEN_216) + : _GEN_216; + assign internalWriteData_13 = + _T_58 + ? (_T_118 == 5'hD + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'hD + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'hD + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'hD + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'hD + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'hD + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'hD ? io_writeReq_0_bits_data[15:8] : _GEN_217) + : _GEN_217; + assign internalWriteData_14 = + _T_58 + ? (_T_118 == 5'hE + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'hE + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'hE + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'hE + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'hE + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'hE + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'hE ? io_writeReq_0_bits_data[15:8] : _GEN_218) + : _GEN_218; + assign internalWriteData_15 = + _T_58 + ? (_T_118 == 5'hF + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'hF + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'hF + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'hF + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'hF + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'hF + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'hF ? io_writeReq_0_bits_data[15:8] : _GEN_219) + : _GEN_219; + assign internalWriteData_16 = + _T_58 + ? (_T_118 == 5'h10 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h10 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h10 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h10 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h10 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h10 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h10 + ? io_writeReq_0_bits_data[15:8] + : _GEN_238 ? io_writeReq_0_bits_data[7:0] : _GEN_220) + : _GEN_220; + assign internalWriteData_17 = + _T_58 + ? (_T_118 == 5'h11 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h11 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h11 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h11 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h11 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h11 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h11 + ? io_writeReq_0_bits_data[15:8] + : _GEN_221) + : _GEN_221; + assign internalWriteData_18 = + _T_58 + ? (_T_118 == 5'h12 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h12 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h12 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h12 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h12 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h12 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h12 + ? io_writeReq_0_bits_data[15:8] + : _GEN_222) + : _GEN_222; + assign internalWriteData_19 = + _T_58 + ? (_T_118 == 5'h13 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h13 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h13 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h13 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h13 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h13 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h13 + ? io_writeReq_0_bits_data[15:8] + : _GEN_223) + : _GEN_223; + assign internalWriteData_20 = + _T_58 + ? (_T_118 == 5'h14 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h14 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h14 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h14 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h14 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h14 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h14 + ? io_writeReq_0_bits_data[15:8] + : _GEN_224) + : _GEN_224; + assign internalWriteData_21 = + _T_58 + ? (_T_118 == 5'h15 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h15 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h15 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h15 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h15 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h15 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h15 + ? io_writeReq_0_bits_data[15:8] + : _GEN_225) + : _GEN_225; + assign internalWriteData_22 = + _T_58 + ? (_T_118 == 5'h16 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h16 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h16 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h16 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h16 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h16 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h16 + ? io_writeReq_0_bits_data[15:8] + : _GEN_226) + : _GEN_226; + assign internalWriteData_23 = + _T_58 + ? (_T_118 == 5'h17 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h17 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h17 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h17 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h17 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h17 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h17 + ? io_writeReq_0_bits_data[15:8] + : _GEN_227) + : _GEN_227; + assign internalWriteData_24 = + _T_58 + ? (_T_118 == 5'h18 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h18 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h18 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h18 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h18 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h18 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h18 + ? io_writeReq_0_bits_data[15:8] + : (&(io_writeReq_0_bits_index[1:0])) + ? io_writeReq_0_bits_data[7:0] + : _GEN_228) + : _GEN_228; + assign internalWriteData_25 = + _T_58 + ? (_T_118 == 5'h19 + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h19 + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h19 + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h19 + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h19 + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h19 + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h19 + ? io_writeReq_0_bits_data[15:8] + : _GEN_229) + : _GEN_229; + assign internalWriteData_26 = + _T_58 + ? (_T_118 == 5'h1A + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h1A + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h1A + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h1A + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h1A + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h1A + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h1A + ? io_writeReq_0_bits_data[15:8] + : _GEN_230) + : _GEN_230; + assign internalWriteData_27 = + _T_58 + ? (_T_118 == 5'h1B + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h1B + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h1B + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h1B + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h1B + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h1B + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h1B + ? io_writeReq_0_bits_data[15:8] + : _GEN_231) + : _GEN_231; + assign internalWriteData_28 = + _T_58 + ? (_T_118 == 5'h1C + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h1C + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h1C + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h1C + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h1C + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h1C + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h1C + ? io_writeReq_0_bits_data[15:8] + : _GEN_232) + : _GEN_232; + assign internalWriteData_29 = + _T_58 + ? (_T_118 == 5'h1D + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h1D + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h1D + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h1D + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h1D + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h1D + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h1D + ? io_writeReq_0_bits_data[15:8] + : _GEN_233) + : _GEN_233; + assign internalWriteData_30 = + _T_58 + ? (_T_118 == 5'h1E + ? io_writeReq_0_bits_data[63:56] + : _T_110 == 5'h1E + ? io_writeReq_0_bits_data[55:48] + : _T_102 == 5'h1E + ? io_writeReq_0_bits_data[47:40] + : _T_94 == 5'h1E + ? io_writeReq_0_bits_data[39:32] + : _T_86 == 5'h1E + ? io_writeReq_0_bits_data[31:24] + : _T_78 == 5'h1E + ? io_writeReq_0_bits_data[23:16] + : _T_70 == 5'h1E + ? io_writeReq_0_bits_data[15:8] + : _GEN_234) + : _GEN_234; + assign internalWriteData_31 = + _T_58 + ? ((&_T_118) + ? io_writeReq_0_bits_data[63:56] + : (&_T_110) + ? io_writeReq_0_bits_data[55:48] + : (&_T_102) + ? io_writeReq_0_bits_data[47:40] + : (&_T_94) + ? io_writeReq_0_bits_data[39:32] + : (&_T_86) + ? io_writeReq_0_bits_data[31:24] + : (&_T_78) + ? io_writeReq_0_bits_data[23:16] + : (&_T_70) ? io_writeReq_0_bits_data[15:8] : _GEN_235) + : _GEN_235; + wire [4:0] _T_122 = _GEN_239 + 5'h7; + assign internalWriteMask_0 = + _T_58 + & (_T_122 == 5'h0 | _T_114 == 5'h0 | _T_106 == 5'h0 | _T_98 == 5'h0 | _T_90 == 5'h0 + | _T_82 == 5'h0 | _T_74 == 5'h0 | _GEN_236) + | (_T_25 + ? _T_57 == 5'h0 | _T_49 == 5'h0 | _T_41 == 5'h0 | _GEN_196 | _GEN_164 | _GEN_84 + : _GEN_164 | _GEN_84); + assign internalWriteMask_1 = + _T_58 + & (_T_122 == 5'h1 | _T_114 == 5'h1 | _T_106 == 5'h1 | _T_98 == 5'h1 | _T_90 == 5'h1 + | _T_82 == 5'h1 | _T_74 == 5'h1) + | (_T_25 + ? _T_57 == 5'h1 | _T_49 == 5'h1 | _T_41 == 5'h1 | _GEN_165 | _GEN_85 + : _GEN_165 | _GEN_85); + assign internalWriteMask_2 = + _T_58 + & (_T_122 == 5'h2 | _T_114 == 5'h2 | _T_106 == 5'h2 | _T_98 == 5'h2 | _T_90 == 5'h2 + | _T_82 == 5'h2 | _T_74 == 5'h2) + | (_T_25 + ? _T_57 == 5'h2 | _T_49 == 5'h2 | _T_41 == 5'h2 | _GEN_166 | _GEN_86 + : _GEN_166 | _GEN_86); + assign internalWriteMask_3 = + _T_58 + & (_T_122 == 5'h3 | _T_114 == 5'h3 | _T_106 == 5'h3 | _T_98 == 5'h3 | _T_90 == 5'h3 + | _T_82 == 5'h3 | _T_74 == 5'h3) + | (_T_25 + ? _T_57 == 5'h3 | _T_49 == 5'h3 | _T_41 == 5'h3 | _GEN_167 | _GEN_87 + : _GEN_167 | _GEN_87); + assign internalWriteMask_4 = + _T_58 + & (_T_122 == 5'h4 | _T_114 == 5'h4 | _T_106 == 5'h4 | _T_98 == 5'h4 | _T_90 == 5'h4 + | _T_82 == 5'h4 | _T_74 == 5'h4) + | (_T_25 + ? _T_57 == 5'h4 | _T_49 == 5'h4 | _T_41 == 5'h4 | _GEN_197 | _GEN_168 | _GEN_88 + : _GEN_168 | _GEN_88); + assign internalWriteMask_5 = + _T_58 + & (_T_122 == 5'h5 | _T_114 == 5'h5 | _T_106 == 5'h5 | _T_98 == 5'h5 | _T_90 == 5'h5 + | _T_82 == 5'h5 | _T_74 == 5'h5) + | (_T_25 + ? _T_57 == 5'h5 | _T_49 == 5'h5 | _T_41 == 5'h5 | _GEN_169 | _GEN_89 + : _GEN_169 | _GEN_89); + assign internalWriteMask_6 = + _T_58 + & (_T_122 == 5'h6 | _T_114 == 5'h6 | _T_106 == 5'h6 | _T_98 == 5'h6 | _T_90 == 5'h6 + | _T_82 == 5'h6 | _T_74 == 5'h6) + | (_T_25 + ? _T_57 == 5'h6 | _T_49 == 5'h6 | _T_41 == 5'h6 | _GEN_170 | _GEN_90 + : _GEN_170 | _GEN_90); + assign internalWriteMask_7 = + _T_58 + & (_T_122 == 5'h7 | _T_114 == 5'h7 | _T_106 == 5'h7 | _T_98 == 5'h7 | _T_90 == 5'h7 + | _T_82 == 5'h7 | _T_74 == 5'h7) + | (_T_25 + ? _T_57 == 5'h7 | _T_49 == 5'h7 | _T_41 == 5'h7 | _GEN_171 | _GEN_91 + : _GEN_171 | _GEN_91); + assign internalWriteMask_8 = + _T_58 + & (_T_122 == 5'h8 | _T_114 == 5'h8 | _T_106 == 5'h8 | _T_98 == 5'h8 | _T_90 == 5'h8 + | _T_82 == 5'h8 | _T_74 == 5'h8 | _GEN_237) + | (_T_25 + ? _T_57 == 5'h8 | _T_49 == 5'h8 | _T_41 == 5'h8 | _GEN_198 | _GEN_172 | _GEN_92 + : _GEN_172 | _GEN_92); + assign internalWriteMask_9 = + _T_58 + & (_T_122 == 5'h9 | _T_114 == 5'h9 | _T_106 == 5'h9 | _T_98 == 5'h9 | _T_90 == 5'h9 + | _T_82 == 5'h9 | _T_74 == 5'h9) + | (_T_25 + ? _T_57 == 5'h9 | _T_49 == 5'h9 | _T_41 == 5'h9 | _GEN_173 | _GEN_93 + : _GEN_173 | _GEN_93); + assign internalWriteMask_10 = + _T_58 + & (_T_122 == 5'hA | _T_114 == 5'hA | _T_106 == 5'hA | _T_98 == 5'hA | _T_90 == 5'hA + | _T_82 == 5'hA | _T_74 == 5'hA) + | (_T_25 + ? _T_57 == 5'hA | _T_49 == 5'hA | _T_41 == 5'hA | _GEN_174 | _GEN_94 + : _GEN_174 | _GEN_94); + assign internalWriteMask_11 = + _T_58 + & (_T_122 == 5'hB | _T_114 == 5'hB | _T_106 == 5'hB | _T_98 == 5'hB | _T_90 == 5'hB + | _T_82 == 5'hB | _T_74 == 5'hB) + | (_T_25 + ? _T_57 == 5'hB | _T_49 == 5'hB | _T_41 == 5'hB | _GEN_175 | _GEN_95 + : _GEN_175 | _GEN_95); + assign internalWriteMask_12 = + _T_58 + & (_T_122 == 5'hC | _T_114 == 5'hC | _T_106 == 5'hC | _T_98 == 5'hC | _T_90 == 5'hC + | _T_82 == 5'hC | _T_74 == 5'hC) + | (_T_25 + ? _T_57 == 5'hC | _T_49 == 5'hC | _T_41 == 5'hC | _GEN_199 | _GEN_176 | _GEN_96 + : _GEN_176 | _GEN_96); + assign internalWriteMask_13 = + _T_58 + & (_T_122 == 5'hD | _T_114 == 5'hD | _T_106 == 5'hD | _T_98 == 5'hD | _T_90 == 5'hD + | _T_82 == 5'hD | _T_74 == 5'hD) + | (_T_25 + ? _T_57 == 5'hD | _T_49 == 5'hD | _T_41 == 5'hD | _GEN_177 | _GEN_97 + : _GEN_177 | _GEN_97); + assign internalWriteMask_14 = + _T_58 + & (_T_122 == 5'hE | _T_114 == 5'hE | _T_106 == 5'hE | _T_98 == 5'hE | _T_90 == 5'hE + | _T_82 == 5'hE | _T_74 == 5'hE) + | (_T_25 + ? _T_57 == 5'hE | _T_49 == 5'hE | _T_41 == 5'hE | _GEN_178 | _GEN_98 + : _GEN_178 | _GEN_98); + assign internalWriteMask_15 = + _T_58 + & (_T_122 == 5'hF | _T_114 == 5'hF | _T_106 == 5'hF | _T_98 == 5'hF | _T_90 == 5'hF + | _T_82 == 5'hF | _T_74 == 5'hF) + | (_T_25 + ? _T_57 == 5'hF | _T_49 == 5'hF | _T_41 == 5'hF | _GEN_179 | _GEN_99 + : _GEN_179 | _GEN_99); + assign internalWriteMask_16 = + _T_58 + & (_T_122 == 5'h10 | _T_114 == 5'h10 | _T_106 == 5'h10 | _T_98 == 5'h10 + | _T_90 == 5'h10 | _T_82 == 5'h10 | _T_74 == 5'h10 | _GEN_238) + | (_T_25 + ? _T_57 == 5'h10 | _T_49 == 5'h10 | _T_41 == 5'h10 | _GEN_200 | _GEN_180 + | _GEN_100 + : _GEN_180 | _GEN_100); + assign internalWriteMask_17 = + _T_58 + & (_T_122 == 5'h11 | _T_114 == 5'h11 | _T_106 == 5'h11 | _T_98 == 5'h11 + | _T_90 == 5'h11 | _T_82 == 5'h11 | _T_74 == 5'h11) + | (_T_25 + ? _T_57 == 5'h11 | _T_49 == 5'h11 | _T_41 == 5'h11 | _GEN_181 | _GEN_101 + : _GEN_181 | _GEN_101); + assign internalWriteMask_18 = + _T_58 + & (_T_122 == 5'h12 | _T_114 == 5'h12 | _T_106 == 5'h12 | _T_98 == 5'h12 + | _T_90 == 5'h12 | _T_82 == 5'h12 | _T_74 == 5'h12) + | (_T_25 + ? _T_57 == 5'h12 | _T_49 == 5'h12 | _T_41 == 5'h12 | _GEN_182 | _GEN_102 + : _GEN_182 | _GEN_102); + assign internalWriteMask_19 = + _T_58 + & (_T_122 == 5'h13 | _T_114 == 5'h13 | _T_106 == 5'h13 | _T_98 == 5'h13 + | _T_90 == 5'h13 | _T_82 == 5'h13 | _T_74 == 5'h13) + | (_T_25 + ? _T_57 == 5'h13 | _T_49 == 5'h13 | _T_41 == 5'h13 | _GEN_183 | _GEN_103 + : _GEN_183 | _GEN_103); + assign internalWriteMask_20 = + _T_58 + & (_T_122 == 5'h14 | _T_114 == 5'h14 | _T_106 == 5'h14 | _T_98 == 5'h14 + | _T_90 == 5'h14 | _T_82 == 5'h14 | _T_74 == 5'h14) + | (_T_25 + ? _T_57 == 5'h14 | _T_49 == 5'h14 | _T_41 == 5'h14 | _GEN_201 | _GEN_184 + | _GEN_104 + : _GEN_184 | _GEN_104); + assign internalWriteMask_21 = + _T_58 + & (_T_122 == 5'h15 | _T_114 == 5'h15 | _T_106 == 5'h15 | _T_98 == 5'h15 + | _T_90 == 5'h15 | _T_82 == 5'h15 | _T_74 == 5'h15) + | (_T_25 + ? _T_57 == 5'h15 | _T_49 == 5'h15 | _T_41 == 5'h15 | _GEN_185 | _GEN_105 + : _GEN_185 | _GEN_105); + assign internalWriteMask_22 = + _T_58 + & (_T_122 == 5'h16 | _T_114 == 5'h16 | _T_106 == 5'h16 | _T_98 == 5'h16 + | _T_90 == 5'h16 | _T_82 == 5'h16 | _T_74 == 5'h16) + | (_T_25 + ? _T_57 == 5'h16 | _T_49 == 5'h16 | _T_41 == 5'h16 | _GEN_186 | _GEN_106 + : _GEN_186 | _GEN_106); + assign internalWriteMask_23 = + _T_58 + & (_T_122 == 5'h17 | _T_114 == 5'h17 | _T_106 == 5'h17 | _T_98 == 5'h17 + | _T_90 == 5'h17 | _T_82 == 5'h17 | _T_74 == 5'h17) + | (_T_25 + ? _T_57 == 5'h17 | _T_49 == 5'h17 | _T_41 == 5'h17 | _GEN_187 | _GEN_107 + : _GEN_187 | _GEN_107); + assign internalWriteMask_24 = + _T_58 + & (_T_122 == 5'h18 | _T_114 == 5'h18 | _T_106 == 5'h18 | _T_98 == 5'h18 + | _T_90 == 5'h18 | _T_82 == 5'h18 | _T_74 == 5'h18 + | (&(io_writeReq_0_bits_index[1:0]))) + | (_T_25 + ? _T_57 == 5'h18 | _T_49 == 5'h18 | _T_41 == 5'h18 | _GEN_202 | _GEN_188 + | _GEN_108 + : _GEN_188 | _GEN_108); + assign internalWriteMask_25 = + _T_58 + & (_T_122 == 5'h19 | _T_114 == 5'h19 | _T_106 == 5'h19 | _T_98 == 5'h19 + | _T_90 == 5'h19 | _T_82 == 5'h19 | _T_74 == 5'h19) + | (_T_25 + ? _T_57 == 5'h19 | _T_49 == 5'h19 | _T_41 == 5'h19 | _GEN_189 | _GEN_109 + : _GEN_189 | _GEN_109); + assign internalWriteMask_26 = + _T_58 + & (_T_122 == 5'h1A | _T_114 == 5'h1A | _T_106 == 5'h1A | _T_98 == 5'h1A + | _T_90 == 5'h1A | _T_82 == 5'h1A | _T_74 == 5'h1A) + | (_T_25 + ? _T_57 == 5'h1A | _T_49 == 5'h1A | _T_41 == 5'h1A | _GEN_190 | _GEN_110 + : _GEN_190 | _GEN_110); + assign internalWriteMask_27 = + _T_58 + & (_T_122 == 5'h1B | _T_114 == 5'h1B | _T_106 == 5'h1B | _T_98 == 5'h1B + | _T_90 == 5'h1B | _T_82 == 5'h1B | _T_74 == 5'h1B) + | (_T_25 + ? _T_57 == 5'h1B | _T_49 == 5'h1B | _T_41 == 5'h1B | _GEN_191 | _GEN_111 + : _GEN_191 | _GEN_111); + assign internalWriteMask_28 = + _T_58 + & (_T_122 == 5'h1C | _T_114 == 5'h1C | _T_106 == 5'h1C | _T_98 == 5'h1C + | _T_90 == 5'h1C | _T_82 == 5'h1C | _T_74 == 5'h1C) + | (_T_25 + ? _T_57 == 5'h1C | _T_49 == 5'h1C | _T_41 == 5'h1C + | (&(io_writeReq_0_bits_index[2:0])) | _GEN_192 | _GEN_112 + : _GEN_192 | _GEN_112); + assign internalWriteMask_29 = + _T_58 + & (_T_122 == 5'h1D | _T_114 == 5'h1D | _T_106 == 5'h1D | _T_98 == 5'h1D + | _T_90 == 5'h1D | _T_82 == 5'h1D | _T_74 == 5'h1D) + | (_T_25 + ? _T_57 == 5'h1D | _T_49 == 5'h1D | _T_41 == 5'h1D | _GEN_193 | _GEN_113 + : _GEN_193 | _GEN_113); + assign internalWriteMask_30 = + _T_58 + & (_T_122 == 5'h1E | _T_114 == 5'h1E | _T_106 == 5'h1E | _T_98 == 5'h1E + | _T_90 == 5'h1E | _T_82 == 5'h1E | _T_74 == 5'h1E) + | (_T_25 + ? _T_57 == 5'h1E | _T_49 == 5'h1E | _T_41 == 5'h1E | _GEN_194 | _GEN_114 + : _GEN_194 | _GEN_114); + assign internalWriteMask_31 = + _T_58 + & ((&_T_122) | (&_T_114) | (&_T_106) | (&_T_98) | (&_T_90) | (&_T_82) | (&_T_74)) + | (_T_25 + ? (&_T_57) | (&_T_49) | (&_T_41) | _GEN_195 | _GEN_115 + : _GEN_195 | _GEN_115); + wire _T_124 = io_writeReq_1_bits_vtype_vsew == 3'h0; + wire _GEN_240 = io_writeReq_1_bits_index == 5'h0; + wire [7:0] _GEN_241 = _T_124 & _GEN_240 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire _GEN_242 = io_writeReq_1_bits_index == 5'h1; + wire _GEN_243 = io_writeReq_1_bits_index == 5'h2; + wire [7:0] _GEN_244 = _T_124 & _GEN_243 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire _GEN_245 = io_writeReq_1_bits_index == 5'h3; + wire _GEN_246 = io_writeReq_1_bits_index == 5'h4; + wire [7:0] _GEN_247 = _T_124 & _GEN_246 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire _GEN_248 = io_writeReq_1_bits_index == 5'h5; + wire _GEN_249 = io_writeReq_1_bits_index == 5'h6; + wire [7:0] _GEN_250 = _T_124 & _GEN_249 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire _GEN_251 = io_writeReq_1_bits_index == 5'h7; + wire _GEN_252 = io_writeReq_1_bits_index == 5'h8; + wire [7:0] _GEN_253 = _T_124 & _GEN_252 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire _GEN_254 = io_writeReq_1_bits_index == 5'h9; + wire _GEN_255 = io_writeReq_1_bits_index == 5'hA; + wire [7:0] _GEN_256 = _T_124 & _GEN_255 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire _GEN_257 = io_writeReq_1_bits_index == 5'hB; + wire _GEN_258 = io_writeReq_1_bits_index == 5'hC; + wire [7:0] _GEN_259 = _T_124 & _GEN_258 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire _GEN_260 = io_writeReq_1_bits_index == 5'hD; + wire _GEN_261 = io_writeReq_1_bits_index == 5'hE; + wire [7:0] _GEN_262 = _T_124 & _GEN_261 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire _GEN_263 = io_writeReq_1_bits_index == 5'hF; + wire _GEN_264 = io_writeReq_1_bits_index == 5'h10; + wire [7:0] _GEN_265 = _T_124 & _GEN_264 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire _GEN_266 = io_writeReq_1_bits_index == 5'h11; + wire _GEN_267 = io_writeReq_1_bits_index == 5'h12; + wire [7:0] _GEN_268 = _T_124 & _GEN_267 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire _GEN_269 = io_writeReq_1_bits_index == 5'h13; + wire _GEN_270 = io_writeReq_1_bits_index == 5'h14; + wire [7:0] _GEN_271 = _T_124 & _GEN_270 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire _GEN_272 = io_writeReq_1_bits_index == 5'h15; + wire _GEN_273 = io_writeReq_1_bits_index == 5'h16; + wire [7:0] _GEN_274 = _T_124 & _GEN_273 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire _GEN_275 = io_writeReq_1_bits_index == 5'h17; + wire _GEN_276 = io_writeReq_1_bits_index == 5'h18; + wire [7:0] _GEN_277 = _T_124 & _GEN_276 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire _GEN_278 = io_writeReq_1_bits_index == 5'h19; + wire _GEN_279 = io_writeReq_1_bits_index == 5'h1A; + wire [7:0] _GEN_280 = _T_124 & _GEN_279 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire _GEN_281 = io_writeReq_1_bits_index == 5'h1B; + wire _GEN_282 = io_writeReq_1_bits_index == 5'h1C; + wire [7:0] _GEN_283 = _T_124 & _GEN_282 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire _GEN_284 = io_writeReq_1_bits_index == 5'h1D; + wire _GEN_285 = io_writeReq_1_bits_index == 5'h1E; + wire [7:0] _GEN_286 = _T_124 & _GEN_285 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire _GEN_287 = _T_124 & _GEN_240; + wire _GEN_288 = _T_124 & _GEN_242; + wire _GEN_289 = _T_124 & _GEN_243; + wire _GEN_290 = _T_124 & _GEN_245; + wire _GEN_291 = _T_124 & _GEN_246; + wire _GEN_292 = _T_124 & _GEN_248; + wire _GEN_293 = _T_124 & _GEN_249; + wire _GEN_294 = _T_124 & _GEN_251; + wire _GEN_295 = _T_124 & _GEN_252; + wire _GEN_296 = _T_124 & _GEN_254; + wire _GEN_297 = _T_124 & _GEN_255; + wire _GEN_298 = _T_124 & _GEN_257; + wire _GEN_299 = _T_124 & _GEN_258; + wire _GEN_300 = _T_124 & _GEN_260; + wire _GEN_301 = _T_124 & _GEN_261; + wire _GEN_302 = _T_124 & _GEN_263; + wire _GEN_303 = _T_124 & _GEN_264; + wire _GEN_304 = _T_124 & _GEN_266; + wire _GEN_305 = _T_124 & _GEN_267; + wire _GEN_306 = _T_124 & _GEN_269; + wire _GEN_307 = _T_124 & _GEN_270; + wire _GEN_308 = _T_124 & _GEN_272; + wire _GEN_309 = _T_124 & _GEN_273; + wire _GEN_310 = _T_124 & _GEN_275; + wire _GEN_311 = _T_124 & _GEN_276; + wire _GEN_312 = _T_124 & _GEN_278; + wire _GEN_313 = _T_124 & _GEN_279; + wire _GEN_314 = _T_124 & _GEN_281; + wire _GEN_315 = _T_124 & _GEN_282; + wire _GEN_316 = _T_124 & _GEN_284; + wire _GEN_317 = _T_124 & _GEN_285; + wire _GEN_318 = _T_124 & (&io_writeReq_1_bits_index); + wire _T_131 = io_writeReq_1_bits_vtype_vsew == 3'h1; + wire _GEN_319 = io_writeReq_1_bits_index[3:0] == 4'h0; + wire _GEN_320 = io_writeReq_1_bits_index[3:0] == 4'h1; + wire _GEN_321 = io_writeReq_1_bits_index[3:0] == 4'h2; + wire _GEN_322 = io_writeReq_1_bits_index[3:0] == 4'h3; + wire _GEN_323 = io_writeReq_1_bits_index[3:0] == 4'h4; + wire _GEN_324 = io_writeReq_1_bits_index[3:0] == 4'h5; + wire _GEN_325 = io_writeReq_1_bits_index[3:0] == 4'h6; + wire _GEN_326 = io_writeReq_1_bits_index[3:0] == 4'h7; + wire _GEN_327 = io_writeReq_1_bits_index[3:0] == 4'h8; + wire _GEN_328 = io_writeReq_1_bits_index[3:0] == 4'h9; + wire _GEN_329 = io_writeReq_1_bits_index[3:0] == 4'hA; + wire _GEN_330 = io_writeReq_1_bits_index[3:0] == 4'hB; + wire _GEN_331 = io_writeReq_1_bits_index[3:0] == 4'hC; + wire _GEN_332 = io_writeReq_1_bits_index[3:0] == 4'hD; + wire _GEN_333 = io_writeReq_1_bits_index[3:0] == 4'hE; + wire [4:0] _GEN_334 = {io_writeReq_1_bits_index[3:0], 1'h0}; + wire [4:0] _T_143 = _GEN_334 + 5'h1; + wire [7:0] _GEN_335 = + _T_131 + ? (_T_143 == 5'h0 + ? io_writeReq_1_bits_data[15:8] + : _GEN_319 ? io_writeReq_1_bits_data[7:0] : _GEN_241) + : _GEN_241; + wire [7:0] _GEN_336 = + _T_131 & _T_143 == 5'h1 + ? io_writeReq_1_bits_data[15:8] + : _T_124 & _GEN_242 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_337 = + _T_131 + ? (_T_143 == 5'h2 + ? io_writeReq_1_bits_data[15:8] + : _GEN_320 ? io_writeReq_1_bits_data[7:0] : _GEN_244) + : _GEN_244; + wire [7:0] _GEN_338 = + _T_131 & _T_143 == 5'h3 + ? io_writeReq_1_bits_data[15:8] + : _T_124 & _GEN_245 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_339 = + _T_131 + ? (_T_143 == 5'h4 + ? io_writeReq_1_bits_data[15:8] + : _GEN_321 ? io_writeReq_1_bits_data[7:0] : _GEN_247) + : _GEN_247; + wire [7:0] _GEN_340 = + _T_131 & _T_143 == 5'h5 + ? io_writeReq_1_bits_data[15:8] + : _T_124 & _GEN_248 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_341 = + _T_131 + ? (_T_143 == 5'h6 + ? io_writeReq_1_bits_data[15:8] + : _GEN_322 ? io_writeReq_1_bits_data[7:0] : _GEN_250) + : _GEN_250; + wire [7:0] _GEN_342 = + _T_131 & _T_143 == 5'h7 + ? io_writeReq_1_bits_data[15:8] + : _T_124 & _GEN_251 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_343 = + _T_131 + ? (_T_143 == 5'h8 + ? io_writeReq_1_bits_data[15:8] + : _GEN_323 ? io_writeReq_1_bits_data[7:0] : _GEN_253) + : _GEN_253; + wire [7:0] _GEN_344 = + _T_131 & _T_143 == 5'h9 + ? io_writeReq_1_bits_data[15:8] + : _T_124 & _GEN_254 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_345 = + _T_131 + ? (_T_143 == 5'hA + ? io_writeReq_1_bits_data[15:8] + : _GEN_324 ? io_writeReq_1_bits_data[7:0] : _GEN_256) + : _GEN_256; + wire [7:0] _GEN_346 = + _T_131 & _T_143 == 5'hB + ? io_writeReq_1_bits_data[15:8] + : _T_124 & _GEN_257 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_347 = + _T_131 + ? (_T_143 == 5'hC + ? io_writeReq_1_bits_data[15:8] + : _GEN_325 ? io_writeReq_1_bits_data[7:0] : _GEN_259) + : _GEN_259; + wire [7:0] _GEN_348 = + _T_131 & _T_143 == 5'hD + ? io_writeReq_1_bits_data[15:8] + : _T_124 & _GEN_260 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_349 = + _T_131 + ? (_T_143 == 5'hE + ? io_writeReq_1_bits_data[15:8] + : _GEN_326 ? io_writeReq_1_bits_data[7:0] : _GEN_262) + : _GEN_262; + wire [7:0] _GEN_350 = + _T_131 & _T_143 == 5'hF + ? io_writeReq_1_bits_data[15:8] + : _T_124 & _GEN_263 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_351 = + _T_131 + ? (_T_143 == 5'h10 + ? io_writeReq_1_bits_data[15:8] + : _GEN_327 ? io_writeReq_1_bits_data[7:0] : _GEN_265) + : _GEN_265; + wire [7:0] _GEN_352 = + _T_131 & _T_143 == 5'h11 + ? io_writeReq_1_bits_data[15:8] + : _T_124 & _GEN_266 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_353 = + _T_131 + ? (_T_143 == 5'h12 + ? io_writeReq_1_bits_data[15:8] + : _GEN_328 ? io_writeReq_1_bits_data[7:0] : _GEN_268) + : _GEN_268; + wire [7:0] _GEN_354 = + _T_131 & _T_143 == 5'h13 + ? io_writeReq_1_bits_data[15:8] + : _T_124 & _GEN_269 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_355 = + _T_131 + ? (_T_143 == 5'h14 + ? io_writeReq_1_bits_data[15:8] + : _GEN_329 ? io_writeReq_1_bits_data[7:0] : _GEN_271) + : _GEN_271; + wire [7:0] _GEN_356 = + _T_131 & _T_143 == 5'h15 + ? io_writeReq_1_bits_data[15:8] + : _T_124 & _GEN_272 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_357 = + _T_131 + ? (_T_143 == 5'h16 + ? io_writeReq_1_bits_data[15:8] + : _GEN_330 ? io_writeReq_1_bits_data[7:0] : _GEN_274) + : _GEN_274; + wire [7:0] _GEN_358 = + _T_131 & _T_143 == 5'h17 + ? io_writeReq_1_bits_data[15:8] + : _T_124 & _GEN_275 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_359 = + _T_131 + ? (_T_143 == 5'h18 + ? io_writeReq_1_bits_data[15:8] + : _GEN_331 ? io_writeReq_1_bits_data[7:0] : _GEN_277) + : _GEN_277; + wire [7:0] _GEN_360 = + _T_131 & _T_143 == 5'h19 + ? io_writeReq_1_bits_data[15:8] + : _T_124 & _GEN_278 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_361 = + _T_131 + ? (_T_143 == 5'h1A + ? io_writeReq_1_bits_data[15:8] + : _GEN_332 ? io_writeReq_1_bits_data[7:0] : _GEN_280) + : _GEN_280; + wire [7:0] _GEN_362 = + _T_131 & _T_143 == 5'h1B + ? io_writeReq_1_bits_data[15:8] + : _T_124 & _GEN_281 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_363 = + _T_131 + ? (_T_143 == 5'h1C + ? io_writeReq_1_bits_data[15:8] + : _GEN_333 ? io_writeReq_1_bits_data[7:0] : _GEN_283) + : _GEN_283; + wire [7:0] _GEN_364 = + _T_131 & _T_143 == 5'h1D + ? io_writeReq_1_bits_data[15:8] + : _T_124 & _GEN_284 ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_365 = + _T_131 + ? (_T_143 == 5'h1E + ? io_writeReq_1_bits_data[15:8] + : (&(io_writeReq_1_bits_index[3:0])) ? io_writeReq_1_bits_data[7:0] : _GEN_286) + : _GEN_286; + wire [7:0] _GEN_366 = + _T_131 & (&_T_143) + ? io_writeReq_1_bits_data[15:8] + : _T_124 & (&io_writeReq_1_bits_index) ? io_writeReq_1_bits_data[7:0] : 8'h0; + wire [4:0] _T_147 = _GEN_334 + 5'h1; + wire _GEN_367 = _T_131 & (_T_147 == 5'h0 | _GEN_319); + wire _GEN_368 = _T_131 & _T_147 == 5'h1; + wire _GEN_369 = _T_131 & (_T_147 == 5'h2 | _GEN_320); + wire _GEN_370 = _T_131 & _T_147 == 5'h3; + wire _GEN_371 = _T_131 & (_T_147 == 5'h4 | _GEN_321); + wire _GEN_372 = _T_131 & _T_147 == 5'h5; + wire _GEN_373 = _T_131 & (_T_147 == 5'h6 | _GEN_322); + wire _GEN_374 = _T_131 & _T_147 == 5'h7; + wire _GEN_375 = _T_131 & (_T_147 == 5'h8 | _GEN_323); + wire _GEN_376 = _T_131 & _T_147 == 5'h9; + wire _GEN_377 = _T_131 & (_T_147 == 5'hA | _GEN_324); + wire _GEN_378 = _T_131 & _T_147 == 5'hB; + wire _GEN_379 = _T_131 & (_T_147 == 5'hC | _GEN_325); + wire _GEN_380 = _T_131 & _T_147 == 5'hD; + wire _GEN_381 = _T_131 & (_T_147 == 5'hE | _GEN_326); + wire _GEN_382 = _T_131 & _T_147 == 5'hF; + wire _GEN_383 = _T_131 & (_T_147 == 5'h10 | _GEN_327); + wire _GEN_384 = _T_131 & _T_147 == 5'h11; + wire _GEN_385 = _T_131 & (_T_147 == 5'h12 | _GEN_328); + wire _GEN_386 = _T_131 & _T_147 == 5'h13; + wire _GEN_387 = _T_131 & (_T_147 == 5'h14 | _GEN_329); + wire _GEN_388 = _T_131 & _T_147 == 5'h15; + wire _GEN_389 = _T_131 & (_T_147 == 5'h16 | _GEN_330); + wire _GEN_390 = _T_131 & _T_147 == 5'h17; + wire _GEN_391 = _T_131 & (_T_147 == 5'h18 | _GEN_331); + wire _GEN_392 = _T_131 & _T_147 == 5'h19; + wire _GEN_393 = _T_131 & (_T_147 == 5'h1A | _GEN_332); + wire _GEN_394 = _T_131 & _T_147 == 5'h1B; + wire _GEN_395 = _T_131 & (_T_147 == 5'h1C | _GEN_333); + wire _GEN_396 = _T_131 & _T_147 == 5'h1D; + wire _GEN_397 = + _T_131 & (_T_147 == 5'h1E | (&(io_writeReq_1_bits_index[3:0]))); + wire _GEN_398 = _T_131 & (&_T_147); + wire _T_148 = io_writeReq_1_bits_vtype_vsew == 3'h2; + wire _GEN_399 = io_writeReq_1_bits_index[2:0] == 3'h0; + wire _GEN_400 = io_writeReq_1_bits_index[2:0] == 3'h1; + wire _GEN_401 = io_writeReq_1_bits_index[2:0] == 3'h2; + wire _GEN_402 = io_writeReq_1_bits_index[2:0] == 3'h3; + wire _GEN_403 = io_writeReq_1_bits_index[2:0] == 3'h4; + wire _GEN_404 = io_writeReq_1_bits_index[2:0] == 3'h5; + wire _GEN_405 = io_writeReq_1_bits_index[2:0] == 3'h6; + wire [4:0] _GEN_406 = {io_writeReq_1_bits_index[2:0], 2'h0}; + wire [4:0] _T_160 = _GEN_406 + 5'h1; + wire [4:0] _T_164 = _GEN_406 + 5'h1; + wire [4:0] _T_168 = _GEN_406 + 5'h2; + wire [4:0] _T_172 = _GEN_406 + 5'h2; + wire [4:0] _T_176 = _GEN_406 + 5'h3; + wire [7:0] _GEN_407 = + _T_148 + ? (_T_176 == 5'h0 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h0 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h0 + ? io_writeReq_1_bits_data[15:8] + : _GEN_399 ? io_writeReq_1_bits_data[7:0] : _GEN_335) + : _GEN_335; + wire [7:0] _GEN_408 = + _T_148 + ? (_T_176 == 5'h1 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h1 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h1 ? io_writeReq_1_bits_data[15:8] : _GEN_336) + : _GEN_336; + wire [7:0] _GEN_409 = + _T_148 + ? (_T_176 == 5'h2 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h2 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h2 ? io_writeReq_1_bits_data[15:8] : _GEN_337) + : _GEN_337; + wire [7:0] _GEN_410 = + _T_148 + ? (_T_176 == 5'h3 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h3 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h3 ? io_writeReq_1_bits_data[15:8] : _GEN_338) + : _GEN_338; + wire [7:0] _GEN_411 = + _T_148 + ? (_T_176 == 5'h4 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h4 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h4 + ? io_writeReq_1_bits_data[15:8] + : _GEN_400 ? io_writeReq_1_bits_data[7:0] : _GEN_339) + : _GEN_339; + wire [7:0] _GEN_412 = + _T_148 + ? (_T_176 == 5'h5 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h5 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h5 ? io_writeReq_1_bits_data[15:8] : _GEN_340) + : _GEN_340; + wire [7:0] _GEN_413 = + _T_148 + ? (_T_176 == 5'h6 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h6 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h6 ? io_writeReq_1_bits_data[15:8] : _GEN_341) + : _GEN_341; + wire [7:0] _GEN_414 = + _T_148 + ? (_T_176 == 5'h7 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h7 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h7 ? io_writeReq_1_bits_data[15:8] : _GEN_342) + : _GEN_342; + wire [7:0] _GEN_415 = + _T_148 + ? (_T_176 == 5'h8 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h8 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h8 + ? io_writeReq_1_bits_data[15:8] + : _GEN_401 ? io_writeReq_1_bits_data[7:0] : _GEN_343) + : _GEN_343; + wire [7:0] _GEN_416 = + _T_148 + ? (_T_176 == 5'h9 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h9 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h9 ? io_writeReq_1_bits_data[15:8] : _GEN_344) + : _GEN_344; + wire [7:0] _GEN_417 = + _T_148 + ? (_T_176 == 5'hA + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'hA + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'hA ? io_writeReq_1_bits_data[15:8] : _GEN_345) + : _GEN_345; + wire [7:0] _GEN_418 = + _T_148 + ? (_T_176 == 5'hB + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'hB + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'hB ? io_writeReq_1_bits_data[15:8] : _GEN_346) + : _GEN_346; + wire [7:0] _GEN_419 = + _T_148 + ? (_T_176 == 5'hC + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'hC + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'hC + ? io_writeReq_1_bits_data[15:8] + : _GEN_402 ? io_writeReq_1_bits_data[7:0] : _GEN_347) + : _GEN_347; + wire [7:0] _GEN_420 = + _T_148 + ? (_T_176 == 5'hD + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'hD + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'hD ? io_writeReq_1_bits_data[15:8] : _GEN_348) + : _GEN_348; + wire [7:0] _GEN_421 = + _T_148 + ? (_T_176 == 5'hE + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'hE + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'hE ? io_writeReq_1_bits_data[15:8] : _GEN_349) + : _GEN_349; + wire [7:0] _GEN_422 = + _T_148 + ? (_T_176 == 5'hF + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'hF + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'hF ? io_writeReq_1_bits_data[15:8] : _GEN_350) + : _GEN_350; + wire [7:0] _GEN_423 = + _T_148 + ? (_T_176 == 5'h10 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h10 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h10 + ? io_writeReq_1_bits_data[15:8] + : _GEN_403 ? io_writeReq_1_bits_data[7:0] : _GEN_351) + : _GEN_351; + wire [7:0] _GEN_424 = + _T_148 + ? (_T_176 == 5'h11 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h11 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h11 ? io_writeReq_1_bits_data[15:8] : _GEN_352) + : _GEN_352; + wire [7:0] _GEN_425 = + _T_148 + ? (_T_176 == 5'h12 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h12 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h12 ? io_writeReq_1_bits_data[15:8] : _GEN_353) + : _GEN_353; + wire [7:0] _GEN_426 = + _T_148 + ? (_T_176 == 5'h13 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h13 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h13 ? io_writeReq_1_bits_data[15:8] : _GEN_354) + : _GEN_354; + wire [7:0] _GEN_427 = + _T_148 + ? (_T_176 == 5'h14 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h14 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h14 + ? io_writeReq_1_bits_data[15:8] + : _GEN_404 ? io_writeReq_1_bits_data[7:0] : _GEN_355) + : _GEN_355; + wire [7:0] _GEN_428 = + _T_148 + ? (_T_176 == 5'h15 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h15 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h15 ? io_writeReq_1_bits_data[15:8] : _GEN_356) + : _GEN_356; + wire [7:0] _GEN_429 = + _T_148 + ? (_T_176 == 5'h16 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h16 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h16 ? io_writeReq_1_bits_data[15:8] : _GEN_357) + : _GEN_357; + wire [7:0] _GEN_430 = + _T_148 + ? (_T_176 == 5'h17 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h17 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h17 ? io_writeReq_1_bits_data[15:8] : _GEN_358) + : _GEN_358; + wire [7:0] _GEN_431 = + _T_148 + ? (_T_176 == 5'h18 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h18 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h18 + ? io_writeReq_1_bits_data[15:8] + : _GEN_405 ? io_writeReq_1_bits_data[7:0] : _GEN_359) + : _GEN_359; + wire [7:0] _GEN_432 = + _T_148 + ? (_T_176 == 5'h19 + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h19 + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h19 ? io_writeReq_1_bits_data[15:8] : _GEN_360) + : _GEN_360; + wire [7:0] _GEN_433 = + _T_148 + ? (_T_176 == 5'h1A + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h1A + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h1A ? io_writeReq_1_bits_data[15:8] : _GEN_361) + : _GEN_361; + wire [7:0] _GEN_434 = + _T_148 + ? (_T_176 == 5'h1B + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h1B + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h1B ? io_writeReq_1_bits_data[15:8] : _GEN_362) + : _GEN_362; + wire [7:0] _GEN_435 = + _T_148 + ? (_T_176 == 5'h1C + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h1C + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h1C + ? io_writeReq_1_bits_data[15:8] + : (&(io_writeReq_1_bits_index[2:0])) + ? io_writeReq_1_bits_data[7:0] + : _GEN_363) + : _GEN_363; + wire [7:0] _GEN_436 = + _T_148 + ? (_T_176 == 5'h1D + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h1D + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h1D ? io_writeReq_1_bits_data[15:8] : _GEN_364) + : _GEN_364; + wire [7:0] _GEN_437 = + _T_148 + ? (_T_176 == 5'h1E + ? io_writeReq_1_bits_data[31:24] + : _T_168 == 5'h1E + ? io_writeReq_1_bits_data[23:16] + : _T_160 == 5'h1E ? io_writeReq_1_bits_data[15:8] : _GEN_365) + : _GEN_365; + wire [7:0] _GEN_438 = + _T_148 + ? ((&_T_176) + ? io_writeReq_1_bits_data[31:24] + : (&_T_168) + ? io_writeReq_1_bits_data[23:16] + : (&_T_160) ? io_writeReq_1_bits_data[15:8] : _GEN_366) + : _GEN_366; + wire [4:0] _T_180 = _GEN_406 + 5'h3; + wire _T_181 = io_writeReq_1_bits_vtype_vsew == 3'h3; + wire _GEN_439 = io_writeReq_1_bits_index[1:0] == 2'h0; + wire _GEN_440 = io_writeReq_1_bits_index[1:0] == 2'h1; + wire _GEN_441 = io_writeReq_1_bits_index[1:0] == 2'h2; + wire [4:0] _GEN_442 = {io_writeReq_1_bits_index[1:0], 3'h0}; + wire [4:0] _T_193 = _GEN_442 + 5'h1; + wire [4:0] _T_197 = _GEN_442 + 5'h1; + wire [4:0] _T_201 = _GEN_442 + 5'h2; + wire [4:0] _T_205 = _GEN_442 + 5'h2; + wire [4:0] _T_209 = _GEN_442 + 5'h3; + wire [4:0] _T_213 = _GEN_442 + 5'h3; + wire [4:0] _T_217 = _GEN_442 + 5'h4; + wire [4:0] _T_221 = _GEN_442 + 5'h4; + wire [4:0] _T_225 = _GEN_442 + 5'h5; + wire [4:0] _T_229 = _GEN_442 + 5'h5; + wire [4:0] _T_233 = _GEN_442 + 5'h6; + wire [4:0] _T_237 = _GEN_442 + 5'h6; + wire [4:0] _T_241 = _GEN_442 + 5'h7; + assign internalWriteData_1_0 = + _T_181 + ? (_T_241 == 5'h0 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h0 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h0 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h0 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h0 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h0 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h0 + ? io_writeReq_1_bits_data[15:8] + : _GEN_439 ? io_writeReq_1_bits_data[7:0] : _GEN_407) + : _GEN_407; + assign internalWriteData_1_1 = + _T_181 + ? (_T_241 == 5'h1 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h1 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h1 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h1 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h1 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h1 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h1 + ? io_writeReq_1_bits_data[15:8] + : _GEN_408) + : _GEN_408; + assign internalWriteData_1_2 = + _T_181 + ? (_T_241 == 5'h2 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h2 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h2 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h2 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h2 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h2 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h2 + ? io_writeReq_1_bits_data[15:8] + : _GEN_409) + : _GEN_409; + assign internalWriteData_1_3 = + _T_181 + ? (_T_241 == 5'h3 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h3 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h3 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h3 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h3 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h3 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h3 + ? io_writeReq_1_bits_data[15:8] + : _GEN_410) + : _GEN_410; + assign internalWriteData_1_4 = + _T_181 + ? (_T_241 == 5'h4 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h4 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h4 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h4 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h4 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h4 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h4 + ? io_writeReq_1_bits_data[15:8] + : _GEN_411) + : _GEN_411; + assign internalWriteData_1_5 = + _T_181 + ? (_T_241 == 5'h5 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h5 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h5 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h5 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h5 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h5 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h5 + ? io_writeReq_1_bits_data[15:8] + : _GEN_412) + : _GEN_412; + assign internalWriteData_1_6 = + _T_181 + ? (_T_241 == 5'h6 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h6 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h6 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h6 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h6 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h6 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h6 + ? io_writeReq_1_bits_data[15:8] + : _GEN_413) + : _GEN_413; + assign internalWriteData_1_7 = + _T_181 + ? (_T_241 == 5'h7 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h7 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h7 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h7 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h7 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h7 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h7 + ? io_writeReq_1_bits_data[15:8] + : _GEN_414) + : _GEN_414; + assign internalWriteData_1_8 = + _T_181 + ? (_T_241 == 5'h8 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h8 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h8 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h8 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h8 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h8 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h8 + ? io_writeReq_1_bits_data[15:8] + : _GEN_440 ? io_writeReq_1_bits_data[7:0] : _GEN_415) + : _GEN_415; + assign internalWriteData_1_9 = + _T_181 + ? (_T_241 == 5'h9 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h9 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h9 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h9 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h9 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h9 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h9 + ? io_writeReq_1_bits_data[15:8] + : _GEN_416) + : _GEN_416; + assign internalWriteData_1_10 = + _T_181 + ? (_T_241 == 5'hA + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'hA + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'hA + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'hA + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'hA + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'hA + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'hA + ? io_writeReq_1_bits_data[15:8] + : _GEN_417) + : _GEN_417; + assign internalWriteData_1_11 = + _T_181 + ? (_T_241 == 5'hB + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'hB + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'hB + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'hB + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'hB + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'hB + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'hB + ? io_writeReq_1_bits_data[15:8] + : _GEN_418) + : _GEN_418; + assign internalWriteData_1_12 = + _T_181 + ? (_T_241 == 5'hC + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'hC + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'hC + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'hC + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'hC + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'hC + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'hC + ? io_writeReq_1_bits_data[15:8] + : _GEN_419) + : _GEN_419; + assign internalWriteData_1_13 = + _T_181 + ? (_T_241 == 5'hD + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'hD + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'hD + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'hD + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'hD + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'hD + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'hD + ? io_writeReq_1_bits_data[15:8] + : _GEN_420) + : _GEN_420; + assign internalWriteData_1_14 = + _T_181 + ? (_T_241 == 5'hE + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'hE + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'hE + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'hE + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'hE + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'hE + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'hE + ? io_writeReq_1_bits_data[15:8] + : _GEN_421) + : _GEN_421; + assign internalWriteData_1_15 = + _T_181 + ? (_T_241 == 5'hF + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'hF + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'hF + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'hF + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'hF + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'hF + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'hF + ? io_writeReq_1_bits_data[15:8] + : _GEN_422) + : _GEN_422; + assign internalWriteData_1_16 = + _T_181 + ? (_T_241 == 5'h10 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h10 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h10 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h10 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h10 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h10 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h10 + ? io_writeReq_1_bits_data[15:8] + : _GEN_441 ? io_writeReq_1_bits_data[7:0] : _GEN_423) + : _GEN_423; + assign internalWriteData_1_17 = + _T_181 + ? (_T_241 == 5'h11 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h11 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h11 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h11 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h11 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h11 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h11 + ? io_writeReq_1_bits_data[15:8] + : _GEN_424) + : _GEN_424; + assign internalWriteData_1_18 = + _T_181 + ? (_T_241 == 5'h12 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h12 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h12 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h12 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h12 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h12 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h12 + ? io_writeReq_1_bits_data[15:8] + : _GEN_425) + : _GEN_425; + assign internalWriteData_1_19 = + _T_181 + ? (_T_241 == 5'h13 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h13 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h13 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h13 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h13 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h13 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h13 + ? io_writeReq_1_bits_data[15:8] + : _GEN_426) + : _GEN_426; + assign internalWriteData_1_20 = + _T_181 + ? (_T_241 == 5'h14 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h14 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h14 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h14 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h14 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h14 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h14 + ? io_writeReq_1_bits_data[15:8] + : _GEN_427) + : _GEN_427; + assign internalWriteData_1_21 = + _T_181 + ? (_T_241 == 5'h15 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h15 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h15 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h15 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h15 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h15 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h15 + ? io_writeReq_1_bits_data[15:8] + : _GEN_428) + : _GEN_428; + assign internalWriteData_1_22 = + _T_181 + ? (_T_241 == 5'h16 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h16 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h16 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h16 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h16 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h16 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h16 + ? io_writeReq_1_bits_data[15:8] + : _GEN_429) + : _GEN_429; + assign internalWriteData_1_23 = + _T_181 + ? (_T_241 == 5'h17 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h17 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h17 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h17 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h17 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h17 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h17 + ? io_writeReq_1_bits_data[15:8] + : _GEN_430) + : _GEN_430; + assign internalWriteData_1_24 = + _T_181 + ? (_T_241 == 5'h18 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h18 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h18 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h18 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h18 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h18 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h18 + ? io_writeReq_1_bits_data[15:8] + : (&(io_writeReq_1_bits_index[1:0])) + ? io_writeReq_1_bits_data[7:0] + : _GEN_431) + : _GEN_431; + assign internalWriteData_1_25 = + _T_181 + ? (_T_241 == 5'h19 + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h19 + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h19 + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h19 + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h19 + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h19 + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h19 + ? io_writeReq_1_bits_data[15:8] + : _GEN_432) + : _GEN_432; + assign internalWriteData_1_26 = + _T_181 + ? (_T_241 == 5'h1A + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h1A + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h1A + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h1A + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h1A + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h1A + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h1A + ? io_writeReq_1_bits_data[15:8] + : _GEN_433) + : _GEN_433; + assign internalWriteData_1_27 = + _T_181 + ? (_T_241 == 5'h1B + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h1B + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h1B + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h1B + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h1B + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h1B + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h1B + ? io_writeReq_1_bits_data[15:8] + : _GEN_434) + : _GEN_434; + assign internalWriteData_1_28 = + _T_181 + ? (_T_241 == 5'h1C + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h1C + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h1C + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h1C + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h1C + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h1C + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h1C + ? io_writeReq_1_bits_data[15:8] + : _GEN_435) + : _GEN_435; + assign internalWriteData_1_29 = + _T_181 + ? (_T_241 == 5'h1D + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h1D + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h1D + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h1D + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h1D + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h1D + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h1D + ? io_writeReq_1_bits_data[15:8] + : _GEN_436) + : _GEN_436; + assign internalWriteData_1_30 = + _T_181 + ? (_T_241 == 5'h1E + ? io_writeReq_1_bits_data[63:56] + : _T_233 == 5'h1E + ? io_writeReq_1_bits_data[55:48] + : _T_225 == 5'h1E + ? io_writeReq_1_bits_data[47:40] + : _T_217 == 5'h1E + ? io_writeReq_1_bits_data[39:32] + : _T_209 == 5'h1E + ? io_writeReq_1_bits_data[31:24] + : _T_201 == 5'h1E + ? io_writeReq_1_bits_data[23:16] + : _T_193 == 5'h1E + ? io_writeReq_1_bits_data[15:8] + : _GEN_437) + : _GEN_437; + assign internalWriteData_1_31 = + _T_181 + ? ((&_T_241) + ? io_writeReq_1_bits_data[63:56] + : (&_T_233) + ? io_writeReq_1_bits_data[55:48] + : (&_T_225) + ? io_writeReq_1_bits_data[47:40] + : (&_T_217) + ? io_writeReq_1_bits_data[39:32] + : (&_T_209) + ? io_writeReq_1_bits_data[31:24] + : (&_T_201) + ? io_writeReq_1_bits_data[23:16] + : (&_T_193) ? io_writeReq_1_bits_data[15:8] : _GEN_438) + : _GEN_438; + wire [4:0] _T_245 = _GEN_442 + 5'h7; + assign internalWriteMask_1_0 = + _T_181 + & (_T_245 == 5'h0 | _T_237 == 5'h0 | _T_229 == 5'h0 | _T_221 == 5'h0 | _T_213 == 5'h0 + | _T_205 == 5'h0 | _T_197 == 5'h0 | _GEN_439) + | (_T_148 + ? _T_180 == 5'h0 | _T_172 == 5'h0 | _T_164 == 5'h0 | _GEN_399 | _GEN_367 + | _GEN_287 + : _GEN_367 | _GEN_287); + assign internalWriteMask_1_1 = + _T_181 + & (_T_245 == 5'h1 | _T_237 == 5'h1 | _T_229 == 5'h1 | _T_221 == 5'h1 | _T_213 == 5'h1 + | _T_205 == 5'h1 | _T_197 == 5'h1) + | (_T_148 + ? _T_180 == 5'h1 | _T_172 == 5'h1 | _T_164 == 5'h1 | _GEN_368 | _GEN_288 + : _GEN_368 | _GEN_288); + assign internalWriteMask_1_2 = + _T_181 + & (_T_245 == 5'h2 | _T_237 == 5'h2 | _T_229 == 5'h2 | _T_221 == 5'h2 | _T_213 == 5'h2 + | _T_205 == 5'h2 | _T_197 == 5'h2) + | (_T_148 + ? _T_180 == 5'h2 | _T_172 == 5'h2 | _T_164 == 5'h2 | _GEN_369 | _GEN_289 + : _GEN_369 | _GEN_289); + assign internalWriteMask_1_3 = + _T_181 + & (_T_245 == 5'h3 | _T_237 == 5'h3 | _T_229 == 5'h3 | _T_221 == 5'h3 | _T_213 == 5'h3 + | _T_205 == 5'h3 | _T_197 == 5'h3) + | (_T_148 + ? _T_180 == 5'h3 | _T_172 == 5'h3 | _T_164 == 5'h3 | _GEN_370 | _GEN_290 + : _GEN_370 | _GEN_290); + assign internalWriteMask_1_4 = + _T_181 + & (_T_245 == 5'h4 | _T_237 == 5'h4 | _T_229 == 5'h4 | _T_221 == 5'h4 | _T_213 == 5'h4 + | _T_205 == 5'h4 | _T_197 == 5'h4) + | (_T_148 + ? _T_180 == 5'h4 | _T_172 == 5'h4 | _T_164 == 5'h4 | _GEN_400 | _GEN_371 + | _GEN_291 + : _GEN_371 | _GEN_291); + assign internalWriteMask_1_5 = + _T_181 + & (_T_245 == 5'h5 | _T_237 == 5'h5 | _T_229 == 5'h5 | _T_221 == 5'h5 | _T_213 == 5'h5 + | _T_205 == 5'h5 | _T_197 == 5'h5) + | (_T_148 + ? _T_180 == 5'h5 | _T_172 == 5'h5 | _T_164 == 5'h5 | _GEN_372 | _GEN_292 + : _GEN_372 | _GEN_292); + assign internalWriteMask_1_6 = + _T_181 + & (_T_245 == 5'h6 | _T_237 == 5'h6 | _T_229 == 5'h6 | _T_221 == 5'h6 | _T_213 == 5'h6 + | _T_205 == 5'h6 | _T_197 == 5'h6) + | (_T_148 + ? _T_180 == 5'h6 | _T_172 == 5'h6 | _T_164 == 5'h6 | _GEN_373 | _GEN_293 + : _GEN_373 | _GEN_293); + assign internalWriteMask_1_7 = + _T_181 + & (_T_245 == 5'h7 | _T_237 == 5'h7 | _T_229 == 5'h7 | _T_221 == 5'h7 | _T_213 == 5'h7 + | _T_205 == 5'h7 | _T_197 == 5'h7) + | (_T_148 + ? _T_180 == 5'h7 | _T_172 == 5'h7 | _T_164 == 5'h7 | _GEN_374 | _GEN_294 + : _GEN_374 | _GEN_294); + assign internalWriteMask_1_8 = + _T_181 + & (_T_245 == 5'h8 | _T_237 == 5'h8 | _T_229 == 5'h8 | _T_221 == 5'h8 | _T_213 == 5'h8 + | _T_205 == 5'h8 | _T_197 == 5'h8 | _GEN_440) + | (_T_148 + ? _T_180 == 5'h8 | _T_172 == 5'h8 | _T_164 == 5'h8 | _GEN_401 | _GEN_375 + | _GEN_295 + : _GEN_375 | _GEN_295); + assign internalWriteMask_1_9 = + _T_181 + & (_T_245 == 5'h9 | _T_237 == 5'h9 | _T_229 == 5'h9 | _T_221 == 5'h9 | _T_213 == 5'h9 + | _T_205 == 5'h9 | _T_197 == 5'h9) + | (_T_148 + ? _T_180 == 5'h9 | _T_172 == 5'h9 | _T_164 == 5'h9 | _GEN_376 | _GEN_296 + : _GEN_376 | _GEN_296); + assign internalWriteMask_1_10 = + _T_181 + & (_T_245 == 5'hA | _T_237 == 5'hA | _T_229 == 5'hA | _T_221 == 5'hA | _T_213 == 5'hA + | _T_205 == 5'hA | _T_197 == 5'hA) + | (_T_148 + ? _T_180 == 5'hA | _T_172 == 5'hA | _T_164 == 5'hA | _GEN_377 | _GEN_297 + : _GEN_377 | _GEN_297); + assign internalWriteMask_1_11 = + _T_181 + & (_T_245 == 5'hB | _T_237 == 5'hB | _T_229 == 5'hB | _T_221 == 5'hB | _T_213 == 5'hB + | _T_205 == 5'hB | _T_197 == 5'hB) + | (_T_148 + ? _T_180 == 5'hB | _T_172 == 5'hB | _T_164 == 5'hB | _GEN_378 | _GEN_298 + : _GEN_378 | _GEN_298); + assign internalWriteMask_1_12 = + _T_181 + & (_T_245 == 5'hC | _T_237 == 5'hC | _T_229 == 5'hC | _T_221 == 5'hC | _T_213 == 5'hC + | _T_205 == 5'hC | _T_197 == 5'hC) + | (_T_148 + ? _T_180 == 5'hC | _T_172 == 5'hC | _T_164 == 5'hC | _GEN_402 | _GEN_379 + | _GEN_299 + : _GEN_379 | _GEN_299); + assign internalWriteMask_1_13 = + _T_181 + & (_T_245 == 5'hD | _T_237 == 5'hD | _T_229 == 5'hD | _T_221 == 5'hD | _T_213 == 5'hD + | _T_205 == 5'hD | _T_197 == 5'hD) + | (_T_148 + ? _T_180 == 5'hD | _T_172 == 5'hD | _T_164 == 5'hD | _GEN_380 | _GEN_300 + : _GEN_380 | _GEN_300); + assign internalWriteMask_1_14 = + _T_181 + & (_T_245 == 5'hE | _T_237 == 5'hE | _T_229 == 5'hE | _T_221 == 5'hE | _T_213 == 5'hE + | _T_205 == 5'hE | _T_197 == 5'hE) + | (_T_148 + ? _T_180 == 5'hE | _T_172 == 5'hE | _T_164 == 5'hE | _GEN_381 | _GEN_301 + : _GEN_381 | _GEN_301); + assign internalWriteMask_1_15 = + _T_181 + & (_T_245 == 5'hF | _T_237 == 5'hF | _T_229 == 5'hF | _T_221 == 5'hF | _T_213 == 5'hF + | _T_205 == 5'hF | _T_197 == 5'hF) + | (_T_148 + ? _T_180 == 5'hF | _T_172 == 5'hF | _T_164 == 5'hF | _GEN_382 | _GEN_302 + : _GEN_382 | _GEN_302); + assign internalWriteMask_1_16 = + _T_181 + & (_T_245 == 5'h10 | _T_237 == 5'h10 | _T_229 == 5'h10 | _T_221 == 5'h10 + | _T_213 == 5'h10 | _T_205 == 5'h10 | _T_197 == 5'h10 | _GEN_441) + | (_T_148 + ? _T_180 == 5'h10 | _T_172 == 5'h10 | _T_164 == 5'h10 | _GEN_403 | _GEN_383 + | _GEN_303 + : _GEN_383 | _GEN_303); + assign internalWriteMask_1_17 = + _T_181 + & (_T_245 == 5'h11 | _T_237 == 5'h11 | _T_229 == 5'h11 | _T_221 == 5'h11 + | _T_213 == 5'h11 | _T_205 == 5'h11 | _T_197 == 5'h11) + | (_T_148 + ? _T_180 == 5'h11 | _T_172 == 5'h11 | _T_164 == 5'h11 | _GEN_384 | _GEN_304 + : _GEN_384 | _GEN_304); + assign internalWriteMask_1_18 = + _T_181 + & (_T_245 == 5'h12 | _T_237 == 5'h12 | _T_229 == 5'h12 | _T_221 == 5'h12 + | _T_213 == 5'h12 | _T_205 == 5'h12 | _T_197 == 5'h12) + | (_T_148 + ? _T_180 == 5'h12 | _T_172 == 5'h12 | _T_164 == 5'h12 | _GEN_385 | _GEN_305 + : _GEN_385 | _GEN_305); + assign internalWriteMask_1_19 = + _T_181 + & (_T_245 == 5'h13 | _T_237 == 5'h13 | _T_229 == 5'h13 | _T_221 == 5'h13 + | _T_213 == 5'h13 | _T_205 == 5'h13 | _T_197 == 5'h13) + | (_T_148 + ? _T_180 == 5'h13 | _T_172 == 5'h13 | _T_164 == 5'h13 | _GEN_386 | _GEN_306 + : _GEN_386 | _GEN_306); + assign internalWriteMask_1_20 = + _T_181 + & (_T_245 == 5'h14 | _T_237 == 5'h14 | _T_229 == 5'h14 | _T_221 == 5'h14 + | _T_213 == 5'h14 | _T_205 == 5'h14 | _T_197 == 5'h14) + | (_T_148 + ? _T_180 == 5'h14 | _T_172 == 5'h14 | _T_164 == 5'h14 | _GEN_404 | _GEN_387 + | _GEN_307 + : _GEN_387 | _GEN_307); + assign internalWriteMask_1_21 = + _T_181 + & (_T_245 == 5'h15 | _T_237 == 5'h15 | _T_229 == 5'h15 | _T_221 == 5'h15 + | _T_213 == 5'h15 | _T_205 == 5'h15 | _T_197 == 5'h15) + | (_T_148 + ? _T_180 == 5'h15 | _T_172 == 5'h15 | _T_164 == 5'h15 | _GEN_388 | _GEN_308 + : _GEN_388 | _GEN_308); + assign internalWriteMask_1_22 = + _T_181 + & (_T_245 == 5'h16 | _T_237 == 5'h16 | _T_229 == 5'h16 | _T_221 == 5'h16 + | _T_213 == 5'h16 | _T_205 == 5'h16 | _T_197 == 5'h16) + | (_T_148 + ? _T_180 == 5'h16 | _T_172 == 5'h16 | _T_164 == 5'h16 | _GEN_389 | _GEN_309 + : _GEN_389 | _GEN_309); + assign internalWriteMask_1_23 = + _T_181 + & (_T_245 == 5'h17 | _T_237 == 5'h17 | _T_229 == 5'h17 | _T_221 == 5'h17 + | _T_213 == 5'h17 | _T_205 == 5'h17 | _T_197 == 5'h17) + | (_T_148 + ? _T_180 == 5'h17 | _T_172 == 5'h17 | _T_164 == 5'h17 | _GEN_390 | _GEN_310 + : _GEN_390 | _GEN_310); + assign internalWriteMask_1_24 = + _T_181 + & (_T_245 == 5'h18 | _T_237 == 5'h18 | _T_229 == 5'h18 | _T_221 == 5'h18 + | _T_213 == 5'h18 | _T_205 == 5'h18 | _T_197 == 5'h18 + | (&(io_writeReq_1_bits_index[1:0]))) + | (_T_148 + ? _T_180 == 5'h18 | _T_172 == 5'h18 | _T_164 == 5'h18 | _GEN_405 | _GEN_391 + | _GEN_311 + : _GEN_391 | _GEN_311); + assign internalWriteMask_1_25 = + _T_181 + & (_T_245 == 5'h19 | _T_237 == 5'h19 | _T_229 == 5'h19 | _T_221 == 5'h19 + | _T_213 == 5'h19 | _T_205 == 5'h19 | _T_197 == 5'h19) + | (_T_148 + ? _T_180 == 5'h19 | _T_172 == 5'h19 | _T_164 == 5'h19 | _GEN_392 | _GEN_312 + : _GEN_392 | _GEN_312); + assign internalWriteMask_1_26 = + _T_181 + & (_T_245 == 5'h1A | _T_237 == 5'h1A | _T_229 == 5'h1A | _T_221 == 5'h1A + | _T_213 == 5'h1A | _T_205 == 5'h1A | _T_197 == 5'h1A) + | (_T_148 + ? _T_180 == 5'h1A | _T_172 == 5'h1A | _T_164 == 5'h1A | _GEN_393 | _GEN_313 + : _GEN_393 | _GEN_313); + assign internalWriteMask_1_27 = + _T_181 + & (_T_245 == 5'h1B | _T_237 == 5'h1B | _T_229 == 5'h1B | _T_221 == 5'h1B + | _T_213 == 5'h1B | _T_205 == 5'h1B | _T_197 == 5'h1B) + | (_T_148 + ? _T_180 == 5'h1B | _T_172 == 5'h1B | _T_164 == 5'h1B | _GEN_394 | _GEN_314 + : _GEN_394 | _GEN_314); + assign internalWriteMask_1_28 = + _T_181 + & (_T_245 == 5'h1C | _T_237 == 5'h1C | _T_229 == 5'h1C | _T_221 == 5'h1C + | _T_213 == 5'h1C | _T_205 == 5'h1C | _T_197 == 5'h1C) + | (_T_148 + ? _T_180 == 5'h1C | _T_172 == 5'h1C | _T_164 == 5'h1C + | (&(io_writeReq_1_bits_index[2:0])) | _GEN_395 | _GEN_315 + : _GEN_395 | _GEN_315); + assign internalWriteMask_1_29 = + _T_181 + & (_T_245 == 5'h1D | _T_237 == 5'h1D | _T_229 == 5'h1D | _T_221 == 5'h1D + | _T_213 == 5'h1D | _T_205 == 5'h1D | _T_197 == 5'h1D) + | (_T_148 + ? _T_180 == 5'h1D | _T_172 == 5'h1D | _T_164 == 5'h1D | _GEN_396 | _GEN_316 + : _GEN_396 | _GEN_316); + assign internalWriteMask_1_30 = + _T_181 + & (_T_245 == 5'h1E | _T_237 == 5'h1E | _T_229 == 5'h1E | _T_221 == 5'h1E + | _T_213 == 5'h1E | _T_205 == 5'h1E | _T_197 == 5'h1E) + | (_T_148 + ? _T_180 == 5'h1E | _T_172 == 5'h1E | _T_164 == 5'h1E | _GEN_397 | _GEN_317 + : _GEN_397 | _GEN_317); + assign internalWriteMask_1_31 = + _T_181 + & ((&_T_245) | (&_T_237) | (&_T_229) | (&_T_221) | (&_T_213) | (&_T_205) | (&_T_197)) + | (_T_148 + ? (&_T_180) | (&_T_172) | (&_T_164) | _GEN_398 | _GEN_318 + : _GEN_398 | _GEN_318); + wire _T_247 = io_writeReq_2_bits_vtype_vsew == 3'h0; + wire _GEN_443 = io_writeReq_2_bits_index == 5'h0; + wire [7:0] _GEN_444 = _T_247 & _GEN_443 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire _GEN_445 = io_writeReq_2_bits_index == 5'h1; + wire _GEN_446 = io_writeReq_2_bits_index == 5'h2; + wire [7:0] _GEN_447 = _T_247 & _GEN_446 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire _GEN_448 = io_writeReq_2_bits_index == 5'h3; + wire _GEN_449 = io_writeReq_2_bits_index == 5'h4; + wire [7:0] _GEN_450 = _T_247 & _GEN_449 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire _GEN_451 = io_writeReq_2_bits_index == 5'h5; + wire _GEN_452 = io_writeReq_2_bits_index == 5'h6; + wire [7:0] _GEN_453 = _T_247 & _GEN_452 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire _GEN_454 = io_writeReq_2_bits_index == 5'h7; + wire _GEN_455 = io_writeReq_2_bits_index == 5'h8; + wire [7:0] _GEN_456 = _T_247 & _GEN_455 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire _GEN_457 = io_writeReq_2_bits_index == 5'h9; + wire _GEN_458 = io_writeReq_2_bits_index == 5'hA; + wire [7:0] _GEN_459 = _T_247 & _GEN_458 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire _GEN_460 = io_writeReq_2_bits_index == 5'hB; + wire _GEN_461 = io_writeReq_2_bits_index == 5'hC; + wire [7:0] _GEN_462 = _T_247 & _GEN_461 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire _GEN_463 = io_writeReq_2_bits_index == 5'hD; + wire _GEN_464 = io_writeReq_2_bits_index == 5'hE; + wire [7:0] _GEN_465 = _T_247 & _GEN_464 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire _GEN_466 = io_writeReq_2_bits_index == 5'hF; + wire _GEN_467 = io_writeReq_2_bits_index == 5'h10; + wire [7:0] _GEN_468 = _T_247 & _GEN_467 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire _GEN_469 = io_writeReq_2_bits_index == 5'h11; + wire _GEN_470 = io_writeReq_2_bits_index == 5'h12; + wire [7:0] _GEN_471 = _T_247 & _GEN_470 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire _GEN_472 = io_writeReq_2_bits_index == 5'h13; + wire _GEN_473 = io_writeReq_2_bits_index == 5'h14; + wire [7:0] _GEN_474 = _T_247 & _GEN_473 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire _GEN_475 = io_writeReq_2_bits_index == 5'h15; + wire _GEN_476 = io_writeReq_2_bits_index == 5'h16; + wire [7:0] _GEN_477 = _T_247 & _GEN_476 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire _GEN_478 = io_writeReq_2_bits_index == 5'h17; + wire _GEN_479 = io_writeReq_2_bits_index == 5'h18; + wire [7:0] _GEN_480 = _T_247 & _GEN_479 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire _GEN_481 = io_writeReq_2_bits_index == 5'h19; + wire _GEN_482 = io_writeReq_2_bits_index == 5'h1A; + wire [7:0] _GEN_483 = _T_247 & _GEN_482 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire _GEN_484 = io_writeReq_2_bits_index == 5'h1B; + wire _GEN_485 = io_writeReq_2_bits_index == 5'h1C; + wire [7:0] _GEN_486 = _T_247 & _GEN_485 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire _GEN_487 = io_writeReq_2_bits_index == 5'h1D; + wire _GEN_488 = io_writeReq_2_bits_index == 5'h1E; + wire [7:0] _GEN_489 = _T_247 & _GEN_488 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire _GEN_490 = _T_247 & _GEN_443; + wire _GEN_491 = _T_247 & _GEN_445; + wire _GEN_492 = _T_247 & _GEN_446; + wire _GEN_493 = _T_247 & _GEN_448; + wire _GEN_494 = _T_247 & _GEN_449; + wire _GEN_495 = _T_247 & _GEN_451; + wire _GEN_496 = _T_247 & _GEN_452; + wire _GEN_497 = _T_247 & _GEN_454; + wire _GEN_498 = _T_247 & _GEN_455; + wire _GEN_499 = _T_247 & _GEN_457; + wire _GEN_500 = _T_247 & _GEN_458; + wire _GEN_501 = _T_247 & _GEN_460; + wire _GEN_502 = _T_247 & _GEN_461; + wire _GEN_503 = _T_247 & _GEN_463; + wire _GEN_504 = _T_247 & _GEN_464; + wire _GEN_505 = _T_247 & _GEN_466; + wire _GEN_506 = _T_247 & _GEN_467; + wire _GEN_507 = _T_247 & _GEN_469; + wire _GEN_508 = _T_247 & _GEN_470; + wire _GEN_509 = _T_247 & _GEN_472; + wire _GEN_510 = _T_247 & _GEN_473; + wire _GEN_511 = _T_247 & _GEN_475; + wire _GEN_512 = _T_247 & _GEN_476; + wire _GEN_513 = _T_247 & _GEN_478; + wire _GEN_514 = _T_247 & _GEN_479; + wire _GEN_515 = _T_247 & _GEN_481; + wire _GEN_516 = _T_247 & _GEN_482; + wire _GEN_517 = _T_247 & _GEN_484; + wire _GEN_518 = _T_247 & _GEN_485; + wire _GEN_519 = _T_247 & _GEN_487; + wire _GEN_520 = _T_247 & _GEN_488; + wire _GEN_521 = _T_247 & (&io_writeReq_2_bits_index); + wire _T_254 = io_writeReq_2_bits_vtype_vsew == 3'h1; + wire _GEN_522 = io_writeReq_2_bits_index[3:0] == 4'h0; + wire _GEN_523 = io_writeReq_2_bits_index[3:0] == 4'h1; + wire _GEN_524 = io_writeReq_2_bits_index[3:0] == 4'h2; + wire _GEN_525 = io_writeReq_2_bits_index[3:0] == 4'h3; + wire _GEN_526 = io_writeReq_2_bits_index[3:0] == 4'h4; + wire _GEN_527 = io_writeReq_2_bits_index[3:0] == 4'h5; + wire _GEN_528 = io_writeReq_2_bits_index[3:0] == 4'h6; + wire _GEN_529 = io_writeReq_2_bits_index[3:0] == 4'h7; + wire _GEN_530 = io_writeReq_2_bits_index[3:0] == 4'h8; + wire _GEN_531 = io_writeReq_2_bits_index[3:0] == 4'h9; + wire _GEN_532 = io_writeReq_2_bits_index[3:0] == 4'hA; + wire _GEN_533 = io_writeReq_2_bits_index[3:0] == 4'hB; + wire _GEN_534 = io_writeReq_2_bits_index[3:0] == 4'hC; + wire _GEN_535 = io_writeReq_2_bits_index[3:0] == 4'hD; + wire _GEN_536 = io_writeReq_2_bits_index[3:0] == 4'hE; + wire [4:0] _GEN_537 = {io_writeReq_2_bits_index[3:0], 1'h0}; + wire [4:0] _T_266 = _GEN_537 + 5'h1; + wire [7:0] _GEN_538 = + _T_254 + ? (_T_266 == 5'h0 + ? io_writeReq_2_bits_data[15:8] + : _GEN_522 ? io_writeReq_2_bits_data[7:0] : _GEN_444) + : _GEN_444; + wire [7:0] _GEN_539 = + _T_254 & _T_266 == 5'h1 + ? io_writeReq_2_bits_data[15:8] + : _T_247 & _GEN_445 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_540 = + _T_254 + ? (_T_266 == 5'h2 + ? io_writeReq_2_bits_data[15:8] + : _GEN_523 ? io_writeReq_2_bits_data[7:0] : _GEN_447) + : _GEN_447; + wire [7:0] _GEN_541 = + _T_254 & _T_266 == 5'h3 + ? io_writeReq_2_bits_data[15:8] + : _T_247 & _GEN_448 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_542 = + _T_254 + ? (_T_266 == 5'h4 + ? io_writeReq_2_bits_data[15:8] + : _GEN_524 ? io_writeReq_2_bits_data[7:0] : _GEN_450) + : _GEN_450; + wire [7:0] _GEN_543 = + _T_254 & _T_266 == 5'h5 + ? io_writeReq_2_bits_data[15:8] + : _T_247 & _GEN_451 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_544 = + _T_254 + ? (_T_266 == 5'h6 + ? io_writeReq_2_bits_data[15:8] + : _GEN_525 ? io_writeReq_2_bits_data[7:0] : _GEN_453) + : _GEN_453; + wire [7:0] _GEN_545 = + _T_254 & _T_266 == 5'h7 + ? io_writeReq_2_bits_data[15:8] + : _T_247 & _GEN_454 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_546 = + _T_254 + ? (_T_266 == 5'h8 + ? io_writeReq_2_bits_data[15:8] + : _GEN_526 ? io_writeReq_2_bits_data[7:0] : _GEN_456) + : _GEN_456; + wire [7:0] _GEN_547 = + _T_254 & _T_266 == 5'h9 + ? io_writeReq_2_bits_data[15:8] + : _T_247 & _GEN_457 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_548 = + _T_254 + ? (_T_266 == 5'hA + ? io_writeReq_2_bits_data[15:8] + : _GEN_527 ? io_writeReq_2_bits_data[7:0] : _GEN_459) + : _GEN_459; + wire [7:0] _GEN_549 = + _T_254 & _T_266 == 5'hB + ? io_writeReq_2_bits_data[15:8] + : _T_247 & _GEN_460 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_550 = + _T_254 + ? (_T_266 == 5'hC + ? io_writeReq_2_bits_data[15:8] + : _GEN_528 ? io_writeReq_2_bits_data[7:0] : _GEN_462) + : _GEN_462; + wire [7:0] _GEN_551 = + _T_254 & _T_266 == 5'hD + ? io_writeReq_2_bits_data[15:8] + : _T_247 & _GEN_463 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_552 = + _T_254 + ? (_T_266 == 5'hE + ? io_writeReq_2_bits_data[15:8] + : _GEN_529 ? io_writeReq_2_bits_data[7:0] : _GEN_465) + : _GEN_465; + wire [7:0] _GEN_553 = + _T_254 & _T_266 == 5'hF + ? io_writeReq_2_bits_data[15:8] + : _T_247 & _GEN_466 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_554 = + _T_254 + ? (_T_266 == 5'h10 + ? io_writeReq_2_bits_data[15:8] + : _GEN_530 ? io_writeReq_2_bits_data[7:0] : _GEN_468) + : _GEN_468; + wire [7:0] _GEN_555 = + _T_254 & _T_266 == 5'h11 + ? io_writeReq_2_bits_data[15:8] + : _T_247 & _GEN_469 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_556 = + _T_254 + ? (_T_266 == 5'h12 + ? io_writeReq_2_bits_data[15:8] + : _GEN_531 ? io_writeReq_2_bits_data[7:0] : _GEN_471) + : _GEN_471; + wire [7:0] _GEN_557 = + _T_254 & _T_266 == 5'h13 + ? io_writeReq_2_bits_data[15:8] + : _T_247 & _GEN_472 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_558 = + _T_254 + ? (_T_266 == 5'h14 + ? io_writeReq_2_bits_data[15:8] + : _GEN_532 ? io_writeReq_2_bits_data[7:0] : _GEN_474) + : _GEN_474; + wire [7:0] _GEN_559 = + _T_254 & _T_266 == 5'h15 + ? io_writeReq_2_bits_data[15:8] + : _T_247 & _GEN_475 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_560 = + _T_254 + ? (_T_266 == 5'h16 + ? io_writeReq_2_bits_data[15:8] + : _GEN_533 ? io_writeReq_2_bits_data[7:0] : _GEN_477) + : _GEN_477; + wire [7:0] _GEN_561 = + _T_254 & _T_266 == 5'h17 + ? io_writeReq_2_bits_data[15:8] + : _T_247 & _GEN_478 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_562 = + _T_254 + ? (_T_266 == 5'h18 + ? io_writeReq_2_bits_data[15:8] + : _GEN_534 ? io_writeReq_2_bits_data[7:0] : _GEN_480) + : _GEN_480; + wire [7:0] _GEN_563 = + _T_254 & _T_266 == 5'h19 + ? io_writeReq_2_bits_data[15:8] + : _T_247 & _GEN_481 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_564 = + _T_254 + ? (_T_266 == 5'h1A + ? io_writeReq_2_bits_data[15:8] + : _GEN_535 ? io_writeReq_2_bits_data[7:0] : _GEN_483) + : _GEN_483; + wire [7:0] _GEN_565 = + _T_254 & _T_266 == 5'h1B + ? io_writeReq_2_bits_data[15:8] + : _T_247 & _GEN_484 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_566 = + _T_254 + ? (_T_266 == 5'h1C + ? io_writeReq_2_bits_data[15:8] + : _GEN_536 ? io_writeReq_2_bits_data[7:0] : _GEN_486) + : _GEN_486; + wire [7:0] _GEN_567 = + _T_254 & _T_266 == 5'h1D + ? io_writeReq_2_bits_data[15:8] + : _T_247 & _GEN_487 ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire [7:0] _GEN_568 = + _T_254 + ? (_T_266 == 5'h1E + ? io_writeReq_2_bits_data[15:8] + : (&(io_writeReq_2_bits_index[3:0])) ? io_writeReq_2_bits_data[7:0] : _GEN_489) + : _GEN_489; + wire [7:0] _GEN_569 = + _T_254 & (&_T_266) + ? io_writeReq_2_bits_data[15:8] + : _T_247 & (&io_writeReq_2_bits_index) ? io_writeReq_2_bits_data[7:0] : 8'h0; + wire [4:0] _T_270 = _GEN_537 + 5'h1; + wire _GEN_570 = _T_254 & (_T_270 == 5'h0 | _GEN_522); + wire _GEN_571 = _T_254 & _T_270 == 5'h1; + wire _GEN_572 = _T_254 & (_T_270 == 5'h2 | _GEN_523); + wire _GEN_573 = _T_254 & _T_270 == 5'h3; + wire _GEN_574 = _T_254 & (_T_270 == 5'h4 | _GEN_524); + wire _GEN_575 = _T_254 & _T_270 == 5'h5; + wire _GEN_576 = _T_254 & (_T_270 == 5'h6 | _GEN_525); + wire _GEN_577 = _T_254 & _T_270 == 5'h7; + wire _GEN_578 = _T_254 & (_T_270 == 5'h8 | _GEN_526); + wire _GEN_579 = _T_254 & _T_270 == 5'h9; + wire _GEN_580 = _T_254 & (_T_270 == 5'hA | _GEN_527); + wire _GEN_581 = _T_254 & _T_270 == 5'hB; + wire _GEN_582 = _T_254 & (_T_270 == 5'hC | _GEN_528); + wire _GEN_583 = _T_254 & _T_270 == 5'hD; + wire _GEN_584 = _T_254 & (_T_270 == 5'hE | _GEN_529); + wire _GEN_585 = _T_254 & _T_270 == 5'hF; + wire _GEN_586 = _T_254 & (_T_270 == 5'h10 | _GEN_530); + wire _GEN_587 = _T_254 & _T_270 == 5'h11; + wire _GEN_588 = _T_254 & (_T_270 == 5'h12 | _GEN_531); + wire _GEN_589 = _T_254 & _T_270 == 5'h13; + wire _GEN_590 = _T_254 & (_T_270 == 5'h14 | _GEN_532); + wire _GEN_591 = _T_254 & _T_270 == 5'h15; + wire _GEN_592 = _T_254 & (_T_270 == 5'h16 | _GEN_533); + wire _GEN_593 = _T_254 & _T_270 == 5'h17; + wire _GEN_594 = _T_254 & (_T_270 == 5'h18 | _GEN_534); + wire _GEN_595 = _T_254 & _T_270 == 5'h19; + wire _GEN_596 = _T_254 & (_T_270 == 5'h1A | _GEN_535); + wire _GEN_597 = _T_254 & _T_270 == 5'h1B; + wire _GEN_598 = _T_254 & (_T_270 == 5'h1C | _GEN_536); + wire _GEN_599 = _T_254 & _T_270 == 5'h1D; + wire _GEN_600 = + _T_254 & (_T_270 == 5'h1E | (&(io_writeReq_2_bits_index[3:0]))); + wire _GEN_601 = _T_254 & (&_T_270); + wire _T_271 = io_writeReq_2_bits_vtype_vsew == 3'h2; + wire _GEN_602 = io_writeReq_2_bits_index[2:0] == 3'h0; + wire _GEN_603 = io_writeReq_2_bits_index[2:0] == 3'h1; + wire _GEN_604 = io_writeReq_2_bits_index[2:0] == 3'h2; + wire _GEN_605 = io_writeReq_2_bits_index[2:0] == 3'h3; + wire _GEN_606 = io_writeReq_2_bits_index[2:0] == 3'h4; + wire _GEN_607 = io_writeReq_2_bits_index[2:0] == 3'h5; + wire _GEN_608 = io_writeReq_2_bits_index[2:0] == 3'h6; + wire [4:0] _GEN_609 = {io_writeReq_2_bits_index[2:0], 2'h0}; + wire [4:0] _T_283 = _GEN_609 + 5'h1; + wire [4:0] _T_287 = _GEN_609 + 5'h1; + wire [4:0] _T_291 = _GEN_609 + 5'h2; + wire [4:0] _T_295 = _GEN_609 + 5'h2; + wire [4:0] _T_299 = _GEN_609 + 5'h3; + wire [7:0] _GEN_610 = + _T_271 + ? (_T_299 == 5'h0 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h0 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h0 + ? io_writeReq_2_bits_data[15:8] + : _GEN_602 ? io_writeReq_2_bits_data[7:0] : _GEN_538) + : _GEN_538; + wire [7:0] _GEN_611 = + _T_271 + ? (_T_299 == 5'h1 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h1 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h1 ? io_writeReq_2_bits_data[15:8] : _GEN_539) + : _GEN_539; + wire [7:0] _GEN_612 = + _T_271 + ? (_T_299 == 5'h2 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h2 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h2 ? io_writeReq_2_bits_data[15:8] : _GEN_540) + : _GEN_540; + wire [7:0] _GEN_613 = + _T_271 + ? (_T_299 == 5'h3 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h3 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h3 ? io_writeReq_2_bits_data[15:8] : _GEN_541) + : _GEN_541; + wire [7:0] _GEN_614 = + _T_271 + ? (_T_299 == 5'h4 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h4 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h4 + ? io_writeReq_2_bits_data[15:8] + : _GEN_603 ? io_writeReq_2_bits_data[7:0] : _GEN_542) + : _GEN_542; + wire [7:0] _GEN_615 = + _T_271 + ? (_T_299 == 5'h5 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h5 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h5 ? io_writeReq_2_bits_data[15:8] : _GEN_543) + : _GEN_543; + wire [7:0] _GEN_616 = + _T_271 + ? (_T_299 == 5'h6 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h6 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h6 ? io_writeReq_2_bits_data[15:8] : _GEN_544) + : _GEN_544; + wire [7:0] _GEN_617 = + _T_271 + ? (_T_299 == 5'h7 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h7 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h7 ? io_writeReq_2_bits_data[15:8] : _GEN_545) + : _GEN_545; + wire [7:0] _GEN_618 = + _T_271 + ? (_T_299 == 5'h8 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h8 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h8 + ? io_writeReq_2_bits_data[15:8] + : _GEN_604 ? io_writeReq_2_bits_data[7:0] : _GEN_546) + : _GEN_546; + wire [7:0] _GEN_619 = + _T_271 + ? (_T_299 == 5'h9 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h9 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h9 ? io_writeReq_2_bits_data[15:8] : _GEN_547) + : _GEN_547; + wire [7:0] _GEN_620 = + _T_271 + ? (_T_299 == 5'hA + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'hA + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'hA ? io_writeReq_2_bits_data[15:8] : _GEN_548) + : _GEN_548; + wire [7:0] _GEN_621 = + _T_271 + ? (_T_299 == 5'hB + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'hB + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'hB ? io_writeReq_2_bits_data[15:8] : _GEN_549) + : _GEN_549; + wire [7:0] _GEN_622 = + _T_271 + ? (_T_299 == 5'hC + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'hC + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'hC + ? io_writeReq_2_bits_data[15:8] + : _GEN_605 ? io_writeReq_2_bits_data[7:0] : _GEN_550) + : _GEN_550; + wire [7:0] _GEN_623 = + _T_271 + ? (_T_299 == 5'hD + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'hD + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'hD ? io_writeReq_2_bits_data[15:8] : _GEN_551) + : _GEN_551; + wire [7:0] _GEN_624 = + _T_271 + ? (_T_299 == 5'hE + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'hE + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'hE ? io_writeReq_2_bits_data[15:8] : _GEN_552) + : _GEN_552; + wire [7:0] _GEN_625 = + _T_271 + ? (_T_299 == 5'hF + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'hF + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'hF ? io_writeReq_2_bits_data[15:8] : _GEN_553) + : _GEN_553; + wire [7:0] _GEN_626 = + _T_271 + ? (_T_299 == 5'h10 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h10 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h10 + ? io_writeReq_2_bits_data[15:8] + : _GEN_606 ? io_writeReq_2_bits_data[7:0] : _GEN_554) + : _GEN_554; + wire [7:0] _GEN_627 = + _T_271 + ? (_T_299 == 5'h11 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h11 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h11 ? io_writeReq_2_bits_data[15:8] : _GEN_555) + : _GEN_555; + wire [7:0] _GEN_628 = + _T_271 + ? (_T_299 == 5'h12 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h12 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h12 ? io_writeReq_2_bits_data[15:8] : _GEN_556) + : _GEN_556; + wire [7:0] _GEN_629 = + _T_271 + ? (_T_299 == 5'h13 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h13 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h13 ? io_writeReq_2_bits_data[15:8] : _GEN_557) + : _GEN_557; + wire [7:0] _GEN_630 = + _T_271 + ? (_T_299 == 5'h14 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h14 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h14 + ? io_writeReq_2_bits_data[15:8] + : _GEN_607 ? io_writeReq_2_bits_data[7:0] : _GEN_558) + : _GEN_558; + wire [7:0] _GEN_631 = + _T_271 + ? (_T_299 == 5'h15 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h15 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h15 ? io_writeReq_2_bits_data[15:8] : _GEN_559) + : _GEN_559; + wire [7:0] _GEN_632 = + _T_271 + ? (_T_299 == 5'h16 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h16 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h16 ? io_writeReq_2_bits_data[15:8] : _GEN_560) + : _GEN_560; + wire [7:0] _GEN_633 = + _T_271 + ? (_T_299 == 5'h17 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h17 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h17 ? io_writeReq_2_bits_data[15:8] : _GEN_561) + : _GEN_561; + wire [7:0] _GEN_634 = + _T_271 + ? (_T_299 == 5'h18 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h18 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h18 + ? io_writeReq_2_bits_data[15:8] + : _GEN_608 ? io_writeReq_2_bits_data[7:0] : _GEN_562) + : _GEN_562; + wire [7:0] _GEN_635 = + _T_271 + ? (_T_299 == 5'h19 + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h19 + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h19 ? io_writeReq_2_bits_data[15:8] : _GEN_563) + : _GEN_563; + wire [7:0] _GEN_636 = + _T_271 + ? (_T_299 == 5'h1A + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h1A + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h1A ? io_writeReq_2_bits_data[15:8] : _GEN_564) + : _GEN_564; + wire [7:0] _GEN_637 = + _T_271 + ? (_T_299 == 5'h1B + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h1B + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h1B ? io_writeReq_2_bits_data[15:8] : _GEN_565) + : _GEN_565; + wire [7:0] _GEN_638 = + _T_271 + ? (_T_299 == 5'h1C + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h1C + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h1C + ? io_writeReq_2_bits_data[15:8] + : (&(io_writeReq_2_bits_index[2:0])) + ? io_writeReq_2_bits_data[7:0] + : _GEN_566) + : _GEN_566; + wire [7:0] _GEN_639 = + _T_271 + ? (_T_299 == 5'h1D + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h1D + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h1D ? io_writeReq_2_bits_data[15:8] : _GEN_567) + : _GEN_567; + wire [7:0] _GEN_640 = + _T_271 + ? (_T_299 == 5'h1E + ? io_writeReq_2_bits_data[31:24] + : _T_291 == 5'h1E + ? io_writeReq_2_bits_data[23:16] + : _T_283 == 5'h1E ? io_writeReq_2_bits_data[15:8] : _GEN_568) + : _GEN_568; + wire [7:0] _GEN_641 = + _T_271 + ? ((&_T_299) + ? io_writeReq_2_bits_data[31:24] + : (&_T_291) + ? io_writeReq_2_bits_data[23:16] + : (&_T_283) ? io_writeReq_2_bits_data[15:8] : _GEN_569) + : _GEN_569; + wire [4:0] _T_303 = _GEN_609 + 5'h3; + wire _T_304 = io_writeReq_2_bits_vtype_vsew == 3'h3; + wire _GEN_642 = io_writeReq_2_bits_index[1:0] == 2'h0; + wire _GEN_643 = io_writeReq_2_bits_index[1:0] == 2'h1; + wire _GEN_644 = io_writeReq_2_bits_index[1:0] == 2'h2; + wire [4:0] _GEN_645 = {io_writeReq_2_bits_index[1:0], 3'h0}; + wire [4:0] _T_316 = _GEN_645 + 5'h1; + wire [4:0] _T_320 = _GEN_645 + 5'h1; + wire [4:0] _T_324 = _GEN_645 + 5'h2; + wire [4:0] _T_328 = _GEN_645 + 5'h2; + wire [4:0] _T_332 = _GEN_645 + 5'h3; + wire [4:0] _T_336 = _GEN_645 + 5'h3; + wire [4:0] _T_340 = _GEN_645 + 5'h4; + wire [4:0] _T_344 = _GEN_645 + 5'h4; + wire [4:0] _T_348 = _GEN_645 + 5'h5; + wire [4:0] _T_352 = _GEN_645 + 5'h5; + wire [4:0] _T_356 = _GEN_645 + 5'h6; + wire [4:0] _T_360 = _GEN_645 + 5'h6; + wire [4:0] _T_364 = _GEN_645 + 5'h7; + assign internalWriteData_2_0 = + _T_304 + ? (_T_364 == 5'h0 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h0 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h0 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h0 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h0 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h0 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h0 + ? io_writeReq_2_bits_data[15:8] + : _GEN_642 ? io_writeReq_2_bits_data[7:0] : _GEN_610) + : _GEN_610; + assign internalWriteData_2_1 = + _T_304 + ? (_T_364 == 5'h1 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h1 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h1 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h1 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h1 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h1 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h1 + ? io_writeReq_2_bits_data[15:8] + : _GEN_611) + : _GEN_611; + assign internalWriteData_2_2 = + _T_304 + ? (_T_364 == 5'h2 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h2 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h2 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h2 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h2 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h2 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h2 + ? io_writeReq_2_bits_data[15:8] + : _GEN_612) + : _GEN_612; + assign internalWriteData_2_3 = + _T_304 + ? (_T_364 == 5'h3 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h3 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h3 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h3 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h3 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h3 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h3 + ? io_writeReq_2_bits_data[15:8] + : _GEN_613) + : _GEN_613; + assign internalWriteData_2_4 = + _T_304 + ? (_T_364 == 5'h4 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h4 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h4 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h4 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h4 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h4 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h4 + ? io_writeReq_2_bits_data[15:8] + : _GEN_614) + : _GEN_614; + assign internalWriteData_2_5 = + _T_304 + ? (_T_364 == 5'h5 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h5 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h5 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h5 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h5 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h5 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h5 + ? io_writeReq_2_bits_data[15:8] + : _GEN_615) + : _GEN_615; + assign internalWriteData_2_6 = + _T_304 + ? (_T_364 == 5'h6 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h6 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h6 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h6 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h6 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h6 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h6 + ? io_writeReq_2_bits_data[15:8] + : _GEN_616) + : _GEN_616; + assign internalWriteData_2_7 = + _T_304 + ? (_T_364 == 5'h7 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h7 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h7 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h7 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h7 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h7 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h7 + ? io_writeReq_2_bits_data[15:8] + : _GEN_617) + : _GEN_617; + assign internalWriteData_2_8 = + _T_304 + ? (_T_364 == 5'h8 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h8 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h8 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h8 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h8 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h8 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h8 + ? io_writeReq_2_bits_data[15:8] + : _GEN_643 ? io_writeReq_2_bits_data[7:0] : _GEN_618) + : _GEN_618; + assign internalWriteData_2_9 = + _T_304 + ? (_T_364 == 5'h9 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h9 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h9 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h9 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h9 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h9 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h9 + ? io_writeReq_2_bits_data[15:8] + : _GEN_619) + : _GEN_619; + assign internalWriteData_2_10 = + _T_304 + ? (_T_364 == 5'hA + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'hA + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'hA + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'hA + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'hA + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'hA + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'hA + ? io_writeReq_2_bits_data[15:8] + : _GEN_620) + : _GEN_620; + assign internalWriteData_2_11 = + _T_304 + ? (_T_364 == 5'hB + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'hB + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'hB + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'hB + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'hB + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'hB + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'hB + ? io_writeReq_2_bits_data[15:8] + : _GEN_621) + : _GEN_621; + assign internalWriteData_2_12 = + _T_304 + ? (_T_364 == 5'hC + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'hC + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'hC + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'hC + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'hC + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'hC + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'hC + ? io_writeReq_2_bits_data[15:8] + : _GEN_622) + : _GEN_622; + assign internalWriteData_2_13 = + _T_304 + ? (_T_364 == 5'hD + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'hD + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'hD + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'hD + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'hD + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'hD + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'hD + ? io_writeReq_2_bits_data[15:8] + : _GEN_623) + : _GEN_623; + assign internalWriteData_2_14 = + _T_304 + ? (_T_364 == 5'hE + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'hE + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'hE + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'hE + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'hE + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'hE + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'hE + ? io_writeReq_2_bits_data[15:8] + : _GEN_624) + : _GEN_624; + assign internalWriteData_2_15 = + _T_304 + ? (_T_364 == 5'hF + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'hF + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'hF + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'hF + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'hF + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'hF + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'hF + ? io_writeReq_2_bits_data[15:8] + : _GEN_625) + : _GEN_625; + assign internalWriteData_2_16 = + _T_304 + ? (_T_364 == 5'h10 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h10 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h10 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h10 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h10 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h10 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h10 + ? io_writeReq_2_bits_data[15:8] + : _GEN_644 ? io_writeReq_2_bits_data[7:0] : _GEN_626) + : _GEN_626; + assign internalWriteData_2_17 = + _T_304 + ? (_T_364 == 5'h11 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h11 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h11 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h11 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h11 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h11 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h11 + ? io_writeReq_2_bits_data[15:8] + : _GEN_627) + : _GEN_627; + assign internalWriteData_2_18 = + _T_304 + ? (_T_364 == 5'h12 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h12 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h12 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h12 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h12 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h12 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h12 + ? io_writeReq_2_bits_data[15:8] + : _GEN_628) + : _GEN_628; + assign internalWriteData_2_19 = + _T_304 + ? (_T_364 == 5'h13 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h13 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h13 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h13 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h13 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h13 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h13 + ? io_writeReq_2_bits_data[15:8] + : _GEN_629) + : _GEN_629; + assign internalWriteData_2_20 = + _T_304 + ? (_T_364 == 5'h14 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h14 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h14 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h14 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h14 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h14 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h14 + ? io_writeReq_2_bits_data[15:8] + : _GEN_630) + : _GEN_630; + assign internalWriteData_2_21 = + _T_304 + ? (_T_364 == 5'h15 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h15 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h15 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h15 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h15 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h15 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h15 + ? io_writeReq_2_bits_data[15:8] + : _GEN_631) + : _GEN_631; + assign internalWriteData_2_22 = + _T_304 + ? (_T_364 == 5'h16 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h16 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h16 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h16 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h16 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h16 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h16 + ? io_writeReq_2_bits_data[15:8] + : _GEN_632) + : _GEN_632; + assign internalWriteData_2_23 = + _T_304 + ? (_T_364 == 5'h17 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h17 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h17 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h17 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h17 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h17 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h17 + ? io_writeReq_2_bits_data[15:8] + : _GEN_633) + : _GEN_633; + assign internalWriteData_2_24 = + _T_304 + ? (_T_364 == 5'h18 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h18 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h18 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h18 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h18 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h18 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h18 + ? io_writeReq_2_bits_data[15:8] + : (&(io_writeReq_2_bits_index[1:0])) + ? io_writeReq_2_bits_data[7:0] + : _GEN_634) + : _GEN_634; + assign internalWriteData_2_25 = + _T_304 + ? (_T_364 == 5'h19 + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h19 + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h19 + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h19 + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h19 + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h19 + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h19 + ? io_writeReq_2_bits_data[15:8] + : _GEN_635) + : _GEN_635; + assign internalWriteData_2_26 = + _T_304 + ? (_T_364 == 5'h1A + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h1A + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h1A + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h1A + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h1A + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h1A + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h1A + ? io_writeReq_2_bits_data[15:8] + : _GEN_636) + : _GEN_636; + assign internalWriteData_2_27 = + _T_304 + ? (_T_364 == 5'h1B + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h1B + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h1B + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h1B + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h1B + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h1B + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h1B + ? io_writeReq_2_bits_data[15:8] + : _GEN_637) + : _GEN_637; + assign internalWriteData_2_28 = + _T_304 + ? (_T_364 == 5'h1C + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h1C + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h1C + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h1C + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h1C + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h1C + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h1C + ? io_writeReq_2_bits_data[15:8] + : _GEN_638) + : _GEN_638; + assign internalWriteData_2_29 = + _T_304 + ? (_T_364 == 5'h1D + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h1D + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h1D + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h1D + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h1D + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h1D + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h1D + ? io_writeReq_2_bits_data[15:8] + : _GEN_639) + : _GEN_639; + assign internalWriteData_2_30 = + _T_304 + ? (_T_364 == 5'h1E + ? io_writeReq_2_bits_data[63:56] + : _T_356 == 5'h1E + ? io_writeReq_2_bits_data[55:48] + : _T_348 == 5'h1E + ? io_writeReq_2_bits_data[47:40] + : _T_340 == 5'h1E + ? io_writeReq_2_bits_data[39:32] + : _T_332 == 5'h1E + ? io_writeReq_2_bits_data[31:24] + : _T_324 == 5'h1E + ? io_writeReq_2_bits_data[23:16] + : _T_316 == 5'h1E + ? io_writeReq_2_bits_data[15:8] + : _GEN_640) + : _GEN_640; + assign internalWriteData_2_31 = + _T_304 + ? ((&_T_364) + ? io_writeReq_2_bits_data[63:56] + : (&_T_356) + ? io_writeReq_2_bits_data[55:48] + : (&_T_348) + ? io_writeReq_2_bits_data[47:40] + : (&_T_340) + ? io_writeReq_2_bits_data[39:32] + : (&_T_332) + ? io_writeReq_2_bits_data[31:24] + : (&_T_324) + ? io_writeReq_2_bits_data[23:16] + : (&_T_316) ? io_writeReq_2_bits_data[15:8] : _GEN_641) + : _GEN_641; + wire [4:0] _T_368 = _GEN_645 + 5'h7; + assign internalWriteMask_2_0 = + _T_304 + & (_T_368 == 5'h0 | _T_360 == 5'h0 | _T_352 == 5'h0 | _T_344 == 5'h0 | _T_336 == 5'h0 + | _T_328 == 5'h0 | _T_320 == 5'h0 | _GEN_642) + | (_T_271 + ? _T_303 == 5'h0 | _T_295 == 5'h0 | _T_287 == 5'h0 | _GEN_602 | _GEN_570 + | _GEN_490 + : _GEN_570 | _GEN_490); + assign internalWriteMask_2_1 = + _T_304 + & (_T_368 == 5'h1 | _T_360 == 5'h1 | _T_352 == 5'h1 | _T_344 == 5'h1 | _T_336 == 5'h1 + | _T_328 == 5'h1 | _T_320 == 5'h1) + | (_T_271 + ? _T_303 == 5'h1 | _T_295 == 5'h1 | _T_287 == 5'h1 | _GEN_571 | _GEN_491 + : _GEN_571 | _GEN_491); + assign internalWriteMask_2_2 = + _T_304 + & (_T_368 == 5'h2 | _T_360 == 5'h2 | _T_352 == 5'h2 | _T_344 == 5'h2 | _T_336 == 5'h2 + | _T_328 == 5'h2 | _T_320 == 5'h2) + | (_T_271 + ? _T_303 == 5'h2 | _T_295 == 5'h2 | _T_287 == 5'h2 | _GEN_572 | _GEN_492 + : _GEN_572 | _GEN_492); + assign internalWriteMask_2_3 = + _T_304 + & (_T_368 == 5'h3 | _T_360 == 5'h3 | _T_352 == 5'h3 | _T_344 == 5'h3 | _T_336 == 5'h3 + | _T_328 == 5'h3 | _T_320 == 5'h3) + | (_T_271 + ? _T_303 == 5'h3 | _T_295 == 5'h3 | _T_287 == 5'h3 | _GEN_573 | _GEN_493 + : _GEN_573 | _GEN_493); + assign internalWriteMask_2_4 = + _T_304 + & (_T_368 == 5'h4 | _T_360 == 5'h4 | _T_352 == 5'h4 | _T_344 == 5'h4 | _T_336 == 5'h4 + | _T_328 == 5'h4 | _T_320 == 5'h4) + | (_T_271 + ? _T_303 == 5'h4 | _T_295 == 5'h4 | _T_287 == 5'h4 | _GEN_603 | _GEN_574 + | _GEN_494 + : _GEN_574 | _GEN_494); + assign internalWriteMask_2_5 = + _T_304 + & (_T_368 == 5'h5 | _T_360 == 5'h5 | _T_352 == 5'h5 | _T_344 == 5'h5 | _T_336 == 5'h5 + | _T_328 == 5'h5 | _T_320 == 5'h5) + | (_T_271 + ? _T_303 == 5'h5 | _T_295 == 5'h5 | _T_287 == 5'h5 | _GEN_575 | _GEN_495 + : _GEN_575 | _GEN_495); + assign internalWriteMask_2_6 = + _T_304 + & (_T_368 == 5'h6 | _T_360 == 5'h6 | _T_352 == 5'h6 | _T_344 == 5'h6 | _T_336 == 5'h6 + | _T_328 == 5'h6 | _T_320 == 5'h6) + | (_T_271 + ? _T_303 == 5'h6 | _T_295 == 5'h6 | _T_287 == 5'h6 | _GEN_576 | _GEN_496 + : _GEN_576 | _GEN_496); + assign internalWriteMask_2_7 = + _T_304 + & (_T_368 == 5'h7 | _T_360 == 5'h7 | _T_352 == 5'h7 | _T_344 == 5'h7 | _T_336 == 5'h7 + | _T_328 == 5'h7 | _T_320 == 5'h7) + | (_T_271 + ? _T_303 == 5'h7 | _T_295 == 5'h7 | _T_287 == 5'h7 | _GEN_577 | _GEN_497 + : _GEN_577 | _GEN_497); + assign internalWriteMask_2_8 = + _T_304 + & (_T_368 == 5'h8 | _T_360 == 5'h8 | _T_352 == 5'h8 | _T_344 == 5'h8 | _T_336 == 5'h8 + | _T_328 == 5'h8 | _T_320 == 5'h8 | _GEN_643) + | (_T_271 + ? _T_303 == 5'h8 | _T_295 == 5'h8 | _T_287 == 5'h8 | _GEN_604 | _GEN_578 + | _GEN_498 + : _GEN_578 | _GEN_498); + assign internalWriteMask_2_9 = + _T_304 + & (_T_368 == 5'h9 | _T_360 == 5'h9 | _T_352 == 5'h9 | _T_344 == 5'h9 | _T_336 == 5'h9 + | _T_328 == 5'h9 | _T_320 == 5'h9) + | (_T_271 + ? _T_303 == 5'h9 | _T_295 == 5'h9 | _T_287 == 5'h9 | _GEN_579 | _GEN_499 + : _GEN_579 | _GEN_499); + assign internalWriteMask_2_10 = + _T_304 + & (_T_368 == 5'hA | _T_360 == 5'hA | _T_352 == 5'hA | _T_344 == 5'hA | _T_336 == 5'hA + | _T_328 == 5'hA | _T_320 == 5'hA) + | (_T_271 + ? _T_303 == 5'hA | _T_295 == 5'hA | _T_287 == 5'hA | _GEN_580 | _GEN_500 + : _GEN_580 | _GEN_500); + assign internalWriteMask_2_11 = + _T_304 + & (_T_368 == 5'hB | _T_360 == 5'hB | _T_352 == 5'hB | _T_344 == 5'hB | _T_336 == 5'hB + | _T_328 == 5'hB | _T_320 == 5'hB) + | (_T_271 + ? _T_303 == 5'hB | _T_295 == 5'hB | _T_287 == 5'hB | _GEN_581 | _GEN_501 + : _GEN_581 | _GEN_501); + assign internalWriteMask_2_12 = + _T_304 + & (_T_368 == 5'hC | _T_360 == 5'hC | _T_352 == 5'hC | _T_344 == 5'hC | _T_336 == 5'hC + | _T_328 == 5'hC | _T_320 == 5'hC) + | (_T_271 + ? _T_303 == 5'hC | _T_295 == 5'hC | _T_287 == 5'hC | _GEN_605 | _GEN_582 + | _GEN_502 + : _GEN_582 | _GEN_502); + assign internalWriteMask_2_13 = + _T_304 + & (_T_368 == 5'hD | _T_360 == 5'hD | _T_352 == 5'hD | _T_344 == 5'hD | _T_336 == 5'hD + | _T_328 == 5'hD | _T_320 == 5'hD) + | (_T_271 + ? _T_303 == 5'hD | _T_295 == 5'hD | _T_287 == 5'hD | _GEN_583 | _GEN_503 + : _GEN_583 | _GEN_503); + assign internalWriteMask_2_14 = + _T_304 + & (_T_368 == 5'hE | _T_360 == 5'hE | _T_352 == 5'hE | _T_344 == 5'hE | _T_336 == 5'hE + | _T_328 == 5'hE | _T_320 == 5'hE) + | (_T_271 + ? _T_303 == 5'hE | _T_295 == 5'hE | _T_287 == 5'hE | _GEN_584 | _GEN_504 + : _GEN_584 | _GEN_504); + assign internalWriteMask_2_15 = + _T_304 + & (_T_368 == 5'hF | _T_360 == 5'hF | _T_352 == 5'hF | _T_344 == 5'hF | _T_336 == 5'hF + | _T_328 == 5'hF | _T_320 == 5'hF) + | (_T_271 + ? _T_303 == 5'hF | _T_295 == 5'hF | _T_287 == 5'hF | _GEN_585 | _GEN_505 + : _GEN_585 | _GEN_505); + assign internalWriteMask_2_16 = + _T_304 + & (_T_368 == 5'h10 | _T_360 == 5'h10 | _T_352 == 5'h10 | _T_344 == 5'h10 + | _T_336 == 5'h10 | _T_328 == 5'h10 | _T_320 == 5'h10 | _GEN_644) + | (_T_271 + ? _T_303 == 5'h10 | _T_295 == 5'h10 | _T_287 == 5'h10 | _GEN_606 | _GEN_586 + | _GEN_506 + : _GEN_586 | _GEN_506); + assign internalWriteMask_2_17 = + _T_304 + & (_T_368 == 5'h11 | _T_360 == 5'h11 | _T_352 == 5'h11 | _T_344 == 5'h11 + | _T_336 == 5'h11 | _T_328 == 5'h11 | _T_320 == 5'h11) + | (_T_271 + ? _T_303 == 5'h11 | _T_295 == 5'h11 | _T_287 == 5'h11 | _GEN_587 | _GEN_507 + : _GEN_587 | _GEN_507); + assign internalWriteMask_2_18 = + _T_304 + & (_T_368 == 5'h12 | _T_360 == 5'h12 | _T_352 == 5'h12 | _T_344 == 5'h12 + | _T_336 == 5'h12 | _T_328 == 5'h12 | _T_320 == 5'h12) + | (_T_271 + ? _T_303 == 5'h12 | _T_295 == 5'h12 | _T_287 == 5'h12 | _GEN_588 | _GEN_508 + : _GEN_588 | _GEN_508); + assign internalWriteMask_2_19 = + _T_304 + & (_T_368 == 5'h13 | _T_360 == 5'h13 | _T_352 == 5'h13 | _T_344 == 5'h13 + | _T_336 == 5'h13 | _T_328 == 5'h13 | _T_320 == 5'h13) + | (_T_271 + ? _T_303 == 5'h13 | _T_295 == 5'h13 | _T_287 == 5'h13 | _GEN_589 | _GEN_509 + : _GEN_589 | _GEN_509); + assign internalWriteMask_2_20 = + _T_304 + & (_T_368 == 5'h14 | _T_360 == 5'h14 | _T_352 == 5'h14 | _T_344 == 5'h14 + | _T_336 == 5'h14 | _T_328 == 5'h14 | _T_320 == 5'h14) + | (_T_271 + ? _T_303 == 5'h14 | _T_295 == 5'h14 | _T_287 == 5'h14 | _GEN_607 | _GEN_590 + | _GEN_510 + : _GEN_590 | _GEN_510); + assign internalWriteMask_2_21 = + _T_304 + & (_T_368 == 5'h15 | _T_360 == 5'h15 | _T_352 == 5'h15 | _T_344 == 5'h15 + | _T_336 == 5'h15 | _T_328 == 5'h15 | _T_320 == 5'h15) + | (_T_271 + ? _T_303 == 5'h15 | _T_295 == 5'h15 | _T_287 == 5'h15 | _GEN_591 | _GEN_511 + : _GEN_591 | _GEN_511); + assign internalWriteMask_2_22 = + _T_304 + & (_T_368 == 5'h16 | _T_360 == 5'h16 | _T_352 == 5'h16 | _T_344 == 5'h16 + | _T_336 == 5'h16 | _T_328 == 5'h16 | _T_320 == 5'h16) + | (_T_271 + ? _T_303 == 5'h16 | _T_295 == 5'h16 | _T_287 == 5'h16 | _GEN_592 | _GEN_512 + : _GEN_592 | _GEN_512); + assign internalWriteMask_2_23 = + _T_304 + & (_T_368 == 5'h17 | _T_360 == 5'h17 | _T_352 == 5'h17 | _T_344 == 5'h17 + | _T_336 == 5'h17 | _T_328 == 5'h17 | _T_320 == 5'h17) + | (_T_271 + ? _T_303 == 5'h17 | _T_295 == 5'h17 | _T_287 == 5'h17 | _GEN_593 | _GEN_513 + : _GEN_593 | _GEN_513); + assign internalWriteMask_2_24 = + _T_304 + & (_T_368 == 5'h18 | _T_360 == 5'h18 | _T_352 == 5'h18 | _T_344 == 5'h18 + | _T_336 == 5'h18 | _T_328 == 5'h18 | _T_320 == 5'h18 + | (&(io_writeReq_2_bits_index[1:0]))) + | (_T_271 + ? _T_303 == 5'h18 | _T_295 == 5'h18 | _T_287 == 5'h18 | _GEN_608 | _GEN_594 + | _GEN_514 + : _GEN_594 | _GEN_514); + assign internalWriteMask_2_25 = + _T_304 + & (_T_368 == 5'h19 | _T_360 == 5'h19 | _T_352 == 5'h19 | _T_344 == 5'h19 + | _T_336 == 5'h19 | _T_328 == 5'h19 | _T_320 == 5'h19) + | (_T_271 + ? _T_303 == 5'h19 | _T_295 == 5'h19 | _T_287 == 5'h19 | _GEN_595 | _GEN_515 + : _GEN_595 | _GEN_515); + assign internalWriteMask_2_26 = + _T_304 + & (_T_368 == 5'h1A | _T_360 == 5'h1A | _T_352 == 5'h1A | _T_344 == 5'h1A + | _T_336 == 5'h1A | _T_328 == 5'h1A | _T_320 == 5'h1A) + | (_T_271 + ? _T_303 == 5'h1A | _T_295 == 5'h1A | _T_287 == 5'h1A | _GEN_596 | _GEN_516 + : _GEN_596 | _GEN_516); + assign internalWriteMask_2_27 = + _T_304 + & (_T_368 == 5'h1B | _T_360 == 5'h1B | _T_352 == 5'h1B | _T_344 == 5'h1B + | _T_336 == 5'h1B | _T_328 == 5'h1B | _T_320 == 5'h1B) + | (_T_271 + ? _T_303 == 5'h1B | _T_295 == 5'h1B | _T_287 == 5'h1B | _GEN_597 | _GEN_517 + : _GEN_597 | _GEN_517); + assign internalWriteMask_2_28 = + _T_304 + & (_T_368 == 5'h1C | _T_360 == 5'h1C | _T_352 == 5'h1C | _T_344 == 5'h1C + | _T_336 == 5'h1C | _T_328 == 5'h1C | _T_320 == 5'h1C) + | (_T_271 + ? _T_303 == 5'h1C | _T_295 == 5'h1C | _T_287 == 5'h1C + | (&(io_writeReq_2_bits_index[2:0])) | _GEN_598 | _GEN_518 + : _GEN_598 | _GEN_518); + assign internalWriteMask_2_29 = + _T_304 + & (_T_368 == 5'h1D | _T_360 == 5'h1D | _T_352 == 5'h1D | _T_344 == 5'h1D + | _T_336 == 5'h1D | _T_328 == 5'h1D | _T_320 == 5'h1D) + | (_T_271 + ? _T_303 == 5'h1D | _T_295 == 5'h1D | _T_287 == 5'h1D | _GEN_599 | _GEN_519 + : _GEN_599 | _GEN_519); + assign internalWriteMask_2_30 = + _T_304 + & (_T_368 == 5'h1E | _T_360 == 5'h1E | _T_352 == 5'h1E | _T_344 == 5'h1E + | _T_336 == 5'h1E | _T_328 == 5'h1E | _T_320 == 5'h1E) + | (_T_271 + ? _T_303 == 5'h1E | _T_295 == 5'h1E | _T_287 == 5'h1E | _GEN_600 | _GEN_520 + : _GEN_600 | _GEN_520); + assign internalWriteMask_2_31 = + _T_304 + & ((&_T_368) | (&_T_360) | (&_T_352) | (&_T_344) | (&_T_336) | (&_T_328) | (&_T_320)) + | (_T_271 + ? (&_T_303) | (&_T_295) | (&_T_287) | _GEN_601 | _GEN_521 + : _GEN_601 | _GEN_521); + vrf_combMem vrf_ext ( + .R0_addr (5'h0), + .R0_en (1'h1), + .R0_clk (clock), + .R1_addr (io_readReq_0_req_vd), + .R1_en (1'h1), + .R1_clk (clock), + .R2_addr (5'h0), + .R2_en (1'h1), + .R2_clk (clock), + .R3_addr (io_readReq_0_req_vs2), + .R3_en (1'h1), + .R3_clk (clock), + .R4_addr (5'h0), + .R4_en (1'h1), + .R4_clk (clock), + .R5_addr (io_readReq_1_req_vd), + .R5_en (1'h1), + .R5_clk (clock), + .R6_addr (io_readReq_1_req_vs1), + .R6_en (1'h1), + .R6_clk (clock), + .R7_addr (io_readReq_1_req_vs2), + .R7_en (1'h1), + .R7_clk (clock), + .R8_addr (5'h0), + .R8_en (1'h1), + .R8_clk (clock), + .R9_addr (io_readReq_2_req_vd), + .R9_en (1'h1), + .R9_clk (clock), + .R10_addr (io_readReq_2_req_vs1), + .R10_en (1'h1), + .R10_clk (clock), + .R11_addr (io_readReq_2_req_vs2), + .R11_en (1'h1), + .R11_clk (clock), + .W0_addr (io_writeReq_0_bits_vd), + .W0_en (io_writeReq_0_valid & io_writeReq_0_bits_writeReq), + .W0_clk (clock), + .W0_data + ({internalWriteData_31, + internalWriteData_30, + internalWriteData_29, + internalWriteData_28, + internalWriteData_27, + internalWriteData_26, + internalWriteData_25, + internalWriteData_24, + internalWriteData_23, + internalWriteData_22, + internalWriteData_21, + internalWriteData_20, + internalWriteData_19, + internalWriteData_18, + internalWriteData_17, + internalWriteData_16, + internalWriteData_15, + internalWriteData_14, + internalWriteData_13, + internalWriteData_12, + internalWriteData_11, + internalWriteData_10, + internalWriteData_9, + internalWriteData_8, + internalWriteData_7, + internalWriteData_6, + internalWriteData_5, + internalWriteData_4, + internalWriteData_3, + internalWriteData_2, + internalWriteData_1, + internalWriteData_0}), + .W0_mask + ({internalWriteMask_31, + internalWriteMask_30, + internalWriteMask_29, + internalWriteMask_28, + internalWriteMask_27, + internalWriteMask_26, + internalWriteMask_25, + internalWriteMask_24, + internalWriteMask_23, + internalWriteMask_22, + internalWriteMask_21, + internalWriteMask_20, + internalWriteMask_19, + internalWriteMask_18, + internalWriteMask_17, + internalWriteMask_16, + internalWriteMask_15, + internalWriteMask_14, + internalWriteMask_13, + internalWriteMask_12, + internalWriteMask_11, + internalWriteMask_10, + internalWriteMask_9, + internalWriteMask_8, + internalWriteMask_7, + internalWriteMask_6, + internalWriteMask_5, + internalWriteMask_4, + internalWriteMask_3, + internalWriteMask_2, + internalWriteMask_1, + internalWriteMask_0}), + .W1_addr (io_writeReq_1_bits_vd), + .W1_en (io_writeReq_1_valid & io_writeReq_1_bits_writeReq), + .W1_clk (clock), + .W1_data + ({internalWriteData_1_31, + internalWriteData_1_30, + internalWriteData_1_29, + internalWriteData_1_28, + internalWriteData_1_27, + internalWriteData_1_26, + internalWriteData_1_25, + internalWriteData_1_24, + internalWriteData_1_23, + internalWriteData_1_22, + internalWriteData_1_21, + internalWriteData_1_20, + internalWriteData_1_19, + internalWriteData_1_18, + internalWriteData_1_17, + internalWriteData_1_16, + internalWriteData_1_15, + internalWriteData_1_14, + internalWriteData_1_13, + internalWriteData_1_12, + internalWriteData_1_11, + internalWriteData_1_10, + internalWriteData_1_9, + internalWriteData_1_8, + internalWriteData_1_7, + internalWriteData_1_6, + internalWriteData_1_5, + internalWriteData_1_4, + internalWriteData_1_3, + internalWriteData_1_2, + internalWriteData_1_1, + internalWriteData_1_0}), + .W1_mask + ({internalWriteMask_1_31, + internalWriteMask_1_30, + internalWriteMask_1_29, + internalWriteMask_1_28, + internalWriteMask_1_27, + internalWriteMask_1_26, + internalWriteMask_1_25, + internalWriteMask_1_24, + internalWriteMask_1_23, + internalWriteMask_1_22, + internalWriteMask_1_21, + internalWriteMask_1_20, + internalWriteMask_1_19, + internalWriteMask_1_18, + internalWriteMask_1_17, + internalWriteMask_1_16, + internalWriteMask_1_15, + internalWriteMask_1_14, + internalWriteMask_1_13, + internalWriteMask_1_12, + internalWriteMask_1_11, + internalWriteMask_1_10, + internalWriteMask_1_9, + internalWriteMask_1_8, + internalWriteMask_1_7, + internalWriteMask_1_6, + internalWriteMask_1_5, + internalWriteMask_1_4, + internalWriteMask_1_3, + internalWriteMask_1_2, + internalWriteMask_1_1, + internalWriteMask_1_0}), + .W2_addr (io_writeReq_2_bits_vd), + .W2_en (io_writeReq_2_valid & io_writeReq_2_bits_writeReq), + .W2_clk (clock), + .W2_data + ({internalWriteData_2_31, + internalWriteData_2_30, + internalWriteData_2_29, + internalWriteData_2_28, + internalWriteData_2_27, + internalWriteData_2_26, + internalWriteData_2_25, + internalWriteData_2_24, + internalWriteData_2_23, + internalWriteData_2_22, + internalWriteData_2_21, + internalWriteData_2_20, + internalWriteData_2_19, + internalWriteData_2_18, + internalWriteData_2_17, + internalWriteData_2_16, + internalWriteData_2_15, + internalWriteData_2_14, + internalWriteData_2_13, + internalWriteData_2_12, + internalWriteData_2_11, + internalWriteData_2_10, + internalWriteData_2_9, + internalWriteData_2_8, + internalWriteData_2_7, + internalWriteData_2_6, + internalWriteData_2_5, + internalWriteData_2_4, + internalWriteData_2_3, + internalWriteData_2_2, + internalWriteData_2_1, + internalWriteData_2_0}), + .W2_mask + ({internalWriteMask_2_31, + internalWriteMask_2_30, + internalWriteMask_2_29, + internalWriteMask_2_28, + internalWriteMask_2_27, + internalWriteMask_2_26, + internalWriteMask_2_25, + internalWriteMask_2_24, + internalWriteMask_2_23, + internalWriteMask_2_22, + internalWriteMask_2_21, + internalWriteMask_2_20, + internalWriteMask_2_19, + internalWriteMask_2_18, + internalWriteMask_2_17, + internalWriteMask_2_16, + internalWriteMask_2_15, + internalWriteMask_2_14, + internalWriteMask_2_13, + internalWriteMask_2_12, + internalWriteMask_2_11, + internalWriteMask_2_10, + internalWriteMask_2_9, + internalWriteMask_2_8, + internalWriteMask_2_7, + internalWriteMask_2_6, + internalWriteMask_2_5, + internalWriteMask_2_4, + internalWriteMask_2_3, + internalWriteMask_2_2, + internalWriteMask_2_1, + internalWriteMask_2_0}), + .R0_data (_vrf_ext_R0_data), + .R1_data (_vrf_ext_R1_data), + .R2_data (/* unused */), + .R3_data (_vrf_ext_R3_data), + .R4_data (_vrf_ext_R4_data), + .R5_data (_vrf_ext_R5_data), + .R6_data (_vrf_ext_R6_data), + .R7_data (_vrf_ext_R7_data), + .R8_data (_vrf_ext_R8_data), + .R9_data (_vrf_ext_R9_data), + .R10_data (_vrf_ext_R10_data), + .R11_data (_vrf_ext_R11_data) + ); + assign io_readReq_0_resp_vs2Out = + _io_readReq_0_resp_res_vdOut_nonVmRes_T_80 + ? {_GEN[_GEN_4 + 5'h7], + _GEN[_GEN_4 + 5'h6], + _GEN[_GEN_4 + 5'h5], + _GEN[_GEN_4 + 5'h4], + _GEN[_GEN_4 + 5'h3], + _GEN[_GEN_4 + 5'h2], + _GEN[_GEN_4 + 5'h1], + _GEN[{io_readReq_0_req_idx[1:0], 3'h0}]} + : _io_readReq_0_resp_res_vdOut_nonVmRes_T_78 + ? {{32{_GEN_3[7]}}, + _GEN_3, + _GEN[_GEN_2 + 5'h2], + _GEN[_GEN_2 + 5'h1], + _GEN[{io_readReq_0_req_idx[2:0], 2'h0}]} + : _io_readReq_0_resp_res_vdOut_nonVmRes_T_76 + ? {{48{_GEN_1[7]}}, _GEN_1, _GEN[{io_readReq_0_req_idx[3:0], 1'h0}]} + : _io_readReq_0_resp_res_vdOut_nonVmRes_T_74 + ? {{56{_GEN[io_readReq_0_req_idx][7]}}, _GEN[io_readReq_0_req_idx]} + : 64'h0; + assign io_readReq_0_resp_vdOut = + _io_readReq_0_resp_res_vdOut_nonVmRes_T_80 + ? {_GEN_5[_GEN_4 + 5'h7], + _GEN_5[_GEN_4 + 5'h6], + _GEN_5[_GEN_4 + 5'h5], + _GEN_5[_GEN_4 + 5'h4], + _GEN_5[_GEN_4 + 5'h3], + _GEN_5[_GEN_4 + 5'h2], + _GEN_5[_GEN_4 + 5'h1], + _GEN_5[{io_readReq_0_req_idx[1:0], 3'h0}]} + : _io_readReq_0_resp_res_vdOut_nonVmRes_T_78 + ? {{32{_GEN_7[7]}}, + _GEN_7, + _GEN_5[_GEN_2 + 5'h2], + _GEN_5[_GEN_2 + 5'h1], + _GEN_5[{io_readReq_0_req_idx[2:0], 2'h0}]} + : _io_readReq_0_resp_res_vdOut_nonVmRes_T_76 + ? {{48{_GEN_6[7]}}, _GEN_6, _GEN_5[{io_readReq_0_req_idx[3:0], 1'h0}]} + : _io_readReq_0_resp_res_vdOut_nonVmRes_T_74 + ? {{56{_GEN_5[io_readReq_0_req_idx][7]}}, _GEN_5[io_readReq_0_req_idx]} + : 64'h0; + assign io_readReq_0_resp_vm = _io_readReq_0_resp_res_vm_T_2[0]; + assign io_readReq_1_resp_vs1Out = + _io_readReq_1_resp_res_vdOut_nonVmRes_T_80 + ? {_GEN_9[_GEN_14 + 5'h7], + _GEN_9[_GEN_14 + 5'h6], + _GEN_9[_GEN_14 + 5'h5], + _GEN_9[_GEN_14 + 5'h4], + _GEN_9[_GEN_14 + 5'h3], + _GEN_9[_GEN_14 + 5'h2], + _GEN_9[_GEN_14 + 5'h1], + _GEN_9[{io_readReq_1_req_idx[1:0], 3'h0}]} + : _io_readReq_1_resp_res_vdOut_nonVmRes_T_78 + ? {{32{_GEN_13[7]}}, + _GEN_13, + _GEN_9[_GEN_12 + 5'h2], + _GEN_9[_GEN_12 + 5'h1], + _GEN_9[{io_readReq_1_req_idx[2:0], 2'h0}]} + : _io_readReq_1_resp_res_vdOut_nonVmRes_T_76 + ? {{48{_GEN_11[7]}}, _GEN_11, _GEN_9[{io_readReq_1_req_idx[3:0], 1'h0}]} + : _io_readReq_1_resp_res_vdOut_nonVmRes_T_74 + ? {{56{_GEN_9[io_readReq_1_req_idx][7]}}, _GEN_9[io_readReq_1_req_idx]} + : 64'h0; + assign io_readReq_1_resp_vs2Out = + _io_readReq_1_resp_res_vdOut_nonVmRes_T_80 + ? {_GEN_15[_GEN_14 + 5'h7], + _GEN_15[_GEN_14 + 5'h6], + _GEN_15[_GEN_14 + 5'h5], + _GEN_15[_GEN_14 + 5'h4], + _GEN_15[_GEN_14 + 5'h3], + _GEN_15[_GEN_14 + 5'h2], + _GEN_15[_GEN_14 + 5'h1], + _GEN_15[{io_readReq_1_req_idx[1:0], 3'h0}]} + : _io_readReq_1_resp_res_vdOut_nonVmRes_T_78 + ? {{32{_GEN_17[7]}}, + _GEN_17, + _GEN_15[_GEN_12 + 5'h2], + _GEN_15[_GEN_12 + 5'h1], + _GEN_15[{io_readReq_1_req_idx[2:0], 2'h0}]} + : _io_readReq_1_resp_res_vdOut_nonVmRes_T_76 + ? {{48{_GEN_16[7]}}, _GEN_16, _GEN_15[{io_readReq_1_req_idx[3:0], 1'h0}]} + : _io_readReq_1_resp_res_vdOut_nonVmRes_T_74 + ? {{56{_GEN_15[io_readReq_1_req_idx][7]}}, + _GEN_15[io_readReq_1_req_idx]} + : 64'h0; + assign io_readReq_1_resp_vdOut = + io_readReq_1_req_readVdAsMaskSource + ? {56'h0, _GEN_18[_GEN_21]} + : _io_readReq_1_resp_res_vdOut_nonVmRes_T_80 + ? {_GEN_18[_GEN_14 + 5'h7], + _GEN_18[_GEN_14 + 5'h6], + _GEN_18[_GEN_14 + 5'h5], + _GEN_18[_GEN_14 + 5'h4], + _GEN_18[_GEN_14 + 5'h3], + _GEN_18[_GEN_14 + 5'h2], + _GEN_18[_GEN_14 + 5'h1], + _GEN_18[{io_readReq_1_req_idx[1:0], 3'h0}]} + : _io_readReq_1_resp_res_vdOut_nonVmRes_T_78 + ? {{32{_GEN_20[7]}}, + _GEN_20, + _GEN_18[_GEN_12 + 5'h2], + _GEN_18[_GEN_12 + 5'h1], + _GEN_18[{io_readReq_1_req_idx[2:0], 2'h0}]} + : _io_readReq_1_resp_res_vdOut_nonVmRes_T_76 + ? {{48{_GEN_19[7]}}, + _GEN_19, + _GEN_18[{io_readReq_1_req_idx[3:0], 1'h0}]} + : _io_readReq_1_resp_res_vdOut_nonVmRes_T_74 + ? {{56{_GEN_18[io_readReq_1_req_idx][7]}}, + _GEN_18[io_readReq_1_req_idx]} + : 64'h0; + assign io_readReq_1_resp_vm = _io_readReq_1_resp_res_vm_T_2[0]; + assign io_readReq_2_resp_vs1Out = + _io_readReq_2_resp_res_vdOut_nonVmRes_T_80 + ? {_GEN_23[_GEN_28 + 5'h7], + _GEN_23[_GEN_28 + 5'h6], + _GEN_23[_GEN_28 + 5'h5], + _GEN_23[_GEN_28 + 5'h4], + _GEN_23[_GEN_28 + 5'h3], + _GEN_23[_GEN_28 + 5'h2], + _GEN_23[_GEN_28 + 5'h1], + _GEN_23[{io_readReq_2_req_idx[1:0], 3'h0}]} + : _io_readReq_2_resp_res_vdOut_nonVmRes_T_78 + ? {{32{_GEN_27[7]}}, + _GEN_27, + _GEN_23[_GEN_26 + 5'h2], + _GEN_23[_GEN_26 + 5'h1], + _GEN_23[{io_readReq_2_req_idx[2:0], 2'h0}]} + : _io_readReq_2_resp_res_vdOut_nonVmRes_T_76 + ? {{48{_GEN_25[7]}}, _GEN_25, _GEN_23[{io_readReq_2_req_idx[3:0], 1'h0}]} + : _io_readReq_2_resp_res_vdOut_nonVmRes_T_74 + ? {{56{_GEN_23[io_readReq_2_req_idx][7]}}, + _GEN_23[io_readReq_2_req_idx]} + : 64'h0; + assign io_readReq_2_resp_vs2Out = + _io_readReq_2_resp_res_vdOut_nonVmRes_T_80 + ? {_GEN_29[_GEN_28 + 5'h7], + _GEN_29[_GEN_28 + 5'h6], + _GEN_29[_GEN_28 + 5'h5], + _GEN_29[_GEN_28 + 5'h4], + _GEN_29[_GEN_28 + 5'h3], + _GEN_29[_GEN_28 + 5'h2], + _GEN_29[_GEN_28 + 5'h1], + _GEN_29[{io_readReq_2_req_idx[1:0], 3'h0}]} + : _io_readReq_2_resp_res_vdOut_nonVmRes_T_78 + ? {{32{_GEN_31[7]}}, + _GEN_31, + _GEN_29[_GEN_26 + 5'h2], + _GEN_29[_GEN_26 + 5'h1], + _GEN_29[{io_readReq_2_req_idx[2:0], 2'h0}]} + : _io_readReq_2_resp_res_vdOut_nonVmRes_T_76 + ? {{48{_GEN_30[7]}}, _GEN_30, _GEN_29[{io_readReq_2_req_idx[3:0], 1'h0}]} + : _io_readReq_2_resp_res_vdOut_nonVmRes_T_74 + ? {{56{_GEN_29[io_readReq_2_req_idx][7]}}, + _GEN_29[io_readReq_2_req_idx]} + : 64'h0; + assign io_readReq_2_resp_vdOut = + io_readReq_2_req_readVdAsMaskSource + ? {56'h0, _GEN_32[_GEN_35]} + : _io_readReq_2_resp_res_vdOut_nonVmRes_T_80 + ? {_GEN_32[_GEN_28 + 5'h7], + _GEN_32[_GEN_28 + 5'h6], + _GEN_32[_GEN_28 + 5'h5], + _GEN_32[_GEN_28 + 5'h4], + _GEN_32[_GEN_28 + 5'h3], + _GEN_32[_GEN_28 + 5'h2], + _GEN_32[_GEN_28 + 5'h1], + _GEN_32[{io_readReq_2_req_idx[1:0], 3'h0}]} + : _io_readReq_2_resp_res_vdOut_nonVmRes_T_78 + ? {{32{_GEN_34[7]}}, + _GEN_34, + _GEN_32[_GEN_26 + 5'h2], + _GEN_32[_GEN_26 + 5'h1], + _GEN_32[{io_readReq_2_req_idx[2:0], 2'h0}]} + : _io_readReq_2_resp_res_vdOut_nonVmRes_T_76 + ? {{48{_GEN_33[7]}}, + _GEN_33, + _GEN_32[{io_readReq_2_req_idx[3:0], 1'h0}]} + : _io_readReq_2_resp_res_vdOut_nonVmRes_T_74 + ? {{56{_GEN_32[io_readReq_2_req_idx][7]}}, + _GEN_32[io_readReq_2_req_idx]} + : 64'h0; + assign io_readReq_2_resp_vm = _io_readReq_2_resp_res_vm_T_2[0]; +endmodule + +module VrfReadyTable( + input clock, + reset, + io_fromVecExecUnit_0_valid, + input [4:0] io_fromVecExecUnit_0_bits_vd, + input [2:0] io_fromVecExecUnit_0_bits_vtype_vsew, + input [4:0] io_fromVecExecUnit_0_bits_index, + input io_fromVecExecUnit_0_bits_last, + io_fromVecExecUnit_0_bits_writeReq, + io_fromVecExecUnit_1_valid, + input [4:0] io_fromVecExecUnit_1_bits_vd, + input [2:0] io_fromVecExecUnit_1_bits_vtype_vsew, + input [4:0] io_fromVecExecUnit_1_bits_index, + input io_fromVecExecUnit_1_bits_last, + io_fromVecExecUnit_1_bits_vm, + io_fromVecExecUnit_1_bits_writeReq, + io_fromVecExecUnit_2_valid, + input [4:0] io_fromVecExecUnit_2_bits_vd, + input [2:0] io_fromVecExecUnit_2_bits_vtype_vsew, + input [4:0] io_fromVecExecUnit_2_bits_index, + input io_fromVecExecUnit_2_bits_last, + io_fromVecExecUnit_2_bits_vm, + io_fromVecExecUnit_2_bits_writeReq, + io_invalidateVd, + io_vs1Check_valid, + input [4:0] io_vs1Check_bits_idx, + input [2:0] io_vs1Check_bits_vtype_vsew, + input io_vs1Check_bits_vm, + io_vs2Check_valid, + input [4:0] io_vs2Check_bits_idx, + input [2:0] io_vs2Check_bits_vtype_vsew, + input io_vs2Check_bits_vm, + io_vdCheck_valid, + input [4:0] io_vdCheck_bits_idx, + input [2:0] io_vdCheck_bits_vtype_vsew, + input io_vdCheck_bits_vm, + io_vmCheck_valid, + output io_vs1Check_ready, + io_vs2Check_ready, + io_vdCheck_ready, + io_vmCheck_ready +); + + reg vrfZeroIdxReadyTable_0; + reg vrfZeroIdxReadyTable_1; + reg vrfZeroIdxReadyTable_2; + reg vrfZeroIdxReadyTable_3; + reg vrfZeroIdxReadyTable_4; + reg vrfZeroIdxReadyTable_5; + reg vrfZeroIdxReadyTable_6; + reg vrfZeroIdxReadyTable_7; + reg vrfZeroIdxReadyTable_8; + reg vrfZeroIdxReadyTable_9; + reg vrfZeroIdxReadyTable_10; + reg vrfZeroIdxReadyTable_11; + reg vrfZeroIdxReadyTable_12; + reg vrfZeroIdxReadyTable_13; + reg vrfZeroIdxReadyTable_14; + reg vrfZeroIdxReadyTable_15; + reg vrfZeroIdxReadyTable_16; + reg vrfZeroIdxReadyTable_17; + reg vrfZeroIdxReadyTable_18; + reg vrfZeroIdxReadyTable_19; + reg vrfZeroIdxReadyTable_20; + reg vrfZeroIdxReadyTable_21; + reg vrfZeroIdxReadyTable_22; + reg vrfZeroIdxReadyTable_23; + reg vrfZeroIdxReadyTable_24; + reg vrfZeroIdxReadyTable_25; + reg vrfZeroIdxReadyTable_26; + reg vrfZeroIdxReadyTable_27; + reg vrfZeroIdxReadyTable_28; + reg vrfZeroIdxReadyTable_29; + reg vrfZeroIdxReadyTable_30; + reg vrfZeroIdxReadyTable_31; + reg vrfWholeIdxReadyTable_0; + reg vrfWholeIdxReadyTable_1; + reg vrfWholeIdxReadyTable_2; + reg vrfWholeIdxReadyTable_3; + reg vrfWholeIdxReadyTable_4; + reg vrfWholeIdxReadyTable_5; + reg vrfWholeIdxReadyTable_6; + reg vrfWholeIdxReadyTable_7; + reg vrfWholeIdxReadyTable_8; + reg vrfWholeIdxReadyTable_9; + reg vrfWholeIdxReadyTable_10; + reg vrfWholeIdxReadyTable_11; + reg vrfWholeIdxReadyTable_12; + reg vrfWholeIdxReadyTable_13; + reg vrfWholeIdxReadyTable_14; + reg vrfWholeIdxReadyTable_15; + reg vrfWholeIdxReadyTable_16; + reg vrfWholeIdxReadyTable_17; + reg vrfWholeIdxReadyTable_18; + reg vrfWholeIdxReadyTable_19; + reg vrfWholeIdxReadyTable_20; + reg vrfWholeIdxReadyTable_21; + reg vrfWholeIdxReadyTable_22; + reg vrfWholeIdxReadyTable_23; + reg vrfWholeIdxReadyTable_24; + reg vrfWholeIdxReadyTable_25; + reg vrfWholeIdxReadyTable_26; + reg vrfWholeIdxReadyTable_27; + reg vrfWholeIdxReadyTable_28; + reg vrfWholeIdxReadyTable_29; + reg vrfWholeIdxReadyTable_30; + reg vrfWholeIdxReadyTable_31; + reg [2:0] vrfWriteSewTable_0_sew; + reg [2:0] vrfWriteSewTable_1_sew; + reg [2:0] vrfWriteSewTable_2_sew; + reg [2:0] vrfWriteSewTable_3_sew; + reg [2:0] vrfWriteSewTable_4_sew; + reg [2:0] vrfWriteSewTable_5_sew; + reg [2:0] vrfWriteSewTable_6_sew; + reg [2:0] vrfWriteSewTable_7_sew; + reg [2:0] vrfWriteSewTable_8_sew; + reg [2:0] vrfWriteSewTable_9_sew; + reg [2:0] vrfWriteSewTable_10_sew; + reg [2:0] vrfWriteSewTable_11_sew; + reg [2:0] vrfWriteSewTable_12_sew; + reg [2:0] vrfWriteSewTable_13_sew; + reg [2:0] vrfWriteSewTable_14_sew; + reg [2:0] vrfWriteSewTable_15_sew; + reg [2:0] vrfWriteSewTable_16_sew; + reg [2:0] vrfWriteSewTable_17_sew; + reg [2:0] vrfWriteSewTable_18_sew; + reg [2:0] vrfWriteSewTable_19_sew; + reg [2:0] vrfWriteSewTable_20_sew; + reg [2:0] vrfWriteSewTable_21_sew; + reg [2:0] vrfWriteSewTable_22_sew; + reg [2:0] vrfWriteSewTable_23_sew; + reg [2:0] vrfWriteSewTable_24_sew; + reg [2:0] vrfWriteSewTable_25_sew; + reg [2:0] vrfWriteSewTable_26_sew; + reg [2:0] vrfWriteSewTable_27_sew; + reg [2:0] vrfWriteSewTable_28_sew; + reg [2:0] vrfWriteSewTable_29_sew; + reg [2:0] vrfWriteSewTable_30_sew; + reg [2:0] vrfWriteSewTable_31_sew; + wire _vdSameWriteList_T = + io_fromVecExecUnit_0_valid & io_fromVecExecUnit_0_bits_writeReq; + wire vs1SameWriteList_0 = + _vdSameWriteList_T & io_fromVecExecUnit_0_bits_vd == io_vs1Check_bits_idx; + wire _vdSameWriteList_T_2 = + io_fromVecExecUnit_1_valid & io_fromVecExecUnit_1_bits_writeReq; + wire vs1SameWriteList_1 = + _vdSameWriteList_T_2 & io_fromVecExecUnit_1_bits_vd == io_vs1Check_bits_idx; + wire _vdSameWriteList_T_4 = + io_fromVecExecUnit_2_valid & io_fromVecExecUnit_2_bits_writeReq; + wire vs1SameWriteList_2 = + _vdSameWriteList_T_4 & io_fromVecExecUnit_2_bits_vd == io_vs1Check_bits_idx; + wire [31:0][2:0] _GEN = + {{vrfWriteSewTable_31_sew}, + {vrfWriteSewTable_30_sew}, + {vrfWriteSewTable_29_sew}, + {vrfWriteSewTable_28_sew}, + {vrfWriteSewTable_27_sew}, + {vrfWriteSewTable_26_sew}, + {vrfWriteSewTable_25_sew}, + {vrfWriteSewTable_24_sew}, + {vrfWriteSewTable_23_sew}, + {vrfWriteSewTable_22_sew}, + {vrfWriteSewTable_21_sew}, + {vrfWriteSewTable_20_sew}, + {vrfWriteSewTable_19_sew}, + {vrfWriteSewTable_18_sew}, + {vrfWriteSewTable_17_sew}, + {vrfWriteSewTable_16_sew}, + {vrfWriteSewTable_15_sew}, + {vrfWriteSewTable_14_sew}, + {vrfWriteSewTable_13_sew}, + {vrfWriteSewTable_12_sew}, + {vrfWriteSewTable_11_sew}, + {vrfWriteSewTable_10_sew}, + {vrfWriteSewTable_9_sew}, + {vrfWriteSewTable_8_sew}, + {vrfWriteSewTable_7_sew}, + {vrfWriteSewTable_6_sew}, + {vrfWriteSewTable_5_sew}, + {vrfWriteSewTable_4_sew}, + {vrfWriteSewTable_3_sew}, + {vrfWriteSewTable_2_sew}, + {vrfWriteSewTable_1_sew}, + {vrfWriteSewTable_0_sew}}; + wire [31:0] _GEN_0 = + {{vrfZeroIdxReadyTable_31}, + {vrfZeroIdxReadyTable_30}, + {vrfZeroIdxReadyTable_29}, + {vrfZeroIdxReadyTable_28}, + {vrfZeroIdxReadyTable_27}, + {vrfZeroIdxReadyTable_26}, + {vrfZeroIdxReadyTable_25}, + {vrfZeroIdxReadyTable_24}, + {vrfZeroIdxReadyTable_23}, + {vrfZeroIdxReadyTable_22}, + {vrfZeroIdxReadyTable_21}, + {vrfZeroIdxReadyTable_20}, + {vrfZeroIdxReadyTable_19}, + {vrfZeroIdxReadyTable_18}, + {vrfZeroIdxReadyTable_17}, + {vrfZeroIdxReadyTable_16}, + {vrfZeroIdxReadyTable_15}, + {vrfZeroIdxReadyTable_14}, + {vrfZeroIdxReadyTable_13}, + {vrfZeroIdxReadyTable_12}, + {vrfZeroIdxReadyTable_11}, + {vrfZeroIdxReadyTable_10}, + {vrfZeroIdxReadyTable_9}, + {vrfZeroIdxReadyTable_8}, + {vrfZeroIdxReadyTable_7}, + {vrfZeroIdxReadyTable_6}, + {vrfZeroIdxReadyTable_5}, + {vrfZeroIdxReadyTable_4}, + {vrfZeroIdxReadyTable_3}, + {vrfZeroIdxReadyTable_2}, + {vrfZeroIdxReadyTable_1}, + {vrfZeroIdxReadyTable_0}}; + wire [31:0] _GEN_1 = + {{vrfWholeIdxReadyTable_31}, + {vrfWholeIdxReadyTable_30}, + {vrfWholeIdxReadyTable_29}, + {vrfWholeIdxReadyTable_28}, + {vrfWholeIdxReadyTable_27}, + {vrfWholeIdxReadyTable_26}, + {vrfWholeIdxReadyTable_25}, + {vrfWholeIdxReadyTable_24}, + {vrfWholeIdxReadyTable_23}, + {vrfWholeIdxReadyTable_22}, + {vrfWholeIdxReadyTable_21}, + {vrfWholeIdxReadyTable_20}, + {vrfWholeIdxReadyTable_19}, + {vrfWholeIdxReadyTable_18}, + {vrfWholeIdxReadyTable_17}, + {vrfWholeIdxReadyTable_16}, + {vrfWholeIdxReadyTable_15}, + {vrfWholeIdxReadyTable_14}, + {vrfWholeIdxReadyTable_13}, + {vrfWholeIdxReadyTable_12}, + {vrfWholeIdxReadyTable_11}, + {vrfWholeIdxReadyTable_10}, + {vrfWholeIdxReadyTable_9}, + {vrfWholeIdxReadyTable_8}, + {vrfWholeIdxReadyTable_7}, + {vrfWholeIdxReadyTable_6}, + {vrfWholeIdxReadyTable_5}, + {vrfWholeIdxReadyTable_4}, + {vrfWholeIdxReadyTable_3}, + {vrfWholeIdxReadyTable_2}, + {vrfWholeIdxReadyTable_1}, + {vrfWholeIdxReadyTable_0}}; + wire vs2SameWriteList_0 = + _vdSameWriteList_T & io_fromVecExecUnit_0_bits_vd == io_vs2Check_bits_idx; + wire vs2SameWriteList_1 = + _vdSameWriteList_T_2 & io_fromVecExecUnit_1_bits_vd == io_vs2Check_bits_idx; + wire vs2SameWriteList_2 = + _vdSameWriteList_T_4 & io_fromVecExecUnit_2_bits_vd == io_vs2Check_bits_idx; + wire vdSameWriteList_0 = + _vdSameWriteList_T & io_fromVecExecUnit_0_bits_vd == io_vdCheck_bits_idx; + wire vdSameWriteList_1 = + _vdSameWriteList_T_2 & io_fromVecExecUnit_1_bits_vd == io_vdCheck_bits_idx; + wire vdSameWriteList_2 = + _vdSameWriteList_T_4 & io_fromVecExecUnit_2_bits_vd == io_vdCheck_bits_idx; + always @(posedge clock) begin + if (reset) begin + vrfZeroIdxReadyTable_0 <= 1'h1; + vrfZeroIdxReadyTable_1 <= 1'h1; + vrfZeroIdxReadyTable_2 <= 1'h1; + vrfZeroIdxReadyTable_3 <= 1'h1; + vrfZeroIdxReadyTable_4 <= 1'h1; + vrfZeroIdxReadyTable_5 <= 1'h1; + vrfZeroIdxReadyTable_6 <= 1'h1; + vrfZeroIdxReadyTable_7 <= 1'h1; + vrfZeroIdxReadyTable_8 <= 1'h1; + vrfZeroIdxReadyTable_9 <= 1'h1; + vrfZeroIdxReadyTable_10 <= 1'h1; + vrfZeroIdxReadyTable_11 <= 1'h1; + vrfZeroIdxReadyTable_12 <= 1'h1; + vrfZeroIdxReadyTable_13 <= 1'h1; + vrfZeroIdxReadyTable_14 <= 1'h1; + vrfZeroIdxReadyTable_15 <= 1'h1; + vrfZeroIdxReadyTable_16 <= 1'h1; + vrfZeroIdxReadyTable_17 <= 1'h1; + vrfZeroIdxReadyTable_18 <= 1'h1; + vrfZeroIdxReadyTable_19 <= 1'h1; + vrfZeroIdxReadyTable_20 <= 1'h1; + vrfZeroIdxReadyTable_21 <= 1'h1; + vrfZeroIdxReadyTable_22 <= 1'h1; + vrfZeroIdxReadyTable_23 <= 1'h1; + vrfZeroIdxReadyTable_24 <= 1'h1; + vrfZeroIdxReadyTable_25 <= 1'h1; + vrfZeroIdxReadyTable_26 <= 1'h1; + vrfZeroIdxReadyTable_27 <= 1'h1; + vrfZeroIdxReadyTable_28 <= 1'h1; + vrfZeroIdxReadyTable_29 <= 1'h1; + vrfZeroIdxReadyTable_30 <= 1'h1; + vrfZeroIdxReadyTable_31 <= 1'h1; + vrfWholeIdxReadyTable_0 <= 1'h1; + vrfWholeIdxReadyTable_1 <= 1'h1; + vrfWholeIdxReadyTable_2 <= 1'h1; + vrfWholeIdxReadyTable_3 <= 1'h1; + vrfWholeIdxReadyTable_4 <= 1'h1; + vrfWholeIdxReadyTable_5 <= 1'h1; + vrfWholeIdxReadyTable_6 <= 1'h1; + vrfWholeIdxReadyTable_7 <= 1'h1; + vrfWholeIdxReadyTable_8 <= 1'h1; + vrfWholeIdxReadyTable_9 <= 1'h1; + vrfWholeIdxReadyTable_10 <= 1'h1; + vrfWholeIdxReadyTable_11 <= 1'h1; + vrfWholeIdxReadyTable_12 <= 1'h1; + vrfWholeIdxReadyTable_13 <= 1'h1; + vrfWholeIdxReadyTable_14 <= 1'h1; + vrfWholeIdxReadyTable_15 <= 1'h1; + vrfWholeIdxReadyTable_16 <= 1'h1; + vrfWholeIdxReadyTable_17 <= 1'h1; + vrfWholeIdxReadyTable_18 <= 1'h1; + vrfWholeIdxReadyTable_19 <= 1'h1; + vrfWholeIdxReadyTable_20 <= 1'h1; + vrfWholeIdxReadyTable_21 <= 1'h1; + vrfWholeIdxReadyTable_22 <= 1'h1; + vrfWholeIdxReadyTable_23 <= 1'h1; + vrfWholeIdxReadyTable_24 <= 1'h1; + vrfWholeIdxReadyTable_25 <= 1'h1; + vrfWholeIdxReadyTable_26 <= 1'h1; + vrfWholeIdxReadyTable_27 <= 1'h1; + vrfWholeIdxReadyTable_28 <= 1'h1; + vrfWholeIdxReadyTable_29 <= 1'h1; + vrfWholeIdxReadyTable_30 <= 1'h1; + vrfWholeIdxReadyTable_31 <= 1'h1; + vrfWriteSewTable_0_sew <= 3'h3; + vrfWriteSewTable_1_sew <= 3'h3; + vrfWriteSewTable_2_sew <= 3'h3; + vrfWriteSewTable_3_sew <= 3'h3; + vrfWriteSewTable_4_sew <= 3'h3; + vrfWriteSewTable_5_sew <= 3'h3; + vrfWriteSewTable_6_sew <= 3'h3; + vrfWriteSewTable_7_sew <= 3'h3; + vrfWriteSewTable_8_sew <= 3'h3; + vrfWriteSewTable_9_sew <= 3'h3; + vrfWriteSewTable_10_sew <= 3'h3; + vrfWriteSewTable_11_sew <= 3'h3; + vrfWriteSewTable_12_sew <= 3'h3; + vrfWriteSewTable_13_sew <= 3'h3; + vrfWriteSewTable_14_sew <= 3'h3; + vrfWriteSewTable_15_sew <= 3'h3; + vrfWriteSewTable_16_sew <= 3'h3; + vrfWriteSewTable_17_sew <= 3'h3; + vrfWriteSewTable_18_sew <= 3'h3; + vrfWriteSewTable_19_sew <= 3'h3; + vrfWriteSewTable_20_sew <= 3'h3; + vrfWriteSewTable_21_sew <= 3'h3; + vrfWriteSewTable_22_sew <= 3'h3; + vrfWriteSewTable_23_sew <= 3'h3; + vrfWriteSewTable_24_sew <= 3'h3; + vrfWriteSewTable_25_sew <= 3'h3; + vrfWriteSewTable_26_sew <= 3'h3; + vrfWriteSewTable_27_sew <= 3'h3; + vrfWriteSewTable_28_sew <= 3'h3; + vrfWriteSewTable_29_sew <= 3'h3; + vrfWriteSewTable_30_sew <= 3'h3; + vrfWriteSewTable_31_sew <= 3'h3; + end + else begin + automatic logic _T_1 = + io_fromVecExecUnit_0_valid & io_fromVecExecUnit_0_bits_index == 5'h0; + automatic logic _GEN_2; + automatic logic _GEN_3 = io_fromVecExecUnit_0_bits_vd == 5'h1; + automatic logic _GEN_4; + automatic logic _GEN_5 = io_fromVecExecUnit_0_bits_vd == 5'h2; + automatic logic _GEN_6; + automatic logic _GEN_7 = io_fromVecExecUnit_0_bits_vd == 5'h3; + automatic logic _GEN_8; + automatic logic _GEN_9 = io_fromVecExecUnit_0_bits_vd == 5'h4; + automatic logic _GEN_10; + automatic logic _GEN_11 = io_fromVecExecUnit_0_bits_vd == 5'h5; + automatic logic _GEN_12; + automatic logic _GEN_13 = io_fromVecExecUnit_0_bits_vd == 5'h6; + automatic logic _GEN_14; + automatic logic _GEN_15 = io_fromVecExecUnit_0_bits_vd == 5'h7; + automatic logic _GEN_16; + automatic logic _GEN_17 = io_fromVecExecUnit_0_bits_vd == 5'h8; + automatic logic _GEN_18; + automatic logic _GEN_19 = io_fromVecExecUnit_0_bits_vd == 5'h9; + automatic logic _GEN_20; + automatic logic _GEN_21 = io_fromVecExecUnit_0_bits_vd == 5'hA; + automatic logic _GEN_22; + automatic logic _GEN_23 = io_fromVecExecUnit_0_bits_vd == 5'hB; + automatic logic _GEN_24; + automatic logic _GEN_25 = io_fromVecExecUnit_0_bits_vd == 5'hC; + automatic logic _GEN_26; + automatic logic _GEN_27 = io_fromVecExecUnit_0_bits_vd == 5'hD; + automatic logic _GEN_28; + automatic logic _GEN_29 = io_fromVecExecUnit_0_bits_vd == 5'hE; + automatic logic _GEN_30; + automatic logic _GEN_31 = io_fromVecExecUnit_0_bits_vd == 5'hF; + automatic logic _GEN_32; + automatic logic _GEN_33 = io_fromVecExecUnit_0_bits_vd == 5'h10; + automatic logic _GEN_34; + automatic logic _GEN_35 = io_fromVecExecUnit_0_bits_vd == 5'h11; + automatic logic _GEN_36; + automatic logic _GEN_37 = io_fromVecExecUnit_0_bits_vd == 5'h12; + automatic logic _GEN_38; + automatic logic _GEN_39 = io_fromVecExecUnit_0_bits_vd == 5'h13; + automatic logic _GEN_40; + automatic logic _GEN_41 = io_fromVecExecUnit_0_bits_vd == 5'h14; + automatic logic _GEN_42; + automatic logic _GEN_43 = io_fromVecExecUnit_0_bits_vd == 5'h15; + automatic logic _GEN_44; + automatic logic _GEN_45 = io_fromVecExecUnit_0_bits_vd == 5'h16; + automatic logic _GEN_46; + automatic logic _GEN_47 = io_fromVecExecUnit_0_bits_vd == 5'h17; + automatic logic _GEN_48; + automatic logic _GEN_49 = io_fromVecExecUnit_0_bits_vd == 5'h18; + automatic logic _GEN_50; + automatic logic _GEN_51 = io_fromVecExecUnit_0_bits_vd == 5'h19; + automatic logic _GEN_52; + automatic logic _GEN_53 = io_fromVecExecUnit_0_bits_vd == 5'h1A; + automatic logic _GEN_54; + automatic logic _GEN_55 = io_fromVecExecUnit_0_bits_vd == 5'h1B; + automatic logic _GEN_56; + automatic logic _GEN_57 = io_fromVecExecUnit_0_bits_vd == 5'h1C; + automatic logic _GEN_58; + automatic logic _GEN_59 = io_fromVecExecUnit_0_bits_vd == 5'h1D; + automatic logic _GEN_60; + automatic logic _GEN_61 = io_fromVecExecUnit_0_bits_vd == 5'h1E; + automatic logic _GEN_62; + automatic logic _GEN_63; + automatic logic _T_3; + automatic logic _GEN_64; + automatic logic _GEN_65; + automatic logic _GEN_66; + automatic logic _GEN_67; + automatic logic _GEN_68; + automatic logic _GEN_69; + automatic logic _GEN_70; + automatic logic _GEN_71; + automatic logic _GEN_72; + automatic logic _GEN_73; + automatic logic _GEN_74; + automatic logic _GEN_75; + automatic logic _GEN_76; + automatic logic _GEN_77; + automatic logic _GEN_78; + automatic logic _GEN_79; + automatic logic _GEN_80; + automatic logic _GEN_81; + automatic logic _GEN_82; + automatic logic _GEN_83; + automatic logic _GEN_84; + automatic logic _GEN_85; + automatic logic _GEN_86; + automatic logic _GEN_87; + automatic logic _GEN_88; + automatic logic _GEN_89; + automatic logic _GEN_90; + automatic logic _GEN_91; + automatic logic _GEN_92; + automatic logic _GEN_93; + automatic logic _GEN_94; + automatic logic _T_5 = + io_fromVecExecUnit_2_valid & io_fromVecExecUnit_2_bits_index == 5'h0; + automatic logic _GEN_95 = + io_fromVecExecUnit_2_valid & _T_5 & ~(|io_fromVecExecUnit_2_bits_vd); + automatic logic _GEN_96 = io_fromVecExecUnit_2_bits_vd == 5'h1; + automatic logic _GEN_97 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_96; + automatic logic _GEN_98 = io_fromVecExecUnit_2_bits_vd == 5'h2; + automatic logic _GEN_99 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_98; + automatic logic _GEN_100 = io_fromVecExecUnit_2_bits_vd == 5'h3; + automatic logic _GEN_101 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_100; + automatic logic _GEN_102 = io_fromVecExecUnit_2_bits_vd == 5'h4; + automatic logic _GEN_103 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_102; + automatic logic _GEN_104 = io_fromVecExecUnit_2_bits_vd == 5'h5; + automatic logic _GEN_105 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_104; + automatic logic _GEN_106 = io_fromVecExecUnit_2_bits_vd == 5'h6; + automatic logic _GEN_107 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_106; + automatic logic _GEN_108 = io_fromVecExecUnit_2_bits_vd == 5'h7; + automatic logic _GEN_109 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_108; + automatic logic _GEN_110 = io_fromVecExecUnit_2_bits_vd == 5'h8; + automatic logic _GEN_111 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_110; + automatic logic _GEN_112 = io_fromVecExecUnit_2_bits_vd == 5'h9; + automatic logic _GEN_113 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_112; + automatic logic _GEN_114 = io_fromVecExecUnit_2_bits_vd == 5'hA; + automatic logic _GEN_115 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_114; + automatic logic _GEN_116 = io_fromVecExecUnit_2_bits_vd == 5'hB; + automatic logic _GEN_117 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_116; + automatic logic _GEN_118 = io_fromVecExecUnit_2_bits_vd == 5'hC; + automatic logic _GEN_119 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_118; + automatic logic _GEN_120 = io_fromVecExecUnit_2_bits_vd == 5'hD; + automatic logic _GEN_121 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_120; + automatic logic _GEN_122 = io_fromVecExecUnit_2_bits_vd == 5'hE; + automatic logic _GEN_123 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_122; + automatic logic _GEN_124 = io_fromVecExecUnit_2_bits_vd == 5'hF; + automatic logic _GEN_125 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_124; + automatic logic _GEN_126 = io_fromVecExecUnit_2_bits_vd == 5'h10; + automatic logic _GEN_127 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_126; + automatic logic _GEN_128 = io_fromVecExecUnit_2_bits_vd == 5'h11; + automatic logic _GEN_129 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_128; + automatic logic _GEN_130 = io_fromVecExecUnit_2_bits_vd == 5'h12; + automatic logic _GEN_131 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_130; + automatic logic _GEN_132 = io_fromVecExecUnit_2_bits_vd == 5'h13; + automatic logic _GEN_133 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_132; + automatic logic _GEN_134 = io_fromVecExecUnit_2_bits_vd == 5'h14; + automatic logic _GEN_135 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_134; + automatic logic _GEN_136 = io_fromVecExecUnit_2_bits_vd == 5'h15; + automatic logic _GEN_137 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_136; + automatic logic _GEN_138 = io_fromVecExecUnit_2_bits_vd == 5'h16; + automatic logic _GEN_139 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_138; + automatic logic _GEN_140 = io_fromVecExecUnit_2_bits_vd == 5'h17; + automatic logic _GEN_141 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_140; + automatic logic _GEN_142 = io_fromVecExecUnit_2_bits_vd == 5'h18; + automatic logic _GEN_143 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_142; + automatic logic _GEN_144 = io_fromVecExecUnit_2_bits_vd == 5'h19; + automatic logic _GEN_145 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_144; + automatic logic _GEN_146 = io_fromVecExecUnit_2_bits_vd == 5'h1A; + automatic logic _GEN_147 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_146; + automatic logic _GEN_148 = io_fromVecExecUnit_2_bits_vd == 5'h1B; + automatic logic _GEN_149 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_148; + automatic logic _GEN_150 = io_fromVecExecUnit_2_bits_vd == 5'h1C; + automatic logic _GEN_151 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_150; + automatic logic _GEN_152 = io_fromVecExecUnit_2_bits_vd == 5'h1D; + automatic logic _GEN_153 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_152; + automatic logic _GEN_154 = io_fromVecExecUnit_2_bits_vd == 5'h1E; + automatic logic _GEN_155 = io_fromVecExecUnit_2_valid & _T_5 & _GEN_154; + automatic logic _GEN_156 = + io_fromVecExecUnit_2_valid & _T_5 & (&io_fromVecExecUnit_2_bits_vd); + automatic logic _T_6 = io_fromVecExecUnit_0_valid & io_fromVecExecUnit_0_bits_last; + automatic logic otherWritesSameVd = + io_fromVecExecUnit_1_valid + & io_fromVecExecUnit_1_bits_vd == io_fromVecExecUnit_0_bits_vd + | io_fromVecExecUnit_2_valid + & io_fromVecExecUnit_2_bits_vd == io_fromVecExecUnit_0_bits_vd; + automatic logic _GEN_157 = + _T_6 & ~otherWritesSameVd & ~(|io_fromVecExecUnit_0_bits_vd); + automatic logic _GEN_158 = _T_6 & ~otherWritesSameVd & _GEN_3; + automatic logic _GEN_159 = _T_6 & ~otherWritesSameVd & _GEN_5; + automatic logic _GEN_160 = _T_6 & ~otherWritesSameVd & _GEN_7; + automatic logic _GEN_161 = _T_6 & ~otherWritesSameVd & _GEN_9; + automatic logic _GEN_162 = _T_6 & ~otherWritesSameVd & _GEN_11; + automatic logic _GEN_163 = _T_6 & ~otherWritesSameVd & _GEN_13; + automatic logic _GEN_164 = _T_6 & ~otherWritesSameVd & _GEN_15; + automatic logic _GEN_165 = _T_6 & ~otherWritesSameVd & _GEN_17; + automatic logic _GEN_166 = _T_6 & ~otherWritesSameVd & _GEN_19; + automatic logic _GEN_167 = _T_6 & ~otherWritesSameVd & _GEN_21; + automatic logic _GEN_168 = _T_6 & ~otherWritesSameVd & _GEN_23; + automatic logic _GEN_169 = _T_6 & ~otherWritesSameVd & _GEN_25; + automatic logic _GEN_170 = _T_6 & ~otherWritesSameVd & _GEN_27; + automatic logic _GEN_171 = _T_6 & ~otherWritesSameVd & _GEN_29; + automatic logic _GEN_172 = _T_6 & ~otherWritesSameVd & _GEN_31; + automatic logic _GEN_173 = _T_6 & ~otherWritesSameVd & _GEN_33; + automatic logic _GEN_174 = _T_6 & ~otherWritesSameVd & _GEN_35; + automatic logic _GEN_175 = _T_6 & ~otherWritesSameVd & _GEN_37; + automatic logic _GEN_176 = _T_6 & ~otherWritesSameVd & _GEN_39; + automatic logic _GEN_177 = _T_6 & ~otherWritesSameVd & _GEN_41; + automatic logic _GEN_178 = _T_6 & ~otherWritesSameVd & _GEN_43; + automatic logic _GEN_179 = _T_6 & ~otherWritesSameVd & _GEN_45; + automatic logic _GEN_180 = _T_6 & ~otherWritesSameVd & _GEN_47; + automatic logic _GEN_181 = _T_6 & ~otherWritesSameVd & _GEN_49; + automatic logic _GEN_182 = _T_6 & ~otherWritesSameVd & _GEN_51; + automatic logic _GEN_183 = _T_6 & ~otherWritesSameVd & _GEN_53; + automatic logic _GEN_184 = _T_6 & ~otherWritesSameVd & _GEN_55; + automatic logic _GEN_185 = _T_6 & ~otherWritesSameVd & _GEN_57; + automatic logic _GEN_186 = _T_6 & ~otherWritesSameVd & _GEN_59; + automatic logic _GEN_187 = _T_6 & ~otherWritesSameVd & _GEN_61; + automatic logic _GEN_188 = + _T_6 & ~otherWritesSameVd & (&io_fromVecExecUnit_0_bits_vd); + automatic logic _GEN_189 = + io_fromVecExecUnit_1_valid & io_fromVecExecUnit_1_bits_last + & ~(io_fromVecExecUnit_0_valid + & io_fromVecExecUnit_0_bits_vd == io_fromVecExecUnit_1_bits_vd + | io_fromVecExecUnit_2_valid + & io_fromVecExecUnit_2_bits_vd == io_fromVecExecUnit_1_bits_vd); + automatic logic _T_10 = io_fromVecExecUnit_2_valid & io_fromVecExecUnit_2_bits_last; + automatic logic otherWritesSameVd_2 = + io_fromVecExecUnit_0_valid + & io_fromVecExecUnit_0_bits_vd == io_fromVecExecUnit_2_bits_vd + | io_fromVecExecUnit_1_valid + & io_fromVecExecUnit_1_bits_vd == io_fromVecExecUnit_2_bits_vd; + automatic logic _GEN_190 = io_invalidateVd & io_vdCheck_bits_idx == 5'h0; + automatic logic _GEN_191 = io_invalidateVd & io_vdCheck_bits_idx == 5'h1; + automatic logic _GEN_192 = io_invalidateVd & io_vdCheck_bits_idx == 5'h2; + automatic logic _GEN_193 = io_invalidateVd & io_vdCheck_bits_idx == 5'h3; + automatic logic _GEN_194 = io_invalidateVd & io_vdCheck_bits_idx == 5'h4; + automatic logic _GEN_195 = io_invalidateVd & io_vdCheck_bits_idx == 5'h5; + automatic logic _GEN_196 = io_invalidateVd & io_vdCheck_bits_idx == 5'h6; + automatic logic _GEN_197 = io_invalidateVd & io_vdCheck_bits_idx == 5'h7; + automatic logic _GEN_198 = io_invalidateVd & io_vdCheck_bits_idx == 5'h8; + automatic logic _GEN_199 = io_invalidateVd & io_vdCheck_bits_idx == 5'h9; + automatic logic _GEN_200 = io_invalidateVd & io_vdCheck_bits_idx == 5'hA; + automatic logic _GEN_201 = io_invalidateVd & io_vdCheck_bits_idx == 5'hB; + automatic logic _GEN_202 = io_invalidateVd & io_vdCheck_bits_idx == 5'hC; + automatic logic _GEN_203 = io_invalidateVd & io_vdCheck_bits_idx == 5'hD; + automatic logic _GEN_204 = io_invalidateVd & io_vdCheck_bits_idx == 5'hE; + automatic logic _GEN_205 = io_invalidateVd & io_vdCheck_bits_idx == 5'hF; + automatic logic _GEN_206 = io_invalidateVd & io_vdCheck_bits_idx == 5'h10; + automatic logic _GEN_207 = io_invalidateVd & io_vdCheck_bits_idx == 5'h11; + automatic logic _GEN_208 = io_invalidateVd & io_vdCheck_bits_idx == 5'h12; + automatic logic _GEN_209 = io_invalidateVd & io_vdCheck_bits_idx == 5'h13; + automatic logic _GEN_210 = io_invalidateVd & io_vdCheck_bits_idx == 5'h14; + automatic logic _GEN_211 = io_invalidateVd & io_vdCheck_bits_idx == 5'h15; + automatic logic _GEN_212 = io_invalidateVd & io_vdCheck_bits_idx == 5'h16; + automatic logic _GEN_213 = io_invalidateVd & io_vdCheck_bits_idx == 5'h17; + automatic logic _GEN_214 = io_invalidateVd & io_vdCheck_bits_idx == 5'h18; + automatic logic _GEN_215 = io_invalidateVd & io_vdCheck_bits_idx == 5'h19; + automatic logic _GEN_216 = io_invalidateVd & io_vdCheck_bits_idx == 5'h1A; + automatic logic _GEN_217 = io_invalidateVd & io_vdCheck_bits_idx == 5'h1B; + automatic logic _GEN_218 = io_invalidateVd & io_vdCheck_bits_idx == 5'h1C; + automatic logic _GEN_219 = io_invalidateVd & io_vdCheck_bits_idx == 5'h1D; + automatic logic _GEN_220 = io_invalidateVd & io_vdCheck_bits_idx == 5'h1E; + automatic logic _GEN_221 = io_invalidateVd & (&io_vdCheck_bits_idx); + _GEN_2 = io_fromVecExecUnit_0_valid & _T_1 & ~(|io_fromVecExecUnit_0_bits_vd); + _GEN_4 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_3; + _GEN_6 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_5; + _GEN_8 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_7; + _GEN_10 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_9; + _GEN_12 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_11; + _GEN_14 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_13; + _GEN_16 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_15; + _GEN_18 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_17; + _GEN_20 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_19; + _GEN_22 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_21; + _GEN_24 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_23; + _GEN_26 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_25; + _GEN_28 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_27; + _GEN_30 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_29; + _GEN_32 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_31; + _GEN_34 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_33; + _GEN_36 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_35; + _GEN_38 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_37; + _GEN_40 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_39; + _GEN_42 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_41; + _GEN_44 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_43; + _GEN_46 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_45; + _GEN_48 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_47; + _GEN_50 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_49; + _GEN_52 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_51; + _GEN_54 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_53; + _GEN_56 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_55; + _GEN_58 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_57; + _GEN_60 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_59; + _GEN_62 = io_fromVecExecUnit_0_valid & _T_1 & _GEN_61; + _GEN_63 = io_fromVecExecUnit_0_valid & _T_1 & (&io_fromVecExecUnit_0_bits_vd); + _T_3 = io_fromVecExecUnit_1_valid & io_fromVecExecUnit_1_bits_index == 5'h0; + _GEN_64 = io_fromVecExecUnit_1_valid & _T_3; + _GEN_65 = io_fromVecExecUnit_1_bits_vd == 5'h1; + _GEN_66 = io_fromVecExecUnit_1_bits_vd == 5'h2; + _GEN_67 = io_fromVecExecUnit_1_bits_vd == 5'h3; + _GEN_68 = io_fromVecExecUnit_1_bits_vd == 5'h4; + _GEN_69 = io_fromVecExecUnit_1_bits_vd == 5'h5; + _GEN_70 = io_fromVecExecUnit_1_bits_vd == 5'h6; + _GEN_71 = io_fromVecExecUnit_1_bits_vd == 5'h7; + _GEN_72 = io_fromVecExecUnit_1_bits_vd == 5'h8; + _GEN_73 = io_fromVecExecUnit_1_bits_vd == 5'h9; + _GEN_74 = io_fromVecExecUnit_1_bits_vd == 5'hA; + _GEN_75 = io_fromVecExecUnit_1_bits_vd == 5'hB; + _GEN_76 = io_fromVecExecUnit_1_bits_vd == 5'hC; + _GEN_77 = io_fromVecExecUnit_1_bits_vd == 5'hD; + _GEN_78 = io_fromVecExecUnit_1_bits_vd == 5'hE; + _GEN_79 = io_fromVecExecUnit_1_bits_vd == 5'hF; + _GEN_80 = io_fromVecExecUnit_1_bits_vd == 5'h10; + _GEN_81 = io_fromVecExecUnit_1_bits_vd == 5'h11; + _GEN_82 = io_fromVecExecUnit_1_bits_vd == 5'h12; + _GEN_83 = io_fromVecExecUnit_1_bits_vd == 5'h13; + _GEN_84 = io_fromVecExecUnit_1_bits_vd == 5'h14; + _GEN_85 = io_fromVecExecUnit_1_bits_vd == 5'h15; + _GEN_86 = io_fromVecExecUnit_1_bits_vd == 5'h16; + _GEN_87 = io_fromVecExecUnit_1_bits_vd == 5'h17; + _GEN_88 = io_fromVecExecUnit_1_bits_vd == 5'h18; + _GEN_89 = io_fromVecExecUnit_1_bits_vd == 5'h19; + _GEN_90 = io_fromVecExecUnit_1_bits_vd == 5'h1A; + _GEN_91 = io_fromVecExecUnit_1_bits_vd == 5'h1B; + _GEN_92 = io_fromVecExecUnit_1_bits_vd == 5'h1C; + _GEN_93 = io_fromVecExecUnit_1_bits_vd == 5'h1D; + _GEN_94 = io_fromVecExecUnit_1_bits_vd == 5'h1E; + vrfZeroIdxReadyTable_0 <= + ~_GEN_190 + & (_GEN_95 + | (_GEN_64 + ? ~(|io_fromVecExecUnit_1_bits_vd) | _GEN_2 | vrfZeroIdxReadyTable_0 + : _GEN_2 | vrfZeroIdxReadyTable_0)); + vrfZeroIdxReadyTable_1 <= + ~_GEN_191 + & (_GEN_97 + | (_GEN_64 + ? _GEN_65 | _GEN_4 | vrfZeroIdxReadyTable_1 + : _GEN_4 | vrfZeroIdxReadyTable_1)); + vrfZeroIdxReadyTable_2 <= + ~_GEN_192 + & (_GEN_99 + | (_GEN_64 + ? _GEN_66 | _GEN_6 | vrfZeroIdxReadyTable_2 + : _GEN_6 | vrfZeroIdxReadyTable_2)); + vrfZeroIdxReadyTable_3 <= + ~_GEN_193 + & (_GEN_101 + | (_GEN_64 + ? _GEN_67 | _GEN_8 | vrfZeroIdxReadyTable_3 + : _GEN_8 | vrfZeroIdxReadyTable_3)); + vrfZeroIdxReadyTable_4 <= + ~_GEN_194 + & (_GEN_103 + | (_GEN_64 + ? _GEN_68 | _GEN_10 | vrfZeroIdxReadyTable_4 + : _GEN_10 | vrfZeroIdxReadyTable_4)); + vrfZeroIdxReadyTable_5 <= + ~_GEN_195 + & (_GEN_105 + | (_GEN_64 + ? _GEN_69 | _GEN_12 | vrfZeroIdxReadyTable_5 + : _GEN_12 | vrfZeroIdxReadyTable_5)); + vrfZeroIdxReadyTable_6 <= + ~_GEN_196 + & (_GEN_107 + | (_GEN_64 + ? _GEN_70 | _GEN_14 | vrfZeroIdxReadyTable_6 + : _GEN_14 | vrfZeroIdxReadyTable_6)); + vrfZeroIdxReadyTable_7 <= + ~_GEN_197 + & (_GEN_109 + | (_GEN_64 + ? _GEN_71 | _GEN_16 | vrfZeroIdxReadyTable_7 + : _GEN_16 | vrfZeroIdxReadyTable_7)); + vrfZeroIdxReadyTable_8 <= + ~_GEN_198 + & (_GEN_111 + | (_GEN_64 + ? _GEN_72 | _GEN_18 | vrfZeroIdxReadyTable_8 + : _GEN_18 | vrfZeroIdxReadyTable_8)); + vrfZeroIdxReadyTable_9 <= + ~_GEN_199 + & (_GEN_113 + | (_GEN_64 + ? _GEN_73 | _GEN_20 | vrfZeroIdxReadyTable_9 + : _GEN_20 | vrfZeroIdxReadyTable_9)); + vrfZeroIdxReadyTable_10 <= + ~_GEN_200 + & (_GEN_115 + | (_GEN_64 + ? _GEN_74 | _GEN_22 | vrfZeroIdxReadyTable_10 + : _GEN_22 | vrfZeroIdxReadyTable_10)); + vrfZeroIdxReadyTable_11 <= + ~_GEN_201 + & (_GEN_117 + | (_GEN_64 + ? _GEN_75 | _GEN_24 | vrfZeroIdxReadyTable_11 + : _GEN_24 | vrfZeroIdxReadyTable_11)); + vrfZeroIdxReadyTable_12 <= + ~_GEN_202 + & (_GEN_119 + | (_GEN_64 + ? _GEN_76 | _GEN_26 | vrfZeroIdxReadyTable_12 + : _GEN_26 | vrfZeroIdxReadyTable_12)); + vrfZeroIdxReadyTable_13 <= + ~_GEN_203 + & (_GEN_121 + | (_GEN_64 + ? _GEN_77 | _GEN_28 | vrfZeroIdxReadyTable_13 + : _GEN_28 | vrfZeroIdxReadyTable_13)); + vrfZeroIdxReadyTable_14 <= + ~_GEN_204 + & (_GEN_123 + | (_GEN_64 + ? _GEN_78 | _GEN_30 | vrfZeroIdxReadyTable_14 + : _GEN_30 | vrfZeroIdxReadyTable_14)); + vrfZeroIdxReadyTable_15 <= + ~_GEN_205 + & (_GEN_125 + | (_GEN_64 + ? _GEN_79 | _GEN_32 | vrfZeroIdxReadyTable_15 + : _GEN_32 | vrfZeroIdxReadyTable_15)); + vrfZeroIdxReadyTable_16 <= + ~_GEN_206 + & (_GEN_127 + | (_GEN_64 + ? _GEN_80 | _GEN_34 | vrfZeroIdxReadyTable_16 + : _GEN_34 | vrfZeroIdxReadyTable_16)); + vrfZeroIdxReadyTable_17 <= + ~_GEN_207 + & (_GEN_129 + | (_GEN_64 + ? _GEN_81 | _GEN_36 | vrfZeroIdxReadyTable_17 + : _GEN_36 | vrfZeroIdxReadyTable_17)); + vrfZeroIdxReadyTable_18 <= + ~_GEN_208 + & (_GEN_131 + | (_GEN_64 + ? _GEN_82 | _GEN_38 | vrfZeroIdxReadyTable_18 + : _GEN_38 | vrfZeroIdxReadyTable_18)); + vrfZeroIdxReadyTable_19 <= + ~_GEN_209 + & (_GEN_133 + | (_GEN_64 + ? _GEN_83 | _GEN_40 | vrfZeroIdxReadyTable_19 + : _GEN_40 | vrfZeroIdxReadyTable_19)); + vrfZeroIdxReadyTable_20 <= + ~_GEN_210 + & (_GEN_135 + | (_GEN_64 + ? _GEN_84 | _GEN_42 | vrfZeroIdxReadyTable_20 + : _GEN_42 | vrfZeroIdxReadyTable_20)); + vrfZeroIdxReadyTable_21 <= + ~_GEN_211 + & (_GEN_137 + | (_GEN_64 + ? _GEN_85 | _GEN_44 | vrfZeroIdxReadyTable_21 + : _GEN_44 | vrfZeroIdxReadyTable_21)); + vrfZeroIdxReadyTable_22 <= + ~_GEN_212 + & (_GEN_139 + | (_GEN_64 + ? _GEN_86 | _GEN_46 | vrfZeroIdxReadyTable_22 + : _GEN_46 | vrfZeroIdxReadyTable_22)); + vrfZeroIdxReadyTable_23 <= + ~_GEN_213 + & (_GEN_141 + | (_GEN_64 + ? _GEN_87 | _GEN_48 | vrfZeroIdxReadyTable_23 + : _GEN_48 | vrfZeroIdxReadyTable_23)); + vrfZeroIdxReadyTable_24 <= + ~_GEN_214 + & (_GEN_143 + | (_GEN_64 + ? _GEN_88 | _GEN_50 | vrfZeroIdxReadyTable_24 + : _GEN_50 | vrfZeroIdxReadyTable_24)); + vrfZeroIdxReadyTable_25 <= + ~_GEN_215 + & (_GEN_145 + | (_GEN_64 + ? _GEN_89 | _GEN_52 | vrfZeroIdxReadyTable_25 + : _GEN_52 | vrfZeroIdxReadyTable_25)); + vrfZeroIdxReadyTable_26 <= + ~_GEN_216 + & (_GEN_147 + | (_GEN_64 + ? _GEN_90 | _GEN_54 | vrfZeroIdxReadyTable_26 + : _GEN_54 | vrfZeroIdxReadyTable_26)); + vrfZeroIdxReadyTable_27 <= + ~_GEN_217 + & (_GEN_149 + | (_GEN_64 + ? _GEN_91 | _GEN_56 | vrfZeroIdxReadyTable_27 + : _GEN_56 | vrfZeroIdxReadyTable_27)); + vrfZeroIdxReadyTable_28 <= + ~_GEN_218 + & (_GEN_151 + | (_GEN_64 + ? _GEN_92 | _GEN_58 | vrfZeroIdxReadyTable_28 + : _GEN_58 | vrfZeroIdxReadyTable_28)); + vrfZeroIdxReadyTable_29 <= + ~_GEN_219 + & (_GEN_153 + | (_GEN_64 + ? _GEN_93 | _GEN_60 | vrfZeroIdxReadyTable_29 + : _GEN_60 | vrfZeroIdxReadyTable_29)); + vrfZeroIdxReadyTable_30 <= + ~_GEN_220 + & (_GEN_155 + | (_GEN_64 + ? _GEN_94 | _GEN_62 | vrfZeroIdxReadyTable_30 + : _GEN_62 | vrfZeroIdxReadyTable_30)); + vrfZeroIdxReadyTable_31 <= + ~_GEN_221 + & (_GEN_156 + | (_GEN_64 + ? (&io_fromVecExecUnit_1_bits_vd) | _GEN_63 | vrfZeroIdxReadyTable_31 + : _GEN_63 | vrfZeroIdxReadyTable_31)); + vrfWholeIdxReadyTable_0 <= + ~_GEN_190 + & (_T_10 & ~otherWritesSameVd_2 & ~(|io_fromVecExecUnit_2_bits_vd) + | (_GEN_189 + ? ~(|io_fromVecExecUnit_1_bits_vd) | _GEN_157 | vrfWholeIdxReadyTable_0 + : _GEN_157 | vrfWholeIdxReadyTable_0)); + vrfWholeIdxReadyTable_1 <= + ~_GEN_191 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_96 + | (_GEN_189 + ? _GEN_65 | _GEN_158 | vrfWholeIdxReadyTable_1 + : _GEN_158 | vrfWholeIdxReadyTable_1)); + vrfWholeIdxReadyTable_2 <= + ~_GEN_192 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_98 + | (_GEN_189 + ? _GEN_66 | _GEN_159 | vrfWholeIdxReadyTable_2 + : _GEN_159 | vrfWholeIdxReadyTable_2)); + vrfWholeIdxReadyTable_3 <= + ~_GEN_193 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_100 + | (_GEN_189 + ? _GEN_67 | _GEN_160 | vrfWholeIdxReadyTable_3 + : _GEN_160 | vrfWholeIdxReadyTable_3)); + vrfWholeIdxReadyTable_4 <= + ~_GEN_194 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_102 + | (_GEN_189 + ? _GEN_68 | _GEN_161 | vrfWholeIdxReadyTable_4 + : _GEN_161 | vrfWholeIdxReadyTable_4)); + vrfWholeIdxReadyTable_5 <= + ~_GEN_195 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_104 + | (_GEN_189 + ? _GEN_69 | _GEN_162 | vrfWholeIdxReadyTable_5 + : _GEN_162 | vrfWholeIdxReadyTable_5)); + vrfWholeIdxReadyTable_6 <= + ~_GEN_196 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_106 + | (_GEN_189 + ? _GEN_70 | _GEN_163 | vrfWholeIdxReadyTable_6 + : _GEN_163 | vrfWholeIdxReadyTable_6)); + vrfWholeIdxReadyTable_7 <= + ~_GEN_197 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_108 + | (_GEN_189 + ? _GEN_71 | _GEN_164 | vrfWholeIdxReadyTable_7 + : _GEN_164 | vrfWholeIdxReadyTable_7)); + vrfWholeIdxReadyTable_8 <= + ~_GEN_198 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_110 + | (_GEN_189 + ? _GEN_72 | _GEN_165 | vrfWholeIdxReadyTable_8 + : _GEN_165 | vrfWholeIdxReadyTable_8)); + vrfWholeIdxReadyTable_9 <= + ~_GEN_199 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_112 + | (_GEN_189 + ? _GEN_73 | _GEN_166 | vrfWholeIdxReadyTable_9 + : _GEN_166 | vrfWholeIdxReadyTable_9)); + vrfWholeIdxReadyTable_10 <= + ~_GEN_200 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_114 + | (_GEN_189 + ? _GEN_74 | _GEN_167 | vrfWholeIdxReadyTable_10 + : _GEN_167 | vrfWholeIdxReadyTable_10)); + vrfWholeIdxReadyTable_11 <= + ~_GEN_201 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_116 + | (_GEN_189 + ? _GEN_75 | _GEN_168 | vrfWholeIdxReadyTable_11 + : _GEN_168 | vrfWholeIdxReadyTable_11)); + vrfWholeIdxReadyTable_12 <= + ~_GEN_202 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_118 + | (_GEN_189 + ? _GEN_76 | _GEN_169 | vrfWholeIdxReadyTable_12 + : _GEN_169 | vrfWholeIdxReadyTable_12)); + vrfWholeIdxReadyTable_13 <= + ~_GEN_203 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_120 + | (_GEN_189 + ? _GEN_77 | _GEN_170 | vrfWholeIdxReadyTable_13 + : _GEN_170 | vrfWholeIdxReadyTable_13)); + vrfWholeIdxReadyTable_14 <= + ~_GEN_204 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_122 + | (_GEN_189 + ? _GEN_78 | _GEN_171 | vrfWholeIdxReadyTable_14 + : _GEN_171 | vrfWholeIdxReadyTable_14)); + vrfWholeIdxReadyTable_15 <= + ~_GEN_205 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_124 + | (_GEN_189 + ? _GEN_79 | _GEN_172 | vrfWholeIdxReadyTable_15 + : _GEN_172 | vrfWholeIdxReadyTable_15)); + vrfWholeIdxReadyTable_16 <= + ~_GEN_206 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_126 + | (_GEN_189 + ? _GEN_80 | _GEN_173 | vrfWholeIdxReadyTable_16 + : _GEN_173 | vrfWholeIdxReadyTable_16)); + vrfWholeIdxReadyTable_17 <= + ~_GEN_207 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_128 + | (_GEN_189 + ? _GEN_81 | _GEN_174 | vrfWholeIdxReadyTable_17 + : _GEN_174 | vrfWholeIdxReadyTable_17)); + vrfWholeIdxReadyTable_18 <= + ~_GEN_208 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_130 + | (_GEN_189 + ? _GEN_82 | _GEN_175 | vrfWholeIdxReadyTable_18 + : _GEN_175 | vrfWholeIdxReadyTable_18)); + vrfWholeIdxReadyTable_19 <= + ~_GEN_209 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_132 + | (_GEN_189 + ? _GEN_83 | _GEN_176 | vrfWholeIdxReadyTable_19 + : _GEN_176 | vrfWholeIdxReadyTable_19)); + vrfWholeIdxReadyTable_20 <= + ~_GEN_210 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_134 + | (_GEN_189 + ? _GEN_84 | _GEN_177 | vrfWholeIdxReadyTable_20 + : _GEN_177 | vrfWholeIdxReadyTable_20)); + vrfWholeIdxReadyTable_21 <= + ~_GEN_211 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_136 + | (_GEN_189 + ? _GEN_85 | _GEN_178 | vrfWholeIdxReadyTable_21 + : _GEN_178 | vrfWholeIdxReadyTable_21)); + vrfWholeIdxReadyTable_22 <= + ~_GEN_212 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_138 + | (_GEN_189 + ? _GEN_86 | _GEN_179 | vrfWholeIdxReadyTable_22 + : _GEN_179 | vrfWholeIdxReadyTable_22)); + vrfWholeIdxReadyTable_23 <= + ~_GEN_213 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_140 + | (_GEN_189 + ? _GEN_87 | _GEN_180 | vrfWholeIdxReadyTable_23 + : _GEN_180 | vrfWholeIdxReadyTable_23)); + vrfWholeIdxReadyTable_24 <= + ~_GEN_214 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_142 + | (_GEN_189 + ? _GEN_88 | _GEN_181 | vrfWholeIdxReadyTable_24 + : _GEN_181 | vrfWholeIdxReadyTable_24)); + vrfWholeIdxReadyTable_25 <= + ~_GEN_215 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_144 + | (_GEN_189 + ? _GEN_89 | _GEN_182 | vrfWholeIdxReadyTable_25 + : _GEN_182 | vrfWholeIdxReadyTable_25)); + vrfWholeIdxReadyTable_26 <= + ~_GEN_216 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_146 + | (_GEN_189 + ? _GEN_90 | _GEN_183 | vrfWholeIdxReadyTable_26 + : _GEN_183 | vrfWholeIdxReadyTable_26)); + vrfWholeIdxReadyTable_27 <= + ~_GEN_217 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_148 + | (_GEN_189 + ? _GEN_91 | _GEN_184 | vrfWholeIdxReadyTable_27 + : _GEN_184 | vrfWholeIdxReadyTable_27)); + vrfWholeIdxReadyTable_28 <= + ~_GEN_218 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_150 + | (_GEN_189 + ? _GEN_92 | _GEN_185 | vrfWholeIdxReadyTable_28 + : _GEN_185 | vrfWholeIdxReadyTable_28)); + vrfWholeIdxReadyTable_29 <= + ~_GEN_219 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_152 + | (_GEN_189 + ? _GEN_93 | _GEN_186 | vrfWholeIdxReadyTable_29 + : _GEN_186 | vrfWholeIdxReadyTable_29)); + vrfWholeIdxReadyTable_30 <= + ~_GEN_220 + & (_T_10 & ~otherWritesSameVd_2 & _GEN_154 + | (_GEN_189 + ? _GEN_94 | _GEN_187 | vrfWholeIdxReadyTable_30 + : _GEN_187 | vrfWholeIdxReadyTable_30)); + vrfWholeIdxReadyTable_31 <= + ~_GEN_221 + & (_T_10 & ~otherWritesSameVd_2 & (&io_fromVecExecUnit_2_bits_vd) + | (_GEN_189 + ? (&io_fromVecExecUnit_1_bits_vd) | _GEN_188 | vrfWholeIdxReadyTable_31 + : _GEN_188 | vrfWholeIdxReadyTable_31)); + if (_GEN_95) + vrfWriteSewTable_0_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & ~(|io_fromVecExecUnit_1_bits_vd)) + vrfWriteSewTable_0_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_2) + vrfWriteSewTable_0_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_97) + vrfWriteSewTable_1_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_65) + vrfWriteSewTable_1_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_4) + vrfWriteSewTable_1_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_99) + vrfWriteSewTable_2_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_66) + vrfWriteSewTable_2_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_6) + vrfWriteSewTable_2_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_101) + vrfWriteSewTable_3_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_67) + vrfWriteSewTable_3_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_8) + vrfWriteSewTable_3_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_103) + vrfWriteSewTable_4_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_68) + vrfWriteSewTable_4_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_10) + vrfWriteSewTable_4_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_105) + vrfWriteSewTable_5_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_69) + vrfWriteSewTable_5_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_12) + vrfWriteSewTable_5_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_107) + vrfWriteSewTable_6_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_70) + vrfWriteSewTable_6_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_14) + vrfWriteSewTable_6_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_109) + vrfWriteSewTable_7_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_71) + vrfWriteSewTable_7_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_16) + vrfWriteSewTable_7_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_111) + vrfWriteSewTable_8_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_72) + vrfWriteSewTable_8_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_18) + vrfWriteSewTable_8_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_113) + vrfWriteSewTable_9_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_73) + vrfWriteSewTable_9_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_20) + vrfWriteSewTable_9_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_115) + vrfWriteSewTable_10_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_74) + vrfWriteSewTable_10_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_22) + vrfWriteSewTable_10_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_117) + vrfWriteSewTable_11_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_75) + vrfWriteSewTable_11_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_24) + vrfWriteSewTable_11_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_119) + vrfWriteSewTable_12_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_76) + vrfWriteSewTable_12_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_26) + vrfWriteSewTable_12_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_121) + vrfWriteSewTable_13_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_77) + vrfWriteSewTable_13_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_28) + vrfWriteSewTable_13_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_123) + vrfWriteSewTable_14_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_78) + vrfWriteSewTable_14_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_30) + vrfWriteSewTable_14_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_125) + vrfWriteSewTable_15_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_79) + vrfWriteSewTable_15_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_32) + vrfWriteSewTable_15_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_127) + vrfWriteSewTable_16_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_80) + vrfWriteSewTable_16_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_34) + vrfWriteSewTable_16_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_129) + vrfWriteSewTable_17_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_81) + vrfWriteSewTable_17_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_36) + vrfWriteSewTable_17_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_131) + vrfWriteSewTable_18_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_82) + vrfWriteSewTable_18_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_38) + vrfWriteSewTable_18_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_133) + vrfWriteSewTable_19_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_83) + vrfWriteSewTable_19_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_40) + vrfWriteSewTable_19_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_135) + vrfWriteSewTable_20_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_84) + vrfWriteSewTable_20_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_42) + vrfWriteSewTable_20_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_137) + vrfWriteSewTable_21_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_85) + vrfWriteSewTable_21_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_44) + vrfWriteSewTable_21_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_139) + vrfWriteSewTable_22_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_86) + vrfWriteSewTable_22_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_46) + vrfWriteSewTable_22_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_141) + vrfWriteSewTable_23_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_87) + vrfWriteSewTable_23_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_48) + vrfWriteSewTable_23_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_143) + vrfWriteSewTable_24_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_88) + vrfWriteSewTable_24_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_50) + vrfWriteSewTable_24_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_145) + vrfWriteSewTable_25_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_89) + vrfWriteSewTable_25_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_52) + vrfWriteSewTable_25_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_147) + vrfWriteSewTable_26_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_90) + vrfWriteSewTable_26_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_54) + vrfWriteSewTable_26_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_149) + vrfWriteSewTable_27_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_91) + vrfWriteSewTable_27_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_56) + vrfWriteSewTable_27_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_151) + vrfWriteSewTable_28_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_92) + vrfWriteSewTable_28_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_58) + vrfWriteSewTable_28_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_153) + vrfWriteSewTable_29_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_93) + vrfWriteSewTable_29_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_60) + vrfWriteSewTable_29_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_155) + vrfWriteSewTable_30_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & _GEN_94) + vrfWriteSewTable_30_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_62) + vrfWriteSewTable_30_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + if (_GEN_156) + vrfWriteSewTable_31_sew <= io_fromVecExecUnit_2_bits_vtype_vsew; + else if (io_fromVecExecUnit_1_valid & _T_3 & (&io_fromVecExecUnit_1_bits_vd)) + vrfWriteSewTable_31_sew <= io_fromVecExecUnit_1_bits_vtype_vsew; + else if (_GEN_63) + vrfWriteSewTable_31_sew <= io_fromVecExecUnit_0_bits_vtype_vsew; + end + end // always @(posedge) + assign io_vs1Check_ready = + io_vs1Check_valid + & (_GEN_0[io_vs1Check_bits_idx] + & (io_vs1Check_bits_vm | io_vs1Check_bits_vtype_vsew <= _GEN[io_vs1Check_bits_idx]) + | {1'h0, {1'h0, vs1SameWriteList_0} + {1'h0, vs1SameWriteList_1}} + + {2'h0, vs1SameWriteList_2} == 3'h1 + & {1'h0, + {1'h0, + vs1SameWriteList_0 + & (io_vs1Check_bits_vm + | io_vs1Check_bits_vtype_vsew <= io_fromVecExecUnit_0_bits_vtype_vsew)} + + {1'h0, + vs1SameWriteList_1 + & (io_vs1Check_bits_vm | ~io_fromVecExecUnit_1_bits_vm + & io_vs1Check_bits_vtype_vsew <= io_fromVecExecUnit_1_bits_vtype_vsew)}} + + {2'h0, + vs1SameWriteList_2 + & (io_vs1Check_bits_vm | ~io_fromVecExecUnit_2_bits_vm + & io_vs1Check_bits_vtype_vsew <= io_fromVecExecUnit_2_bits_vtype_vsew)} == 3'h1 + | _GEN_1[io_vs1Check_bits_idx]); + assign io_vs2Check_ready = + io_vs2Check_valid + & (_GEN_0[io_vs2Check_bits_idx] + & (io_vs2Check_bits_vm | io_vs2Check_bits_vtype_vsew <= _GEN[io_vs2Check_bits_idx]) + | {1'h0, {1'h0, vs2SameWriteList_0} + {1'h0, vs2SameWriteList_1}} + + {2'h0, vs2SameWriteList_2} == 3'h1 + & {1'h0, + {1'h0, + vs2SameWriteList_0 + & (io_vs2Check_bits_vm + | io_vs2Check_bits_vtype_vsew <= io_fromVecExecUnit_0_bits_vtype_vsew)} + + {1'h0, + vs2SameWriteList_1 + & (io_vs2Check_bits_vm | ~io_fromVecExecUnit_1_bits_vm + & io_vs2Check_bits_vtype_vsew <= io_fromVecExecUnit_1_bits_vtype_vsew)}} + + {2'h0, + vs2SameWriteList_2 + & (io_vs2Check_bits_vm | ~io_fromVecExecUnit_2_bits_vm + & io_vs2Check_bits_vtype_vsew <= io_fromVecExecUnit_2_bits_vtype_vsew)} == 3'h1 + | _GEN_1[io_vs2Check_bits_idx]); + assign io_vdCheck_ready = + io_vdCheck_valid + & (_GEN_0[io_vdCheck_bits_idx] + & (io_vdCheck_bits_vm | io_vdCheck_bits_vtype_vsew <= _GEN[io_vdCheck_bits_idx]) + | {1'h0, {1'h0, vdSameWriteList_0} + {1'h0, vdSameWriteList_1}} + + {2'h0, vdSameWriteList_2} == 3'h1 + & {1'h0, + {1'h0, + vdSameWriteList_0 + & (io_vdCheck_bits_vm + | io_vdCheck_bits_vtype_vsew <= io_fromVecExecUnit_0_bits_vtype_vsew)} + + {1'h0, + vdSameWriteList_1 + & (io_vdCheck_bits_vm | ~io_fromVecExecUnit_1_bits_vm + & io_vdCheck_bits_vtype_vsew <= io_fromVecExecUnit_1_bits_vtype_vsew)}} + + {2'h0, + vdSameWriteList_2 + & (io_vdCheck_bits_vm | ~io_fromVecExecUnit_2_bits_vm + & io_vdCheck_bits_vtype_vsew <= io_fromVecExecUnit_2_bits_vtype_vsew)} == 3'h1 + | _GEN_1[io_vdCheck_bits_idx]); + assign io_vmCheck_ready = + io_vmCheck_valid + & (vrfZeroIdxReadyTable_0 + | {1'h0, + {1'h0, _vdSameWriteList_T & ~(|io_fromVecExecUnit_0_bits_vd)} + + {1'h0, _vdSameWriteList_T_2 & ~(|io_fromVecExecUnit_1_bits_vd)}} + + {2'h0, _vdSameWriteList_T_4 & ~(|io_fromVecExecUnit_2_bits_vd)} == 3'h1 + | vrfWholeIdxReadyTable_0); +endmodule + +module IntegerAluExecUnit( + input clock, + reset, + io_signalIn_valid, + input [4:0] io_signalIn_bits_vs1, + io_signalIn_bits_vs2, + io_signalIn_bits_vd, + input [63:0] io_signalIn_bits_scalarVal, + input [5:0] io_signalIn_bits_vectorDecode_veuFun, + input [2:0] io_signalIn_bits_vectorDecode_vSource, + input io_signalIn_bits_vectorDecode_vm, + input [3:0] io_signalIn_bits_scalarDecode_branch, + input [2:0] io_signalIn_bits_scalarDecode_writeback_selector, + input [1:0] io_signalIn_bits_scalarDecode_memory_function, + input [2:0] io_signalIn_bits_scalarDecode_csr_funct, + input io_signalIn_bits_scalarDecode_fence, + io_signalIn_bits_vecConf_vtype_vill, + io_signalIn_bits_vecConf_vtype_vma, + io_signalIn_bits_vecConf_vtype_vta, + input [2:0] io_signalIn_bits_vecConf_vtype_vsew, + io_signalIn_bits_vecConf_vtype_vlmul, + input [5:0] io_signalIn_bits_vecConf_vl, + input [63:0] io_signalIn_bits_pc_addr, + io_readVrf_resp_vs1Out, + io_readVrf_resp_vs2Out, + io_readVrf_resp_vdOut, + input io_readVrf_resp_vm, + output io_signalIn_ready, + output [2:0] io_readVrf_req_sew, + output io_readVrf_req_readVdAsMaskSource, + output [4:0] io_readVrf_req_idx, + io_readVrf_req_vs1, + io_readVrf_req_vs2, + io_readVrf_req_vd, + output io_dataOut_toVRF_valid, + output [4:0] io_dataOut_toVRF_bits_vd, + output [2:0] io_dataOut_toVRF_bits_vtype_vsew, + output [4:0] io_dataOut_toVRF_bits_index, + output io_dataOut_toVRF_bits_last, + output [63:0] io_dataOut_toVRF_bits_data, + output io_dataOut_toVRF_bits_vm, + io_dataOut_toVRF_bits_writeReq, + io_toExWbReg_valid, + output [63:0] io_toExWbReg_bits_dataSignals_pc_addr, + io_toExWbReg_bits_dataSignals_exResult, + output [3:0] io_toExWbReg_bits_ctrlSignals_decode_branch, + output [2:0] io_toExWbReg_bits_ctrlSignals_decode_writeback_selector, + output [1:0] io_toExWbReg_bits_ctrlSignals_decode_memory_function, + output [2:0] io_toExWbReg_bits_ctrlSignals_decode_csr_funct, + output io_toExWbReg_bits_ctrlSignals_decode_fence, + output [4:0] io_toExWbReg_bits_ctrlSignals_rd_index, + output io_toExWbReg_bits_vectorCsrPorts_vtype_vill, + io_toExWbReg_bits_vectorCsrPorts_vtype_vma, + io_toExWbReg_bits_vectorCsrPorts_vtype_vta, + output [2:0] io_toExWbReg_bits_vectorCsrPorts_vtype_vsew, + io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul, + output [5:0] io_toExWbReg_bits_vectorCsrPorts_vl, + output io_toExWbReg_bits_vectorExecNum_valid, + output [4:0] io_toExWbReg_bits_vectorExecNum_bits +); + + wire _io_dataOut_toVRF_bits_writeReq_output; + wire _io_dataOut_toVRF_bits_last_output; + wire _io_dataOut_toVRF_valid_output; + wire valueToExec_vm; + wire [63:0] valueToExec_vs2Out; + wire [63:0] valueToExec_vs1Out; + reg instInfoReg_valid; + reg [4:0] instInfoReg_bits_vs1; + reg [4:0] instInfoReg_bits_vs2; + reg [4:0] instInfoReg_bits_vd; + reg [63:0] instInfoReg_bits_scalarVal; + reg [5:0] instInfoReg_bits_vectorDecode_veuFun; + reg [2:0] instInfoReg_bits_vectorDecode_vSource; + reg instInfoReg_bits_vectorDecode_vm; + reg [3:0] instInfoReg_bits_scalarDecode_branch; + reg [2:0] instInfoReg_bits_scalarDecode_writeback_selector; + reg [1:0] instInfoReg_bits_scalarDecode_memory_function; + reg [2:0] instInfoReg_bits_scalarDecode_csr_funct; + reg instInfoReg_bits_scalarDecode_fence; + reg instInfoReg_bits_vecConf_vtype_vill; + reg instInfoReg_bits_vecConf_vtype_vma; + reg instInfoReg_bits_vecConf_vtype_vta; + reg [2:0] instInfoReg_bits_vecConf_vtype_vsew; + reg [2:0] instInfoReg_bits_vecConf_vtype_vlmul; + reg [5:0] instInfoReg_bits_vecConf_vl; + reg [63:0] instInfoReg_bits_pc_addr; + reg [4:0] idx; + reg [63:0] reductionAccumulator; + reg [4:0] executedNum; + wire [4:0] _GEN = {3'h0, idx[4:3]}; + wire [63:0] execValue1 = + instInfoReg_bits_vectorDecode_vSource == 3'h0 + | instInfoReg_bits_vectorDecode_vSource == 3'h3 + ? io_readVrf_resp_vs1Out + : instInfoReg_bits_scalarVal; + wire _io_signalIn_ready_output = + ~instInfoReg_valid | _io_dataOut_toVRF_bits_last_output; + wire [64:0] _GEN_0 = {1'h0, valueToExec_vs2Out}; + wire [64:0] _GEN_1 = {1'h0, valueToExec_vs1Out}; + wire [64:0] _execResult_T_25 = _GEN_0 + _GEN_1; + wire [64:0] _GEN_2 = {64'h0, valueToExec_vm}; + wire [64:0] _GEN_3 = _execResult_T_25 + _GEN_2; + wire [64:0] _execResult_T_1 = _GEN_0 - _GEN_1; + wire [64:0] _GEN_4 = _execResult_T_1 - _GEN_2; + wire _execResult_multiplyResHighBits_T_5 = + instInfoReg_bits_vecConf_vtype_vsew == 3'h0; + wire _execResult_multiplyResHighBits_T_7 = + instInfoReg_bits_vecConf_vtype_vsew == 3'h1; + wire _execResult_multiplyResHighBits_T_9 = + instInfoReg_bits_vecConf_vtype_vsew == 3'h2; + wire _execResult_multiplyResHighBits_T_11 = + instInfoReg_bits_vecConf_vtype_vsew == 3'h3; + wire [64:0] _execResult_vs1ForMult_T_49 = + _execResult_multiplyResHighBits_T_11 + ? {~(instInfoReg_bits_vectorDecode_veuFun == 6'h23 + | instInfoReg_bits_vectorDecode_veuFun == 6'h24) & valueToExec_vs1Out[63], + valueToExec_vs1Out} + : _execResult_multiplyResHighBits_T_9 + ? {instInfoReg_bits_vectorDecode_veuFun == 6'h23 + | instInfoReg_bits_vectorDecode_veuFun == 6'h24 + ? 33'h0 + : {33{valueToExec_vs1Out[31]}}, + valueToExec_vs1Out[31:0]} + : _execResult_multiplyResHighBits_T_7 + ? {instInfoReg_bits_vectorDecode_veuFun == 6'h23 + | instInfoReg_bits_vectorDecode_veuFun == 6'h24 + ? 49'h0 + : {49{valueToExec_vs1Out[15]}}, + valueToExec_vs1Out[15:0]} + : _execResult_multiplyResHighBits_T_5 + ? {instInfoReg_bits_vectorDecode_veuFun == 6'h23 + | instInfoReg_bits_vectorDecode_veuFun == 6'h24 + ? 57'h0 + : {57{valueToExec_vs1Out[7]}}, + valueToExec_vs1Out[7:0]} + : _GEN_1; + wire [64:0] _execResult_multiplyRes_T_5 = + instInfoReg_bits_vectorDecode_veuFun == 6'h27 + | instInfoReg_bits_vectorDecode_veuFun == 6'h28 + ? (_execResult_multiplyResHighBits_T_11 + ? {io_readVrf_resp_vdOut[63], io_readVrf_resp_vdOut} + : _execResult_multiplyResHighBits_T_9 + ? {{33{io_readVrf_resp_vdOut[31]}}, io_readVrf_resp_vdOut[31:0]} + : _execResult_multiplyResHighBits_T_7 + ? {{49{io_readVrf_resp_vdOut[15]}}, io_readVrf_resp_vdOut[15:0]} + : _execResult_multiplyResHighBits_T_5 + ? {{57{io_readVrf_resp_vdOut[7]}}, io_readVrf_resp_vdOut[7:0]} + : {1'h0, io_readVrf_resp_vdOut}) + : _execResult_multiplyResHighBits_T_11 + ? {instInfoReg_bits_vectorDecode_veuFun != 6'h23 & valueToExec_vs2Out[63], + valueToExec_vs2Out} + : _execResult_multiplyResHighBits_T_9 + ? {instInfoReg_bits_vectorDecode_veuFun == 6'h23 + ? 33'h0 + : {33{valueToExec_vs2Out[31]}}, + valueToExec_vs2Out[31:0]} + : _execResult_multiplyResHighBits_T_7 + ? {instInfoReg_bits_vectorDecode_veuFun == 6'h23 + ? 49'h0 + : {49{valueToExec_vs2Out[15]}}, + valueToExec_vs2Out[15:0]} + : _execResult_multiplyResHighBits_T_5 + ? {instInfoReg_bits_vectorDecode_veuFun == 6'h23 + ? 57'h0 + : {57{valueToExec_vs2Out[7]}}, + valueToExec_vs2Out[7:0]} + : _GEN_0; + wire [127:0] _GEN_5 = + {{63{_execResult_multiplyRes_T_5[64]}}, _execResult_multiplyRes_T_5} + * {{63{_execResult_vs1ForMult_T_49[64]}}, _execResult_vs1ForMult_T_49}; + wire [63:0] execResult_32 = + _execResult_multiplyResHighBits_T_11 + ? _GEN_5[63:0] + : {32'h0, + _execResult_multiplyResHighBits_T_9 + ? _GEN_5[31:0] + : {16'h0, + _execResult_multiplyResHighBits_T_7 ? _GEN_5[15:0] : {8'h0, _GEN_5[7:0]}}}; + wire [63:0] execResult_35 = + _execResult_multiplyResHighBits_T_11 + ? _GEN_5[127:64] + : {32'h0, + _execResult_multiplyResHighBits_T_9 + ? _GEN_5[63:32] + : {16'h0, + _execResult_multiplyResHighBits_T_7 + ? _GEN_5[31:16] + : {8'h0, _GEN_5[15:8]}}}; + wire [63:0] _GEN_6 = 64'h0 - _GEN_5[63:0]; + wire [63:0] _GEN_7 = + instInfoReg_bits_vectorDecode_veuFun == 6'h28 + ? _GEN_6 + valueToExec_vs2Out + : instInfoReg_bits_vectorDecode_veuFun == 6'h27 + ? _GEN_5[63:0] + valueToExec_vs2Out + : instInfoReg_bits_vectorDecode_veuFun == 6'h26 + ? _GEN_6 + io_readVrf_resp_vdOut + : instInfoReg_bits_vectorDecode_veuFun == 6'h25 + ? _GEN_5[63:0] + io_readVrf_resp_vdOut + : execResult_32 + io_readVrf_resp_vdOut; + wire execResult_7 = valueToExec_vs2Out == valueToExec_vs1Out; + wire execResult_9 = valueToExec_vs2Out < valueToExec_vs1Out; + wire execResult_13 = valueToExec_vs2Out > valueToExec_vs1Out; + wire [63:0] execResult_21 = valueToExec_vs2Out & valueToExec_vs1Out; + wire [63:0] execResult_22 = valueToExec_vs2Out | valueToExec_vs1Out; + wire [63:0] execResult_23 = valueToExec_vs2Out ^ valueToExec_vs1Out; + wire execResult_24 = valueToExec_vs2Out[0] & valueToExec_vs1Out[0]; + wire execResult_27 = valueToExec_vs2Out[0] ^ valueToExec_vs1Out[0]; + wire execResult_28 = valueToExec_vs2Out[0] | valueToExec_vs1Out[0]; + wire [7:0] _GEN_8 = {5'h0, idx[2:0]}; + wire [7:0] _valueToExec_vs1Out_T_4 = execValue1[7:0] >> _GEN_8; + assign valueToExec_vs1Out = + instInfoReg_bits_vectorDecode_vSource == 3'h3 + ? {63'h0, _valueToExec_vs1Out_T_4[0]} + : ~(instInfoReg_bits_vectorDecode_veuFun == 6'h29 + | instInfoReg_bits_vectorDecode_veuFun == 6'h2A + | instInfoReg_bits_vectorDecode_veuFun == 6'h2B + | instInfoReg_bits_vectorDecode_veuFun == 6'h2C + | instInfoReg_bits_vectorDecode_veuFun == 6'h2D + | instInfoReg_bits_vectorDecode_veuFun == 6'h2E + | instInfoReg_bits_vectorDecode_veuFun == 6'h2F + | instInfoReg_bits_vectorDecode_veuFun == 6'h30) | idx == 5'h0 + ? execValue1 + : reductionAccumulator; + wire [7:0] _valueToExec_vs2Out_T_4 = io_readVrf_resp_vs2Out[7:0] >> _GEN_8; + assign valueToExec_vs2Out = + instInfoReg_bits_vectorDecode_vSource == 3'h3 + ? {63'h0, _valueToExec_vs2Out_T_4[0]} + : io_readVrf_resp_vs2Out; + assign valueToExec_vm = + ~((instInfoReg_bits_vectorDecode_veuFun == 6'h5 + | instInfoReg_bits_vectorDecode_veuFun == 6'h7) & instInfoReg_bits_vectorDecode_vm) + & io_readVrf_resp_vm; + wire [63:0][63:0] _GEN_9 = + {{64'h0}, + {64'h0}, + {64'h0}, + {64'h0}, + {64'h0}, + {64'h0}, + {64'h0}, + {64'h0}, + {64'h0}, + {64'h0}, + {64'h0}, + {64'h0}, + {64'h0}, + {64'h0}, + {64'h0}, + {execResult_23}, + {execResult_22}, + {execResult_21}, + {$signed(valueToExec_vs2Out) < $signed(valueToExec_vs1Out) + ? valueToExec_vs2Out + : valueToExec_vs1Out}, + {execResult_9 ? valueToExec_vs2Out : valueToExec_vs1Out}, + {$signed(valueToExec_vs2Out) > $signed(valueToExec_vs1Out) + ? valueToExec_vs2Out + : valueToExec_vs1Out}, + {execResult_13 ? valueToExec_vs2Out : valueToExec_vs1Out}, + {_execResult_T_25[63:0]}, + {_GEN_7}, + {_GEN_7}, + {_GEN_7}, + {_GEN_7}, + {execResult_35}, + {execResult_35}, + {execResult_35}, + {execResult_32}, + {{63'h0, ~execResult_27}}, + {{63'h0, valueToExec_vs2Out[0] | ~(valueToExec_vs1Out[0])}}, + {{63'h0, ~execResult_28}}, + {{63'h0, execResult_28}}, + {{63'h0, execResult_27}}, + {{63'h0, valueToExec_vs2Out[0] & ~(valueToExec_vs1Out[0])}}, + {{63'h0, ~execResult_24}}, + {{63'h0, execResult_24}}, + {execResult_23}, + {execResult_22}, + {execResult_21}, + {valueToExec_vs1Out}, + {valueToExec_vm ? valueToExec_vs1Out : valueToExec_vs2Out}, + {$signed(valueToExec_vs2Out) > $signed(valueToExec_vs1Out) + ? valueToExec_vs2Out + : valueToExec_vs1Out}, + {execResult_13 ? valueToExec_vs2Out : valueToExec_vs1Out}, + {$signed(valueToExec_vs2Out) < $signed(valueToExec_vs1Out) + ? valueToExec_vs2Out + : valueToExec_vs1Out}, + {execResult_9 ? valueToExec_vs2Out : valueToExec_vs1Out}, + {{63'h0, $signed(valueToExec_vs2Out) > $signed(valueToExec_vs1Out)}}, + {{63'h0, execResult_13}}, + {{63'h0, $signed(valueToExec_vs2Out) <= $signed(valueToExec_vs1Out)}}, + {{63'h0, ~execResult_13}}, + {{63'h0, $signed(valueToExec_vs2Out) < $signed(valueToExec_vs1Out)}}, + {{63'h0, execResult_9}}, + {{63'h0, ~execResult_7}}, + {{63'h0, execResult_7}}, + {{63'h0, _GEN_4[64]}}, + {_GEN_4[63:0]}, + {{63'h0, _GEN_3[64]}}, + {_GEN_3[63:0]}, + {valueToExec_vs1Out - valueToExec_vs2Out}, + {_execResult_T_1[63:0]}, + {_execResult_T_25[63:0]}, + {64'h0}}; + wire [63:0] _GEN_10 = + (instInfoReg_bits_vectorDecode_veuFun == 6'h29 + | instInfoReg_bits_vectorDecode_veuFun == 6'h2A + | instInfoReg_bits_vectorDecode_veuFun == 6'h2B + | instInfoReg_bits_vectorDecode_veuFun == 6'h2C + | instInfoReg_bits_vectorDecode_veuFun == 6'h2D + | instInfoReg_bits_vectorDecode_veuFun == 6'h2E + | instInfoReg_bits_vectorDecode_veuFun == 6'h2F + | instInfoReg_bits_vectorDecode_veuFun == 6'h30) & ~instInfoReg_bits_vectorDecode_vm + & ~io_readVrf_resp_vm + ? reductionAccumulator + : _GEN_9[instInfoReg_bits_vectorDecode_veuFun]; + wire [7:0][7:0] _GEN_11 = + {{{_GEN_10[0], io_readVrf_resp_vdOut[6:0]}}, + {{io_readVrf_resp_vdOut[7], _GEN_10[0], io_readVrf_resp_vdOut[5:0]}}, + {{io_readVrf_resp_vdOut[7:6], _GEN_10[0], io_readVrf_resp_vdOut[4:0]}}, + {{io_readVrf_resp_vdOut[7:5], _GEN_10[0], io_readVrf_resp_vdOut[3:0]}}, + {{io_readVrf_resp_vdOut[7:4], _GEN_10[0], io_readVrf_resp_vdOut[2:0]}}, + {{io_readVrf_resp_vdOut[7:3], _GEN_10[0], io_readVrf_resp_vdOut[1:0]}}, + {{io_readVrf_resp_vdOut[7:2], _GEN_10[0], io_readVrf_resp_vdOut[0]}}, + {{io_readVrf_resp_vdOut[7:1], _GEN_10[0]}}}; + wire _io_dataOut_toVRF_bits_writeReq_T_63 = + instInfoReg_bits_vectorDecode_veuFun == 6'h29 + | instInfoReg_bits_vectorDecode_veuFun == 6'h2A + | instInfoReg_bits_vectorDecode_veuFun == 6'h2B + | instInfoReg_bits_vectorDecode_veuFun == 6'h2C + | instInfoReg_bits_vectorDecode_veuFun == 6'h2D + | instInfoReg_bits_vectorDecode_veuFun == 6'h2E + | instInfoReg_bits_vectorDecode_veuFun == 6'h2F + | instInfoReg_bits_vectorDecode_veuFun == 6'h30 + ? _io_dataOut_toVRF_bits_last_output + : instInfoReg_bits_vectorDecode_vm | io_readVrf_resp_vm + | instInfoReg_bits_vectorDecode_veuFun == 6'h4 + | instInfoReg_bits_vectorDecode_veuFun == 6'h5 + | instInfoReg_bits_vectorDecode_veuFun == 6'h6 + | instInfoReg_bits_vectorDecode_veuFun == 6'h7 + | instInfoReg_bits_vectorDecode_veuFun == 6'h14 + | instInfoReg_bits_vectorDecode_veuFun == 6'h19 + | instInfoReg_bits_vectorDecode_veuFun == 6'h1A + | instInfoReg_bits_vectorDecode_veuFun == 6'h1B + | instInfoReg_bits_vectorDecode_veuFun == 6'h1C + | instInfoReg_bits_vectorDecode_veuFun == 6'h1D + | instInfoReg_bits_vectorDecode_veuFun == 6'h1E + | instInfoReg_bits_vectorDecode_veuFun == 6'h1F + | instInfoReg_bits_vectorDecode_veuFun == 6'h20; + wire _T_27 = instInfoReg_bits_vectorDecode_veuFun == 6'h31; + wire _T_29 = instInfoReg_bits_vectorDecode_veuFun == 6'h32; + wire _GEN_12 = instInfoReg_valid & (_T_27 | _T_29); + assign _io_dataOut_toVRF_valid_output = _GEN_12 | instInfoReg_valid; + assign _io_dataOut_toVRF_bits_last_output = + _GEN_12 | {1'h0, idx} == instInfoReg_bits_vecConf_vl - 6'h1 & instInfoReg_valid; + assign _io_dataOut_toVRF_bits_writeReq_output = + instInfoReg_valid + ? ~_T_27 & (_T_29 | _io_dataOut_toVRF_bits_writeReq_T_63) + : _io_dataOut_toVRF_bits_writeReq_T_63; + wire _GEN_13 = _GEN_12 | _io_dataOut_toVRF_bits_last_output; + always @(posedge clock) begin + automatic logic _T_2; + _T_2 = io_signalIn_valid & _io_signalIn_ready_output; + if (reset) begin + instInfoReg_valid <= 1'h0; + idx <= 5'h0; + reductionAccumulator <= 64'h0; + executedNum <= 5'h0; + end + else begin + instInfoReg_valid <= _T_2 | ~_io_dataOut_toVRF_bits_last_output & instInfoReg_valid; + if (_T_2 | _io_dataOut_toVRF_bits_last_output | ~instInfoReg_valid) begin + idx <= 5'h0; + executedNum <= 5'h0; + end + else begin + idx <= idx + 5'h1; + executedNum <= + executedNum + + {4'h0, + _io_dataOut_toVRF_valid_output & _io_dataOut_toVRF_bits_writeReq_output}; + end + reductionAccumulator <= _GEN_10; + end + if (_T_2) begin + instInfoReg_bits_vs1 <= io_signalIn_bits_vs1; + instInfoReg_bits_vs2 <= io_signalIn_bits_vs2; + instInfoReg_bits_vd <= io_signalIn_bits_vd; + instInfoReg_bits_scalarVal <= io_signalIn_bits_scalarVal; + instInfoReg_bits_vectorDecode_veuFun <= io_signalIn_bits_vectorDecode_veuFun; + instInfoReg_bits_vectorDecode_vSource <= io_signalIn_bits_vectorDecode_vSource; + instInfoReg_bits_vectorDecode_vm <= io_signalIn_bits_vectorDecode_vm; + instInfoReg_bits_scalarDecode_branch <= io_signalIn_bits_scalarDecode_branch; + instInfoReg_bits_scalarDecode_writeback_selector <= + io_signalIn_bits_scalarDecode_writeback_selector; + instInfoReg_bits_scalarDecode_memory_function <= + io_signalIn_bits_scalarDecode_memory_function; + instInfoReg_bits_scalarDecode_csr_funct <= io_signalIn_bits_scalarDecode_csr_funct; + instInfoReg_bits_scalarDecode_fence <= io_signalIn_bits_scalarDecode_fence; + instInfoReg_bits_vecConf_vtype_vill <= io_signalIn_bits_vecConf_vtype_vill; + instInfoReg_bits_vecConf_vtype_vma <= io_signalIn_bits_vecConf_vtype_vma; + instInfoReg_bits_vecConf_vtype_vta <= io_signalIn_bits_vecConf_vtype_vta; + instInfoReg_bits_vecConf_vtype_vsew <= io_signalIn_bits_vecConf_vtype_vsew; + instInfoReg_bits_vecConf_vtype_vlmul <= io_signalIn_bits_vecConf_vtype_vlmul; + instInfoReg_bits_vecConf_vl <= io_signalIn_bits_vecConf_vl; + instInfoReg_bits_pc_addr <= io_signalIn_bits_pc_addr; + end + end // always @(posedge) + assign io_signalIn_ready = _io_signalIn_ready_output; + assign io_readVrf_req_sew = + instInfoReg_bits_vectorDecode_vSource == 3'h3 + ? 3'h0 + : instInfoReg_bits_vecConf_vtype_vsew; + assign io_readVrf_req_readVdAsMaskSource = + (instInfoReg_bits_vectorDecode_veuFun == 6'h8 + | instInfoReg_bits_vectorDecode_veuFun == 6'h9 + | instInfoReg_bits_vectorDecode_veuFun == 6'hA + | instInfoReg_bits_vectorDecode_veuFun == 6'hB + | instInfoReg_bits_vectorDecode_veuFun == 6'hC + | instInfoReg_bits_vectorDecode_veuFun == 6'hD + | instInfoReg_bits_vectorDecode_veuFun == 6'hE + | instInfoReg_bits_vectorDecode_veuFun == 6'hF + | instInfoReg_bits_vectorDecode_veuFun == 6'h5 + | instInfoReg_bits_vectorDecode_veuFun == 6'h7 + | instInfoReg_bits_vectorDecode_veuFun == 6'h19 + | instInfoReg_bits_vectorDecode_veuFun == 6'h1A + | instInfoReg_bits_vectorDecode_veuFun == 6'h1B + | instInfoReg_bits_vectorDecode_veuFun == 6'h1C + | instInfoReg_bits_vectorDecode_veuFun == 6'h1D + | instInfoReg_bits_vectorDecode_veuFun == 6'h1E + | instInfoReg_bits_vectorDecode_veuFun == 6'h1F + | instInfoReg_bits_vectorDecode_veuFun == 6'h20) + & instInfoReg_bits_vectorDecode_vSource != 3'h3; + assign io_readVrf_req_idx = instInfoReg_bits_vectorDecode_vSource == 3'h3 ? _GEN : idx; + assign io_readVrf_req_vs1 = instInfoReg_bits_vs1; + assign io_readVrf_req_vs2 = instInfoReg_bits_vs2; + assign io_readVrf_req_vd = instInfoReg_bits_vd; + assign io_dataOut_toVRF_valid = _io_dataOut_toVRF_valid_output; + assign io_dataOut_toVRF_bits_vd = instInfoReg_bits_vd; + assign io_dataOut_toVRF_bits_vtype_vsew = + instInfoReg_bits_vectorDecode_veuFun == 6'h8 + | instInfoReg_bits_vectorDecode_veuFun == 6'h9 + | instInfoReg_bits_vectorDecode_veuFun == 6'hA + | instInfoReg_bits_vectorDecode_veuFun == 6'hB + | instInfoReg_bits_vectorDecode_veuFun == 6'hC + | instInfoReg_bits_vectorDecode_veuFun == 6'hD + | instInfoReg_bits_vectorDecode_veuFun == 6'hE + | instInfoReg_bits_vectorDecode_veuFun == 6'hF + | instInfoReg_bits_vectorDecode_veuFun == 6'h5 + | instInfoReg_bits_vectorDecode_veuFun == 6'h7 + | instInfoReg_bits_vectorDecode_veuFun == 6'h19 + | instInfoReg_bits_vectorDecode_veuFun == 6'h1A + | instInfoReg_bits_vectorDecode_veuFun == 6'h1B + | instInfoReg_bits_vectorDecode_veuFun == 6'h1C + | instInfoReg_bits_vectorDecode_veuFun == 6'h1D + | instInfoReg_bits_vectorDecode_veuFun == 6'h1E + | instInfoReg_bits_vectorDecode_veuFun == 6'h1F + | instInfoReg_bits_vectorDecode_veuFun == 6'h20 + ? 3'h0 + : instInfoReg_bits_vecConf_vtype_vsew; + assign io_dataOut_toVRF_bits_index = + instInfoReg_bits_vectorDecode_veuFun == 6'h29 + | instInfoReg_bits_vectorDecode_veuFun == 6'h2A + | instInfoReg_bits_vectorDecode_veuFun == 6'h2B + | instInfoReg_bits_vectorDecode_veuFun == 6'h2C + | instInfoReg_bits_vectorDecode_veuFun == 6'h2D + | instInfoReg_bits_vectorDecode_veuFun == 6'h2E + | instInfoReg_bits_vectorDecode_veuFun == 6'h2F + | instInfoReg_bits_vectorDecode_veuFun == 6'h30 + ? 5'h0 + : instInfoReg_bits_vectorDecode_veuFun == 6'h8 + | instInfoReg_bits_vectorDecode_veuFun == 6'h9 + | instInfoReg_bits_vectorDecode_veuFun == 6'hA + | instInfoReg_bits_vectorDecode_veuFun == 6'hB + | instInfoReg_bits_vectorDecode_veuFun == 6'hC + | instInfoReg_bits_vectorDecode_veuFun == 6'hD + | instInfoReg_bits_vectorDecode_veuFun == 6'hE + | instInfoReg_bits_vectorDecode_veuFun == 6'hF + | instInfoReg_bits_vectorDecode_veuFun == 6'h5 + | instInfoReg_bits_vectorDecode_veuFun == 6'h7 + | instInfoReg_bits_vectorDecode_veuFun == 6'h19 + | instInfoReg_bits_vectorDecode_veuFun == 6'h1A + | instInfoReg_bits_vectorDecode_veuFun == 6'h1B + | instInfoReg_bits_vectorDecode_veuFun == 6'h1C + | instInfoReg_bits_vectorDecode_veuFun == 6'h1D + | instInfoReg_bits_vectorDecode_veuFun == 6'h1E + | instInfoReg_bits_vectorDecode_veuFun == 6'h1F + | instInfoReg_bits_vectorDecode_veuFun == 6'h20 + ? _GEN + : idx; + assign io_dataOut_toVRF_bits_last = _io_dataOut_toVRF_bits_last_output; + assign io_dataOut_toVRF_bits_data = + ~instInfoReg_valid | _T_27 | ~_T_29 + ? (instInfoReg_bits_vectorDecode_veuFun == 6'h8 + | instInfoReg_bits_vectorDecode_veuFun == 6'h9 + | instInfoReg_bits_vectorDecode_veuFun == 6'hA + | instInfoReg_bits_vectorDecode_veuFun == 6'hB + | instInfoReg_bits_vectorDecode_veuFun == 6'hC + | instInfoReg_bits_vectorDecode_veuFun == 6'hD + | instInfoReg_bits_vectorDecode_veuFun == 6'hE + | instInfoReg_bits_vectorDecode_veuFun == 6'hF + | instInfoReg_bits_vectorDecode_veuFun == 6'h5 + | instInfoReg_bits_vectorDecode_veuFun == 6'h7 + | instInfoReg_bits_vectorDecode_veuFun == 6'h19 + | instInfoReg_bits_vectorDecode_veuFun == 6'h1A + | instInfoReg_bits_vectorDecode_veuFun == 6'h1B + | instInfoReg_bits_vectorDecode_veuFun == 6'h1C + | instInfoReg_bits_vectorDecode_veuFun == 6'h1D + | instInfoReg_bits_vectorDecode_veuFun == 6'h1E + | instInfoReg_bits_vectorDecode_veuFun == 6'h1F + | instInfoReg_bits_vectorDecode_veuFun == 6'h20 + ? {56'h0, _GEN_11[idx[2:0]]} + : _GEN_10) + : instInfoReg_bits_scalarVal; + assign io_dataOut_toVRF_bits_vm = + instInfoReg_bits_vectorDecode_veuFun == 6'h8 + | instInfoReg_bits_vectorDecode_veuFun == 6'h9 + | instInfoReg_bits_vectorDecode_veuFun == 6'hA + | instInfoReg_bits_vectorDecode_veuFun == 6'hB + | instInfoReg_bits_vectorDecode_veuFun == 6'hC + | instInfoReg_bits_vectorDecode_veuFun == 6'hD + | instInfoReg_bits_vectorDecode_veuFun == 6'hE + | instInfoReg_bits_vectorDecode_veuFun == 6'hF + | instInfoReg_bits_vectorDecode_veuFun == 6'h5 + | instInfoReg_bits_vectorDecode_veuFun == 6'h7 + | instInfoReg_bits_vectorDecode_veuFun == 6'h19 + | instInfoReg_bits_vectorDecode_veuFun == 6'h1A + | instInfoReg_bits_vectorDecode_veuFun == 6'h1B + | instInfoReg_bits_vectorDecode_veuFun == 6'h1C + | instInfoReg_bits_vectorDecode_veuFun == 6'h1D + | instInfoReg_bits_vectorDecode_veuFun == 6'h1E + | instInfoReg_bits_vectorDecode_veuFun == 6'h1F + | instInfoReg_bits_vectorDecode_veuFun == 6'h20; + assign io_dataOut_toVRF_bits_writeReq = _io_dataOut_toVRF_bits_writeReq_output; + assign io_toExWbReg_valid = _GEN_13; + assign io_toExWbReg_bits_dataSignals_pc_addr = instInfoReg_bits_pc_addr; + assign io_toExWbReg_bits_dataSignals_exResult = io_readVrf_resp_vs2Out; + assign io_toExWbReg_bits_ctrlSignals_decode_branch = + instInfoReg_bits_scalarDecode_branch; + assign io_toExWbReg_bits_ctrlSignals_decode_writeback_selector = + instInfoReg_bits_scalarDecode_writeback_selector; + assign io_toExWbReg_bits_ctrlSignals_decode_memory_function = + instInfoReg_bits_scalarDecode_memory_function; + assign io_toExWbReg_bits_ctrlSignals_decode_csr_funct = + instInfoReg_bits_scalarDecode_csr_funct; + assign io_toExWbReg_bits_ctrlSignals_decode_fence = instInfoReg_bits_scalarDecode_fence; + assign io_toExWbReg_bits_ctrlSignals_rd_index = + instInfoReg_valid & _T_27 ? instInfoReg_bits_vd : 5'h0; + assign io_toExWbReg_bits_vectorCsrPorts_vtype_vill = + instInfoReg_bits_vecConf_vtype_vill; + assign io_toExWbReg_bits_vectorCsrPorts_vtype_vma = instInfoReg_bits_vecConf_vtype_vma; + assign io_toExWbReg_bits_vectorCsrPorts_vtype_vta = instInfoReg_bits_vecConf_vtype_vta; + assign io_toExWbReg_bits_vectorCsrPorts_vtype_vsew = + instInfoReg_bits_vecConf_vtype_vsew; + assign io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul = + instInfoReg_bits_vecConf_vtype_vlmul; + assign io_toExWbReg_bits_vectorCsrPorts_vl = instInfoReg_bits_vecConf_vl; + assign io_toExWbReg_bits_vectorExecNum_valid = _GEN_13; + assign io_toExWbReg_bits_vectorExecNum_bits = + _GEN_12 + ? 5'h1 + : executedNum + + {4'h0, _io_dataOut_toVRF_valid_output & _io_dataOut_toVRF_bits_writeReq_output}; +endmodule + +module VectorCpu( + input clock, + reset, + io_frontend_resp_valid, + input [63:0] io_frontend_resp_bits_pc_addr, + input [31:0] io_frontend_resp_bits_inst_bits, + input io_frontend_resp_bits_exceptionSignals_valid, + input [63:0] io_frontend_resp_bits_exceptionSignals_bits, + input io_dcache_axi4lite_ar_ready, + io_dcache_axi4lite_aw_ready, + io_dcache_axi4lite_b_valid, + io_dcache_axi4lite_r_valid, + input [63:0] io_dcache_axi4lite_r_bits_data, + input io_dcache_axi4lite_w_ready, + input [63:0] io_hartid, + output io_frontend_req_valid, + output [63:0] io_frontend_req_bits_pc, + output io_frontend_resp_ready, + io_dcache_axi4lite_ar_valid, + output [63:0] io_dcache_axi4lite_ar_bits_addr, + output io_dcache_axi4lite_aw_valid, + output [63:0] io_dcache_axi4lite_aw_bits_addr, + output io_dcache_axi4lite_w_valid, + output [63:0] io_dcache_axi4lite_w_bits_data, + output [7:0] io_dcache_axi4lite_w_bits_strb +); + + wire _sysInst_in_pipeline_T_13; + wire _sysInst_in_pipeline_T_6; + wire _bypassingUnit_io_WB_in_valid_T_2; + wire _bypassingUnit_io_WB_in_bits_rd_valid_T_4; + wire WB_pc_redirect; + wire EX_stall; + wire _bypassingUnit_io_EX_in_bits_rd_valid_T_31; + wire ID_flush; + wire _vrfReadyTable_io_vmCheck_valid_T_4; + wire _vrfReadyTable_io_vdCheck_valid_T_2; + wire _vrfReadyTable_io_vs2Check_valid_T_8; + wire _vrfReadyTable_io_vs1Check_valid_T_8; + wire rs2_required_but_not_valid; + wire rs1_required_but_not_valid; + wire _vecAluExecUnit_1_io_signalIn_ready; + wire [2:0] _vecAluExecUnit_1_io_readVrf_req_sew; + wire _vecAluExecUnit_1_io_readVrf_req_readVdAsMaskSource; + wire [4:0] _vecAluExecUnit_1_io_readVrf_req_idx; + wire [4:0] _vecAluExecUnit_1_io_readVrf_req_vs1; + wire [4:0] _vecAluExecUnit_1_io_readVrf_req_vs2; + wire [4:0] _vecAluExecUnit_1_io_readVrf_req_vd; + wire _vecAluExecUnit_1_io_dataOut_toVRF_valid; + wire [4:0] _vecAluExecUnit_1_io_dataOut_toVRF_bits_vd; + wire [2:0] _vecAluExecUnit_1_io_dataOut_toVRF_bits_vtype_vsew; + wire [4:0] _vecAluExecUnit_1_io_dataOut_toVRF_bits_index; + wire _vecAluExecUnit_1_io_dataOut_toVRF_bits_last; + wire [63:0] _vecAluExecUnit_1_io_dataOut_toVRF_bits_data; + wire _vecAluExecUnit_1_io_dataOut_toVRF_bits_vm; + wire _vecAluExecUnit_1_io_dataOut_toVRF_bits_writeReq; + wire _vecAluExecUnit_1_io_toExWbReg_valid; + wire [63:0] _vecAluExecUnit_1_io_toExWbReg_bits_dataSignals_pc_addr; + wire [63:0] _vecAluExecUnit_1_io_toExWbReg_bits_dataSignals_exResult; + wire [3:0] _vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_branch; + wire [2:0] + _vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_writeback_selector; + wire [1:0] _vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_memory_function; + wire [2:0] _vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_csr_funct; + wire _vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_fence; + wire [4:0] _vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_rd_index; + wire _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vill; + wire _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vma; + wire _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vta; + wire [2:0] _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vsew; + wire [2:0] _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul; + wire [5:0] _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vl; + wire _vecAluExecUnit_1_io_toExWbReg_bits_vectorExecNum_valid; + wire [4:0] _vecAluExecUnit_1_io_toExWbReg_bits_vectorExecNum_bits; + wire _vecAluExecUnit_0_io_signalIn_ready; + wire [2:0] _vecAluExecUnit_0_io_readVrf_req_sew; + wire _vecAluExecUnit_0_io_readVrf_req_readVdAsMaskSource; + wire [4:0] _vecAluExecUnit_0_io_readVrf_req_idx; + wire [4:0] _vecAluExecUnit_0_io_readVrf_req_vs1; + wire [4:0] _vecAluExecUnit_0_io_readVrf_req_vs2; + wire [4:0] _vecAluExecUnit_0_io_readVrf_req_vd; + wire _vecAluExecUnit_0_io_dataOut_toVRF_valid; + wire [4:0] _vecAluExecUnit_0_io_dataOut_toVRF_bits_vd; + wire [2:0] _vecAluExecUnit_0_io_dataOut_toVRF_bits_vtype_vsew; + wire [4:0] _vecAluExecUnit_0_io_dataOut_toVRF_bits_index; + wire _vecAluExecUnit_0_io_dataOut_toVRF_bits_last; + wire [63:0] _vecAluExecUnit_0_io_dataOut_toVRF_bits_data; + wire _vecAluExecUnit_0_io_dataOut_toVRF_bits_vm; + wire _vecAluExecUnit_0_io_dataOut_toVRF_bits_writeReq; + wire _vecAluExecUnit_0_io_toExWbReg_valid; + wire [63:0] _vecAluExecUnit_0_io_toExWbReg_bits_dataSignals_pc_addr; + wire [63:0] _vecAluExecUnit_0_io_toExWbReg_bits_dataSignals_exResult; + wire [3:0] _vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_branch; + wire [2:0] + _vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_writeback_selector; + wire [1:0] _vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_memory_function; + wire [2:0] _vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_csr_funct; + wire _vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_fence; + wire [4:0] _vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_rd_index; + wire _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vill; + wire _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vma; + wire _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vta; + wire [2:0] _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vsew; + wire [2:0] _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul; + wire [5:0] _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vl; + wire _vecAluExecUnit_0_io_toExWbReg_bits_vectorExecNum_valid; + wire [4:0] _vecAluExecUnit_0_io_toExWbReg_bits_vectorExecNum_bits; + wire _vrfReadyTable_io_vs1Check_ready; + wire _vrfReadyTable_io_vs2Check_ready; + wire _vrfReadyTable_io_vdCheck_ready; + wire _vrfReadyTable_io_vmCheck_ready; + wire [63:0] _vecRegFile_io_readReq_0_resp_vs2Out; + wire [63:0] _vecRegFile_io_readReq_0_resp_vdOut; + wire _vecRegFile_io_readReq_0_resp_vm; + wire [63:0] _vecRegFile_io_readReq_1_resp_vs1Out; + wire [63:0] _vecRegFile_io_readReq_1_resp_vs2Out; + wire [63:0] _vecRegFile_io_readReq_1_resp_vdOut; + wire _vecRegFile_io_readReq_1_resp_vm; + wire [63:0] _vecRegFile_io_readReq_2_resp_vs1Out; + wire [63:0] _vecRegFile_io_readReq_2_resp_vs2Out; + wire [63:0] _vecRegFile_io_readReq_2_resp_vdOut; + wire _vecRegFile_io_readReq_2_resp_vm; + wire _vecCtrlUnit_io_resp_valid; + wire _vecCtrlUnit_io_resp_bits_vtype_vill; + wire _vecCtrlUnit_io_resp_bits_vtype_vma; + wire _vecCtrlUnit_io_resp_bits_vtype_vta; + wire [2:0] _vecCtrlUnit_io_resp_bits_vtype_vsew; + wire [2:0] _vecCtrlUnit_io_resp_bits_vtype_vlmul; + wire [5:0] _vecCtrlUnit_io_resp_bits_vl; + wire _vectorDecoder_io_out_isConfsetInst; + wire [1:0] _vectorDecoder_io_out_avl_sel; + wire [1:0] _vectorDecoder_io_out_vtype_sel; + wire [2:0] _vectorDecoder_io_out_mop; + wire [5:0] _vectorDecoder_io_out_veuFun; + wire [2:0] _vectorDecoder_io_out_vSource; + wire _vectorDecoder_io_out_vm; + wire _multiplier_io_resp_valid; + wire [63:0] _multiplier_io_resp_bits; + wire [63:0] _csrUnit_io_resp_data; + wire _vectorLdstUnit_io_signalIn_ready; + wire [2:0] _vectorLdstUnit_io_readVrf_req_sew; + wire [4:0] _vectorLdstUnit_io_readVrf_req_idx; + wire [4:0] _vectorLdstUnit_io_readVrf_req_vs2; + wire [4:0] _vectorLdstUnit_io_readVrf_req_vd; + wire _vectorLdstUnit_io_scalarResp_valid; + wire [63:0] _vectorLdstUnit_io_scalarResp_bits_data; + wire _vectorLdstUnit_io_vectorResp_toVRF_valid; + wire [4:0] _vectorLdstUnit_io_vectorResp_toVRF_bits_vd; + wire [2:0] _vectorLdstUnit_io_vectorResp_toVRF_bits_vtype_vsew; + wire [4:0] _vectorLdstUnit_io_vectorResp_toVRF_bits_index; + wire _vectorLdstUnit_io_vectorResp_toVRF_bits_last; + wire [63:0] _vectorLdstUnit_io_vectorResp_toVRF_bits_data; + wire _vectorLdstUnit_io_vectorResp_toVRF_bits_writeReq; + wire _vectorLdstUnit_io_toExWbReg_valid; + wire [63:0] _vectorLdstUnit_io_toExWbReg_bits_dataSignals_pc_addr; + wire [3:0] _vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_branch; + wire [2:0] + _vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_writeback_selector; + wire [1:0] _vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_memory_function; + wire [2:0] _vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_csr_funct; + wire _vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_fence; + wire [4:0] _vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_rd_index; + wire _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vill; + wire _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vma; + wire _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vta; + wire [2:0] _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vsew; + wire [2:0] _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul; + wire [5:0] _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vl; + wire _vectorLdstUnit_io_toExWbReg_bits_vectorExecNum_valid; + wire [4:0] _vectorLdstUnit_io_toExWbReg_bits_vectorExecNum_bits; + wire _bypassingUnit_io_ID_out_rs1_value_valid; + wire [63:0] _bypassingUnit_io_ID_out_rs1_value_bits; + wire _bypassingUnit_io_ID_out_rs1_bypassMatchAtEX; + wire _bypassingUnit_io_ID_out_rs1_bypassMatchAtWB; + wire _bypassingUnit_io_ID_out_rs2_value_valid; + wire [63:0] _bypassingUnit_io_ID_out_rs2_value_bits; + wire _bypassingUnit_io_ID_out_rs2_bypassMatchAtEX; + wire _bypassingUnit_io_ID_out_rs2_bypassMatchAtWB; + wire _branch_evaluator_io_out_valid; + wire [63:0] _branch_evaluator_io_out_bits_pc; + wire [63:0] _alu_io_out; + wire [63:0] _rf_io_rs1_out; + wire [63:0] _rf_io_rs2_out; + wire _branch_predictor_io_out_valid; + wire [63:0] _branch_predictor_io_out_bits_pc; + wire _decoder_io_out_valid; + wire [3:0] _decoder_io_out_bits_branch; + wire [1:0] _decoder_io_out_bits_value1; + wire [2:0] _decoder_io_out_bits_value2; + wire [3:0] _decoder_io_out_bits_arithmetic_funct; + wire _decoder_io_out_bits_alu_flag; + wire _decoder_io_out_bits_op32; + wire [2:0] _decoder_io_out_bits_writeback_selector; + wire [1:0] _decoder_io_out_bits_memory_function; + wire [1:0] _decoder_io_out_bits_memory_length; + wire _decoder_io_out_bits_mem_sext; + wire [2:0] _decoder_io_out_bits_csr_funct; + wire _decoder_io_out_bits_fence; + wire _decoder_io_out_bits_vector; + reg cpu_operating; + reg ID_EX_REG_valid; + reg [63:0] ID_EX_REG_bits_dataSignals_pc_addr; + reg [63:0] ID_EX_REG_bits_dataSignals_bp_destPC; + reg ID_EX_REG_bits_dataSignals_bp_taken; + reg [63:0] ID_EX_REG_bits_dataSignals_imm; + reg [63:0] ID_EX_REG_bits_dataSignals_rs1; + reg [63:0] ID_EX_REG_bits_dataSignals_rs2; + reg [11:0] ID_EX_REG_bits_dataSignals_zimm; + reg [3:0] ID_EX_REG_bits_ctrlSignals_decode_branch; + reg [1:0] ID_EX_REG_bits_ctrlSignals_decode_value1; + reg [2:0] ID_EX_REG_bits_ctrlSignals_decode_value2; + reg [3:0] ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct; + reg ID_EX_REG_bits_ctrlSignals_decode_alu_flag; + reg ID_EX_REG_bits_ctrlSignals_decode_op32; + reg [2:0] ID_EX_REG_bits_ctrlSignals_decode_writeback_selector; + reg [1:0] ID_EX_REG_bits_ctrlSignals_decode_memory_function; + reg [2:0] ID_EX_REG_bits_ctrlSignals_decode_csr_funct; + reg ID_EX_REG_bits_ctrlSignals_decode_fence; + reg ID_EX_REG_bits_ctrlSignals_decode_vector; + reg [4:0] ID_EX_REG_bits_ctrlSignals_rd_index; + reg ID_EX_REG_bits_exceptionSignals_valid; + reg [63:0] ID_EX_REG_bits_exceptionSignals_bits; + reg ID_EX_REG_bits_vectorCtrlSignals_isConfsetInst; + reg [1:0] ID_EX_REG_bits_vectorCtrlSignals_avl_sel; + reg [1:0] ID_EX_REG_bits_vectorCtrlSignals_vtype_sel; + reg [5:0] ID_EX_REG_bits_vectorCtrlSignals_veuFun; + reg EX_WB_REG_valid; + reg [63:0] EX_WB_REG_bits_dataSignals_pc_addr; + reg [63:0] EX_WB_REG_bits_dataSignals_exResult; + reg [63:0] EX_WB_REG_bits_dataSignals_datatoCSR; + reg [11:0] EX_WB_REG_bits_dataSignals_csr_addr; + reg [3:0] EX_WB_REG_bits_ctrlSignals_decode_branch; + reg [2:0] EX_WB_REG_bits_ctrlSignals_decode_writeback_selector; + reg [1:0] EX_WB_REG_bits_ctrlSignals_decode_memory_function; + reg [2:0] EX_WB_REG_bits_ctrlSignals_decode_csr_funct; + reg EX_WB_REG_bits_ctrlSignals_decode_fence; + reg [4:0] EX_WB_REG_bits_ctrlSignals_rd_index; + reg EX_WB_REG_bits_exceptionSignals_valid; + reg [63:0] EX_WB_REG_bits_exceptionSignals_bits; + reg EX_WB_REG_bits_vectorCsrPorts_vtype_vill; + reg EX_WB_REG_bits_vectorCsrPorts_vtype_vma; + reg EX_WB_REG_bits_vectorCsrPorts_vtype_vta; + reg [2:0] EX_WB_REG_bits_vectorCsrPorts_vtype_vsew; + reg [2:0] EX_WB_REG_bits_vectorCsrPorts_vtype_vlmul; + reg [5:0] EX_WB_REG_bits_vectorCsrPorts_vl; + reg EX_WB_REG_bits_vectorExecNum_valid; + reg [4:0] EX_WB_REG_bits_vectorExecNum_bits; + wire _T_34 = _decoder_io_out_valid & _decoder_io_out_bits_vector; + wire ID_stall = + ~ID_flush + & (ID_EX_REG_valid & EX_stall | rs1_required_but_not_valid + | rs2_required_but_not_valid | _sysInst_in_pipeline_T_6 | _sysInst_in_pipeline_T_13 + | ~((~_vrfReadyTable_io_vs1Check_valid_T_8 | _vrfReadyTable_io_vs1Check_ready) + & (~_vrfReadyTable_io_vs2Check_valid_T_8 | _vrfReadyTable_io_vs2Check_ready) + & (~_vrfReadyTable_io_vdCheck_valid_T_2 | _vrfReadyTable_io_vdCheck_ready) + & (~_vrfReadyTable_io_vmCheck_valid_T_4 | _vrfReadyTable_io_vmCheck_ready) + & (~(_T_34 & ~_vectorDecoder_io_out_isConfsetInst + & (|_vectorDecoder_io_out_mop)) | _vectorLdstUnit_io_signalIn_ready) + & (~(_T_34 & ~_vectorDecoder_io_out_isConfsetInst + & ~(|_vectorDecoder_io_out_mop)) | _vecAluExecUnit_0_io_signalIn_ready + | _vecAluExecUnit_1_io_signalIn_ready)) + | ~(_vectorLdstUnit_io_signalIn_ready & _vecAluExecUnit_0_io_signalIn_ready + & _vecAluExecUnit_1_io_signalIn_ready) & _decoder_io_out_valid + & (~_decoder_io_out_bits_vector | _vectorDecoder_io_out_isConfsetInst + | _vectorDecoder_io_out_veuFun == 6'h31 + | _vectorDecoder_io_out_veuFun == 6'h32)); + wire _io_frontend_resp_ready_output = cpu_operating & ~ID_stall; + wire _io_frontend_req_valid_T = + _branch_evaluator_io_out_valid & ID_EX_REG_valid; + wire ID_inst_valid = + io_frontend_resp_valid & _io_frontend_resp_ready_output; + wire [63:0] rs1ValueToEX = + _bypassingUnit_io_ID_out_rs1_value_valid + ? _bypassingUnit_io_ID_out_rs1_value_bits + : _rf_io_rs1_out; + assign rs1_required_but_not_valid = + _bypassingUnit_io_ID_out_rs1_bypassMatchAtEX + ? ~_bypassingUnit_io_EX_in_bits_rd_valid_T_31 + : _bypassingUnit_io_ID_out_rs1_bypassMatchAtWB + & ~_bypassingUnit_io_WB_in_bits_rd_valid_T_4; + assign rs2_required_but_not_valid = + _bypassingUnit_io_ID_out_rs2_bypassMatchAtEX + ? ~_bypassingUnit_io_EX_in_bits_rd_valid_T_31 + : _bypassingUnit_io_ID_out_rs2_bypassMatchAtWB + & ~_bypassingUnit_io_WB_in_bits_rd_valid_T_4; + wire vecConfBypass_vtype_vill = + _vecCtrlUnit_io_resp_valid + ? _vecCtrlUnit_io_resp_bits_vtype_vill + : EX_WB_REG_bits_vectorCsrPorts_vtype_vill; + wire vecConfBypass_vtype_vma = + _vecCtrlUnit_io_resp_valid + ? _vecCtrlUnit_io_resp_bits_vtype_vma + : EX_WB_REG_bits_vectorCsrPorts_vtype_vma; + wire vecConfBypass_vtype_vta = + _vecCtrlUnit_io_resp_valid + ? _vecCtrlUnit_io_resp_bits_vtype_vta + : EX_WB_REG_bits_vectorCsrPorts_vtype_vta; + wire [2:0] vecConfBypass_vtype_vsew = + _vecCtrlUnit_io_resp_valid + ? _vecCtrlUnit_io_resp_bits_vtype_vsew + : EX_WB_REG_bits_vectorCsrPorts_vtype_vsew; + wire [2:0] vecConfBypass_vtype_vlmul = + _vecCtrlUnit_io_resp_valid + ? _vecCtrlUnit_io_resp_bits_vtype_vlmul + : EX_WB_REG_bits_vectorCsrPorts_vtype_vlmul; + wire [5:0] vecConfBypass_vl = + _vecCtrlUnit_io_resp_valid + ? _vecCtrlUnit_io_resp_bits_vl + : EX_WB_REG_bits_vectorCsrPorts_vl; + assign _vrfReadyTable_io_vs1Check_valid_T_8 = + _T_34 & ~_vectorDecoder_io_out_isConfsetInst & ~(|_vectorDecoder_io_out_mop) + & _vectorDecoder_io_out_vSource == 3'h0; + assign _vrfReadyTable_io_vs2Check_valid_T_8 = + _T_34 & ~_vectorDecoder_io_out_isConfsetInst + & (~(|_vectorDecoder_io_out_mop) | _vectorDecoder_io_out_mop == 3'h4); + assign _vrfReadyTable_io_vdCheck_valid_T_2 = + _T_34 & ~_vectorDecoder_io_out_isConfsetInst; + assign _vrfReadyTable_io_vmCheck_valid_T_4 = + _T_34 & ~_vectorDecoder_io_out_isConfsetInst & ~_vectorDecoder_io_out_vm; + wire _T_17 = ID_flush | ID_stall; + wire _T_9 = + io_frontend_resp_valid & _decoder_io_out_valid & _decoder_io_out_bits_vector + & ~_vectorDecoder_io_out_isConfsetInst & ~(|_vectorDecoder_io_out_mop); + wire _T_14 = + _vecAluExecUnit_1_io_signalIn_ready & ~_vecAluExecUnit_0_io_signalIn_ready; + `ifndef SYNTHESIS + always @(posedge clock) begin + automatic logic _GEN = ~_T_17 & _T_9; + if ((`PRINTF_COND_) & _GEN & _vecAluExecUnit_0_io_signalIn_ready & ~reset) + $fwrite(32'h80000002, "vecAluExecUnit%d valid\n", 1'h0); + if ((`PRINTF_COND_) & _GEN & _T_14 & ~reset) + $fwrite(32'h80000002, "vecAluExecUnit%d valid\n", 1'h1); + end // always @(posedge) + `endif // not def SYNTHESIS + wire _T_26 = io_frontend_resp_valid & _decoder_io_out_valid; + wire _T_25 = + _T_26 & _decoder_io_out_bits_vector & ~_vectorDecoder_io_out_isConfsetInst + & (|_vectorDecoder_io_out_mop) & _vectorLdstUnit_io_signalIn_ready; + assign ID_flush = WB_pc_redirect | _branch_evaluator_io_out_valid; + reg multiplier_hasValue; + wire _exScalarRes_T_10 = + ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'h9 + | ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'hA + | ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'hB + | ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'hC; + wire _exVectorRes_T_4 = + ID_EX_REG_bits_vectorCtrlSignals_veuFun == 6'h31 + | ID_EX_REG_bits_vectorCtrlSignals_veuFun == 6'h32; + wire [63:0] _GEN_0 = {58'h0, _vecCtrlUnit_io_resp_bits_vl}; + assign _bypassingUnit_io_EX_in_bits_rd_valid_T_31 = + (ID_EX_REG_bits_ctrlSignals_decode_writeback_selector == 3'h5 + | ~(ID_EX_REG_bits_ctrlSignals_decode_writeback_selector == 3'h0 + | ID_EX_REG_bits_ctrlSignals_decode_writeback_selector == 3'h4 + | ID_EX_REG_bits_ctrlSignals_decode_writeback_selector == 3'h3) + & (ID_EX_REG_bits_ctrlSignals_decode_writeback_selector == 3'h2 + ? ~(ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'h9 + | ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'hA + | ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'hB + | ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'hC) + | _multiplier_io_resp_valid + : ID_EX_REG_bits_ctrlSignals_decode_writeback_selector == 3'h1)) + & ID_EX_REG_valid; + assign EX_stall = + ID_EX_REG_valid + & (ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'h9 + | ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'hA + | ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'hB + | ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'hC) + & ~_multiplier_io_resp_valid; + assign WB_pc_redirect = + EX_WB_REG_valid + & (EX_WB_REG_bits_ctrlSignals_decode_branch == 4'hA + | EX_WB_REG_bits_ctrlSignals_decode_branch == 4'h9); + wire WB_inst_can_retire = + EX_WB_REG_valid & ~EX_WB_REG_bits_exceptionSignals_valid; + wire [7:0][63:0] _GEN_1 = + {{64'h0}, + {64'h0}, + {EX_WB_REG_bits_dataSignals_exResult}, + {_vectorLdstUnit_io_scalarResp_bits_data}, + {_csrUnit_io_resp_data}, + {EX_WB_REG_bits_dataSignals_exResult}, + {EX_WB_REG_bits_dataSignals_pc_addr + 64'h4}, + {64'h0}}; + wire [63:0] _rf_io_req_bits_data_T_16 = + _GEN_1[EX_WB_REG_bits_ctrlSignals_decode_writeback_selector]; + assign _bypassingUnit_io_WB_in_bits_rd_valid_T_4 = + _bypassingUnit_io_WB_in_valid_T_2 + & (EX_WB_REG_bits_ctrlSignals_decode_memory_function != 2'h1 + | _vectorLdstUnit_io_scalarResp_valid); + assign _bypassingUnit_io_WB_in_valid_T_2 = + (|EX_WB_REG_bits_ctrlSignals_decode_writeback_selector) & WB_inst_can_retire; + assign _sysInst_in_pipeline_T_6 = + ID_EX_REG_valid + & (ID_EX_REG_bits_ctrlSignals_decode_fence + | ID_EX_REG_bits_ctrlSignals_decode_branch == 4'h9 + | ID_EX_REG_bits_ctrlSignals_decode_branch == 4'hA); + assign _sysInst_in_pipeline_T_13 = + EX_WB_REG_valid + & (EX_WB_REG_bits_ctrlSignals_decode_fence + | EX_WB_REG_bits_ctrlSignals_decode_branch == 4'h9 + | EX_WB_REG_bits_ctrlSignals_decode_branch == 4'hA); + always @(posedge clock) begin + automatic logic _GEN_2 = + _vectorLdstUnit_io_toExWbReg_valid | _vecAluExecUnit_1_io_toExWbReg_valid + | _vecAluExecUnit_0_io_toExWbReg_valid; + if (reset) begin + cpu_operating <= 1'h0; + ID_EX_REG_valid <= 1'h0; + EX_WB_REG_valid <= 1'h0; + multiplier_hasValue <= 1'h0; + end + else begin + cpu_operating <= ~reset | cpu_operating; + ID_EX_REG_valid <= ~ID_flush & (EX_stall ? ID_EX_REG_valid : ID_inst_valid); + EX_WB_REG_valid <= + ~WB_pc_redirect + & (_vectorLdstUnit_io_toExWbReg_valid + ? _vectorLdstUnit_io_toExWbReg_valid + : _vecAluExecUnit_1_io_toExWbReg_valid + ? _vecAluExecUnit_1_io_toExWbReg_valid + : _vecAluExecUnit_0_io_toExWbReg_valid + ? _vecAluExecUnit_0_io_toExWbReg_valid + : ID_EX_REG_valid + & (~(ID_EX_REG_bits_ctrlSignals_decode_memory_function == 2'h1 + | ID_EX_REG_bits_ctrlSignals_decode_memory_function == 2'h2) + | _vectorLdstUnit_io_signalIn_ready) + & (~(ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'h9 + | ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'hA + | ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'hB + | ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'hC) + | _multiplier_io_resp_valid) + & (~ID_EX_REG_bits_ctrlSignals_decode_vector + | ID_EX_REG_bits_vectorCtrlSignals_isConfsetInst + | _vectorLdstUnit_io_toExWbReg_valid + | _vecAluExecUnit_0_io_toExWbReg_valid + | _vecAluExecUnit_1_io_toExWbReg_valid)); + multiplier_hasValue <= + (ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'h9 + | ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'hA + | ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'hB + | ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'hC) & ID_EX_REG_valid + & ~_multiplier_io_resp_valid; + end + if (~EX_stall) begin + automatic logic ID_fetchException = + io_frontend_resp_bits_exceptionSignals_valid & ID_inst_valid; + automatic logic ID_illegal_instruction; + automatic logic ID_ecall; + ID_illegal_instruction = ~_decoder_io_out_valid & ID_inst_valid; + ID_ecall = + _decoder_io_out_valid & _decoder_io_out_bits_branch == 4'h9 & ID_inst_valid; + ID_EX_REG_bits_dataSignals_pc_addr <= io_frontend_resp_bits_pc_addr; + ID_EX_REG_bits_dataSignals_bp_destPC <= _branch_predictor_io_out_bits_pc; + ID_EX_REG_bits_dataSignals_bp_taken <= _branch_predictor_io_out_valid; + if (_decoder_io_out_bits_value1 == 2'h2) + ID_EX_REG_bits_dataSignals_imm <= + {{32{io_frontend_resp_bits_inst_bits[31]}}, + io_frontend_resp_bits_inst_bits[31:12], + 12'h0}; + else if (&_decoder_io_out_bits_value1) + ID_EX_REG_bits_dataSignals_imm <= {59'h0, io_frontend_resp_bits_inst_bits[19:15]}; + else if (_decoder_io_out_bits_value2 == 3'h2) + ID_EX_REG_bits_dataSignals_imm <= + {{52{io_frontend_resp_bits_inst_bits[31]}}, + io_frontend_resp_bits_inst_bits[31:20]}; + else if (_decoder_io_out_bits_value2 == 3'h3) + ID_EX_REG_bits_dataSignals_imm <= + {{52{io_frontend_resp_bits_inst_bits[31]}}, + io_frontend_resp_bits_inst_bits[31:25], + io_frontend_resp_bits_inst_bits[11:7]}; + else + ID_EX_REG_bits_dataSignals_imm <= 64'h0; + if (_bypassingUnit_io_ID_out_rs1_value_valid) + ID_EX_REG_bits_dataSignals_rs1 <= _bypassingUnit_io_ID_out_rs1_value_bits; + else + ID_EX_REG_bits_dataSignals_rs1 <= _rf_io_rs1_out; + if (_bypassingUnit_io_ID_out_rs2_value_valid) + ID_EX_REG_bits_dataSignals_rs2 <= _bypassingUnit_io_ID_out_rs2_value_bits; + else + ID_EX_REG_bits_dataSignals_rs2 <= _rf_io_rs2_out; + ID_EX_REG_bits_dataSignals_zimm <= io_frontend_resp_bits_inst_bits[31:20]; + ID_EX_REG_bits_ctrlSignals_decode_branch <= _decoder_io_out_bits_branch; + ID_EX_REG_bits_ctrlSignals_decode_value1 <= _decoder_io_out_bits_value1; + ID_EX_REG_bits_ctrlSignals_decode_value2 <= _decoder_io_out_bits_value2; + ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct <= + _decoder_io_out_bits_arithmetic_funct; + ID_EX_REG_bits_ctrlSignals_decode_alu_flag <= _decoder_io_out_bits_alu_flag; + ID_EX_REG_bits_ctrlSignals_decode_op32 <= _decoder_io_out_bits_op32; + ID_EX_REG_bits_ctrlSignals_decode_writeback_selector <= + _decoder_io_out_bits_writeback_selector; + ID_EX_REG_bits_ctrlSignals_decode_memory_function <= + _decoder_io_out_bits_memory_function; + ID_EX_REG_bits_ctrlSignals_decode_csr_funct <= _decoder_io_out_bits_csr_funct; + ID_EX_REG_bits_ctrlSignals_decode_fence <= _decoder_io_out_bits_fence; + ID_EX_REG_bits_ctrlSignals_decode_vector <= _decoder_io_out_bits_vector; + ID_EX_REG_bits_ctrlSignals_rd_index <= io_frontend_resp_bits_inst_bits[11:7]; + ID_EX_REG_bits_exceptionSignals_valid <= + ID_fetchException | ID_illegal_instruction | ID_ecall; + if (ID_fetchException) + ID_EX_REG_bits_exceptionSignals_bits <= + io_frontend_resp_bits_exceptionSignals_bits; + else + ID_EX_REG_bits_exceptionSignals_bits <= + {60'h0, ID_illegal_instruction ? 4'h2 : ID_ecall ? 4'hB : 4'h0}; + end + if (EX_stall | ~_T_34) begin + end + else begin + ID_EX_REG_bits_vectorCtrlSignals_isConfsetInst <= + _vectorDecoder_io_out_isConfsetInst; + ID_EX_REG_bits_vectorCtrlSignals_avl_sel <= _vectorDecoder_io_out_avl_sel; + ID_EX_REG_bits_vectorCtrlSignals_vtype_sel <= _vectorDecoder_io_out_vtype_sel; + ID_EX_REG_bits_vectorCtrlSignals_veuFun <= _vectorDecoder_io_out_veuFun; + end + if (_vectorLdstUnit_io_toExWbReg_valid) begin + EX_WB_REG_bits_dataSignals_pc_addr <= + _vectorLdstUnit_io_toExWbReg_bits_dataSignals_pc_addr; + EX_WB_REG_bits_dataSignals_exResult <= 64'h0; + EX_WB_REG_bits_ctrlSignals_decode_branch <= + _vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_branch; + EX_WB_REG_bits_ctrlSignals_decode_writeback_selector <= + _vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_writeback_selector; + EX_WB_REG_bits_ctrlSignals_decode_memory_function <= + _vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_memory_function; + EX_WB_REG_bits_ctrlSignals_decode_csr_funct <= + _vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_csr_funct; + EX_WB_REG_bits_ctrlSignals_decode_fence <= + _vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_fence; + EX_WB_REG_bits_ctrlSignals_rd_index <= + _vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_rd_index; + EX_WB_REG_bits_vectorCsrPorts_vtype_vill <= + _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vill; + EX_WB_REG_bits_vectorCsrPorts_vtype_vma <= + _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vma; + EX_WB_REG_bits_vectorCsrPorts_vtype_vta <= + _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vta; + EX_WB_REG_bits_vectorCsrPorts_vtype_vsew <= + _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vsew; + EX_WB_REG_bits_vectorCsrPorts_vtype_vlmul <= + _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul; + EX_WB_REG_bits_vectorCsrPorts_vl <= + _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vl; + EX_WB_REG_bits_vectorExecNum_valid <= + _vectorLdstUnit_io_toExWbReg_bits_vectorExecNum_valid; + EX_WB_REG_bits_vectorExecNum_bits <= + _vectorLdstUnit_io_toExWbReg_bits_vectorExecNum_bits; + end + else if (_vecAluExecUnit_1_io_toExWbReg_valid) begin + EX_WB_REG_bits_dataSignals_pc_addr <= + _vecAluExecUnit_1_io_toExWbReg_bits_dataSignals_pc_addr; + EX_WB_REG_bits_dataSignals_exResult <= + _vecAluExecUnit_1_io_toExWbReg_bits_dataSignals_exResult; + EX_WB_REG_bits_ctrlSignals_decode_branch <= + _vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_branch; + EX_WB_REG_bits_ctrlSignals_decode_writeback_selector <= + _vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_writeback_selector; + EX_WB_REG_bits_ctrlSignals_decode_memory_function <= + _vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_memory_function; + EX_WB_REG_bits_ctrlSignals_decode_csr_funct <= + _vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_csr_funct; + EX_WB_REG_bits_ctrlSignals_decode_fence <= + _vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_fence; + EX_WB_REG_bits_ctrlSignals_rd_index <= + _vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_rd_index; + EX_WB_REG_bits_vectorCsrPorts_vtype_vill <= + _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vill; + EX_WB_REG_bits_vectorCsrPorts_vtype_vma <= + _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vma; + EX_WB_REG_bits_vectorCsrPorts_vtype_vta <= + _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vta; + EX_WB_REG_bits_vectorCsrPorts_vtype_vsew <= + _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vsew; + EX_WB_REG_bits_vectorCsrPorts_vtype_vlmul <= + _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul; + EX_WB_REG_bits_vectorCsrPorts_vl <= + _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vl; + EX_WB_REG_bits_vectorExecNum_valid <= + _vecAluExecUnit_1_io_toExWbReg_bits_vectorExecNum_valid; + EX_WB_REG_bits_vectorExecNum_bits <= + _vecAluExecUnit_1_io_toExWbReg_bits_vectorExecNum_bits; + end + else begin + if (_vecAluExecUnit_0_io_toExWbReg_valid) begin + EX_WB_REG_bits_dataSignals_pc_addr <= + _vecAluExecUnit_0_io_toExWbReg_bits_dataSignals_pc_addr; + EX_WB_REG_bits_dataSignals_exResult <= + _vecAluExecUnit_0_io_toExWbReg_bits_dataSignals_exResult; + EX_WB_REG_bits_ctrlSignals_decode_branch <= + _vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_branch; + EX_WB_REG_bits_ctrlSignals_decode_writeback_selector <= + _vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_writeback_selector; + EX_WB_REG_bits_ctrlSignals_decode_memory_function <= + _vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_memory_function; + EX_WB_REG_bits_ctrlSignals_decode_csr_funct <= + _vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_csr_funct; + EX_WB_REG_bits_ctrlSignals_decode_fence <= + _vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_fence; + EX_WB_REG_bits_ctrlSignals_rd_index <= + _vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_rd_index; + EX_WB_REG_bits_vectorCsrPorts_vtype_vill <= + _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vill; + EX_WB_REG_bits_vectorCsrPorts_vtype_vma <= + _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vma; + EX_WB_REG_bits_vectorCsrPorts_vtype_vta <= + _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vta; + EX_WB_REG_bits_vectorCsrPorts_vtype_vsew <= + _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vsew; + EX_WB_REG_bits_vectorCsrPorts_vtype_vlmul <= + _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul; + EX_WB_REG_bits_vectorCsrPorts_vl <= + _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vl; + EX_WB_REG_bits_vectorExecNum_bits <= + _vecAluExecUnit_0_io_toExWbReg_bits_vectorExecNum_bits; + end + else begin + EX_WB_REG_bits_dataSignals_pc_addr <= ID_EX_REG_bits_dataSignals_pc_addr; + if (ID_EX_REG_bits_ctrlSignals_decode_writeback_selector == 3'h5) begin + if (_exVectorRes_T_4) + EX_WB_REG_bits_dataSignals_exResult <= + _vecAluExecUnit_0_io_toExWbReg_bits_dataSignals_exResult; + else + EX_WB_REG_bits_dataSignals_exResult <= _GEN_0; + end + else if (ID_EX_REG_bits_ctrlSignals_decode_writeback_selector == 3'h2) begin + if (_exScalarRes_T_10) + EX_WB_REG_bits_dataSignals_exResult <= _multiplier_io_resp_bits; + else + EX_WB_REG_bits_dataSignals_exResult <= _alu_io_out; + end + else + EX_WB_REG_bits_dataSignals_exResult <= 64'h0; + EX_WB_REG_bits_ctrlSignals_decode_branch <= + ID_EX_REG_bits_ctrlSignals_decode_branch; + EX_WB_REG_bits_ctrlSignals_decode_writeback_selector <= + ID_EX_REG_bits_ctrlSignals_decode_writeback_selector; + EX_WB_REG_bits_ctrlSignals_decode_memory_function <= + ID_EX_REG_bits_ctrlSignals_decode_memory_function; + EX_WB_REG_bits_ctrlSignals_decode_csr_funct <= + ID_EX_REG_bits_ctrlSignals_decode_csr_funct; + EX_WB_REG_bits_ctrlSignals_decode_fence <= + ID_EX_REG_bits_ctrlSignals_decode_fence; + EX_WB_REG_bits_ctrlSignals_rd_index <= ID_EX_REG_bits_ctrlSignals_rd_index; + if (_vecCtrlUnit_io_resp_valid) begin + EX_WB_REG_bits_vectorCsrPorts_vtype_vill <= + _vecCtrlUnit_io_resp_bits_vtype_vill; + EX_WB_REG_bits_vectorCsrPorts_vtype_vma <= _vecCtrlUnit_io_resp_bits_vtype_vma; + EX_WB_REG_bits_vectorCsrPorts_vtype_vta <= _vecCtrlUnit_io_resp_bits_vtype_vta; + EX_WB_REG_bits_vectorCsrPorts_vtype_vsew <= + _vecCtrlUnit_io_resp_bits_vtype_vsew; + EX_WB_REG_bits_vectorCsrPorts_vtype_vlmul <= + _vecCtrlUnit_io_resp_bits_vtype_vlmul; + EX_WB_REG_bits_vectorCsrPorts_vl <= _vecCtrlUnit_io_resp_bits_vl; + end + EX_WB_REG_bits_vectorExecNum_bits <= 5'h0; + end + EX_WB_REG_bits_vectorExecNum_valid <= + _vecAluExecUnit_0_io_toExWbReg_valid + & _vecAluExecUnit_0_io_toExWbReg_bits_vectorExecNum_valid; + end + if (_GEN_2) begin + EX_WB_REG_bits_dataSignals_datatoCSR <= 64'h0; + EX_WB_REG_bits_dataSignals_csr_addr <= 12'h0; + end + else begin + if (ID_EX_REG_bits_ctrlSignals_decode_value1 == 2'h1) + EX_WB_REG_bits_dataSignals_datatoCSR <= ID_EX_REG_bits_dataSignals_rs1; + else + EX_WB_REG_bits_dataSignals_datatoCSR <= ID_EX_REG_bits_dataSignals_imm; + EX_WB_REG_bits_dataSignals_csr_addr <= ID_EX_REG_bits_dataSignals_zimm; + end + EX_WB_REG_bits_exceptionSignals_valid <= + ~_GEN_2 + & (ID_EX_REG_valid & ID_EX_REG_bits_exceptionSignals_valid + | ID_EX_REG_bits_ctrlSignals_decode_branch == 4'h9 & ID_EX_REG_valid); + if (_GEN_2 | ~ID_EX_REG_bits_exceptionSignals_valid) + EX_WB_REG_bits_exceptionSignals_bits <= 64'h0; + else + EX_WB_REG_bits_exceptionSignals_bits <= ID_EX_REG_bits_exceptionSignals_bits; + end // always @(posedge) + Decoder decoder ( + .io_inst_bits (io_frontend_resp_bits_inst_bits), + .io_out_valid (_decoder_io_out_valid), + .io_out_bits_branch (_decoder_io_out_bits_branch), + .io_out_bits_value1 (_decoder_io_out_bits_value1), + .io_out_bits_value2 (_decoder_io_out_bits_value2), + .io_out_bits_arithmetic_funct (_decoder_io_out_bits_arithmetic_funct), + .io_out_bits_alu_flag (_decoder_io_out_bits_alu_flag), + .io_out_bits_op32 (_decoder_io_out_bits_op32), + .io_out_bits_writeback_selector (_decoder_io_out_bits_writeback_selector), + .io_out_bits_memory_function (_decoder_io_out_bits_memory_function), + .io_out_bits_memory_length (_decoder_io_out_bits_memory_length), + .io_out_bits_mem_sext (_decoder_io_out_bits_mem_sext), + .io_out_bits_csr_funct (_decoder_io_out_bits_csr_funct), + .io_out_bits_fence (_decoder_io_out_bits_fence), + .io_out_bits_vector (_decoder_io_out_bits_vector) + ); + BranchPredictor branch_predictor ( + .clock (clock), + .reset (reset), + .io_pc_addr (io_frontend_resp_bits_pc_addr), + .io_imm + ({{44{io_frontend_resp_bits_inst_bits[31]}}, + _decoder_io_out_bits_branch == 4'h1 | _decoder_io_out_bits_branch == 4'h2 + | _decoder_io_out_bits_branch == 4'h3 | _decoder_io_out_bits_branch == 4'h4 + | _decoder_io_out_bits_branch == 4'h5 | _decoder_io_out_bits_branch == 4'h6 + ? {{8{io_frontend_resp_bits_inst_bits[31]}}, + io_frontend_resp_bits_inst_bits[7], + io_frontend_resp_bits_inst_bits[30:25], + io_frontend_resp_bits_inst_bits[11:8]} + : {io_frontend_resp_bits_inst_bits[19:12], + io_frontend_resp_bits_inst_bits[20], + io_frontend_resp_bits_inst_bits[30:21]}, + 1'h0}), + .io_BranchType (_decoder_io_out_bits_branch), + .io_out_valid (_branch_predictor_io_out_valid), + .io_out_bits_pc (_branch_predictor_io_out_bits_pc) + ); + RegFile rf ( + .clock (clock), + .io_rs1 (io_frontend_resp_bits_inst_bits[19:15]), + .io_rs2 (io_frontend_resp_bits_inst_bits[24:20]), + .io_req_valid + (WB_inst_can_retire & (|EX_WB_REG_bits_ctrlSignals_decode_writeback_selector)), + .io_req_bits_rd (EX_WB_REG_bits_ctrlSignals_rd_index), + .io_req_bits_data (_rf_io_req_bits_data_T_16), + .io_rs1_out (_rf_io_rs1_out), + .io_rs2_out (_rf_io_rs2_out) + ); + ALU alu ( + .io_funct_arithmetic_funct (ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct), + .io_funct_alu_flag (ID_EX_REG_bits_ctrlSignals_decode_alu_flag), + .io_funct_op32 (ID_EX_REG_bits_ctrlSignals_decode_op32), + .io_in1 + (ID_EX_REG_bits_ctrlSignals_decode_value1 == 2'h2 + ? ID_EX_REG_bits_dataSignals_imm + : ID_EX_REG_bits_ctrlSignals_decode_value1 == 2'h1 + ? ID_EX_REG_bits_dataSignals_rs1 + : 64'h0), + .io_in2 + (ID_EX_REG_bits_ctrlSignals_decode_value2 == 3'h4 + ? ID_EX_REG_bits_dataSignals_pc_addr + : ID_EX_REG_bits_ctrlSignals_decode_value2 == 3'h3 + | ID_EX_REG_bits_ctrlSignals_decode_value2 == 3'h2 + ? ID_EX_REG_bits_dataSignals_imm + : ID_EX_REG_bits_ctrlSignals_decode_value2 == 3'h1 + ? ID_EX_REG_bits_dataSignals_rs2 + : 64'h0), + .io_out (_alu_io_out) + ); + BranchEvaluator branch_evaluator ( + .io_req_valid (ID_EX_REG_valid), + .io_req_bits_ALU_Result (_alu_io_out), + .io_req_bits_BranchType (ID_EX_REG_bits_ctrlSignals_decode_branch), + .io_req_bits_destPC (ID_EX_REG_bits_dataSignals_bp_destPC), + .io_req_bits_pc_addr (ID_EX_REG_bits_dataSignals_pc_addr), + .io_req_bits_bp_taken (ID_EX_REG_bits_dataSignals_bp_taken), + .io_out_valid (_branch_evaluator_io_out_valid), + .io_out_bits_pc (_branch_evaluator_io_out_bits_pc) + ); + BypassingUnit bypassingUnit ( + .io_ID_in_rs1_index_valid + (_decoder_io_out_bits_value1 == 2'h1 & _decoder_io_out_valid + & io_frontend_resp_valid), + .io_ID_in_rs1_index_bits (io_frontend_resp_bits_inst_bits[19:15]), + .io_ID_in_rs2_index_valid + ((_decoder_io_out_bits_value2 == 3'h1 + | _decoder_io_out_bits_memory_function == 2'h2) & _decoder_io_out_valid + & io_frontend_resp_valid), + .io_ID_in_rs2_index_bits (io_frontend_resp_bits_inst_bits[24:20]), + .io_EX_in_valid + ((|ID_EX_REG_bits_ctrlSignals_decode_writeback_selector) & ID_EX_REG_valid), + .io_EX_in_bits_rd_valid (_bypassingUnit_io_EX_in_bits_rd_valid_T_31), + .io_EX_in_bits_rd_bits_index (ID_EX_REG_bits_ctrlSignals_rd_index), + .io_EX_in_bits_rd_bits_value + (ID_EX_REG_bits_ctrlSignals_decode_writeback_selector == 3'h5 + ? (_exVectorRes_T_4 + ? _vecAluExecUnit_0_io_toExWbReg_bits_dataSignals_exResult + : _GEN_0) + : ID_EX_REG_bits_ctrlSignals_decode_writeback_selector == 3'h2 + ? (_exScalarRes_T_10 ? _multiplier_io_resp_bits : _alu_io_out) + : ID_EX_REG_bits_ctrlSignals_decode_writeback_selector == 3'h1 + ? ID_EX_REG_bits_dataSignals_pc_addr + 64'h4 + : 64'h0), + .io_WB_in_valid (_bypassingUnit_io_WB_in_valid_T_2), + .io_WB_in_bits_rd_valid (_bypassingUnit_io_WB_in_bits_rd_valid_T_4), + .io_WB_in_bits_rd_bits_index (EX_WB_REG_bits_ctrlSignals_rd_index), + .io_WB_in_bits_rd_bits_value (_rf_io_req_bits_data_T_16), + .io_ID_out_rs1_value_valid (_bypassingUnit_io_ID_out_rs1_value_valid), + .io_ID_out_rs1_value_bits (_bypassingUnit_io_ID_out_rs1_value_bits), + .io_ID_out_rs1_bypassMatchAtEX (_bypassingUnit_io_ID_out_rs1_bypassMatchAtEX), + .io_ID_out_rs1_bypassMatchAtWB (_bypassingUnit_io_ID_out_rs1_bypassMatchAtWB), + .io_ID_out_rs2_value_valid (_bypassingUnit_io_ID_out_rs2_value_valid), + .io_ID_out_rs2_value_bits (_bypassingUnit_io_ID_out_rs2_value_bits), + .io_ID_out_rs2_bypassMatchAtEX (_bypassingUnit_io_ID_out_rs2_bypassMatchAtEX), + .io_ID_out_rs2_bypassMatchAtWB (_bypassingUnit_io_ID_out_rs2_bypassMatchAtWB) + ); + VectorLdstUnit vectorLdstUnit ( + .clock (clock), + .reset (reset), + .io_signalIn_valid + (~_T_17 + & (_T_25 | _T_26 + & (_decoder_io_out_bits_memory_function == 2'h1 + | _decoder_io_out_bits_memory_function == 2'h2) + & _vectorLdstUnit_io_signalIn_ready)), + .io_signalIn_bits_scalar_rs2Value + (_bypassingUnit_io_ID_out_rs2_value_valid + ? _bypassingUnit_io_ID_out_rs2_value_bits + : _rf_io_rs2_out), + .io_signalIn_bits_scalar_immediate + (_T_25 + ? (_decoder_io_out_bits_memory_function == 2'h1 + ? {{52{io_frontend_resp_bits_inst_bits[31]}}, + io_frontend_resp_bits_inst_bits[31:20]} + : {{52{io_frontend_resp_bits_inst_bits[31]}}, + io_frontend_resp_bits_inst_bits[31:25], + io_frontend_resp_bits_inst_bits[11:7]}) + : _decoder_io_out_bits_memory_function == 2'h1 + ? {{52{io_frontend_resp_bits_inst_bits[31]}}, + io_frontend_resp_bits_inst_bits[31:20]} + : {{52{io_frontend_resp_bits_inst_bits[31]}}, + io_frontend_resp_bits_inst_bits[31:25], + io_frontend_resp_bits_inst_bits[11:7]}), + .io_signalIn_bits_scalar_rdIndex + (io_frontend_resp_bits_inst_bits[11:7]), + .io_signalIn_bits_vector_vs2 + (_T_25 ? io_frontend_resp_bits_inst_bits[24:20] : 5'h0), + .io_signalIn_bits_vector_vd + (_T_25 ? io_frontend_resp_bits_inst_bits[11:7] : 5'h0), + .io_signalIn_bits_vector_scalarVal (rs1ValueToEX), + .io_signalIn_bits_vector_vectorDecode_mop + (_T_25 ? _vectorDecoder_io_out_mop : 3'h0), + .io_signalIn_bits_vector_vectorDecode_vm + (_T_25 & _vectorDecoder_io_out_vm), + .io_signalIn_bits_vector_scalarDecode_branch + (_decoder_io_out_bits_branch), + .io_signalIn_bits_vector_scalarDecode_writeback_selector + (_decoder_io_out_bits_writeback_selector), + .io_signalIn_bits_vector_scalarDecode_memory_function + (_decoder_io_out_bits_memory_function), + .io_signalIn_bits_vector_scalarDecode_memory_length + (_decoder_io_out_bits_memory_length), + .io_signalIn_bits_vector_scalarDecode_mem_sext + (_decoder_io_out_bits_mem_sext), + .io_signalIn_bits_vector_scalarDecode_csr_funct + (_decoder_io_out_bits_csr_funct), + .io_signalIn_bits_vector_scalarDecode_fence (_decoder_io_out_bits_fence), + .io_signalIn_bits_vector_scalarDecode_vector + (_decoder_io_out_bits_vector), + .io_signalIn_bits_vector_vecConf_vtype_vill + (_T_25 & vecConfBypass_vtype_vill), + .io_signalIn_bits_vector_vecConf_vtype_vma + (_T_25 & vecConfBypass_vtype_vma), + .io_signalIn_bits_vector_vecConf_vtype_vta + (_T_25 & vecConfBypass_vtype_vta), + .io_signalIn_bits_vector_vecConf_vtype_vsew + (_T_25 ? vecConfBypass_vtype_vsew : 3'h0), + .io_signalIn_bits_vector_vecConf_vtype_vlmul + (_T_25 ? vecConfBypass_vtype_vlmul : 3'h0), + .io_signalIn_bits_vector_vecConf_vl + (_T_25 ? vecConfBypass_vl : 6'h0), + .io_signalIn_bits_vector_pc_addr + (io_frontend_resp_bits_pc_addr), + .io_readVrf_resp_vs2Out + (_vecRegFile_io_readReq_0_resp_vs2Out), + .io_readVrf_resp_vdOut + (_vecRegFile_io_readReq_0_resp_vdOut), + .io_readVrf_resp_vm + (_vecRegFile_io_readReq_0_resp_vm), + .io_dcache_ar_ready + (io_dcache_axi4lite_ar_ready), + .io_dcache_aw_ready + (io_dcache_axi4lite_aw_ready), + .io_dcache_b_valid (io_dcache_axi4lite_b_valid), + .io_dcache_r_valid (io_dcache_axi4lite_r_valid), + .io_dcache_r_bits_data + (io_dcache_axi4lite_r_bits_data), + .io_dcache_w_ready (io_dcache_axi4lite_w_ready), + .io_signalIn_ready + (_vectorLdstUnit_io_signalIn_ready), + .io_readVrf_req_sew + (_vectorLdstUnit_io_readVrf_req_sew), + .io_readVrf_req_idx + (_vectorLdstUnit_io_readVrf_req_idx), + .io_readVrf_req_vs2 + (_vectorLdstUnit_io_readVrf_req_vs2), + .io_readVrf_req_vd + (_vectorLdstUnit_io_readVrf_req_vd), + .io_scalarResp_valid + (_vectorLdstUnit_io_scalarResp_valid), + .io_scalarResp_bits_data + (_vectorLdstUnit_io_scalarResp_bits_data), + .io_vectorResp_toVRF_valid + (_vectorLdstUnit_io_vectorResp_toVRF_valid), + .io_vectorResp_toVRF_bits_vd + (_vectorLdstUnit_io_vectorResp_toVRF_bits_vd), + .io_vectorResp_toVRF_bits_vtype_vsew + (_vectorLdstUnit_io_vectorResp_toVRF_bits_vtype_vsew), + .io_vectorResp_toVRF_bits_index + (_vectorLdstUnit_io_vectorResp_toVRF_bits_index), + .io_vectorResp_toVRF_bits_last + (_vectorLdstUnit_io_vectorResp_toVRF_bits_last), + .io_vectorResp_toVRF_bits_data + (_vectorLdstUnit_io_vectorResp_toVRF_bits_data), + .io_vectorResp_toVRF_bits_writeReq + (_vectorLdstUnit_io_vectorResp_toVRF_bits_writeReq), + .io_dcache_ar_valid + (io_dcache_axi4lite_ar_valid), + .io_dcache_ar_bits_addr + (io_dcache_axi4lite_ar_bits_addr), + .io_dcache_aw_valid + (io_dcache_axi4lite_aw_valid), + .io_dcache_aw_bits_addr + (io_dcache_axi4lite_aw_bits_addr), + .io_dcache_w_valid (io_dcache_axi4lite_w_valid), + .io_dcache_w_bits_data + (io_dcache_axi4lite_w_bits_data), + .io_dcache_w_bits_strb + (io_dcache_axi4lite_w_bits_strb), + .io_toExWbReg_valid + (_vectorLdstUnit_io_toExWbReg_valid), + .io_toExWbReg_bits_dataSignals_pc_addr + (_vectorLdstUnit_io_toExWbReg_bits_dataSignals_pc_addr), + .io_toExWbReg_bits_ctrlSignals_decode_branch + (_vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_branch), + .io_toExWbReg_bits_ctrlSignals_decode_writeback_selector + (_vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_writeback_selector), + .io_toExWbReg_bits_ctrlSignals_decode_memory_function + (_vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_memory_function), + .io_toExWbReg_bits_ctrlSignals_decode_csr_funct + (_vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_csr_funct), + .io_toExWbReg_bits_ctrlSignals_decode_fence + (_vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_fence), + .io_toExWbReg_bits_ctrlSignals_rd_index + (_vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_rd_index), + .io_toExWbReg_bits_vectorCsrPorts_vtype_vill + (_vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vill), + .io_toExWbReg_bits_vectorCsrPorts_vtype_vma + (_vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vma), + .io_toExWbReg_bits_vectorCsrPorts_vtype_vta + (_vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vta), + .io_toExWbReg_bits_vectorCsrPorts_vtype_vsew + (_vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vsew), + .io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul + (_vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul), + .io_toExWbReg_bits_vectorCsrPorts_vl + (_vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vl), + .io_toExWbReg_bits_vectorExecNum_valid + (_vectorLdstUnit_io_toExWbReg_bits_vectorExecNum_valid), + .io_toExWbReg_bits_vectorExecNum_bits + (_vectorLdstUnit_io_toExWbReg_bits_vectorExecNum_bits) + ); + CSRUnit csrUnit ( + .clock (clock), + .reset (reset), + .io_req_bits_funct_branch (EX_WB_REG_bits_ctrlSignals_decode_branch), + .io_req_bits_funct_csr_funct (EX_WB_REG_bits_ctrlSignals_decode_csr_funct), + .io_req_bits_data (EX_WB_REG_bits_dataSignals_datatoCSR), + .io_req_bits_csr_addr (EX_WB_REG_bits_dataSignals_csr_addr), + .io_fromCPU_cpu_operating (cpu_operating), + .io_fromCPU_inst_retire (WB_inst_can_retire), + .io_fromCPU_hartid (io_hartid), + .io_fromCPU_vectorExecNum_valid (EX_WB_REG_bits_vectorExecNum_valid), + .io_fromCPU_vectorExecNum_bits (EX_WB_REG_bits_vectorExecNum_bits), + .io_exception_valid + (EX_WB_REG_bits_exceptionSignals_valid & EX_WB_REG_valid), + .io_exception_bits_mepc_write (EX_WB_REG_bits_dataSignals_pc_addr), + .io_exception_bits_mcause_write (EX_WB_REG_bits_exceptionSignals_bits), + .io_vectorCsrPorts_vtype_vill (EX_WB_REG_bits_vectorCsrPorts_vtype_vill), + .io_vectorCsrPorts_vtype_vma (EX_WB_REG_bits_vectorCsrPorts_vtype_vma), + .io_vectorCsrPorts_vtype_vta (EX_WB_REG_bits_vectorCsrPorts_vtype_vta), + .io_vectorCsrPorts_vtype_vsew (EX_WB_REG_bits_vectorCsrPorts_vtype_vsew), + .io_vectorCsrPorts_vtype_vlmul (EX_WB_REG_bits_vectorCsrPorts_vtype_vlmul), + .io_vectorCsrPorts_vl (EX_WB_REG_bits_vectorCsrPorts_vl), + .io_resp_data (_csrUnit_io_resp_data) + ); + NonPipelinedMultiplierWrap multiplier ( + .clock (clock), + .reset (reset), + .io_req_valid + ((ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'h9 + | ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'hA + | ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'hB + | ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct == 4'hC) + & ~multiplier_hasValue & ID_EX_REG_valid & ~WB_pc_redirect), + .io_req_bits_rs1 (ID_EX_REG_bits_dataSignals_rs1), + .io_req_bits_rs2 (ID_EX_REG_bits_dataSignals_rs2), + .io_req_bits_funct_arithmetic_funct + (ID_EX_REG_bits_ctrlSignals_decode_arithmetic_funct), + .io_req_bits_funct_op32 (ID_EX_REG_bits_ctrlSignals_decode_op32), + .io_resp_valid (_multiplier_io_resp_valid), + .io_resp_bits (_multiplier_io_resp_bits) + ); + VectorDecoder vectorDecoder ( + .io_inst_bits (io_frontend_resp_bits_inst_bits), + .io_out_isConfsetInst (_vectorDecoder_io_out_isConfsetInst), + .io_out_avl_sel (_vectorDecoder_io_out_avl_sel), + .io_out_vtype_sel (_vectorDecoder_io_out_vtype_sel), + .io_out_mop (_vectorDecoder_io_out_mop), + .io_out_veuFun (_vectorDecoder_io_out_veuFun), + .io_out_vSource (_vectorDecoder_io_out_vSource), + .io_out_vm (_vectorDecoder_io_out_vm) + ); + VecCtrlUnit vecCtrlUnit ( + .io_req_valid + (ID_EX_REG_valid & ID_EX_REG_bits_ctrlSignals_decode_vector + & ID_EX_REG_bits_vectorCtrlSignals_isConfsetInst), + .io_req_bits_vDecode_avl_sel (ID_EX_REG_bits_vectorCtrlSignals_avl_sel), + .io_req_bits_vDecode_vtype_sel (ID_EX_REG_bits_vectorCtrlSignals_vtype_sel), + .io_req_bits_rs1_value (ID_EX_REG_bits_dataSignals_rs1), + .io_req_bits_rs2_value (ID_EX_REG_bits_dataSignals_rs2), + .io_req_bits_zimm ({52'h0, ID_EX_REG_bits_dataSignals_zimm}), + .io_req_bits_uimm (ID_EX_REG_bits_dataSignals_imm), + .io_resp_valid (_vecCtrlUnit_io_resp_valid), + .io_resp_bits_vtype_vill (_vecCtrlUnit_io_resp_bits_vtype_vill), + .io_resp_bits_vtype_vma (_vecCtrlUnit_io_resp_bits_vtype_vma), + .io_resp_bits_vtype_vta (_vecCtrlUnit_io_resp_bits_vtype_vta), + .io_resp_bits_vtype_vsew (_vecCtrlUnit_io_resp_bits_vtype_vsew), + .io_resp_bits_vtype_vlmul (_vecCtrlUnit_io_resp_bits_vtype_vlmul), + .io_resp_bits_vl (_vecCtrlUnit_io_resp_bits_vl) + ); + VecRegFile vecRegFile ( + .clock (clock), + .io_readReq_0_req_sew (_vectorLdstUnit_io_readVrf_req_sew), + .io_readReq_0_req_idx (_vectorLdstUnit_io_readVrf_req_idx), + .io_readReq_0_req_vs2 (_vectorLdstUnit_io_readVrf_req_vs2), + .io_readReq_0_req_vd (_vectorLdstUnit_io_readVrf_req_vd), + .io_readReq_1_req_sew (_vecAluExecUnit_0_io_readVrf_req_sew), + .io_readReq_1_req_readVdAsMaskSource + (_vecAluExecUnit_0_io_readVrf_req_readVdAsMaskSource), + .io_readReq_1_req_idx (_vecAluExecUnit_0_io_readVrf_req_idx), + .io_readReq_1_req_vs1 (_vecAluExecUnit_0_io_readVrf_req_vs1), + .io_readReq_1_req_vs2 (_vecAluExecUnit_0_io_readVrf_req_vs2), + .io_readReq_1_req_vd (_vecAluExecUnit_0_io_readVrf_req_vd), + .io_readReq_2_req_sew (_vecAluExecUnit_1_io_readVrf_req_sew), + .io_readReq_2_req_readVdAsMaskSource + (_vecAluExecUnit_1_io_readVrf_req_readVdAsMaskSource), + .io_readReq_2_req_idx (_vecAluExecUnit_1_io_readVrf_req_idx), + .io_readReq_2_req_vs1 (_vecAluExecUnit_1_io_readVrf_req_vs1), + .io_readReq_2_req_vs2 (_vecAluExecUnit_1_io_readVrf_req_vs2), + .io_readReq_2_req_vd (_vecAluExecUnit_1_io_readVrf_req_vd), + .io_writeReq_0_valid (_vectorLdstUnit_io_vectorResp_toVRF_valid), + .io_writeReq_0_bits_vd (_vectorLdstUnit_io_vectorResp_toVRF_bits_vd), + .io_writeReq_0_bits_vtype_vsew + (_vectorLdstUnit_io_vectorResp_toVRF_bits_vtype_vsew), + .io_writeReq_0_bits_index (_vectorLdstUnit_io_vectorResp_toVRF_bits_index), + .io_writeReq_0_bits_data (_vectorLdstUnit_io_vectorResp_toVRF_bits_data), + .io_writeReq_0_bits_writeReq + (_vectorLdstUnit_io_vectorResp_toVRF_bits_writeReq), + .io_writeReq_1_valid (_vecAluExecUnit_0_io_dataOut_toVRF_valid), + .io_writeReq_1_bits_vd (_vecAluExecUnit_0_io_dataOut_toVRF_bits_vd), + .io_writeReq_1_bits_vtype_vsew + (_vecAluExecUnit_0_io_dataOut_toVRF_bits_vtype_vsew), + .io_writeReq_1_bits_index (_vecAluExecUnit_0_io_dataOut_toVRF_bits_index), + .io_writeReq_1_bits_data (_vecAluExecUnit_0_io_dataOut_toVRF_bits_data), + .io_writeReq_1_bits_writeReq + (_vecAluExecUnit_0_io_dataOut_toVRF_bits_writeReq), + .io_writeReq_2_valid (_vecAluExecUnit_1_io_dataOut_toVRF_valid), + .io_writeReq_2_bits_vd (_vecAluExecUnit_1_io_dataOut_toVRF_bits_vd), + .io_writeReq_2_bits_vtype_vsew + (_vecAluExecUnit_1_io_dataOut_toVRF_bits_vtype_vsew), + .io_writeReq_2_bits_index (_vecAluExecUnit_1_io_dataOut_toVRF_bits_index), + .io_writeReq_2_bits_data (_vecAluExecUnit_1_io_dataOut_toVRF_bits_data), + .io_writeReq_2_bits_writeReq + (_vecAluExecUnit_1_io_dataOut_toVRF_bits_writeReq), + .io_readReq_0_resp_vs2Out (_vecRegFile_io_readReq_0_resp_vs2Out), + .io_readReq_0_resp_vdOut (_vecRegFile_io_readReq_0_resp_vdOut), + .io_readReq_0_resp_vm (_vecRegFile_io_readReq_0_resp_vm), + .io_readReq_1_resp_vs1Out (_vecRegFile_io_readReq_1_resp_vs1Out), + .io_readReq_1_resp_vs2Out (_vecRegFile_io_readReq_1_resp_vs2Out), + .io_readReq_1_resp_vdOut (_vecRegFile_io_readReq_1_resp_vdOut), + .io_readReq_1_resp_vm (_vecRegFile_io_readReq_1_resp_vm), + .io_readReq_2_resp_vs1Out (_vecRegFile_io_readReq_2_resp_vs1Out), + .io_readReq_2_resp_vs2Out (_vecRegFile_io_readReq_2_resp_vs2Out), + .io_readReq_2_resp_vdOut (_vecRegFile_io_readReq_2_resp_vdOut), + .io_readReq_2_resp_vm (_vecRegFile_io_readReq_2_resp_vm) + ); + VrfReadyTable vrfReadyTable ( + .clock (clock), + .reset (reset), + .io_fromVecExecUnit_0_valid (_vectorLdstUnit_io_vectorResp_toVRF_valid), + .io_fromVecExecUnit_0_bits_vd (_vectorLdstUnit_io_vectorResp_toVRF_bits_vd), + .io_fromVecExecUnit_0_bits_vtype_vsew + (_vectorLdstUnit_io_vectorResp_toVRF_bits_vtype_vsew), + .io_fromVecExecUnit_0_bits_index + (_vectorLdstUnit_io_vectorResp_toVRF_bits_index), + .io_fromVecExecUnit_0_bits_last (_vectorLdstUnit_io_vectorResp_toVRF_bits_last), + .io_fromVecExecUnit_0_bits_writeReq + (_vectorLdstUnit_io_vectorResp_toVRF_bits_writeReq), + .io_fromVecExecUnit_1_valid (_vecAluExecUnit_0_io_dataOut_toVRF_valid), + .io_fromVecExecUnit_1_bits_vd (_vecAluExecUnit_0_io_dataOut_toVRF_bits_vd), + .io_fromVecExecUnit_1_bits_vtype_vsew + (_vecAluExecUnit_0_io_dataOut_toVRF_bits_vtype_vsew), + .io_fromVecExecUnit_1_bits_index (_vecAluExecUnit_0_io_dataOut_toVRF_bits_index), + .io_fromVecExecUnit_1_bits_last (_vecAluExecUnit_0_io_dataOut_toVRF_bits_last), + .io_fromVecExecUnit_1_bits_vm (_vecAluExecUnit_0_io_dataOut_toVRF_bits_vm), + .io_fromVecExecUnit_1_bits_writeReq + (_vecAluExecUnit_0_io_dataOut_toVRF_bits_writeReq), + .io_fromVecExecUnit_2_valid (_vecAluExecUnit_1_io_dataOut_toVRF_valid), + .io_fromVecExecUnit_2_bits_vd (_vecAluExecUnit_1_io_dataOut_toVRF_bits_vd), + .io_fromVecExecUnit_2_bits_vtype_vsew + (_vecAluExecUnit_1_io_dataOut_toVRF_bits_vtype_vsew), + .io_fromVecExecUnit_2_bits_index (_vecAluExecUnit_1_io_dataOut_toVRF_bits_index), + .io_fromVecExecUnit_2_bits_last (_vecAluExecUnit_1_io_dataOut_toVRF_bits_last), + .io_fromVecExecUnit_2_bits_vm (_vecAluExecUnit_1_io_dataOut_toVRF_bits_vm), + .io_fromVecExecUnit_2_bits_writeReq + (_vecAluExecUnit_1_io_dataOut_toVRF_bits_writeReq), + .io_invalidateVd + (ID_inst_valid & _decoder_io_out_valid & _decoder_io_out_bits_vector + & ~_vectorDecoder_io_out_isConfsetInst + & _decoder_io_out_bits_memory_function != 2'h2 + & ~(_vectorDecoder_io_out_veuFun == 6'h31 + | _vectorDecoder_io_out_veuFun == 6'h32)), + .io_vs1Check_valid (_vrfReadyTable_io_vs1Check_valid_T_8), + .io_vs1Check_bits_idx (io_frontend_resp_bits_inst_bits[19:15]), + .io_vs1Check_bits_vtype_vsew (vecConfBypass_vtype_vsew), + .io_vs1Check_bits_vm + (_vectorDecoder_io_out_veuFun == 6'h19 | _vectorDecoder_io_out_veuFun == 6'h1A + | _vectorDecoder_io_out_veuFun == 6'h1B | _vectorDecoder_io_out_veuFun == 6'h1C + | _vectorDecoder_io_out_veuFun == 6'h1D | _vectorDecoder_io_out_veuFun == 6'h1E + | _vectorDecoder_io_out_veuFun == 6'h1F | _vectorDecoder_io_out_veuFun == 6'h20), + .io_vs2Check_valid (_vrfReadyTable_io_vs2Check_valid_T_8), + .io_vs2Check_bits_idx (io_frontend_resp_bits_inst_bits[24:20]), + .io_vs2Check_bits_vtype_vsew (vecConfBypass_vtype_vsew), + .io_vs2Check_bits_vm + (_vectorDecoder_io_out_veuFun == 6'h19 | _vectorDecoder_io_out_veuFun == 6'h1A + | _vectorDecoder_io_out_veuFun == 6'h1B | _vectorDecoder_io_out_veuFun == 6'h1C + | _vectorDecoder_io_out_veuFun == 6'h1D | _vectorDecoder_io_out_veuFun == 6'h1E + | _vectorDecoder_io_out_veuFun == 6'h1F | _vectorDecoder_io_out_veuFun == 6'h20), + .io_vdCheck_valid (_vrfReadyTable_io_vdCheck_valid_T_2), + .io_vdCheck_bits_idx (io_frontend_resp_bits_inst_bits[11:7]), + .io_vdCheck_bits_vtype_vsew (vecConfBypass_vtype_vsew), + .io_vdCheck_bits_vm + (_vectorDecoder_io_out_veuFun == 6'h8 | _vectorDecoder_io_out_veuFun == 6'h9 + | _vectorDecoder_io_out_veuFun == 6'hA | _vectorDecoder_io_out_veuFun == 6'hB + | _vectorDecoder_io_out_veuFun == 6'hC | _vectorDecoder_io_out_veuFun == 6'hD + | _vectorDecoder_io_out_veuFun == 6'hE | _vectorDecoder_io_out_veuFun == 6'hF + | _vectorDecoder_io_out_veuFun == 6'h5 | _vectorDecoder_io_out_veuFun == 6'h7 + | _vectorDecoder_io_out_veuFun == 6'h19 | _vectorDecoder_io_out_veuFun == 6'h1A + | _vectorDecoder_io_out_veuFun == 6'h1B | _vectorDecoder_io_out_veuFun == 6'h1C + | _vectorDecoder_io_out_veuFun == 6'h1D | _vectorDecoder_io_out_veuFun == 6'h1E + | _vectorDecoder_io_out_veuFun == 6'h1F | _vectorDecoder_io_out_veuFun == 6'h20), + .io_vmCheck_valid (_vrfReadyTable_io_vmCheck_valid_T_4), + .io_vs1Check_ready (_vrfReadyTable_io_vs1Check_ready), + .io_vs2Check_ready (_vrfReadyTable_io_vs2Check_ready), + .io_vdCheck_ready (_vrfReadyTable_io_vdCheck_ready), + .io_vmCheck_ready (_vrfReadyTable_io_vmCheck_ready) + ); + IntegerAluExecUnit vecAluExecUnit_0 ( + .clock (clock), + .reset (reset), + .io_signalIn_valid + (~_T_17 & _T_9 & _vecAluExecUnit_0_io_signalIn_ready), + .io_signalIn_bits_vs1 + (io_frontend_resp_bits_inst_bits[19:15]), + .io_signalIn_bits_vs2 + (io_frontend_resp_bits_inst_bits[24:20]), + .io_signalIn_bits_vd + (io_frontend_resp_bits_inst_bits[11:7]), + .io_signalIn_bits_scalarVal + (_vectorDecoder_io_out_vSource == 3'h1 + ? rs1ValueToEX + : {{59{io_frontend_resp_bits_inst_bits[19]}}, + io_frontend_resp_bits_inst_bits[19:15]}), + .io_signalIn_bits_vectorDecode_veuFun + (_vectorDecoder_io_out_veuFun), + .io_signalIn_bits_vectorDecode_vSource + (_vectorDecoder_io_out_vSource), + .io_signalIn_bits_vectorDecode_vm (_vectorDecoder_io_out_vm), + .io_signalIn_bits_scalarDecode_branch + (_decoder_io_out_bits_branch), + .io_signalIn_bits_scalarDecode_writeback_selector + (_decoder_io_out_bits_writeback_selector), + .io_signalIn_bits_scalarDecode_memory_function + (_decoder_io_out_bits_memory_function), + .io_signalIn_bits_scalarDecode_csr_funct + (_decoder_io_out_bits_csr_funct), + .io_signalIn_bits_scalarDecode_fence (_decoder_io_out_bits_fence), + .io_signalIn_bits_vecConf_vtype_vill (vecConfBypass_vtype_vill), + .io_signalIn_bits_vecConf_vtype_vma (vecConfBypass_vtype_vma), + .io_signalIn_bits_vecConf_vtype_vta (vecConfBypass_vtype_vta), + .io_signalIn_bits_vecConf_vtype_vsew (vecConfBypass_vtype_vsew), + .io_signalIn_bits_vecConf_vtype_vlmul (vecConfBypass_vtype_vlmul), + .io_signalIn_bits_vecConf_vl (vecConfBypass_vl), + .io_signalIn_bits_pc_addr + (io_frontend_resp_bits_pc_addr), + .io_readVrf_resp_vs1Out + (_vecRegFile_io_readReq_1_resp_vs1Out), + .io_readVrf_resp_vs2Out + (_vecRegFile_io_readReq_1_resp_vs2Out), + .io_readVrf_resp_vdOut + (_vecRegFile_io_readReq_1_resp_vdOut), + .io_readVrf_resp_vm + (_vecRegFile_io_readReq_1_resp_vm), + .io_signalIn_ready + (_vecAluExecUnit_0_io_signalIn_ready), + .io_readVrf_req_sew + (_vecAluExecUnit_0_io_readVrf_req_sew), + .io_readVrf_req_readVdAsMaskSource + (_vecAluExecUnit_0_io_readVrf_req_readVdAsMaskSource), + .io_readVrf_req_idx + (_vecAluExecUnit_0_io_readVrf_req_idx), + .io_readVrf_req_vs1 + (_vecAluExecUnit_0_io_readVrf_req_vs1), + .io_readVrf_req_vs2 + (_vecAluExecUnit_0_io_readVrf_req_vs2), + .io_readVrf_req_vd + (_vecAluExecUnit_0_io_readVrf_req_vd), + .io_dataOut_toVRF_valid + (_vecAluExecUnit_0_io_dataOut_toVRF_valid), + .io_dataOut_toVRF_bits_vd + (_vecAluExecUnit_0_io_dataOut_toVRF_bits_vd), + .io_dataOut_toVRF_bits_vtype_vsew + (_vecAluExecUnit_0_io_dataOut_toVRF_bits_vtype_vsew), + .io_dataOut_toVRF_bits_index + (_vecAluExecUnit_0_io_dataOut_toVRF_bits_index), + .io_dataOut_toVRF_bits_last + (_vecAluExecUnit_0_io_dataOut_toVRF_bits_last), + .io_dataOut_toVRF_bits_data + (_vecAluExecUnit_0_io_dataOut_toVRF_bits_data), + .io_dataOut_toVRF_bits_vm + (_vecAluExecUnit_0_io_dataOut_toVRF_bits_vm), + .io_dataOut_toVRF_bits_writeReq + (_vecAluExecUnit_0_io_dataOut_toVRF_bits_writeReq), + .io_toExWbReg_valid + (_vecAluExecUnit_0_io_toExWbReg_valid), + .io_toExWbReg_bits_dataSignals_pc_addr + (_vecAluExecUnit_0_io_toExWbReg_bits_dataSignals_pc_addr), + .io_toExWbReg_bits_dataSignals_exResult + (_vecAluExecUnit_0_io_toExWbReg_bits_dataSignals_exResult), + .io_toExWbReg_bits_ctrlSignals_decode_branch + (_vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_branch), + .io_toExWbReg_bits_ctrlSignals_decode_writeback_selector + (_vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_writeback_selector), + .io_toExWbReg_bits_ctrlSignals_decode_memory_function + (_vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_memory_function), + .io_toExWbReg_bits_ctrlSignals_decode_csr_funct + (_vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_csr_funct), + .io_toExWbReg_bits_ctrlSignals_decode_fence + (_vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_fence), + .io_toExWbReg_bits_ctrlSignals_rd_index + (_vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_rd_index), + .io_toExWbReg_bits_vectorCsrPorts_vtype_vill + (_vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vill), + .io_toExWbReg_bits_vectorCsrPorts_vtype_vma + (_vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vma), + .io_toExWbReg_bits_vectorCsrPorts_vtype_vta + (_vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vta), + .io_toExWbReg_bits_vectorCsrPorts_vtype_vsew + (_vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vsew), + .io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul + (_vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul), + .io_toExWbReg_bits_vectorCsrPorts_vl + (_vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vl), + .io_toExWbReg_bits_vectorExecNum_valid + (_vecAluExecUnit_0_io_toExWbReg_bits_vectorExecNum_valid), + .io_toExWbReg_bits_vectorExecNum_bits + (_vecAluExecUnit_0_io_toExWbReg_bits_vectorExecNum_bits) + ); + IntegerAluExecUnit vecAluExecUnit_1 ( + .clock (clock), + .reset (reset), + .io_signalIn_valid (~_T_17 & _T_9 & _T_14), + .io_signalIn_bits_vs1 + (io_frontend_resp_bits_inst_bits[19:15]), + .io_signalIn_bits_vs2 + (io_frontend_resp_bits_inst_bits[24:20]), + .io_signalIn_bits_vd + (io_frontend_resp_bits_inst_bits[11:7]), + .io_signalIn_bits_scalarVal + (_vectorDecoder_io_out_vSource == 3'h1 + ? rs1ValueToEX + : {{59{io_frontend_resp_bits_inst_bits[19]}}, + io_frontend_resp_bits_inst_bits[19:15]}), + .io_signalIn_bits_vectorDecode_veuFun + (_vectorDecoder_io_out_veuFun), + .io_signalIn_bits_vectorDecode_vSource + (_vectorDecoder_io_out_vSource), + .io_signalIn_bits_vectorDecode_vm (_vectorDecoder_io_out_vm), + .io_signalIn_bits_scalarDecode_branch + (_decoder_io_out_bits_branch), + .io_signalIn_bits_scalarDecode_writeback_selector + (_decoder_io_out_bits_writeback_selector), + .io_signalIn_bits_scalarDecode_memory_function + (_decoder_io_out_bits_memory_function), + .io_signalIn_bits_scalarDecode_csr_funct + (_decoder_io_out_bits_csr_funct), + .io_signalIn_bits_scalarDecode_fence (_decoder_io_out_bits_fence), + .io_signalIn_bits_vecConf_vtype_vill (vecConfBypass_vtype_vill), + .io_signalIn_bits_vecConf_vtype_vma (vecConfBypass_vtype_vma), + .io_signalIn_bits_vecConf_vtype_vta (vecConfBypass_vtype_vta), + .io_signalIn_bits_vecConf_vtype_vsew (vecConfBypass_vtype_vsew), + .io_signalIn_bits_vecConf_vtype_vlmul (vecConfBypass_vtype_vlmul), + .io_signalIn_bits_vecConf_vl (vecConfBypass_vl), + .io_signalIn_bits_pc_addr + (io_frontend_resp_bits_pc_addr), + .io_readVrf_resp_vs1Out + (_vecRegFile_io_readReq_2_resp_vs1Out), + .io_readVrf_resp_vs2Out + (_vecRegFile_io_readReq_2_resp_vs2Out), + .io_readVrf_resp_vdOut + (_vecRegFile_io_readReq_2_resp_vdOut), + .io_readVrf_resp_vm + (_vecRegFile_io_readReq_2_resp_vm), + .io_signalIn_ready + (_vecAluExecUnit_1_io_signalIn_ready), + .io_readVrf_req_sew + (_vecAluExecUnit_1_io_readVrf_req_sew), + .io_readVrf_req_readVdAsMaskSource + (_vecAluExecUnit_1_io_readVrf_req_readVdAsMaskSource), + .io_readVrf_req_idx + (_vecAluExecUnit_1_io_readVrf_req_idx), + .io_readVrf_req_vs1 + (_vecAluExecUnit_1_io_readVrf_req_vs1), + .io_readVrf_req_vs2 + (_vecAluExecUnit_1_io_readVrf_req_vs2), + .io_readVrf_req_vd + (_vecAluExecUnit_1_io_readVrf_req_vd), + .io_dataOut_toVRF_valid + (_vecAluExecUnit_1_io_dataOut_toVRF_valid), + .io_dataOut_toVRF_bits_vd + (_vecAluExecUnit_1_io_dataOut_toVRF_bits_vd), + .io_dataOut_toVRF_bits_vtype_vsew + (_vecAluExecUnit_1_io_dataOut_toVRF_bits_vtype_vsew), + .io_dataOut_toVRF_bits_index + (_vecAluExecUnit_1_io_dataOut_toVRF_bits_index), + .io_dataOut_toVRF_bits_last + (_vecAluExecUnit_1_io_dataOut_toVRF_bits_last), + .io_dataOut_toVRF_bits_data + (_vecAluExecUnit_1_io_dataOut_toVRF_bits_data), + .io_dataOut_toVRF_bits_vm + (_vecAluExecUnit_1_io_dataOut_toVRF_bits_vm), + .io_dataOut_toVRF_bits_writeReq + (_vecAluExecUnit_1_io_dataOut_toVRF_bits_writeReq), + .io_toExWbReg_valid + (_vecAluExecUnit_1_io_toExWbReg_valid), + .io_toExWbReg_bits_dataSignals_pc_addr + (_vecAluExecUnit_1_io_toExWbReg_bits_dataSignals_pc_addr), + .io_toExWbReg_bits_dataSignals_exResult + (_vecAluExecUnit_1_io_toExWbReg_bits_dataSignals_exResult), + .io_toExWbReg_bits_ctrlSignals_decode_branch + (_vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_branch), + .io_toExWbReg_bits_ctrlSignals_decode_writeback_selector + (_vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_writeback_selector), + .io_toExWbReg_bits_ctrlSignals_decode_memory_function + (_vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_memory_function), + .io_toExWbReg_bits_ctrlSignals_decode_csr_funct + (_vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_csr_funct), + .io_toExWbReg_bits_ctrlSignals_decode_fence + (_vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_fence), + .io_toExWbReg_bits_ctrlSignals_rd_index + (_vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_rd_index), + .io_toExWbReg_bits_vectorCsrPorts_vtype_vill + (_vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vill), + .io_toExWbReg_bits_vectorCsrPorts_vtype_vma + (_vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vma), + .io_toExWbReg_bits_vectorCsrPorts_vtype_vta + (_vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vta), + .io_toExWbReg_bits_vectorCsrPorts_vtype_vsew + (_vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vsew), + .io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul + (_vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul), + .io_toExWbReg_bits_vectorCsrPorts_vl + (_vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vl), + .io_toExWbReg_bits_vectorExecNum_valid + (_vecAluExecUnit_1_io_toExWbReg_bits_vectorExecNum_valid), + .io_toExWbReg_bits_vectorExecNum_bits + (_vecAluExecUnit_1_io_toExWbReg_bits_vectorExecNum_bits) + ); + assign io_frontend_req_valid = + WB_pc_redirect | _io_frontend_req_valid_T | _branch_predictor_io_out_valid + & io_frontend_resp_valid & _io_frontend_resp_ready_output; + assign io_frontend_req_bits_pc = + WB_pc_redirect + ? _csrUnit_io_resp_data + : _io_frontend_req_valid_T + ? _branch_evaluator_io_out_bits_pc + : _branch_predictor_io_out_bits_pc; + assign io_frontend_resp_ready = _io_frontend_resp_ready_output; +endmodule + +module Core( + input clock, + reset, + io_icache_axi4lite_ar_ready, + io_icache_axi4lite_aw_ready, + io_icache_axi4lite_b_valid, + input [2:0] io_icache_axi4lite_b_bits_resp, + input io_icache_axi4lite_r_valid, + input [31:0] io_icache_axi4lite_r_bits_data, + input [2:0] io_icache_axi4lite_r_bits_resp, + input io_icache_axi4lite_w_ready, + io_dcache_axi4lite_ar_ready, + io_dcache_axi4lite_aw_ready, + io_dcache_axi4lite_b_valid, + input [2:0] io_dcache_axi4lite_b_bits_resp, + input io_dcache_axi4lite_r_valid, + input [63:0] io_dcache_axi4lite_r_bits_data, + input [2:0] io_dcache_axi4lite_r_bits_resp, + input io_dcache_axi4lite_w_ready, + input [63:0] io_reset_vector, + io_hartid, + output io_icache_axi4lite_ar_valid, + output [63:0] io_icache_axi4lite_ar_bits_addr, + output [2:0] io_icache_axi4lite_ar_bits_prot, + output io_icache_axi4lite_aw_valid, + output [63:0] io_icache_axi4lite_aw_bits_addr, + output [2:0] io_icache_axi4lite_aw_bits_prot, + output io_icache_axi4lite_b_ready, + io_icache_axi4lite_r_ready, + io_icache_axi4lite_w_valid, + output [31:0] io_icache_axi4lite_w_bits_data, + output [3:0] io_icache_axi4lite_w_bits_strb, + output io_dcache_axi4lite_ar_valid, + output [63:0] io_dcache_axi4lite_ar_bits_addr, + output [2:0] io_dcache_axi4lite_ar_bits_prot, + output io_dcache_axi4lite_aw_valid, + output [63:0] io_dcache_axi4lite_aw_bits_addr, + output [2:0] io_dcache_axi4lite_aw_bits_prot, + output io_dcache_axi4lite_b_ready, + io_dcache_axi4lite_r_ready, + io_dcache_axi4lite_w_valid, + output [63:0] io_dcache_axi4lite_w_bits_data, + output [7:0] io_dcache_axi4lite_w_bits_strb +); + + wire _internalCpu_io_frontend_req_valid; + wire [63:0] _internalCpu_io_frontend_req_bits_pc; + wire _internalCpu_io_frontend_resp_ready; + wire _frontend_io_cpu_resp_valid; + wire [63:0] _frontend_io_cpu_resp_bits_pc_addr; + wire [31:0] _frontend_io_cpu_resp_bits_inst_bits; + wire _frontend_io_cpu_resp_bits_exceptionSignals_valid; + wire [63:0] _frontend_io_cpu_resp_bits_exceptionSignals_bits; + Frontend frontend ( + .clock (clock), + .reset (reset), + .io_cpu_req_valid (_internalCpu_io_frontend_req_valid), + .io_cpu_req_bits_pc (_internalCpu_io_frontend_req_bits_pc), + .io_cpu_resp_ready (_internalCpu_io_frontend_resp_ready), + .io_icache_axi4lite_ar_ready (io_icache_axi4lite_ar_ready), + .io_icache_axi4lite_r_valid (io_icache_axi4lite_r_valid), + .io_icache_axi4lite_r_bits_data (io_icache_axi4lite_r_bits_data), + .io_reset_vector (io_reset_vector), + .io_cpu_resp_valid (_frontend_io_cpu_resp_valid), + .io_cpu_resp_bits_pc_addr (_frontend_io_cpu_resp_bits_pc_addr), + .io_cpu_resp_bits_inst_bits (_frontend_io_cpu_resp_bits_inst_bits), + .io_cpu_resp_bits_exceptionSignals_valid + (_frontend_io_cpu_resp_bits_exceptionSignals_valid), + .io_cpu_resp_bits_exceptionSignals_bits + (_frontend_io_cpu_resp_bits_exceptionSignals_bits), + .io_icache_axi4lite_ar_valid (io_icache_axi4lite_ar_valid), + .io_icache_axi4lite_ar_bits_addr (io_icache_axi4lite_ar_bits_addr), + .io_icache_axi4lite_r_ready (io_icache_axi4lite_r_ready) + ); + VectorCpu internalCpu ( + .clock (clock), + .reset (reset), + .io_frontend_resp_valid (_frontend_io_cpu_resp_valid), + .io_frontend_resp_bits_pc_addr (_frontend_io_cpu_resp_bits_pc_addr), + .io_frontend_resp_bits_inst_bits (_frontend_io_cpu_resp_bits_inst_bits), + .io_frontend_resp_bits_exceptionSignals_valid + (_frontend_io_cpu_resp_bits_exceptionSignals_valid), + .io_frontend_resp_bits_exceptionSignals_bits + (_frontend_io_cpu_resp_bits_exceptionSignals_bits), + .io_dcache_axi4lite_ar_ready (io_dcache_axi4lite_ar_ready), + .io_dcache_axi4lite_aw_ready (io_dcache_axi4lite_aw_ready), + .io_dcache_axi4lite_b_valid (io_dcache_axi4lite_b_valid), + .io_dcache_axi4lite_r_valid (io_dcache_axi4lite_r_valid), + .io_dcache_axi4lite_r_bits_data (io_dcache_axi4lite_r_bits_data), + .io_dcache_axi4lite_w_ready (io_dcache_axi4lite_w_ready), + .io_hartid (io_hartid), + .io_frontend_req_valid (_internalCpu_io_frontend_req_valid), + .io_frontend_req_bits_pc (_internalCpu_io_frontend_req_bits_pc), + .io_frontend_resp_ready (_internalCpu_io_frontend_resp_ready), + .io_dcache_axi4lite_ar_valid (io_dcache_axi4lite_ar_valid), + .io_dcache_axi4lite_ar_bits_addr (io_dcache_axi4lite_ar_bits_addr), + .io_dcache_axi4lite_aw_valid (io_dcache_axi4lite_aw_valid), + .io_dcache_axi4lite_aw_bits_addr (io_dcache_axi4lite_aw_bits_addr), + .io_dcache_axi4lite_w_valid (io_dcache_axi4lite_w_valid), + .io_dcache_axi4lite_w_bits_data (io_dcache_axi4lite_w_bits_data), + .io_dcache_axi4lite_w_bits_strb (io_dcache_axi4lite_w_bits_strb) + ); + assign io_icache_axi4lite_ar_bits_prot = 3'h0; + assign io_icache_axi4lite_aw_valid = 1'h0; + assign io_icache_axi4lite_aw_bits_addr = 64'h0; + assign io_icache_axi4lite_aw_bits_prot = 3'h0; + assign io_icache_axi4lite_b_ready = 1'h0; + assign io_icache_axi4lite_w_valid = 1'h0; + assign io_icache_axi4lite_w_bits_data = 32'h0; + assign io_icache_axi4lite_w_bits_strb = 4'h0; + assign io_dcache_axi4lite_ar_bits_prot = 3'h0; + assign io_dcache_axi4lite_aw_bits_prot = 3'h0; + assign io_dcache_axi4lite_b_ready = 1'h1; + assign io_dcache_axi4lite_r_ready = 1'h1; +endmodule + diff --git a/fpga/Dcache_for_Verilator.sv b/fpga/Dcache_for_Verilator.sv new file mode 100644 index 00000000..a93e8370 --- /dev/null +++ b/fpga/Dcache_for_Verilator.sv @@ -0,0 +1,155 @@ +// Generated by CIRCT firtool-1.38.0 +// VCS coverage exclude_file +module mem_combMem_Data( + input [11:0] R0_addr, + input R0_en, + R0_clk, + input [11:0] W0_addr, + input W0_en, + W0_clk, + input [63:0] W0_data, + input [7:0] W0_mask, + output [63:0] R0_data +); + + (* rw_addr_collision = "yes" *) + reg [63:0] Memory[0:4095]; + + initial begin + $readmemh("vector_matmul_data.mem", Memory); + end + + reg _GEN; + reg [11:0] _GEN_0; + always @(posedge R0_clk) begin + _GEN <= R0_en; + _GEN_0 <= R0_addr; + end // always @(posedge) + always @(posedge W0_clk) begin + if (W0_en & W0_mask[0]) + Memory[W0_addr][32'h0 +: 8] <= W0_data[7:0]; + if (W0_en & W0_mask[1]) + Memory[W0_addr][32'h8 +: 8] <= W0_data[15:8]; + if (W0_en & W0_mask[2]) + Memory[W0_addr][32'h10 +: 8] <= W0_data[23:16]; + if (W0_en & W0_mask[3]) + Memory[W0_addr][32'h18 +: 8] <= W0_data[31:24]; + if (W0_en & W0_mask[4]) + Memory[W0_addr][32'h20 +: 8] <= W0_data[39:32]; + if (W0_en & W0_mask[5]) + Memory[W0_addr][32'h28 +: 8] <= W0_data[47:40]; + if (W0_en & W0_mask[6]) + Memory[W0_addr][32'h30 +: 8] <= W0_data[55:48]; + if (W0_en & W0_mask[7]) + Memory[W0_addr][32'h38 +: 8] <= W0_data[63:56]; + end // always @(posedge) + assign R0_data = _GEN ? Memory[_GEN_0] : 64'bx; +endmodule + +module Dcache_for_Verilator( + input clock, + reset, + io_ar_valid, + input [63:0] io_ar_bits_addr, + input [2:0] io_ar_bits_prot, + input io_aw_valid, + input [63:0] io_aw_bits_addr, + input [2:0] io_aw_bits_prot, + input io_b_ready, + io_r_ready, + io_w_valid, + input [63:0] io_w_bits_data, + input [7:0] io_w_bits_strb, + output io_ar_ready, + io_aw_ready, + io_b_valid, + output [2:0] io_b_bits_resp, + output io_r_valid, + output [63:0] io_r_bits_data, + output [2:0] io_r_bits_resp, + output io_w_ready, + debug_valid, + output [31:0] debug_bits +); + + wire [63:0] _mem_ext_R0_data; + reg debugToHost_valid; + reg [31:0] debugToHost_bits; + wire [14:0] _GEN = io_ar_bits_addr[14:0] - 15'h4000; + wire [63:0] internalWriteAddr = io_aw_bits_addr - 64'h4000; + reg [2:0] io_r_bits_data_REG; + wire [7:0][63:0] _GEN_0 = + {{{56'h0, _mem_ext_R0_data[63:56]}}, + {{48'h0, _mem_ext_R0_data[63:48]}}, + {{40'h0, _mem_ext_R0_data[63:40]}}, + {{32'h0, _mem_ext_R0_data[63:32]}}, + {{24'h0, _mem_ext_R0_data[63:24]}}, + {{16'h0, _mem_ext_R0_data[63:16]}}, + {{8'h0, _mem_ext_R0_data[63:8]}}, + {_mem_ext_R0_data}}; + reg io_r_valid_REG; + wire [63:0] _GEN_1 = + internalWriteAddr[2:0] == 3'h2 + ? {io_w_bits_data[47:0], 16'h0} + : internalWriteAddr[2:0] == 3'h1 ? {io_w_bits_data[55:0], 8'h0} : io_w_bits_data; + wire [7:0][63:0] _GEN_2 = + {{{io_w_bits_data[7:0], 56'h0}}, + {{io_w_bits_data[15:0], 48'h0}}, + {{io_w_bits_data[23:0], 40'h0}}, + {{io_w_bits_data[31:0], 32'h0}}, + {{io_w_bits_data[39:0], 24'h0}}, + {_GEN_1}, + {_GEN_1}, + {_GEN_1}}; + wire _io_b_valid_T = io_aw_valid & io_w_valid; + wire mem_MPORT_en = _io_b_valid_T & internalWriteAddr < 64'h1FFF; + wire [7:0][7:0] _GEN_3 = + {{{io_w_bits_strb[0], 7'h0}}, + {{io_w_bits_strb[1:0], 6'h0}}, + {{io_w_bits_strb[2:0], 5'h0}}, + {{io_w_bits_strb[3:0], 4'h0}}, + {{io_w_bits_strb[4:0], 3'h0}}, + {{io_w_bits_strb[5:0], 2'h0}}, + {{io_w_bits_strb[6:0], 1'h0}}, + {io_w_bits_strb}}; + reg io_b_valid_REG; + always @(posedge clock) begin + if (reset) begin + debugToHost_valid <= 1'h0; + debugToHost_bits <= 32'h0; + end + else begin + automatic logic _T_46 = _io_b_valid_T & io_aw_bits_addr == 64'h10000000; + debugToHost_valid <= ~mem_MPORT_en & _T_46; + if (mem_MPORT_en | ~_T_46) begin + end + else + debugToHost_bits <= io_w_bits_data[31:0]; + end + io_r_bits_data_REG <= _GEN[2:0]; + io_r_valid_REG <= io_ar_valid; + io_b_valid_REG <= _io_b_valid_T; + end // always @(posedge) + mem_combMem_Data mem_ext ( + .R0_addr (_GEN[14:3]), + .R0_en (1'h1), + .R0_clk (clock), + .W0_addr (internalWriteAddr[14:3]), + .W0_en (mem_MPORT_en), + .W0_clk (clock), + .W0_data (_GEN_2[internalWriteAddr[2:0]]), + .W0_mask (_GEN_3[internalWriteAddr[2:0]]), + .R0_data (_mem_ext_R0_data) + ); + assign io_ar_ready = 1'h1; + assign io_aw_ready = 1'h1; + assign io_b_valid = io_b_valid_REG; + assign io_b_bits_resp = 3'h0; + assign io_r_valid = io_r_valid_REG; + assign io_r_bits_data = _GEN_0[io_r_bits_data_REG]; + assign io_r_bits_resp = 3'h0; + assign io_w_ready = 1'h1; + assign debug_valid = debugToHost_valid; + assign debug_bits = debugToHost_bits; +endmodule + diff --git a/fpga/Icache_for_Verilator.sv b/fpga/Icache_for_Verilator.sv new file mode 100644 index 00000000..839b0d69 --- /dev/null +++ b/fpga/Icache_for_Verilator.sv @@ -0,0 +1,120 @@ +// Generated by CIRCT firtool-1.38.0 +// VCS coverage exclude_file +module mem_combMem( + input [12:0] R0_addr, + input R0_en, + R0_clk, + input [12:0] W0_addr, + input W0_en, + W0_clk, + input [31:0] W0_data, + input [3:0] W0_mask, + output [31:0] R0_data +); + + (* rw_addr_collision = "yes" *) + reg [31:0] Memory[0:8191]; + + initial begin + $readmemh("vector_matmul_inst.mem", Memory); + end + + reg _GEN; + reg [12:0] _GEN_0; + always @(posedge R0_clk) begin + _GEN <= R0_en; + _GEN_0 <= R0_addr; + end // always @(posedge) + always @(posedge W0_clk) begin + if (W0_en & W0_mask[0]) + Memory[W0_addr][32'h0 +: 8] <= W0_data[7:0]; + if (W0_en & W0_mask[1]) + Memory[W0_addr][32'h8 +: 8] <= W0_data[15:8]; + if (W0_en & W0_mask[2]) + Memory[W0_addr][32'h10 +: 8] <= W0_data[23:16]; + if (W0_en & W0_mask[3]) + Memory[W0_addr][32'h18 +: 8] <= W0_data[31:24]; + end // always @(posedge) + assign R0_data = _GEN ? Memory[_GEN_0] : 32'bx; +endmodule + +module Icache_for_Verilator( + input clock, + reset, + io_ar_valid, + input [63:0] io_ar_bits_addr, + input [2:0] io_ar_bits_prot, + input io_aw_valid, + input [63:0] io_aw_bits_addr, + input [2:0] io_aw_bits_prot, + input io_b_ready, + io_r_ready, + io_w_valid, + input [31:0] io_w_bits_data, + input [3:0] io_w_bits_strb, + output io_ar_ready, + io_aw_ready, + io_b_valid, + output [2:0] io_b_bits_resp, + output io_r_valid, + output [31:0] io_r_bits_data, + output [2:0] io_r_bits_resp, + output io_w_ready +); + + wire _io_r_valid_output; + wire [31:0] _mem_ext_R0_data; + reg [31:0] r_channel_bits_reg_data; + reg [2:0] r_channel_bits_reg_resp; + reg r_channel_valid_reg; + wire r_stall = _io_r_valid_output & ~io_r_ready; + reg retain_r_channel; + reg r_channel_valid_reg_REG; + reg io_r_valid_REG; + assign _io_r_valid_output = retain_r_channel ? r_channel_valid_reg : io_r_valid_REG; + reg b_valid; + wire mem_MPORT_en = io_aw_valid & io_w_valid; + always @(posedge clock) begin + if (r_stall & retain_r_channel) begin + end + else begin + r_channel_bits_reg_data <= _mem_ext_R0_data; + r_channel_bits_reg_resp <= 3'h0; + end + if (r_stall) begin + if (retain_r_channel) begin + end + else + r_channel_valid_reg <= io_r_valid_REG; + end + else + r_channel_valid_reg <= r_channel_valid_reg_REG; + retain_r_channel <= r_stall; + r_channel_valid_reg_REG <= io_ar_valid & ~r_stall; + io_r_valid_REG <= io_ar_valid & ~r_stall; + if (reset) + b_valid <= 1'h0; + else + b_valid <= mem_MPORT_en; + end // always @(posedge) + mem_combMem mem_ext ( + .R0_addr (io_ar_bits_addr[14:2]), + .R0_en (1'h1), + .R0_clk (clock), + .W0_addr (io_aw_bits_addr[14:2]), + .W0_en (mem_MPORT_en), + .W0_clk (clock), + .W0_data (io_w_bits_data), + .W0_mask (io_w_bits_strb), + .R0_data (_mem_ext_R0_data) + ); + assign io_ar_ready = ~r_stall; + assign io_aw_ready = 1'h1; + assign io_b_valid = b_valid; + assign io_b_bits_resp = 3'h0; + assign io_r_valid = _io_r_valid_output; + assign io_r_bits_data = retain_r_channel ? r_channel_bits_reg_data : _mem_ext_R0_data; + assign io_r_bits_resp = retain_r_channel ? r_channel_bits_reg_resp : 3'h0; + assign io_w_ready = 1'h1; +endmodule + diff --git a/fpga/fpga.v b/fpga/fpga.v index e95d52d7..557d20b6 100644 --- a/fpga/fpga.v +++ b/fpga/fpga.v @@ -26,16 +26,64 @@ module fpga( output [6:0] SEG_0, output [7:0] AN_0 ); + wire CLKFBOUT, iPCK; + wire [31:0] check; - wire CLK_top; + wire CLK_top, CLK_25MHz; - design_1_wrapper clk_wiz( - .clk_in1_0(clk_in1_0), - .clk_out1_0(CLK_top) + BUFG iBUFG(.I(CLK_top), .O(CLK_25MHz)); + MMCME2_BASE #( + .CLKFBOUT_MULT_F(25.0), + .CLKFBOUT_PHASE(0.0), + .CLKIN1_PERIOD(10.0), // 100Hz -> 10ns + .CLKOUT0_DIVIDE_F(20.0), + .CLKOUT1_DIVIDE(1), + .CLKOUT2_DIVIDE(1), + .CLKOUT3_DIVIDE(1), + .CLKOUT4_DIVIDE(1), + .CLKOUT5_DIVIDE(1), + .CLKOUT6_DIVIDE(1), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0.0), + .CLKOUT1_PHASE(0.0), + .CLKOUT2_PHASE(0.0), + .CLKOUT3_PHASE(0.0), + .CLKOUT4_PHASE(0.0), + .CLKOUT5_PHASE(0.0), + .CLKOUT6_PHASE(0.0), + .CLKOUT4_CASCADE("FALSE"), + .DIVCLK_DIVIDE(5), + .REF_JITTER1(0.0), + .STARTUP_WAIT("FALSE") + ) MMCME2_BASE_inst ( + .CLKOUT0(CLK_top), + .CLKOUT0B(), // 1-bit output: Inverted CLKOUT0 + .CLKOUT1(), // 1-bit output: CLKOUT1 + .CLKOUT1B(), // 1-bit output: Inverted CLKOUT1 + .CLKOUT2(), // 1-bit output: CLKOUT2 + .CLKOUT2B(), // 1-bit output: Inverted CLKOUT2 + .CLKOUT3(), // 1-bit output: CLKOUT3 + .CLKOUT3B(), // 1-bit output: Inverted CLKOUT3 + .CLKOUT4(), // 1-bit output: CLKOUT4 + .CLKOUT5(), // 1-bit output: CLKOUT5 + .CLKOUT6(), // 1-bit output: CLKOUT6 + .CLKFBOUT(CLKFBOUT), + .CLKFBOUTB(), // 1-bit output: Inverted CLKFBOUT + .LOCKED(), + .CLKIN1(clk_in1_0), + .PWRDWN(1'b0), // 1-bit input: Power-down + .RST(1'b0), // 1-bit input: Reset + .CLKFBIN(CLKFBOUT) ); top top( - .CLK(CLK_top), + .CLK(CLK_25MHz), .RST(RST_0), .tohost(check) ); From 3affdf3b615075bf199bc6396ba30b4c30f64dd8 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Fri, 1 Dec 2023 19:23:36 +0900 Subject: [PATCH 11/13] a --- src/main/scala/hajime/vectormodules/VectorCpu.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/hajime/vectormodules/VectorCpu.scala b/src/main/scala/hajime/vectormodules/VectorCpu.scala index fcfe9476..346b9aa6 100644 --- a/src/main/scala/hajime/vectormodules/VectorCpu.scala +++ b/src/main/scala/hajime/vectormodules/VectorCpu.scala @@ -427,6 +427,7 @@ class VectorCpu(implicit params: HajimeCoreParams) extends CpuModule with Scalar )) Mux(ID_EX_REG.bits.ctrlSignals.decode.branch === Branch.ECALL.asUInt, 0xb.U(params.xprlen.W), 0.U) + // EX_WB_REGに信号自体がvalidかを覚えさせておく when(vecCtrlUnit.io.resp.valid) { EX_WB_REG.bits.vectorCsrPorts.get := vecCtrlUnit.io.resp.bits } From eba6eb286bfe6d4c7e0afc87de056544415192b6 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Mon, 4 Dec 2023 15:18:46 +0900 Subject: [PATCH 12/13] a --- fpga/Core.sv | 222 +++--------------- fpga/fpga.v | 4 +- .../hajime/vectormodules/VectorCpu.scala | 6 + 3 files changed, 36 insertions(+), 196 deletions(-) diff --git a/fpga/Core.sv b/fpga/Core.sv index 5bc431b1..1ef7b1ae 100644 --- a/fpga/Core.sv +++ b/fpga/Core.sv @@ -1846,11 +1846,7 @@ module VectorLdstUnit( input [2:0] io_signalIn_bits_vector_scalarDecode_csr_funct, input io_signalIn_bits_vector_scalarDecode_fence, io_signalIn_bits_vector_scalarDecode_vector, - io_signalIn_bits_vector_vecConf_vtype_vill, - io_signalIn_bits_vector_vecConf_vtype_vma, - io_signalIn_bits_vector_vecConf_vtype_vta, input [2:0] io_signalIn_bits_vector_vecConf_vtype_vsew, - io_signalIn_bits_vector_vecConf_vtype_vlmul, input [5:0] io_signalIn_bits_vector_vecConf_vl, input [63:0] io_signalIn_bits_vector_pc_addr, io_readVrf_resp_vs2Out, @@ -1891,12 +1887,6 @@ module VectorLdstUnit( output [2:0] io_toExWbReg_bits_ctrlSignals_decode_csr_funct, output io_toExWbReg_bits_ctrlSignals_decode_fence, output [4:0] io_toExWbReg_bits_ctrlSignals_rd_index, - output io_toExWbReg_bits_vectorCsrPorts_vtype_vill, - io_toExWbReg_bits_vectorCsrPorts_vtype_vma, - io_toExWbReg_bits_vectorCsrPorts_vtype_vta, - output [2:0] io_toExWbReg_bits_vectorCsrPorts_vtype_vsew, - io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul, - output [5:0] io_toExWbReg_bits_vectorCsrPorts_vl, output io_toExWbReg_bits_vectorExecNum_valid, output [4:0] io_toExWbReg_bits_vectorExecNum_bits ); @@ -1919,11 +1909,7 @@ module VectorLdstUnit( reg [2:0] vectorReqReg_scalarDecode_csr_funct; reg vectorReqReg_scalarDecode_fence; reg vectorReqReg_scalarDecode_vector; - reg vectorReqReg_vecConf_vtype_vill; - reg vectorReqReg_vecConf_vtype_vma; - reg vectorReqReg_vecConf_vtype_vta; reg [2:0] vectorReqReg_vecConf_vtype_vsew; - reg [2:0] vectorReqReg_vecConf_vtype_vlmul; reg [5:0] vectorReqReg_vecConf_vl; reg [63:0] vectorReqReg_pc_addr; reg hasVectorInst; @@ -2070,11 +2056,7 @@ module VectorLdstUnit( io_signalIn_bits_vector_scalarDecode_csr_funct; vectorReqReg_scalarDecode_fence <= io_signalIn_bits_vector_scalarDecode_fence; vectorReqReg_scalarDecode_vector <= io_signalIn_bits_vector_scalarDecode_vector; - vectorReqReg_vecConf_vtype_vill <= io_signalIn_bits_vector_vecConf_vtype_vill; - vectorReqReg_vecConf_vtype_vma <= io_signalIn_bits_vector_vecConf_vtype_vma; - vectorReqReg_vecConf_vtype_vta <= io_signalIn_bits_vector_vecConf_vtype_vta; vectorReqReg_vecConf_vtype_vsew <= io_signalIn_bits_vector_vecConf_vtype_vsew; - vectorReqReg_vecConf_vtype_vlmul <= io_signalIn_bits_vector_vecConf_vtype_vlmul; vectorReqReg_vecConf_vl <= io_signalIn_bits_vector_vecConf_vl; vectorReqReg_pc_addr <= io_signalIn_bits_vector_pc_addr; end @@ -2137,12 +2119,6 @@ module VectorLdstUnit( vectorReqReg_scalarDecode_csr_funct; assign io_toExWbReg_bits_ctrlSignals_decode_fence = vectorReqReg_scalarDecode_fence; assign io_toExWbReg_bits_ctrlSignals_rd_index = scalarReqReg_bits_rdIndex; - assign io_toExWbReg_bits_vectorCsrPorts_vtype_vill = vectorReqReg_vecConf_vtype_vill; - assign io_toExWbReg_bits_vectorCsrPorts_vtype_vma = vectorReqReg_vecConf_vtype_vma; - assign io_toExWbReg_bits_vectorCsrPorts_vtype_vta = vectorReqReg_vecConf_vtype_vta; - assign io_toExWbReg_bits_vectorCsrPorts_vtype_vsew = vectorReqReg_vecConf_vtype_vsew; - assign io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul = vectorReqReg_vecConf_vtype_vlmul; - assign io_toExWbReg_bits_vectorCsrPorts_vl = vectorReqReg_vecConf_vl; assign io_toExWbReg_bits_vectorExecNum_valid = _io_toExWbReg_valid_output & vectorReqReg_scalarDecode_vector & (vectorReqReg_scalarDecode_memory_function == 2'h1 @@ -9771,11 +9747,7 @@ module IntegerAluExecUnit( input [1:0] io_signalIn_bits_scalarDecode_memory_function, input [2:0] io_signalIn_bits_scalarDecode_csr_funct, input io_signalIn_bits_scalarDecode_fence, - io_signalIn_bits_vecConf_vtype_vill, - io_signalIn_bits_vecConf_vtype_vma, - io_signalIn_bits_vecConf_vtype_vta, input [2:0] io_signalIn_bits_vecConf_vtype_vsew, - io_signalIn_bits_vecConf_vtype_vlmul, input [5:0] io_signalIn_bits_vecConf_vl, input [63:0] io_signalIn_bits_pc_addr, io_readVrf_resp_vs1Out, @@ -9806,12 +9778,6 @@ module IntegerAluExecUnit( output [2:0] io_toExWbReg_bits_ctrlSignals_decode_csr_funct, output io_toExWbReg_bits_ctrlSignals_decode_fence, output [4:0] io_toExWbReg_bits_ctrlSignals_rd_index, - output io_toExWbReg_bits_vectorCsrPorts_vtype_vill, - io_toExWbReg_bits_vectorCsrPorts_vtype_vma, - io_toExWbReg_bits_vectorCsrPorts_vtype_vta, - output [2:0] io_toExWbReg_bits_vectorCsrPorts_vtype_vsew, - io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul, - output [5:0] io_toExWbReg_bits_vectorCsrPorts_vl, output io_toExWbReg_bits_vectorExecNum_valid, output [4:0] io_toExWbReg_bits_vectorExecNum_bits ); @@ -9835,16 +9801,22 @@ module IntegerAluExecUnit( reg [1:0] instInfoReg_bits_scalarDecode_memory_function; reg [2:0] instInfoReg_bits_scalarDecode_csr_funct; reg instInfoReg_bits_scalarDecode_fence; - reg instInfoReg_bits_vecConf_vtype_vill; - reg instInfoReg_bits_vecConf_vtype_vma; - reg instInfoReg_bits_vecConf_vtype_vta; reg [2:0] instInfoReg_bits_vecConf_vtype_vsew; - reg [2:0] instInfoReg_bits_vecConf_vtype_vlmul; reg [5:0] instInfoReg_bits_vecConf_vl; reg [63:0] instInfoReg_bits_pc_addr; reg [4:0] idx; reg [63:0] reductionAccumulator; reg [4:0] executedNum; + `ifndef SYNTHESIS + always @(posedge clock) begin + if (~reset & instInfoReg_valid & instInfoReg_bits_vecConf_vl == 6'h0) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Zero vl instruction in VectorExecUnit\n at VectorExecUnit.scala:74 assert(!(instInfoReg.valid && instInfoReg.bits.vecConf.vl === 0.U), \"Zero vl instruction in VectorExecUnit\")\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS wire [4:0] _GEN = {3'h0, idx[4:3]}; wire [63:0] execValue1 = instInfoReg_bits_vectorDecode_vSource == 3'h0 @@ -10106,15 +10078,15 @@ module IntegerAluExecUnit( | instInfoReg_bits_vectorDecode_veuFun == 6'h1E | instInfoReg_bits_vectorDecode_veuFun == 6'h1F | instInfoReg_bits_vectorDecode_veuFun == 6'h20; - wire _T_27 = instInfoReg_bits_vectorDecode_veuFun == 6'h31; - wire _T_29 = instInfoReg_bits_vectorDecode_veuFun == 6'h32; - wire _GEN_12 = instInfoReg_valid & (_T_27 | _T_29); + wire _T_33 = instInfoReg_bits_vectorDecode_veuFun == 6'h31; + wire _T_35 = instInfoReg_bits_vectorDecode_veuFun == 6'h32; + wire _GEN_12 = instInfoReg_valid & (_T_33 | _T_35); assign _io_dataOut_toVRF_valid_output = _GEN_12 | instInfoReg_valid; assign _io_dataOut_toVRF_bits_last_output = _GEN_12 | {1'h0, idx} == instInfoReg_bits_vecConf_vl - 6'h1 & instInfoReg_valid; assign _io_dataOut_toVRF_bits_writeReq_output = instInfoReg_valid - ? ~_T_27 & (_T_29 | _io_dataOut_toVRF_bits_writeReq_T_63) + ? ~_T_33 & (_T_35 | _io_dataOut_toVRF_bits_writeReq_T_63) : _io_dataOut_toVRF_bits_writeReq_T_63; wire _GEN_13 = _GEN_12 | _io_dataOut_toVRF_bits_last_output; always @(posedge clock) begin @@ -10156,11 +10128,7 @@ module IntegerAluExecUnit( io_signalIn_bits_scalarDecode_memory_function; instInfoReg_bits_scalarDecode_csr_funct <= io_signalIn_bits_scalarDecode_csr_funct; instInfoReg_bits_scalarDecode_fence <= io_signalIn_bits_scalarDecode_fence; - instInfoReg_bits_vecConf_vtype_vill <= io_signalIn_bits_vecConf_vtype_vill; - instInfoReg_bits_vecConf_vtype_vma <= io_signalIn_bits_vecConf_vtype_vma; - instInfoReg_bits_vecConf_vtype_vta <= io_signalIn_bits_vecConf_vtype_vta; instInfoReg_bits_vecConf_vtype_vsew <= io_signalIn_bits_vecConf_vtype_vsew; - instInfoReg_bits_vecConf_vtype_vlmul <= io_signalIn_bits_vecConf_vtype_vlmul; instInfoReg_bits_vecConf_vl <= io_signalIn_bits_vecConf_vl; instInfoReg_bits_pc_addr <= io_signalIn_bits_pc_addr; end @@ -10249,7 +10217,7 @@ module IntegerAluExecUnit( : idx; assign io_dataOut_toVRF_bits_last = _io_dataOut_toVRF_bits_last_output; assign io_dataOut_toVRF_bits_data = - ~instInfoReg_valid | _T_27 | ~_T_29 + ~instInfoReg_valid | _T_33 | ~_T_35 ? (instInfoReg_bits_vectorDecode_veuFun == 6'h8 | instInfoReg_bits_vectorDecode_veuFun == 6'h9 | instInfoReg_bits_vectorDecode_veuFun == 6'hA @@ -10304,16 +10272,7 @@ module IntegerAluExecUnit( instInfoReg_bits_scalarDecode_csr_funct; assign io_toExWbReg_bits_ctrlSignals_decode_fence = instInfoReg_bits_scalarDecode_fence; assign io_toExWbReg_bits_ctrlSignals_rd_index = - instInfoReg_valid & _T_27 ? instInfoReg_bits_vd : 5'h0; - assign io_toExWbReg_bits_vectorCsrPorts_vtype_vill = - instInfoReg_bits_vecConf_vtype_vill; - assign io_toExWbReg_bits_vectorCsrPorts_vtype_vma = instInfoReg_bits_vecConf_vtype_vma; - assign io_toExWbReg_bits_vectorCsrPorts_vtype_vta = instInfoReg_bits_vecConf_vtype_vta; - assign io_toExWbReg_bits_vectorCsrPorts_vtype_vsew = - instInfoReg_bits_vecConf_vtype_vsew; - assign io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul = - instInfoReg_bits_vecConf_vtype_vlmul; - assign io_toExWbReg_bits_vectorCsrPorts_vl = instInfoReg_bits_vecConf_vl; + instInfoReg_valid & _T_33 ? instInfoReg_bits_vd : 5'h0; assign io_toExWbReg_bits_vectorExecNum_valid = _GEN_13; assign io_toExWbReg_bits_vectorExecNum_bits = _GEN_12 @@ -10388,12 +10347,6 @@ module VectorCpu( wire [2:0] _vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_csr_funct; wire _vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_fence; wire [4:0] _vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_rd_index; - wire _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vill; - wire _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vma; - wire _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vta; - wire [2:0] _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vsew; - wire [2:0] _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul; - wire [5:0] _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vl; wire _vecAluExecUnit_1_io_toExWbReg_bits_vectorExecNum_valid; wire [4:0] _vecAluExecUnit_1_io_toExWbReg_bits_vectorExecNum_bits; wire _vecAluExecUnit_0_io_signalIn_ready; @@ -10421,12 +10374,6 @@ module VectorCpu( wire [2:0] _vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_csr_funct; wire _vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_fence; wire [4:0] _vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_rd_index; - wire _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vill; - wire _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vma; - wire _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vta; - wire [2:0] _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vsew; - wire [2:0] _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul; - wire [5:0] _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vl; wire _vecAluExecUnit_0_io_toExWbReg_bits_vectorExecNum_valid; wire [4:0] _vecAluExecUnit_0_io_toExWbReg_bits_vectorExecNum_bits; wire _vrfReadyTable_io_vs1Check_ready; @@ -10484,12 +10431,6 @@ module VectorCpu( wire [2:0] _vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_csr_funct; wire _vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_fence; wire [4:0] _vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_rd_index; - wire _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vill; - wire _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vma; - wire _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vta; - wire [2:0] _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vsew; - wire [2:0] _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul; - wire [5:0] _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vl; wire _vectorLdstUnit_io_toExWbReg_bits_vectorExecNum_valid; wire [4:0] _vectorLdstUnit_io_toExWbReg_bits_vectorExecNum_bits; wire _bypassingUnit_io_ID_out_rs1_value_valid; @@ -10607,26 +10548,10 @@ module VectorCpu( ? ~_bypassingUnit_io_EX_in_bits_rd_valid_T_31 : _bypassingUnit_io_ID_out_rs2_bypassMatchAtWB & ~_bypassingUnit_io_WB_in_bits_rd_valid_T_4; - wire vecConfBypass_vtype_vill = - _vecCtrlUnit_io_resp_valid - ? _vecCtrlUnit_io_resp_bits_vtype_vill - : EX_WB_REG_bits_vectorCsrPorts_vtype_vill; - wire vecConfBypass_vtype_vma = - _vecCtrlUnit_io_resp_valid - ? _vecCtrlUnit_io_resp_bits_vtype_vma - : EX_WB_REG_bits_vectorCsrPorts_vtype_vma; - wire vecConfBypass_vtype_vta = - _vecCtrlUnit_io_resp_valid - ? _vecCtrlUnit_io_resp_bits_vtype_vta - : EX_WB_REG_bits_vectorCsrPorts_vtype_vta; wire [2:0] vecConfBypass_vtype_vsew = _vecCtrlUnit_io_resp_valid ? _vecCtrlUnit_io_resp_bits_vtype_vsew : EX_WB_REG_bits_vectorCsrPorts_vtype_vsew; - wire [2:0] vecConfBypass_vtype_vlmul = - _vecCtrlUnit_io_resp_valid - ? _vecCtrlUnit_io_resp_bits_vtype_vlmul - : EX_WB_REG_bits_vectorCsrPorts_vtype_vlmul; wire [5:0] vecConfBypass_vl = _vecCtrlUnit_io_resp_valid ? _vecCtrlUnit_io_resp_bits_vl @@ -10853,18 +10778,6 @@ module VectorCpu( _vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_fence; EX_WB_REG_bits_ctrlSignals_rd_index <= _vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_rd_index; - EX_WB_REG_bits_vectorCsrPorts_vtype_vill <= - _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vill; - EX_WB_REG_bits_vectorCsrPorts_vtype_vma <= - _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vma; - EX_WB_REG_bits_vectorCsrPorts_vtype_vta <= - _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vta; - EX_WB_REG_bits_vectorCsrPorts_vtype_vsew <= - _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vsew; - EX_WB_REG_bits_vectorCsrPorts_vtype_vlmul <= - _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul; - EX_WB_REG_bits_vectorCsrPorts_vl <= - _vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vl; EX_WB_REG_bits_vectorExecNum_valid <= _vectorLdstUnit_io_toExWbReg_bits_vectorExecNum_valid; EX_WB_REG_bits_vectorExecNum_bits <= @@ -10887,18 +10800,6 @@ module VectorCpu( _vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_fence; EX_WB_REG_bits_ctrlSignals_rd_index <= _vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_rd_index; - EX_WB_REG_bits_vectorCsrPorts_vtype_vill <= - _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vill; - EX_WB_REG_bits_vectorCsrPorts_vtype_vma <= - _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vma; - EX_WB_REG_bits_vectorCsrPorts_vtype_vta <= - _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vta; - EX_WB_REG_bits_vectorCsrPorts_vtype_vsew <= - _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vsew; - EX_WB_REG_bits_vectorCsrPorts_vtype_vlmul <= - _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul; - EX_WB_REG_bits_vectorCsrPorts_vl <= - _vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vl; EX_WB_REG_bits_vectorExecNum_valid <= _vecAluExecUnit_1_io_toExWbReg_bits_vectorExecNum_valid; EX_WB_REG_bits_vectorExecNum_bits <= @@ -10922,18 +10823,6 @@ module VectorCpu( _vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_fence; EX_WB_REG_bits_ctrlSignals_rd_index <= _vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_rd_index; - EX_WB_REG_bits_vectorCsrPorts_vtype_vill <= - _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vill; - EX_WB_REG_bits_vectorCsrPorts_vtype_vma <= - _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vma; - EX_WB_REG_bits_vectorCsrPorts_vtype_vta <= - _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vta; - EX_WB_REG_bits_vectorCsrPorts_vtype_vsew <= - _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vsew; - EX_WB_REG_bits_vectorCsrPorts_vtype_vlmul <= - _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul; - EX_WB_REG_bits_vectorCsrPorts_vl <= - _vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vl; EX_WB_REG_bits_vectorExecNum_bits <= _vecAluExecUnit_0_io_toExWbReg_bits_vectorExecNum_bits; end @@ -10965,17 +10854,6 @@ module VectorCpu( EX_WB_REG_bits_ctrlSignals_decode_fence <= ID_EX_REG_bits_ctrlSignals_decode_fence; EX_WB_REG_bits_ctrlSignals_rd_index <= ID_EX_REG_bits_ctrlSignals_rd_index; - if (_vecCtrlUnit_io_resp_valid) begin - EX_WB_REG_bits_vectorCsrPorts_vtype_vill <= - _vecCtrlUnit_io_resp_bits_vtype_vill; - EX_WB_REG_bits_vectorCsrPorts_vtype_vma <= _vecCtrlUnit_io_resp_bits_vtype_vma; - EX_WB_REG_bits_vectorCsrPorts_vtype_vta <= _vecCtrlUnit_io_resp_bits_vtype_vta; - EX_WB_REG_bits_vectorCsrPorts_vtype_vsew <= - _vecCtrlUnit_io_resp_bits_vtype_vsew; - EX_WB_REG_bits_vectorCsrPorts_vtype_vlmul <= - _vecCtrlUnit_io_resp_bits_vtype_vlmul; - EX_WB_REG_bits_vectorCsrPorts_vl <= _vecCtrlUnit_io_resp_bits_vl; - end EX_WB_REG_bits_vectorExecNum_bits <= 5'h0; end EX_WB_REG_bits_vectorExecNum_valid <= @@ -11001,6 +10879,16 @@ module VectorCpu( EX_WB_REG_bits_exceptionSignals_bits <= 64'h0; else EX_WB_REG_bits_exceptionSignals_bits <= ID_EX_REG_bits_exceptionSignals_bits; + if (_GEN_2 | ~_vecCtrlUnit_io_resp_valid) begin + end + else begin + EX_WB_REG_bits_vectorCsrPorts_vtype_vill <= _vecCtrlUnit_io_resp_bits_vtype_vill; + EX_WB_REG_bits_vectorCsrPorts_vtype_vma <= _vecCtrlUnit_io_resp_bits_vtype_vma; + EX_WB_REG_bits_vectorCsrPorts_vtype_vta <= _vecCtrlUnit_io_resp_bits_vtype_vta; + EX_WB_REG_bits_vectorCsrPorts_vtype_vsew <= _vecCtrlUnit_io_resp_bits_vtype_vsew; + EX_WB_REG_bits_vectorCsrPorts_vtype_vlmul <= _vecCtrlUnit_io_resp_bits_vtype_vlmul; + EX_WB_REG_bits_vectorCsrPorts_vl <= _vecCtrlUnit_io_resp_bits_vl; + end end // always @(posedge) Decoder decoder ( .io_inst_bits (io_frontend_resp_bits_inst_bits), @@ -11172,18 +11060,8 @@ module VectorCpu( .io_signalIn_bits_vector_scalarDecode_fence (_decoder_io_out_bits_fence), .io_signalIn_bits_vector_scalarDecode_vector (_decoder_io_out_bits_vector), - .io_signalIn_bits_vector_vecConf_vtype_vill - (_T_25 & vecConfBypass_vtype_vill), - .io_signalIn_bits_vector_vecConf_vtype_vma - (_T_25 & vecConfBypass_vtype_vma), - .io_signalIn_bits_vector_vecConf_vtype_vta - (_T_25 & vecConfBypass_vtype_vta), - .io_signalIn_bits_vector_vecConf_vtype_vsew - (_T_25 ? vecConfBypass_vtype_vsew : 3'h0), - .io_signalIn_bits_vector_vecConf_vtype_vlmul - (_T_25 ? vecConfBypass_vtype_vlmul : 3'h0), - .io_signalIn_bits_vector_vecConf_vl - (_T_25 ? vecConfBypass_vl : 6'h0), + .io_signalIn_bits_vector_vecConf_vtype_vsew (vecConfBypass_vtype_vsew), + .io_signalIn_bits_vector_vecConf_vl (vecConfBypass_vl), .io_signalIn_bits_vector_pc_addr (io_frontend_resp_bits_pc_addr), .io_readVrf_resp_vs2Out @@ -11258,18 +11136,6 @@ module VectorCpu( (_vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_decode_fence), .io_toExWbReg_bits_ctrlSignals_rd_index (_vectorLdstUnit_io_toExWbReg_bits_ctrlSignals_rd_index), - .io_toExWbReg_bits_vectorCsrPorts_vtype_vill - (_vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vill), - .io_toExWbReg_bits_vectorCsrPorts_vtype_vma - (_vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vma), - .io_toExWbReg_bits_vectorCsrPorts_vtype_vta - (_vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vta), - .io_toExWbReg_bits_vectorCsrPorts_vtype_vsew - (_vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vsew), - .io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul - (_vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul), - .io_toExWbReg_bits_vectorCsrPorts_vl - (_vectorLdstUnit_io_toExWbReg_bits_vectorCsrPorts_vl), .io_toExWbReg_bits_vectorExecNum_valid (_vectorLdstUnit_io_toExWbReg_bits_vectorExecNum_valid), .io_toExWbReg_bits_vectorExecNum_bits @@ -11501,11 +11367,7 @@ module VectorCpu( .io_signalIn_bits_scalarDecode_csr_funct (_decoder_io_out_bits_csr_funct), .io_signalIn_bits_scalarDecode_fence (_decoder_io_out_bits_fence), - .io_signalIn_bits_vecConf_vtype_vill (vecConfBypass_vtype_vill), - .io_signalIn_bits_vecConf_vtype_vma (vecConfBypass_vtype_vma), - .io_signalIn_bits_vecConf_vtype_vta (vecConfBypass_vtype_vta), .io_signalIn_bits_vecConf_vtype_vsew (vecConfBypass_vtype_vsew), - .io_signalIn_bits_vecConf_vtype_vlmul (vecConfBypass_vtype_vlmul), .io_signalIn_bits_vecConf_vl (vecConfBypass_vl), .io_signalIn_bits_pc_addr (io_frontend_resp_bits_pc_addr), @@ -11565,18 +11427,6 @@ module VectorCpu( (_vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_decode_fence), .io_toExWbReg_bits_ctrlSignals_rd_index (_vecAluExecUnit_0_io_toExWbReg_bits_ctrlSignals_rd_index), - .io_toExWbReg_bits_vectorCsrPorts_vtype_vill - (_vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vill), - .io_toExWbReg_bits_vectorCsrPorts_vtype_vma - (_vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vma), - .io_toExWbReg_bits_vectorCsrPorts_vtype_vta - (_vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vta), - .io_toExWbReg_bits_vectorCsrPorts_vtype_vsew - (_vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vsew), - .io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul - (_vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul), - .io_toExWbReg_bits_vectorCsrPorts_vl - (_vecAluExecUnit_0_io_toExWbReg_bits_vectorCsrPorts_vl), .io_toExWbReg_bits_vectorExecNum_valid (_vecAluExecUnit_0_io_toExWbReg_bits_vectorExecNum_valid), .io_toExWbReg_bits_vectorExecNum_bits @@ -11611,11 +11461,7 @@ module VectorCpu( .io_signalIn_bits_scalarDecode_csr_funct (_decoder_io_out_bits_csr_funct), .io_signalIn_bits_scalarDecode_fence (_decoder_io_out_bits_fence), - .io_signalIn_bits_vecConf_vtype_vill (vecConfBypass_vtype_vill), - .io_signalIn_bits_vecConf_vtype_vma (vecConfBypass_vtype_vma), - .io_signalIn_bits_vecConf_vtype_vta (vecConfBypass_vtype_vta), .io_signalIn_bits_vecConf_vtype_vsew (vecConfBypass_vtype_vsew), - .io_signalIn_bits_vecConf_vtype_vlmul (vecConfBypass_vtype_vlmul), .io_signalIn_bits_vecConf_vl (vecConfBypass_vl), .io_signalIn_bits_pc_addr (io_frontend_resp_bits_pc_addr), @@ -11675,18 +11521,6 @@ module VectorCpu( (_vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_decode_fence), .io_toExWbReg_bits_ctrlSignals_rd_index (_vecAluExecUnit_1_io_toExWbReg_bits_ctrlSignals_rd_index), - .io_toExWbReg_bits_vectorCsrPorts_vtype_vill - (_vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vill), - .io_toExWbReg_bits_vectorCsrPorts_vtype_vma - (_vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vma), - .io_toExWbReg_bits_vectorCsrPorts_vtype_vta - (_vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vta), - .io_toExWbReg_bits_vectorCsrPorts_vtype_vsew - (_vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vsew), - .io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul - (_vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vtype_vlmul), - .io_toExWbReg_bits_vectorCsrPorts_vl - (_vecAluExecUnit_1_io_toExWbReg_bits_vectorCsrPorts_vl), .io_toExWbReg_bits_vectorExecNum_valid (_vecAluExecUnit_1_io_toExWbReg_bits_vectorExecNum_valid), .io_toExWbReg_bits_vectorExecNum_bits diff --git a/fpga/fpga.v b/fpga/fpga.v index 557d20b6..158c858c 100644 --- a/fpga/fpga.v +++ b/fpga/fpga.v @@ -33,10 +33,10 @@ module fpga( BUFG iBUFG(.I(CLK_top), .O(CLK_25MHz)); MMCME2_BASE #( - .CLKFBOUT_MULT_F(25.0), + .CLKFBOUT_MULT_F(50.0), .CLKFBOUT_PHASE(0.0), .CLKIN1_PERIOD(10.0), // 100Hz -> 10ns - .CLKOUT0_DIVIDE_F(20.0), + .CLKOUT0_DIVIDE_F(40.0), .CLKOUT1_DIVIDE(1), .CLKOUT2_DIVIDE(1), .CLKOUT3_DIVIDE(1), diff --git a/src/main/scala/hajime/vectormodules/VectorCpu.scala b/src/main/scala/hajime/vectormodules/VectorCpu.scala index 346b9aa6..33b802fb 100644 --- a/src/main/scala/hajime/vectormodules/VectorCpu.scala +++ b/src/main/scala/hajime/vectormodules/VectorCpu.scala @@ -291,6 +291,7 @@ class VectorCpu(implicit params: HajimeCoreParams) extends CpuModule with Scalar vectorLdstUnit.io.signalIn.bits.vector.scalarVal := rs1ValueToEX vectorLdstUnit.io.signalIn.bits.vector.scalarDecode := decoder.io.out.bits vectorLdstUnit.io.signalIn.bits.vector.pc := io.frontend.resp.bits.pc + vectorLdstUnit.io.signalIn.bits.vector.vecConf := vecConfBypass } .otherwise { vectorLdstUnit.io.signalIn := DontCare vectorLdstUnit.io.signalIn.valid := false.B @@ -430,6 +431,8 @@ class VectorCpu(implicit params: HajimeCoreParams) extends CpuModule with Scalar // EX_WB_REGに信号自体がvalidかを覚えさせておく when(vecCtrlUnit.io.resp.valid) { EX_WB_REG.bits.vectorCsrPorts.get := vecCtrlUnit.io.resp.bits + } .otherwise { + EX_WB_REG.bits.vectorCsrPorts.get := EX_WB_REG.bits.vectorCsrPorts.get } if (params.debug) EX_WB_REG.bits.debug.get := ID_EX_REG.bits.debug.get @@ -449,14 +452,17 @@ class VectorCpu(implicit params: HajimeCoreParams) extends CpuModule with Scalar for(d <- vecAluExecUnit) { when(d.io.toExWbReg.valid) { EX_WB_REG := d.io.toExWbReg + EX_WB_REG.bits.vectorCsrPorts.get := EX_WB_REG.bits.vectorCsrPorts.get } } when(vectorLdstUnit.io.toExWbReg.valid) { EX_WB_REG := vectorLdstUnit.io.toExWbReg + EX_WB_REG.bits.vectorCsrPorts.get := EX_WB_REG.bits.vectorCsrPorts.get } when(WB_stall) { EX_WB_REG := EX_WB_REG + EX_WB_REG.bits.vectorCsrPorts.get := EX_WB_REG.bits.vectorCsrPorts.get } // flush the EX_WB register if ecall, mret or exception From 551e64826d18a98ebea02d2f5fcb142f691f45a7 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Fri, 8 Dec 2023 19:58:05 +0900 Subject: [PATCH 13/13] removed unnecessary wire --- fpga/fpga.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/fpga.v b/fpga/fpga.v index 158c858c..7d81d024 100644 --- a/fpga/fpga.v +++ b/fpga/fpga.v @@ -26,7 +26,7 @@ module fpga( output [6:0] SEG_0, output [7:0] AN_0 ); - wire CLKFBOUT, iPCK; + wire CLKFBOUT; wire [31:0] check; wire CLK_top, CLK_25MHz;