From d5bed200048a48ad94af87b517e752c72e2c2334 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Fri, 10 Nov 2023 16:27:39 +0900 Subject: [PATCH 01/14] a --- src/main/scala/hajime/common/Instructions.scala | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/main/scala/hajime/common/Instructions.scala b/src/main/scala/hajime/common/Instructions.scala index c4a23b3d..45a0dbdb 100644 --- a/src/main/scala/hajime/common/Instructions.scala +++ b/src/main/scala/hajime/common/Instructions.scala @@ -189,10 +189,10 @@ object VectorInstructions extends ScalarOpConstants with VectorOpConstants { case "vmulh" => "100111" case "vmulhu" => "100100" case "vmulhsu" => "100110" - case "vmacc" => ??? - case "vnmsac" => ??? - case "vmadd" => ??? - case "vnmsub" => ??? + case "vmacc" => "101101" + case "vnmsac" => "101111" + case "vmadd" => "101001" + case "vnmsub" => "101011" case "vmerge" => "010111" case "vmv" => "010111" case "vredsum" => ??? @@ -294,6 +294,11 @@ object VectorInstructions extends ScalarOpConstants with VectorOpConstants { def VMULHSU_VV = vArithGen(vInst = "vmulhsu", vsource = VSOURCE.MVV) def VMULHSU_VX = vArithGen(vInst = "vmulhsu", vsource = VSOURCE.MVX) + def VMACC_VV = vArithGen(vInst = "vmacc", vsource = VSOURCE.MVV) + def VMACC_VX = vArithGen(vInst = "vmacc", vsource = VSOURCE.MVX) + def VNMSAC_VV = vArithGen(vInst = "vnmsac", vsource = VSOURCE.MVV) + def VNMSAC_VX = vArithGen(vInst = "vnmsac", vsource = VSOURCE.MVX) + def VMERGE_VVM = vArithGen(vInst = "vmerge", vsource = VSOURCE.VV, vm = "0") def VMERGE_VXM = vArithGen(vInst = "vmerge", vsource = VSOURCE.VX, vm = "0") def VMERGE_VIM = vArithGen(vInst = "vmerge", vsource = VSOURCE.VI, vm = "0") From c7eb1f75a353d253b62e8b1aecb90f57c87f6248 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Sat, 11 Nov 2023 16:35:14 +0900 Subject: [PATCH 02/14] add multiply-and-add vector insts --- .../scala/hajime/common/Instructions.scala | 4 +++ .../scala/hajime/publicmodules/Decoder.scala | 8 +++++ .../hajime/vectormodules/VectorDecoder.scala | 14 ++++++++- .../hajime/vectormodules/VectorExecUnit.scala | 29 +++++++++++++++---- .../vectormodules/VectorOpConstants.scala | 2 +- 5 files changed, 50 insertions(+), 7 deletions(-) diff --git a/src/main/scala/hajime/common/Instructions.scala b/src/main/scala/hajime/common/Instructions.scala index 45a0dbdb..52ececb2 100644 --- a/src/main/scala/hajime/common/Instructions.scala +++ b/src/main/scala/hajime/common/Instructions.scala @@ -298,6 +298,10 @@ object VectorInstructions extends ScalarOpConstants with VectorOpConstants { def VMACC_VX = vArithGen(vInst = "vmacc", vsource = VSOURCE.MVX) def VNMSAC_VV = vArithGen(vInst = "vnmsac", vsource = VSOURCE.MVV) def VNMSAC_VX = vArithGen(vInst = "vnmsac", vsource = VSOURCE.MVX) + def VMADD_VV = vArithGen(vInst = "vmadd", vsource = VSOURCE.MVV) + def VMADD_VX = vArithGen(vInst = "vmadd", vsource = VSOURCE.MVX) + def VNMSUB_VV = vArithGen(vInst = "vnmsub", vsource = VSOURCE.MVV) + def VNMSUB_VX = vArithGen(vInst = "vnmsub", vsource = VSOURCE.MVX) def VMERGE_VVM = vArithGen(vInst = "vmerge", vsource = VSOURCE.VV, vm = "0") def VMERGE_VXM = vArithGen(vInst = "vmerge", vsource = VSOURCE.VX, vm = "0") diff --git a/src/main/scala/hajime/publicmodules/Decoder.scala b/src/main/scala/hajime/publicmodules/Decoder.scala index 40581a27..5bc0337a 100644 --- a/src/main/scala/hajime/publicmodules/Decoder.scala +++ b/src/main/scala/hajime/publicmodules/Decoder.scala @@ -263,6 +263,14 @@ object RvvDecode extends DecodeConstants { VMULHU_VX -> List(Y, Branch.NONE, Value1.RS1, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), VMULHSU_VV -> List(Y, Branch.NONE, Value1.ZERO, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), VMULHSU_VX -> List(Y, Branch.NONE, Value1.RS1, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), + VMACC_VV -> List(Y, Branch.NONE, Value1.ZERO, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), + VMACC_VX -> List(Y, Branch.NONE, Value1.RS1, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), + VNMSAC_VV -> List(Y, Branch.NONE, Value1.ZERO, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), + VNMSAC_VX -> List(Y, Branch.NONE, Value1.RS1, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), + VMADD_VV -> List(Y, Branch.NONE, Value1.ZERO, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), + VMADD_VX -> List(Y, Branch.NONE, Value1.RS1, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), + VNMSUB_VV -> List(Y, Branch.NONE, Value1.ZERO, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), + VNMSUB_VX -> List(Y, Branch.NONE, Value1.RS1, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), ) } diff --git a/src/main/scala/hajime/vectormodules/VectorDecoder.scala b/src/main/scala/hajime/vectormodules/VectorDecoder.scala index 1f83bb89..272a7905 100644 --- a/src/main/scala/hajime/vectormodules/VectorDecoder.scala +++ b/src/main/scala/hajime/vectormodules/VectorDecoder.scala @@ -47,6 +47,10 @@ object VDecode extends DecodeConstants with VectorOpConstants { case "vmulh" => MULH case "vmulhu" => MULHU case "vmulhsu" => MULHSU + case "vmacc" => MACC + case "vnmsac" => NMSAC + case "vmadd" => MADD + case "vnmsub" => NMSUB case "vmand" => MAND case "vmnand" => MNAND case "vmandn" => MANDN @@ -180,7 +184,15 @@ object VDecode extends DecodeConstants with VectorOpConstants { VMULHU_VV -> amogus("vmulhu", VSOURCE.VV), VMULHU_VX -> amogus("vmulhu", VSOURCE.VX), VMULHSU_VV -> amogus("vmulhsu", VSOURCE.VV), - VMULHSU_VX -> amogus("vmulhsu", VSOURCE.VX) + VMULHSU_VX -> amogus("vmulhsu", VSOURCE.VX), + VMACC_VV -> amogus("vmacc", VSOURCE.VV), + VMACC_VX -> amogus("vmacc", VSOURCE.VX), + VNMSAC_VV -> amogus("vnmsac", VSOURCE.VV), + VNMSAC_VX -> amogus("vnmsac", VSOURCE.VX), + VMADD_VV -> amogus("vmadd", VSOURCE.VV), + VMADD_VX -> amogus("vmadd", VSOURCE.VX), + VNMSUB_VV -> amogus("vnmsub", VSOURCE.VV), + VNMSUB_VX -> amogus("vnmsub", VSOURCE.VX) ) } diff --git a/src/main/scala/hajime/vectormodules/VectorExecUnit.scala b/src/main/scala/hajime/vectormodules/VectorExecUnit.scala index 51dd3995..488c81ce 100644 --- a/src/main/scala/hajime/vectormodules/VectorExecUnit.scala +++ b/src/main/scala/hajime/vectormodules/VectorExecUnit.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.experimental.BundleLiterals._ import circt.stage.ChiselStage import chisel3.util._ -import hajime.common.Functions.{signExtend, lsHasElementEquivalentToUInt} +import hajime.common.Functions.{lsHasElementEquivalentToUInt, signExtend} import hajime.common._ import hajime.publicmodules._ import hajime.simple4Stage._ @@ -141,13 +141,20 @@ class IntegerAluExecUnit(implicit params: HajimeCoreParams) extends VectorExecUn } ) ).asSInt - val multiplyRes = (vs2ForMult * vs1ForMult).asUInt + + val vdForMult = MuxLookup(vsew, vdOut)( + (0 until 4).map( + i => i.U -> vdOut((8 << i) - 1, 0).ext(params.xprlen+1) + ) + ).asSInt + // vs2*vs1, vd*vs1 + val multiplyRes = (Mux(Seq(VEU_FUN.MADD, VEU_FUN.NMSUB).map(_.asUInt).has(vectorDec.veuFun), vdForMult, vs2ForMult) * vs1ForMult).asUInt val multiplyResLowBits = MuxLookup(vsew, multiplyRes(7,0))( (0 until 4).map( i => i.U -> multiplyRes((8 << i) - 1, 0) ) ) - // (15, 7) + // (15, 8) // (31, 16) // (63, 32) // (127, 64) @@ -156,6 +163,17 @@ class IntegerAluExecUnit(implicit params: HajimeCoreParams) extends VectorExecUn i => i.U -> multiplyRes((16 << i) - 1, 8 << i) ) ) + + // multiply-add + val mulAddRes = MuxLookup(vectorDec.veuFun, multiplyResLowBits + vdOut)(Seq( + VEU_FUN.MACC -> (multiplyRes + vdOut), + VEU_FUN.NMSAC -> (-multiplyRes + vdOut), + VEU_FUN.MADD -> (multiplyRes + vs2Out), + VEU_FUN.NMSUB -> (-multiplyRes + vs2Out), + ).map { + case (fcn, res) => (fcn.asUInt -> res) + }) + // vadd, vsub, vrsub, vadc, vmadc, (vsbc, vmsbc), // seq, sne, // sltu, slt, sleu, sle, @@ -175,7 +193,8 @@ class IntegerAluExecUnit(implicit params: HajimeCoreParams) extends VectorExecUn (vs2Out & vs1Out) :: (vs2Out | vs1Out) :: (vs2Out ^ vs1Out) :: (vs2Mask && vs1Mask) :: !(vs2Mask && vs1Mask) :: (vs2Mask && !vs1Mask) :: (vs2Mask ^ vs1Mask) :: (vs2Mask || vs1Mask) :: !(vs2Mask || vs1Mask) :: (vs2Mask || !vs1Mask) :: !(vs2Mask ^ vs1Mask) :: - multiplyResLowBits :: multiplyResHighBits :: multiplyResHighBits :: multiplyResHighBits :: Nil + multiplyResLowBits :: multiplyResHighBits :: multiplyResHighBits :: multiplyResHighBits :: + mulAddRes :: mulAddRes :: mulAddRes :: mulAddRes :: Nil } import VEU_FUN._ @@ -187,7 +206,7 @@ class IntegerAluExecUnit(implicit params: HajimeCoreParams) extends VectorExecUn val rawResult = MuxLookup(instInfoReg.bits.vectorDecode.veuFun, 0.U)( Seq(ADD, SUB, RSUB, ADC, MADC, SBC, MSBC, SEQ, SNE, SLTU, SLT, SLEU, SLE, SGTU, SGT, MINU, MIN, MAXU, MAX, MERGE, MV, AND, OR, XOR, MAND, MNAND, MANDN, MXOR, MOR, MNOR, MORN, MXNOR, - MUL, MULH, MULHU, MULHSU).zipWithIndex.map( + MUL, MULH, MULHU, MULHSU, MACC, NMSAC, MADD, NMSUB).zipWithIndex.map( x => x._1.asUInt -> execResult(x._2) ) ) diff --git a/src/main/scala/hajime/vectormodules/VectorOpConstants.scala b/src/main/scala/hajime/vectormodules/VectorOpConstants.scala index 8aa15c1f..c853d51e 100644 --- a/src/main/scala/hajime/vectormodules/VectorOpConstants.scala +++ b/src/main/scala/hajime/vectormodules/VectorOpConstants.scala @@ -27,7 +27,7 @@ trait VectorOpConstants { object VEU_FUN extends ChiselEnum { val NONE, ADD, SUB, RSUB, ADC, MADC, SBC, MSBC, SEQ, SNE, SLTU, SLT, SLEU, SLE, SGTU, SGT, MINU, MIN, MAXU, MAX, MERGE, MV, AND, OR, XOR, MAND, MNAND, MANDN, MXOR, MOR, MNOR, MORN, MXNOR, - MUL, MULH, MULHU, MULHSU = Value + MUL, MULH, MULHU, MULHSU, MACC, NMSAC, MADD, NMSUB = Value val compMaskList = SEQ :: SNE :: SLTU :: SLT :: SLEU :: SLE :: SGTU :: SGT :: Nil val carryMaskList = MADC :: MSBC :: Nil val ignoreMaskList = ADC :: MADC :: SBC :: MSBC :: MERGE :: Nil From 010245ba4809cc01ff624c3734dbfee249c8a621 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Mon, 13 Nov 2023 12:48:56 +0900 Subject: [PATCH 03/14] vmacc --- .../resources/applications_vector/build.sh | 37 +- .../resources/applications_vector/vmacc.dump | 1052 +++++++++++++++++ .../applications_vector/vmacc/vmacc.c | 61 + .../applications_vector/vmacc_data.hex | 180 +++ .../applications_vector/vmacc_inst.hex | 631 ++++++++++ .../RandomArrayGen.scala | 9 +- .../hajime/vectormodules/VectorCpuSpec.scala | 3 +- 7 files changed, 1950 insertions(+), 23 deletions(-) create mode 100644 src/main/resources/applications_vector/vmacc.dump create mode 100644 src/main/resources/applications_vector/vmacc/vmacc.c create mode 100644 src/main/resources/applications_vector/vmacc_data.hex create mode 100644 src/main/resources/applications_vector/vmacc_inst.hex diff --git a/src/main/resources/applications_vector/build.sh b/src/main/resources/applications_vector/build.sh index 02b316ed..555714fe 100644 --- a/src/main/resources/applications_vector/build.sh +++ b/src/main/resources/applications_vector/build.sh @@ -93,7 +93,6 @@ cat vector_index_text_init.temp vector_index_text.temp vector_index_text_startup riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vadd.riscv ./vadd/vadd.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vadd.riscv > vadd.dump -riscv64-unknown-elf-objdump --disassemble-all vadd.riscv > vadd.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vadd_rodata.bin vadd.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vadd_rodata_str1_8.bin vadd.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vadd_sdata.bin vadd.riscv @@ -111,7 +110,6 @@ cat vadd_text_init.temp vadd_text.temp vadd_text_startup.temp > vadd_inst.hex riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vsub.riscv ./vsub/vsub.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vsub.riscv > vsub.dump -riscv64-unknown-elf-objdump --disassemble-all vsub.riscv > vsub.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vsub_rodata.bin vsub.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vsub_rodata_str1_8.bin vsub.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vsub_sdata.bin vsub.riscv @@ -129,7 +127,6 @@ cat vsub_text_init.temp vsub_text.temp vsub_text_startup.temp > vsub_inst.hex riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vmadc.riscv ./vmadc/vmadc.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vmadc.riscv > vmadc.dump -riscv64-unknown-elf-objdump --disassemble-all vmadc.riscv > vmadc.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vmadc_rodata.bin vmadc.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vmadc_rodata_str1_8.bin vmadc.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vmadc_sdata.bin vmadc.riscv @@ -147,7 +144,6 @@ cat vmadc_text_init.temp vmadc_text.temp vmadc_text_startup.temp > vmadc_inst.he riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vmsbc.riscv ./vmsbc/vmsbc.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vmsbc.riscv > vmsbc.dump -riscv64-unknown-elf-objdump --disassemble-all vmsbc.riscv > vmsbc.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vmsbc_rodata.bin vmsbc.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vmsbc_rodata_str1_8.bin vmsbc.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vmsbc_sdata.bin vmsbc.riscv @@ -165,7 +161,6 @@ cat vmsbc_text_init.temp vmsbc_text.temp vmsbc_text_startup.temp > vmsbc_inst.he riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vand.riscv ./vand/vand.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vand.riscv > vand.dump -riscv64-unknown-elf-objdump --disassemble-all vand.riscv > vand.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vand_rodata.bin vand.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vand_rodata_str1_8.bin vand.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vand_sdata.bin vand.riscv @@ -183,7 +178,6 @@ cat vand_text_init.temp vand_text.temp vand_text_startup.temp > vand_inst.hex riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vmseq.riscv ./vmseq/vmseq.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vmseq.riscv > vmseq.dump -riscv64-unknown-elf-objdump --disassemble-all vmseq.riscv > vmseq.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vmseq_rodata.bin vmseq.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vmseq_rodata_str1_8.bin vmseq.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vmseq_sdata.bin vmseq.riscv @@ -201,7 +195,6 @@ cat vmseq_text_init.temp vmseq_text.temp vmseq_text_startup.temp > vmseq_inst.he riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vmslt.riscv ./vmslt/vmslt.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vmslt.riscv > vmslt.dump -riscv64-unknown-elf-objdump --disassemble-all vmslt.riscv > vmslt.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vmslt_rodata.bin vmslt.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vmslt_rodata_str1_8.bin vmslt.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vmslt_sdata.bin vmslt.riscv @@ -219,7 +212,6 @@ cat vmslt_text_init.temp vmslt_text.temp vmslt_text_startup.temp > vmslt_inst.he riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vmsle.riscv ./vmsle/vmsle.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vmsle.riscv > vmsle.dump -riscv64-unknown-elf-objdump --disassemble-all vmsle.riscv > vmsle.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vmsle_rodata.bin vmsle.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vmsle_rodata_str1_8.bin vmsle.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vmsle_sdata.bin vmsle.riscv @@ -237,7 +229,6 @@ cat vmsle_text_init.temp vmsle_text.temp vmsle_text_startup.temp > vmsle_inst.he riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vmsgt.riscv ./vmsgt/vmsgt.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vmsgt.riscv > vmsgt.dump -riscv64-unknown-elf-objdump --disassemble-all vmsgt.riscv > vmsgt.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vmsgt_rodata.bin vmsgt.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vmsgt_rodata_str1_8.bin vmsgt.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vmsgt_sdata.bin vmsgt.riscv @@ -255,7 +246,6 @@ cat vmsgt_text_init.temp vmsgt_text.temp vmsgt_text_startup.temp > vmsgt_inst.he riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vmand.riscv ./vmand/vmand.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vmand.riscv > vmand.dump -riscv64-unknown-elf-objdump --disassemble-all vmand.riscv > vmand.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vmand_rodata.bin vmand.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vmand_rodata_str1_8.bin vmand.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vmand_sdata.bin vmand.riscv @@ -273,7 +263,6 @@ cat vmand_text_init.temp vmand_text.temp vmand_text_startup.temp > vmand_inst.he riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vmor.riscv ./vmor/vmor.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vmor.riscv > vmor.dump -riscv64-unknown-elf-objdump --disassemble-all vmor.riscv > vmor.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vmor_rodata.bin vmor.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vmor_rodata_str1_8.bin vmor.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vmor_sdata.bin vmor.riscv @@ -291,7 +280,6 @@ cat vmor_text_init.temp vmor_text.temp vmor_text_startup.temp > vmor_inst.hex riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vmxor.riscv ./vmxor/vmxor.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vmxor.riscv > vmxor.dump -riscv64-unknown-elf-objdump --disassemble-all vmxor.riscv > vmxor.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vmxor_rodata.bin vmxor.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vmxor_rodata_str1_8.bin vmxor.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vmxor_sdata.bin vmxor.riscv @@ -309,7 +297,6 @@ cat vmxor_text_init.temp vmxor_text.temp vmxor_text_startup.temp > vmxor_inst.he riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vminmax.riscv ./vminmax/vminmax.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vminmax.riscv > vminmax.dump -riscv64-unknown-elf-objdump --disassemble-all vminmax.riscv > vminmax.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vminmax_rodata.bin vminmax.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vminmax_rodata_str1_8.bin vminmax.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vminmax_sdata.bin vminmax.riscv @@ -327,7 +314,6 @@ cat vminmax_text_init.temp vminmax_text.temp vminmax_text_startup.temp > vminmax riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vmerge.riscv ./vmerge/vmerge.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vmerge.riscv > vmerge.dump -riscv64-unknown-elf-objdump --disassemble-all vmerge.riscv > vmerge.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vmerge_rodata.bin vmerge.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vmerge_rodata_str1_8.bin vmerge.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vmerge_sdata.bin vmerge.riscv @@ -345,7 +331,6 @@ cat vmerge_text_init.temp vmerge_text.temp vmerge_text_startup.temp > vmerge_ins riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vmv.riscv ./vmv/vmv.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vmv.riscv > vmv.dump -riscv64-unknown-elf-objdump --disassemble-all vmv.riscv > vmv.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vmv_rodata.bin vmv.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vmv_rodata_str1_8.bin vmv.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vmv_sdata.bin vmv.riscv @@ -363,7 +348,6 @@ cat vmv_text_init.temp vmv_text.temp vmv_text_startup.temp > vmv_inst.hex riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vector_median.riscv ./vector_median/median.c ./vector_median/vector_median.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vector_median.riscv > vector_median.dump -riscv64-unknown-elf-objdump --disassemble-all vector_median.riscv > vector_median.dump riscv64-unknown-elf-objcopy --dump-section .data=vector_median_data.bin vector_median.riscv riscv64-unknown-elf-objcopy --dump-section .rodata=vector_median_rodata.bin vector_median.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vector_median_rodata_str1_8.bin vector_median.riscv @@ -383,7 +367,6 @@ cat vector_median_text_init.temp vector_median_text.temp vector_median_text_star riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vmul.riscv ./vmul/vmul.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vmul.riscv > vmul.dump -riscv64-unknown-elf-objdump --disassemble-all vmul.riscv > vmul.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vmul_rodata.bin vmul.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vmul_rodata_str1_8.bin vmul.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vmul_sdata.bin vmul.riscv @@ -401,7 +384,6 @@ cat vmul_text_init.temp vmul_text.temp vmul_text_startup.temp > vmul_inst.hex riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vmulh.riscv ./vmulh/vmulh.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vmulh.riscv > vmulh.dump -riscv64-unknown-elf-objdump --disassemble-all vmulh.riscv > vmulh.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vmulh_rodata.bin vmulh.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vmulh_rodata_str1_8.bin vmulh.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vmulh_sdata.bin vmulh.riscv @@ -419,7 +401,6 @@ cat vmulh_text_init.temp vmulh_text.temp vmulh_text_startup.temp > vmulh_inst.he riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vmulhu.riscv ./vmulhu/vmulhu.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vmulhu.riscv > vmulhu.dump -riscv64-unknown-elf-objdump --disassemble-all vmulhu.riscv > vmulhu.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vmulhu_rodata.bin vmulhu.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vmulhu_rodata_str1_8.bin vmulhu.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vmulhu_sdata.bin vmulhu.riscv @@ -437,7 +418,6 @@ cat vmulhu_text_init.temp vmulhu_text.temp vmulhu_text_startup.temp > vmulhu_ins riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vmulhsu.riscv ./vmulhsu/vmulhsu.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld riscv64-unknown-elf-objdump --disassemble-all vmulhsu.riscv > vmulhsu.dump -riscv64-unknown-elf-objdump --disassemble-all vmulhsu.riscv > vmulhsu.dump riscv64-unknown-elf-objcopy --dump-section .rodata=vmulhsu_rodata.bin vmulhsu.riscv riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vmulhsu_rodata_str1_8.bin vmulhsu.riscv riscv64-unknown-elf-objcopy --dump-section .sdata=vmulhsu_sdata.bin vmulhsu.riscv @@ -453,4 +433,21 @@ hexdump -v -e '1/4 "%08x" "\n"' vmulhsu_text_startup.bin > vmulhsu_text_startup. cat vmulhsu_rodata.temp vmulhsu_rodata_str1_8.temp vmulhsu_sdata.temp > vmulhsu_data.hex cat vmulhsu_text_init.temp vmulhsu_text.temp vmulhsu_text_startup.temp > vmulhsu_inst.hex +riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vmacc.riscv ./vmacc/vmacc.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld +riscv64-unknown-elf-objdump --disassemble-all vmacc.riscv > vmacc.dump +riscv64-unknown-elf-objcopy --dump-section .rodata=vmacc_rodata.bin vmacc.riscv +riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vmacc_rodata_str1_8.bin vmacc.riscv +riscv64-unknown-elf-objcopy --dump-section .sdata=vmacc_sdata.bin vmacc.riscv +riscv64-unknown-elf-objcopy --dump-section .text.init=vmacc_text_init.bin vmacc.riscv +riscv64-unknown-elf-objcopy --dump-section .text=vmacc_text.bin vmacc.riscv +riscv64-unknown-elf-objcopy --dump-section .text.startup=vmacc_text_startup.bin vmacc.riscv +hexdump -v -e '1/4 "%08x" "\n"' vmacc_rodata.bin > vmacc_rodata.temp +hexdump -v -e '1/4 "%08x" "\n"' vmacc_rodata_str1_8.bin > vmacc_rodata_str1_8.temp +hexdump -v -e '1/4 "%08x" "\n"' vmacc_sdata.bin > vmacc_sdata.temp +hexdump -v -e '1/4 "%08x" "\n"' vmacc_text_init.bin > vmacc_text_init.temp +hexdump -v -e '1/4 "%08x" "\n"' vmacc_text.bin > vmacc_text.temp +hexdump -v -e '1/4 "%08x" "\n"' vmacc_text_startup.bin > vmacc_text_startup.temp +cat vmacc_rodata.temp vmacc_rodata_str1_8.temp vmacc_sdata.temp > vmacc_data.hex +cat vmacc_text_init.temp vmacc_text.temp vmacc_text_startup.temp > vmacc_inst.hex + rm *.riscv *.bin *.temp \ No newline at end of file diff --git a/src/main/resources/applications_vector/vmacc.dump b/src/main/resources/applications_vector/vmacc.dump new file mode 100644 index 00000000..796753c6 --- /dev/null +++ b/src/main/resources/applications_vector/vmacc.dump @@ -0,0 +1,1052 @@ + +vmacc.riscv: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000000000000 <_start>: + 0: 00000093 li ra,0 + 4: 00000113 li sp,0 + 8: 00000193 li gp,0 + c: 00000213 li tp,0 + 10: 00000293 li t0,0 + 14: 00000313 li t1,0 + 18: 00000393 li t2,0 + 1c: 00000413 li s0,0 + 20: 00000493 li s1,0 + 24: 00000513 li a0,0 + 28: 00000593 li a1,0 + 2c: 00000613 li a2,0 + 30: 00000693 li a3,0 + 34: 00000713 li a4,0 + 38: 00000793 li a5,0 + 3c: 00000813 li a6,0 + 40: 00000893 li a7,0 + 44: 00000913 li s2,0 + 48: 00000993 li s3,0 + 4c: 00000a13 li s4,0 + 50: 00000a93 li s5,0 + 54: 00000b13 li s6,0 + 58: 00000b93 li s7,0 + 5c: 00000c13 li s8,0 + 60: 00000c93 li s9,0 + 64: 00000d13 li s10,0 + 68: 00000d93 li s11,0 + 6c: 00000e13 li t3,0 + 70: 00000e93 li t4,0 + 74: 00000f13 li t5,0 + 78: 00000f93 li t6,0 + 7c: 00000297 auipc t0,0x0 + 80: 03828293 add t0,t0,56 # b4 + 84: 30529073 csrw mtvec,t0 + 88: 00005197 auipc gp,0x5 + 8c: a4018193 add gp,gp,-1472 # 4ac8 <__global_pointer$> + 90: 10000217 auipc tp,0x10000 + 94: ff720213 add tp,tp,-9 # 10000087 <_end+0x3f> + 98: fc027213 and tp,tp,-64 + 9c: f1402573 csrr a0,mhartid + a0: 00100593 li a1,1 + a4: 00b57063 bgeu a0,a1,a4 <_start+0xa4> + a8: 00006137 lui sp,0x6 + ac: ff01011b addw sp,sp,-16 # 5ff0 <__global_pointer$+0x1528> + b0: 6580006f j 708 <_init> + +00000000000000b4 : + b4: ef010113 add sp,sp,-272 + b8: 00113423 sd ra,8(sp) + bc: 00213823 sd sp,16(sp) + c0: 00313c23 sd gp,24(sp) + c4: 02413023 sd tp,32(sp) + c8: 02513423 sd t0,40(sp) + cc: 02613823 sd t1,48(sp) + d0: 02713c23 sd t2,56(sp) + d4: 04813023 sd s0,64(sp) + d8: 04913423 sd s1,72(sp) + dc: 04a13823 sd a0,80(sp) + e0: 04b13c23 sd a1,88(sp) + e4: 06c13023 sd a2,96(sp) + e8: 06d13423 sd a3,104(sp) + ec: 06e13823 sd a4,112(sp) + f0: 06f13c23 sd a5,120(sp) + f4: 09013023 sd a6,128(sp) + f8: 09113423 sd a7,136(sp) + fc: 09213823 sd s2,144(sp) + 100: 09313c23 sd s3,152(sp) + 104: 0b413023 sd s4,160(sp) + 108: 0b513423 sd s5,168(sp) + 10c: 0b613823 sd s6,176(sp) + 110: 0b713c23 sd s7,184(sp) + 114: 0d813023 sd s8,192(sp) + 118: 0d913423 sd s9,200(sp) + 11c: 0da13823 sd s10,208(sp) + 120: 0db13c23 sd s11,216(sp) + 124: 0fc13023 sd t3,224(sp) + 128: 0fd13423 sd t4,232(sp) + 12c: 0fe13823 sd t5,240(sp) + 130: 0ff13c23 sd t6,248(sp) + 134: 34202573 csrr a0,mcause + 138: 341025f3 csrr a1,mepc + 13c: 00010613 mv a2,sp + 140: 2d0000ef jal 410 + 144: 34151073 csrw mepc,a0 + 148: 000022b7 lui t0,0x2 + 14c: 8002829b addw t0,t0,-2048 # 1800 + 150: 3002a073 csrs mstatus,t0 + 154: 00813083 ld ra,8(sp) + 158: 01013103 ld sp,16(sp) + 15c: 01813183 ld gp,24(sp) + 160: 02013203 ld tp,32(sp) + 164: 02813283 ld t0,40(sp) + 168: 03013303 ld t1,48(sp) + 16c: 03813383 ld t2,56(sp) + 170: 04013403 ld s0,64(sp) + 174: 04813483 ld s1,72(sp) + 178: 05013503 ld a0,80(sp) + 17c: 05813583 ld a1,88(sp) + 180: 06013603 ld a2,96(sp) + 184: 06813683 ld a3,104(sp) + 188: 07013703 ld a4,112(sp) + 18c: 07813783 ld a5,120(sp) + 190: 08013803 ld a6,128(sp) + 194: 08813883 ld a7,136(sp) + 198: 09013903 ld s2,144(sp) + 19c: 09813983 ld s3,152(sp) + 1a0: 0a013a03 ld s4,160(sp) + 1a4: 0a813a83 ld s5,168(sp) + 1a8: 0b013b03 ld s6,176(sp) + 1ac: 0b813b83 ld s7,184(sp) + 1b0: 0c013c03 ld s8,192(sp) + 1b4: 0c813c83 ld s9,200(sp) + 1b8: 0d013d03 ld s10,208(sp) + 1bc: 0d813d83 ld s11,216(sp) + 1c0: 0e013e03 ld t3,224(sp) + 1c4: 0e813e83 ld t4,232(sp) + 1c8: 0f013f03 ld t5,240(sp) + 1cc: 0f813f83 ld t6,248(sp) + 1d0: 11010113 add sp,sp,272 + 1d4: 30200073 mret + +Disassembly of section .text: + +00000000000001d8 : + 1d8: b0201073 csrw minstret,zero + 1dc: b0001073 csrw mcycle,zero + 1e0: 00008067 ret + +00000000000001e4 : + 1e4: 03000793 li a5,48 + 1e8: 00f58023 sb a5,0(a1) + 1ec: 07800793 li a5,120 + 1f0: 00f580a3 sb a5,1(a1) + 1f4: 00158813 add a6,a1,1 + 1f8: 00958793 add a5,a1,9 + 1fc: 00900613 li a2,9 + 200: 00f57713 and a4,a0,15 + 204: 03770693 add a3,a4,55 + 208: 00e66463 bltu a2,a4,210 + 20c: 03070693 add a3,a4,48 + 210: 00d78023 sb a3,0(a5) + 214: fff78793 add a5,a5,-1 + 218: 40455513 sra a0,a0,0x4 + 21c: fef812e3 bne a6,a5,200 + 220: 00058523 sb zero,10(a1) + 224: 00008067 ret + +0000000000000228 : + 228: 03000793 li a5,48 + 22c: 00f58023 sb a5,0(a1) + 230: 07800793 li a5,120 + 234: 00f580a3 sb a5,1(a1) + 238: 00158813 add a6,a1,1 + 23c: 01158793 add a5,a1,17 + 240: 00900613 li a2,9 + 244: 00f57713 and a4,a0,15 + 248: 03770693 add a3,a4,55 + 24c: 00e66463 bltu a2,a4,254 + 250: 03070693 add a3,a4,48 + 254: 00d78023 sb a3,0(a5) + 258: fff78793 add a5,a5,-1 + 25c: 40455513 sra a0,a0,0x4 + 260: fef812e3 bne a6,a5,244 + 264: 00058923 sb zero,18(a1) + 268: 00008067 ret + +000000000000026c : + 26c: 00054783 lbu a5,0(a0) + 270: 00078c63 beqz a5,288 + 274: 10000737 lui a4,0x10000 + 278: 00f70023 sb a5,0(a4) # 10000000 + 27c: 00154783 lbu a5,1(a0) + 280: 00150513 add a0,a0,1 + 284: fe079ae3 bnez a5,278 + 288: 00008067 ret + +000000000000028c : + 28c: fe010113 add sp,sp,-32 + 290: c0202673 rdinstret a2 + 294: c00025f3 rdcycle a1 + 298: 00004717 auipc a4,0x4 + 29c: eb870713 add a4,a4,-328 # 4150 + 2a0: 06300793 li a5,99 + 2a4: 100006b7 lui a3,0x10000 + 2a8: 00f68023 sb a5,0(a3) # 10000000 + 2ac: 00174783 lbu a5,1(a4) + 2b0: 00170713 add a4,a4,1 + 2b4: fe079ae3 bnez a5,2a8 + 2b8: ffff8737 lui a4,0xffff8 + 2bc: 83074713 xor a4,a4,-2000 + 2c0: 01910793 add a5,sp,25 + 2c4: 00e11423 sh a4,8(sp) + 2c8: 00910813 add a6,sp,9 + 2cc: 00078713 mv a4,a5 + 2d0: 00900893 li a7,9 + 2d4: 00f5f693 and a3,a1,15 + 2d8: 03768513 add a0,a3,55 + 2dc: 00d8e463 bltu a7,a3,2e4 + 2e0: 03068513 add a0,a3,48 + 2e4: 00a70023 sb a0,0(a4) # ffffffffffff8000 <_end+0xffffffffefff7fb8> + 2e8: fff70713 add a4,a4,-1 + 2ec: 4045d593 sra a1,a1,0x4 + 2f0: fee812e3 bne a6,a4,2d4 + 2f4: 00814703 lbu a4,8(sp) + 2f8: 00010d23 sb zero,26(sp) + 2fc: 00810693 add a3,sp,8 + 300: 100005b7 lui a1,0x10000 + 304: 00070a63 beqz a4,318 + 308: 00e58023 sb a4,0(a1) # 10000000 + 30c: 0016c703 lbu a4,1(a3) + 310: 00168693 add a3,a3,1 + 314: fe071ae3 bnez a4,308 + 318: 00004697 auipc a3,0x4 + 31c: e4068693 add a3,a3,-448 # 4158 + 320: 00a00713 li a4,10 + 324: 100005b7 lui a1,0x10000 + 328: 00e58023 sb a4,0(a1) # 10000000 + 32c: 0016c703 lbu a4,1(a3) + 330: 00168693 add a3,a3,1 + 334: fe071ae3 bnez a4,328 + 338: ffff8737 lui a4,0xffff8 + 33c: 83074713 xor a4,a4,-2000 + 340: 00060693 mv a3,a2 + 344: 00e11423 sh a4,8(sp) + 348: 00900593 li a1,9 + 34c: 00f6f713 and a4,a3,15 + 350: 03770613 add a2,a4,55 # ffffffffffff8037 <_end+0xffffffffefff7fef> + 354: 00e5e463 bltu a1,a4,35c + 358: 03070613 add a2,a4,48 + 35c: 00c78023 sb a2,0(a5) + 360: fff78793 add a5,a5,-1 + 364: 4046d693 sra a3,a3,0x4 + 368: fef812e3 bne a6,a5,34c + 36c: 00814783 lbu a5,8(sp) + 370: 00010d23 sb zero,26(sp) + 374: 00810713 add a4,sp,8 + 378: 100006b7 lui a3,0x10000 + 37c: 00078a63 beqz a5,390 + 380: 00f68023 sb a5,0(a3) # 10000000 + 384: 00174783 lbu a5,1(a4) + 388: 00170713 add a4,a4,1 + 38c: fe079ae3 bnez a5,380 + 390: 100007b7 lui a5,0x10000 + 394: 00a00713 li a4,10 + 398: 00e78023 sb a4,0(a5) # 10000000 + 39c: 02010113 add sp,sp,32 + 3a0: 00008067 ret + +00000000000003a4 : + 3a4: fe010113 add sp,sp,-32 + 3a8: 00813823 sd s0,16(sp) + 3ac: 00113c23 sd ra,24(sp) + 3b0: 00050413 mv s0,a0 + 3b4: 00004717 auipc a4,0x4 + 3b8: db470713 add a4,a4,-588 # 4168 + 3bc: 04500793 li a5,69 + 3c0: 100006b7 lui a3,0x10000 + 3c4: 00f68023 sb a5,0(a3) # 10000000 + 3c8: 00174783 lbu a5,1(a4) + 3cc: 00170713 add a4,a4,1 + 3d0: fe079ae3 bnez a5,3c4 + 3d4: 00010593 mv a1,sp + 3d8: 00040513 mv a0,s0 + 3dc: e09ff0ef jal 1e4 + 3e0: 00014703 lbu a4,0(sp) + 3e4: 00070e63 beqz a4,400 + 3e8: 00010793 mv a5,sp + 3ec: 100006b7 lui a3,0x10000 + 3f0: 00e68023 sb a4,0(a3) # 10000000 + 3f4: 0017c703 lbu a4,1(a5) + 3f8: 00178793 add a5,a5,1 + 3fc: fe071ae3 bnez a4,3f0 + 400: 00040513 mv a0,s0 + 404: 100007b7 lui a5,0x10000 + 408: 00078023 sb zero,0(a5) # 10000000 + 40c: 0000006f j 40c + +0000000000000410 : + 410: ffff87b7 lui a5,0xffff8 + 414: fd010113 add sp,sp,-48 + 418: 8307c793 xor a5,a5,-2000 + 41c: 00f11423 sh a5,8(sp) + 420: 02113423 sd ra,40(sp) + 424: 01910793 add a5,sp,25 + 428: 00910813 add a6,sp,9 + 42c: 00900613 li a2,9 + 430: 00f5f713 and a4,a1,15 + 434: 03770693 add a3,a4,55 + 438: 00e66463 bltu a2,a4,440 + 43c: 03070693 add a3,a4,48 + 440: 00d78023 sb a3,0(a5) # ffffffffffff8000 <_end+0xffffffffefff7fb8> + 444: fff78793 add a5,a5,-1 + 448: 4045d593 sra a1,a1,0x4 + 44c: ff0792e3 bne a5,a6,430 + 450: 00010d23 sb zero,26(sp) + 454: 00b00793 li a5,11 + 458: 02a7e063 bltu a5,a0,478 + 45c: 00004717 auipc a4,0x4 + 460: cc470713 add a4,a4,-828 # 4120 + 464: 00251513 sll a0,a0,0x2 + 468: 00e50533 add a0,a0,a4 + 46c: 00052783 lw a5,0(a0) + 470: 00e787b3 add a5,a5,a4 + 474: 00078067 jr a5 + 478: 00004717 auipc a4,0x4 + 47c: e1870713 add a4,a4,-488 # 4290 + 480: 05500793 li a5,85 + 484: 100006b7 lui a3,0x10000 + 488: 00f68023 sb a5,0(a3) # 10000000 + 48c: 00174783 lbu a5,1(a4) + 490: 00170713 add a4,a4,1 + 494: fe079ae3 bnez a5,488 + 498: 00814783 lbu a5,8(sp) + 49c: 00810713 add a4,sp,8 + 4a0: 100006b7 lui a3,0x10000 + 4a4: 00078a63 beqz a5,4b8 + 4a8: 00f68023 sb a5,0(a3) # 10000000 + 4ac: 00174783 lbu a5,1(a4) + 4b0: 00170713 add a4,a4,1 + 4b4: fe079ae3 bnez a5,4a8 + 4b8: 00004717 auipc a4,0x4 + 4bc: df870713 add a4,a4,-520 # 42b0 + 4c0: 00a00793 li a5,10 + 4c4: 100006b7 lui a3,0x10000 + 4c8: 00f68023 sb a5,0(a3) # 10000000 + 4cc: 00174783 lbu a5,1(a4) + 4d0: 00170713 add a4,a4,1 + 4d4: fe079ae3 bnez a5,4c8 + 4d8: fff00513 li a0,-1 + 4dc: ec9ff0ef jal 3a4 + 4e0: 00004717 auipc a4,0x4 + 4e4: c9870713 add a4,a4,-872 # 4178 + 4e8: 04900793 li a5,73 + 4ec: 100006b7 lui a3,0x10000 + 4f0: 00f68023 sb a5,0(a3) # 10000000 + 4f4: 00174783 lbu a5,1(a4) + 4f8: 00170713 add a4,a4,1 + 4fc: fe079ae3 bnez a5,4f0 + 500: 00814783 lbu a5,8(sp) + 504: 00810713 add a4,sp,8 + 508: 100006b7 lui a3,0x10000 + 50c: fc0786e3 beqz a5,4d8 + 510: 00f68023 sb a5,0(a3) # 10000000 + 514: 00174783 lbu a5,1(a4) + 518: 00170713 add a4,a4,1 + 51c: fe079ae3 bnez a5,510 + 520: fb9ff06f j 4d8 + 524: 00004717 auipc a4,0x4 + 528: c7c70713 add a4,a4,-900 # 41a0 + 52c: 04900793 li a5,73 + 530: 100006b7 lui a3,0x10000 + 534: 00f68023 sb a5,0(a3) # 10000000 + 538: 00174783 lbu a5,1(a4) + 53c: 00170713 add a4,a4,1 + 540: fe079ae3 bnez a5,534 + 544: 00814783 lbu a5,8(sp) + 548: f80788e3 beqz a5,4d8 + 54c: 00810713 add a4,sp,8 + 550: 100006b7 lui a3,0x10000 + 554: 00f68023 sb a5,0(a3) # 10000000 + 558: 00174783 lbu a5,1(a4) + 55c: 00170713 add a4,a4,1 + 560: fe079ae3 bnez a5,554 + 564: f75ff06f j 4d8 + 568: 00004717 auipc a4,0x4 + 56c: c6070713 add a4,a4,-928 # 41c8 + 570: 04900793 li a5,73 + 574: 100006b7 lui a3,0x10000 + 578: 00f68023 sb a5,0(a3) # 10000000 + 57c: 00174783 lbu a5,1(a4) + 580: 00170713 add a4,a4,1 + 584: fe079ae3 bnez a5,578 + 588: 00814783 lbu a5,8(sp) + 58c: f40786e3 beqz a5,4d8 + 590: 00810713 add a4,sp,8 + 594: 100006b7 lui a3,0x10000 + 598: 00f68023 sb a5,0(a3) # 10000000 + 59c: 00174783 lbu a5,1(a4) + 5a0: 00170713 add a4,a4,1 + 5a4: fe079ae3 bnez a5,598 + 5a8: f31ff06f j 4d8 + 5ac: 00004717 auipc a4,0x4 + 5b0: c3c70713 add a4,a4,-964 # 41e8 + 5b4: 04c00793 li a5,76 + 5b8: 100006b7 lui a3,0x10000 + 5bc: 00f68023 sb a5,0(a3) # 10000000 + 5c0: 00174783 lbu a5,1(a4) + 5c4: 00170713 add a4,a4,1 + 5c8: fe079ae3 bnez a5,5bc + 5cc: 00814783 lbu a5,8(sp) + 5d0: f00784e3 beqz a5,4d8 + 5d4: 00810713 add a4,sp,8 + 5d8: 100006b7 lui a3,0x10000 + 5dc: 00f68023 sb a5,0(a3) # 10000000 + 5e0: 00174783 lbu a5,1(a4) + 5e4: 00170713 add a4,a4,1 + 5e8: fe079ae3 bnez a5,5dc + 5ec: eedff06f j 4d8 + 5f0: 00004717 auipc a4,0x4 + 5f4: c1870713 add a4,a4,-1000 # 4208 + 5f8: 04c00793 li a5,76 + 5fc: 100006b7 lui a3,0x10000 + 600: 00f68023 sb a5,0(a3) # 10000000 + 604: 00174783 lbu a5,1(a4) + 608: 00170713 add a4,a4,1 + 60c: fe079ae3 bnez a5,600 + 610: 00814783 lbu a5,8(sp) + 614: ec0782e3 beqz a5,4d8 + 618: 00810713 add a4,sp,8 + 61c: 100006b7 lui a3,0x10000 + 620: 00f68023 sb a5,0(a3) # 10000000 + 624: 00174783 lbu a5,1(a4) + 628: 00170713 add a4,a4,1 + 62c: fe079ae3 bnez a5,620 + 630: ea9ff06f j 4d8 + 634: 00004717 auipc a4,0x4 + 638: bf470713 add a4,a4,-1036 # 4228 + 63c: 05300793 li a5,83 + 640: 100006b7 lui a3,0x10000 + 644: 00f68023 sb a5,0(a3) # 10000000 + 648: 00174783 lbu a5,1(a4) + 64c: 00170713 add a4,a4,1 + 650: fe079ae3 bnez a5,644 + 654: 00814783 lbu a5,8(sp) + 658: e80780e3 beqz a5,4d8 + 65c: 00810713 add a4,sp,8 + 660: 100006b7 lui a3,0x10000 + 664: 00f68023 sb a5,0(a3) # 10000000 + 668: 00174783 lbu a5,1(a4) + 66c: 00170713 add a4,a4,1 + 670: fe079ae3 bnez a5,664 + 674: e65ff06f j 4d8 + 678: 00004717 auipc a4,0x4 + 67c: bd870713 add a4,a4,-1064 # 4250 + 680: 05300793 li a5,83 + 684: 100006b7 lui a3,0x10000 + 688: 00f68023 sb a5,0(a3) # 10000000 + 68c: 00174783 lbu a5,1(a4) + 690: 00170713 add a4,a4,1 + 694: fe079ae3 bnez a5,688 + 698: 00814783 lbu a5,8(sp) + 69c: e2078ee3 beqz a5,4d8 + 6a0: 00810713 add a4,sp,8 + 6a4: 100006b7 lui a3,0x10000 + 6a8: 00f68023 sb a5,0(a3) # 10000000 + 6ac: 00174783 lbu a5,1(a4) + 6b0: 00170713 add a4,a4,1 + 6b4: fe079ae3 bnez a5,6a8 + 6b8: e21ff06f j 4d8 + 6bc: 00004717 auipc a4,0x4 + 6c0: bb470713 add a4,a4,-1100 # 4270 + 6c4: 04500793 li a5,69 + 6c8: 100006b7 lui a3,0x10000 + 6cc: 00f68023 sb a5,0(a3) # 10000000 + 6d0: 00174783 lbu a5,1(a4) + 6d4: 00170713 add a4,a4,1 + 6d8: fe079ae3 bnez a5,6cc + 6dc: 00814783 lbu a5,8(sp) + 6e0: de078ce3 beqz a5,4d8 + 6e4: 00810713 add a4,sp,8 + 6e8: 100006b7 lui a3,0x10000 + 6ec: 00f68023 sb a5,0(a3) # 10000000 + 6f0: 00174783 lbu a5,1(a4) + 6f4: 00170713 add a4,a4,1 + 6f8: fe079ae3 bnez a5,6ec + 6fc: dddff06f j 4d8 + +0000000000000700 : + 700: 00051063 bnez a0,700 + 704: 00008067 ret + +0000000000000708 <_init>: + 708: ff010113 add sp,sp,-16 + 70c: 00000593 li a1,0 + 710: 00000513 li a0,0 + 714: 00113423 sd ra,8(sp) + 718: 1d8000ef jal 8f0
+ 71c: c89ff0ef jal 3a4 + +0000000000000720 : + 720: 00b567b3 or a5,a0,a1 + 724: 00c7e7b3 or a5,a5,a2 + 728: 0077f793 and a5,a5,7 + 72c: 00c50833 add a6,a0,a2 + 730: 02078463 beqz a5,758 + 734: 00c58633 add a2,a1,a2 + 738: 00050793 mv a5,a0 + 73c: 0b057663 bgeu a0,a6,7e8 + 740: 0005c703 lbu a4,0(a1) + 744: 00158593 add a1,a1,1 + 748: 00178793 add a5,a5,1 + 74c: fee78fa3 sb a4,-1(a5) + 750: fec598e3 bne a1,a2,740 + 754: 00008067 ret + 758: 04050693 add a3,a0,64 + 75c: 0906f863 bgeu a3,a6,7ec + 760: 00058713 mv a4,a1 + 764: 00068793 mv a5,a3 + 768: 00073383 ld t2,0(a4) + 76c: 00873283 ld t0,8(a4) + 770: 01073f83 ld t6,16(a4) + 774: 01873f03 ld t5,24(a4) + 778: 02073e83 ld t4,32(a4) + 77c: 02873e03 ld t3,40(a4) + 780: 03073303 ld t1,48(a4) + 784: 03873883 ld a7,56(a4) + 788: 04078793 add a5,a5,64 + 78c: f877b023 sd t2,-128(a5) + 790: f857b423 sd t0,-120(a5) + 794: f9f7b823 sd t6,-112(a5) + 798: f9e7bc23 sd t5,-104(a5) + 79c: fbd7b023 sd t4,-96(a5) + 7a0: fbc7b423 sd t3,-88(a5) + 7a4: fa67b823 sd t1,-80(a5) + 7a8: fb17bc23 sd a7,-72(a5) + 7ac: 04070713 add a4,a4,64 + 7b0: fb07ece3 bltu a5,a6,768 + 7b4: fbf60613 add a2,a2,-65 + 7b8: fc067793 and a5,a2,-64 + 7bc: 04078793 add a5,a5,64 + 7c0: fc067613 and a2,a2,-64 + 7c4: 00f585b3 add a1,a1,a5 + 7c8: 00c687b3 add a5,a3,a2 + 7cc: f907f4e3 bgeu a5,a6,754 + 7d0: 0005b703 ld a4,0(a1) + 7d4: 00878793 add a5,a5,8 + 7d8: 00858593 add a1,a1,8 + 7dc: fee7bc23 sd a4,-8(a5) + 7e0: ff07e8e3 bltu a5,a6,7d0 + 7e4: 00008067 ret + 7e8: 00008067 ret + 7ec: 00050793 mv a5,a0 + 7f0: fddff06f j 7cc + +00000000000007f4 : + 7f4: 00c567b3 or a5,a0,a2 + 7f8: 0077f793 and a5,a5,7 + 7fc: 00c50633 add a2,a0,a2 + 800: 0ff5f713 zext.b a4,a1 + 804: 00078e63 beqz a5,820 + 808: 00050793 mv a5,a0 + 80c: 02c57c63 bgeu a0,a2,844 + 810: 00178793 add a5,a5,1 + 814: fee78fa3 sb a4,-1(a5) + 818: fef61ce3 bne a2,a5,810 + 81c: 00008067 ret + 820: 00004797 auipc a5,0x4 + 824: aa87b783 ld a5,-1368(a5) # 42c8 + 828: 02f70733 mul a4,a4,a5 + 82c: fec578e3 bgeu a0,a2,81c + 830: 00050793 mv a5,a0 + 834: 00878793 add a5,a5,8 + 838: fee7bc23 sd a4,-8(a5) + 83c: fec7ece3 bltu a5,a2,834 + 840: 00008067 ret + 844: 00008067 ret + +0000000000000848 : + 848: 00054783 lbu a5,0(a0) + 84c: 00078e63 beqz a5,868 + 850: 00050793 mv a5,a0 + 854: 0017c703 lbu a4,1(a5) + 858: 00178793 add a5,a5,1 + 85c: fe071ce3 bnez a4,854 + 860: 40a78533 sub a0,a5,a0 + 864: 00008067 ret + 868: 00000513 li a0,0 + 86c: 00008067 ret + +0000000000000870 : + 870: 00b506b3 add a3,a0,a1 + 874: 00050793 mv a5,a0 + 878: 00059863 bnez a1,888 + 87c: 0240006f j 8a0 + 880: 00178793 add a5,a5,1 + 884: 00f68a63 beq a3,a5,898 + 888: 0007c703 lbu a4,0(a5) + 88c: fe071ae3 bnez a4,880 + 890: 40a78533 sub a0,a5,a0 + 894: 00008067 ret + 898: 40a68533 sub a0,a3,a0 + 89c: 00008067 ret + 8a0: 00000513 li a0,0 + 8a4: 00008067 ret + +00000000000008a8 : + 8a8: 00054783 lbu a5,0(a0) + 8ac: 00158593 add a1,a1,1 + 8b0: 00150513 add a0,a0,1 + 8b4: fff5c703 lbu a4,-1(a1) + 8b8: 00078a63 beqz a5,8cc + 8bc: fee786e3 beq a5,a4,8a8 + 8c0: 0007851b sext.w a0,a5 + 8c4: 40e5053b subw a0,a0,a4 + 8c8: 00008067 ret + 8cc: 00000513 li a0,0 + 8d0: ff5ff06f j 8c4 + +00000000000008d4 : + 8d4: 00050793 mv a5,a0 + 8d8: 0005c703 lbu a4,0(a1) + 8dc: 00178793 add a5,a5,1 + 8e0: 00158593 add a1,a1,1 + 8e4: fee78fa3 sb a4,-1(a5) + 8e8: fe0718e3 bnez a4,8d8 + 8ec: 00008067 ret + +Disassembly of section .text.startup: + +00000000000008f0
: + 8f0: 00004517 auipc a0,0x4 + 8f4: 9e050513 add a0,a0,-1568 # 42d0 + 8f8: 00003597 auipc a1,0x3 + 8fc: 70858593 add a1,a1,1800 # 4000 + 900: 00003617 auipc a2,0x3 + 904: 76060613 add a2,a2,1888 # 4060 + 908: 00003697 auipc a3,0x3 + 90c: 7b868693 add a3,a3,1976 # 40c0 + 910: 02900713 li a4,41 + 914: 0c877857 vsetvli a6,a4,e16,m1,ta,ma + 918: 0008079b sext.w a5,a6 + 91c: 0206d507 vle16.v v10,(a3) + 920: 02065587 vle16.v v11,(a2) + 924: 0205d607 vle16.v v12,(a1) + 928: b6b52657 vmacc.vv v12,v10,v11 + 92c: 02055627 vse16.v v12,(a0) + 930: 00179793 sll a5,a5,0x1 + 934: 4107073b subw a4,a4,a6 + 938: 00f686b3 add a3,a3,a5 + 93c: 00f60633 add a2,a2,a5 + 940: 00f585b3 add a1,a1,a5 + 944: 00f50533 add a0,a0,a5 + 948: fc0716e3 bnez a4,914 + 94c: 86818693 add a3,gp,-1944 # 4330 + 950: 00003717 auipc a4,0x3 + 954: 77070713 add a4,a4,1904 # 40c0 + 958: 00003517 auipc a0,0x3 + 95c: 70850513 add a0,a0,1800 # 4060 + 960: 00003597 auipc a1,0x3 + 964: 6a058593 add a1,a1,1696 # 4000 + 968: 00003317 auipc t1,0x3 + 96c: 7aa30313 add t1,t1,1962 # 4112 + 970: 00068613 mv a2,a3 + 974: 00075783 lhu a5,0(a4) + 978: 00055883 lhu a7,0(a0) + 97c: 0005d803 lhu a6,0(a1) + 980: 00260613 add a2,a2,2 + 984: 031787bb mulw a5,a5,a7 + 988: 00270713 add a4,a4,2 + 98c: 00250513 add a0,a0,2 + 990: 00258593 add a1,a1,2 + 994: 010787bb addw a5,a5,a6 + 998: fef61f23 sh a5,-2(a2) + 99c: fc671ce3 bne a4,t1,974 + 9a0: 00004797 auipc a5,0x4 + 9a4: 93078793 add a5,a5,-1744 # 42d0 + 9a8: 85a18593 add a1,gp,-1958 # 4322 + 9ac: 00100513 li a0,1 + 9b0: 00079603 lh a2,0(a5) + 9b4: 00069703 lh a4,0(a3) + 9b8: 00278793 add a5,a5,2 + 9bc: 00268693 add a3,a3,2 + 9c0: 00e60463 beq a2,a4,9c8 + 9c4: 00000513 li a0,0 + 9c8: fef594e3 bne a1,a5,9b0 + 9cc: 00154513 xor a0,a0,1 + 9d0: 00008067 ret + 9d4: fff00513 li a0,-1 + 9d8: 00008067 ret + +Disassembly of section .rodata: + +0000000000004000 : + 4000: de7f6f4f .4byte 0xde7f6f4f + 4004: 6560 vmsge.vx v10,v0,zero,v0.t + 4006: 7f28 .2byte 0x7f28 + 4008: d47bad0b .4byte 0xd47bad0b + 400c: 3561 vmsge.vx v10,v0,zero,v0.t + 400e: 4922134f .4byte 0x4922134f + 4012: f869 .2byte 0xf869 + 4014: e2be .2byte 0xe2be + 4016: 66655b7f 2fd0f487 .byte 0x7f, 0x5b, 0x65, 0x66, 0x87, 0xf4, 0xd0, 0x2f, 0x85, 0xa2, 0xf8, 0x25, 0xb9, 0x7f, 0x66, 0x6d, 0x55, 0xc4, 0xdb, 0x5f + 401e: 25f8a285 6d667fb9 + 4026: 5fdbc455 + 402a: 9789 .2byte 0x9789 + 402c: eb716457 vwmulsu.vx v8,v23,sp + 4030: 7b54 .2byte 0x7b54 + 4032: def2 .2byte 0xdef2 + 4034: 4301 vmsge.vx v6,v0,zero,v0.t + 4036: fd67d5cf .4byte 0xfd67d5cf + 403a: 71b8 .2byte 0x71b8 + 403c: 7b50 .2byte 0x7b50 + 403e: 3ed7a5a3 sw a3,1003(a5) + 4042: 7231 .2byte 0x7231 + 4044: 1c16 .2byte 0x1c16 + 4046: a8c5c137 lui sp,0xa8c5c + 404a: 8948 .2byte 0x8948 + 404c: 4769 .2byte 0x4769 + 404e: f820 vmsge.vx v16,v0,ra,v0.t + 4050: 72589fb7 lui t6,0x72589 + 4054: 4c0c .2byte 0x4c0c + 4056: 0a9e .2byte 0xa9e + 4058: 1240 vmsge.vx v4,v0,zero,v0.t + 405a: 2f0a .2byte 0x2f0a + 405c: 20f2 .2byte 0x20f2 + 405e: 920a .2byte 0x920a + +0000000000004060 : + 4060: 7729 .2byte 0x7729 + 4062: 4ec6 .2byte 0x4ec6 + 4064: 160e .2byte 0x160e + 4066: aa00 vmsge.vx v20,v0,ra,v0.t + 4068: b0d5 .2byte 0xb0d5 + 406a: be1a073b .4byte 0xbe1a073b + 406e: c35e .2byte 0xc35e + 4070: e6b2 .2byte 0xe6b2 + 4072: 6f98 .2byte 0x6f98 + 4074: de929e9b .4byte 0xde929e9b + 4078: 72e270db .4byte 0x72e270db + 407c: e9d8 .2byte 0xe9d8 + 407e: 9bf6 .2byte 0x9bf6 + 4080: 44dc .2byte 0x44dc + 4082: f1b6bdef jal s11,fffffffffff6ff9c <_end+0xffffffffeff6ff54> + 4086: 8df9 .2byte 0x8df9 + 4088: b8ba .2byte 0xb8ba + 408a: 1e11 .2byte 0x1e11 + 408c: 4132 .2byte 0x4132 + 408e: d955 .2byte 0xd955 + 4090: 1711 .2byte 0x1711 + 4092: 9a81 vmsge.vx v21,v0,ra,v0.t + 4094: 645f 190b fe67 .byte 0x5f, 0x64, 0x0b, 0x19, 0x67, 0xfe + 409a: 0438 .2byte 0x438 + 409c: 2255 .2byte 0x2255 + 409e: c2dea2b3 .4byte 0xc2dea2b3 + 40a2: 69ac .2byte 0x69ac + 40a4: dd7d .2byte 0xdd7d + 40a6: d433ccc3 vmsge.vx v25,v3,t2,v0.t + 40aa: 30c4 .2byte 0x30c4 + 40ac: 7639 .2byte 0x7639 + 40ae: ae61 vmsge.vx v28,v0,ra,v0.t + 40b0: 717f .2byte 0x717f + 40b2: a7bc8f9b addw t6,s9,-1413 + 40b6: 3df5 .2byte 0x3df5 + 40b8: 6b708b4f .4byte 0x6b708b4f + 40bc: 55c5 .2byte 0x55c5 + 40be: c9da .2byte 0xc9da + +00000000000040c0 : + 40c0: 968d .2byte 0x968d + 40c2: d593c97b .4byte 0xd593c97b + 40c6: 631e .2byte 0x631e + 40c8: b990 .2byte 0xb990 + 40ca: 5cbaad63 vmsge.vx v26,v11,s5,v0.t + 40ce: 5fe4 .2byte 0x5fe4 + 40d0: 9232 .2byte 0x9232 + 40d2: aa6a .2byte 0xaa6a + 40d4: 4186 .2byte 0x4186 + 40d6: 4d80d87b .4byte 0x4d80d87b + 40da: 31a7d16f jal sp,813f4 <__global_pointer$+0x7c92c> + 40de: a180 vmsge.vx v3,v0,ra,v0.t + 40e0: 6bc2 vmsge.vx v23,v0,zero,v0.t + 40e2: b1ac .2byte 0xb1ac + 40e4: b049 .2byte 0xb049 + 40e6: 3552 .2byte 0x3552 + 40e8: c256 .2byte 0xc256 + 40ea: 5275 .2byte 0x5275 + 40ec: 7cfe .2byte 0x7cfe + 40ee: 496c .2byte 0x496c + 40f0: d4a6 .2byte 0xd4a6 + 40f2: f964 .2byte 0xf964 + 40f4: 8da3049b addw s1,t1,-1830 + 40f8: bb15 .2byte 0xbb15 + 40fa: 975c .2byte 0x975c + 40fc: c4ad .2byte 0xc4ad + 40fe: cdac .2byte 0xcdac + 4100: add7e053 .4byte 0xadd7e053 + 4104: 529c8f93 add t6,s9,1321 + 4108: 969c .2byte 0x969c + 410a: 601d .2byte 0x601d + 410c: 14ce39a7 .4byte 0x14ce39a7 + 4110: 7f38 .2byte 0x7f38 + 4112: 3884 .2byte 0x3884 + 4114: 8d44 .2byte 0x8d44 + 4116: f1809d8b .4byte 0xf1809d8b + 411a: 2f01 vmsge.vx v30,v0,zero,v0.t + 411c: ca10 .2byte 0xca10 + 411e: 3bc0 vmsge.vx v23,v0,zero,v0.t + 4120: c3c0 vmsge.vx v7,v0,ra,v0.t + 4122: ffff .2byte 0xffff + 4124: c404 .2byte 0xc404 + 4126: ffff .2byte 0xffff + 4128: c448 .2byte 0xc448 + 412a: ffff .2byte 0xffff + 412c: c358 .2byte 0xc358 + 412e: ffff .2byte 0xffff + 4130: c48c .2byte 0xc48c + 4132: ffff .2byte 0xffff + 4134: c4d0 .2byte 0xc4d0 + 4136: ffff .2byte 0xffff + 4138: c514 .2byte 0xc514 + 413a: ffff .2byte 0xffff + 413c: c558 .2byte 0xc558 + 413e: ffff .2byte 0xffff + 4140: c358 .2byte 0xc358 + 4142: ffff .2byte 0xffff + 4144: c358 .2byte 0xc358 + 4146: ffff .2byte 0xffff + 4148: c358 .2byte 0xc358 + 414a: ffff .2byte 0xffff + 414c: c59c .2byte 0xc59c + 414e: ffff .2byte 0xffff + +Disassembly of section .rodata.str1.8: + +0000000000004150 <.rodata.str1.8>: + 4150: 6c637963 bgeu t1,t1,4822 <_tbss_end+0x492> + 4154: 3a65 .2byte 0x3a65 + 4156: 0020 vmsge.vx v0,v0,zero,v0.t + 4158: 690a .2byte 0x690a + 415a: 736e .2byte 0x736e + 415c: 7274 .2byte 0x7274 + 415e: 7465 .2byte 0x7465 + 4160: 203a .2byte 0x203a + 4162: 0000 vmsge.vx v0,v0,zero,v0.t + 4164: 0000 vmsge.vx v0,v0,zero,v0.t + 4166: 0000 vmsge.vx v0,v0,zero,v0.t + 4168: 7845 .2byte 0x7845 + 416a: 7469 .2byte 0x7469 + 416c: 6320 vmsge.vx v6,v0,zero,v0.t + 416e: 3a65646f jal s0,5a514 <__global_pointer$+0x55a4c> + 4172: 0020 vmsge.vx v0,v0,zero,v0.t + 4174: 0000 vmsge.vx v0,v0,zero,v0.t + 4176: 0000 vmsge.vx v0,v0,zero,v0.t + 4178: 4e49 .2byte 0x4e49 + 417a: 55525453 .4byte 0x55525453 + 417e: 4f495443 vmsge.vx v8,v20,s2 + 4182: 204e .2byte 0x204e + 4184: 4441 vmsge.vx v8,v0,zero,v0.t + 4186: 5244 .2byte 0x5244 + 4188: 5345 .2byte 0x5345 + 418a: 494d2053 .4byte 0x494d2053 + 418e: 494c4153 .4byte 0x494c4153 + 4192: 44454e47 .4byte 0x44454e47 + 4196: 6120 vmsge.vx v2,v0,zero,v0.t + 4198: 2074 .2byte 0x2074 + 419a: 4350 .2byte 0x4350 + 419c: 203a .2byte 0x203a + 419e: 0000 vmsge.vx v0,v0,zero,v0.t + 41a0: 4e49 .2byte 0x4e49 + 41a2: 55525453 .4byte 0x55525453 + 41a6: 4f495443 vmsge.vx v8,v20,s2 + 41aa: 204e .2byte 0x204e + 41ac: 4341 vmsge.vx v6,v0,zero,v0.t + 41ae: 53534543 vmsge.vx v10,v21,t1 + 41b2: 4620 vmsge.vx v12,v0,zero,v0.t + 41b4: 5541 vmsge.vx v10,v0,zero,v0.t + 41b6: 544c .2byte 0x544c + 41b8: 6120 vmsge.vx v2,v0,zero,v0.t + 41ba: 2074 .2byte 0x2074 + 41bc: 4350 .2byte 0x4350 + 41be: 203a .2byte 0x203a + ... + 41c8: 4c49 .2byte 0x4c49 + 41ca: 454c .2byte 0x454c + 41cc: 204c4147 .4byte 0x204c4147 + 41d0: 4e49 .2byte 0x4e49 + 41d2: 55525453 .4byte 0x55525453 + 41d6: 4f495443 vmsge.vx v8,v20,s2 + 41da: 204e .2byte 0x204e + 41dc: 7461 vmsge.vx v8,v0,zero,v0.t + 41de: 5020 vmsge.vx v0,v0,zero,v0.t + 41e0: 00203a43 vmsge.vx v20,v2,zero,v0.t + 41e4: 0000 vmsge.vx v0,v0,zero,v0.t + 41e6: 0000 vmsge.vx v0,v0,zero,v0.t + 41e8: 4f4c .2byte 0x4f4c + 41ea: 4441 vmsge.vx v8,v0,zero,v0.t + 41ec: 4120 vmsge.vx v2,v0,zero,v0.t + 41ee: 4444 .2byte 0x4444 + 41f0: 4552 .2byte 0x4552 + 41f2: 4d205353 .4byte 0x4d205353 + 41f6: 5349 .2byte 0x5349 + 41f8: 4c41 vmsge.vx v24,v0,zero,v0.t + 41fa: 4749 .2byte 0x4749 + 41fc: 454e .2byte 0x454e + 41fe: 2044 .2byte 0x2044 + 4200: 7461 vmsge.vx v8,v0,zero,v0.t + 4202: 5020 vmsge.vx v0,v0,zero,v0.t + 4204: 00203a43 vmsge.vx v20,v2,zero,v0.t + 4208: 4f4c .2byte 0x4f4c + 420a: 4441 vmsge.vx v8,v0,zero,v0.t + 420c: 4120 vmsge.vx v2,v0,zero,v0.t + 420e: 53454343 vmsge.vx v6,v20,a0 + 4212: 41462053 .4byte 0x41462053 + 4216: 4c55 .2byte 0x4c55 + 4218: 2054 .2byte 0x2054 + 421a: 7461 vmsge.vx v8,v0,zero,v0.t + 421c: 5020 vmsge.vx v0,v0,zero,v0.t + 421e: 00203a43 vmsge.vx v20,v2,zero,v0.t + 4222: 0000 vmsge.vx v0,v0,zero,v0.t + 4224: 0000 vmsge.vx v0,v0,zero,v0.t + 4226: 0000 vmsge.vx v0,v0,zero,v0.t + 4228: 524f5453 .4byte 0x524f5453 + 422c: 2045 .2byte 0x2045 + 422e: 4441 vmsge.vx v8,v0,zero,v0.t + 4230: 5244 .2byte 0x5244 + 4232: 5345 .2byte 0x5345 + 4234: 494d2053 .4byte 0x494d2053 + 4238: 494c4153 .4byte 0x494c4153 + 423c: 44454e47 .4byte 0x44454e47 + 4240: 6120 vmsge.vx v2,v0,zero,v0.t + 4242: 2074 .2byte 0x2074 + 4244: 4350 .2byte 0x4350 + 4246: 203a .2byte 0x203a + ... + 4250: 524f5453 .4byte 0x524f5453 + 4254: 2045 .2byte 0x2045 + 4256: 4341 vmsge.vx v6,v0,zero,v0.t + 4258: 53534543 vmsge.vx v10,v21,t1 + 425c: 4620 vmsge.vx v12,v0,zero,v0.t + 425e: 5541 vmsge.vx v10,v0,zero,v0.t + 4260: 544c .2byte 0x544c + 4262: 6120 vmsge.vx v2,v0,zero,v0.t + 4264: 2074 .2byte 0x2074 + 4266: 4350 .2byte 0x4350 + 4268: 203a .2byte 0x203a + 426a: 0000 vmsge.vx v0,v0,zero,v0.t + 426c: 0000 vmsge.vx v0,v0,zero,v0.t + 426e: 0000 vmsge.vx v0,v0,zero,v0.t + 4270: 4345 .2byte 0x4345 + 4272: 4c41 vmsge.vx v24,v0,zero,v0.t + 4274: 204c .2byte 0x204c + 4276: 5246 .2byte 0x5246 + 4278: 4d204d4f .4byte 0x4d204d4f + 427c: 4d2d .2byte 0x4d2d + 427e: 2045444f .4byte 0x2045444f + 4282: 7461 vmsge.vx v8,v0,zero,v0.t + 4284: 5020 vmsge.vx v0,v0,zero,v0.t + 4286: 00203a43 vmsge.vx v20,v2,zero,v0.t + 428a: 0000 vmsge.vx v0,v0,zero,v0.t + 428c: 0000 vmsge.vx v0,v0,zero,v0.t + 428e: 0000 vmsge.vx v0,v0,zero,v0.t + 4290: 4e55 .2byte 0x4e55 + 4292: 574f4e4b .4byte 0x574f4e4b + 4296: 204e .2byte 0x204e + 4298: 5845 .2byte 0x5845 + 429a: 54504543 vmsge.vx v10,v5,zero,v0.t + 429e: 4f49 .2byte 0x4f49 + 42a0: 204e .2byte 0x204e + 42a2: 7461 vmsge.vx v8,v0,zero,v0.t + 42a4: 5020 vmsge.vx v0,v0,zero,v0.t + 42a6: 00203a43 vmsge.vx v20,v2,zero,v0.t + 42aa: 0000 vmsge.vx v0,v0,zero,v0.t + 42ac: 0000 vmsge.vx v0,v0,zero,v0.t + 42ae: 0000 vmsge.vx v0,v0,zero,v0.t + 42b0: 430a .2byte 0x430a + 42b2: 4548 .2byte 0x4548 + 42b4: 4d204b43 vmsge.vx v22,v18,zero,v0.t + 42b8: 53554143 vmsge.vx v2,v21,a0 + 42bc: 2045 .2byte 0x2045 + 42be: 6e69 .2byte 0x6e69 + 42c0: 5220 vmsge.vx v4,v0,zero,v0.t + 42c2: 4c54 .2byte 0x4c54 + ... + +Disassembly of section .sdata: + +00000000000042c8 <__global_pointer$-0x800>: + 42c8: 0101 vmsge.vx v2,v0,zero,v0.t + 42ca: 0101 vmsge.vx v2,v0,zero,v0.t + 42cc: 0101 vmsge.vx v2,v0,zero,v0.t + 42ce: 0101 vmsge.vx v2,v0,zero,v0.t + +Disassembly of section .bss: + +00000000000042d0 : + ... + +0000000000004330 : + ... + +Disassembly of section .tohost: + +0000000010000000 : + ... + +0000000010000040 : + ... + +Disassembly of section .comment: + +0000000000000000 <.comment>: + 0: 3a434347 .4byte 0x3a434347 + 4: 2820 vmsge.vx v16,v0,zero,v0.t + 6: 65653267 .4byte 0x65653267 + a: 6535 .2byte 0x6535 + c: 3334 .2byte 0x3334 + e: 3030 .2byte 0x3030 + 10: 3831 .2byte 0x3831 + 12: 2029 .2byte 0x2029 + 14: 3231 .2byte 0x3231 + 16: 322e .2byte 0x322e + 18: 302e .2byte 0x302e + ... + +Disassembly of section .riscv.attributes: + +0000000000000000 <.riscv.attributes>: + 0: 5e41 vmsge.vx v28,v0,zero,v0.t + 2: 0000 vmsge.vx v0,v0,zero,v0.t + 4: 7200 vmsge.vx v4,v0,zero,v0.t + 6: 7369 .2byte 0x7369 + 8: 01007663 bgeu zero,a6,14 <_start+0x14> + c: 0054 .2byte 0x54 + e: 0000 vmsge.vx v0,v0,zero,v0.t + 10: 1004 .2byte 0x1004 + 12: 7205 .2byte 0x7205 + 14: 3676 .2byte 0x3676 + 16: 6934 .2byte 0x6934 + 18: 7032 .2byte 0x7032 + 1a: 5f31 .2byte 0x5f31 + 1c: 326d .2byte 0x326d + 1e: 3070 .2byte 0x3070 + 20: 7a5f 6369 7273 .byte 0x5f, 0x7a, 0x69, 0x63, 0x73, 0x72 + 26: 7032 .2byte 0x7032 + 28: 5f30 .2byte 0x5f30 + 2a: 6d7a .2byte 0x6d7a + 2c: 756d .2byte 0x756d + 2e: 316c .2byte 0x316c + 30: 3070 .2byte 0x3070 + 32: 7a5f 6576 3233 .byte 0x5f, 0x7a, 0x76, 0x65, 0x33, 0x32 + 38: 3178 .2byte 0x3178 + 3a: 3070 .2byte 0x3070 + 3c: 7a5f 6576 3436 .byte 0x5f, 0x7a, 0x76, 0x65, 0x36, 0x34 + 42: 3178 .2byte 0x3178 + 44: 3070 .2byte 0x3070 + 46: 7a5f 6c76 3233 .byte 0x5f, 0x7a, 0x76, 0x6c, 0x33, 0x32 + 4c: 3162 vmsge.vx v2,v0,zero,v0.t + 4e: 3070 .2byte 0x3070 + 50: 7a5f 6c76 3436 .byte 0x5f, 0x7a, 0x76, 0x6c, 0x36, 0x34 + 56: 3162 vmsge.vx v2,v0,zero,v0.t + 58: 3070 .2byte 0x3070 + 5a: 0800 vmsge.vx v16,v0,zero,v0.t + 5c: 0a01 vmsge.vx v20,v0,zero,v0.t + 5e: 0b Address 0x5e is out of bounds. + diff --git a/src/main/resources/applications_vector/vmacc/vmacc.c b/src/main/resources/applications_vector/vmacc/vmacc.c new file mode 100644 index 00000000..376a1dee --- /dev/null +++ b/src/main/resources/applications_vector/vmacc/vmacc.c @@ -0,0 +1,61 @@ +#include "util.h" + +#define size_t long +#define N 48 + +const signed short dataArray0[N] = {-26995, -13957, -10861, 25374, -18032, -21149, 23738, 24548, -28110, -21910, 16774, -10117, 19840, -11921, 12711, -24192, 27586, -20052, -20407, 13650, -15786, 21109, 31998, 18796, -11098, -1692, 1179, -29277, -17643, -26788, -15187, -12884, -8109, -21033, -28781, 21148, -26980, 24605, 14759, 5326, 32568, 14468, -29372, -25205, -3712, 12033, -13808, 15296}; +const signed short dataArray1[N] = {30505, 20166, 5646, -22016, -20267, 1851, -16870, -15522, -6478, 28568, -24933, -8558, 28891, 29410, -5672, -25610, 17628, -16913, -3658, -29191, -18246, 7697, 16690, -9899, 5905, -25983, 25695, 6411, -409, 1080, 8789, -23885, -15650, 27052, -8835, -13117, -11213, 12484, 30265, -20895, 29055, -28773, -22596, 15861, -29873, 27504, 21957, -13862}; +const signed short dataArray2[N] = {28495, -8577, 25952, 32552, -21237, -11141, 13665, 4943, 18722, -1943, -7490, 23423, 26213, -2937, 12240, -23931, 9720, 32697, 28006, -15275, 24539, -26743, 25687, -5263, 31572, -8462, 17153, -10801, -665, 29112, 31568, -23133, 16087, 29233, 7190, -16073, -22331, -30392, 18281, -2016, -24649, 29272, 19468, 2718, 4672, 12042, 8434, -28150}; +signed short resultArray[N] = {0}; +signed short answerArray[N] = {0}; + +extern void printstr(char* str); +extern void int64ToHex(long num, char* str); +extern void int32ToHex(int num, char* str); +extern void clearCounters(); +extern void printCounters(); + +int main(int argc, char** argv) { + int vl, avl = 41; + const signed short *ptr0 = dataArray0; + const signed short *ptr1 = dataArray1; + const signed short *ptr2 = dataArray2; + signed short *ptr3 = resultArray; + while(avl != 0) { + asm volatile ("vsetvli %0, %1, e16, m1, ta, ma" + : "=r"(vl) + : "r"(avl)); + // asm volatile ("li t0, 0x1919"); + asm volatile ("vle16.v v10, (%0)" + : + : "r"(ptr0)); + asm volatile ("vle16.v v11, (%0)" + : + : "r"(ptr1)); + asm volatile ("vle16.v v12, (%0)" + : + : "r"(ptr2)); + // v12 = v10 * v11 + v12 + asm volatile ("vmacc.vv v12, v10, v11"); + asm volatile ("vse16.v v12, (%0)" + : + : "r"(ptr3)); + ptr0 += vl; + ptr1 += vl; + ptr2 += vl; + ptr3 += vl; + avl -= vl; + } + int i; + for(i=0; i<41; i++) { + answerArray[i] = dataArray0[i] * dataArray1[i] + dataArray2[i]; + } + + _Bool correct = 1; + for(i=0; i<41; i++) { + if(resultArray[i] != answerArray[i]) { + correct = 0; + } + } + return !correct; +} diff --git a/src/main/resources/applications_vector/vmacc_data.hex b/src/main/resources/applications_vector/vmacc_data.hex new file mode 100644 index 00000000..76ca0b6b --- /dev/null +++ b/src/main/resources/applications_vector/vmacc_data.hex @@ -0,0 +1,180 @@ +de7f6f4f +7f286560 +d47bad0b +134f3561 +f8694922 +5b7fe2be +f4876665 +a2852fd0 +7fb925f8 +c4556d66 +97895fdb +eb716457 +def27b54 +d5cf4301 +71b8fd67 +a5a37b50 +72313ed7 +c1371c16 +8948a8c5 +f8204769 +72589fb7 +0a9e4c0c +2f0a1240 +920a20f2 +4ec67729 +aa00160e +073bb0d5 +c35ebe1a +6f98e6b2 +de929e9b +72e270db +9bf6e9d8 +bdef44dc +8df9f1b6 +1e11b8ba +d9554132 +9a811711 +190b645f +0438fe67 +a2b32255 +69acc2de +ccc3dd7d +30c4d433 +ae617639 +8f9b717f +3df5a7bc +6b708b4f +c9da55c5 +c97b968d +631ed593 +ad63b990 +5fe45cba +aa6a9232 +d87b4186 +d16f4d80 +a18031a7 +b1ac6bc2 +3552b049 +5275c256 +496c7cfe +f964d4a6 +8da3049b +975cbb15 +cdacc4ad +add7e053 +529c8f93 +601d969c +14ce39a7 +38847f38 +9d8b8d44 +2f01f180 +3bc0ca10 +ffffc3c0 +ffffc404 +ffffc448 +ffffc358 +ffffc48c +ffffc4d0 +ffffc514 +ffffc558 +ffffc358 +ffffc358 +ffffc358 +ffffc59c +6c637963 +00203a65 +736e690a +74657274 +0000203a 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b/src/main/resources/applications_vector/vmacc_inst.hex new file mode 100644 index 00000000..ec9e8524 --- /dev/null +++ b/src/main/resources/applications_vector/vmacc_inst.hex @@ -0,0 +1,631 @@ +00000093 +00000113 +00000193 +00000213 +00000293 +00000313 +00000393 +00000413 +00000493 +00000513 +00000593 +00000613 +00000693 +00000713 +00000793 +00000813 +00000893 +00000913 +00000993 +00000a13 +00000a93 +00000b13 +00000b93 +00000c13 +00000c93 +00000d13 +00000d93 +00000e13 +00000e93 +00000f13 +00000f93 +00000297 +03828293 +30529073 +00005197 +a4018193 +10000217 +ff720213 +fc027213 +f1402573 +00100593 +00b57063 +00006137 +ff01011b +6580006f +ef010113 +00113423 +00213823 +00313c23 +02413023 +02513423 +02613823 +02713c23 +04813023 +04913423 +04a13823 +04b13c23 +06c13023 +06d13423 +06e13823 +06f13c23 +09013023 +09113423 +09213823 +09313c23 +0b413023 +0b513423 +0b613823 +0b713c23 +0d813023 +0d913423 +0da13823 +0db13c23 +0fc13023 +0fd13423 +0fe13823 +0ff13c23 +34202573 +341025f3 +00010613 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+02900713 +0c877857 +0008079b +0206d507 +02065587 +0205d607 +b6b52657 +02055627 +00179793 +4107073b +00f686b3 +00f60633 +00f585b3 +00f50533 +fc0716e3 +86818693 +00003717 +77070713 +00003517 +70850513 +00003597 +6a058593 +00003317 +7aa30313 +00068613 +00075783 +00055883 +0005d803 +00260613 +031787bb +00270713 +00250513 +00258593 +010787bb +fef61f23 +fc671ce3 +00004797 +93078793 +85a18593 +00100513 +00079603 +00069703 +00278793 +00268693 +00e60463 +00000513 +fef594e3 +00154513 +00008067 +fff00513 +00008067 diff --git a/src/main/scala/my_random_useful_programs/RandomArrayGen.scala b/src/main/scala/my_random_useful_programs/RandomArrayGen.scala index 4b0e3f30..d2cb2d44 100644 --- a/src/main/scala/my_random_useful_programs/RandomArrayGen.scala +++ b/src/main/scala/my_random_useful_programs/RandomArrayGen.scala @@ -23,12 +23,17 @@ object RandomArrayWithElenGen extends App { private def function(): Boolean = { (0 until 4).map(_ => Random.nextBoolean()).reduce(_ && _) } + val randomArray = (0 until 3).map( + _ => (0 until 48).map(_ => Random.nextInt(0xFFFF) - 0x8000) + ) val randomArray0 = (0 until 48).map(_ => Random.nextInt(0xFFFF) - 0x8000) val randomArray1 = (0 until 48).map(_ => Random.nextInt(0xFFFF) - 0x8000) + val randomArray2 = (0 until 48).map(_ => Random.nextInt(0xFFFF) - 0x8000) val boolArray = (0 until 48).map(_ => function()) val hasEqualArray = randomArray0.lazyZip(randomArray1).lazyZip(boolArray).map { case (v1, v2, b) => if(b) v1 else v2 } - println(randomArray0.mkString("{", ", ", "};")) - println(randomArray1.mkString("{", ", ", "};")) + randomArray.foreach( + l => println(l.mkString("{", ", ", "};")) + ) } \ No newline at end of file diff --git a/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala b/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala index a4473623..32c21285 100644 --- a/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala +++ b/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala @@ -139,7 +139,8 @@ class Zve64xAppTestForVecCpu extends AnyFlatSpec with ChiselScalatestTester { "vadd", "vsub", "vand", "vmseq", "vmslt", "vmsle", "vmsgt", "vminmax", "vmerge", "vmv", "vmand", "vmor", "vmxor", - "vmul", "vmulh", "vmulhu", "vmulhsu" + "vmul", "vmulh", "vmulhu", "vmulhsu", + "vmacc", ) val applicationTest = Seq( "vector_median" From 09fc478e18f7ed43b27f2fba077994a137a2f71d Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Mon, 13 Nov 2023 13:32:34 +0900 Subject: [PATCH 04/14] vmacc.vx --- .../resources/applications_vector/vmacc.dump | 112 ++++++++++++------ .../applications_vector/vmacc/vmacc.c | 34 ++++++ .../applications_vector/vmacc_inst.hex | 88 ++++++++++---- 3 files changed, 178 insertions(+), 56 deletions(-) diff --git a/src/main/resources/applications_vector/vmacc.dump b/src/main/resources/applications_vector/vmacc.dump index 796753c6..0d336d8b 100644 --- a/src/main/resources/applications_vector/vmacc.dump +++ b/src/main/resources/applications_vector/vmacc.dump @@ -638,42 +638,86 @@ Disassembly of section .text.startup: 940: 00f585b3 add a1,a1,a5 944: 00f50533 add a0,a0,a5 948: fc0716e3 bnez a4,914 - 94c: 86818693 add a3,gp,-1944 # 4330 - 950: 00003717 auipc a4,0x3 - 954: 77070713 add a4,a4,1904 # 40c0 - 958: 00003517 auipc a0,0x3 - 95c: 70850513 add a0,a0,1800 # 4060 - 960: 00003597 auipc a1,0x3 - 964: 6a058593 add a1,a1,1696 # 4000 + 94c: 00003697 auipc a3,0x3 + 950: 77468693 add a3,a3,1908 # 40c0 + 954: 00003617 auipc a2,0x3 + 958: 70c60613 add a2,a2,1804 # 4060 + 95c: 86818593 add a1,gp,-1944 # 4330 + 960: 00003897 auipc a7,0x3 + 964: 6a088893 add a7,a7,1696 # 4000 968: 00003317 auipc t1,0x3 96c: 7aa30313 add t1,t1,1962 # 4112 - 970: 00068613 mv a2,a3 - 974: 00075783 lhu a5,0(a4) - 978: 00055883 lhu a7,0(a0) - 97c: 0005d803 lhu a6,0(a1) - 980: 00260613 add a2,a2,2 - 984: 031787bb mulw a5,a5,a7 - 988: 00270713 add a4,a4,2 - 98c: 00250513 add a0,a0,2 - 990: 00258593 add a1,a1,2 - 994: 010787bb addw a5,a5,a6 - 998: fef61f23 sh a5,-2(a2) - 99c: fc671ce3 bne a4,t1,974 - 9a0: 00004797 auipc a5,0x4 - 9a4: 93078793 add a5,a5,-1744 # 42d0 - 9a8: 85a18593 add a1,gp,-1958 # 4322 - 9ac: 00100513 li a0,1 - 9b0: 00079603 lh a2,0(a5) - 9b4: 00069703 lh a4,0(a3) - 9b8: 00278793 add a5,a5,2 - 9bc: 00268693 add a3,a3,2 - 9c0: 00e60463 beq a2,a4,9c8 - 9c4: 00000513 li a0,0 - 9c8: fef594e3 bne a1,a5,9b0 - 9cc: 00154513 xor a0,a0,1 - 9d0: 00008067 ret - 9d4: fff00513 li a0,-1 - 9d8: 00008067 ret + 970: 00058813 mv a6,a1 + 974: 00060513 mv a0,a2 + 978: 00068713 mv a4,a3 + 97c: 00075783 lhu a5,0(a4) + 980: 00055e83 lhu t4,0(a0) + 984: 0008de03 lhu t3,0(a7) + 988: 00280813 add a6,a6,2 + 98c: 03d787bb mulw a5,a5,t4 + 990: 00270713 add a4,a4,2 + 994: 00250513 add a0,a0,2 + 998: 00288893 add a7,a7,2 + 99c: 01c787bb addw a5,a5,t3 + 9a0: fef81f23 sh a5,-2(a6) + 9a4: fc671ce3 bne a4,t1,97c + 9a8: 00004717 auipc a4,0x4 + 9ac: 92870713 add a4,a4,-1752 # 42d0 + 9b0: 85a18893 add a7,gp,-1958 # 4322 + 9b4: 86818813 add a6,gp,-1944 # 4330 + 9b8: 00070793 mv a5,a4 + 9bc: 00100513 li a0,1 + 9c0: 00081e83 lh t4,0(a6) + 9c4: 00079e03 lh t3,0(a5) + 9c8: 00280813 add a6,a6,2 + 9cc: 00278793 add a5,a5,2 + 9d0: 01ce8463 beq t4,t3,9d8 + 9d4: 00000513 li a0,0 + 9d8: ff1794e3 bne a5,a7,9c0 + 9dc: 000022b7 lui t0,0x2 + 9e0: 00004f17 auipc t5,0x4 + 9e4: 8f0f0f13 add t5,t5,-1808 # 42d0 + 9e8: 00003e97 auipc t4,0x3 + 9ec: 678e8e93 add t4,t4,1656 # 4060 + 9f0: 00003e17 auipc t3,0x3 + 9f4: 6d0e0e13 add t3,t3,1744 # 40c0 + 9f8: 02900813 li a6,41 + 9fc: 9192829b addw t0,t0,-1767 # 1919 + a00: 0c887fd7 vsetvli t6,a6,e16,m1,ta,ma + a04: 000f879b sext.w a5,t6 + a08: 020e5507 vle16.v v10,(t3) + a0c: 020ed587 vle16.v v11,(t4) + a10: b6a2e5d7 vmacc.vx v11,t0,v10 + a14: 020f55a7 vse16.v v11,(t5) + a18: 00179793 sll a5,a5,0x1 + a1c: 41f8083b subw a6,a6,t6 + a20: 00fe0e33 add t3,t3,a5 + a24: 00fe8eb3 add t4,t4,a5 + a28: 00ff0f33 add t5,t5,a5 + a2c: fc081ae3 bnez a6,a00 + a30: 00002eb7 lui t4,0x2 + a34: 86818813 add a6,gp,-1944 # 4330 + a38: 919e8e9b addw t4,t4,-1767 # 1919 + a3c: 0006d783 lhu a5,0(a3) + a40: 00065e03 lhu t3,0(a2) + a44: 00280813 add a6,a6,2 + a48: 02fe87bb mulw a5,t4,a5 + a4c: 00268693 add a3,a3,2 + a50: 00260613 add a2,a2,2 + a54: 01c787bb addw a5,a5,t3 + a58: fef81f23 sh a5,-2(a6) + a5c: fe6690e3 bne a3,t1,a3c + a60: 00071683 lh a3,0(a4) + a64: 00059783 lh a5,0(a1) + a68: 00270713 add a4,a4,2 + a6c: 00258593 add a1,a1,2 + a70: 00f68463 beq a3,a5,a78 + a74: 00000513 li a0,0 + a78: ff1714e3 bne a4,a7,a60 + a7c: 00154513 xor a0,a0,1 + a80: 00008067 ret + a84: fff00513 li a0,-1 + a88: 00008067 ret Disassembly of section .rodata: diff --git a/src/main/resources/applications_vector/vmacc/vmacc.c b/src/main/resources/applications_vector/vmacc/vmacc.c index 376a1dee..d37efde4 100644 --- a/src/main/resources/applications_vector/vmacc/vmacc.c +++ b/src/main/resources/applications_vector/vmacc/vmacc.c @@ -57,5 +57,39 @@ int main(int argc, char** argv) { correct = 0; } } + avl = 41; + ptr0 = dataArray0; + ptr1 = dataArray1; + ptr3 = resultArray; + while(avl != 0) { + asm volatile ("vsetvli %0, %1, e16, m1, ta, ma" + : "=r"(vl) + : "r"(avl)); + asm volatile ("vle16.v v10, (%0)" + : + : "r"(ptr0)); + asm volatile ("vle16.v v11, (%0)" + : + : "r"(ptr1)); + // v11 = 0x1919 * v10 + v11 + asm volatile ("vmacc.vx v11, %0, v10" + : + : "r"(0x1919)); + asm volatile ("vse16.v v11, (%0)" + : + : "r"(ptr3)); + ptr0 += vl; + ptr1 += vl; + ptr3 += vl; + avl -= vl; + } + for(i=0; i<41; i++) { + answerArray[i] = 0x1919 * dataArray0[i] + dataArray1[i]; + } + for(i=0; i<41; i++) { + if(resultArray[i] != answerArray[i]) { + correct = 0; + } + } return !correct; } diff --git a/src/main/resources/applications_vector/vmacc_inst.hex b/src/main/resources/applications_vector/vmacc_inst.hex index ec9e8524..4dc9d509 100644 --- a/src/main/resources/applications_vector/vmacc_inst.hex +++ b/src/main/resources/applications_vector/vmacc_inst.hex @@ -593,38 +593,82 @@ b6b52657 00f585b3 00f50533 fc0716e3 -86818693 -00003717 -77070713 -00003517 -70850513 -00003597 -6a058593 +00003697 +77468693 +00003617 +70c60613 +86818593 +00003897 +6a088893 00003317 7aa30313 -00068613 +00058813 +00060513 +00068713 00075783 -00055883 -0005d803 -00260613 -031787bb +00055e83 +0008de03 +00280813 +03d787bb 00270713 00250513 -00258593 -010787bb -fef61f23 +00288893 +01c787bb +fef81f23 fc671ce3 -00004797 -93078793 -85a18593 +00004717 +92870713 +85a18893 +86818813 +00070793 00100513 -00079603 -00069703 +00081e83 +00079e03 +00280813 00278793 +01ce8463 +00000513 +ff1794e3 +000022b7 +00004f17 +8f0f0f13 +00003e97 +678e8e93 +00003e17 +6d0e0e13 +02900813 +9192829b +0c887fd7 +000f879b +020e5507 +020ed587 +b6a2e5d7 +020f55a7 +00179793 +41f8083b +00fe0e33 +00fe8eb3 +00ff0f33 +fc081ae3 +00002eb7 +86818813 +919e8e9b +0006d783 +00065e03 +00280813 +02fe87bb 00268693 -00e60463 +00260613 +01c787bb +fef81f23 +fe6690e3 +00071683 +00059783 +00270713 +00258593 +00f68463 00000513 -fef594e3 +ff1714e3 00154513 00008067 fff00513 From 585f54d4f01d913475d83188f2c9128a35353d0d Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Mon, 13 Nov 2023 13:42:42 +0900 Subject: [PATCH 05/14] vnmsac --- .../resources/applications_vector/build.sh | 17 + .../resources/applications_vector/vnmsac.dump | 1098 +++++++++++++++++ .../applications_vector/vnmsac/vnmsac.c | 95 ++ .../applications_vector/vnmsac_data.hex | 180 +++ .../applications_vector/vnmsac_inst.hex | 677 ++++++++++ .../hajime/vectormodules/VectorCpuSpec.scala | 2 +- 6 files changed, 2068 insertions(+), 1 deletion(-) create mode 100644 src/main/resources/applications_vector/vnmsac.dump create mode 100644 src/main/resources/applications_vector/vnmsac/vnmsac.c create mode 100644 src/main/resources/applications_vector/vnmsac_data.hex create mode 100644 src/main/resources/applications_vector/vnmsac_inst.hex diff --git a/src/main/resources/applications_vector/build.sh b/src/main/resources/applications_vector/build.sh index 555714fe..9b2a59b9 100644 --- a/src/main/resources/applications_vector/build.sh +++ b/src/main/resources/applications_vector/build.sh @@ -450,4 +450,21 @@ hexdump -v -e '1/4 "%08x" "\n"' vmacc_text_startup.bin > vmacc_text_startup.temp cat vmacc_rodata.temp vmacc_rodata_str1_8.temp vmacc_sdata.temp > vmacc_data.hex cat vmacc_text_init.temp vmacc_text.temp vmacc_text_startup.temp > vmacc_inst.hex +riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vnmsac.riscv ./vnmsac/vnmsac.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld +riscv64-unknown-elf-objdump --disassemble-all vnmsac.riscv > vnmsac.dump +riscv64-unknown-elf-objcopy --dump-section .rodata=vnmsac_rodata.bin vnmsac.riscv +riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vnmsac_rodata_str1_8.bin vnmsac.riscv +riscv64-unknown-elf-objcopy --dump-section .sdata=vnmsac_sdata.bin vnmsac.riscv +riscv64-unknown-elf-objcopy --dump-section .text.init=vnmsac_text_init.bin vnmsac.riscv +riscv64-unknown-elf-objcopy --dump-section .text=vnmsac_text.bin vnmsac.riscv +riscv64-unknown-elf-objcopy --dump-section .text.startup=vnmsac_text_startup.bin vnmsac.riscv +hexdump -v -e '1/4 "%08x" "\n"' vnmsac_rodata.bin > vnmsac_rodata.temp +hexdump -v -e '1/4 "%08x" "\n"' vnmsac_rodata_str1_8.bin > vnmsac_rodata_str1_8.temp +hexdump -v -e '1/4 "%08x" "\n"' vnmsac_sdata.bin > vnmsac_sdata.temp +hexdump -v -e '1/4 "%08x" "\n"' vnmsac_text_init.bin > vnmsac_text_init.temp +hexdump -v -e '1/4 "%08x" "\n"' vnmsac_text.bin > vnmsac_text.temp +hexdump -v -e '1/4 "%08x" "\n"' vnmsac_text_startup.bin > vnmsac_text_startup.temp +cat vnmsac_rodata.temp vnmsac_rodata_str1_8.temp vnmsac_sdata.temp > vnmsac_data.hex +cat vnmsac_text_init.temp vnmsac_text.temp vnmsac_text_startup.temp > vnmsac_inst.hex + rm *.riscv *.bin *.temp \ No newline at end of file diff --git a/src/main/resources/applications_vector/vnmsac.dump b/src/main/resources/applications_vector/vnmsac.dump new file mode 100644 index 00000000..f064e387 --- /dev/null +++ b/src/main/resources/applications_vector/vnmsac.dump @@ -0,0 +1,1098 @@ + +vnmsac.riscv: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000000000000 <_start>: + 0: 00000093 li ra,0 + 4: 00000113 li sp,0 + 8: 00000193 li gp,0 + c: 00000213 li tp,0 + 10: 00000293 li t0,0 + 14: 00000313 li t1,0 + 18: 00000393 li t2,0 + 1c: 00000413 li s0,0 + 20: 00000493 li s1,0 + 24: 00000513 li a0,0 + 28: 00000593 li a1,0 + 2c: 00000613 li a2,0 + 30: 00000693 li a3,0 + 34: 00000713 li a4,0 + 38: 00000793 li a5,0 + 3c: 00000813 li a6,0 + 40: 00000893 li a7,0 + 44: 00000913 li s2,0 + 48: 00000993 li s3,0 + 4c: 00000a13 li s4,0 + 50: 00000a93 li s5,0 + 54: 00000b13 li s6,0 + 58: 00000b93 li s7,0 + 5c: 00000c13 li s8,0 + 60: 00000c93 li s9,0 + 64: 00000d13 li s10,0 + 68: 00000d93 li s11,0 + 6c: 00000e13 li t3,0 + 70: 00000e93 li t4,0 + 74: 00000f13 li t5,0 + 78: 00000f93 li t6,0 + 7c: 00000297 auipc t0,0x0 + 80: 03828293 add t0,t0,56 # b4 + 84: 30529073 csrw mtvec,t0 + 88: 00005197 auipc gp,0x5 + 8c: a4018193 add gp,gp,-1472 # 4ac8 <__global_pointer$> + 90: 10000217 auipc tp,0x10000 + 94: ff720213 add tp,tp,-9 # 10000087 <_end+0x3f> + 98: fc027213 and tp,tp,-64 + 9c: f1402573 csrr a0,mhartid + a0: 00100593 li a1,1 + a4: 00b57063 bgeu a0,a1,a4 <_start+0xa4> + a8: 00006137 lui sp,0x6 + ac: ff01011b addw sp,sp,-16 # 5ff0 <__global_pointer$+0x1528> + b0: 6580006f j 708 <_init> + +00000000000000b4 : + b4: ef010113 add sp,sp,-272 + b8: 00113423 sd ra,8(sp) + bc: 00213823 sd sp,16(sp) + c0: 00313c23 sd gp,24(sp) + c4: 02413023 sd tp,32(sp) + c8: 02513423 sd t0,40(sp) + cc: 02613823 sd t1,48(sp) + d0: 02713c23 sd t2,56(sp) + d4: 04813023 sd s0,64(sp) + d8: 04913423 sd s1,72(sp) + dc: 04a13823 sd a0,80(sp) + e0: 04b13c23 sd a1,88(sp) + e4: 06c13023 sd a2,96(sp) + e8: 06d13423 sd a3,104(sp) + ec: 06e13823 sd a4,112(sp) + f0: 06f13c23 sd a5,120(sp) + f4: 09013023 sd a6,128(sp) + f8: 09113423 sd a7,136(sp) + fc: 09213823 sd s2,144(sp) + 100: 09313c23 sd s3,152(sp) + 104: 0b413023 sd s4,160(sp) + 108: 0b513423 sd s5,168(sp) + 10c: 0b613823 sd s6,176(sp) + 110: 0b713c23 sd s7,184(sp) + 114: 0d813023 sd s8,192(sp) + 118: 0d913423 sd s9,200(sp) + 11c: 0da13823 sd s10,208(sp) + 120: 0db13c23 sd s11,216(sp) + 124: 0fc13023 sd t3,224(sp) + 128: 0fd13423 sd t4,232(sp) + 12c: 0fe13823 sd t5,240(sp) + 130: 0ff13c23 sd t6,248(sp) + 134: 34202573 csrr a0,mcause + 138: 341025f3 csrr a1,mepc + 13c: 00010613 mv a2,sp + 140: 2d0000ef jal 410 + 144: 34151073 csrw mepc,a0 + 148: 000022b7 lui t0,0x2 + 14c: 8002829b addw t0,t0,-2048 # 1800 + 150: 3002a073 csrs mstatus,t0 + 154: 00813083 ld ra,8(sp) + 158: 01013103 ld sp,16(sp) + 15c: 01813183 ld gp,24(sp) + 160: 02013203 ld tp,32(sp) + 164: 02813283 ld t0,40(sp) + 168: 03013303 ld t1,48(sp) + 16c: 03813383 ld t2,56(sp) + 170: 04013403 ld s0,64(sp) + 174: 04813483 ld s1,72(sp) + 178: 05013503 ld a0,80(sp) + 17c: 05813583 ld a1,88(sp) + 180: 06013603 ld a2,96(sp) + 184: 06813683 ld a3,104(sp) + 188: 07013703 ld a4,112(sp) + 18c: 07813783 ld a5,120(sp) + 190: 08013803 ld a6,128(sp) + 194: 08813883 ld a7,136(sp) + 198: 09013903 ld s2,144(sp) + 19c: 09813983 ld s3,152(sp) + 1a0: 0a013a03 ld s4,160(sp) + 1a4: 0a813a83 ld s5,168(sp) + 1a8: 0b013b03 ld s6,176(sp) + 1ac: 0b813b83 ld s7,184(sp) + 1b0: 0c013c03 ld s8,192(sp) + 1b4: 0c813c83 ld s9,200(sp) + 1b8: 0d013d03 ld s10,208(sp) + 1bc: 0d813d83 ld s11,216(sp) + 1c0: 0e013e03 ld t3,224(sp) + 1c4: 0e813e83 ld t4,232(sp) + 1c8: 0f013f03 ld t5,240(sp) + 1cc: 0f813f83 ld t6,248(sp) + 1d0: 11010113 add sp,sp,272 + 1d4: 30200073 mret + +Disassembly of section .text: + +00000000000001d8 : + 1d8: b0201073 csrw minstret,zero + 1dc: b0001073 csrw mcycle,zero + 1e0: 00008067 ret + +00000000000001e4 : + 1e4: 03000793 li a5,48 + 1e8: 00f58023 sb a5,0(a1) + 1ec: 07800793 li a5,120 + 1f0: 00f580a3 sb a5,1(a1) + 1f4: 00158813 add a6,a1,1 + 1f8: 00958793 add a5,a1,9 + 1fc: 00900613 li a2,9 + 200: 00f57713 and a4,a0,15 + 204: 03770693 add a3,a4,55 + 208: 00e66463 bltu a2,a4,210 + 20c: 03070693 add a3,a4,48 + 210: 00d78023 sb a3,0(a5) + 214: fff78793 add a5,a5,-1 + 218: 40455513 sra a0,a0,0x4 + 21c: fef812e3 bne a6,a5,200 + 220: 00058523 sb zero,10(a1) + 224: 00008067 ret + +0000000000000228 : + 228: 03000793 li a5,48 + 22c: 00f58023 sb a5,0(a1) + 230: 07800793 li a5,120 + 234: 00f580a3 sb a5,1(a1) + 238: 00158813 add a6,a1,1 + 23c: 01158793 add a5,a1,17 + 240: 00900613 li a2,9 + 244: 00f57713 and a4,a0,15 + 248: 03770693 add a3,a4,55 + 24c: 00e66463 bltu a2,a4,254 + 250: 03070693 add a3,a4,48 + 254: 00d78023 sb a3,0(a5) + 258: fff78793 add a5,a5,-1 + 25c: 40455513 sra a0,a0,0x4 + 260: fef812e3 bne a6,a5,244 + 264: 00058923 sb zero,18(a1) + 268: 00008067 ret + +000000000000026c : + 26c: 00054783 lbu a5,0(a0) + 270: 00078c63 beqz a5,288 + 274: 10000737 lui a4,0x10000 + 278: 00f70023 sb a5,0(a4) # 10000000 + 27c: 00154783 lbu a5,1(a0) + 280: 00150513 add a0,a0,1 + 284: fe079ae3 bnez a5,278 + 288: 00008067 ret + +000000000000028c : + 28c: fe010113 add sp,sp,-32 + 290: c0202673 rdinstret a2 + 294: c00025f3 rdcycle a1 + 298: 00004717 auipc a4,0x4 + 29c: eb870713 add a4,a4,-328 # 4150 + 2a0: 06300793 li a5,99 + 2a4: 100006b7 lui a3,0x10000 + 2a8: 00f68023 sb a5,0(a3) # 10000000 + 2ac: 00174783 lbu a5,1(a4) + 2b0: 00170713 add a4,a4,1 + 2b4: fe079ae3 bnez a5,2a8 + 2b8: ffff8737 lui a4,0xffff8 + 2bc: 83074713 xor a4,a4,-2000 + 2c0: 01910793 add a5,sp,25 + 2c4: 00e11423 sh a4,8(sp) + 2c8: 00910813 add a6,sp,9 + 2cc: 00078713 mv a4,a5 + 2d0: 00900893 li a7,9 + 2d4: 00f5f693 and a3,a1,15 + 2d8: 03768513 add a0,a3,55 + 2dc: 00d8e463 bltu a7,a3,2e4 + 2e0: 03068513 add a0,a3,48 + 2e4: 00a70023 sb a0,0(a4) # ffffffffffff8000 <_end+0xffffffffefff7fb8> + 2e8: fff70713 add a4,a4,-1 + 2ec: 4045d593 sra a1,a1,0x4 + 2f0: fee812e3 bne a6,a4,2d4 + 2f4: 00814703 lbu a4,8(sp) + 2f8: 00010d23 sb zero,26(sp) + 2fc: 00810693 add a3,sp,8 + 300: 100005b7 lui a1,0x10000 + 304: 00070a63 beqz a4,318 + 308: 00e58023 sb a4,0(a1) # 10000000 + 30c: 0016c703 lbu a4,1(a3) + 310: 00168693 add a3,a3,1 + 314: fe071ae3 bnez a4,308 + 318: 00004697 auipc a3,0x4 + 31c: e4068693 add a3,a3,-448 # 4158 + 320: 00a00713 li a4,10 + 324: 100005b7 lui a1,0x10000 + 328: 00e58023 sb a4,0(a1) # 10000000 + 32c: 0016c703 lbu a4,1(a3) + 330: 00168693 add a3,a3,1 + 334: fe071ae3 bnez a4,328 + 338: ffff8737 lui a4,0xffff8 + 33c: 83074713 xor a4,a4,-2000 + 340: 00060693 mv a3,a2 + 344: 00e11423 sh a4,8(sp) + 348: 00900593 li a1,9 + 34c: 00f6f713 and a4,a3,15 + 350: 03770613 add a2,a4,55 # ffffffffffff8037 <_end+0xffffffffefff7fef> + 354: 00e5e463 bltu a1,a4,35c + 358: 03070613 add a2,a4,48 + 35c: 00c78023 sb a2,0(a5) + 360: fff78793 add a5,a5,-1 + 364: 4046d693 sra a3,a3,0x4 + 368: fef812e3 bne a6,a5,34c + 36c: 00814783 lbu a5,8(sp) + 370: 00010d23 sb zero,26(sp) + 374: 00810713 add a4,sp,8 + 378: 100006b7 lui a3,0x10000 + 37c: 00078a63 beqz a5,390 + 380: 00f68023 sb a5,0(a3) # 10000000 + 384: 00174783 lbu a5,1(a4) + 388: 00170713 add a4,a4,1 + 38c: fe079ae3 bnez a5,380 + 390: 100007b7 lui a5,0x10000 + 394: 00a00713 li a4,10 + 398: 00e78023 sb a4,0(a5) # 10000000 + 39c: 02010113 add sp,sp,32 + 3a0: 00008067 ret + +00000000000003a4 : + 3a4: fe010113 add sp,sp,-32 + 3a8: 00813823 sd s0,16(sp) + 3ac: 00113c23 sd ra,24(sp) + 3b0: 00050413 mv s0,a0 + 3b4: 00004717 auipc a4,0x4 + 3b8: db470713 add a4,a4,-588 # 4168 + 3bc: 04500793 li a5,69 + 3c0: 100006b7 lui a3,0x10000 + 3c4: 00f68023 sb a5,0(a3) # 10000000 + 3c8: 00174783 lbu a5,1(a4) + 3cc: 00170713 add a4,a4,1 + 3d0: fe079ae3 bnez a5,3c4 + 3d4: 00010593 mv a1,sp + 3d8: 00040513 mv a0,s0 + 3dc: e09ff0ef jal 1e4 + 3e0: 00014703 lbu a4,0(sp) + 3e4: 00070e63 beqz a4,400 + 3e8: 00010793 mv a5,sp + 3ec: 100006b7 lui a3,0x10000 + 3f0: 00e68023 sb a4,0(a3) # 10000000 + 3f4: 0017c703 lbu a4,1(a5) + 3f8: 00178793 add a5,a5,1 + 3fc: fe071ae3 bnez a4,3f0 + 400: 00040513 mv a0,s0 + 404: 100007b7 lui a5,0x10000 + 408: 00078023 sb zero,0(a5) # 10000000 + 40c: 0000006f j 40c + +0000000000000410 : + 410: ffff87b7 lui a5,0xffff8 + 414: fd010113 add sp,sp,-48 + 418: 8307c793 xor a5,a5,-2000 + 41c: 00f11423 sh a5,8(sp) + 420: 02113423 sd ra,40(sp) + 424: 01910793 add a5,sp,25 + 428: 00910813 add a6,sp,9 + 42c: 00900613 li a2,9 + 430: 00f5f713 and a4,a1,15 + 434: 03770693 add a3,a4,55 + 438: 00e66463 bltu a2,a4,440 + 43c: 03070693 add a3,a4,48 + 440: 00d78023 sb a3,0(a5) # ffffffffffff8000 <_end+0xffffffffefff7fb8> + 444: fff78793 add a5,a5,-1 + 448: 4045d593 sra a1,a1,0x4 + 44c: ff0792e3 bne a5,a6,430 + 450: 00010d23 sb zero,26(sp) + 454: 00b00793 li a5,11 + 458: 02a7e063 bltu a5,a0,478 + 45c: 00004717 auipc a4,0x4 + 460: cc470713 add a4,a4,-828 # 4120 + 464: 00251513 sll a0,a0,0x2 + 468: 00e50533 add a0,a0,a4 + 46c: 00052783 lw a5,0(a0) + 470: 00e787b3 add a5,a5,a4 + 474: 00078067 jr a5 + 478: 00004717 auipc a4,0x4 + 47c: e1870713 add a4,a4,-488 # 4290 + 480: 05500793 li a5,85 + 484: 100006b7 lui a3,0x10000 + 488: 00f68023 sb a5,0(a3) # 10000000 + 48c: 00174783 lbu a5,1(a4) + 490: 00170713 add a4,a4,1 + 494: fe079ae3 bnez a5,488 + 498: 00814783 lbu a5,8(sp) + 49c: 00810713 add a4,sp,8 + 4a0: 100006b7 lui a3,0x10000 + 4a4: 00078a63 beqz a5,4b8 + 4a8: 00f68023 sb a5,0(a3) # 10000000 + 4ac: 00174783 lbu a5,1(a4) + 4b0: 00170713 add a4,a4,1 + 4b4: fe079ae3 bnez a5,4a8 + 4b8: 00004717 auipc a4,0x4 + 4bc: df870713 add a4,a4,-520 # 42b0 + 4c0: 00a00793 li a5,10 + 4c4: 100006b7 lui a3,0x10000 + 4c8: 00f68023 sb a5,0(a3) # 10000000 + 4cc: 00174783 lbu a5,1(a4) + 4d0: 00170713 add a4,a4,1 + 4d4: fe079ae3 bnez a5,4c8 + 4d8: fff00513 li a0,-1 + 4dc: ec9ff0ef jal 3a4 + 4e0: 00004717 auipc a4,0x4 + 4e4: c9870713 add a4,a4,-872 # 4178 + 4e8: 04900793 li a5,73 + 4ec: 100006b7 lui a3,0x10000 + 4f0: 00f68023 sb a5,0(a3) # 10000000 + 4f4: 00174783 lbu a5,1(a4) + 4f8: 00170713 add a4,a4,1 + 4fc: fe079ae3 bnez a5,4f0 + 500: 00814783 lbu a5,8(sp) + 504: 00810713 add a4,sp,8 + 508: 100006b7 lui a3,0x10000 + 50c: fc0786e3 beqz a5,4d8 + 510: 00f68023 sb a5,0(a3) # 10000000 + 514: 00174783 lbu a5,1(a4) + 518: 00170713 add a4,a4,1 + 51c: fe079ae3 bnez a5,510 + 520: fb9ff06f j 4d8 + 524: 00004717 auipc a4,0x4 + 528: c7c70713 add a4,a4,-900 # 41a0 + 52c: 04900793 li a5,73 + 530: 100006b7 lui a3,0x10000 + 534: 00f68023 sb a5,0(a3) # 10000000 + 538: 00174783 lbu a5,1(a4) + 53c: 00170713 add a4,a4,1 + 540: fe079ae3 bnez a5,534 + 544: 00814783 lbu a5,8(sp) + 548: f80788e3 beqz a5,4d8 + 54c: 00810713 add a4,sp,8 + 550: 100006b7 lui a3,0x10000 + 554: 00f68023 sb a5,0(a3) # 10000000 + 558: 00174783 lbu a5,1(a4) + 55c: 00170713 add a4,a4,1 + 560: fe079ae3 bnez a5,554 + 564: f75ff06f j 4d8 + 568: 00004717 auipc a4,0x4 + 56c: c6070713 add a4,a4,-928 # 41c8 + 570: 04900793 li a5,73 + 574: 100006b7 lui a3,0x10000 + 578: 00f68023 sb a5,0(a3) # 10000000 + 57c: 00174783 lbu a5,1(a4) + 580: 00170713 add a4,a4,1 + 584: fe079ae3 bnez a5,578 + 588: 00814783 lbu a5,8(sp) + 58c: f40786e3 beqz a5,4d8 + 590: 00810713 add a4,sp,8 + 594: 100006b7 lui a3,0x10000 + 598: 00f68023 sb a5,0(a3) # 10000000 + 59c: 00174783 lbu a5,1(a4) + 5a0: 00170713 add a4,a4,1 + 5a4: fe079ae3 bnez a5,598 + 5a8: f31ff06f j 4d8 + 5ac: 00004717 auipc a4,0x4 + 5b0: c3c70713 add a4,a4,-964 # 41e8 + 5b4: 04c00793 li a5,76 + 5b8: 100006b7 lui a3,0x10000 + 5bc: 00f68023 sb a5,0(a3) # 10000000 + 5c0: 00174783 lbu a5,1(a4) + 5c4: 00170713 add a4,a4,1 + 5c8: fe079ae3 bnez a5,5bc + 5cc: 00814783 lbu a5,8(sp) + 5d0: f00784e3 beqz a5,4d8 + 5d4: 00810713 add a4,sp,8 + 5d8: 100006b7 lui a3,0x10000 + 5dc: 00f68023 sb a5,0(a3) # 10000000 + 5e0: 00174783 lbu a5,1(a4) + 5e4: 00170713 add a4,a4,1 + 5e8: fe079ae3 bnez a5,5dc + 5ec: eedff06f j 4d8 + 5f0: 00004717 auipc a4,0x4 + 5f4: c1870713 add a4,a4,-1000 # 4208 + 5f8: 04c00793 li a5,76 + 5fc: 100006b7 lui a3,0x10000 + 600: 00f68023 sb a5,0(a3) # 10000000 + 604: 00174783 lbu a5,1(a4) + 608: 00170713 add a4,a4,1 + 60c: fe079ae3 bnez a5,600 + 610: 00814783 lbu a5,8(sp) + 614: ec0782e3 beqz a5,4d8 + 618: 00810713 add a4,sp,8 + 61c: 100006b7 lui a3,0x10000 + 620: 00f68023 sb a5,0(a3) # 10000000 + 624: 00174783 lbu a5,1(a4) + 628: 00170713 add a4,a4,1 + 62c: fe079ae3 bnez a5,620 + 630: ea9ff06f j 4d8 + 634: 00004717 auipc a4,0x4 + 638: bf470713 add a4,a4,-1036 # 4228 + 63c: 05300793 li a5,83 + 640: 100006b7 lui a3,0x10000 + 644: 00f68023 sb a5,0(a3) # 10000000 + 648: 00174783 lbu a5,1(a4) + 64c: 00170713 add a4,a4,1 + 650: fe079ae3 bnez a5,644 + 654: 00814783 lbu a5,8(sp) + 658: e80780e3 beqz a5,4d8 + 65c: 00810713 add a4,sp,8 + 660: 100006b7 lui a3,0x10000 + 664: 00f68023 sb a5,0(a3) # 10000000 + 668: 00174783 lbu a5,1(a4) + 66c: 00170713 add a4,a4,1 + 670: fe079ae3 bnez a5,664 + 674: e65ff06f j 4d8 + 678: 00004717 auipc a4,0x4 + 67c: bd870713 add a4,a4,-1064 # 4250 + 680: 05300793 li a5,83 + 684: 100006b7 lui a3,0x10000 + 688: 00f68023 sb a5,0(a3) # 10000000 + 68c: 00174783 lbu a5,1(a4) + 690: 00170713 add a4,a4,1 + 694: fe079ae3 bnez a5,688 + 698: 00814783 lbu a5,8(sp) + 69c: e2078ee3 beqz a5,4d8 + 6a0: 00810713 add a4,sp,8 + 6a4: 100006b7 lui a3,0x10000 + 6a8: 00f68023 sb a5,0(a3) # 10000000 + 6ac: 00174783 lbu a5,1(a4) + 6b0: 00170713 add a4,a4,1 + 6b4: fe079ae3 bnez a5,6a8 + 6b8: e21ff06f j 4d8 + 6bc: 00004717 auipc a4,0x4 + 6c0: bb470713 add a4,a4,-1100 # 4270 + 6c4: 04500793 li a5,69 + 6c8: 100006b7 lui a3,0x10000 + 6cc: 00f68023 sb a5,0(a3) # 10000000 + 6d0: 00174783 lbu a5,1(a4) + 6d4: 00170713 add a4,a4,1 + 6d8: fe079ae3 bnez a5,6cc + 6dc: 00814783 lbu a5,8(sp) + 6e0: de078ce3 beqz a5,4d8 + 6e4: 00810713 add a4,sp,8 + 6e8: 100006b7 lui a3,0x10000 + 6ec: 00f68023 sb a5,0(a3) # 10000000 + 6f0: 00174783 lbu a5,1(a4) + 6f4: 00170713 add a4,a4,1 + 6f8: fe079ae3 bnez a5,6ec + 6fc: dddff06f j 4d8 + +0000000000000700 : + 700: 00051063 bnez a0,700 + 704: 00008067 ret + +0000000000000708 <_init>: + 708: ff010113 add sp,sp,-16 + 70c: 00000593 li a1,0 + 710: 00000513 li a0,0 + 714: 00113423 sd ra,8(sp) + 718: 1d8000ef jal 8f0
+ 71c: c89ff0ef jal 3a4 + +0000000000000720 : + 720: 00b567b3 or a5,a0,a1 + 724: 00c7e7b3 or a5,a5,a2 + 728: 0077f793 and a5,a5,7 + 72c: 00c50833 add a6,a0,a2 + 730: 02078463 beqz a5,758 + 734: 00c58633 add a2,a1,a2 + 738: 00050793 mv a5,a0 + 73c: 0b057663 bgeu a0,a6,7e8 + 740: 0005c703 lbu a4,0(a1) + 744: 00158593 add a1,a1,1 + 748: 00178793 add a5,a5,1 + 74c: fee78fa3 sb a4,-1(a5) + 750: fec598e3 bne a1,a2,740 + 754: 00008067 ret + 758: 04050693 add a3,a0,64 + 75c: 0906f863 bgeu a3,a6,7ec + 760: 00058713 mv a4,a1 + 764: 00068793 mv a5,a3 + 768: 00073383 ld t2,0(a4) + 76c: 00873283 ld t0,8(a4) + 770: 01073f83 ld t6,16(a4) + 774: 01873f03 ld t5,24(a4) + 778: 02073e83 ld t4,32(a4) + 77c: 02873e03 ld t3,40(a4) + 780: 03073303 ld t1,48(a4) + 784: 03873883 ld a7,56(a4) + 788: 04078793 add a5,a5,64 + 78c: f877b023 sd t2,-128(a5) + 790: f857b423 sd t0,-120(a5) + 794: f9f7b823 sd t6,-112(a5) + 798: f9e7bc23 sd t5,-104(a5) + 79c: fbd7b023 sd t4,-96(a5) + 7a0: fbc7b423 sd t3,-88(a5) + 7a4: fa67b823 sd t1,-80(a5) + 7a8: fb17bc23 sd a7,-72(a5) + 7ac: 04070713 add a4,a4,64 + 7b0: fb07ece3 bltu a5,a6,768 + 7b4: fbf60613 add a2,a2,-65 + 7b8: fc067793 and a5,a2,-64 + 7bc: 04078793 add a5,a5,64 + 7c0: fc067613 and a2,a2,-64 + 7c4: 00f585b3 add a1,a1,a5 + 7c8: 00c687b3 add a5,a3,a2 + 7cc: f907f4e3 bgeu a5,a6,754 + 7d0: 0005b703 ld a4,0(a1) + 7d4: 00878793 add a5,a5,8 + 7d8: 00858593 add a1,a1,8 + 7dc: fee7bc23 sd a4,-8(a5) + 7e0: ff07e8e3 bltu a5,a6,7d0 + 7e4: 00008067 ret + 7e8: 00008067 ret + 7ec: 00050793 mv a5,a0 + 7f0: fddff06f j 7cc + +00000000000007f4 : + 7f4: 00c567b3 or a5,a0,a2 + 7f8: 0077f793 and a5,a5,7 + 7fc: 00c50633 add a2,a0,a2 + 800: 0ff5f713 zext.b a4,a1 + 804: 00078e63 beqz a5,820 + 808: 00050793 mv a5,a0 + 80c: 02c57c63 bgeu a0,a2,844 + 810: 00178793 add a5,a5,1 + 814: fee78fa3 sb a4,-1(a5) + 818: fef61ce3 bne a2,a5,810 + 81c: 00008067 ret + 820: 00004797 auipc a5,0x4 + 824: aa87b783 ld a5,-1368(a5) # 42c8 + 828: 02f70733 mul a4,a4,a5 + 82c: fec578e3 bgeu a0,a2,81c + 830: 00050793 mv a5,a0 + 834: 00878793 add a5,a5,8 + 838: fee7bc23 sd a4,-8(a5) + 83c: fec7ece3 bltu a5,a2,834 + 840: 00008067 ret + 844: 00008067 ret + +0000000000000848 : + 848: 00054783 lbu a5,0(a0) + 84c: 00078e63 beqz a5,868 + 850: 00050793 mv a5,a0 + 854: 0017c703 lbu a4,1(a5) + 858: 00178793 add a5,a5,1 + 85c: fe071ce3 bnez a4,854 + 860: 40a78533 sub a0,a5,a0 + 864: 00008067 ret + 868: 00000513 li a0,0 + 86c: 00008067 ret + +0000000000000870 : + 870: 00b506b3 add a3,a0,a1 + 874: 00050793 mv a5,a0 + 878: 00059863 bnez a1,888 + 87c: 0240006f j 8a0 + 880: 00178793 add a5,a5,1 + 884: 00f68a63 beq a3,a5,898 + 888: 0007c703 lbu a4,0(a5) + 88c: fe071ae3 bnez a4,880 + 890: 40a78533 sub a0,a5,a0 + 894: 00008067 ret + 898: 40a68533 sub a0,a3,a0 + 89c: 00008067 ret + 8a0: 00000513 li a0,0 + 8a4: 00008067 ret + +00000000000008a8 : + 8a8: 00054783 lbu a5,0(a0) + 8ac: 00158593 add a1,a1,1 + 8b0: 00150513 add a0,a0,1 + 8b4: fff5c703 lbu a4,-1(a1) + 8b8: 00078a63 beqz a5,8cc + 8bc: fee786e3 beq a5,a4,8a8 + 8c0: 0007851b sext.w a0,a5 + 8c4: 40e5053b subw a0,a0,a4 + 8c8: 00008067 ret + 8cc: 00000513 li a0,0 + 8d0: ff5ff06f j 8c4 + +00000000000008d4 : + 8d4: 00050793 mv a5,a0 + 8d8: 0005c703 lbu a4,0(a1) + 8dc: 00178793 add a5,a5,1 + 8e0: 00158593 add a1,a1,1 + 8e4: fee78fa3 sb a4,-1(a5) + 8e8: fe0718e3 bnez a4,8d8 + 8ec: 00008067 ret + +Disassembly of section .text.startup: + +00000000000008f0
: + 8f0: 00004517 auipc a0,0x4 + 8f4: 9e050513 add a0,a0,-1568 # 42d0 + 8f8: 00003597 auipc a1,0x3 + 8fc: 70858593 add a1,a1,1800 # 4000 + 900: 00003617 auipc a2,0x3 + 904: 76060613 add a2,a2,1888 # 4060 + 908: 00003697 auipc a3,0x3 + 90c: 7b868693 add a3,a3,1976 # 40c0 + 910: 02900713 li a4,41 + 914: 0c877857 vsetvli a6,a4,e16,m1,ta,ma + 918: 0008079b sext.w a5,a6 + 91c: 0206d507 vle16.v v10,(a3) + 920: 02065587 vle16.v v11,(a2) + 924: 0205d607 vle16.v v12,(a1) + 928: beb52657 vnmsac.vv v12,v10,v11 + 92c: 02055627 vse16.v v12,(a0) + 930: 00179793 sll a5,a5,0x1 + 934: 4107073b subw a4,a4,a6 + 938: 00f686b3 add a3,a3,a5 + 93c: 00f60633 add a2,a2,a5 + 940: 00f585b3 add a1,a1,a5 + 944: 00f50533 add a0,a0,a5 + 948: fc0716e3 bnez a4,914 + 94c: 00003697 auipc a3,0x3 + 950: 77468693 add a3,a3,1908 # 40c0 + 954: 00003597 auipc a1,0x3 + 958: 70c58593 add a1,a1,1804 # 4060 + 95c: 86818813 add a6,gp,-1944 # 4330 + 960: 00003797 auipc a5,0x3 + 964: 6a078793 add a5,a5,1696 # 4000 + 968: 00003e97 auipc t4,0x3 + 96c: 6eae8e93 add t4,t4,1770 # 4052 + 970: 00080313 mv t1,a6 + 974: 00058893 mv a7,a1 + 978: 00068513 mv a0,a3 + 97c: 00055603 lhu a2,0(a0) + 980: 0008de03 lhu t3,0(a7) + 984: 0007d703 lhu a4,0(a5) + 988: 00230313 add t1,t1,2 + 98c: 03c6063b mulw a2,a2,t3 + 990: 00278793 add a5,a5,2 + 994: 00250513 add a0,a0,2 + 998: 00288893 add a7,a7,2 + 99c: 40c7073b subw a4,a4,a2 + 9a0: fee31f23 sh a4,-2(t1) + 9a4: fdd79ce3 bne a5,t4,97c + 9a8: 00004717 auipc a4,0x4 + 9ac: 92870713 add a4,a4,-1752 # 42d0 + 9b0: 85a18893 add a7,gp,-1958 # 4322 + 9b4: 86818613 add a2,gp,-1944 # 4330 + 9b8: 00070793 mv a5,a4 + 9bc: 00100513 li a0,1 + 9c0: 00061e03 lh t3,0(a2) + 9c4: 00079303 lh t1,0(a5) + 9c8: 00260613 add a2,a2,2 + 9cc: 00278793 add a5,a5,2 + 9d0: 006e0463 beq t3,t1,9d8 + 9d4: 00000513 li a0,0 + 9d8: ff1794e3 bne a5,a7,9c0 + 9dc: 00002fb7 lui t6,0x2 + 9e0: 00004e97 auipc t4,0x4 + 9e4: 8f0e8e93 add t4,t4,-1808 # 42d0 + 9e8: 00003e17 auipc t3,0x3 + 9ec: 678e0e13 add t3,t3,1656 # 4060 + 9f0: 00003317 auipc t1,0x3 + 9f4: 6d030313 add t1,t1,1744 # 40c0 + 9f8: 02900613 li a2,41 + 9fc: 919f8f9b addw t6,t6,-1767 # 1919 + a00: 0c867f57 vsetvli t5,a2,e16,m1,ta,ma + a04: 000f079b sext.w a5,t5 + a08: 02035507 vle16.v v10,(t1) + a0c: 020e5587 vle16.v v11,(t3) + a10: beafe5d7 vnmsac.vx v11,t6,v10 + a14: 020ed5a7 vse16.v v11,(t4) + a18: 00179793 sll a5,a5,0x1 + a1c: 41e6063b subw a2,a2,t5 + a20: 00f30333 add t1,t1,a5 + a24: 00fe0e33 add t3,t3,a5 + a28: 00fe8eb3 add t4,t4,a5 + a2c: fc061ae3 bnez a2,a00 + a30: ffffee37 lui t3,0xffffe + a34: 00003e97 auipc t4,0x3 + a38: 6dee8e93 add t4,t4,1758 # 4112 + a3c: 86818613 add a2,gp,-1944 # 4330 + a40: 6e7e0e1b addw t3,t3,1767 # ffffffffffffe6e7 <_end+0xffffffffefffe69f> + a44: 0006d783 lhu a5,0(a3) + a48: 0005d303 lhu t1,0(a1) + a4c: 00260613 add a2,a2,2 + a50: 02fe07bb mulw a5,t3,a5 + a54: 00268693 add a3,a3,2 + a58: 00258593 add a1,a1,2 + a5c: 006787bb addw a5,a5,t1 + a60: fef61f23 sh a5,-2(a2) + a64: fede90e3 bne t4,a3,a44 + a68: 00071683 lh a3,0(a4) + a6c: 00081783 lh a5,0(a6) + a70: 00270713 add a4,a4,2 + a74: 00280813 add a6,a6,2 + a78: 00f68463 beq a3,a5,a80 + a7c: 00000513 li a0,0 + a80: ff1714e3 bne a4,a7,a68 + a84: 00154513 xor a0,a0,1 + a88: 00008067 ret + a8c: fff00513 li a0,-1 + a90: 00008067 ret + +Disassembly of section .rodata: + +0000000000004000 : + 4000: de7f6f4f .4byte 0xde7f6f4f + 4004: 6560 vmsge.vx v10,v0,zero,v0.t + 4006: 7f28 .2byte 0x7f28 + 4008: d47bad0b .4byte 0xd47bad0b + 400c: 3561 vmsge.vx v10,v0,zero,v0.t + 400e: 4922134f .4byte 0x4922134f + 4012: f869 .2byte 0xf869 + 4014: e2be .2byte 0xe2be + 4016: 66655b7f 2fd0f487 .byte 0x7f, 0x5b, 0x65, 0x66, 0x87, 0xf4, 0xd0, 0x2f, 0x85, 0xa2, 0xf8, 0x25, 0xb9, 0x7f, 0x66, 0x6d, 0x55, 0xc4, 0xdb, 0x5f + 401e: 25f8a285 6d667fb9 + 4026: 5fdbc455 + 402a: 9789 .2byte 0x9789 + 402c: eb716457 vwmulsu.vx v8,v23,sp + 4030: 7b54 .2byte 0x7b54 + 4032: def2 .2byte 0xdef2 + 4034: 4301 vmsge.vx v6,v0,zero,v0.t + 4036: fd67d5cf .4byte 0xfd67d5cf + 403a: 71b8 .2byte 0x71b8 + 403c: 7b50 .2byte 0x7b50 + 403e: 3ed7a5a3 sw a3,1003(a5) + 4042: 7231 .2byte 0x7231 + 4044: 1c16 .2byte 0x1c16 + 4046: a8c5c137 lui sp,0xa8c5c + 404a: 8948 .2byte 0x8948 + 404c: 4769 .2byte 0x4769 + 404e: f820 vmsge.vx v16,v0,ra,v0.t + 4050: 72589fb7 lui t6,0x72589 + 4054: 4c0c .2byte 0x4c0c + 4056: 0a9e .2byte 0xa9e + 4058: 1240 vmsge.vx v4,v0,zero,v0.t + 405a: 2f0a .2byte 0x2f0a + 405c: 20f2 .2byte 0x20f2 + 405e: 920a .2byte 0x920a + +0000000000004060 : + 4060: 7729 .2byte 0x7729 + 4062: 4ec6 .2byte 0x4ec6 + 4064: 160e .2byte 0x160e + 4066: aa00 vmsge.vx v20,v0,ra,v0.t + 4068: b0d5 .2byte 0xb0d5 + 406a: be1a073b .4byte 0xbe1a073b + 406e: c35e .2byte 0xc35e + 4070: e6b2 .2byte 0xe6b2 + 4072: 6f98 .2byte 0x6f98 + 4074: de929e9b .4byte 0xde929e9b + 4078: 72e270db .4byte 0x72e270db + 407c: e9d8 .2byte 0xe9d8 + 407e: 9bf6 .2byte 0x9bf6 + 4080: 44dc .2byte 0x44dc + 4082: f1b6bdef jal s11,fffffffffff6ff9c <_end+0xffffffffeff6ff54> + 4086: 8df9 .2byte 0x8df9 + 4088: b8ba .2byte 0xb8ba + 408a: 1e11 .2byte 0x1e11 + 408c: 4132 .2byte 0x4132 + 408e: d955 .2byte 0xd955 + 4090: 1711 .2byte 0x1711 + 4092: 9a81 vmsge.vx v21,v0,ra,v0.t + 4094: 645f 190b fe67 .byte 0x5f, 0x64, 0x0b, 0x19, 0x67, 0xfe + 409a: 0438 .2byte 0x438 + 409c: 2255 .2byte 0x2255 + 409e: c2dea2b3 .4byte 0xc2dea2b3 + 40a2: 69ac .2byte 0x69ac + 40a4: dd7d .2byte 0xdd7d + 40a6: d433ccc3 vmsge.vx v25,v3,t2,v0.t + 40aa: 30c4 .2byte 0x30c4 + 40ac: 7639 .2byte 0x7639 + 40ae: ae61 vmsge.vx v28,v0,ra,v0.t + 40b0: 717f .2byte 0x717f + 40b2: a7bc8f9b addw t6,s9,-1413 + 40b6: 3df5 .2byte 0x3df5 + 40b8: 6b708b4f .4byte 0x6b708b4f + 40bc: 55c5 .2byte 0x55c5 + 40be: c9da .2byte 0xc9da + +00000000000040c0 : + 40c0: 968d .2byte 0x968d + 40c2: d593c97b .4byte 0xd593c97b + 40c6: 631e .2byte 0x631e + 40c8: b990 .2byte 0xb990 + 40ca: 5cbaad63 vmsge.vx v26,v11,s5,v0.t + 40ce: 5fe4 .2byte 0x5fe4 + 40d0: 9232 .2byte 0x9232 + 40d2: aa6a .2byte 0xaa6a + 40d4: 4186 .2byte 0x4186 + 40d6: 4d80d87b .4byte 0x4d80d87b + 40da: 31a7d16f jal sp,813f4 <__global_pointer$+0x7c92c> + 40de: a180 vmsge.vx v3,v0,ra,v0.t + 40e0: 6bc2 vmsge.vx v23,v0,zero,v0.t + 40e2: b1ac .2byte 0xb1ac + 40e4: b049 .2byte 0xb049 + 40e6: 3552 .2byte 0x3552 + 40e8: c256 .2byte 0xc256 + 40ea: 5275 .2byte 0x5275 + 40ec: 7cfe .2byte 0x7cfe + 40ee: 496c .2byte 0x496c + 40f0: d4a6 .2byte 0xd4a6 + 40f2: f964 .2byte 0xf964 + 40f4: 8da3049b addw s1,t1,-1830 + 40f8: bb15 .2byte 0xbb15 + 40fa: 975c .2byte 0x975c + 40fc: c4ad .2byte 0xc4ad + 40fe: cdac .2byte 0xcdac + 4100: add7e053 .4byte 0xadd7e053 + 4104: 529c8f93 add t6,s9,1321 + 4108: 969c .2byte 0x969c + 410a: 601d .2byte 0x601d + 410c: 14ce39a7 .4byte 0x14ce39a7 + 4110: 7f38 .2byte 0x7f38 + 4112: 3884 .2byte 0x3884 + 4114: 8d44 .2byte 0x8d44 + 4116: f1809d8b .4byte 0xf1809d8b + 411a: 2f01 vmsge.vx v30,v0,zero,v0.t + 411c: ca10 .2byte 0xca10 + 411e: 3bc0 vmsge.vx v23,v0,zero,v0.t + 4120: c3c0 vmsge.vx v7,v0,ra,v0.t + 4122: ffff .2byte 0xffff + 4124: c404 .2byte 0xc404 + 4126: ffff .2byte 0xffff + 4128: c448 .2byte 0xc448 + 412a: ffff .2byte 0xffff + 412c: c358 .2byte 0xc358 + 412e: ffff .2byte 0xffff + 4130: c48c .2byte 0xc48c + 4132: ffff .2byte 0xffff + 4134: c4d0 .2byte 0xc4d0 + 4136: ffff .2byte 0xffff + 4138: c514 .2byte 0xc514 + 413a: ffff .2byte 0xffff + 413c: c558 .2byte 0xc558 + 413e: ffff .2byte 0xffff + 4140: c358 .2byte 0xc358 + 4142: ffff .2byte 0xffff + 4144: c358 .2byte 0xc358 + 4146: ffff .2byte 0xffff + 4148: c358 .2byte 0xc358 + 414a: ffff .2byte 0xffff + 414c: c59c .2byte 0xc59c + 414e: ffff .2byte 0xffff + +Disassembly of section .rodata.str1.8: + +0000000000004150 <.rodata.str1.8>: + 4150: 6c637963 bgeu t1,t1,4822 <_tbss_end+0x492> + 4154: 3a65 .2byte 0x3a65 + 4156: 0020 vmsge.vx v0,v0,zero,v0.t + 4158: 690a .2byte 0x690a + 415a: 736e .2byte 0x736e + 415c: 7274 .2byte 0x7274 + 415e: 7465 .2byte 0x7465 + 4160: 203a .2byte 0x203a + 4162: 0000 vmsge.vx v0,v0,zero,v0.t + 4164: 0000 vmsge.vx v0,v0,zero,v0.t + 4166: 0000 vmsge.vx v0,v0,zero,v0.t + 4168: 7845 .2byte 0x7845 + 416a: 7469 .2byte 0x7469 + 416c: 6320 vmsge.vx v6,v0,zero,v0.t + 416e: 3a65646f jal s0,5a514 <__global_pointer$+0x55a4c> + 4172: 0020 vmsge.vx v0,v0,zero,v0.t + 4174: 0000 vmsge.vx v0,v0,zero,v0.t + 4176: 0000 vmsge.vx v0,v0,zero,v0.t + 4178: 4e49 .2byte 0x4e49 + 417a: 55525453 .4byte 0x55525453 + 417e: 4f495443 vmsge.vx v8,v20,s2 + 4182: 204e .2byte 0x204e + 4184: 4441 vmsge.vx v8,v0,zero,v0.t + 4186: 5244 .2byte 0x5244 + 4188: 5345 .2byte 0x5345 + 418a: 494d2053 .4byte 0x494d2053 + 418e: 494c4153 .4byte 0x494c4153 + 4192: 44454e47 .4byte 0x44454e47 + 4196: 6120 vmsge.vx v2,v0,zero,v0.t + 4198: 2074 .2byte 0x2074 + 419a: 4350 .2byte 0x4350 + 419c: 203a .2byte 0x203a + 419e: 0000 vmsge.vx v0,v0,zero,v0.t + 41a0: 4e49 .2byte 0x4e49 + 41a2: 55525453 .4byte 0x55525453 + 41a6: 4f495443 vmsge.vx v8,v20,s2 + 41aa: 204e .2byte 0x204e + 41ac: 4341 vmsge.vx v6,v0,zero,v0.t + 41ae: 53534543 vmsge.vx v10,v21,t1 + 41b2: 4620 vmsge.vx v12,v0,zero,v0.t + 41b4: 5541 vmsge.vx v10,v0,zero,v0.t + 41b6: 544c .2byte 0x544c + 41b8: 6120 vmsge.vx v2,v0,zero,v0.t + 41ba: 2074 .2byte 0x2074 + 41bc: 4350 .2byte 0x4350 + 41be: 203a .2byte 0x203a + ... + 41c8: 4c49 .2byte 0x4c49 + 41ca: 454c .2byte 0x454c + 41cc: 204c4147 .4byte 0x204c4147 + 41d0: 4e49 .2byte 0x4e49 + 41d2: 55525453 .4byte 0x55525453 + 41d6: 4f495443 vmsge.vx v8,v20,s2 + 41da: 204e .2byte 0x204e + 41dc: 7461 vmsge.vx v8,v0,zero,v0.t + 41de: 5020 vmsge.vx v0,v0,zero,v0.t + 41e0: 00203a43 vmsge.vx v20,v2,zero,v0.t + 41e4: 0000 vmsge.vx v0,v0,zero,v0.t + 41e6: 0000 vmsge.vx v0,v0,zero,v0.t + 41e8: 4f4c .2byte 0x4f4c + 41ea: 4441 vmsge.vx v8,v0,zero,v0.t + 41ec: 4120 vmsge.vx v2,v0,zero,v0.t + 41ee: 4444 .2byte 0x4444 + 41f0: 4552 .2byte 0x4552 + 41f2: 4d205353 .4byte 0x4d205353 + 41f6: 5349 .2byte 0x5349 + 41f8: 4c41 vmsge.vx v24,v0,zero,v0.t + 41fa: 4749 .2byte 0x4749 + 41fc: 454e .2byte 0x454e + 41fe: 2044 .2byte 0x2044 + 4200: 7461 vmsge.vx v8,v0,zero,v0.t + 4202: 5020 vmsge.vx v0,v0,zero,v0.t + 4204: 00203a43 vmsge.vx v20,v2,zero,v0.t + 4208: 4f4c .2byte 0x4f4c + 420a: 4441 vmsge.vx v8,v0,zero,v0.t + 420c: 4120 vmsge.vx v2,v0,zero,v0.t + 420e: 53454343 vmsge.vx v6,v20,a0 + 4212: 41462053 .4byte 0x41462053 + 4216: 4c55 .2byte 0x4c55 + 4218: 2054 .2byte 0x2054 + 421a: 7461 vmsge.vx v8,v0,zero,v0.t + 421c: 5020 vmsge.vx v0,v0,zero,v0.t + 421e: 00203a43 vmsge.vx v20,v2,zero,v0.t + 4222: 0000 vmsge.vx v0,v0,zero,v0.t + 4224: 0000 vmsge.vx v0,v0,zero,v0.t + 4226: 0000 vmsge.vx v0,v0,zero,v0.t + 4228: 524f5453 .4byte 0x524f5453 + 422c: 2045 .2byte 0x2045 + 422e: 4441 vmsge.vx v8,v0,zero,v0.t + 4230: 5244 .2byte 0x5244 + 4232: 5345 .2byte 0x5345 + 4234: 494d2053 .4byte 0x494d2053 + 4238: 494c4153 .4byte 0x494c4153 + 423c: 44454e47 .4byte 0x44454e47 + 4240: 6120 vmsge.vx v2,v0,zero,v0.t + 4242: 2074 .2byte 0x2074 + 4244: 4350 .2byte 0x4350 + 4246: 203a .2byte 0x203a + ... + 4250: 524f5453 .4byte 0x524f5453 + 4254: 2045 .2byte 0x2045 + 4256: 4341 vmsge.vx v6,v0,zero,v0.t + 4258: 53534543 vmsge.vx v10,v21,t1 + 425c: 4620 vmsge.vx v12,v0,zero,v0.t + 425e: 5541 vmsge.vx v10,v0,zero,v0.t + 4260: 544c .2byte 0x544c + 4262: 6120 vmsge.vx v2,v0,zero,v0.t + 4264: 2074 .2byte 0x2074 + 4266: 4350 .2byte 0x4350 + 4268: 203a .2byte 0x203a + 426a: 0000 vmsge.vx v0,v0,zero,v0.t + 426c: 0000 vmsge.vx v0,v0,zero,v0.t + 426e: 0000 vmsge.vx v0,v0,zero,v0.t + 4270: 4345 .2byte 0x4345 + 4272: 4c41 vmsge.vx v24,v0,zero,v0.t + 4274: 204c .2byte 0x204c + 4276: 5246 .2byte 0x5246 + 4278: 4d204d4f .4byte 0x4d204d4f + 427c: 4d2d .2byte 0x4d2d + 427e: 2045444f .4byte 0x2045444f + 4282: 7461 vmsge.vx v8,v0,zero,v0.t + 4284: 5020 vmsge.vx v0,v0,zero,v0.t + 4286: 00203a43 vmsge.vx v20,v2,zero,v0.t + 428a: 0000 vmsge.vx v0,v0,zero,v0.t + 428c: 0000 vmsge.vx v0,v0,zero,v0.t + 428e: 0000 vmsge.vx v0,v0,zero,v0.t + 4290: 4e55 .2byte 0x4e55 + 4292: 574f4e4b .4byte 0x574f4e4b + 4296: 204e .2byte 0x204e + 4298: 5845 .2byte 0x5845 + 429a: 54504543 vmsge.vx v10,v5,zero,v0.t + 429e: 4f49 .2byte 0x4f49 + 42a0: 204e .2byte 0x204e + 42a2: 7461 vmsge.vx v8,v0,zero,v0.t + 42a4: 5020 vmsge.vx v0,v0,zero,v0.t + 42a6: 00203a43 vmsge.vx v20,v2,zero,v0.t + 42aa: 0000 vmsge.vx v0,v0,zero,v0.t + 42ac: 0000 vmsge.vx v0,v0,zero,v0.t + 42ae: 0000 vmsge.vx v0,v0,zero,v0.t + 42b0: 430a .2byte 0x430a + 42b2: 4548 .2byte 0x4548 + 42b4: 4d204b43 vmsge.vx v22,v18,zero,v0.t + 42b8: 53554143 vmsge.vx v2,v21,a0 + 42bc: 2045 .2byte 0x2045 + 42be: 6e69 .2byte 0x6e69 + 42c0: 5220 vmsge.vx v4,v0,zero,v0.t + 42c2: 4c54 .2byte 0x4c54 + ... + +Disassembly of section .sdata: + +00000000000042c8 <__global_pointer$-0x800>: + 42c8: 0101 vmsge.vx v2,v0,zero,v0.t + 42ca: 0101 vmsge.vx v2,v0,zero,v0.t + 42cc: 0101 vmsge.vx v2,v0,zero,v0.t + 42ce: 0101 vmsge.vx v2,v0,zero,v0.t + +Disassembly of section .bss: + +00000000000042d0 : + ... + +0000000000004330 : + ... + +Disassembly of section .tohost: + +0000000010000000 : + ... + +0000000010000040 : + ... + +Disassembly of section .comment: + +0000000000000000 <.comment>: + 0: 3a434347 .4byte 0x3a434347 + 4: 2820 vmsge.vx v16,v0,zero,v0.t + 6: 65653267 .4byte 0x65653267 + a: 6535 .2byte 0x6535 + c: 3334 .2byte 0x3334 + e: 3030 .2byte 0x3030 + 10: 3831 .2byte 0x3831 + 12: 2029 .2byte 0x2029 + 14: 3231 .2byte 0x3231 + 16: 322e .2byte 0x322e + 18: 302e .2byte 0x302e + ... + +Disassembly of section .riscv.attributes: + +0000000000000000 <.riscv.attributes>: + 0: 5e41 vmsge.vx v28,v0,zero,v0.t + 2: 0000 vmsge.vx v0,v0,zero,v0.t + 4: 7200 vmsge.vx v4,v0,zero,v0.t + 6: 7369 .2byte 0x7369 + 8: 01007663 bgeu zero,a6,14 <_start+0x14> + c: 0054 .2byte 0x54 + e: 0000 vmsge.vx v0,v0,zero,v0.t + 10: 1004 .2byte 0x1004 + 12: 7205 .2byte 0x7205 + 14: 3676 .2byte 0x3676 + 16: 6934 .2byte 0x6934 + 18: 7032 .2byte 0x7032 + 1a: 5f31 .2byte 0x5f31 + 1c: 326d .2byte 0x326d + 1e: 3070 .2byte 0x3070 + 20: 7a5f 6369 7273 .byte 0x5f, 0x7a, 0x69, 0x63, 0x73, 0x72 + 26: 7032 .2byte 0x7032 + 28: 5f30 .2byte 0x5f30 + 2a: 6d7a .2byte 0x6d7a + 2c: 756d .2byte 0x756d + 2e: 316c .2byte 0x316c + 30: 3070 .2byte 0x3070 + 32: 7a5f 6576 3233 .byte 0x5f, 0x7a, 0x76, 0x65, 0x33, 0x32 + 38: 3178 .2byte 0x3178 + 3a: 3070 .2byte 0x3070 + 3c: 7a5f 6576 3436 .byte 0x5f, 0x7a, 0x76, 0x65, 0x36, 0x34 + 42: 3178 .2byte 0x3178 + 44: 3070 .2byte 0x3070 + 46: 7a5f 6c76 3233 .byte 0x5f, 0x7a, 0x76, 0x6c, 0x33, 0x32 + 4c: 3162 vmsge.vx v2,v0,zero,v0.t + 4e: 3070 .2byte 0x3070 + 50: 7a5f 6c76 3436 .byte 0x5f, 0x7a, 0x76, 0x6c, 0x36, 0x34 + 56: 3162 vmsge.vx v2,v0,zero,v0.t + 58: 3070 .2byte 0x3070 + 5a: 0800 vmsge.vx v16,v0,zero,v0.t + 5c: 0a01 vmsge.vx v20,v0,zero,v0.t + 5e: 0b Address 0x5e is out of bounds. + diff --git a/src/main/resources/applications_vector/vnmsac/vnmsac.c b/src/main/resources/applications_vector/vnmsac/vnmsac.c new file mode 100644 index 00000000..e298de01 --- /dev/null +++ b/src/main/resources/applications_vector/vnmsac/vnmsac.c @@ -0,0 +1,95 @@ +#include "util.h" + +#define size_t long +#define N 48 + +const signed short dataArray0[N] = {-26995, -13957, -10861, 25374, -18032, -21149, 23738, 24548, -28110, -21910, 16774, -10117, 19840, -11921, 12711, -24192, 27586, -20052, -20407, 13650, -15786, 21109, 31998, 18796, -11098, -1692, 1179, -29277, -17643, -26788, -15187, -12884, -8109, -21033, -28781, 21148, -26980, 24605, 14759, 5326, 32568, 14468, -29372, -25205, -3712, 12033, -13808, 15296}; +const signed short dataArray1[N] = {30505, 20166, 5646, -22016, -20267, 1851, -16870, -15522, -6478, 28568, -24933, -8558, 28891, 29410, -5672, -25610, 17628, -16913, -3658, -29191, -18246, 7697, 16690, -9899, 5905, -25983, 25695, 6411, -409, 1080, 8789, -23885, -15650, 27052, -8835, -13117, -11213, 12484, 30265, -20895, 29055, -28773, -22596, 15861, -29873, 27504, 21957, -13862}; +const signed short dataArray2[N] = {28495, -8577, 25952, 32552, -21237, -11141, 13665, 4943, 18722, -1943, -7490, 23423, 26213, -2937, 12240, -23931, 9720, 32697, 28006, -15275, 24539, -26743, 25687, -5263, 31572, -8462, 17153, -10801, -665, 29112, 31568, -23133, 16087, 29233, 7190, -16073, -22331, -30392, 18281, -2016, -24649, 29272, 19468, 2718, 4672, 12042, 8434, -28150}; +signed short resultArray[N] = {0}; +signed short answerArray[N] = {0}; + +extern void printstr(char* str); +extern void int64ToHex(long num, char* str); +extern void int32ToHex(int num, char* str); +extern void clearCounters(); +extern void printCounters(); + +int main(int argc, char** argv) { + int vl, avl = 41; + const signed short *ptr0 = dataArray0; + const signed short *ptr1 = dataArray1; + const signed short *ptr2 = dataArray2; + signed short *ptr3 = resultArray; + while(avl != 0) { + asm volatile ("vsetvli %0, %1, e16, m1, ta, ma" + : "=r"(vl) + : "r"(avl)); + // asm volatile ("li t0, 0x1919"); + asm volatile ("vle16.v v10, (%0)" + : + : "r"(ptr0)); + asm volatile ("vle16.v v11, (%0)" + : + : "r"(ptr1)); + asm volatile ("vle16.v v12, (%0)" + : + : "r"(ptr2)); + // v12 = -(v10 * v11) + v12 + asm volatile ("vnmsac.vv v12, v10, v11"); + asm volatile ("vse16.v v12, (%0)" + : + : "r"(ptr3)); + ptr0 += vl; + ptr1 += vl; + ptr2 += vl; + ptr3 += vl; + avl -= vl; + } + int i; + for(i=0; i<41; i++) { + answerArray[i] = -(dataArray0[i] * dataArray1[i]) + dataArray2[i]; + } + + _Bool correct = 1; + for(i=0; i<41; i++) { + if(resultArray[i] != answerArray[i]) { + correct = 0; + } + } + avl = 41; + ptr0 = dataArray0; + ptr1 = dataArray1; + ptr3 = resultArray; + while(avl != 0) { + asm volatile ("vsetvli %0, %1, e16, m1, ta, ma" + : "=r"(vl) + : "r"(avl)); + asm volatile ("vle16.v v10, (%0)" + : + : "r"(ptr0)); + asm volatile ("vle16.v v11, (%0)" + : + : "r"(ptr1)); + // v11 = -(0x1919 * v10) + v11 + asm volatile ("vnmsac.vx v11, %0, v10" + : + : "r"(0x1919)); + asm volatile ("vse16.v v11, (%0)" + : + : "r"(ptr3)); + ptr0 += vl; + ptr1 += vl; + ptr3 += vl; + avl -= vl; + } + for(i=0; i<41; i++) { + answerArray[i] = -(0x1919 * dataArray0[i]) + dataArray1[i]; + } + for(i=0; i<41; i++) { + if(resultArray[i] != answerArray[i]) { + correct = 0; + } + } + return !correct; +} diff --git a/src/main/resources/applications_vector/vnmsac_data.hex b/src/main/resources/applications_vector/vnmsac_data.hex new file mode 100644 index 00000000..76ca0b6b --- /dev/null +++ b/src/main/resources/applications_vector/vnmsac_data.hex @@ -0,0 +1,180 @@ +de7f6f4f +7f286560 +d47bad0b +134f3561 +f8694922 +5b7fe2be +f4876665 +a2852fd0 +7fb925f8 +c4556d66 +97895fdb +eb716457 +def27b54 +d5cf4301 +71b8fd67 +a5a37b50 +72313ed7 +c1371c16 +8948a8c5 +f8204769 +72589fb7 +0a9e4c0c +2f0a1240 +920a20f2 +4ec67729 +aa00160e +073bb0d5 +c35ebe1a +6f98e6b2 +de929e9b +72e270db +9bf6e9d8 +bdef44dc +8df9f1b6 +1e11b8ba +d9554132 +9a811711 +190b645f +0438fe67 +a2b32255 +69acc2de +ccc3dd7d +30c4d433 +ae617639 +8f9b717f +3df5a7bc +6b708b4f +c9da55c5 +c97b968d +631ed593 +ad63b990 +5fe45cba +aa6a9232 +d87b4186 +d16f4d80 +a18031a7 +b1ac6bc2 +3552b049 +5275c256 +496c7cfe +f964d4a6 +8da3049b +975cbb15 +cdacc4ad +add7e053 +529c8f93 +601d969c +14ce39a7 +38847f38 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+3a435020 +00000020 +00000000 +4548430a +4d204b43 +53554143 +6e692045 +4c545220 +00000000 +01010101 +01010101 diff --git a/src/main/resources/applications_vector/vnmsac_inst.hex b/src/main/resources/applications_vector/vnmsac_inst.hex new file mode 100644 index 00000000..ac6b151d --- /dev/null +++ b/src/main/resources/applications_vector/vnmsac_inst.hex @@ -0,0 +1,677 @@ +00000093 +00000113 +00000193 +00000213 +00000293 +00000313 +00000393 +00000413 +00000493 +00000513 +00000593 +00000613 +00000693 +00000713 +00000793 +00000813 +00000893 +00000913 +00000993 +00000a13 +00000a93 +00000b13 +00000b93 +00000c13 +00000c93 +00000d13 +00000d93 +00000e13 +00000e93 +00000f13 +00000f93 +00000297 +03828293 +30529073 +00005197 +a4018193 +10000217 +ff720213 +fc027213 +f1402573 +00100593 +00b57063 +00006137 +ff01011b +6580006f +ef010113 +00113423 +00213823 +00313c23 +02413023 +02513423 +02613823 +02713c23 +04813023 +04913423 +04a13823 +04b13c23 +06c13023 +06d13423 +06e13823 +06f13c23 +09013023 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+00008067 +00000513 +ff5ff06f +00050793 +0005c703 +00178793 +00158593 +fee78fa3 +fe0718e3 +00008067 +00004517 +9e050513 +00003597 +70858593 +00003617 +76060613 +00003697 +7b868693 +02900713 +0c877857 +0008079b +0206d507 +02065587 +0205d607 +beb52657 +02055627 +00179793 +4107073b +00f686b3 +00f60633 +00f585b3 +00f50533 +fc0716e3 +00003697 +77468693 +00003597 +70c58593 +86818813 +00003797 +6a078793 +00003e97 +6eae8e93 +00080313 +00058893 +00068513 +00055603 +0008de03 +0007d703 +00230313 +03c6063b +00278793 +00250513 +00288893 +40c7073b +fee31f23 +fdd79ce3 +00004717 +92870713 +85a18893 +86818613 +00070793 +00100513 +00061e03 +00079303 +00260613 +00278793 +006e0463 +00000513 +ff1794e3 +00002fb7 +00004e97 +8f0e8e93 +00003e17 +678e0e13 +00003317 +6d030313 +02900613 +919f8f9b +0c867f57 +000f079b +02035507 +020e5587 +beafe5d7 +020ed5a7 +00179793 +41e6063b +00f30333 +00fe0e33 +00fe8eb3 +fc061ae3 +ffffee37 +00003e97 +6dee8e93 +86818613 +6e7e0e1b +0006d783 +0005d303 +00260613 +02fe07bb +00268693 +00258593 +006787bb +fef61f23 +fede90e3 +00071683 +00081783 +00270713 +00280813 +00f68463 +00000513 +ff1714e3 +00154513 +00008067 +fff00513 +00008067 diff --git a/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala b/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala index 32c21285..b9e2fa60 100644 --- a/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala +++ b/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala @@ -140,7 +140,7 @@ class Zve64xAppTestForVecCpu extends AnyFlatSpec with ChiselScalatestTester { "vminmax", "vmerge", "vmv", "vmand", "vmor", "vmxor", "vmul", "vmulh", "vmulhu", "vmulhsu", - "vmacc", + "vmacc", "vnmsac", ) val applicationTest = Seq( "vector_median" From 64942d692965cc83453d9e5da8027a0f953c0d9c Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Mon, 13 Nov 2023 13:56:49 +0900 Subject: [PATCH 06/14] vmadd --- .../resources/applications_vector/build.sh | 17 + .../resources/applications_vector/vmadd.dump | 1098 +++++++++++++++++ .../applications_vector/vmadd/vmadd.c | 95 ++ .../applications_vector/vmadd_data.hex | 180 +++ .../applications_vector/vmadd_inst.hex | 677 ++++++++++ .../hajime/vectormodules/VectorCpuSpec.scala | 2 +- 6 files changed, 2068 insertions(+), 1 deletion(-) create mode 100644 src/main/resources/applications_vector/vmadd.dump create mode 100644 src/main/resources/applications_vector/vmadd/vmadd.c create mode 100644 src/main/resources/applications_vector/vmadd_data.hex create mode 100644 src/main/resources/applications_vector/vmadd_inst.hex diff --git a/src/main/resources/applications_vector/build.sh b/src/main/resources/applications_vector/build.sh index 9b2a59b9..986580dc 100644 --- a/src/main/resources/applications_vector/build.sh +++ b/src/main/resources/applications_vector/build.sh @@ -467,4 +467,21 @@ hexdump -v -e '1/4 "%08x" "\n"' vnmsac_text_startup.bin > vnmsac_text_startup.te cat vnmsac_rodata.temp vnmsac_rodata_str1_8.temp vnmsac_sdata.temp > vnmsac_data.hex cat vnmsac_text_init.temp vnmsac_text.temp vnmsac_text_startup.temp > vnmsac_inst.hex +riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vmadd.riscv ./vmadd/vmadd.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld +riscv64-unknown-elf-objdump --disassemble-all vmadd.riscv > vmadd.dump +riscv64-unknown-elf-objcopy --dump-section .rodata=vmadd_rodata.bin vmadd.riscv +riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vmadd_rodata_str1_8.bin vmadd.riscv +riscv64-unknown-elf-objcopy --dump-section .sdata=vmadd_sdata.bin vmadd.riscv +riscv64-unknown-elf-objcopy --dump-section .text.init=vmadd_text_init.bin vmadd.riscv +riscv64-unknown-elf-objcopy --dump-section .text=vmadd_text.bin vmadd.riscv +riscv64-unknown-elf-objcopy --dump-section .text.startup=vmadd_text_startup.bin vmadd.riscv +hexdump -v -e '1/4 "%08x" "\n"' vmadd_rodata.bin > vmadd_rodata.temp +hexdump -v -e '1/4 "%08x" "\n"' vmadd_rodata_str1_8.bin > vmadd_rodata_str1_8.temp +hexdump -v -e '1/4 "%08x" "\n"' vmadd_sdata.bin > vmadd_sdata.temp +hexdump -v -e '1/4 "%08x" "\n"' vmadd_text_init.bin > vmadd_text_init.temp +hexdump -v -e '1/4 "%08x" "\n"' vmadd_text.bin > vmadd_text.temp +hexdump -v -e '1/4 "%08x" "\n"' vmadd_text_startup.bin > vmadd_text_startup.temp +cat vmadd_rodata.temp vmadd_rodata_str1_8.temp vmadd_sdata.temp > vmadd_data.hex +cat vmadd_text_init.temp vmadd_text.temp vmadd_text_startup.temp > vmadd_inst.hex + rm *.riscv *.bin *.temp \ No newline at end of file diff --git a/src/main/resources/applications_vector/vmadd.dump b/src/main/resources/applications_vector/vmadd.dump new file mode 100644 index 00000000..6528a00a --- /dev/null +++ b/src/main/resources/applications_vector/vmadd.dump @@ -0,0 +1,1098 @@ + +vmadd.riscv: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000000000000 <_start>: + 0: 00000093 li ra,0 + 4: 00000113 li sp,0 + 8: 00000193 li gp,0 + c: 00000213 li tp,0 + 10: 00000293 li t0,0 + 14: 00000313 li t1,0 + 18: 00000393 li t2,0 + 1c: 00000413 li s0,0 + 20: 00000493 li s1,0 + 24: 00000513 li a0,0 + 28: 00000593 li a1,0 + 2c: 00000613 li a2,0 + 30: 00000693 li a3,0 + 34: 00000713 li a4,0 + 38: 00000793 li a5,0 + 3c: 00000813 li a6,0 + 40: 00000893 li a7,0 + 44: 00000913 li s2,0 + 48: 00000993 li s3,0 + 4c: 00000a13 li s4,0 + 50: 00000a93 li s5,0 + 54: 00000b13 li s6,0 + 58: 00000b93 li s7,0 + 5c: 00000c13 li s8,0 + 60: 00000c93 li s9,0 + 64: 00000d13 li s10,0 + 68: 00000d93 li s11,0 + 6c: 00000e13 li t3,0 + 70: 00000e93 li t4,0 + 74: 00000f13 li t5,0 + 78: 00000f93 li t6,0 + 7c: 00000297 auipc t0,0x0 + 80: 03828293 add t0,t0,56 # b4 + 84: 30529073 csrw mtvec,t0 + 88: 00005197 auipc gp,0x5 + 8c: a4018193 add gp,gp,-1472 # 4ac8 <__global_pointer$> + 90: 10000217 auipc tp,0x10000 + 94: ff720213 add tp,tp,-9 # 10000087 <_end+0x3f> + 98: fc027213 and tp,tp,-64 + 9c: f1402573 csrr a0,mhartid + a0: 00100593 li a1,1 + a4: 00b57063 bgeu a0,a1,a4 <_start+0xa4> + a8: 00006137 lui sp,0x6 + ac: ff01011b addw sp,sp,-16 # 5ff0 <__global_pointer$+0x1528> + b0: 6580006f j 708 <_init> + +00000000000000b4 : + b4: ef010113 add sp,sp,-272 + b8: 00113423 sd ra,8(sp) + bc: 00213823 sd sp,16(sp) + c0: 00313c23 sd gp,24(sp) + c4: 02413023 sd tp,32(sp) + c8: 02513423 sd t0,40(sp) + cc: 02613823 sd t1,48(sp) + d0: 02713c23 sd t2,56(sp) + d4: 04813023 sd s0,64(sp) + d8: 04913423 sd s1,72(sp) + dc: 04a13823 sd a0,80(sp) + e0: 04b13c23 sd a1,88(sp) + e4: 06c13023 sd a2,96(sp) + e8: 06d13423 sd a3,104(sp) + ec: 06e13823 sd a4,112(sp) + f0: 06f13c23 sd a5,120(sp) + f4: 09013023 sd a6,128(sp) + f8: 09113423 sd a7,136(sp) + fc: 09213823 sd s2,144(sp) + 100: 09313c23 sd s3,152(sp) + 104: 0b413023 sd s4,160(sp) + 108: 0b513423 sd s5,168(sp) + 10c: 0b613823 sd s6,176(sp) + 110: 0b713c23 sd s7,184(sp) + 114: 0d813023 sd s8,192(sp) + 118: 0d913423 sd s9,200(sp) + 11c: 0da13823 sd s10,208(sp) + 120: 0db13c23 sd s11,216(sp) + 124: 0fc13023 sd t3,224(sp) + 128: 0fd13423 sd t4,232(sp) + 12c: 0fe13823 sd t5,240(sp) + 130: 0ff13c23 sd t6,248(sp) + 134: 34202573 csrr a0,mcause + 138: 341025f3 csrr a1,mepc + 13c: 00010613 mv a2,sp + 140: 2d0000ef jal 410 + 144: 34151073 csrw mepc,a0 + 148: 000022b7 lui t0,0x2 + 14c: 8002829b addw t0,t0,-2048 # 1800 + 150: 3002a073 csrs mstatus,t0 + 154: 00813083 ld ra,8(sp) + 158: 01013103 ld sp,16(sp) + 15c: 01813183 ld gp,24(sp) + 160: 02013203 ld tp,32(sp) + 164: 02813283 ld t0,40(sp) + 168: 03013303 ld t1,48(sp) + 16c: 03813383 ld t2,56(sp) + 170: 04013403 ld s0,64(sp) + 174: 04813483 ld s1,72(sp) + 178: 05013503 ld a0,80(sp) + 17c: 05813583 ld a1,88(sp) + 180: 06013603 ld a2,96(sp) + 184: 06813683 ld a3,104(sp) + 188: 07013703 ld a4,112(sp) + 18c: 07813783 ld a5,120(sp) + 190: 08013803 ld a6,128(sp) + 194: 08813883 ld a7,136(sp) + 198: 09013903 ld s2,144(sp) + 19c: 09813983 ld s3,152(sp) + 1a0: 0a013a03 ld s4,160(sp) + 1a4: 0a813a83 ld s5,168(sp) + 1a8: 0b013b03 ld s6,176(sp) + 1ac: 0b813b83 ld s7,184(sp) + 1b0: 0c013c03 ld s8,192(sp) + 1b4: 0c813c83 ld s9,200(sp) + 1b8: 0d013d03 ld s10,208(sp) + 1bc: 0d813d83 ld s11,216(sp) + 1c0: 0e013e03 ld t3,224(sp) + 1c4: 0e813e83 ld t4,232(sp) + 1c8: 0f013f03 ld t5,240(sp) + 1cc: 0f813f83 ld t6,248(sp) + 1d0: 11010113 add sp,sp,272 + 1d4: 30200073 mret + +Disassembly of section .text: + +00000000000001d8 : + 1d8: b0201073 csrw minstret,zero + 1dc: b0001073 csrw mcycle,zero + 1e0: 00008067 ret + +00000000000001e4 : + 1e4: 03000793 li a5,48 + 1e8: 00f58023 sb a5,0(a1) + 1ec: 07800793 li a5,120 + 1f0: 00f580a3 sb a5,1(a1) + 1f4: 00158813 add a6,a1,1 + 1f8: 00958793 add a5,a1,9 + 1fc: 00900613 li a2,9 + 200: 00f57713 and a4,a0,15 + 204: 03770693 add a3,a4,55 + 208: 00e66463 bltu a2,a4,210 + 20c: 03070693 add a3,a4,48 + 210: 00d78023 sb a3,0(a5) + 214: fff78793 add a5,a5,-1 + 218: 40455513 sra a0,a0,0x4 + 21c: fef812e3 bne a6,a5,200 + 220: 00058523 sb zero,10(a1) + 224: 00008067 ret + +0000000000000228 : + 228: 03000793 li a5,48 + 22c: 00f58023 sb a5,0(a1) + 230: 07800793 li a5,120 + 234: 00f580a3 sb a5,1(a1) + 238: 00158813 add a6,a1,1 + 23c: 01158793 add a5,a1,17 + 240: 00900613 li a2,9 + 244: 00f57713 and a4,a0,15 + 248: 03770693 add a3,a4,55 + 24c: 00e66463 bltu a2,a4,254 + 250: 03070693 add a3,a4,48 + 254: 00d78023 sb a3,0(a5) + 258: fff78793 add a5,a5,-1 + 25c: 40455513 sra a0,a0,0x4 + 260: fef812e3 bne a6,a5,244 + 264: 00058923 sb zero,18(a1) + 268: 00008067 ret + +000000000000026c : + 26c: 00054783 lbu a5,0(a0) + 270: 00078c63 beqz a5,288 + 274: 10000737 lui a4,0x10000 + 278: 00f70023 sb a5,0(a4) # 10000000 + 27c: 00154783 lbu a5,1(a0) + 280: 00150513 add a0,a0,1 + 284: fe079ae3 bnez a5,278 + 288: 00008067 ret + +000000000000028c : + 28c: fe010113 add sp,sp,-32 + 290: c0202673 rdinstret a2 + 294: c00025f3 rdcycle a1 + 298: 00004717 auipc a4,0x4 + 29c: eb870713 add a4,a4,-328 # 4150 + 2a0: 06300793 li a5,99 + 2a4: 100006b7 lui a3,0x10000 + 2a8: 00f68023 sb a5,0(a3) # 10000000 + 2ac: 00174783 lbu a5,1(a4) + 2b0: 00170713 add a4,a4,1 + 2b4: fe079ae3 bnez a5,2a8 + 2b8: ffff8737 lui a4,0xffff8 + 2bc: 83074713 xor a4,a4,-2000 + 2c0: 01910793 add a5,sp,25 + 2c4: 00e11423 sh a4,8(sp) + 2c8: 00910813 add a6,sp,9 + 2cc: 00078713 mv a4,a5 + 2d0: 00900893 li a7,9 + 2d4: 00f5f693 and a3,a1,15 + 2d8: 03768513 add a0,a3,55 + 2dc: 00d8e463 bltu a7,a3,2e4 + 2e0: 03068513 add a0,a3,48 + 2e4: 00a70023 sb a0,0(a4) # ffffffffffff8000 <_end+0xffffffffefff7fb8> + 2e8: fff70713 add a4,a4,-1 + 2ec: 4045d593 sra a1,a1,0x4 + 2f0: fee812e3 bne a6,a4,2d4 + 2f4: 00814703 lbu a4,8(sp) + 2f8: 00010d23 sb zero,26(sp) + 2fc: 00810693 add a3,sp,8 + 300: 100005b7 lui a1,0x10000 + 304: 00070a63 beqz a4,318 + 308: 00e58023 sb a4,0(a1) # 10000000 + 30c: 0016c703 lbu a4,1(a3) + 310: 00168693 add a3,a3,1 + 314: fe071ae3 bnez a4,308 + 318: 00004697 auipc a3,0x4 + 31c: e4068693 add a3,a3,-448 # 4158 + 320: 00a00713 li a4,10 + 324: 100005b7 lui a1,0x10000 + 328: 00e58023 sb a4,0(a1) # 10000000 + 32c: 0016c703 lbu a4,1(a3) + 330: 00168693 add a3,a3,1 + 334: fe071ae3 bnez a4,328 + 338: ffff8737 lui a4,0xffff8 + 33c: 83074713 xor a4,a4,-2000 + 340: 00060693 mv a3,a2 + 344: 00e11423 sh a4,8(sp) + 348: 00900593 li a1,9 + 34c: 00f6f713 and a4,a3,15 + 350: 03770613 add a2,a4,55 # ffffffffffff8037 <_end+0xffffffffefff7fef> + 354: 00e5e463 bltu a1,a4,35c + 358: 03070613 add a2,a4,48 + 35c: 00c78023 sb a2,0(a5) + 360: fff78793 add a5,a5,-1 + 364: 4046d693 sra a3,a3,0x4 + 368: fef812e3 bne a6,a5,34c + 36c: 00814783 lbu a5,8(sp) + 370: 00010d23 sb zero,26(sp) + 374: 00810713 add a4,sp,8 + 378: 100006b7 lui a3,0x10000 + 37c: 00078a63 beqz a5,390 + 380: 00f68023 sb a5,0(a3) # 10000000 + 384: 00174783 lbu a5,1(a4) + 388: 00170713 add a4,a4,1 + 38c: fe079ae3 bnez a5,380 + 390: 100007b7 lui a5,0x10000 + 394: 00a00713 li a4,10 + 398: 00e78023 sb a4,0(a5) # 10000000 + 39c: 02010113 add sp,sp,32 + 3a0: 00008067 ret + +00000000000003a4 : + 3a4: fe010113 add sp,sp,-32 + 3a8: 00813823 sd s0,16(sp) + 3ac: 00113c23 sd ra,24(sp) + 3b0: 00050413 mv s0,a0 + 3b4: 00004717 auipc a4,0x4 + 3b8: db470713 add a4,a4,-588 # 4168 + 3bc: 04500793 li a5,69 + 3c0: 100006b7 lui a3,0x10000 + 3c4: 00f68023 sb a5,0(a3) # 10000000 + 3c8: 00174783 lbu a5,1(a4) + 3cc: 00170713 add a4,a4,1 + 3d0: fe079ae3 bnez a5,3c4 + 3d4: 00010593 mv a1,sp + 3d8: 00040513 mv a0,s0 + 3dc: e09ff0ef jal 1e4 + 3e0: 00014703 lbu a4,0(sp) + 3e4: 00070e63 beqz a4,400 + 3e8: 00010793 mv a5,sp + 3ec: 100006b7 lui a3,0x10000 + 3f0: 00e68023 sb a4,0(a3) # 10000000 + 3f4: 0017c703 lbu a4,1(a5) + 3f8: 00178793 add a5,a5,1 + 3fc: fe071ae3 bnez a4,3f0 + 400: 00040513 mv a0,s0 + 404: 100007b7 lui a5,0x10000 + 408: 00078023 sb zero,0(a5) # 10000000 + 40c: 0000006f j 40c + +0000000000000410 : + 410: ffff87b7 lui a5,0xffff8 + 414: fd010113 add sp,sp,-48 + 418: 8307c793 xor a5,a5,-2000 + 41c: 00f11423 sh a5,8(sp) + 420: 02113423 sd ra,40(sp) + 424: 01910793 add a5,sp,25 + 428: 00910813 add a6,sp,9 + 42c: 00900613 li a2,9 + 430: 00f5f713 and a4,a1,15 + 434: 03770693 add a3,a4,55 + 438: 00e66463 bltu a2,a4,440 + 43c: 03070693 add a3,a4,48 + 440: 00d78023 sb a3,0(a5) # ffffffffffff8000 <_end+0xffffffffefff7fb8> + 444: fff78793 add a5,a5,-1 + 448: 4045d593 sra a1,a1,0x4 + 44c: ff0792e3 bne a5,a6,430 + 450: 00010d23 sb zero,26(sp) + 454: 00b00793 li a5,11 + 458: 02a7e063 bltu a5,a0,478 + 45c: 00004717 auipc a4,0x4 + 460: cc470713 add a4,a4,-828 # 4120 + 464: 00251513 sll a0,a0,0x2 + 468: 00e50533 add a0,a0,a4 + 46c: 00052783 lw a5,0(a0) + 470: 00e787b3 add a5,a5,a4 + 474: 00078067 jr a5 + 478: 00004717 auipc a4,0x4 + 47c: e1870713 add a4,a4,-488 # 4290 + 480: 05500793 li a5,85 + 484: 100006b7 lui a3,0x10000 + 488: 00f68023 sb a5,0(a3) # 10000000 + 48c: 00174783 lbu a5,1(a4) + 490: 00170713 add a4,a4,1 + 494: fe079ae3 bnez a5,488 + 498: 00814783 lbu a5,8(sp) + 49c: 00810713 add a4,sp,8 + 4a0: 100006b7 lui a3,0x10000 + 4a4: 00078a63 beqz a5,4b8 + 4a8: 00f68023 sb a5,0(a3) # 10000000 + 4ac: 00174783 lbu a5,1(a4) + 4b0: 00170713 add a4,a4,1 + 4b4: fe079ae3 bnez a5,4a8 + 4b8: 00004717 auipc a4,0x4 + 4bc: df870713 add a4,a4,-520 # 42b0 + 4c0: 00a00793 li a5,10 + 4c4: 100006b7 lui a3,0x10000 + 4c8: 00f68023 sb a5,0(a3) # 10000000 + 4cc: 00174783 lbu a5,1(a4) + 4d0: 00170713 add a4,a4,1 + 4d4: fe079ae3 bnez a5,4c8 + 4d8: fff00513 li a0,-1 + 4dc: ec9ff0ef jal 3a4 + 4e0: 00004717 auipc a4,0x4 + 4e4: c9870713 add a4,a4,-872 # 4178 + 4e8: 04900793 li a5,73 + 4ec: 100006b7 lui a3,0x10000 + 4f0: 00f68023 sb a5,0(a3) # 10000000 + 4f4: 00174783 lbu a5,1(a4) + 4f8: 00170713 add a4,a4,1 + 4fc: fe079ae3 bnez a5,4f0 + 500: 00814783 lbu a5,8(sp) + 504: 00810713 add a4,sp,8 + 508: 100006b7 lui a3,0x10000 + 50c: fc0786e3 beqz a5,4d8 + 510: 00f68023 sb a5,0(a3) # 10000000 + 514: 00174783 lbu a5,1(a4) + 518: 00170713 add a4,a4,1 + 51c: fe079ae3 bnez a5,510 + 520: fb9ff06f j 4d8 + 524: 00004717 auipc a4,0x4 + 528: c7c70713 add a4,a4,-900 # 41a0 + 52c: 04900793 li a5,73 + 530: 100006b7 lui a3,0x10000 + 534: 00f68023 sb a5,0(a3) # 10000000 + 538: 00174783 lbu a5,1(a4) + 53c: 00170713 add a4,a4,1 + 540: fe079ae3 bnez a5,534 + 544: 00814783 lbu a5,8(sp) + 548: f80788e3 beqz a5,4d8 + 54c: 00810713 add a4,sp,8 + 550: 100006b7 lui a3,0x10000 + 554: 00f68023 sb a5,0(a3) # 10000000 + 558: 00174783 lbu a5,1(a4) + 55c: 00170713 add a4,a4,1 + 560: fe079ae3 bnez a5,554 + 564: f75ff06f j 4d8 + 568: 00004717 auipc a4,0x4 + 56c: c6070713 add a4,a4,-928 # 41c8 + 570: 04900793 li a5,73 + 574: 100006b7 lui a3,0x10000 + 578: 00f68023 sb a5,0(a3) # 10000000 + 57c: 00174783 lbu a5,1(a4) + 580: 00170713 add a4,a4,1 + 584: fe079ae3 bnez a5,578 + 588: 00814783 lbu a5,8(sp) + 58c: f40786e3 beqz a5,4d8 + 590: 00810713 add a4,sp,8 + 594: 100006b7 lui a3,0x10000 + 598: 00f68023 sb a5,0(a3) # 10000000 + 59c: 00174783 lbu a5,1(a4) + 5a0: 00170713 add a4,a4,1 + 5a4: fe079ae3 bnez a5,598 + 5a8: f31ff06f j 4d8 + 5ac: 00004717 auipc a4,0x4 + 5b0: c3c70713 add a4,a4,-964 # 41e8 + 5b4: 04c00793 li a5,76 + 5b8: 100006b7 lui a3,0x10000 + 5bc: 00f68023 sb a5,0(a3) # 10000000 + 5c0: 00174783 lbu a5,1(a4) + 5c4: 00170713 add a4,a4,1 + 5c8: fe079ae3 bnez a5,5bc + 5cc: 00814783 lbu a5,8(sp) + 5d0: f00784e3 beqz a5,4d8 + 5d4: 00810713 add a4,sp,8 + 5d8: 100006b7 lui a3,0x10000 + 5dc: 00f68023 sb a5,0(a3) # 10000000 + 5e0: 00174783 lbu a5,1(a4) + 5e4: 00170713 add a4,a4,1 + 5e8: fe079ae3 bnez a5,5dc + 5ec: eedff06f j 4d8 + 5f0: 00004717 auipc a4,0x4 + 5f4: c1870713 add a4,a4,-1000 # 4208 + 5f8: 04c00793 li a5,76 + 5fc: 100006b7 lui a3,0x10000 + 600: 00f68023 sb a5,0(a3) # 10000000 + 604: 00174783 lbu a5,1(a4) + 608: 00170713 add a4,a4,1 + 60c: fe079ae3 bnez a5,600 + 610: 00814783 lbu a5,8(sp) + 614: ec0782e3 beqz a5,4d8 + 618: 00810713 add a4,sp,8 + 61c: 100006b7 lui a3,0x10000 + 620: 00f68023 sb a5,0(a3) # 10000000 + 624: 00174783 lbu a5,1(a4) + 628: 00170713 add a4,a4,1 + 62c: fe079ae3 bnez a5,620 + 630: ea9ff06f j 4d8 + 634: 00004717 auipc a4,0x4 + 638: bf470713 add a4,a4,-1036 # 4228 + 63c: 05300793 li a5,83 + 640: 100006b7 lui a3,0x10000 + 644: 00f68023 sb a5,0(a3) # 10000000 + 648: 00174783 lbu a5,1(a4) + 64c: 00170713 add a4,a4,1 + 650: fe079ae3 bnez a5,644 + 654: 00814783 lbu a5,8(sp) + 658: e80780e3 beqz a5,4d8 + 65c: 00810713 add a4,sp,8 + 660: 100006b7 lui a3,0x10000 + 664: 00f68023 sb a5,0(a3) # 10000000 + 668: 00174783 lbu a5,1(a4) + 66c: 00170713 add a4,a4,1 + 670: fe079ae3 bnez a5,664 + 674: e65ff06f j 4d8 + 678: 00004717 auipc a4,0x4 + 67c: bd870713 add a4,a4,-1064 # 4250 + 680: 05300793 li a5,83 + 684: 100006b7 lui a3,0x10000 + 688: 00f68023 sb a5,0(a3) # 10000000 + 68c: 00174783 lbu a5,1(a4) + 690: 00170713 add a4,a4,1 + 694: fe079ae3 bnez a5,688 + 698: 00814783 lbu a5,8(sp) + 69c: e2078ee3 beqz a5,4d8 + 6a0: 00810713 add a4,sp,8 + 6a4: 100006b7 lui a3,0x10000 + 6a8: 00f68023 sb a5,0(a3) # 10000000 + 6ac: 00174783 lbu a5,1(a4) + 6b0: 00170713 add a4,a4,1 + 6b4: fe079ae3 bnez a5,6a8 + 6b8: e21ff06f j 4d8 + 6bc: 00004717 auipc a4,0x4 + 6c0: bb470713 add a4,a4,-1100 # 4270 + 6c4: 04500793 li a5,69 + 6c8: 100006b7 lui a3,0x10000 + 6cc: 00f68023 sb a5,0(a3) # 10000000 + 6d0: 00174783 lbu a5,1(a4) + 6d4: 00170713 add a4,a4,1 + 6d8: fe079ae3 bnez a5,6cc + 6dc: 00814783 lbu a5,8(sp) + 6e0: de078ce3 beqz a5,4d8 + 6e4: 00810713 add a4,sp,8 + 6e8: 100006b7 lui a3,0x10000 + 6ec: 00f68023 sb a5,0(a3) # 10000000 + 6f0: 00174783 lbu a5,1(a4) + 6f4: 00170713 add a4,a4,1 + 6f8: fe079ae3 bnez a5,6ec + 6fc: dddff06f j 4d8 + +0000000000000700 : + 700: 00051063 bnez a0,700 + 704: 00008067 ret + +0000000000000708 <_init>: + 708: ff010113 add sp,sp,-16 + 70c: 00000593 li a1,0 + 710: 00000513 li a0,0 + 714: 00113423 sd ra,8(sp) + 718: 1d8000ef jal 8f0
+ 71c: c89ff0ef jal 3a4 + +0000000000000720 : + 720: 00b567b3 or a5,a0,a1 + 724: 00c7e7b3 or a5,a5,a2 + 728: 0077f793 and a5,a5,7 + 72c: 00c50833 add a6,a0,a2 + 730: 02078463 beqz a5,758 + 734: 00c58633 add a2,a1,a2 + 738: 00050793 mv a5,a0 + 73c: 0b057663 bgeu a0,a6,7e8 + 740: 0005c703 lbu a4,0(a1) + 744: 00158593 add a1,a1,1 + 748: 00178793 add a5,a5,1 + 74c: fee78fa3 sb a4,-1(a5) + 750: fec598e3 bne a1,a2,740 + 754: 00008067 ret + 758: 04050693 add a3,a0,64 + 75c: 0906f863 bgeu a3,a6,7ec + 760: 00058713 mv a4,a1 + 764: 00068793 mv a5,a3 + 768: 00073383 ld t2,0(a4) + 76c: 00873283 ld t0,8(a4) + 770: 01073f83 ld t6,16(a4) + 774: 01873f03 ld t5,24(a4) + 778: 02073e83 ld t4,32(a4) + 77c: 02873e03 ld t3,40(a4) + 780: 03073303 ld t1,48(a4) + 784: 03873883 ld a7,56(a4) + 788: 04078793 add a5,a5,64 + 78c: f877b023 sd t2,-128(a5) + 790: f857b423 sd t0,-120(a5) + 794: f9f7b823 sd t6,-112(a5) + 798: f9e7bc23 sd t5,-104(a5) + 79c: fbd7b023 sd t4,-96(a5) + 7a0: fbc7b423 sd t3,-88(a5) + 7a4: fa67b823 sd t1,-80(a5) + 7a8: fb17bc23 sd a7,-72(a5) + 7ac: 04070713 add a4,a4,64 + 7b0: fb07ece3 bltu a5,a6,768 + 7b4: fbf60613 add a2,a2,-65 + 7b8: fc067793 and a5,a2,-64 + 7bc: 04078793 add a5,a5,64 + 7c0: fc067613 and a2,a2,-64 + 7c4: 00f585b3 add a1,a1,a5 + 7c8: 00c687b3 add a5,a3,a2 + 7cc: f907f4e3 bgeu a5,a6,754 + 7d0: 0005b703 ld a4,0(a1) + 7d4: 00878793 add a5,a5,8 + 7d8: 00858593 add a1,a1,8 + 7dc: fee7bc23 sd a4,-8(a5) + 7e0: ff07e8e3 bltu a5,a6,7d0 + 7e4: 00008067 ret + 7e8: 00008067 ret + 7ec: 00050793 mv a5,a0 + 7f0: fddff06f j 7cc + +00000000000007f4 : + 7f4: 00c567b3 or a5,a0,a2 + 7f8: 0077f793 and a5,a5,7 + 7fc: 00c50633 add a2,a0,a2 + 800: 0ff5f713 zext.b a4,a1 + 804: 00078e63 beqz a5,820 + 808: 00050793 mv a5,a0 + 80c: 02c57c63 bgeu a0,a2,844 + 810: 00178793 add a5,a5,1 + 814: fee78fa3 sb a4,-1(a5) + 818: fef61ce3 bne a2,a5,810 + 81c: 00008067 ret + 820: 00004797 auipc a5,0x4 + 824: aa87b783 ld a5,-1368(a5) # 42c8 + 828: 02f70733 mul a4,a4,a5 + 82c: fec578e3 bgeu a0,a2,81c + 830: 00050793 mv a5,a0 + 834: 00878793 add a5,a5,8 + 838: fee7bc23 sd a4,-8(a5) + 83c: fec7ece3 bltu a5,a2,834 + 840: 00008067 ret + 844: 00008067 ret + +0000000000000848 : + 848: 00054783 lbu a5,0(a0) + 84c: 00078e63 beqz a5,868 + 850: 00050793 mv a5,a0 + 854: 0017c703 lbu a4,1(a5) + 858: 00178793 add a5,a5,1 + 85c: fe071ce3 bnez a4,854 + 860: 40a78533 sub a0,a5,a0 + 864: 00008067 ret + 868: 00000513 li a0,0 + 86c: 00008067 ret + +0000000000000870 : + 870: 00b506b3 add a3,a0,a1 + 874: 00050793 mv a5,a0 + 878: 00059863 bnez a1,888 + 87c: 0240006f j 8a0 + 880: 00178793 add a5,a5,1 + 884: 00f68a63 beq a3,a5,898 + 888: 0007c703 lbu a4,0(a5) + 88c: fe071ae3 bnez a4,880 + 890: 40a78533 sub a0,a5,a0 + 894: 00008067 ret + 898: 40a68533 sub a0,a3,a0 + 89c: 00008067 ret + 8a0: 00000513 li a0,0 + 8a4: 00008067 ret + +00000000000008a8 : + 8a8: 00054783 lbu a5,0(a0) + 8ac: 00158593 add a1,a1,1 + 8b0: 00150513 add a0,a0,1 + 8b4: fff5c703 lbu a4,-1(a1) + 8b8: 00078a63 beqz a5,8cc + 8bc: fee786e3 beq a5,a4,8a8 + 8c0: 0007851b sext.w a0,a5 + 8c4: 40e5053b subw a0,a0,a4 + 8c8: 00008067 ret + 8cc: 00000513 li a0,0 + 8d0: ff5ff06f j 8c4 + +00000000000008d4 : + 8d4: 00050793 mv a5,a0 + 8d8: 0005c703 lbu a4,0(a1) + 8dc: 00178793 add a5,a5,1 + 8e0: 00158593 add a1,a1,1 + 8e4: fee78fa3 sb a4,-1(a5) + 8e8: fe0718e3 bnez a4,8d8 + 8ec: 00008067 ret + +Disassembly of section .text.startup: + +00000000000008f0
: + 8f0: 00004517 auipc a0,0x4 + 8f4: 9e050513 add a0,a0,-1568 # 42d0 + 8f8: 00003597 auipc a1,0x3 + 8fc: 70858593 add a1,a1,1800 # 4000 + 900: 00003617 auipc a2,0x3 + 904: 76060613 add a2,a2,1888 # 4060 + 908: 00003697 auipc a3,0x3 + 90c: 7b868693 add a3,a3,1976 # 40c0 + 910: 02900713 li a4,41 + 914: 0c877857 vsetvli a6,a4,e16,m1,ta,ma + 918: 0008079b sext.w a5,a6 + 91c: 0206d507 vle16.v v10,(a3) + 920: 02065587 vle16.v v11,(a2) + 924: 0205d607 vle16.v v12,(a1) + 928: a6b52657 vmadd.vv v12,v10,v11 + 92c: 02055627 vse16.v v12,(a0) + 930: 00179793 sll a5,a5,0x1 + 934: 4107073b subw a4,a4,a6 + 938: 00f686b3 add a3,a3,a5 + 93c: 00f60633 add a2,a2,a5 + 940: 00f585b3 add a1,a1,a5 + 944: 00f50533 add a0,a0,a5 + 948: fc0716e3 bnez a4,914 + 94c: 00003617 auipc a2,0x3 + 950: 77460613 add a2,a2,1908 # 40c0 + 954: 00003697 auipc a3,0x3 + 958: 70c68693 add a3,a3,1804 # 4060 + 95c: 86818593 add a1,gp,-1944 # 4330 + 960: 00003897 auipc a7,0x3 + 964: 6a088893 add a7,a7,1696 # 4000 + 968: 00003e97 auipc t4,0x3 + 96c: 7aae8e93 add t4,t4,1962 # 4112 + 970: 00058813 mv a6,a1 + 974: 00068513 mv a0,a3 + 978: 00060713 mv a4,a2 + 97c: 00075783 lhu a5,0(a4) + 980: 0008de03 lhu t3,0(a7) + 984: 00055303 lhu t1,0(a0) + 988: 00280813 add a6,a6,2 + 98c: 03c787bb mulw a5,a5,t3 + 990: 00270713 add a4,a4,2 + 994: 00288893 add a7,a7,2 + 998: 00250513 add a0,a0,2 + 99c: 006787bb addw a5,a5,t1 + 9a0: fef81f23 sh a5,-2(a6) + 9a4: fdd71ce3 bne a4,t4,97c + 9a8: 00004717 auipc a4,0x4 + 9ac: 92870713 add a4,a4,-1752 # 42d0 + 9b0: 85a18893 add a7,gp,-1958 # 4322 + 9b4: 86818813 add a6,gp,-1944 # 4330 + 9b8: 00070793 mv a5,a4 + 9bc: 00100513 li a0,1 + 9c0: 00081e03 lh t3,0(a6) + 9c4: 00079303 lh t1,0(a5) + 9c8: 00280813 add a6,a6,2 + 9cc: 00278793 add a5,a5,2 + 9d0: 006e0463 beq t3,t1,9d8 + 9d4: 00000513 li a0,0 + 9d8: ff1794e3 bne a5,a7,9c0 + 9dc: 00002fb7 lui t6,0x2 + 9e0: 00004e97 auipc t4,0x4 + 9e4: 8f0e8e93 add t4,t4,-1808 # 42d0 + 9e8: 00003e17 auipc t3,0x3 + 9ec: 678e0e13 add t3,t3,1656 # 4060 + 9f0: 00003317 auipc t1,0x3 + 9f4: 6d030313 add t1,t1,1744 # 40c0 + 9f8: 02900813 li a6,41 + 9fc: 919f8f9b addw t6,t6,-1767 # 1919 + a00: 0c887f57 vsetvli t5,a6,e16,m1,ta,ma + a04: 000f079b sext.w a5,t5 + a08: 02035507 vle16.v v10,(t1) + a0c: 020e5587 vle16.v v11,(t3) + a10: a6afe5d7 vmadd.vx v11,t6,v10 + a14: 020ed5a7 vse16.v v11,(t4) + a18: 00179793 sll a5,a5,0x1 + a1c: 41e8083b subw a6,a6,t5 + a20: 00f30333 add t1,t1,a5 + a24: 00fe0e33 add t3,t3,a5 + a28: 00fe8eb3 add t4,t4,a5 + a2c: fc081ae3 bnez a6,a00 + a30: 00002e37 lui t3,0x2 + a34: 00003e97 auipc t4,0x3 + a38: 67ee8e93 add t4,t4,1662 # 40b2 + a3c: 86818813 add a6,gp,-1944 # 4330 + a40: 919e0e1b addw t3,t3,-1767 # 1919 + a44: 0006d783 lhu a5,0(a3) + a48: 00065303 lhu t1,0(a2) + a4c: 00280813 add a6,a6,2 + a50: 02fe07bb mulw a5,t3,a5 + a54: 00268693 add a3,a3,2 + a58: 00260613 add a2,a2,2 + a5c: 006787bb addw a5,a5,t1 + a60: fef81f23 sh a5,-2(a6) + a64: fede90e3 bne t4,a3,a44 + a68: 00071683 lh a3,0(a4) + a6c: 00059783 lh a5,0(a1) + a70: 00270713 add a4,a4,2 + a74: 00258593 add a1,a1,2 + a78: 00f68463 beq a3,a5,a80 + a7c: 00000513 li a0,0 + a80: ff1714e3 bne a4,a7,a68 + a84: 00154513 xor a0,a0,1 + a88: 00008067 ret + a8c: fff00513 li a0,-1 + a90: 00008067 ret + +Disassembly of section .rodata: + +0000000000004000 : + 4000: de7f6f4f .4byte 0xde7f6f4f + 4004: 6560 vmsge.vx v10,v0,zero,v0.t + 4006: 7f28 .2byte 0x7f28 + 4008: d47bad0b .4byte 0xd47bad0b + 400c: 3561 vmsge.vx v10,v0,zero,v0.t + 400e: 4922134f .4byte 0x4922134f + 4012: f869 .2byte 0xf869 + 4014: e2be .2byte 0xe2be + 4016: 66655b7f 2fd0f487 .byte 0x7f, 0x5b, 0x65, 0x66, 0x87, 0xf4, 0xd0, 0x2f, 0x85, 0xa2, 0xf8, 0x25, 0xb9, 0x7f, 0x66, 0x6d, 0x55, 0xc4, 0xdb, 0x5f + 401e: 25f8a285 6d667fb9 + 4026: 5fdbc455 + 402a: 9789 .2byte 0x9789 + 402c: eb716457 vwmulsu.vx v8,v23,sp + 4030: 7b54 .2byte 0x7b54 + 4032: def2 .2byte 0xdef2 + 4034: 4301 vmsge.vx v6,v0,zero,v0.t + 4036: fd67d5cf .4byte 0xfd67d5cf + 403a: 71b8 .2byte 0x71b8 + 403c: 7b50 .2byte 0x7b50 + 403e: 3ed7a5a3 sw a3,1003(a5) + 4042: 7231 .2byte 0x7231 + 4044: 1c16 .2byte 0x1c16 + 4046: a8c5c137 lui sp,0xa8c5c + 404a: 8948 .2byte 0x8948 + 404c: 4769 .2byte 0x4769 + 404e: f820 vmsge.vx v16,v0,ra,v0.t + 4050: 72589fb7 lui t6,0x72589 + 4054: 4c0c .2byte 0x4c0c + 4056: 0a9e .2byte 0xa9e + 4058: 1240 vmsge.vx v4,v0,zero,v0.t + 405a: 2f0a .2byte 0x2f0a + 405c: 20f2 .2byte 0x20f2 + 405e: 920a .2byte 0x920a + +0000000000004060 : + 4060: 7729 .2byte 0x7729 + 4062: 4ec6 .2byte 0x4ec6 + 4064: 160e .2byte 0x160e + 4066: aa00 vmsge.vx v20,v0,ra,v0.t + 4068: b0d5 .2byte 0xb0d5 + 406a: be1a073b .4byte 0xbe1a073b + 406e: c35e .2byte 0xc35e + 4070: e6b2 .2byte 0xe6b2 + 4072: 6f98 .2byte 0x6f98 + 4074: de929e9b .4byte 0xde929e9b + 4078: 72e270db .4byte 0x72e270db + 407c: e9d8 .2byte 0xe9d8 + 407e: 9bf6 .2byte 0x9bf6 + 4080: 44dc .2byte 0x44dc + 4082: f1b6bdef jal s11,fffffffffff6ff9c <_end+0xffffffffeff6ff54> + 4086: 8df9 .2byte 0x8df9 + 4088: b8ba .2byte 0xb8ba + 408a: 1e11 .2byte 0x1e11 + 408c: 4132 .2byte 0x4132 + 408e: d955 .2byte 0xd955 + 4090: 1711 .2byte 0x1711 + 4092: 9a81 vmsge.vx v21,v0,ra,v0.t + 4094: 645f 190b fe67 .byte 0x5f, 0x64, 0x0b, 0x19, 0x67, 0xfe + 409a: 0438 .2byte 0x438 + 409c: 2255 .2byte 0x2255 + 409e: c2dea2b3 .4byte 0xc2dea2b3 + 40a2: 69ac .2byte 0x69ac + 40a4: dd7d .2byte 0xdd7d + 40a6: d433ccc3 vmsge.vx v25,v3,t2,v0.t + 40aa: 30c4 .2byte 0x30c4 + 40ac: 7639 .2byte 0x7639 + 40ae: ae61 vmsge.vx v28,v0,ra,v0.t + 40b0: 717f .2byte 0x717f + 40b2: a7bc8f9b addw t6,s9,-1413 + 40b6: 3df5 .2byte 0x3df5 + 40b8: 6b708b4f .4byte 0x6b708b4f + 40bc: 55c5 .2byte 0x55c5 + 40be: c9da .2byte 0xc9da + +00000000000040c0 : + 40c0: 968d .2byte 0x968d + 40c2: d593c97b .4byte 0xd593c97b + 40c6: 631e .2byte 0x631e + 40c8: b990 .2byte 0xb990 + 40ca: 5cbaad63 vmsge.vx v26,v11,s5,v0.t + 40ce: 5fe4 .2byte 0x5fe4 + 40d0: 9232 .2byte 0x9232 + 40d2: aa6a .2byte 0xaa6a + 40d4: 4186 .2byte 0x4186 + 40d6: 4d80d87b .4byte 0x4d80d87b + 40da: 31a7d16f jal sp,813f4 <__global_pointer$+0x7c92c> + 40de: a180 vmsge.vx v3,v0,ra,v0.t + 40e0: 6bc2 vmsge.vx v23,v0,zero,v0.t + 40e2: b1ac .2byte 0xb1ac + 40e4: b049 .2byte 0xb049 + 40e6: 3552 .2byte 0x3552 + 40e8: c256 .2byte 0xc256 + 40ea: 5275 .2byte 0x5275 + 40ec: 7cfe .2byte 0x7cfe + 40ee: 496c .2byte 0x496c + 40f0: d4a6 .2byte 0xd4a6 + 40f2: f964 .2byte 0xf964 + 40f4: 8da3049b addw s1,t1,-1830 + 40f8: bb15 .2byte 0xbb15 + 40fa: 975c .2byte 0x975c + 40fc: c4ad .2byte 0xc4ad + 40fe: cdac .2byte 0xcdac + 4100: add7e053 .4byte 0xadd7e053 + 4104: 529c8f93 add t6,s9,1321 + 4108: 969c .2byte 0x969c + 410a: 601d .2byte 0x601d + 410c: 14ce39a7 .4byte 0x14ce39a7 + 4110: 7f38 .2byte 0x7f38 + 4112: 3884 .2byte 0x3884 + 4114: 8d44 .2byte 0x8d44 + 4116: f1809d8b .4byte 0xf1809d8b + 411a: 2f01 vmsge.vx v30,v0,zero,v0.t + 411c: ca10 .2byte 0xca10 + 411e: 3bc0 vmsge.vx v23,v0,zero,v0.t + 4120: c3c0 vmsge.vx v7,v0,ra,v0.t + 4122: ffff .2byte 0xffff + 4124: c404 .2byte 0xc404 + 4126: ffff .2byte 0xffff + 4128: c448 .2byte 0xc448 + 412a: ffff .2byte 0xffff + 412c: c358 .2byte 0xc358 + 412e: ffff .2byte 0xffff + 4130: c48c .2byte 0xc48c + 4132: ffff .2byte 0xffff + 4134: c4d0 .2byte 0xc4d0 + 4136: ffff .2byte 0xffff + 4138: c514 .2byte 0xc514 + 413a: ffff .2byte 0xffff + 413c: c558 .2byte 0xc558 + 413e: ffff .2byte 0xffff + 4140: c358 .2byte 0xc358 + 4142: ffff .2byte 0xffff + 4144: c358 .2byte 0xc358 + 4146: ffff .2byte 0xffff + 4148: c358 .2byte 0xc358 + 414a: ffff .2byte 0xffff + 414c: c59c .2byte 0xc59c + 414e: ffff .2byte 0xffff + +Disassembly of section .rodata.str1.8: + +0000000000004150 <.rodata.str1.8>: + 4150: 6c637963 bgeu t1,t1,4822 <_tbss_end+0x492> + 4154: 3a65 .2byte 0x3a65 + 4156: 0020 vmsge.vx v0,v0,zero,v0.t + 4158: 690a .2byte 0x690a + 415a: 736e .2byte 0x736e + 415c: 7274 .2byte 0x7274 + 415e: 7465 .2byte 0x7465 + 4160: 203a .2byte 0x203a + 4162: 0000 vmsge.vx v0,v0,zero,v0.t + 4164: 0000 vmsge.vx v0,v0,zero,v0.t + 4166: 0000 vmsge.vx v0,v0,zero,v0.t + 4168: 7845 .2byte 0x7845 + 416a: 7469 .2byte 0x7469 + 416c: 6320 vmsge.vx v6,v0,zero,v0.t + 416e: 3a65646f jal s0,5a514 <__global_pointer$+0x55a4c> + 4172: 0020 vmsge.vx v0,v0,zero,v0.t + 4174: 0000 vmsge.vx v0,v0,zero,v0.t + 4176: 0000 vmsge.vx v0,v0,zero,v0.t + 4178: 4e49 .2byte 0x4e49 + 417a: 55525453 .4byte 0x55525453 + 417e: 4f495443 vmsge.vx v8,v20,s2 + 4182: 204e .2byte 0x204e + 4184: 4441 vmsge.vx v8,v0,zero,v0.t + 4186: 5244 .2byte 0x5244 + 4188: 5345 .2byte 0x5345 + 418a: 494d2053 .4byte 0x494d2053 + 418e: 494c4153 .4byte 0x494c4153 + 4192: 44454e47 .4byte 0x44454e47 + 4196: 6120 vmsge.vx v2,v0,zero,v0.t + 4198: 2074 .2byte 0x2074 + 419a: 4350 .2byte 0x4350 + 419c: 203a .2byte 0x203a + 419e: 0000 vmsge.vx v0,v0,zero,v0.t + 41a0: 4e49 .2byte 0x4e49 + 41a2: 55525453 .4byte 0x55525453 + 41a6: 4f495443 vmsge.vx v8,v20,s2 + 41aa: 204e .2byte 0x204e + 41ac: 4341 vmsge.vx v6,v0,zero,v0.t + 41ae: 53534543 vmsge.vx v10,v21,t1 + 41b2: 4620 vmsge.vx v12,v0,zero,v0.t + 41b4: 5541 vmsge.vx v10,v0,zero,v0.t + 41b6: 544c .2byte 0x544c + 41b8: 6120 vmsge.vx v2,v0,zero,v0.t + 41ba: 2074 .2byte 0x2074 + 41bc: 4350 .2byte 0x4350 + 41be: 203a .2byte 0x203a + ... + 41c8: 4c49 .2byte 0x4c49 + 41ca: 454c .2byte 0x454c + 41cc: 204c4147 .4byte 0x204c4147 + 41d0: 4e49 .2byte 0x4e49 + 41d2: 55525453 .4byte 0x55525453 + 41d6: 4f495443 vmsge.vx v8,v20,s2 + 41da: 204e .2byte 0x204e + 41dc: 7461 vmsge.vx v8,v0,zero,v0.t + 41de: 5020 vmsge.vx v0,v0,zero,v0.t + 41e0: 00203a43 vmsge.vx v20,v2,zero,v0.t + 41e4: 0000 vmsge.vx v0,v0,zero,v0.t + 41e6: 0000 vmsge.vx v0,v0,zero,v0.t + 41e8: 4f4c .2byte 0x4f4c + 41ea: 4441 vmsge.vx v8,v0,zero,v0.t + 41ec: 4120 vmsge.vx v2,v0,zero,v0.t + 41ee: 4444 .2byte 0x4444 + 41f0: 4552 .2byte 0x4552 + 41f2: 4d205353 .4byte 0x4d205353 + 41f6: 5349 .2byte 0x5349 + 41f8: 4c41 vmsge.vx v24,v0,zero,v0.t + 41fa: 4749 .2byte 0x4749 + 41fc: 454e .2byte 0x454e + 41fe: 2044 .2byte 0x2044 + 4200: 7461 vmsge.vx v8,v0,zero,v0.t + 4202: 5020 vmsge.vx v0,v0,zero,v0.t + 4204: 00203a43 vmsge.vx v20,v2,zero,v0.t + 4208: 4f4c .2byte 0x4f4c + 420a: 4441 vmsge.vx v8,v0,zero,v0.t + 420c: 4120 vmsge.vx v2,v0,zero,v0.t + 420e: 53454343 vmsge.vx v6,v20,a0 + 4212: 41462053 .4byte 0x41462053 + 4216: 4c55 .2byte 0x4c55 + 4218: 2054 .2byte 0x2054 + 421a: 7461 vmsge.vx v8,v0,zero,v0.t + 421c: 5020 vmsge.vx v0,v0,zero,v0.t + 421e: 00203a43 vmsge.vx v20,v2,zero,v0.t + 4222: 0000 vmsge.vx v0,v0,zero,v0.t + 4224: 0000 vmsge.vx v0,v0,zero,v0.t + 4226: 0000 vmsge.vx v0,v0,zero,v0.t + 4228: 524f5453 .4byte 0x524f5453 + 422c: 2045 .2byte 0x2045 + 422e: 4441 vmsge.vx v8,v0,zero,v0.t + 4230: 5244 .2byte 0x5244 + 4232: 5345 .2byte 0x5345 + 4234: 494d2053 .4byte 0x494d2053 + 4238: 494c4153 .4byte 0x494c4153 + 423c: 44454e47 .4byte 0x44454e47 + 4240: 6120 vmsge.vx v2,v0,zero,v0.t + 4242: 2074 .2byte 0x2074 + 4244: 4350 .2byte 0x4350 + 4246: 203a .2byte 0x203a + ... + 4250: 524f5453 .4byte 0x524f5453 + 4254: 2045 .2byte 0x2045 + 4256: 4341 vmsge.vx v6,v0,zero,v0.t + 4258: 53534543 vmsge.vx v10,v21,t1 + 425c: 4620 vmsge.vx v12,v0,zero,v0.t + 425e: 5541 vmsge.vx v10,v0,zero,v0.t + 4260: 544c .2byte 0x544c + 4262: 6120 vmsge.vx v2,v0,zero,v0.t + 4264: 2074 .2byte 0x2074 + 4266: 4350 .2byte 0x4350 + 4268: 203a .2byte 0x203a + 426a: 0000 vmsge.vx v0,v0,zero,v0.t + 426c: 0000 vmsge.vx v0,v0,zero,v0.t + 426e: 0000 vmsge.vx v0,v0,zero,v0.t + 4270: 4345 .2byte 0x4345 + 4272: 4c41 vmsge.vx v24,v0,zero,v0.t + 4274: 204c .2byte 0x204c + 4276: 5246 .2byte 0x5246 + 4278: 4d204d4f .4byte 0x4d204d4f + 427c: 4d2d .2byte 0x4d2d + 427e: 2045444f .4byte 0x2045444f + 4282: 7461 vmsge.vx v8,v0,zero,v0.t + 4284: 5020 vmsge.vx v0,v0,zero,v0.t + 4286: 00203a43 vmsge.vx v20,v2,zero,v0.t + 428a: 0000 vmsge.vx v0,v0,zero,v0.t + 428c: 0000 vmsge.vx v0,v0,zero,v0.t + 428e: 0000 vmsge.vx v0,v0,zero,v0.t + 4290: 4e55 .2byte 0x4e55 + 4292: 574f4e4b .4byte 0x574f4e4b + 4296: 204e .2byte 0x204e + 4298: 5845 .2byte 0x5845 + 429a: 54504543 vmsge.vx v10,v5,zero,v0.t + 429e: 4f49 .2byte 0x4f49 + 42a0: 204e .2byte 0x204e + 42a2: 7461 vmsge.vx v8,v0,zero,v0.t + 42a4: 5020 vmsge.vx v0,v0,zero,v0.t + 42a6: 00203a43 vmsge.vx v20,v2,zero,v0.t + 42aa: 0000 vmsge.vx v0,v0,zero,v0.t + 42ac: 0000 vmsge.vx v0,v0,zero,v0.t + 42ae: 0000 vmsge.vx v0,v0,zero,v0.t + 42b0: 430a .2byte 0x430a + 42b2: 4548 .2byte 0x4548 + 42b4: 4d204b43 vmsge.vx v22,v18,zero,v0.t + 42b8: 53554143 vmsge.vx v2,v21,a0 + 42bc: 2045 .2byte 0x2045 + 42be: 6e69 .2byte 0x6e69 + 42c0: 5220 vmsge.vx v4,v0,zero,v0.t + 42c2: 4c54 .2byte 0x4c54 + ... + +Disassembly of section .sdata: + +00000000000042c8 <__global_pointer$-0x800>: + 42c8: 0101 vmsge.vx v2,v0,zero,v0.t + 42ca: 0101 vmsge.vx v2,v0,zero,v0.t + 42cc: 0101 vmsge.vx v2,v0,zero,v0.t + 42ce: 0101 vmsge.vx v2,v0,zero,v0.t + +Disassembly of section .bss: + +00000000000042d0 : + ... + +0000000000004330 : + ... + +Disassembly of section .tohost: + +0000000010000000 : + ... + +0000000010000040 : + ... + +Disassembly of section .comment: + +0000000000000000 <.comment>: + 0: 3a434347 .4byte 0x3a434347 + 4: 2820 vmsge.vx v16,v0,zero,v0.t + 6: 65653267 .4byte 0x65653267 + a: 6535 .2byte 0x6535 + c: 3334 .2byte 0x3334 + e: 3030 .2byte 0x3030 + 10: 3831 .2byte 0x3831 + 12: 2029 .2byte 0x2029 + 14: 3231 .2byte 0x3231 + 16: 322e .2byte 0x322e + 18: 302e .2byte 0x302e + ... + +Disassembly of section .riscv.attributes: + +0000000000000000 <.riscv.attributes>: + 0: 5e41 vmsge.vx v28,v0,zero,v0.t + 2: 0000 vmsge.vx v0,v0,zero,v0.t + 4: 7200 vmsge.vx v4,v0,zero,v0.t + 6: 7369 .2byte 0x7369 + 8: 01007663 bgeu zero,a6,14 <_start+0x14> + c: 0054 .2byte 0x54 + e: 0000 vmsge.vx v0,v0,zero,v0.t + 10: 1004 .2byte 0x1004 + 12: 7205 .2byte 0x7205 + 14: 3676 .2byte 0x3676 + 16: 6934 .2byte 0x6934 + 18: 7032 .2byte 0x7032 + 1a: 5f31 .2byte 0x5f31 + 1c: 326d .2byte 0x326d + 1e: 3070 .2byte 0x3070 + 20: 7a5f 6369 7273 .byte 0x5f, 0x7a, 0x69, 0x63, 0x73, 0x72 + 26: 7032 .2byte 0x7032 + 28: 5f30 .2byte 0x5f30 + 2a: 6d7a .2byte 0x6d7a + 2c: 756d .2byte 0x756d + 2e: 316c .2byte 0x316c + 30: 3070 .2byte 0x3070 + 32: 7a5f 6576 3233 .byte 0x5f, 0x7a, 0x76, 0x65, 0x33, 0x32 + 38: 3178 .2byte 0x3178 + 3a: 3070 .2byte 0x3070 + 3c: 7a5f 6576 3436 .byte 0x5f, 0x7a, 0x76, 0x65, 0x36, 0x34 + 42: 3178 .2byte 0x3178 + 44: 3070 .2byte 0x3070 + 46: 7a5f 6c76 3233 .byte 0x5f, 0x7a, 0x76, 0x6c, 0x33, 0x32 + 4c: 3162 vmsge.vx v2,v0,zero,v0.t + 4e: 3070 .2byte 0x3070 + 50: 7a5f 6c76 3436 .byte 0x5f, 0x7a, 0x76, 0x6c, 0x36, 0x34 + 56: 3162 vmsge.vx v2,v0,zero,v0.t + 58: 3070 .2byte 0x3070 + 5a: 0800 vmsge.vx v16,v0,zero,v0.t + 5c: 0a01 vmsge.vx v20,v0,zero,v0.t + 5e: 0b Address 0x5e is out of bounds. + diff --git a/src/main/resources/applications_vector/vmadd/vmadd.c b/src/main/resources/applications_vector/vmadd/vmadd.c new file mode 100644 index 00000000..43141846 --- /dev/null +++ b/src/main/resources/applications_vector/vmadd/vmadd.c @@ -0,0 +1,95 @@ +#include "util.h" + +#define size_t long +#define N 48 + +const signed short dataArray0[N] = {-26995, -13957, -10861, 25374, -18032, -21149, 23738, 24548, -28110, -21910, 16774, -10117, 19840, -11921, 12711, -24192, 27586, -20052, -20407, 13650, -15786, 21109, 31998, 18796, -11098, -1692, 1179, -29277, -17643, -26788, -15187, -12884, -8109, -21033, -28781, 21148, -26980, 24605, 14759, 5326, 32568, 14468, -29372, -25205, -3712, 12033, -13808, 15296}; +const signed short dataArray1[N] = {30505, 20166, 5646, -22016, -20267, 1851, -16870, -15522, -6478, 28568, -24933, -8558, 28891, 29410, -5672, -25610, 17628, -16913, -3658, -29191, -18246, 7697, 16690, -9899, 5905, -25983, 25695, 6411, -409, 1080, 8789, -23885, -15650, 27052, -8835, -13117, -11213, 12484, 30265, -20895, 29055, -28773, -22596, 15861, -29873, 27504, 21957, -13862}; +const signed short dataArray2[N] = {28495, -8577, 25952, 32552, -21237, -11141, 13665, 4943, 18722, -1943, -7490, 23423, 26213, -2937, 12240, -23931, 9720, 32697, 28006, -15275, 24539, -26743, 25687, -5263, 31572, -8462, 17153, -10801, -665, 29112, 31568, -23133, 16087, 29233, 7190, -16073, -22331, -30392, 18281, -2016, -24649, 29272, 19468, 2718, 4672, 12042, 8434, -28150}; +signed short resultArray[N] = {0}; +signed short answerArray[N] = {0}; + +extern void printstr(char* str); +extern void int64ToHex(long num, char* str); +extern void int32ToHex(int num, char* str); +extern void clearCounters(); +extern void printCounters(); + +int main(int argc, char** argv) { + int vl, avl = 41; + const signed short *ptr0 = dataArray0; + const signed short *ptr1 = dataArray1; + const signed short *ptr2 = dataArray2; + signed short *ptr3 = resultArray; + while(avl != 0) { + asm volatile ("vsetvli %0, %1, e16, m1, ta, ma" + : "=r"(vl) + : "r"(avl)); + // asm volatile ("li t0, 0x1919"); + asm volatile ("vle16.v v10, (%0)" + : + : "r"(ptr0)); + asm volatile ("vle16.v v11, (%0)" + : + : "r"(ptr1)); + asm volatile ("vle16.v v12, (%0)" + : + : "r"(ptr2)); + // v12 = v10 * v12 + v11 + asm volatile ("vmadd.vv v12, v10, v11"); + asm volatile ("vse16.v v12, (%0)" + : + : "r"(ptr3)); + ptr0 += vl; + ptr1 += vl; + ptr2 += vl; + ptr3 += vl; + avl -= vl; + } + int i; + for(i=0; i<41; i++) { + answerArray[i] = dataArray0[i] * dataArray2[i] + dataArray1[i]; + } + + _Bool correct = 1; + for(i=0; i<41; i++) { + if(resultArray[i] != answerArray[i]) { + correct = 0; + } + } + avl = 41; + ptr0 = dataArray0; + ptr1 = dataArray1; + ptr3 = resultArray; + while(avl != 0) { + asm volatile ("vsetvli %0, %1, e16, m1, ta, ma" + : "=r"(vl) + : "r"(avl)); + asm volatile ("vle16.v v10, (%0)" + : + : "r"(ptr0)); + asm volatile ("vle16.v v11, (%0)" + : + : "r"(ptr1)); + // v11 = 0x1919 * v11 + v10 + asm volatile ("vmadd.vx v11, %0, v10" + : + : "r"(0x1919)); + asm volatile ("vse16.v v11, (%0)" + : + : "r"(ptr3)); + ptr0 += vl; + ptr1 += vl; + ptr3 += vl; + avl -= vl; + } + for(i=0; i<41; i++) { + answerArray[i] = 0x1919 * dataArray1[i] + dataArray0[i]; + } + for(i=0; i<41; i++) { + if(resultArray[i] != answerArray[i]) { + correct = 0; + } + } + return !correct; +} diff --git a/src/main/resources/applications_vector/vmadd_data.hex b/src/main/resources/applications_vector/vmadd_data.hex new file mode 100644 index 00000000..76ca0b6b --- /dev/null +++ b/src/main/resources/applications_vector/vmadd_data.hex @@ -0,0 +1,180 @@ +de7f6f4f +7f286560 +d47bad0b +134f3561 +f8694922 +5b7fe2be +f4876665 +a2852fd0 +7fb925f8 +c4556d66 +97895fdb +eb716457 +def27b54 +d5cf4301 +71b8fd67 +a5a37b50 +72313ed7 +c1371c16 +8948a8c5 +f8204769 +72589fb7 +0a9e4c0c +2f0a1240 +920a20f2 +4ec67729 +aa00160e +073bb0d5 +c35ebe1a +6f98e6b2 +de929e9b +72e270db +9bf6e9d8 +bdef44dc +8df9f1b6 +1e11b8ba +d9554132 +9a811711 +190b645f +0438fe67 +a2b32255 +69acc2de +ccc3dd7d +30c4d433 +ae617639 +8f9b717f +3df5a7bc +6b708b4f +c9da55c5 +c97b968d +631ed593 +ad63b990 +5fe45cba +aa6a9232 +d87b4186 +d16f4d80 +a18031a7 +b1ac6bc2 +3552b049 +5275c256 +496c7cfe +f964d4a6 +8da3049b +975cbb15 +cdacc4ad +add7e053 +529c8f93 +601d969c +14ce39a7 +38847f38 +9d8b8d44 +2f01f180 +3bc0ca10 +ffffc3c0 +ffffc404 +ffffc448 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+6e692045 +4c545220 +00000000 +01010101 +01010101 diff --git a/src/main/resources/applications_vector/vmadd_inst.hex b/src/main/resources/applications_vector/vmadd_inst.hex new file mode 100644 index 00000000..685c5d79 --- /dev/null +++ b/src/main/resources/applications_vector/vmadd_inst.hex @@ -0,0 +1,677 @@ +00000093 +00000113 +00000193 +00000213 +00000293 +00000313 +00000393 +00000413 +00000493 +00000513 +00000593 +00000613 +00000693 +00000713 +00000793 +00000813 +00000893 +00000913 +00000993 +00000a13 +00000a93 +00000b13 +00000b93 +00000c13 +00000c93 +00000d13 +00000d93 +00000e13 +00000e93 +00000f13 +00000f93 +00000297 +03828293 +30529073 +00005197 +a4018193 +10000217 +ff720213 +fc027213 +f1402573 +00100593 +00b57063 +00006137 +ff01011b +6580006f +ef010113 +00113423 +00213823 +00313c23 +02413023 +02513423 +02613823 +02713c23 +04813023 +04913423 +04a13823 +04b13c23 +06c13023 +06d13423 +06e13823 +06f13c23 +09013023 +09113423 +09213823 +09313c23 +0b413023 +0b513423 +0b613823 +0b713c23 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+00258593 +00f68463 +00000513 +ff1714e3 +00154513 +00008067 +fff00513 +00008067 diff --git a/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala b/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala index b9e2fa60..a4d7997b 100644 --- a/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala +++ b/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala @@ -140,7 +140,7 @@ class Zve64xAppTestForVecCpu extends AnyFlatSpec with ChiselScalatestTester { "vminmax", "vmerge", "vmv", "vmand", "vmor", "vmxor", "vmul", "vmulh", "vmulhu", "vmulhsu", - "vmacc", "vnmsac", + "vmacc", "vnmsac", "vmadd", ) val applicationTest = Seq( "vector_median" From b06bdd24102b5356cc90d2ec9046632b2e1bc16a Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Mon, 13 Nov 2023 14:05:31 +0900 Subject: [PATCH 07/14] vnmsub --- .../resources/applications_vector/build.sh | 17 + .../resources/applications_vector/vnmsub.dump | 1096 +++++++++++++++++ .../applications_vector/vnmsub/vnmsub.c | 95 ++ .../applications_vector/vnmsub_data.hex | 180 +++ .../applications_vector/vnmsub_inst.hex | 675 ++++++++++ .../hajime/vectormodules/VectorCpuSpec.scala | 2 +- 6 files changed, 2064 insertions(+), 1 deletion(-) create mode 100644 src/main/resources/applications_vector/vnmsub.dump create mode 100644 src/main/resources/applications_vector/vnmsub/vnmsub.c create mode 100644 src/main/resources/applications_vector/vnmsub_data.hex create mode 100644 src/main/resources/applications_vector/vnmsub_inst.hex diff --git a/src/main/resources/applications_vector/build.sh b/src/main/resources/applications_vector/build.sh index 986580dc..1f2fe07e 100644 --- a/src/main/resources/applications_vector/build.sh +++ b/src/main/resources/applications_vector/build.sh @@ -484,4 +484,21 @@ hexdump -v -e '1/4 "%08x" "\n"' vmadd_text_startup.bin > vmadd_text_startup.temp cat vmadd_rodata.temp vmadd_rodata_str1_8.temp vmadd_sdata.temp > vmadd_data.hex cat vmadd_text_init.temp vmadd_text.temp vmadd_text_startup.temp > vmadd_inst.hex +riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vnmsub.riscv ./vnmsub/vnmsub.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld +riscv64-unknown-elf-objdump --disassemble-all vnmsub.riscv > vnmsub.dump +riscv64-unknown-elf-objcopy --dump-section .rodata=vnmsub_rodata.bin vnmsub.riscv +riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vnmsub_rodata_str1_8.bin vnmsub.riscv +riscv64-unknown-elf-objcopy --dump-section .sdata=vnmsub_sdata.bin vnmsub.riscv +riscv64-unknown-elf-objcopy --dump-section .text.init=vnmsub_text_init.bin vnmsub.riscv +riscv64-unknown-elf-objcopy --dump-section .text=vnmsub_text.bin vnmsub.riscv +riscv64-unknown-elf-objcopy --dump-section .text.startup=vnmsub_text_startup.bin vnmsub.riscv +hexdump -v -e '1/4 "%08x" "\n"' vnmsub_rodata.bin > vnmsub_rodata.temp +hexdump -v -e '1/4 "%08x" "\n"' vnmsub_rodata_str1_8.bin > vnmsub_rodata_str1_8.temp +hexdump -v -e '1/4 "%08x" "\n"' vnmsub_sdata.bin > vnmsub_sdata.temp +hexdump -v -e '1/4 "%08x" "\n"' vnmsub_text_init.bin > vnmsub_text_init.temp +hexdump -v -e '1/4 "%08x" "\n"' vnmsub_text.bin > vnmsub_text.temp +hexdump -v -e '1/4 "%08x" "\n"' vnmsub_text_startup.bin > vnmsub_text_startup.temp +cat vnmsub_rodata.temp vnmsub_rodata_str1_8.temp vnmsub_sdata.temp > vnmsub_data.hex +cat vnmsub_text_init.temp vnmsub_text.temp vnmsub_text_startup.temp > vnmsub_inst.hex + rm *.riscv *.bin *.temp \ No newline at end of file diff --git a/src/main/resources/applications_vector/vnmsub.dump b/src/main/resources/applications_vector/vnmsub.dump new file mode 100644 index 00000000..510e9f98 --- /dev/null +++ b/src/main/resources/applications_vector/vnmsub.dump @@ -0,0 +1,1096 @@ + +vnmsub.riscv: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000000000000 <_start>: + 0: 00000093 li ra,0 + 4: 00000113 li sp,0 + 8: 00000193 li gp,0 + c: 00000213 li tp,0 + 10: 00000293 li t0,0 + 14: 00000313 li t1,0 + 18: 00000393 li t2,0 + 1c: 00000413 li s0,0 + 20: 00000493 li s1,0 + 24: 00000513 li a0,0 + 28: 00000593 li a1,0 + 2c: 00000613 li a2,0 + 30: 00000693 li a3,0 + 34: 00000713 li a4,0 + 38: 00000793 li a5,0 + 3c: 00000813 li a6,0 + 40: 00000893 li a7,0 + 44: 00000913 li s2,0 + 48: 00000993 li s3,0 + 4c: 00000a13 li s4,0 + 50: 00000a93 li s5,0 + 54: 00000b13 li s6,0 + 58: 00000b93 li s7,0 + 5c: 00000c13 li s8,0 + 60: 00000c93 li s9,0 + 64: 00000d13 li s10,0 + 68: 00000d93 li s11,0 + 6c: 00000e13 li t3,0 + 70: 00000e93 li t4,0 + 74: 00000f13 li t5,0 + 78: 00000f93 li t6,0 + 7c: 00000297 auipc t0,0x0 + 80: 03828293 add t0,t0,56 # b4 + 84: 30529073 csrw mtvec,t0 + 88: 00005197 auipc gp,0x5 + 8c: a4018193 add gp,gp,-1472 # 4ac8 <__global_pointer$> + 90: 10000217 auipc tp,0x10000 + 94: ff720213 add tp,tp,-9 # 10000087 <_end+0x3f> + 98: fc027213 and tp,tp,-64 + 9c: f1402573 csrr a0,mhartid + a0: 00100593 li a1,1 + a4: 00b57063 bgeu a0,a1,a4 <_start+0xa4> + a8: 00006137 lui sp,0x6 + ac: ff01011b addw sp,sp,-16 # 5ff0 <__global_pointer$+0x1528> + b0: 6580006f j 708 <_init> + +00000000000000b4 : + b4: ef010113 add sp,sp,-272 + b8: 00113423 sd ra,8(sp) + bc: 00213823 sd sp,16(sp) + c0: 00313c23 sd gp,24(sp) + c4: 02413023 sd tp,32(sp) + c8: 02513423 sd t0,40(sp) + cc: 02613823 sd t1,48(sp) + d0: 02713c23 sd t2,56(sp) + d4: 04813023 sd s0,64(sp) + d8: 04913423 sd s1,72(sp) + dc: 04a13823 sd a0,80(sp) + e0: 04b13c23 sd a1,88(sp) + e4: 06c13023 sd a2,96(sp) + e8: 06d13423 sd a3,104(sp) + ec: 06e13823 sd a4,112(sp) + f0: 06f13c23 sd a5,120(sp) + f4: 09013023 sd a6,128(sp) + f8: 09113423 sd a7,136(sp) + fc: 09213823 sd s2,144(sp) + 100: 09313c23 sd s3,152(sp) + 104: 0b413023 sd s4,160(sp) + 108: 0b513423 sd s5,168(sp) + 10c: 0b613823 sd s6,176(sp) + 110: 0b713c23 sd s7,184(sp) + 114: 0d813023 sd s8,192(sp) + 118: 0d913423 sd s9,200(sp) + 11c: 0da13823 sd s10,208(sp) + 120: 0db13c23 sd s11,216(sp) + 124: 0fc13023 sd t3,224(sp) + 128: 0fd13423 sd t4,232(sp) + 12c: 0fe13823 sd t5,240(sp) + 130: 0ff13c23 sd t6,248(sp) + 134: 34202573 csrr a0,mcause + 138: 341025f3 csrr a1,mepc + 13c: 00010613 mv a2,sp + 140: 2d0000ef jal 410 + 144: 34151073 csrw mepc,a0 + 148: 000022b7 lui t0,0x2 + 14c: 8002829b addw t0,t0,-2048 # 1800 + 150: 3002a073 csrs mstatus,t0 + 154: 00813083 ld ra,8(sp) + 158: 01013103 ld sp,16(sp) + 15c: 01813183 ld gp,24(sp) + 160: 02013203 ld tp,32(sp) + 164: 02813283 ld t0,40(sp) + 168: 03013303 ld t1,48(sp) + 16c: 03813383 ld t2,56(sp) + 170: 04013403 ld s0,64(sp) + 174: 04813483 ld s1,72(sp) + 178: 05013503 ld a0,80(sp) + 17c: 05813583 ld a1,88(sp) + 180: 06013603 ld a2,96(sp) + 184: 06813683 ld a3,104(sp) + 188: 07013703 ld a4,112(sp) + 18c: 07813783 ld a5,120(sp) + 190: 08013803 ld a6,128(sp) + 194: 08813883 ld a7,136(sp) + 198: 09013903 ld s2,144(sp) + 19c: 09813983 ld s3,152(sp) + 1a0: 0a013a03 ld s4,160(sp) + 1a4: 0a813a83 ld s5,168(sp) + 1a8: 0b013b03 ld s6,176(sp) + 1ac: 0b813b83 ld s7,184(sp) + 1b0: 0c013c03 ld s8,192(sp) + 1b4: 0c813c83 ld s9,200(sp) + 1b8: 0d013d03 ld s10,208(sp) + 1bc: 0d813d83 ld s11,216(sp) + 1c0: 0e013e03 ld t3,224(sp) + 1c4: 0e813e83 ld t4,232(sp) + 1c8: 0f013f03 ld t5,240(sp) + 1cc: 0f813f83 ld t6,248(sp) + 1d0: 11010113 add sp,sp,272 + 1d4: 30200073 mret + +Disassembly of section .text: + +00000000000001d8 : + 1d8: b0201073 csrw minstret,zero + 1dc: b0001073 csrw mcycle,zero + 1e0: 00008067 ret + +00000000000001e4 : + 1e4: 03000793 li a5,48 + 1e8: 00f58023 sb a5,0(a1) + 1ec: 07800793 li a5,120 + 1f0: 00f580a3 sb a5,1(a1) + 1f4: 00158813 add a6,a1,1 + 1f8: 00958793 add a5,a1,9 + 1fc: 00900613 li a2,9 + 200: 00f57713 and a4,a0,15 + 204: 03770693 add a3,a4,55 + 208: 00e66463 bltu a2,a4,210 + 20c: 03070693 add a3,a4,48 + 210: 00d78023 sb a3,0(a5) + 214: fff78793 add a5,a5,-1 + 218: 40455513 sra a0,a0,0x4 + 21c: fef812e3 bne a6,a5,200 + 220: 00058523 sb zero,10(a1) + 224: 00008067 ret + +0000000000000228 : + 228: 03000793 li a5,48 + 22c: 00f58023 sb a5,0(a1) + 230: 07800793 li a5,120 + 234: 00f580a3 sb a5,1(a1) + 238: 00158813 add a6,a1,1 + 23c: 01158793 add a5,a1,17 + 240: 00900613 li a2,9 + 244: 00f57713 and a4,a0,15 + 248: 03770693 add a3,a4,55 + 24c: 00e66463 bltu a2,a4,254 + 250: 03070693 add a3,a4,48 + 254: 00d78023 sb a3,0(a5) + 258: fff78793 add a5,a5,-1 + 25c: 40455513 sra a0,a0,0x4 + 260: fef812e3 bne a6,a5,244 + 264: 00058923 sb zero,18(a1) + 268: 00008067 ret + +000000000000026c : + 26c: 00054783 lbu a5,0(a0) + 270: 00078c63 beqz a5,288 + 274: 10000737 lui a4,0x10000 + 278: 00f70023 sb a5,0(a4) # 10000000 + 27c: 00154783 lbu a5,1(a0) + 280: 00150513 add a0,a0,1 + 284: fe079ae3 bnez a5,278 + 288: 00008067 ret + +000000000000028c : + 28c: fe010113 add sp,sp,-32 + 290: c0202673 rdinstret a2 + 294: c00025f3 rdcycle a1 + 298: 00004717 auipc a4,0x4 + 29c: eb870713 add a4,a4,-328 # 4150 + 2a0: 06300793 li a5,99 + 2a4: 100006b7 lui a3,0x10000 + 2a8: 00f68023 sb a5,0(a3) # 10000000 + 2ac: 00174783 lbu a5,1(a4) + 2b0: 00170713 add a4,a4,1 + 2b4: fe079ae3 bnez a5,2a8 + 2b8: ffff8737 lui a4,0xffff8 + 2bc: 83074713 xor a4,a4,-2000 + 2c0: 01910793 add a5,sp,25 + 2c4: 00e11423 sh a4,8(sp) + 2c8: 00910813 add a6,sp,9 + 2cc: 00078713 mv a4,a5 + 2d0: 00900893 li a7,9 + 2d4: 00f5f693 and a3,a1,15 + 2d8: 03768513 add a0,a3,55 + 2dc: 00d8e463 bltu a7,a3,2e4 + 2e0: 03068513 add a0,a3,48 + 2e4: 00a70023 sb a0,0(a4) # ffffffffffff8000 <_end+0xffffffffefff7fb8> + 2e8: fff70713 add a4,a4,-1 + 2ec: 4045d593 sra a1,a1,0x4 + 2f0: fee812e3 bne a6,a4,2d4 + 2f4: 00814703 lbu a4,8(sp) + 2f8: 00010d23 sb zero,26(sp) + 2fc: 00810693 add a3,sp,8 + 300: 100005b7 lui a1,0x10000 + 304: 00070a63 beqz a4,318 + 308: 00e58023 sb a4,0(a1) # 10000000 + 30c: 0016c703 lbu a4,1(a3) + 310: 00168693 add a3,a3,1 + 314: fe071ae3 bnez a4,308 + 318: 00004697 auipc a3,0x4 + 31c: e4068693 add a3,a3,-448 # 4158 + 320: 00a00713 li a4,10 + 324: 100005b7 lui a1,0x10000 + 328: 00e58023 sb a4,0(a1) # 10000000 + 32c: 0016c703 lbu a4,1(a3) + 330: 00168693 add a3,a3,1 + 334: fe071ae3 bnez a4,328 + 338: ffff8737 lui a4,0xffff8 + 33c: 83074713 xor a4,a4,-2000 + 340: 00060693 mv a3,a2 + 344: 00e11423 sh a4,8(sp) + 348: 00900593 li a1,9 + 34c: 00f6f713 and a4,a3,15 + 350: 03770613 add a2,a4,55 # ffffffffffff8037 <_end+0xffffffffefff7fef> + 354: 00e5e463 bltu a1,a4,35c + 358: 03070613 add a2,a4,48 + 35c: 00c78023 sb a2,0(a5) + 360: fff78793 add a5,a5,-1 + 364: 4046d693 sra a3,a3,0x4 + 368: fef812e3 bne a6,a5,34c + 36c: 00814783 lbu a5,8(sp) + 370: 00010d23 sb zero,26(sp) + 374: 00810713 add a4,sp,8 + 378: 100006b7 lui a3,0x10000 + 37c: 00078a63 beqz a5,390 + 380: 00f68023 sb a5,0(a3) # 10000000 + 384: 00174783 lbu a5,1(a4) + 388: 00170713 add a4,a4,1 + 38c: fe079ae3 bnez a5,380 + 390: 100007b7 lui a5,0x10000 + 394: 00a00713 li a4,10 + 398: 00e78023 sb a4,0(a5) # 10000000 + 39c: 02010113 add sp,sp,32 + 3a0: 00008067 ret + +00000000000003a4 : + 3a4: fe010113 add sp,sp,-32 + 3a8: 00813823 sd s0,16(sp) + 3ac: 00113c23 sd ra,24(sp) + 3b0: 00050413 mv s0,a0 + 3b4: 00004717 auipc a4,0x4 + 3b8: db470713 add a4,a4,-588 # 4168 + 3bc: 04500793 li a5,69 + 3c0: 100006b7 lui a3,0x10000 + 3c4: 00f68023 sb a5,0(a3) # 10000000 + 3c8: 00174783 lbu a5,1(a4) + 3cc: 00170713 add a4,a4,1 + 3d0: fe079ae3 bnez a5,3c4 + 3d4: 00010593 mv a1,sp + 3d8: 00040513 mv a0,s0 + 3dc: e09ff0ef jal 1e4 + 3e0: 00014703 lbu a4,0(sp) + 3e4: 00070e63 beqz a4,400 + 3e8: 00010793 mv a5,sp + 3ec: 100006b7 lui a3,0x10000 + 3f0: 00e68023 sb a4,0(a3) # 10000000 + 3f4: 0017c703 lbu a4,1(a5) + 3f8: 00178793 add a5,a5,1 + 3fc: fe071ae3 bnez a4,3f0 + 400: 00040513 mv a0,s0 + 404: 100007b7 lui a5,0x10000 + 408: 00078023 sb zero,0(a5) # 10000000 + 40c: 0000006f j 40c + +0000000000000410 : + 410: ffff87b7 lui a5,0xffff8 + 414: fd010113 add sp,sp,-48 + 418: 8307c793 xor a5,a5,-2000 + 41c: 00f11423 sh a5,8(sp) + 420: 02113423 sd ra,40(sp) + 424: 01910793 add a5,sp,25 + 428: 00910813 add a6,sp,9 + 42c: 00900613 li a2,9 + 430: 00f5f713 and a4,a1,15 + 434: 03770693 add a3,a4,55 + 438: 00e66463 bltu a2,a4,440 + 43c: 03070693 add a3,a4,48 + 440: 00d78023 sb a3,0(a5) # ffffffffffff8000 <_end+0xffffffffefff7fb8> + 444: fff78793 add a5,a5,-1 + 448: 4045d593 sra a1,a1,0x4 + 44c: ff0792e3 bne a5,a6,430 + 450: 00010d23 sb zero,26(sp) + 454: 00b00793 li a5,11 + 458: 02a7e063 bltu a5,a0,478 + 45c: 00004717 auipc a4,0x4 + 460: cc470713 add a4,a4,-828 # 4120 + 464: 00251513 sll a0,a0,0x2 + 468: 00e50533 add a0,a0,a4 + 46c: 00052783 lw a5,0(a0) + 470: 00e787b3 add a5,a5,a4 + 474: 00078067 jr a5 + 478: 00004717 auipc a4,0x4 + 47c: e1870713 add a4,a4,-488 # 4290 + 480: 05500793 li a5,85 + 484: 100006b7 lui a3,0x10000 + 488: 00f68023 sb a5,0(a3) # 10000000 + 48c: 00174783 lbu a5,1(a4) + 490: 00170713 add a4,a4,1 + 494: fe079ae3 bnez a5,488 + 498: 00814783 lbu a5,8(sp) + 49c: 00810713 add a4,sp,8 + 4a0: 100006b7 lui a3,0x10000 + 4a4: 00078a63 beqz a5,4b8 + 4a8: 00f68023 sb a5,0(a3) # 10000000 + 4ac: 00174783 lbu a5,1(a4) + 4b0: 00170713 add a4,a4,1 + 4b4: fe079ae3 bnez a5,4a8 + 4b8: 00004717 auipc a4,0x4 + 4bc: df870713 add a4,a4,-520 # 42b0 + 4c0: 00a00793 li a5,10 + 4c4: 100006b7 lui a3,0x10000 + 4c8: 00f68023 sb a5,0(a3) # 10000000 + 4cc: 00174783 lbu a5,1(a4) + 4d0: 00170713 add a4,a4,1 + 4d4: fe079ae3 bnez a5,4c8 + 4d8: fff00513 li a0,-1 + 4dc: ec9ff0ef jal 3a4 + 4e0: 00004717 auipc a4,0x4 + 4e4: c9870713 add a4,a4,-872 # 4178 + 4e8: 04900793 li a5,73 + 4ec: 100006b7 lui a3,0x10000 + 4f0: 00f68023 sb a5,0(a3) # 10000000 + 4f4: 00174783 lbu a5,1(a4) + 4f8: 00170713 add a4,a4,1 + 4fc: fe079ae3 bnez a5,4f0 + 500: 00814783 lbu a5,8(sp) + 504: 00810713 add a4,sp,8 + 508: 100006b7 lui a3,0x10000 + 50c: fc0786e3 beqz a5,4d8 + 510: 00f68023 sb a5,0(a3) # 10000000 + 514: 00174783 lbu a5,1(a4) + 518: 00170713 add a4,a4,1 + 51c: fe079ae3 bnez a5,510 + 520: fb9ff06f j 4d8 + 524: 00004717 auipc a4,0x4 + 528: c7c70713 add a4,a4,-900 # 41a0 + 52c: 04900793 li a5,73 + 530: 100006b7 lui a3,0x10000 + 534: 00f68023 sb a5,0(a3) # 10000000 + 538: 00174783 lbu a5,1(a4) + 53c: 00170713 add a4,a4,1 + 540: fe079ae3 bnez a5,534 + 544: 00814783 lbu a5,8(sp) + 548: f80788e3 beqz a5,4d8 + 54c: 00810713 add a4,sp,8 + 550: 100006b7 lui a3,0x10000 + 554: 00f68023 sb a5,0(a3) # 10000000 + 558: 00174783 lbu a5,1(a4) + 55c: 00170713 add a4,a4,1 + 560: fe079ae3 bnez a5,554 + 564: f75ff06f j 4d8 + 568: 00004717 auipc a4,0x4 + 56c: c6070713 add a4,a4,-928 # 41c8 + 570: 04900793 li a5,73 + 574: 100006b7 lui a3,0x10000 + 578: 00f68023 sb a5,0(a3) # 10000000 + 57c: 00174783 lbu a5,1(a4) + 580: 00170713 add a4,a4,1 + 584: fe079ae3 bnez a5,578 + 588: 00814783 lbu a5,8(sp) + 58c: f40786e3 beqz a5,4d8 + 590: 00810713 add a4,sp,8 + 594: 100006b7 lui a3,0x10000 + 598: 00f68023 sb a5,0(a3) # 10000000 + 59c: 00174783 lbu a5,1(a4) + 5a0: 00170713 add a4,a4,1 + 5a4: fe079ae3 bnez a5,598 + 5a8: f31ff06f j 4d8 + 5ac: 00004717 auipc a4,0x4 + 5b0: c3c70713 add a4,a4,-964 # 41e8 + 5b4: 04c00793 li a5,76 + 5b8: 100006b7 lui a3,0x10000 + 5bc: 00f68023 sb a5,0(a3) # 10000000 + 5c0: 00174783 lbu a5,1(a4) + 5c4: 00170713 add a4,a4,1 + 5c8: fe079ae3 bnez a5,5bc + 5cc: 00814783 lbu a5,8(sp) + 5d0: f00784e3 beqz a5,4d8 + 5d4: 00810713 add a4,sp,8 + 5d8: 100006b7 lui a3,0x10000 + 5dc: 00f68023 sb a5,0(a3) # 10000000 + 5e0: 00174783 lbu a5,1(a4) + 5e4: 00170713 add a4,a4,1 + 5e8: fe079ae3 bnez a5,5dc + 5ec: eedff06f j 4d8 + 5f0: 00004717 auipc a4,0x4 + 5f4: c1870713 add a4,a4,-1000 # 4208 + 5f8: 04c00793 li a5,76 + 5fc: 100006b7 lui a3,0x10000 + 600: 00f68023 sb a5,0(a3) # 10000000 + 604: 00174783 lbu a5,1(a4) + 608: 00170713 add a4,a4,1 + 60c: fe079ae3 bnez a5,600 + 610: 00814783 lbu a5,8(sp) + 614: ec0782e3 beqz a5,4d8 + 618: 00810713 add a4,sp,8 + 61c: 100006b7 lui a3,0x10000 + 620: 00f68023 sb a5,0(a3) # 10000000 + 624: 00174783 lbu a5,1(a4) + 628: 00170713 add a4,a4,1 + 62c: fe079ae3 bnez a5,620 + 630: ea9ff06f j 4d8 + 634: 00004717 auipc a4,0x4 + 638: bf470713 add a4,a4,-1036 # 4228 + 63c: 05300793 li a5,83 + 640: 100006b7 lui a3,0x10000 + 644: 00f68023 sb a5,0(a3) # 10000000 + 648: 00174783 lbu a5,1(a4) + 64c: 00170713 add a4,a4,1 + 650: fe079ae3 bnez a5,644 + 654: 00814783 lbu a5,8(sp) + 658: e80780e3 beqz a5,4d8 + 65c: 00810713 add a4,sp,8 + 660: 100006b7 lui a3,0x10000 + 664: 00f68023 sb a5,0(a3) # 10000000 + 668: 00174783 lbu a5,1(a4) + 66c: 00170713 add a4,a4,1 + 670: fe079ae3 bnez a5,664 + 674: e65ff06f j 4d8 + 678: 00004717 auipc a4,0x4 + 67c: bd870713 add a4,a4,-1064 # 4250 + 680: 05300793 li a5,83 + 684: 100006b7 lui a3,0x10000 + 688: 00f68023 sb a5,0(a3) # 10000000 + 68c: 00174783 lbu a5,1(a4) + 690: 00170713 add a4,a4,1 + 694: fe079ae3 bnez a5,688 + 698: 00814783 lbu a5,8(sp) + 69c: e2078ee3 beqz a5,4d8 + 6a0: 00810713 add a4,sp,8 + 6a4: 100006b7 lui a3,0x10000 + 6a8: 00f68023 sb a5,0(a3) # 10000000 + 6ac: 00174783 lbu a5,1(a4) + 6b0: 00170713 add a4,a4,1 + 6b4: fe079ae3 bnez a5,6a8 + 6b8: e21ff06f j 4d8 + 6bc: 00004717 auipc a4,0x4 + 6c0: bb470713 add a4,a4,-1100 # 4270 + 6c4: 04500793 li a5,69 + 6c8: 100006b7 lui a3,0x10000 + 6cc: 00f68023 sb a5,0(a3) # 10000000 + 6d0: 00174783 lbu a5,1(a4) + 6d4: 00170713 add a4,a4,1 + 6d8: fe079ae3 bnez a5,6cc + 6dc: 00814783 lbu a5,8(sp) + 6e0: de078ce3 beqz a5,4d8 + 6e4: 00810713 add a4,sp,8 + 6e8: 100006b7 lui a3,0x10000 + 6ec: 00f68023 sb a5,0(a3) # 10000000 + 6f0: 00174783 lbu a5,1(a4) + 6f4: 00170713 add a4,a4,1 + 6f8: fe079ae3 bnez a5,6ec + 6fc: dddff06f j 4d8 + +0000000000000700 : + 700: 00051063 bnez a0,700 + 704: 00008067 ret + +0000000000000708 <_init>: + 708: ff010113 add sp,sp,-16 + 70c: 00000593 li a1,0 + 710: 00000513 li a0,0 + 714: 00113423 sd ra,8(sp) + 718: 1d8000ef jal 8f0
+ 71c: c89ff0ef jal 3a4 + +0000000000000720 : + 720: 00b567b3 or a5,a0,a1 + 724: 00c7e7b3 or a5,a5,a2 + 728: 0077f793 and a5,a5,7 + 72c: 00c50833 add a6,a0,a2 + 730: 02078463 beqz a5,758 + 734: 00c58633 add a2,a1,a2 + 738: 00050793 mv a5,a0 + 73c: 0b057663 bgeu a0,a6,7e8 + 740: 0005c703 lbu a4,0(a1) + 744: 00158593 add a1,a1,1 + 748: 00178793 add a5,a5,1 + 74c: fee78fa3 sb a4,-1(a5) + 750: fec598e3 bne a1,a2,740 + 754: 00008067 ret + 758: 04050693 add a3,a0,64 + 75c: 0906f863 bgeu a3,a6,7ec + 760: 00058713 mv a4,a1 + 764: 00068793 mv a5,a3 + 768: 00073383 ld t2,0(a4) + 76c: 00873283 ld t0,8(a4) + 770: 01073f83 ld t6,16(a4) + 774: 01873f03 ld t5,24(a4) + 778: 02073e83 ld t4,32(a4) + 77c: 02873e03 ld t3,40(a4) + 780: 03073303 ld t1,48(a4) + 784: 03873883 ld a7,56(a4) + 788: 04078793 add a5,a5,64 + 78c: f877b023 sd t2,-128(a5) + 790: f857b423 sd t0,-120(a5) + 794: f9f7b823 sd t6,-112(a5) + 798: f9e7bc23 sd t5,-104(a5) + 79c: fbd7b023 sd t4,-96(a5) + 7a0: fbc7b423 sd t3,-88(a5) + 7a4: fa67b823 sd t1,-80(a5) + 7a8: fb17bc23 sd a7,-72(a5) + 7ac: 04070713 add a4,a4,64 + 7b0: fb07ece3 bltu a5,a6,768 + 7b4: fbf60613 add a2,a2,-65 + 7b8: fc067793 and a5,a2,-64 + 7bc: 04078793 add a5,a5,64 + 7c0: fc067613 and a2,a2,-64 + 7c4: 00f585b3 add a1,a1,a5 + 7c8: 00c687b3 add a5,a3,a2 + 7cc: f907f4e3 bgeu a5,a6,754 + 7d0: 0005b703 ld a4,0(a1) + 7d4: 00878793 add a5,a5,8 + 7d8: 00858593 add a1,a1,8 + 7dc: fee7bc23 sd a4,-8(a5) + 7e0: ff07e8e3 bltu a5,a6,7d0 + 7e4: 00008067 ret + 7e8: 00008067 ret + 7ec: 00050793 mv a5,a0 + 7f0: fddff06f j 7cc + +00000000000007f4 : + 7f4: 00c567b3 or a5,a0,a2 + 7f8: 0077f793 and a5,a5,7 + 7fc: 00c50633 add a2,a0,a2 + 800: 0ff5f713 zext.b a4,a1 + 804: 00078e63 beqz a5,820 + 808: 00050793 mv a5,a0 + 80c: 02c57c63 bgeu a0,a2,844 + 810: 00178793 add a5,a5,1 + 814: fee78fa3 sb a4,-1(a5) + 818: fef61ce3 bne a2,a5,810 + 81c: 00008067 ret + 820: 00004797 auipc a5,0x4 + 824: aa87b783 ld a5,-1368(a5) # 42c8 + 828: 02f70733 mul a4,a4,a5 + 82c: fec578e3 bgeu a0,a2,81c + 830: 00050793 mv a5,a0 + 834: 00878793 add a5,a5,8 + 838: fee7bc23 sd a4,-8(a5) + 83c: fec7ece3 bltu a5,a2,834 + 840: 00008067 ret + 844: 00008067 ret + +0000000000000848 : + 848: 00054783 lbu a5,0(a0) + 84c: 00078e63 beqz a5,868 + 850: 00050793 mv a5,a0 + 854: 0017c703 lbu a4,1(a5) + 858: 00178793 add a5,a5,1 + 85c: fe071ce3 bnez a4,854 + 860: 40a78533 sub a0,a5,a0 + 864: 00008067 ret + 868: 00000513 li a0,0 + 86c: 00008067 ret + +0000000000000870 : + 870: 00b506b3 add a3,a0,a1 + 874: 00050793 mv a5,a0 + 878: 00059863 bnez a1,888 + 87c: 0240006f j 8a0 + 880: 00178793 add a5,a5,1 + 884: 00f68a63 beq a3,a5,898 + 888: 0007c703 lbu a4,0(a5) + 88c: fe071ae3 bnez a4,880 + 890: 40a78533 sub a0,a5,a0 + 894: 00008067 ret + 898: 40a68533 sub a0,a3,a0 + 89c: 00008067 ret + 8a0: 00000513 li a0,0 + 8a4: 00008067 ret + +00000000000008a8 : + 8a8: 00054783 lbu a5,0(a0) + 8ac: 00158593 add a1,a1,1 + 8b0: 00150513 add a0,a0,1 + 8b4: fff5c703 lbu a4,-1(a1) + 8b8: 00078a63 beqz a5,8cc + 8bc: fee786e3 beq a5,a4,8a8 + 8c0: 0007851b sext.w a0,a5 + 8c4: 40e5053b subw a0,a0,a4 + 8c8: 00008067 ret + 8cc: 00000513 li a0,0 + 8d0: ff5ff06f j 8c4 + +00000000000008d4 : + 8d4: 00050793 mv a5,a0 + 8d8: 0005c703 lbu a4,0(a1) + 8dc: 00178793 add a5,a5,1 + 8e0: 00158593 add a1,a1,1 + 8e4: fee78fa3 sb a4,-1(a5) + 8e8: fe0718e3 bnez a4,8d8 + 8ec: 00008067 ret + +Disassembly of section .text.startup: + +00000000000008f0
: + 8f0: 00004517 auipc a0,0x4 + 8f4: 9e050513 add a0,a0,-1568 # 42d0 + 8f8: 00003597 auipc a1,0x3 + 8fc: 70858593 add a1,a1,1800 # 4000 + 900: 00003617 auipc a2,0x3 + 904: 76060613 add a2,a2,1888 # 4060 + 908: 00003697 auipc a3,0x3 + 90c: 7b868693 add a3,a3,1976 # 40c0 + 910: 02900713 li a4,41 + 914: 0c877857 vsetvli a6,a4,e16,m1,ta,ma + 918: 0008079b sext.w a5,a6 + 91c: 0206d507 vle16.v v10,(a3) + 920: 02065587 vle16.v v11,(a2) + 924: 0205d607 vle16.v v12,(a1) + 928: aeb52657 vnmsub.vv v12,v10,v11 + 92c: 02055627 vse16.v v12,(a0) + 930: 00179793 sll a5,a5,0x1 + 934: 4107073b subw a4,a4,a6 + 938: 00f686b3 add a3,a3,a5 + 93c: 00f60633 add a2,a2,a5 + 940: 00f585b3 add a1,a1,a5 + 944: 00f50533 add a0,a0,a5 + 948: fc0716e3 bnez a4,914 + 94c: 00003697 auipc a3,0x3 + 950: 71468693 add a3,a3,1812 # 4060 + 954: 00003597 auipc a1,0x3 + 958: 76c58593 add a1,a1,1900 # 40c0 + 95c: 86818813 add a6,gp,-1944 # 4330 + 960: 00003317 auipc t1,0x3 + 964: 6a030313 add t1,t1,1696 # 4000 + 968: 00003e17 auipc t3,0x3 + 96c: 74ae0e13 add t3,t3,1866 # 40b2 + 970: 00080893 mv a7,a6 + 974: 00058513 mv a0,a1 + 978: 00068793 mv a5,a3 + 97c: 00055603 lhu a2,0(a0) + 980: 00035e83 lhu t4,0(t1) + 984: 0007d703 lhu a4,0(a5) + 988: 00288893 add a7,a7,2 + 98c: 03d6063b mulw a2,a2,t4 + 990: 00278793 add a5,a5,2 + 994: 00250513 add a0,a0,2 + 998: 00230313 add t1,t1,2 + 99c: 40c7073b subw a4,a4,a2 + 9a0: fee89f23 sh a4,-2(a7) + 9a4: fdc79ce3 bne a5,t3,97c + 9a8: 00004717 auipc a4,0x4 + 9ac: 92870713 add a4,a4,-1752 # 42d0 + 9b0: 85a18893 add a7,gp,-1958 # 4322 + 9b4: 86818613 add a2,gp,-1944 # 4330 + 9b8: 00070793 mv a5,a4 + 9bc: 00100513 li a0,1 + 9c0: 00061e83 lh t4,0(a2) + 9c4: 00079303 lh t1,0(a5) + 9c8: 00260613 add a2,a2,2 + 9cc: 00278793 add a5,a5,2 + 9d0: 006e8463 beq t4,t1,9d8 + 9d4: 00000513 li a0,0 + 9d8: ff1794e3 bne a5,a7,9c0 + 9dc: 000022b7 lui t0,0x2 + 9e0: 00004f17 auipc t5,0x4 + 9e4: 8f0f0f13 add t5,t5,-1808 # 42d0 + 9e8: 00003e97 auipc t4,0x3 + 9ec: 678e8e93 add t4,t4,1656 # 4060 + 9f0: 00003317 auipc t1,0x3 + 9f4: 6d030313 add t1,t1,1744 # 40c0 + 9f8: 02900613 li a2,41 + 9fc: 9192829b addw t0,t0,-1767 # 1919 + a00: 0c867fd7 vsetvli t6,a2,e16,m1,ta,ma + a04: 000f879b sext.w a5,t6 + a08: 02035507 vle16.v v10,(t1) + a0c: 020ed587 vle16.v v11,(t4) + a10: aea2e5d7 vnmsub.vx v11,t0,v10 + a14: 020f55a7 vse16.v v11,(t5) + a18: 00179793 sll a5,a5,0x1 + a1c: 41f6063b subw a2,a2,t6 + a20: 00f30333 add t1,t1,a5 + a24: 00fe8eb3 add t4,t4,a5 + a28: 00ff0f33 add t5,t5,a5 + a2c: fc061ae3 bnez a2,a00 + a30: ffffeeb7 lui t4,0xffffe + a34: 86818613 add a2,gp,-1944 # 4330 + a38: 6e7e8e9b addw t4,t4,1767 # ffffffffffffe6e7 <_end+0xffffffffefffe69f> + a3c: 0006d783 lhu a5,0(a3) + a40: 0005d303 lhu t1,0(a1) + a44: 00260613 add a2,a2,2 + a48: 02fe87bb mulw a5,t4,a5 + a4c: 00268693 add a3,a3,2 + a50: 00258593 add a1,a1,2 + a54: 006787bb addw a5,a5,t1 + a58: fef61f23 sh a5,-2(a2) + a5c: ffc690e3 bne a3,t3,a3c + a60: 00071683 lh a3,0(a4) + a64: 00081783 lh a5,0(a6) + a68: 00270713 add a4,a4,2 + a6c: 00280813 add a6,a6,2 + a70: 00f68463 beq a3,a5,a78 + a74: 00000513 li a0,0 + a78: ff1714e3 bne a4,a7,a60 + a7c: 00154513 xor a0,a0,1 + a80: 00008067 ret + a84: fff00513 li a0,-1 + a88: 00008067 ret + +Disassembly of section .rodata: + +0000000000004000 : + 4000: de7f6f4f .4byte 0xde7f6f4f + 4004: 6560 vmsge.vx v10,v0,zero,v0.t + 4006: 7f28 .2byte 0x7f28 + 4008: d47bad0b .4byte 0xd47bad0b + 400c: 3561 vmsge.vx v10,v0,zero,v0.t + 400e: 4922134f .4byte 0x4922134f + 4012: f869 .2byte 0xf869 + 4014: e2be .2byte 0xe2be + 4016: 66655b7f 2fd0f487 .byte 0x7f, 0x5b, 0x65, 0x66, 0x87, 0xf4, 0xd0, 0x2f, 0x85, 0xa2, 0xf8, 0x25, 0xb9, 0x7f, 0x66, 0x6d, 0x55, 0xc4, 0xdb, 0x5f + 401e: 25f8a285 6d667fb9 + 4026: 5fdbc455 + 402a: 9789 .2byte 0x9789 + 402c: eb716457 vwmulsu.vx v8,v23,sp + 4030: 7b54 .2byte 0x7b54 + 4032: def2 .2byte 0xdef2 + 4034: 4301 vmsge.vx v6,v0,zero,v0.t + 4036: fd67d5cf .4byte 0xfd67d5cf + 403a: 71b8 .2byte 0x71b8 + 403c: 7b50 .2byte 0x7b50 + 403e: 3ed7a5a3 sw a3,1003(a5) + 4042: 7231 .2byte 0x7231 + 4044: 1c16 .2byte 0x1c16 + 4046: a8c5c137 lui sp,0xa8c5c + 404a: 8948 .2byte 0x8948 + 404c: 4769 .2byte 0x4769 + 404e: f820 vmsge.vx v16,v0,ra,v0.t + 4050: 72589fb7 lui t6,0x72589 + 4054: 4c0c .2byte 0x4c0c + 4056: 0a9e .2byte 0xa9e + 4058: 1240 vmsge.vx v4,v0,zero,v0.t + 405a: 2f0a .2byte 0x2f0a + 405c: 20f2 .2byte 0x20f2 + 405e: 920a .2byte 0x920a + +0000000000004060 : + 4060: 7729 .2byte 0x7729 + 4062: 4ec6 .2byte 0x4ec6 + 4064: 160e .2byte 0x160e + 4066: aa00 vmsge.vx v20,v0,ra,v0.t + 4068: b0d5 .2byte 0xb0d5 + 406a: be1a073b .4byte 0xbe1a073b + 406e: c35e .2byte 0xc35e + 4070: e6b2 .2byte 0xe6b2 + 4072: 6f98 .2byte 0x6f98 + 4074: de929e9b .4byte 0xde929e9b + 4078: 72e270db .4byte 0x72e270db + 407c: e9d8 .2byte 0xe9d8 + 407e: 9bf6 .2byte 0x9bf6 + 4080: 44dc .2byte 0x44dc + 4082: f1b6bdef jal s11,fffffffffff6ff9c <_end+0xffffffffeff6ff54> + 4086: 8df9 .2byte 0x8df9 + 4088: b8ba .2byte 0xb8ba + 408a: 1e11 .2byte 0x1e11 + 408c: 4132 .2byte 0x4132 + 408e: d955 .2byte 0xd955 + 4090: 1711 .2byte 0x1711 + 4092: 9a81 vmsge.vx v21,v0,ra,v0.t + 4094: 645f 190b fe67 .byte 0x5f, 0x64, 0x0b, 0x19, 0x67, 0xfe + 409a: 0438 .2byte 0x438 + 409c: 2255 .2byte 0x2255 + 409e: c2dea2b3 .4byte 0xc2dea2b3 + 40a2: 69ac .2byte 0x69ac + 40a4: dd7d .2byte 0xdd7d + 40a6: d433ccc3 vmsge.vx v25,v3,t2,v0.t + 40aa: 30c4 .2byte 0x30c4 + 40ac: 7639 .2byte 0x7639 + 40ae: ae61 vmsge.vx v28,v0,ra,v0.t + 40b0: 717f .2byte 0x717f + 40b2: a7bc8f9b addw t6,s9,-1413 + 40b6: 3df5 .2byte 0x3df5 + 40b8: 6b708b4f .4byte 0x6b708b4f + 40bc: 55c5 .2byte 0x55c5 + 40be: c9da .2byte 0xc9da + +00000000000040c0 : + 40c0: 968d .2byte 0x968d + 40c2: d593c97b .4byte 0xd593c97b + 40c6: 631e .2byte 0x631e + 40c8: b990 .2byte 0xb990 + 40ca: 5cbaad63 vmsge.vx v26,v11,s5,v0.t + 40ce: 5fe4 .2byte 0x5fe4 + 40d0: 9232 .2byte 0x9232 + 40d2: aa6a .2byte 0xaa6a + 40d4: 4186 .2byte 0x4186 + 40d6: 4d80d87b .4byte 0x4d80d87b + 40da: 31a7d16f jal sp,813f4 <__global_pointer$+0x7c92c> + 40de: a180 vmsge.vx v3,v0,ra,v0.t + 40e0: 6bc2 vmsge.vx v23,v0,zero,v0.t + 40e2: b1ac .2byte 0xb1ac + 40e4: b049 .2byte 0xb049 + 40e6: 3552 .2byte 0x3552 + 40e8: c256 .2byte 0xc256 + 40ea: 5275 .2byte 0x5275 + 40ec: 7cfe .2byte 0x7cfe + 40ee: 496c .2byte 0x496c + 40f0: d4a6 .2byte 0xd4a6 + 40f2: f964 .2byte 0xf964 + 40f4: 8da3049b addw s1,t1,-1830 + 40f8: bb15 .2byte 0xbb15 + 40fa: 975c .2byte 0x975c + 40fc: c4ad .2byte 0xc4ad + 40fe: cdac .2byte 0xcdac + 4100: add7e053 .4byte 0xadd7e053 + 4104: 529c8f93 add t6,s9,1321 + 4108: 969c .2byte 0x969c + 410a: 601d .2byte 0x601d + 410c: 14ce39a7 .4byte 0x14ce39a7 + 4110: 7f38 .2byte 0x7f38 + 4112: 3884 .2byte 0x3884 + 4114: 8d44 .2byte 0x8d44 + 4116: f1809d8b .4byte 0xf1809d8b + 411a: 2f01 vmsge.vx v30,v0,zero,v0.t + 411c: ca10 .2byte 0xca10 + 411e: 3bc0 vmsge.vx v23,v0,zero,v0.t + 4120: c3c0 vmsge.vx v7,v0,ra,v0.t + 4122: ffff .2byte 0xffff + 4124: c404 .2byte 0xc404 + 4126: ffff .2byte 0xffff + 4128: c448 .2byte 0xc448 + 412a: ffff .2byte 0xffff + 412c: c358 .2byte 0xc358 + 412e: ffff .2byte 0xffff + 4130: c48c .2byte 0xc48c + 4132: ffff .2byte 0xffff + 4134: c4d0 .2byte 0xc4d0 + 4136: ffff .2byte 0xffff + 4138: c514 .2byte 0xc514 + 413a: ffff .2byte 0xffff + 413c: c558 .2byte 0xc558 + 413e: ffff .2byte 0xffff + 4140: c358 .2byte 0xc358 + 4142: ffff .2byte 0xffff + 4144: c358 .2byte 0xc358 + 4146: ffff .2byte 0xffff + 4148: c358 .2byte 0xc358 + 414a: ffff .2byte 0xffff + 414c: c59c .2byte 0xc59c + 414e: ffff .2byte 0xffff + +Disassembly of section .rodata.str1.8: + +0000000000004150 <.rodata.str1.8>: + 4150: 6c637963 bgeu t1,t1,4822 <_tbss_end+0x492> + 4154: 3a65 .2byte 0x3a65 + 4156: 0020 vmsge.vx v0,v0,zero,v0.t + 4158: 690a .2byte 0x690a + 415a: 736e .2byte 0x736e + 415c: 7274 .2byte 0x7274 + 415e: 7465 .2byte 0x7465 + 4160: 203a .2byte 0x203a + 4162: 0000 vmsge.vx v0,v0,zero,v0.t + 4164: 0000 vmsge.vx v0,v0,zero,v0.t + 4166: 0000 vmsge.vx v0,v0,zero,v0.t + 4168: 7845 .2byte 0x7845 + 416a: 7469 .2byte 0x7469 + 416c: 6320 vmsge.vx v6,v0,zero,v0.t + 416e: 3a65646f jal s0,5a514 <__global_pointer$+0x55a4c> + 4172: 0020 vmsge.vx v0,v0,zero,v0.t + 4174: 0000 vmsge.vx v0,v0,zero,v0.t + 4176: 0000 vmsge.vx v0,v0,zero,v0.t + 4178: 4e49 .2byte 0x4e49 + 417a: 55525453 .4byte 0x55525453 + 417e: 4f495443 vmsge.vx v8,v20,s2 + 4182: 204e .2byte 0x204e + 4184: 4441 vmsge.vx v8,v0,zero,v0.t + 4186: 5244 .2byte 0x5244 + 4188: 5345 .2byte 0x5345 + 418a: 494d2053 .4byte 0x494d2053 + 418e: 494c4153 .4byte 0x494c4153 + 4192: 44454e47 .4byte 0x44454e47 + 4196: 6120 vmsge.vx v2,v0,zero,v0.t + 4198: 2074 .2byte 0x2074 + 419a: 4350 .2byte 0x4350 + 419c: 203a .2byte 0x203a + 419e: 0000 vmsge.vx v0,v0,zero,v0.t + 41a0: 4e49 .2byte 0x4e49 + 41a2: 55525453 .4byte 0x55525453 + 41a6: 4f495443 vmsge.vx v8,v20,s2 + 41aa: 204e .2byte 0x204e + 41ac: 4341 vmsge.vx v6,v0,zero,v0.t + 41ae: 53534543 vmsge.vx v10,v21,t1 + 41b2: 4620 vmsge.vx v12,v0,zero,v0.t + 41b4: 5541 vmsge.vx v10,v0,zero,v0.t + 41b6: 544c .2byte 0x544c + 41b8: 6120 vmsge.vx v2,v0,zero,v0.t + 41ba: 2074 .2byte 0x2074 + 41bc: 4350 .2byte 0x4350 + 41be: 203a .2byte 0x203a + ... + 41c8: 4c49 .2byte 0x4c49 + 41ca: 454c .2byte 0x454c + 41cc: 204c4147 .4byte 0x204c4147 + 41d0: 4e49 .2byte 0x4e49 + 41d2: 55525453 .4byte 0x55525453 + 41d6: 4f495443 vmsge.vx v8,v20,s2 + 41da: 204e .2byte 0x204e + 41dc: 7461 vmsge.vx v8,v0,zero,v0.t + 41de: 5020 vmsge.vx v0,v0,zero,v0.t + 41e0: 00203a43 vmsge.vx v20,v2,zero,v0.t + 41e4: 0000 vmsge.vx v0,v0,zero,v0.t + 41e6: 0000 vmsge.vx v0,v0,zero,v0.t + 41e8: 4f4c .2byte 0x4f4c + 41ea: 4441 vmsge.vx v8,v0,zero,v0.t + 41ec: 4120 vmsge.vx v2,v0,zero,v0.t + 41ee: 4444 .2byte 0x4444 + 41f0: 4552 .2byte 0x4552 + 41f2: 4d205353 .4byte 0x4d205353 + 41f6: 5349 .2byte 0x5349 + 41f8: 4c41 vmsge.vx v24,v0,zero,v0.t + 41fa: 4749 .2byte 0x4749 + 41fc: 454e .2byte 0x454e + 41fe: 2044 .2byte 0x2044 + 4200: 7461 vmsge.vx v8,v0,zero,v0.t + 4202: 5020 vmsge.vx v0,v0,zero,v0.t + 4204: 00203a43 vmsge.vx v20,v2,zero,v0.t + 4208: 4f4c .2byte 0x4f4c + 420a: 4441 vmsge.vx v8,v0,zero,v0.t + 420c: 4120 vmsge.vx v2,v0,zero,v0.t + 420e: 53454343 vmsge.vx v6,v20,a0 + 4212: 41462053 .4byte 0x41462053 + 4216: 4c55 .2byte 0x4c55 + 4218: 2054 .2byte 0x2054 + 421a: 7461 vmsge.vx v8,v0,zero,v0.t + 421c: 5020 vmsge.vx v0,v0,zero,v0.t + 421e: 00203a43 vmsge.vx v20,v2,zero,v0.t + 4222: 0000 vmsge.vx v0,v0,zero,v0.t + 4224: 0000 vmsge.vx v0,v0,zero,v0.t + 4226: 0000 vmsge.vx v0,v0,zero,v0.t + 4228: 524f5453 .4byte 0x524f5453 + 422c: 2045 .2byte 0x2045 + 422e: 4441 vmsge.vx v8,v0,zero,v0.t + 4230: 5244 .2byte 0x5244 + 4232: 5345 .2byte 0x5345 + 4234: 494d2053 .4byte 0x494d2053 + 4238: 494c4153 .4byte 0x494c4153 + 423c: 44454e47 .4byte 0x44454e47 + 4240: 6120 vmsge.vx v2,v0,zero,v0.t + 4242: 2074 .2byte 0x2074 + 4244: 4350 .2byte 0x4350 + 4246: 203a .2byte 0x203a + ... + 4250: 524f5453 .4byte 0x524f5453 + 4254: 2045 .2byte 0x2045 + 4256: 4341 vmsge.vx v6,v0,zero,v0.t + 4258: 53534543 vmsge.vx v10,v21,t1 + 425c: 4620 vmsge.vx v12,v0,zero,v0.t + 425e: 5541 vmsge.vx v10,v0,zero,v0.t + 4260: 544c .2byte 0x544c + 4262: 6120 vmsge.vx v2,v0,zero,v0.t + 4264: 2074 .2byte 0x2074 + 4266: 4350 .2byte 0x4350 + 4268: 203a .2byte 0x203a + 426a: 0000 vmsge.vx v0,v0,zero,v0.t + 426c: 0000 vmsge.vx v0,v0,zero,v0.t + 426e: 0000 vmsge.vx v0,v0,zero,v0.t + 4270: 4345 .2byte 0x4345 + 4272: 4c41 vmsge.vx v24,v0,zero,v0.t + 4274: 204c .2byte 0x204c + 4276: 5246 .2byte 0x5246 + 4278: 4d204d4f .4byte 0x4d204d4f + 427c: 4d2d .2byte 0x4d2d + 427e: 2045444f .4byte 0x2045444f + 4282: 7461 vmsge.vx v8,v0,zero,v0.t + 4284: 5020 vmsge.vx v0,v0,zero,v0.t + 4286: 00203a43 vmsge.vx v20,v2,zero,v0.t + 428a: 0000 vmsge.vx v0,v0,zero,v0.t + 428c: 0000 vmsge.vx v0,v0,zero,v0.t + 428e: 0000 vmsge.vx v0,v0,zero,v0.t + 4290: 4e55 .2byte 0x4e55 + 4292: 574f4e4b .4byte 0x574f4e4b + 4296: 204e .2byte 0x204e + 4298: 5845 .2byte 0x5845 + 429a: 54504543 vmsge.vx v10,v5,zero,v0.t + 429e: 4f49 .2byte 0x4f49 + 42a0: 204e .2byte 0x204e + 42a2: 7461 vmsge.vx v8,v0,zero,v0.t + 42a4: 5020 vmsge.vx v0,v0,zero,v0.t + 42a6: 00203a43 vmsge.vx v20,v2,zero,v0.t + 42aa: 0000 vmsge.vx v0,v0,zero,v0.t + 42ac: 0000 vmsge.vx v0,v0,zero,v0.t + 42ae: 0000 vmsge.vx v0,v0,zero,v0.t + 42b0: 430a .2byte 0x430a + 42b2: 4548 .2byte 0x4548 + 42b4: 4d204b43 vmsge.vx v22,v18,zero,v0.t + 42b8: 53554143 vmsge.vx v2,v21,a0 + 42bc: 2045 .2byte 0x2045 + 42be: 6e69 .2byte 0x6e69 + 42c0: 5220 vmsge.vx v4,v0,zero,v0.t + 42c2: 4c54 .2byte 0x4c54 + ... + +Disassembly of section .sdata: + +00000000000042c8 <__global_pointer$-0x800>: + 42c8: 0101 vmsge.vx v2,v0,zero,v0.t + 42ca: 0101 vmsge.vx v2,v0,zero,v0.t + 42cc: 0101 vmsge.vx v2,v0,zero,v0.t + 42ce: 0101 vmsge.vx v2,v0,zero,v0.t + +Disassembly of section .bss: + +00000000000042d0 : + ... + +0000000000004330 : + ... + +Disassembly of section .tohost: + +0000000010000000 : + ... + +0000000010000040 : + ... + +Disassembly of section .comment: + +0000000000000000 <.comment>: + 0: 3a434347 .4byte 0x3a434347 + 4: 2820 vmsge.vx v16,v0,zero,v0.t + 6: 65653267 .4byte 0x65653267 + a: 6535 .2byte 0x6535 + c: 3334 .2byte 0x3334 + e: 3030 .2byte 0x3030 + 10: 3831 .2byte 0x3831 + 12: 2029 .2byte 0x2029 + 14: 3231 .2byte 0x3231 + 16: 322e .2byte 0x322e + 18: 302e .2byte 0x302e + ... + +Disassembly of section .riscv.attributes: + +0000000000000000 <.riscv.attributes>: + 0: 5e41 vmsge.vx v28,v0,zero,v0.t + 2: 0000 vmsge.vx v0,v0,zero,v0.t + 4: 7200 vmsge.vx v4,v0,zero,v0.t + 6: 7369 .2byte 0x7369 + 8: 01007663 bgeu zero,a6,14 <_start+0x14> + c: 0054 .2byte 0x54 + e: 0000 vmsge.vx v0,v0,zero,v0.t + 10: 1004 .2byte 0x1004 + 12: 7205 .2byte 0x7205 + 14: 3676 .2byte 0x3676 + 16: 6934 .2byte 0x6934 + 18: 7032 .2byte 0x7032 + 1a: 5f31 .2byte 0x5f31 + 1c: 326d .2byte 0x326d + 1e: 3070 .2byte 0x3070 + 20: 7a5f 6369 7273 .byte 0x5f, 0x7a, 0x69, 0x63, 0x73, 0x72 + 26: 7032 .2byte 0x7032 + 28: 5f30 .2byte 0x5f30 + 2a: 6d7a .2byte 0x6d7a + 2c: 756d .2byte 0x756d + 2e: 316c .2byte 0x316c + 30: 3070 .2byte 0x3070 + 32: 7a5f 6576 3233 .byte 0x5f, 0x7a, 0x76, 0x65, 0x33, 0x32 + 38: 3178 .2byte 0x3178 + 3a: 3070 .2byte 0x3070 + 3c: 7a5f 6576 3436 .byte 0x5f, 0x7a, 0x76, 0x65, 0x36, 0x34 + 42: 3178 .2byte 0x3178 + 44: 3070 .2byte 0x3070 + 46: 7a5f 6c76 3233 .byte 0x5f, 0x7a, 0x76, 0x6c, 0x33, 0x32 + 4c: 3162 vmsge.vx v2,v0,zero,v0.t + 4e: 3070 .2byte 0x3070 + 50: 7a5f 6c76 3436 .byte 0x5f, 0x7a, 0x76, 0x6c, 0x36, 0x34 + 56: 3162 vmsge.vx v2,v0,zero,v0.t + 58: 3070 .2byte 0x3070 + 5a: 0800 vmsge.vx v16,v0,zero,v0.t + 5c: 0a01 vmsge.vx v20,v0,zero,v0.t + 5e: 0b Address 0x5e is out of bounds. + diff --git a/src/main/resources/applications_vector/vnmsub/vnmsub.c b/src/main/resources/applications_vector/vnmsub/vnmsub.c new file mode 100644 index 00000000..0da2d233 --- /dev/null +++ b/src/main/resources/applications_vector/vnmsub/vnmsub.c @@ -0,0 +1,95 @@ +#include "util.h" + +#define size_t long +#define N 48 + +const signed short dataArray0[N] = {-26995, -13957, -10861, 25374, -18032, -21149, 23738, 24548, -28110, -21910, 16774, -10117, 19840, -11921, 12711, -24192, 27586, -20052, -20407, 13650, -15786, 21109, 31998, 18796, -11098, -1692, 1179, -29277, -17643, -26788, -15187, -12884, -8109, -21033, -28781, 21148, -26980, 24605, 14759, 5326, 32568, 14468, -29372, -25205, -3712, 12033, -13808, 15296}; +const signed short dataArray1[N] = {30505, 20166, 5646, -22016, -20267, 1851, -16870, -15522, -6478, 28568, -24933, -8558, 28891, 29410, -5672, -25610, 17628, -16913, -3658, -29191, -18246, 7697, 16690, -9899, 5905, -25983, 25695, 6411, -409, 1080, 8789, -23885, -15650, 27052, -8835, -13117, -11213, 12484, 30265, -20895, 29055, -28773, -22596, 15861, -29873, 27504, 21957, -13862}; +const signed short dataArray2[N] = {28495, -8577, 25952, 32552, -21237, -11141, 13665, 4943, 18722, -1943, -7490, 23423, 26213, -2937, 12240, -23931, 9720, 32697, 28006, -15275, 24539, -26743, 25687, -5263, 31572, -8462, 17153, -10801, -665, 29112, 31568, -23133, 16087, 29233, 7190, -16073, -22331, -30392, 18281, -2016, -24649, 29272, 19468, 2718, 4672, 12042, 8434, -28150}; +signed short resultArray[N] = {0}; +signed short answerArray[N] = {0}; + +extern void printstr(char* str); +extern void int64ToHex(long num, char* str); +extern void int32ToHex(int num, char* str); +extern void clearCounters(); +extern void printCounters(); + +int main(int argc, char** argv) { + int vl, avl = 41; + const signed short *ptr0 = dataArray0; + const signed short *ptr1 = dataArray1; + const signed short *ptr2 = dataArray2; + signed short *ptr3 = resultArray; + while(avl != 0) { + asm volatile ("vsetvli %0, %1, e16, m1, ta, ma" + : "=r"(vl) + : "r"(avl)); + // asm volatile ("li t0, 0x1919"); + asm volatile ("vle16.v v10, (%0)" + : + : "r"(ptr0)); + asm volatile ("vle16.v v11, (%0)" + : + : "r"(ptr1)); + asm volatile ("vle16.v v12, (%0)" + : + : "r"(ptr2)); + // v12 = -(v10 * v12) + v11 + asm volatile ("vnmsub.vv v12, v10, v11"); + asm volatile ("vse16.v v12, (%0)" + : + : "r"(ptr3)); + ptr0 += vl; + ptr1 += vl; + ptr2 += vl; + ptr3 += vl; + avl -= vl; + } + int i; + for(i=0; i<41; i++) { + answerArray[i] = -(dataArray0[i] * dataArray2[i]) + dataArray1[i]; + } + + _Bool correct = 1; + for(i=0; i<41; i++) { + if(resultArray[i] != answerArray[i]) { + correct = 0; + } + } + avl = 41; + ptr0 = dataArray0; + ptr1 = dataArray1; + ptr3 = resultArray; + while(avl != 0) { + asm volatile ("vsetvli %0, %1, e16, m1, ta, ma" + : "=r"(vl) + : "r"(avl)); + asm volatile ("vle16.v v10, (%0)" + : + : "r"(ptr0)); + asm volatile ("vle16.v v11, (%0)" + : + : "r"(ptr1)); + // v11 = -(0x1919 * v11) + v10 + asm volatile ("vnmsub.vx v11, %0, v10" + : + : "r"(0x1919)); + asm volatile ("vse16.v v11, (%0)" + : + : "r"(ptr3)); + ptr0 += vl; + ptr1 += vl; + ptr3 += vl; + avl -= vl; + } + for(i=0; i<41; i++) { + answerArray[i] = -(0x1919 * dataArray1[i]) + dataArray0[i]; + } + for(i=0; i<41; i++) { + if(resultArray[i] != answerArray[i]) { + correct = 0; + } + } + return !correct; +} diff --git a/src/main/resources/applications_vector/vnmsub_data.hex b/src/main/resources/applications_vector/vnmsub_data.hex new file mode 100644 index 00000000..76ca0b6b --- /dev/null +++ b/src/main/resources/applications_vector/vnmsub_data.hex @@ -0,0 +1,180 @@ +de7f6f4f +7f286560 +d47bad0b +134f3561 +f8694922 +5b7fe2be +f4876665 +a2852fd0 +7fb925f8 +c4556d66 +97895fdb +eb716457 +def27b54 +d5cf4301 +71b8fd67 +a5a37b50 +72313ed7 +c1371c16 +8948a8c5 +f8204769 +72589fb7 +0a9e4c0c +2f0a1240 +920a20f2 +4ec67729 +aa00160e +073bb0d5 +c35ebe1a +6f98e6b2 +de929e9b +72e270db +9bf6e9d8 +bdef44dc +8df9f1b6 +1e11b8ba +d9554132 +9a811711 +190b645f +0438fe67 +a2b32255 +69acc2de +ccc3dd7d +30c4d433 +ae617639 +8f9b717f +3df5a7bc +6b708b4f +c9da55c5 +c97b968d +631ed593 +ad63b990 +5fe45cba +aa6a9232 +d87b4186 +d16f4d80 +a18031a7 +b1ac6bc2 +3552b049 +5275c256 +496c7cfe +f964d4a6 +8da3049b +975cbb15 +cdacc4ad +add7e053 +529c8f93 +601d969c +14ce39a7 +38847f38 +9d8b8d44 +2f01f180 +3bc0ca10 +ffffc3c0 +ffffc404 +ffffc448 +ffffc358 +ffffc48c +ffffc4d0 +ffffc514 +ffffc558 +ffffc358 +ffffc358 +ffffc358 +ffffc59c +6c637963 +00203a65 +736e690a +74657274 +0000203a +00000000 +74697845 +646f6320 +00203a65 +00000000 +54534e49 +54435552 +204e4f49 +52444441 +20535345 +4153494d +4e47494c +61204445 +43502074 +0000203a +54534e49 +54435552 +204e4f49 +45434341 +46205353 +544c5541 +20746120 +203a4350 +00000000 +00000000 +454c4c49 +204c4147 +54534e49 +54435552 +204e4f49 +50207461 +00203a43 +00000000 +44414f4c +44444120 +53534552 +53494d20 +47494c41 +2044454e +50207461 +00203a43 +44414f4c +43434120 +20535345 +4c554146 +74612054 +3a435020 +00000020 +00000000 +524f5453 +44412045 +53455244 +494d2053 +494c4153 +44454e47 +20746120 +203a4350 +00000000 +00000000 +524f5453 +43412045 +53534543 +55414620 +6120544c +43502074 +0000203a +00000000 +4c414345 +5246204c +4d204d4f +444f4d2d +74612045 +3a435020 +00000020 +00000000 +4e4b4e55 +204e574f +45435845 +4f495450 +7461204e +3a435020 +00000020 +00000000 +4548430a +4d204b43 +53554143 +6e692045 +4c545220 +00000000 +01010101 +01010101 diff --git a/src/main/resources/applications_vector/vnmsub_inst.hex b/src/main/resources/applications_vector/vnmsub_inst.hex new file mode 100644 index 00000000..060caf40 --- /dev/null +++ b/src/main/resources/applications_vector/vnmsub_inst.hex @@ -0,0 +1,675 @@ +00000093 +00000113 +00000193 +00000213 +00000293 +00000313 +00000393 +00000413 +00000493 +00000513 +00000593 +00000613 +00000693 +00000713 +00000793 +00000813 +00000893 +00000913 +00000993 +00000a13 +00000a93 +00000b13 +00000b93 +00000c13 +00000c93 +00000d13 +00000d93 +00000e13 +00000e93 +00000f13 +00000f93 +00000297 +03828293 +30529073 +00005197 +a4018193 +10000217 +ff720213 +fc027213 +f1402573 +00100593 +00b57063 +00006137 +ff01011b +6580006f +ef010113 +00113423 +00213823 +00313c23 +02413023 +02513423 +02613823 +02713c23 +04813023 +04913423 +04a13823 +04b13c23 +06c13023 +06d13423 +06e13823 +06f13c23 +09013023 +09113423 +09213823 +09313c23 +0b413023 +0b513423 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+00280813 +00f68463 +00000513 +ff1714e3 +00154513 +00008067 +fff00513 +00008067 diff --git a/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala b/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala index a4d7997b..1e0761d8 100644 --- a/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala +++ b/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala @@ -140,7 +140,7 @@ class Zve64xAppTestForVecCpu extends AnyFlatSpec with ChiselScalatestTester { "vminmax", "vmerge", "vmv", "vmand", "vmor", "vmxor", "vmul", "vmulh", "vmulhu", "vmulhsu", - "vmacc", "vnmsac", "vmadd", + "vmacc", "vnmsac", "vmadd", "vnmsub", ) val applicationTest = Seq( "vector_median" From 7f1a667841df16fa114f06bff17c1abc39010fc9 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Mon, 13 Nov 2023 18:35:59 +0900 Subject: [PATCH 08/14] vector reduction support --- .../scala/hajime/common/Instructions.scala | 25 +++++++++++----- .../hajime/vectormodules/VectorExecUnit.scala | 30 +++++++++++++++---- .../vectormodules/VectorOpConstants.scala | 7 ++++- 3 files changed, 47 insertions(+), 15 deletions(-) diff --git a/src/main/scala/hajime/common/Instructions.scala b/src/main/scala/hajime/common/Instructions.scala index 52ececb2..8aa7fc2f 100644 --- a/src/main/scala/hajime/common/Instructions.scala +++ b/src/main/scala/hajime/common/Instructions.scala @@ -195,14 +195,14 @@ object VectorInstructions extends ScalarOpConstants with VectorOpConstants { case "vnmsub" => "101011" case "vmerge" => "010111" case "vmv" => "010111" - case "vredsum" => ??? - case "vredmaxu" => ??? - case "vredmax" => ??? - case "vredminu" => ??? - case "vredmin" => ??? - case "vredand" => ??? - case "vredor" => ??? - case "vredxor" => ??? + case "vredsum" => "000000" + case "vredmaxu" => "000110" + case "vredmax" => "000111" + case "vredminu" => "000100" + case "vredmin" => "000101" + case "vredand" => "000001" + case "vredor" => "000010" + case "vredxor" => "000011" case "vmand" => "011001" case "vmnand" => "011101" case "vmandn" => "011000" @@ -310,6 +310,15 @@ object VectorInstructions extends ScalarOpConstants with VectorOpConstants { def VMV_VX = vArithGen(vInst = "vmv", vsource = VSOURCE.VX, vm = "1", vs2Zero = true) def VMV_VI = vArithGen(vInst = "vmv", vsource = VSOURCE.VI, vm = "1", vs2Zero = true) + def VREDSUM_VS = vArithGen(vInst = "vredsum", vsource = VSOURCE.MVV) + def VREDMAXU_VS = vArithGen(vInst = "vredmaxu", vsource = VSOURCE.MVV) + def VREDMAX_VS = vArithGen(vInst = "vredmax", vsource = VSOURCE.MVV) + def VREDMINU_VS = vArithGen(vInst = "vredminu", vsource = VSOURCE.MVV) + def VREDMIN_VS = vArithGen(vInst = "vredmin", vsource = VSOURCE.MVV) + def VREDAND_VS = vArithGen(vInst = "vredand", vsource = VSOURCE.MVV) + def VREDOR_VS = vArithGen(vInst = "vredor", vsource = VSOURCE.MVV) + def VREDXOR_VS = vArithGen(vInst = "vredxor", vsource = VSOURCE.MVV) + def VMAND_MM = vArithGen(vInst = "vmand", vsource = VSOURCE.MVV, vm = "1") def VMNAND_MM = vArithGen(vInst = "vmnand", vsource = VSOURCE.MVV, vm = "1") def VMANDN_MM = vArithGen(vInst = "vmandn", vsource = VSOURCE.MVV, vm = "1") diff --git a/src/main/scala/hajime/vectormodules/VectorExecUnit.scala b/src/main/scala/hajime/vectormodules/VectorExecUnit.scala index 488c81ce..945d6373 100644 --- a/src/main/scala/hajime/vectormodules/VectorExecUnit.scala +++ b/src/main/scala/hajime/vectormodules/VectorExecUnit.scala @@ -49,6 +49,7 @@ abstract class VectorExecUnit(implicit params: HajimeCoreParams) extends Module )) val idx = RegInit(0.U(log2Up(params.vlen/8).W)) + val reductionAccumulator = RegInit(0.U(params.xprlen.W)) val executedNum = RegInit(0.U(log2Up(params.vlen/8).W)) when((io.signalIn.valid && io.signalIn.ready) || io.dataOut.toVRF.bits.last) { idx := 0.U @@ -194,22 +195,34 @@ class IntegerAluExecUnit(implicit params: HajimeCoreParams) extends VectorExecUn (vs2Mask && vs1Mask) :: !(vs2Mask && vs1Mask) :: (vs2Mask && !vs1Mask) :: (vs2Mask ^ vs1Mask) :: (vs2Mask || vs1Mask) :: !(vs2Mask || vs1Mask) :: (vs2Mask || !vs1Mask) :: !(vs2Mask ^ vs1Mask) :: multiplyResLowBits :: multiplyResHighBits :: multiplyResHighBits :: multiplyResHighBits :: - mulAddRes :: mulAddRes :: mulAddRes :: mulAddRes :: Nil + mulAddRes :: mulAddRes :: mulAddRes :: mulAddRes :: + // reduction + vs2Out + vs1Out :: Mux(vs2Out > vs1Out, vs2Out, vs1Out) :: Mux(vs2Out.asSInt > vs1Out.asSInt, vs2Out, vs1Out) :: + Mux(vs2Out < vs1Out, vs2Out, vs1Out) :: Mux(vs2Out.asSInt < vs1Out.asSInt, vs2Out, vs1Out) :: + (vs2Out & vs1Out) :: (vs2Out | vs1Out) :: (vs2Out ^ vs1Out) :: Nil } import VEU_FUN._ // TODO: vs1Outの判定はMVVではなくベクトルマスク命令か否かで - valueToExec.vs1Out := Mux(instInfoReg.bits.vectorDecode.vSource === VSOURCE.MVV.asUInt, execValue1(7,0)(idx(2,0)), execValue1) + valueToExec.vs1Out := MuxCase(execValue1, Seq( + (instInfoReg.bits.vectorDecode.vSource === VSOURCE.MVV.asUInt) -> execValue1(7,0)(idx(2,0)), + (instInfoReg.bits.vectorDecode.veuFun.isReductionInst) -> Mux(idx === 0.U, execValue1, reductionAccumulator) + )) // Mux(instInfoReg.bits.vectorDecode.vSource === VSOURCE.MVV.asUInt, execValue1(7,0)(idx(2,0)), execValue1) valueToExec.vs2Out := Mux(instInfoReg.bits.vectorDecode.vSource === VSOURCE.MVV.asUInt, execValue2(7,0)(idx(2,0)), execValue2) // VMADC, VMSBCでマスクが無効(vm=1)の場合は0 valueToExec.vm := !(instInfoReg.bits.vectorDecode.veuFun.isCarryMask && instInfoReg.bits.vectorDecode.vm) && io.readVrf.resp.vm - val rawResult = MuxLookup(instInfoReg.bits.vectorDecode.veuFun, 0.U)( + // reductionでvm=0ならばaccumulatorをそのまま入れる + val rawResult = Mux(instInfoReg.bits.vectorDecode.veuFun.isReductionInst && !instInfoReg.bits.vectorDecode.vm && !io.readVrf.resp.vm, + reductionAccumulator, + MuxLookup(instInfoReg.bits.vectorDecode.veuFun, 0.U)( Seq(ADD, SUB, RSUB, ADC, MADC, SBC, MSBC, SEQ, SNE, SLTU, SLT, SLEU, SLE, SGTU, SGT, MINU, MIN, MAXU, MAX, MERGE, MV, AND, OR, XOR, MAND, MNAND, MANDN, MXOR, MOR, MNOR, MORN, MXNOR, - MUL, MULH, MULHU, MULHSU, MACC, NMSAC, MADD, NMSUB).zipWithIndex.map( + MUL, MULH, MULHU, MULHSU, MACC, NMSAC, MADD, NMSUB, + REDSUM, REDMAXU, REDMAX, REDMINU, REDMIN, REDAND, REDOR, REDXOR).zipWithIndex.map( x => x._1.asUInt -> execResult(x._2) ) - ) + )) + reductionAccumulator := rawResult io.dataOut.toVRF.bits.data := Mux(instInfoReg.bits.vectorDecode.veuFun.writeAsMask, MuxLookup(idx(2, 0), rawResult)( (0 until 8).map( @@ -220,7 +233,12 @@ class IntegerAluExecUnit(implicit params: HajimeCoreParams) extends VectorExecUn ), rawResult) io.dataOut.toVRF.bits.vm := instInfoReg.bits.vectorDecode.veuFun.writeAsMask // vadc, vmadc, bsbc, vmsbc, vmerge, vmand...vmxnor writes to VRF regardless of vm - io.dataOut.toVRF.bits.writeReq := instInfoReg.bits.vectorDecode.vm || io.readVrf.resp.vm || instInfoReg.bits.vectorDecode.veuFun.ignoreMask || instInfoReg.bits.vectorDecode.veuFun.isMaskInst + // reductionならば最後のみ書く + io.dataOut.toVRF.bits.writeReq := Mux(instInfoReg.bits.vectorDecode.veuFun.isReductionInst, io.dataOut.toVRF.bits.last, instInfoReg.bits.vectorDecode.vm || io.readVrf.resp.vm || instInfoReg.bits.vectorDecode.veuFun.ignoreMask || instInfoReg.bits.vectorDecode.veuFun.isMaskInst) + // reductionならばidxは0 + when(instInfoReg.bits.vectorDecode.veuFun.isReductionInst) { + io.dataOut.toVRF.bits.index := 0.U + } } object IntegerAluExecUnit extends App { diff --git a/src/main/scala/hajime/vectormodules/VectorOpConstants.scala b/src/main/scala/hajime/vectormodules/VectorOpConstants.scala index c853d51e..893f5dc6 100644 --- a/src/main/scala/hajime/vectormodules/VectorOpConstants.scala +++ b/src/main/scala/hajime/vectormodules/VectorOpConstants.scala @@ -27,11 +27,13 @@ trait VectorOpConstants { object VEU_FUN extends ChiselEnum { val NONE, ADD, SUB, RSUB, ADC, MADC, SBC, MSBC, SEQ, SNE, SLTU, SLT, SLEU, SLE, SGTU, SGT, MINU, MIN, MAXU, MAX, MERGE, MV, AND, OR, XOR, MAND, MNAND, MANDN, MXOR, MOR, MNOR, MORN, MXNOR, - MUL, MULH, MULHU, MULHSU, MACC, NMSAC, MADD, NMSUB = Value + MUL, MULH, MULHU, MULHSU, MACC, NMSAC, MADD, NMSUB, + REDSUM, REDMAXU, REDMAX, REDMINU, REDMIN, REDAND, REDOR, REDXOR = Value val compMaskList = SEQ :: SNE :: SLTU :: SLT :: SLEU :: SLE :: SGTU :: SGT :: Nil val carryMaskList = MADC :: MSBC :: Nil val ignoreMaskList = ADC :: MADC :: SBC :: MSBC :: MERGE :: Nil val maskInstList = MAND :: MNAND :: MANDN :: MXOR :: MOR :: MNOR :: MORN :: MXNOR :: Nil + val reductionInstList = REDSUM :: REDMAXU :: REDMAX :: REDMINU :: REDMIN :: REDAND :: REDOR :: REDXOR :: Nil implicit class masks(signal: UInt) { def isCompMask: Bool = { @@ -52,6 +54,9 @@ trait VectorOpConstants { def writeAsMask: Bool = { signal.isArithmeticMask || signal.isMaskInst } + def isReductionInst: Bool = { + reductionInstList.map(_.asUInt).has(signal) + } } } From 92d08d24e7976000719b5188a556a962067a1929 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Mon, 13 Nov 2023 18:59:34 +0900 Subject: [PATCH 09/14] decode reduction inst --- .../scala/hajime/publicmodules/Decoder.scala | 8 ++++++++ .../hajime/vectormodules/VectorDecoder.scala | 18 +++++++++++++++++- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/src/main/scala/hajime/publicmodules/Decoder.scala b/src/main/scala/hajime/publicmodules/Decoder.scala index 5bc0337a..14852274 100644 --- a/src/main/scala/hajime/publicmodules/Decoder.scala +++ b/src/main/scala/hajime/publicmodules/Decoder.scala @@ -271,6 +271,14 @@ object RvvDecode extends DecodeConstants { VMADD_VX -> List(Y, Branch.NONE, Value1.RS1, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), VNMSUB_VV -> List(Y, Branch.NONE, Value1.ZERO, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), VNMSUB_VX -> List(Y, Branch.NONE, Value1.RS1, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), + VREDSUM_VS -> List(Y, Branch.NONE, Value1.ZERO, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), + VREDMAXU_VS -> List(Y, Branch.NONE, Value1.ZERO, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), + VREDMAX_VS -> List(Y, Branch.NONE, Value1.ZERO, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), + VREDMINU_VS -> List(Y, Branch.NONE, Value1.ZERO, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), + VREDMIN_VS -> List(Y, Branch.NONE, Value1.ZERO, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), + VREDAND_VS -> List(Y, Branch.NONE, Value1.ZERO, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), + VREDOR_VS -> List(Y, Branch.NONE, Value1.ZERO, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), + VREDXOR_VS -> List(Y, Branch.NONE, Value1.ZERO, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), ) } diff --git a/src/main/scala/hajime/vectormodules/VectorDecoder.scala b/src/main/scala/hajime/vectormodules/VectorDecoder.scala index 272a7905..722e890d 100644 --- a/src/main/scala/hajime/vectormodules/VectorDecoder.scala +++ b/src/main/scala/hajime/vectormodules/VectorDecoder.scala @@ -51,6 +51,14 @@ object VDecode extends DecodeConstants with VectorOpConstants { case "vnmsac" => NMSAC case "vmadd" => MADD case "vnmsub" => NMSUB + case "vredsum" => REDSUM + case "vredmaxu" => REDMAXU + case "vredmax" => REDMAX + case "vredminu" => REDMINU + case "vredmin" => REDMIN + case "vredand" => REDAND + case "vredor" => REDOR + case "vredxor" => REDXOR case "vmand" => MAND case "vmnand" => MNAND case "vmandn" => MANDN @@ -192,7 +200,15 @@ object VDecode extends DecodeConstants with VectorOpConstants { VMADD_VV -> amogus("vmadd", VSOURCE.VV), VMADD_VX -> amogus("vmadd", VSOURCE.VX), VNMSUB_VV -> amogus("vnmsub", VSOURCE.VV), - VNMSUB_VX -> amogus("vnmsub", VSOURCE.VX) + VNMSUB_VX -> amogus("vnmsub", VSOURCE.VX), + VREDSUM_VS -> amogus("vredsum", VSOURCE.VV), + VREDMAXU_VS -> amogus("vredmaxu", VSOURCE.VV), + VREDMAX_VS -> amogus("vredmax", VSOURCE.VV), + VREDMINU_VS -> amogus("vredminu", VSOURCE.VV), + VREDMIN_VS -> amogus("vredmin", VSOURCE.VV), + VREDAND_VS -> amogus("vredand", VSOURCE.VV), + VREDOR_VS -> amogus("vredor", VSOURCE.VV), + VREDXOR_VS -> amogus("vredxor", VSOURCE.VV), ) } From acefad15d847bc442789b8c80fb55c018632d481 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Mon, 13 Nov 2023 19:19:18 +0900 Subject: [PATCH 10/14] a --- .../applications_vector/vredsum/vredsum.c | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 src/main/resources/applications_vector/vredsum/vredsum.c diff --git a/src/main/resources/applications_vector/vredsum/vredsum.c b/src/main/resources/applications_vector/vredsum/vredsum.c new file mode 100644 index 00000000..405dfbda --- /dev/null +++ b/src/main/resources/applications_vector/vredsum/vredsum.c @@ -0,0 +1,84 @@ +#include "util.h" + +#define size_t long +#define N 48 + +const signed short dataArray0[N] = {227, 222, 39, 155, 33, 229, 40, 58, 172, 122, 182, 72, 70, 11, 29, 209, 168, 250, 120, 66, 179, 133, 115, 55, 253, 82, 196, 219, 44, 120, 18, 179, 143, 6, 120, 112, 192, 18, 144, 89, 238, 106, 17, 50, 153, 105, 173, 160}; +signed short result, answer; + +extern void printstr(char* str); +extern void int64ToHex(long num, char* str); +extern void int32ToHex(int num, char* str); +extern void clearCounters(); +extern void printCounters(); + +int main(int argc, char** argv) { + int vl, avl = 41; + const signed short *ptr0 = dataArray0; + signed short sum = 0; + while(avl != 0) { + asm volatile ("vsetvli %0, %1, e16, m1, ta, ma" + : "=r"(vl) + : "r"(avl)); + // v11[0] = sum; + asm volatile ("vmv.s.x v11, %0" + : + : "r"(sum)); + asm volatile ("vle16.v v10, (%0)" + : + : "r"(ptr0)); + // v10[0] = sum + sum(v10) + asm volatile ("vredsum.vs v10, v10, v11"); + // sum = sum(v10) + asm volatile ("vmv.x.s %0, v10" + : "=r"(sum)); + ptr0 += vl; + avl -= vl; + } + int i; + for(i=0; i<41; i++) { + answerArray[i] = -(dataArray0[i] * dataArray2[i]) + dataArray1[i]; + } + + _Bool correct = 1; + for(i=0; i<41; i++) { + if(resultArray[i] != answerArray[i]) { + correct = 0; + } + } + avl = 41; + ptr0 = dataArray0; + ptr1 = dataArray1; + ptr3 = resultArray; + while(avl != 0) { + asm volatile ("vsetvli %0, %1, e16, m1, ta, ma" + : "=r"(vl) + : "r"(avl)); + asm volatile ("vle16.v v10, (%0)" + : + : "r"(ptr0)); + asm volatile ("vle16.v v11, (%0)" + : + : "r"(ptr1)); + // v11 = -(0x1919 * v11) + v10 + asm volatile ("vnmsub.vx v11, %0, v10" + : + : "r"(0x1919)); + asm volatile ("vse16.v v11, (%0)" + : + : "r"(ptr3)); + ptr0 += vl; + ptr1 += vl; + ptr3 += vl; + avl -= vl; + } + for(i=0; i<41; i++) { + answerArray[i] = -(0x1919 * dataArray1[i]) + dataArray0[i]; + } + for(i=0; i<41; i++) { + if(resultArray[i] != answerArray[i]) { + correct = 0; + } + } + return !correct; +} \ No newline at end of file From 71dfb9d5e4357ff9e1ed4b4a836014d26ef23ed8 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Mon, 13 Nov 2023 19:50:34 +0900 Subject: [PATCH 11/14] a --- .../applications_vector/vredsum/vredsum.c | 46 ++----------------- 1 file changed, 4 insertions(+), 42 deletions(-) diff --git a/src/main/resources/applications_vector/vredsum/vredsum.c b/src/main/resources/applications_vector/vredsum/vredsum.c index 405dfbda..1a446439 100644 --- a/src/main/resources/applications_vector/vredsum/vredsum.c +++ b/src/main/resources/applications_vector/vredsum/vredsum.c @@ -35,50 +35,12 @@ int main(int argc, char** argv) { ptr0 += vl; avl -= vl; } - int i; + result = sum; + int i, answer = 0; for(i=0; i<41; i++) { - answerArray[i] = -(dataArray0[i] * dataArray2[i]) + dataArray1[i]; + answer += dataArray0[i]; } - _Bool correct = 1; - for(i=0; i<41; i++) { - if(resultArray[i] != answerArray[i]) { - correct = 0; - } - } - avl = 41; - ptr0 = dataArray0; - ptr1 = dataArray1; - ptr3 = resultArray; - while(avl != 0) { - asm volatile ("vsetvli %0, %1, e16, m1, ta, ma" - : "=r"(vl) - : "r"(avl)); - asm volatile ("vle16.v v10, (%0)" - : - : "r"(ptr0)); - asm volatile ("vle16.v v11, (%0)" - : - : "r"(ptr1)); - // v11 = -(0x1919 * v11) + v10 - asm volatile ("vnmsub.vx v11, %0, v10" - : - : "r"(0x1919)); - asm volatile ("vse16.v v11, (%0)" - : - : "r"(ptr3)); - ptr0 += vl; - ptr1 += vl; - ptr3 += vl; - avl -= vl; - } - for(i=0; i<41; i++) { - answerArray[i] = -(0x1919 * dataArray1[i]) + dataArray0[i]; - } - for(i=0; i<41; i++) { - if(resultArray[i] != answerArray[i]) { - correct = 0; - } - } + _Bool correct = (result == answer); return !correct; } \ No newline at end of file From 2e60ed565639887ab816130e5331660d4c5b5780 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Tue, 14 Nov 2023 16:41:25 +0900 Subject: [PATCH 12/14] vredsum dont works? --- .../resources/applications_vector/build.sh | 17 + .../applications_vector/vredsum.dump | 951 ++++++++++++++++++ .../applications_vector/vredsum_data.hex | 132 +++ .../applications_vector/vredsum_inst.hex | 603 +++++++++++ .../scala/hajime/common/Instructions.scala | 16 +- .../scala/hajime/publicmodules/Decoder.scala | 2 + .../hajime/vectormodules/VectorCpu.scala | 9 +- .../hajime/vectormodules/VectorDecoder.scala | 6 +- .../hajime/vectormodules/VectorExecUnit.scala | 20 + .../vectormodules/VectorOpConstants.scala | 3 +- .../hajime/vectormodules/VectorCpuSpec.scala | 1 + 11 files changed, 1751 insertions(+), 9 deletions(-) create mode 100644 src/main/resources/applications_vector/vredsum.dump create mode 100644 src/main/resources/applications_vector/vredsum_data.hex create mode 100644 src/main/resources/applications_vector/vredsum_inst.hex diff --git a/src/main/resources/applications_vector/build.sh b/src/main/resources/applications_vector/build.sh index 1f2fe07e..c3c5f129 100644 --- a/src/main/resources/applications_vector/build.sh +++ b/src/main/resources/applications_vector/build.sh @@ -501,4 +501,21 @@ hexdump -v -e '1/4 "%08x" "\n"' vnmsub_text_startup.bin > vnmsub_text_startup.te cat vnmsub_rodata.temp vnmsub_rodata_str1_8.temp vnmsub_sdata.temp > vnmsub_data.hex cat vnmsub_text_init.temp vnmsub_text.temp vnmsub_text_startup.temp > vnmsub_inst.hex +riscv64-unknown-elf-gcc -I ../application_headers -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv64im_zicsr_zve64x -mabi=lp64 -o vredsum.riscv ./vredsum/vredsum.c ../application_headers/syscalls.c ../application_headers/crt.S -static -nostdlib -nostartfiles -T ../application_headers/test.ld +riscv64-unknown-elf-objdump --disassemble-all vredsum.riscv > vredsum.dump +riscv64-unknown-elf-objcopy --dump-section .rodata=vredsum_rodata.bin vredsum.riscv +riscv64-unknown-elf-objcopy --dump-section .rodata.str1.8=vredsum_rodata_str1_8.bin vredsum.riscv +riscv64-unknown-elf-objcopy --dump-section .sdata=vredsum_sdata.bin vredsum.riscv +riscv64-unknown-elf-objcopy --dump-section .text.init=vredsum_text_init.bin vredsum.riscv +riscv64-unknown-elf-objcopy --dump-section .text=vredsum_text.bin vredsum.riscv +riscv64-unknown-elf-objcopy --dump-section .text.startup=vredsum_text_startup.bin vredsum.riscv +hexdump -v -e '1/4 "%08x" "\n"' vredsum_rodata.bin > vredsum_rodata.temp +hexdump -v -e '1/4 "%08x" "\n"' vredsum_rodata_str1_8.bin > vredsum_rodata_str1_8.temp +hexdump -v -e '1/4 "%08x" "\n"' vredsum_sdata.bin > vredsum_sdata.temp +hexdump -v -e '1/4 "%08x" "\n"' vredsum_text_init.bin > vredsum_text_init.temp +hexdump -v -e '1/4 "%08x" "\n"' vredsum_text.bin > vredsum_text.temp +hexdump -v -e '1/4 "%08x" "\n"' vredsum_text_startup.bin > vredsum_text_startup.temp +cat vredsum_rodata.temp vredsum_rodata_str1_8.temp vredsum_sdata.temp > vredsum_data.hex +cat vredsum_text_init.temp vredsum_text.temp vredsum_text_startup.temp > vredsum_inst.hex + rm *.riscv *.bin *.temp \ No newline at end of file diff --git a/src/main/resources/applications_vector/vredsum.dump b/src/main/resources/applications_vector/vredsum.dump new file mode 100644 index 00000000..951811ff --- /dev/null +++ b/src/main/resources/applications_vector/vredsum.dump @@ -0,0 +1,951 @@ + +vredsum.riscv: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000000000000 <_start>: + 0: 00000093 li ra,0 + 4: 00000113 li sp,0 + 8: 00000193 li gp,0 + c: 00000213 li tp,0 + 10: 00000293 li t0,0 + 14: 00000313 li t1,0 + 18: 00000393 li t2,0 + 1c: 00000413 li s0,0 + 20: 00000493 li s1,0 + 24: 00000513 li a0,0 + 28: 00000593 li a1,0 + 2c: 00000613 li a2,0 + 30: 00000693 li a3,0 + 34: 00000713 li a4,0 + 38: 00000793 li a5,0 + 3c: 00000813 li a6,0 + 40: 00000893 li a7,0 + 44: 00000913 li s2,0 + 48: 00000993 li s3,0 + 4c: 00000a13 li s4,0 + 50: 00000a93 li s5,0 + 54: 00000b13 li s6,0 + 58: 00000b93 li s7,0 + 5c: 00000c13 li s8,0 + 60: 00000c93 li s9,0 + 64: 00000d13 li s10,0 + 68: 00000d93 li s11,0 + 6c: 00000e13 li t3,0 + 70: 00000e93 li t4,0 + 74: 00000f13 li t5,0 + 78: 00000f93 li t6,0 + 7c: 00000297 auipc t0,0x0 + 80: 03828293 add t0,t0,56 # b4 + 84: 30529073 csrw mtvec,t0 + 88: 00005197 auipc gp,0x5 + 8c: 98018193 add gp,gp,-1664 # 4a08 <__global_pointer$> + 90: 10000217 auipc tp,0x10000 + 94: ff720213 add tp,tp,-9 # 10000087 <_end+0x3f> + 98: fc027213 and tp,tp,-64 + 9c: f1402573 csrr a0,mhartid + a0: 00100593 li a1,1 + a4: 00b57063 bgeu a0,a1,a4 <_start+0xa4> + a8: 00006137 lui sp,0x6 + ac: ff01011b addw sp,sp,-16 # 5ff0 <__global_pointer$+0x15e8> + b0: 6580006f j 708 <_init> + +00000000000000b4 : + b4: ef010113 add sp,sp,-272 + b8: 00113423 sd ra,8(sp) + bc: 00213823 sd sp,16(sp) + c0: 00313c23 sd gp,24(sp) + c4: 02413023 sd tp,32(sp) + c8: 02513423 sd t0,40(sp) + cc: 02613823 sd t1,48(sp) + d0: 02713c23 sd t2,56(sp) + d4: 04813023 sd s0,64(sp) + d8: 04913423 sd s1,72(sp) + dc: 04a13823 sd a0,80(sp) + e0: 04b13c23 sd a1,88(sp) + e4: 06c13023 sd a2,96(sp) + e8: 06d13423 sd a3,104(sp) + ec: 06e13823 sd a4,112(sp) + f0: 06f13c23 sd a5,120(sp) + f4: 09013023 sd a6,128(sp) + f8: 09113423 sd a7,136(sp) + fc: 09213823 sd s2,144(sp) + 100: 09313c23 sd s3,152(sp) + 104: 0b413023 sd s4,160(sp) + 108: 0b513423 sd s5,168(sp) + 10c: 0b613823 sd s6,176(sp) + 110: 0b713c23 sd s7,184(sp) + 114: 0d813023 sd s8,192(sp) + 118: 0d913423 sd s9,200(sp) + 11c: 0da13823 sd s10,208(sp) + 120: 0db13c23 sd s11,216(sp) + 124: 0fc13023 sd t3,224(sp) + 128: 0fd13423 sd t4,232(sp) + 12c: 0fe13823 sd t5,240(sp) + 130: 0ff13c23 sd t6,248(sp) + 134: 34202573 csrr a0,mcause + 138: 341025f3 csrr a1,mepc + 13c: 00010613 mv a2,sp + 140: 2d0000ef jal 410 + 144: 34151073 csrw mepc,a0 + 148: 000022b7 lui t0,0x2 + 14c: 8002829b addw t0,t0,-2048 # 1800 + 150: 3002a073 csrs mstatus,t0 + 154: 00813083 ld ra,8(sp) + 158: 01013103 ld sp,16(sp) + 15c: 01813183 ld gp,24(sp) + 160: 02013203 ld tp,32(sp) + 164: 02813283 ld t0,40(sp) + 168: 03013303 ld t1,48(sp) + 16c: 03813383 ld t2,56(sp) + 170: 04013403 ld s0,64(sp) + 174: 04813483 ld s1,72(sp) + 178: 05013503 ld a0,80(sp) + 17c: 05813583 ld a1,88(sp) + 180: 06013603 ld a2,96(sp) + 184: 06813683 ld a3,104(sp) + 188: 07013703 ld a4,112(sp) + 18c: 07813783 ld a5,120(sp) + 190: 08013803 ld a6,128(sp) + 194: 08813883 ld a7,136(sp) + 198: 09013903 ld s2,144(sp) + 19c: 09813983 ld s3,152(sp) + 1a0: 0a013a03 ld s4,160(sp) + 1a4: 0a813a83 ld s5,168(sp) + 1a8: 0b013b03 ld s6,176(sp) + 1ac: 0b813b83 ld s7,184(sp) + 1b0: 0c013c03 ld s8,192(sp) + 1b4: 0c813c83 ld s9,200(sp) + 1b8: 0d013d03 ld s10,208(sp) + 1bc: 0d813d83 ld s11,216(sp) + 1c0: 0e013e03 ld t3,224(sp) + 1c4: 0e813e83 ld t4,232(sp) + 1c8: 0f013f03 ld t5,240(sp) + 1cc: 0f813f83 ld t6,248(sp) + 1d0: 11010113 add sp,sp,272 + 1d4: 30200073 mret + +Disassembly of section .text: + +00000000000001d8 : + 1d8: b0201073 csrw minstret,zero + 1dc: b0001073 csrw mcycle,zero + 1e0: 00008067 ret + +00000000000001e4 : + 1e4: 03000793 li a5,48 + 1e8: 00f58023 sb a5,0(a1) + 1ec: 07800793 li a5,120 + 1f0: 00f580a3 sb a5,1(a1) + 1f4: 00158813 add a6,a1,1 + 1f8: 00958793 add a5,a1,9 + 1fc: 00900613 li a2,9 + 200: 00f57713 and a4,a0,15 + 204: 03770693 add a3,a4,55 + 208: 00e66463 bltu a2,a4,210 + 20c: 03070693 add a3,a4,48 + 210: 00d78023 sb a3,0(a5) + 214: fff78793 add a5,a5,-1 + 218: 40455513 sra a0,a0,0x4 + 21c: fef812e3 bne a6,a5,200 + 220: 00058523 sb zero,10(a1) + 224: 00008067 ret + +0000000000000228 : + 228: 03000793 li a5,48 + 22c: 00f58023 sb a5,0(a1) + 230: 07800793 li a5,120 + 234: 00f580a3 sb a5,1(a1) + 238: 00158813 add a6,a1,1 + 23c: 01158793 add a5,a1,17 + 240: 00900613 li a2,9 + 244: 00f57713 and a4,a0,15 + 248: 03770693 add a3,a4,55 + 24c: 00e66463 bltu a2,a4,254 + 250: 03070693 add a3,a4,48 + 254: 00d78023 sb a3,0(a5) + 258: fff78793 add a5,a5,-1 + 25c: 40455513 sra a0,a0,0x4 + 260: fef812e3 bne a6,a5,244 + 264: 00058923 sb zero,18(a1) + 268: 00008067 ret + +000000000000026c : + 26c: 00054783 lbu a5,0(a0) + 270: 00078c63 beqz a5,288 + 274: 10000737 lui a4,0x10000 + 278: 00f70023 sb a5,0(a4) # 10000000 + 27c: 00154783 lbu a5,1(a0) + 280: 00150513 add a0,a0,1 + 284: fe079ae3 bnez a5,278 + 288: 00008067 ret + +000000000000028c : + 28c: fe010113 add sp,sp,-32 + 290: c0202673 rdinstret a2 + 294: c00025f3 rdcycle a1 + 298: 00004717 auipc a4,0x4 + 29c: df870713 add a4,a4,-520 # 4090 + 2a0: 06300793 li a5,99 + 2a4: 100006b7 lui a3,0x10000 + 2a8: 00f68023 sb a5,0(a3) # 10000000 + 2ac: 00174783 lbu a5,1(a4) + 2b0: 00170713 add a4,a4,1 + 2b4: fe079ae3 bnez a5,2a8 + 2b8: ffff8737 lui a4,0xffff8 + 2bc: 83074713 xor a4,a4,-2000 + 2c0: 01910793 add a5,sp,25 + 2c4: 00e11423 sh a4,8(sp) + 2c8: 00910813 add a6,sp,9 + 2cc: 00078713 mv a4,a5 + 2d0: 00900893 li a7,9 + 2d4: 00f5f693 and a3,a1,15 + 2d8: 03768513 add a0,a3,55 + 2dc: 00d8e463 bltu a7,a3,2e4 + 2e0: 03068513 add a0,a3,48 + 2e4: 00a70023 sb a0,0(a4) # ffffffffffff8000 <_end+0xffffffffefff7fb8> + 2e8: fff70713 add a4,a4,-1 + 2ec: 4045d593 sra a1,a1,0x4 + 2f0: fee812e3 bne a6,a4,2d4 + 2f4: 00814703 lbu a4,8(sp) + 2f8: 00010d23 sb zero,26(sp) + 2fc: 00810693 add a3,sp,8 + 300: 100005b7 lui a1,0x10000 + 304: 00070a63 beqz a4,318 + 308: 00e58023 sb a4,0(a1) # 10000000 + 30c: 0016c703 lbu a4,1(a3) + 310: 00168693 add a3,a3,1 + 314: fe071ae3 bnez a4,308 + 318: 00004697 auipc a3,0x4 + 31c: d8068693 add a3,a3,-640 # 4098 + 320: 00a00713 li a4,10 + 324: 100005b7 lui a1,0x10000 + 328: 00e58023 sb a4,0(a1) # 10000000 + 32c: 0016c703 lbu a4,1(a3) + 330: 00168693 add a3,a3,1 + 334: fe071ae3 bnez a4,328 + 338: ffff8737 lui a4,0xffff8 + 33c: 83074713 xor a4,a4,-2000 + 340: 00060693 mv a3,a2 + 344: 00e11423 sh a4,8(sp) + 348: 00900593 li a1,9 + 34c: 00f6f713 and a4,a3,15 + 350: 03770613 add a2,a4,55 # ffffffffffff8037 <_end+0xffffffffefff7fef> + 354: 00e5e463 bltu a1,a4,35c + 358: 03070613 add a2,a4,48 + 35c: 00c78023 sb a2,0(a5) + 360: fff78793 add a5,a5,-1 + 364: 4046d693 sra a3,a3,0x4 + 368: fef812e3 bne a6,a5,34c + 36c: 00814783 lbu a5,8(sp) + 370: 00010d23 sb zero,26(sp) + 374: 00810713 add a4,sp,8 + 378: 100006b7 lui a3,0x10000 + 37c: 00078a63 beqz a5,390 + 380: 00f68023 sb a5,0(a3) # 10000000 + 384: 00174783 lbu a5,1(a4) + 388: 00170713 add a4,a4,1 + 38c: fe079ae3 bnez a5,380 + 390: 100007b7 lui a5,0x10000 + 394: 00a00713 li a4,10 + 398: 00e78023 sb a4,0(a5) # 10000000 + 39c: 02010113 add sp,sp,32 + 3a0: 00008067 ret + +00000000000003a4 : + 3a4: fe010113 add sp,sp,-32 + 3a8: 00813823 sd s0,16(sp) + 3ac: 00113c23 sd ra,24(sp) + 3b0: 00050413 mv s0,a0 + 3b4: 00004717 auipc a4,0x4 + 3b8: cf470713 add a4,a4,-780 # 40a8 + 3bc: 04500793 li a5,69 + 3c0: 100006b7 lui a3,0x10000 + 3c4: 00f68023 sb a5,0(a3) # 10000000 + 3c8: 00174783 lbu a5,1(a4) + 3cc: 00170713 add a4,a4,1 + 3d0: fe079ae3 bnez a5,3c4 + 3d4: 00010593 mv a1,sp + 3d8: 00040513 mv a0,s0 + 3dc: e09ff0ef jal 1e4 + 3e0: 00014703 lbu a4,0(sp) + 3e4: 00070e63 beqz a4,400 + 3e8: 00010793 mv a5,sp + 3ec: 100006b7 lui a3,0x10000 + 3f0: 00e68023 sb a4,0(a3) # 10000000 + 3f4: 0017c703 lbu a4,1(a5) + 3f8: 00178793 add a5,a5,1 + 3fc: fe071ae3 bnez a4,3f0 + 400: 00040513 mv a0,s0 + 404: 100007b7 lui a5,0x10000 + 408: 00078023 sb zero,0(a5) # 10000000 + 40c: 0000006f j 40c + +0000000000000410 : + 410: ffff87b7 lui a5,0xffff8 + 414: fd010113 add sp,sp,-48 + 418: 8307c793 xor a5,a5,-2000 + 41c: 00f11423 sh a5,8(sp) + 420: 02113423 sd ra,40(sp) + 424: 01910793 add a5,sp,25 + 428: 00910813 add a6,sp,9 + 42c: 00900613 li a2,9 + 430: 00f5f713 and a4,a1,15 + 434: 03770693 add a3,a4,55 + 438: 00e66463 bltu a2,a4,440 + 43c: 03070693 add a3,a4,48 + 440: 00d78023 sb a3,0(a5) # ffffffffffff8000 <_end+0xffffffffefff7fb8> + 444: fff78793 add a5,a5,-1 + 448: 4045d593 sra a1,a1,0x4 + 44c: ff0792e3 bne a5,a6,430 + 450: 00010d23 sb zero,26(sp) + 454: 00b00793 li a5,11 + 458: 02a7e063 bltu a5,a0,478 + 45c: 00004717 auipc a4,0x4 + 460: c0470713 add a4,a4,-1020 # 4060 + 464: 00251513 sll a0,a0,0x2 + 468: 00e50533 add a0,a0,a4 + 46c: 00052783 lw a5,0(a0) + 470: 00e787b3 add a5,a5,a4 + 474: 00078067 jr a5 + 478: 00004717 auipc a4,0x4 + 47c: d5870713 add a4,a4,-680 # 41d0 + 480: 05500793 li a5,85 + 484: 100006b7 lui a3,0x10000 + 488: 00f68023 sb a5,0(a3) # 10000000 + 48c: 00174783 lbu a5,1(a4) + 490: 00170713 add a4,a4,1 + 494: fe079ae3 bnez a5,488 + 498: 00814783 lbu a5,8(sp) + 49c: 00810713 add a4,sp,8 + 4a0: 100006b7 lui a3,0x10000 + 4a4: 00078a63 beqz a5,4b8 + 4a8: 00f68023 sb a5,0(a3) # 10000000 + 4ac: 00174783 lbu a5,1(a4) + 4b0: 00170713 add a4,a4,1 + 4b4: fe079ae3 bnez a5,4a8 + 4b8: 00004717 auipc a4,0x4 + 4bc: d3870713 add a4,a4,-712 # 41f0 + 4c0: 00a00793 li a5,10 + 4c4: 100006b7 lui a3,0x10000 + 4c8: 00f68023 sb a5,0(a3) # 10000000 + 4cc: 00174783 lbu a5,1(a4) + 4d0: 00170713 add a4,a4,1 + 4d4: fe079ae3 bnez a5,4c8 + 4d8: fff00513 li a0,-1 + 4dc: ec9ff0ef jal 3a4 + 4e0: 00004717 auipc a4,0x4 + 4e4: bd870713 add a4,a4,-1064 # 40b8 + 4e8: 04900793 li a5,73 + 4ec: 100006b7 lui a3,0x10000 + 4f0: 00f68023 sb a5,0(a3) # 10000000 + 4f4: 00174783 lbu a5,1(a4) + 4f8: 00170713 add a4,a4,1 + 4fc: fe079ae3 bnez a5,4f0 + 500: 00814783 lbu a5,8(sp) + 504: 00810713 add a4,sp,8 + 508: 100006b7 lui a3,0x10000 + 50c: fc0786e3 beqz a5,4d8 + 510: 00f68023 sb a5,0(a3) # 10000000 + 514: 00174783 lbu a5,1(a4) + 518: 00170713 add a4,a4,1 + 51c: fe079ae3 bnez a5,510 + 520: fb9ff06f j 4d8 + 524: 00004717 auipc a4,0x4 + 528: bbc70713 add a4,a4,-1092 # 40e0 + 52c: 04900793 li a5,73 + 530: 100006b7 lui a3,0x10000 + 534: 00f68023 sb a5,0(a3) # 10000000 + 538: 00174783 lbu a5,1(a4) + 53c: 00170713 add a4,a4,1 + 540: fe079ae3 bnez a5,534 + 544: 00814783 lbu a5,8(sp) + 548: f80788e3 beqz a5,4d8 + 54c: 00810713 add a4,sp,8 + 550: 100006b7 lui a3,0x10000 + 554: 00f68023 sb a5,0(a3) # 10000000 + 558: 00174783 lbu a5,1(a4) + 55c: 00170713 add a4,a4,1 + 560: fe079ae3 bnez a5,554 + 564: f75ff06f j 4d8 + 568: 00004717 auipc a4,0x4 + 56c: ba070713 add a4,a4,-1120 # 4108 + 570: 04900793 li a5,73 + 574: 100006b7 lui a3,0x10000 + 578: 00f68023 sb a5,0(a3) # 10000000 + 57c: 00174783 lbu a5,1(a4) + 580: 00170713 add a4,a4,1 + 584: fe079ae3 bnez a5,578 + 588: 00814783 lbu a5,8(sp) + 58c: f40786e3 beqz a5,4d8 + 590: 00810713 add a4,sp,8 + 594: 100006b7 lui a3,0x10000 + 598: 00f68023 sb a5,0(a3) # 10000000 + 59c: 00174783 lbu a5,1(a4) + 5a0: 00170713 add a4,a4,1 + 5a4: fe079ae3 bnez a5,598 + 5a8: f31ff06f j 4d8 + 5ac: 00004717 auipc a4,0x4 + 5b0: b7c70713 add a4,a4,-1156 # 4128 + 5b4: 04c00793 li a5,76 + 5b8: 100006b7 lui a3,0x10000 + 5bc: 00f68023 sb a5,0(a3) # 10000000 + 5c0: 00174783 lbu a5,1(a4) + 5c4: 00170713 add a4,a4,1 + 5c8: fe079ae3 bnez a5,5bc + 5cc: 00814783 lbu a5,8(sp) + 5d0: f00784e3 beqz a5,4d8 + 5d4: 00810713 add a4,sp,8 + 5d8: 100006b7 lui a3,0x10000 + 5dc: 00f68023 sb a5,0(a3) # 10000000 + 5e0: 00174783 lbu a5,1(a4) + 5e4: 00170713 add a4,a4,1 + 5e8: fe079ae3 bnez a5,5dc + 5ec: eedff06f j 4d8 + 5f0: 00004717 auipc a4,0x4 + 5f4: b5870713 add a4,a4,-1192 # 4148 + 5f8: 04c00793 li a5,76 + 5fc: 100006b7 lui a3,0x10000 + 600: 00f68023 sb a5,0(a3) # 10000000 + 604: 00174783 lbu a5,1(a4) + 608: 00170713 add a4,a4,1 + 60c: fe079ae3 bnez a5,600 + 610: 00814783 lbu a5,8(sp) + 614: ec0782e3 beqz a5,4d8 + 618: 00810713 add a4,sp,8 + 61c: 100006b7 lui a3,0x10000 + 620: 00f68023 sb a5,0(a3) # 10000000 + 624: 00174783 lbu a5,1(a4) + 628: 00170713 add a4,a4,1 + 62c: fe079ae3 bnez a5,620 + 630: ea9ff06f j 4d8 + 634: 00004717 auipc a4,0x4 + 638: b3470713 add a4,a4,-1228 # 4168 + 63c: 05300793 li a5,83 + 640: 100006b7 lui a3,0x10000 + 644: 00f68023 sb a5,0(a3) # 10000000 + 648: 00174783 lbu a5,1(a4) + 64c: 00170713 add a4,a4,1 + 650: fe079ae3 bnez a5,644 + 654: 00814783 lbu a5,8(sp) + 658: e80780e3 beqz a5,4d8 + 65c: 00810713 add a4,sp,8 + 660: 100006b7 lui a3,0x10000 + 664: 00f68023 sb a5,0(a3) # 10000000 + 668: 00174783 lbu a5,1(a4) + 66c: 00170713 add a4,a4,1 + 670: fe079ae3 bnez a5,664 + 674: e65ff06f j 4d8 + 678: 00004717 auipc a4,0x4 + 67c: b1870713 add a4,a4,-1256 # 4190 + 680: 05300793 li a5,83 + 684: 100006b7 lui a3,0x10000 + 688: 00f68023 sb a5,0(a3) # 10000000 + 68c: 00174783 lbu a5,1(a4) + 690: 00170713 add a4,a4,1 + 694: fe079ae3 bnez a5,688 + 698: 00814783 lbu a5,8(sp) + 69c: e2078ee3 beqz a5,4d8 + 6a0: 00810713 add a4,sp,8 + 6a4: 100006b7 lui a3,0x10000 + 6a8: 00f68023 sb a5,0(a3) # 10000000 + 6ac: 00174783 lbu a5,1(a4) + 6b0: 00170713 add a4,a4,1 + 6b4: fe079ae3 bnez a5,6a8 + 6b8: e21ff06f j 4d8 + 6bc: 00004717 auipc a4,0x4 + 6c0: af470713 add a4,a4,-1292 # 41b0 + 6c4: 04500793 li a5,69 + 6c8: 100006b7 lui a3,0x10000 + 6cc: 00f68023 sb a5,0(a3) # 10000000 + 6d0: 00174783 lbu a5,1(a4) + 6d4: 00170713 add a4,a4,1 + 6d8: fe079ae3 bnez a5,6cc + 6dc: 00814783 lbu a5,8(sp) + 6e0: de078ce3 beqz a5,4d8 + 6e4: 00810713 add a4,sp,8 + 6e8: 100006b7 lui a3,0x10000 + 6ec: 00f68023 sb a5,0(a3) # 10000000 + 6f0: 00174783 lbu a5,1(a4) + 6f4: 00170713 add a4,a4,1 + 6f8: fe079ae3 bnez a5,6ec + 6fc: dddff06f j 4d8 + +0000000000000700 : + 700: 00051063 bnez a0,700 + 704: 00008067 ret + +0000000000000708 <_init>: + 708: ff010113 add sp,sp,-16 + 70c: 00000593 li a1,0 + 710: 00000513 li a0,0 + 714: 00113423 sd ra,8(sp) + 718: 1d8000ef jal 8f0
+ 71c: c89ff0ef jal 3a4 + +0000000000000720 : + 720: 00b567b3 or a5,a0,a1 + 724: 00c7e7b3 or a5,a5,a2 + 728: 0077f793 and a5,a5,7 + 72c: 00c50833 add a6,a0,a2 + 730: 02078463 beqz a5,758 + 734: 00c58633 add a2,a1,a2 + 738: 00050793 mv a5,a0 + 73c: 0b057663 bgeu a0,a6,7e8 + 740: 0005c703 lbu a4,0(a1) + 744: 00158593 add a1,a1,1 + 748: 00178793 add a5,a5,1 + 74c: fee78fa3 sb a4,-1(a5) + 750: fec598e3 bne a1,a2,740 + 754: 00008067 ret + 758: 04050693 add a3,a0,64 + 75c: 0906f863 bgeu a3,a6,7ec + 760: 00058713 mv a4,a1 + 764: 00068793 mv a5,a3 + 768: 00073383 ld t2,0(a4) + 76c: 00873283 ld t0,8(a4) + 770: 01073f83 ld t6,16(a4) + 774: 01873f03 ld t5,24(a4) + 778: 02073e83 ld t4,32(a4) + 77c: 02873e03 ld t3,40(a4) + 780: 03073303 ld t1,48(a4) + 784: 03873883 ld a7,56(a4) + 788: 04078793 add a5,a5,64 + 78c: f877b023 sd t2,-128(a5) + 790: f857b423 sd t0,-120(a5) + 794: f9f7b823 sd t6,-112(a5) + 798: f9e7bc23 sd t5,-104(a5) + 79c: fbd7b023 sd t4,-96(a5) + 7a0: fbc7b423 sd t3,-88(a5) + 7a4: fa67b823 sd t1,-80(a5) + 7a8: fb17bc23 sd a7,-72(a5) + 7ac: 04070713 add a4,a4,64 + 7b0: fb07ece3 bltu a5,a6,768 + 7b4: fbf60613 add a2,a2,-65 + 7b8: fc067793 and a5,a2,-64 + 7bc: 04078793 add a5,a5,64 + 7c0: fc067613 and a2,a2,-64 + 7c4: 00f585b3 add a1,a1,a5 + 7c8: 00c687b3 add a5,a3,a2 + 7cc: f907f4e3 bgeu a5,a6,754 + 7d0: 0005b703 ld a4,0(a1) + 7d4: 00878793 add a5,a5,8 + 7d8: 00858593 add a1,a1,8 + 7dc: fee7bc23 sd a4,-8(a5) + 7e0: ff07e8e3 bltu a5,a6,7d0 + 7e4: 00008067 ret + 7e8: 00008067 ret + 7ec: 00050793 mv a5,a0 + 7f0: fddff06f j 7cc + +00000000000007f4 : + 7f4: 00c567b3 or a5,a0,a2 + 7f8: 0077f793 and a5,a5,7 + 7fc: 00c50633 add a2,a0,a2 + 800: 0ff5f713 zext.b a4,a1 + 804: 00078e63 beqz a5,820 + 808: 00050793 mv a5,a0 + 80c: 02c57c63 bgeu a0,a2,844 + 810: 00178793 add a5,a5,1 + 814: fee78fa3 sb a4,-1(a5) + 818: fef61ce3 bne a2,a5,810 + 81c: 00008067 ret + 820: 00004797 auipc a5,0x4 + 824: 9e87b783 ld a5,-1560(a5) # 4208 + 828: 02f70733 mul a4,a4,a5 + 82c: fec578e3 bgeu a0,a2,81c + 830: 00050793 mv a5,a0 + 834: 00878793 add a5,a5,8 + 838: fee7bc23 sd a4,-8(a5) + 83c: fec7ece3 bltu a5,a2,834 + 840: 00008067 ret + 844: 00008067 ret + +0000000000000848 : + 848: 00054783 lbu a5,0(a0) + 84c: 00078e63 beqz a5,868 + 850: 00050793 mv a5,a0 + 854: 0017c703 lbu a4,1(a5) + 858: 00178793 add a5,a5,1 + 85c: fe071ce3 bnez a4,854 + 860: 40a78533 sub a0,a5,a0 + 864: 00008067 ret + 868: 00000513 li a0,0 + 86c: 00008067 ret + +0000000000000870 : + 870: 00b506b3 add a3,a0,a1 + 874: 00050793 mv a5,a0 + 878: 00059863 bnez a1,888 + 87c: 0240006f j 8a0 + 880: 00178793 add a5,a5,1 + 884: 00f68a63 beq a3,a5,898 + 888: 0007c703 lbu a4,0(a5) + 88c: fe071ae3 bnez a4,880 + 890: 40a78533 sub a0,a5,a0 + 894: 00008067 ret + 898: 40a68533 sub a0,a3,a0 + 89c: 00008067 ret + 8a0: 00000513 li a0,0 + 8a4: 00008067 ret + +00000000000008a8 : + 8a8: 00054783 lbu a5,0(a0) + 8ac: 00158593 add a1,a1,1 + 8b0: 00150513 add a0,a0,1 + 8b4: fff5c703 lbu a4,-1(a1) + 8b8: 00078a63 beqz a5,8cc + 8bc: fee786e3 beq a5,a4,8a8 + 8c0: 0007851b sext.w a0,a5 + 8c4: 40e5053b subw a0,a0,a4 + 8c8: 00008067 ret + 8cc: 00000513 li a0,0 + 8d0: ff5ff06f j 8c4 + +00000000000008d4 : + 8d4: 00050793 mv a5,a0 + 8d8: 0005c703 lbu a4,0(a1) + 8dc: 00178793 add a5,a5,1 + 8e0: 00158593 add a1,a1,1 + 8e4: fee78fa3 sb a4,-1(a5) + 8e8: fe0718e3 bnez a4,8d8 + 8ec: 00008067 ret + +Disassembly of section .text.startup: + +00000000000008f0
: + 8f0: 00000513 li a0,0 + 8f4: 00003697 auipc a3,0x3 + 8f8: 70c68693 add a3,a3,1804 # 4000 + 8fc: 02900713 li a4,41 + 900: 0c877657 vsetvli a2,a4,e16,m1,ta,ma + 904: 0006079b sext.w a5,a2 + 908: 420565d7 vmv.s.x v11,a0 + 90c: 0206d507 vle16.v v10,(a3) + 910: 02a5a557 vredsum.vs v10,v10,v11 + 914: 42a025d7 vmv.x.s a1,v10 + 918: 00179793 sll a5,a5,0x1 + 91c: 0105951b sllw a0,a1,0x10 + 920: 40c7073b subw a4,a4,a2 + 924: 4105551b sraw a0,a0,0x10 + 928: 00f686b3 add a3,a3,a5 + 92c: fc071ae3 bnez a4,900 + 930: 00004797 auipc a5,0x4 + 934: 8eb79123 sh a1,-1822(a5) # 4212 + 938: 00003797 auipc a5,0x3 + 93c: 6c878793 add a5,a5,1736 # 4000 + 940: 00003617 auipc a2,0x3 + 944: 71260613 add a2,a2,1810 # 4052 + 948: 00079683 lh a3,0(a5) + 94c: 00278793 add a5,a5,2 + 950: 00e6873b addw a4,a3,a4 + 954: fec79ae3 bne a5,a2,948 + 958: 40e50533 sub a0,a0,a4 + 95c: 00a03533 snez a0,a0 + 960: 00008067 ret + 964: fff00513 li a0,-1 + 968: 00008067 ret + +Disassembly of section .rodata: + +0000000000004000 : + 4000: 00de00e3 beq t3,a3,4800 <_tbss_end+0x5ec> + 4004: 009b0027 .4byte 0x9b0027 + 4008: 0021 vmsge.vx v0,v0,zero,v0.t + 400a: 00e5 .2byte 0xe5 + 400c: 0028 .2byte 0x28 + 400e: 003a .2byte 0x3a + 4010: 00ac .2byte 0xac + 4012: 007a .2byte 0x7a + 4014: 00b6 .2byte 0xb6 + 4016: 0048 .2byte 0x48 + 4018: 0046 .2byte 0x46 + 401a: 001d000b .4byte 0x1d000b + 401e: 00d1 .2byte 0xd1 + 4020: 00a8 .2byte 0xa8 + 4022: 00fa .2byte 0xfa + 4024: 0078 .2byte 0x78 + 4026: 0042 vmsge.vx v0,v0,zero,v0.t + 4028: 008500b3 add ra,a0,s0 + 402c: 00370073 .4byte 0x370073 + 4030: 00fd .2byte 0xfd + 4032: 0052 .2byte 0x52 + 4034: 00c4 .2byte 0xc4 + 4036: 002c00db .4byte 0x2c00db + 403a: 0078 .2byte 0x78 + 403c: 0012 .2byte 0x12 + 403e: 008f00b3 add ra,t5,s0 + 4042: 0006 .2byte 0x6 + 4044: 0078 .2byte 0x78 + 4046: 0070 .2byte 0x70 + 4048: 00c0 vmsge.vx v1,v0,zero,v0.t + 404a: 0012 .2byte 0x12 + 404c: 0090 .2byte 0x90 + 404e: 0059 .2byte 0x59 + 4050: 00ee .2byte 0xee + 4052: 006a .2byte 0x6a + 4054: 0011 .2byte 0x11 + 4056: 0032 .2byte 0x32 + 4058: 0099 .2byte 0x99 + 405a: 0069 .2byte 0x69 + 405c: 00ad .2byte 0xad + 405e: 00a0 vmsge.vx v1,v0,zero,v0.t + 4060: c480 vmsge.vx v9,v0,ra,v0.t + 4062: ffff .2byte 0xffff + 4064: c4c4 .2byte 0xc4c4 + 4066: ffff .2byte 0xffff + 4068: c508 .2byte 0xc508 + 406a: ffff .2byte 0xffff + 406c: c418 .2byte 0xc418 + 406e: ffff .2byte 0xffff + 4070: c54c .2byte 0xc54c + 4072: ffff .2byte 0xffff + 4074: c590 .2byte 0xc590 + 4076: ffff .2byte 0xffff + 4078: c5d4 .2byte 0xc5d4 + 407a: ffff .2byte 0xffff + 407c: c618 .2byte 0xc618 + 407e: ffff .2byte 0xffff + 4080: c418 .2byte 0xc418 + 4082: ffff .2byte 0xffff + 4084: c418 .2byte 0xc418 + 4086: ffff .2byte 0xffff + 4088: c418 .2byte 0xc418 + 408a: ffff .2byte 0xffff + 408c: c65c .2byte 0xc65c + 408e: ffff .2byte 0xffff + +Disassembly of section .rodata.str1.8: + +0000000000004090 <.rodata.str1.8>: + 4090: 6c637963 bgeu t1,t1,4762 <_tbss_end+0x54e> + 4094: 3a65 .2byte 0x3a65 + 4096: 0020 vmsge.vx v0,v0,zero,v0.t + 4098: 690a .2byte 0x690a + 409a: 736e .2byte 0x736e + 409c: 7274 .2byte 0x7274 + 409e: 7465 .2byte 0x7465 + 40a0: 203a .2byte 0x203a + 40a2: 0000 vmsge.vx v0,v0,zero,v0.t + 40a4: 0000 vmsge.vx v0,v0,zero,v0.t + 40a6: 0000 vmsge.vx v0,v0,zero,v0.t + 40a8: 7845 .2byte 0x7845 + 40aa: 7469 .2byte 0x7469 + 40ac: 6320 vmsge.vx v6,v0,zero,v0.t + 40ae: 3a65646f jal s0,5a454 <__global_pointer$+0x55a4c> + 40b2: 0020 vmsge.vx v0,v0,zero,v0.t + 40b4: 0000 vmsge.vx v0,v0,zero,v0.t + 40b6: 0000 vmsge.vx v0,v0,zero,v0.t + 40b8: 4e49 .2byte 0x4e49 + 40ba: 55525453 .4byte 0x55525453 + 40be: 4f495443 vmsge.vx v8,v20,s2 + 40c2: 204e .2byte 0x204e + 40c4: 4441 vmsge.vx v8,v0,zero,v0.t + 40c6: 5244 .2byte 0x5244 + 40c8: 5345 .2byte 0x5345 + 40ca: 494d2053 .4byte 0x494d2053 + 40ce: 494c4153 .4byte 0x494c4153 + 40d2: 44454e47 .4byte 0x44454e47 + 40d6: 6120 vmsge.vx v2,v0,zero,v0.t + 40d8: 2074 .2byte 0x2074 + 40da: 4350 .2byte 0x4350 + 40dc: 203a .2byte 0x203a + 40de: 0000 vmsge.vx v0,v0,zero,v0.t + 40e0: 4e49 .2byte 0x4e49 + 40e2: 55525453 .4byte 0x55525453 + 40e6: 4f495443 vmsge.vx v8,v20,s2 + 40ea: 204e .2byte 0x204e + 40ec: 4341 vmsge.vx v6,v0,zero,v0.t + 40ee: 53534543 vmsge.vx v10,v21,t1 + 40f2: 4620 vmsge.vx v12,v0,zero,v0.t + 40f4: 5541 vmsge.vx v10,v0,zero,v0.t + 40f6: 544c .2byte 0x544c + 40f8: 6120 vmsge.vx v2,v0,zero,v0.t + 40fa: 2074 .2byte 0x2074 + 40fc: 4350 .2byte 0x4350 + 40fe: 203a .2byte 0x203a + ... + 4108: 4c49 .2byte 0x4c49 + 410a: 454c .2byte 0x454c + 410c: 204c4147 .4byte 0x204c4147 + 4110: 4e49 .2byte 0x4e49 + 4112: 55525453 .4byte 0x55525453 + 4116: 4f495443 vmsge.vx v8,v20,s2 + 411a: 204e .2byte 0x204e + 411c: 7461 vmsge.vx v8,v0,zero,v0.t + 411e: 5020 vmsge.vx v0,v0,zero,v0.t + 4120: 00203a43 vmsge.vx v20,v2,zero,v0.t + 4124: 0000 vmsge.vx v0,v0,zero,v0.t + 4126: 0000 vmsge.vx v0,v0,zero,v0.t + 4128: 4f4c .2byte 0x4f4c + 412a: 4441 vmsge.vx v8,v0,zero,v0.t + 412c: 4120 vmsge.vx v2,v0,zero,v0.t + 412e: 4444 .2byte 0x4444 + 4130: 4552 .2byte 0x4552 + 4132: 4d205353 .4byte 0x4d205353 + 4136: 5349 .2byte 0x5349 + 4138: 4c41 vmsge.vx v24,v0,zero,v0.t + 413a: 4749 .2byte 0x4749 + 413c: 454e .2byte 0x454e + 413e: 2044 .2byte 0x2044 + 4140: 7461 vmsge.vx v8,v0,zero,v0.t + 4142: 5020 vmsge.vx v0,v0,zero,v0.t + 4144: 00203a43 vmsge.vx v20,v2,zero,v0.t + 4148: 4f4c .2byte 0x4f4c + 414a: 4441 vmsge.vx v8,v0,zero,v0.t + 414c: 4120 vmsge.vx v2,v0,zero,v0.t + 414e: 53454343 vmsge.vx v6,v20,a0 + 4152: 41462053 .4byte 0x41462053 + 4156: 4c55 .2byte 0x4c55 + 4158: 2054 .2byte 0x2054 + 415a: 7461 vmsge.vx v8,v0,zero,v0.t + 415c: 5020 vmsge.vx v0,v0,zero,v0.t + 415e: 00203a43 vmsge.vx v20,v2,zero,v0.t + 4162: 0000 vmsge.vx v0,v0,zero,v0.t + 4164: 0000 vmsge.vx v0,v0,zero,v0.t + 4166: 0000 vmsge.vx v0,v0,zero,v0.t + 4168: 524f5453 .4byte 0x524f5453 + 416c: 2045 .2byte 0x2045 + 416e: 4441 vmsge.vx v8,v0,zero,v0.t + 4170: 5244 .2byte 0x5244 + 4172: 5345 .2byte 0x5345 + 4174: 494d2053 .4byte 0x494d2053 + 4178: 494c4153 .4byte 0x494c4153 + 417c: 44454e47 .4byte 0x44454e47 + 4180: 6120 vmsge.vx v2,v0,zero,v0.t + 4182: 2074 .2byte 0x2074 + 4184: 4350 .2byte 0x4350 + 4186: 203a .2byte 0x203a + ... + 4190: 524f5453 .4byte 0x524f5453 + 4194: 2045 .2byte 0x2045 + 4196: 4341 vmsge.vx v6,v0,zero,v0.t + 4198: 53534543 vmsge.vx v10,v21,t1 + 419c: 4620 vmsge.vx v12,v0,zero,v0.t + 419e: 5541 vmsge.vx v10,v0,zero,v0.t + 41a0: 544c .2byte 0x544c + 41a2: 6120 vmsge.vx v2,v0,zero,v0.t + 41a4: 2074 .2byte 0x2074 + 41a6: 4350 .2byte 0x4350 + 41a8: 203a .2byte 0x203a + 41aa: 0000 vmsge.vx v0,v0,zero,v0.t + 41ac: 0000 vmsge.vx v0,v0,zero,v0.t + 41ae: 0000 vmsge.vx v0,v0,zero,v0.t + 41b0: 4345 .2byte 0x4345 + 41b2: 4c41 vmsge.vx v24,v0,zero,v0.t + 41b4: 204c .2byte 0x204c + 41b6: 5246 .2byte 0x5246 + 41b8: 4d204d4f .4byte 0x4d204d4f + 41bc: 4d2d .2byte 0x4d2d + 41be: 2045444f .4byte 0x2045444f + 41c2: 7461 vmsge.vx v8,v0,zero,v0.t + 41c4: 5020 vmsge.vx v0,v0,zero,v0.t + 41c6: 00203a43 vmsge.vx v20,v2,zero,v0.t + 41ca: 0000 vmsge.vx v0,v0,zero,v0.t + 41cc: 0000 vmsge.vx v0,v0,zero,v0.t + 41ce: 0000 vmsge.vx v0,v0,zero,v0.t + 41d0: 4e55 .2byte 0x4e55 + 41d2: 574f4e4b .4byte 0x574f4e4b + 41d6: 204e .2byte 0x204e + 41d8: 5845 .2byte 0x5845 + 41da: 54504543 vmsge.vx v10,v5,zero,v0.t + 41de: 4f49 .2byte 0x4f49 + 41e0: 204e .2byte 0x204e + 41e2: 7461 vmsge.vx v8,v0,zero,v0.t + 41e4: 5020 vmsge.vx v0,v0,zero,v0.t + 41e6: 00203a43 vmsge.vx v20,v2,zero,v0.t + 41ea: 0000 vmsge.vx v0,v0,zero,v0.t + 41ec: 0000 vmsge.vx v0,v0,zero,v0.t + 41ee: 0000 vmsge.vx v0,v0,zero,v0.t + 41f0: 430a .2byte 0x430a + 41f2: 4548 .2byte 0x4548 + 41f4: 4d204b43 vmsge.vx v22,v18,zero,v0.t + 41f8: 53554143 vmsge.vx v2,v21,a0 + 41fc: 2045 .2byte 0x2045 + 41fe: 6e69 .2byte 0x6e69 + 4200: 5220 vmsge.vx v4,v0,zero,v0.t + 4202: 4c54 .2byte 0x4c54 + ... + +Disassembly of section .sdata: + +0000000000004208 <__global_pointer$-0x800>: + 4208: 0101 vmsge.vx v2,v0,zero,v0.t + 420a: 0101 vmsge.vx v2,v0,zero,v0.t + 420c: 0101 vmsge.vx v2,v0,zero,v0.t + 420e: 0101 vmsge.vx v2,v0,zero,v0.t + +Disassembly of section .sbss: + +0000000000004210 : + ... + +0000000000004212 : + ... + +Disassembly of section .tohost: + +0000000010000000 : + ... + +0000000010000040 : + ... + +Disassembly of section .comment: + +0000000000000000 <.comment>: + 0: 3a434347 .4byte 0x3a434347 + 4: 2820 vmsge.vx v16,v0,zero,v0.t + 6: 65653267 .4byte 0x65653267 + a: 6535 .2byte 0x6535 + c: 3334 .2byte 0x3334 + e: 3030 .2byte 0x3030 + 10: 3831 .2byte 0x3831 + 12: 2029 .2byte 0x2029 + 14: 3231 .2byte 0x3231 + 16: 322e .2byte 0x322e + 18: 302e .2byte 0x302e + ... + +Disassembly of section .riscv.attributes: + +0000000000000000 <.riscv.attributes>: + 0: 5e41 vmsge.vx v28,v0,zero,v0.t + 2: 0000 vmsge.vx v0,v0,zero,v0.t + 4: 7200 vmsge.vx v4,v0,zero,v0.t + 6: 7369 .2byte 0x7369 + 8: 01007663 bgeu zero,a6,14 <_start+0x14> + c: 0054 .2byte 0x54 + e: 0000 vmsge.vx v0,v0,zero,v0.t + 10: 1004 .2byte 0x1004 + 12: 7205 .2byte 0x7205 + 14: 3676 .2byte 0x3676 + 16: 6934 .2byte 0x6934 + 18: 7032 .2byte 0x7032 + 1a: 5f31 .2byte 0x5f31 + 1c: 326d .2byte 0x326d + 1e: 3070 .2byte 0x3070 + 20: 7a5f 6369 7273 .byte 0x5f, 0x7a, 0x69, 0x63, 0x73, 0x72 + 26: 7032 .2byte 0x7032 + 28: 5f30 .2byte 0x5f30 + 2a: 6d7a .2byte 0x6d7a + 2c: 756d .2byte 0x756d + 2e: 316c .2byte 0x316c + 30: 3070 .2byte 0x3070 + 32: 7a5f 6576 3233 .byte 0x5f, 0x7a, 0x76, 0x65, 0x33, 0x32 + 38: 3178 .2byte 0x3178 + 3a: 3070 .2byte 0x3070 + 3c: 7a5f 6576 3436 .byte 0x5f, 0x7a, 0x76, 0x65, 0x36, 0x34 + 42: 3178 .2byte 0x3178 + 44: 3070 .2byte 0x3070 + 46: 7a5f 6c76 3233 .byte 0x5f, 0x7a, 0x76, 0x6c, 0x33, 0x32 + 4c: 3162 vmsge.vx v2,v0,zero,v0.t + 4e: 3070 .2byte 0x3070 + 50: 7a5f 6c76 3436 .byte 0x5f, 0x7a, 0x76, 0x6c, 0x36, 0x34 + 56: 3162 vmsge.vx v2,v0,zero,v0.t + 58: 3070 .2byte 0x3070 + 5a: 0800 vmsge.vx v16,v0,zero,v0.t + 5c: 0a01 vmsge.vx v20,v0,zero,v0.t + 5e: 0b Address 0x5e is out of bounds. + diff --git a/src/main/resources/applications_vector/vredsum_data.hex b/src/main/resources/applications_vector/vredsum_data.hex new file mode 100644 index 00000000..82170a50 --- /dev/null +++ b/src/main/resources/applications_vector/vredsum_data.hex @@ -0,0 +1,132 @@ +00de00e3 +009b0027 +00e50021 +003a0028 +007a00ac +004800b6 +000b0046 +00d1001d +00fa00a8 +00420078 +008500b3 +00370073 +005200fd +00db00c4 +0078002c +00b30012 +0006008f +00700078 +001200c0 +00590090 +006a00ee +00320011 +00690099 +00a000ad +ffffc480 +ffffc4c4 +ffffc508 +ffffc418 +ffffc54c +ffffc590 +ffffc5d4 +ffffc618 +ffffc418 +ffffc418 +ffffc418 +ffffc65c +6c637963 +00203a65 +736e690a +74657274 +0000203a +00000000 +74697845 +646f6320 +00203a65 +00000000 +54534e49 +54435552 +204e4f49 +52444441 +20535345 +4153494d +4e47494c +61204445 +43502074 +0000203a +54534e49 +54435552 +204e4f49 +45434341 +46205353 +544c5541 +20746120 +203a4350 +00000000 +00000000 +454c4c49 +204c4147 +54534e49 +54435552 +204e4f49 +50207461 +00203a43 +00000000 +44414f4c +44444120 +53534552 +53494d20 +47494c41 +2044454e +50207461 +00203a43 +44414f4c +43434120 +20535345 +4c554146 +74612054 +3a435020 +00000020 +00000000 +524f5453 +44412045 +53455244 +494d2053 +494c4153 +44454e47 +20746120 +203a4350 +00000000 +00000000 +524f5453 +43412045 +53534543 +55414620 +6120544c +43502074 +0000203a +00000000 +4c414345 +5246204c +4d204d4f +444f4d2d +74612045 +3a435020 +00000020 +00000000 +4e4b4e55 +204e574f +45435845 +4f495450 +7461204e +3a435020 +00000020 +00000000 +4548430a +4d204b43 +53554143 +6e692045 +4c545220 +00000000 +01010101 +01010101 diff --git a/src/main/resources/applications_vector/vredsum_inst.hex b/src/main/resources/applications_vector/vredsum_inst.hex new file mode 100644 index 00000000..01c36359 --- /dev/null +++ b/src/main/resources/applications_vector/vredsum_inst.hex @@ -0,0 +1,603 @@ +00000093 +00000113 +00000193 +00000213 +00000293 +00000313 +00000393 +00000413 +00000493 +00000513 +00000593 +00000613 +00000693 +00000713 +00000793 +00000813 +00000893 +00000913 +00000993 +00000a13 +00000a93 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a/src/main/scala/hajime/common/Instructions.scala +++ b/src/main/scala/hajime/common/Instructions.scala @@ -162,6 +162,8 @@ object VectorInstructions extends ScalarOpConstants with VectorOpConstants { } } def vFunct6Gen(vInst: String): String = { + val VWXUNARY0 = "010000" + val VRXUNARY0 = "010000" vInst match { case "vadd" => "000000" case "vsub" => "000010" @@ -211,18 +213,19 @@ object VectorInstructions extends ScalarOpConstants with VectorOpConstants { case "vmnor" => "011110" case "vmorn" => "011100" case "vmxnor" => "011111" - case "vmv_x_s" => ??? - case "vmv_s_x" => ??? + case "vmv_x_s" => VWXUNARY0 + case "vmv_s_x" => VRXUNARY0 case _ => throw new Exception(s"inst $vInst is invalid") } } - def vArithGen(vInst: String, vsource: VSOURCE.Type, vm: String, vs2Zero: Boolean) = { + def vArithGen(vInst: String, vsource: VSOURCE.Type, vm: String, vs2Zero: Boolean, vs1Zero: Boolean): BitPat = { if (vm == "?" || vm == "0" || vm == "1") { - BitPat("b" + vFunct6Gen(vInst) + vm + (if(vs2Zero) "00000" else "?????") + "?????" + vsourceGen(vsource) + "?????" + "1010111") + BitPat("b" + vFunct6Gen(vInst) + vm + (if (vs2Zero) "00000" else "?????") + (if(vs1Zero) "00000" else "?????") + vsourceGen(vsource) + "?????" + "1010111") } else { throw new Exception(s"vm $vm is invalid") } } + def vArithGen(vInst: String, vsource: VSOURCE.Type, vm: String, vs2Zero: Boolean): BitPat = vArithGen(vInst, vsource, vm, vs2Zero, vs1Zero = false) def vArithGen(vInst: String, vsource: VSOURCE.Type, vm: String): BitPat = vArithGen(vInst, vsource, vm, vs2Zero = false) def vArithGen(vInst: String, vsource: VSOURCE.Type): BitPat = vArithGen(vInst, vsource, vm = "?") def VADD_VV = vArithGen(vInst = "vadd", vsource = VSOURCE.VV) @@ -327,6 +330,11 @@ object VectorInstructions extends ScalarOpConstants with VectorOpConstants { def VMNOR_MM = vArithGen(vInst = "vmnor", vsource = VSOURCE.MVV, vm = "1") def VMORN_MM = vArithGen(vInst = "vmorn", vsource = VSOURCE.MVV, vm = "1") def VMXNOR_MM = vArithGen(vInst = "vmxnor", vsource = VSOURCE.MVV, vm = "1") + + // x[rd] = vs2[0] + def VMV_X_S = vArithGen(vInst = "vmv_x_s", vsource = VSOURCE.MVV, vm = "1", vs2Zero = false, vs1Zero = true) + // vd[0] = x[rs1] + def VMV_S_X = vArithGen(vInst = "vmv_s_x", vsource = VSOURCE.MVX, vm = "1", vs2Zero = true, vs1Zero = false) } object Causes { diff --git a/src/main/scala/hajime/publicmodules/Decoder.scala b/src/main/scala/hajime/publicmodules/Decoder.scala index 14852274..d55d4955 100644 --- a/src/main/scala/hajime/publicmodules/Decoder.scala +++ b/src/main/scala/hajime/publicmodules/Decoder.scala @@ -279,6 +279,8 @@ object RvvDecode extends DecodeConstants { VREDAND_VS -> List(Y, Branch.NONE, Value1.ZERO, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), VREDOR_VS -> List(Y, Branch.NONE, Value1.ZERO, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), VREDXOR_VS -> List(Y, Branch.NONE, Value1.ZERO, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), + VMV_X_S -> List(Y, Branch.NONE, Value1.ZERO, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.VECTOR, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), + VMV_S_X -> List(Y, Branch.NONE, Value1.RS1, Value2.ZERO, ARITHMETIC_FCN.NONE, N, N, WB_SEL.NONE, MEM_FCN.M_NONE, MEM_LEN.B, N, CSR_FCN.N, N, Y), ) } diff --git a/src/main/scala/hajime/vectormodules/VectorCpu.scala b/src/main/scala/hajime/vectormodules/VectorCpu.scala index 5f5aa876..524f6c6c 100644 --- a/src/main/scala/hajime/vectormodules/VectorCpu.scala +++ b/src/main/scala/hajime/vectormodules/VectorCpu.scala @@ -117,7 +117,7 @@ class VectorCpu(implicit params: HajimeCoreParams) extends CpuModule with Scalar val vecInstInEx = !vecExecUnitsReady.reduce(_ && _) // flushならばストールさせる必要はない ID_stall := !ID_flush && ((ID_EX_REG.valid && EX_stall) || rs1_required_but_not_valid || rs2_required_but_not_valid || sysInst_in_pipeline || vectorInstStall - || (vecInstInEx && decoder.io.out.valid && (!decoder.io.out.bits.vector.get || vectorDecoder.io.out.isConfsetInst))) + || (vecInstInEx && decoder.io.out.valid && (!decoder.io.out.bits.vector.get || vectorDecoder.io.out.isConfsetInst || vectorDecoder.io.out.vecPermutation))) io.frontend.resp.ready := cpu_operating && !ID_stall io.frontend.req := Mux(branch_evaluator.io.out.valid && ID_EX_REG.valid, branch_evaluator.io.out, branch_predictor.io.out) @@ -203,8 +203,10 @@ class VectorCpu(implicit params: HajimeCoreParams) extends CpuModule with Scalar vrfReadyTable.io.vdCheck.bits.vm := vectorDecoder.io.out.veuFun.writeAsMask // vmフィールドが1ならばvmを使用する vrfReadyTable.io.vmCheck.valid := decoder.io.out.valid && decoder.io.out.bits.vector.get && !vectorDecoder.io.out.isConfsetInst && !vectorDecoder.io.out.vm - // ベクトル設定命令でなく，かつストア命令で無ければvdへ書き込む - vrfReadyTable.io.invalidateVd := io.frontend.resp.valid && io.frontend.resp.ready && decoder.io.out.valid && decoder.io.out.bits.vector.get && !vectorDecoder.io.out.isConfsetInst && !decoder.io.out.bits.memWrite + // ベクトル設定命令でなく，かつストア命令で無い，ならばvdへ書き込む + // vmv.{x.s, s.x}はチェイニングしないので無視する + vrfReadyTable.io.invalidateVd := io.frontend.resp.valid && io.frontend.resp.ready && decoder.io.out.valid && decoder.io.out.bits.vector.get && + !vectorDecoder.io.out.isConfsetInst && !decoder.io.out.bits.memWrite && !vectorDecoder.io.out.vecPermutation // vecAluExecUnitを使用するなら，空いている方をvalidにする when(ID_flush || ID_stall) { @@ -381,6 +383,7 @@ class VectorCpu(implicit params: HajimeCoreParams) extends CpuModule with Scalar } // placefolder for vec->scalar inst (vcpop.m, vfirst.m, vmv.x.s) + // ベクトル機能ユニットが上書きする？ val exVectorRes = vecCtrlUnit.io.resp.bits.vl bypassingUnit.io.EX.in.bits.rd.bits.index := ID_EX_REG.bits.ctrlSignals.rd_index diff --git a/src/main/scala/hajime/vectormodules/VectorDecoder.scala b/src/main/scala/hajime/vectormodules/VectorDecoder.scala index 722e890d..703c2b85 100644 --- a/src/main/scala/hajime/vectormodules/VectorDecoder.scala +++ b/src/main/scala/hajime/vectormodules/VectorDecoder.scala @@ -3,6 +3,7 @@ package hajime.vectormodules import chisel3._ import circt.stage.ChiselStage import chisel3.util._ +import hajime.common.Functions.lsHasElementEquivalentToUInt import hajime.common.VectorInstructions._ import hajime.common._ import hajime.publicmodules._ @@ -69,7 +70,7 @@ object VDecode extends DecodeConstants with VectorOpConstants { case "vmxnor" => MXNOR case _ => throw new Exception("fuck") } - List(N, AVL_SEL.NONE, VTYPE_SEL.NONE, MOP.NONE, UMOP.NORMAL, Y, veuFunSel, vSource) + List(N, AVL_SEL.NONE, VTYPE_SEL.NONE, MOP.NONE, UMOP.NONE, Y, veuFunSel, vSource) } val table: Array[(BitPat, List[EnumType])] = Array( @@ -209,6 +210,8 @@ object VDecode extends DecodeConstants with VectorOpConstants { VREDAND_VS -> amogus("vredand", VSOURCE.VV), VREDOR_VS -> amogus("vredor", VSOURCE.VV), VREDXOR_VS -> amogus("vredxor", VSOURCE.VV), + VMV_X_S -> List(N, AVL_SEL.NONE, VTYPE_SEL.NONE, MOP.NONE, UMOP.NONE, Y, VEU_FUN.MV_X_S, VSOURCE.VV), + VMV_S_X -> List(N, AVL_SEL.NONE, VTYPE_SEL.NONE, MOP.NONE, UMOP.NONE, Y, VEU_FUN.MV_S_X, VSOURCE.VX), ) } @@ -230,6 +233,7 @@ class VectorDecoderResp extends Bundle with ScalarOpConstants with VectorOpConst def toList: List[UInt] = List(isConfsetInst, avl_sel, vtype_sel, mop, umop, vrfWrite, veuFun, vSource) def useVecAluExec: Bool = !isConfsetInst && (mop === MOP.NONE.asUInt) def useVecLdstExec: Bool = !isConfsetInst && (mop =/= MOP.NONE.asUInt) + def vecPermutation: Bool = Seq(VEU_FUN.MV_X_S, VEU_FUN.MV_S_X).map(_.asUInt).has(veuFun) } class VectorDecoderIO(implicit params: HajimeCoreParams) extends Bundle { diff --git a/src/main/scala/hajime/vectormodules/VectorExecUnit.scala b/src/main/scala/hajime/vectormodules/VectorExecUnit.scala index 945d6373..bcf84d37 100644 --- a/src/main/scala/hajime/vectormodules/VectorExecUnit.scala +++ b/src/main/scala/hajime/vectormodules/VectorExecUnit.scala @@ -239,6 +239,26 @@ class IntegerAluExecUnit(implicit params: HajimeCoreParams) extends VectorExecUn when(instInfoReg.bits.vectorDecode.veuFun.isReductionInst) { io.dataOut.toVRF.bits.index := 0.U } + + // vmv.x.s + when(instInfoReg.bits.vectorDecode.veuFun === VEU_FUN.MV_X_S.asUInt) { + io.dataOut.toVRF.valid := true.B + io.dataOut.toVRF.bits.last := true.B + io.dataOut.toVRF.bits.writeReq := false.B + io.toExWbReg.valid := true.B + io.toExWbReg.bits.vectorExecNum.get.bits := 1.U + io.toExWbReg.bits.vectorExecNum.get.valid := true.B + io.toExWbReg.bits.ctrlSignals.rd_index := instInfoReg.bits.vd + io.toExWbReg.bits.dataSignals.exResult := io.readVrf.resp.vs1Out + } .elsewhen(instInfoReg.bits.vectorDecode.veuFun === VEU_FUN.MV_S_X.asUInt) { + io.dataOut.toVRF.valid := true.B + io.dataOut.toVRF.bits.data := instInfoReg.bits.scalarVal + io.dataOut.toVRF.bits.last := true.B + io.dataOut.toVRF.bits.writeReq := true.B + io.toExWbReg.valid := true.B + io.toExWbReg.bits.vectorExecNum.get.bits := 1.U + io.toExWbReg.bits.vectorExecNum.get.valid := true.B + } } object IntegerAluExecUnit extends App { diff --git a/src/main/scala/hajime/vectormodules/VectorOpConstants.scala b/src/main/scala/hajime/vectormodules/VectorOpConstants.scala index 893f5dc6..c3f6bdf4 100644 --- a/src/main/scala/hajime/vectormodules/VectorOpConstants.scala +++ b/src/main/scala/hajime/vectormodules/VectorOpConstants.scala @@ -28,7 +28,8 @@ trait VectorOpConstants { val NONE, ADD, SUB, RSUB, ADC, MADC, SBC, MSBC, SEQ, SNE, SLTU, SLT, SLEU, SLE, SGTU, SGT, MINU, MIN, MAXU, MAX, MERGE, MV, AND, OR, XOR, MAND, MNAND, MANDN, MXOR, MOR, MNOR, MORN, MXNOR, MUL, MULH, MULHU, MULHSU, MACC, NMSAC, MADD, NMSUB, - REDSUM, REDMAXU, REDMAX, REDMINU, REDMIN, REDAND, REDOR, REDXOR = Value + REDSUM, REDMAXU, REDMAX, REDMINU, REDMIN, REDAND, REDOR, REDXOR, + MV_X_S, MV_S_X = Value val compMaskList = SEQ :: SNE :: SLTU :: SLT :: SLEU :: SLE :: SGTU :: SGT :: Nil val carryMaskList = MADC :: MSBC :: Nil val ignoreMaskList = ADC :: MADC :: SBC :: MSBC :: MERGE :: Nil diff --git a/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala b/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala index 1e0761d8..ff6b5892 100644 --- a/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala +++ b/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala @@ -141,6 +141,7 @@ class Zve64xAppTestForVecCpu extends AnyFlatSpec with ChiselScalatestTester { "vmand", "vmor", "vmxor", "vmul", "vmulh", "vmulhu", "vmulhsu", "vmacc", "vnmsac", "vmadd", "vnmsub", + "vredsum", ) val applicationTest = Seq( "vector_median" From cab99b327535b71165ce2aedd609aef20a81256f Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Tue, 14 Nov 2023 17:07:35 +0900 Subject: [PATCH 13/14] aaaa --- .../hajime/vectormodules/VectorExecUnit.scala | 39 ++++++++++--------- 1 file changed, 21 insertions(+), 18 deletions(-) diff --git a/src/main/scala/hajime/vectormodules/VectorExecUnit.scala b/src/main/scala/hajime/vectormodules/VectorExecUnit.scala index bcf84d37..cc53ea4f 100644 --- a/src/main/scala/hajime/vectormodules/VectorExecUnit.scala +++ b/src/main/scala/hajime/vectormodules/VectorExecUnit.scala @@ -240,24 +240,27 @@ class IntegerAluExecUnit(implicit params: HajimeCoreParams) extends VectorExecUn io.dataOut.toVRF.bits.index := 0.U } - // vmv.x.s - when(instInfoReg.bits.vectorDecode.veuFun === VEU_FUN.MV_X_S.asUInt) { - io.dataOut.toVRF.valid := true.B - io.dataOut.toVRF.bits.last := true.B - io.dataOut.toVRF.bits.writeReq := false.B - io.toExWbReg.valid := true.B - io.toExWbReg.bits.vectorExecNum.get.bits := 1.U - io.toExWbReg.bits.vectorExecNum.get.valid := true.B - io.toExWbReg.bits.ctrlSignals.rd_index := instInfoReg.bits.vd - io.toExWbReg.bits.dataSignals.exResult := io.readVrf.resp.vs1Out - } .elsewhen(instInfoReg.bits.vectorDecode.veuFun === VEU_FUN.MV_S_X.asUInt) { - io.dataOut.toVRF.valid := true.B - io.dataOut.toVRF.bits.data := instInfoReg.bits.scalarVal - io.dataOut.toVRF.bits.last := true.B - io.dataOut.toVRF.bits.writeReq := true.B - io.toExWbReg.valid := true.B - io.toExWbReg.bits.vectorExecNum.get.bits := 1.U - io.toExWbReg.bits.vectorExecNum.get.valid := true.B + when(instInfoReg.valid) { + when(instInfoReg.bits.vectorDecode.veuFun === VEU_FUN.MV_X_S.asUInt) { + // vmv.x.s + io.dataOut.toVRF.valid := true.B + io.dataOut.toVRF.bits.last := true.B + io.dataOut.toVRF.bits.writeReq := false.B + io.toExWbReg.valid := true.B + io.toExWbReg.bits.vectorExecNum.get.bits := 1.U + io.toExWbReg.bits.vectorExecNum.get.valid := true.B + io.toExWbReg.bits.ctrlSignals.rd_index := instInfoReg.bits.vd + io.toExWbReg.bits.dataSignals.exResult := io.readVrf.resp.vs1Out + }.elsewhen(instInfoReg.bits.vectorDecode.veuFun === VEU_FUN.MV_S_X.asUInt) { + // vmv.s.x + io.dataOut.toVRF.valid := true.B + io.dataOut.toVRF.bits.data := instInfoReg.bits.scalarVal + io.dataOut.toVRF.bits.last := true.B + io.dataOut.toVRF.bits.writeReq := true.B + io.toExWbReg.valid := true.B + io.toExWbReg.bits.vectorExecNum.get.bits := 1.U + io.toExWbReg.bits.vectorExecNum.get.valid := true.B + } } } From 0508386eb15560d9e7d30660ac0e3dba20bd4e60 Mon Sep 17 00:00:00 2001 From: HidetaroTanaka Date: Tue, 14 Nov 2023 17:33:22 +0900 Subject: [PATCH 14/14] fimally --- src/main/scala/hajime/vectormodules/VectorCpu.scala | 3 +-- src/main/scala/hajime/vectormodules/VectorExecUnit.scala | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/main/scala/hajime/vectormodules/VectorCpu.scala b/src/main/scala/hajime/vectormodules/VectorCpu.scala index 524f6c6c..ad9d2ca0 100644 --- a/src/main/scala/hajime/vectormodules/VectorCpu.scala +++ b/src/main/scala/hajime/vectormodules/VectorCpu.scala @@ -383,8 +383,7 @@ class VectorCpu(implicit params: HajimeCoreParams) extends CpuModule with Scalar } // placefolder for vec->scalar inst (vcpop.m, vfirst.m, vmv.x.s) - // ベクトル機能ユニットが上書きする？ - val exVectorRes = vecCtrlUnit.io.resp.bits.vl + val exVectorRes = Mux(ID_EX_REG.bits.vectorCtrlSignals.get.vecPermutation, vecAluExecUnit(0).io.toExWbReg.bits.dataSignals.exResult, vecCtrlUnit.io.resp.bits.vl) bypassingUnit.io.EX.in.bits.rd.bits.index := ID_EX_REG.bits.ctrlSignals.rd_index bypassingUnit.io.EX.in.bits.rd.bits.value := MuxLookup(ID_EX_REG.bits.ctrlSignals.decode.writeback_selector, 0.U)(Seq( diff --git a/src/main/scala/hajime/vectormodules/VectorExecUnit.scala b/src/main/scala/hajime/vectormodules/VectorExecUnit.scala index cc53ea4f..9f6c5144 100644 --- a/src/main/scala/hajime/vectormodules/VectorExecUnit.scala +++ b/src/main/scala/hajime/vectormodules/VectorExecUnit.scala @@ -250,7 +250,7 @@ class IntegerAluExecUnit(implicit params: HajimeCoreParams) extends VectorExecUn io.toExWbReg.bits.vectorExecNum.get.bits := 1.U io.toExWbReg.bits.vectorExecNum.get.valid := true.B io.toExWbReg.bits.ctrlSignals.rd_index := instInfoReg.bits.vd - io.toExWbReg.bits.dataSignals.exResult := io.readVrf.resp.vs1Out + io.toExWbReg.bits.dataSignals.exResult := io.readVrf.resp.vs2Out }.elsewhen(instInfoReg.bits.vectorDecode.veuFun === VEU_FUN.MV_S_X.asUInt) { // vmv.s.x io.dataOut.toVRF.valid := true.B