From 82c983bcfe66198ae8b27a497b01ab75c7e7e107 Mon Sep 17 00:00:00 2001 From: IngHK Date: Sun, 10 Mar 2024 08:48:21 +0100 Subject: [PATCH] small improvements compile errors --- src/class/cdc/cdc_host.c | 20 ++++----- src/class/cdc/serial/ch34x.h | 4 +- src/class/cdc/serial/cp210x.h | 74 ++++++++++++++++----------------- src/class/cdc/serial/ftdi_sio.h | 58 +++++++++++++------------- src/class/cdc/serial/pl2303.h | 6 +-- 5 files changed, 81 insertions(+), 81 deletions(-) diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 69b630ee5f..7c09d77eb8 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -1171,9 +1171,9 @@ static bool ftdi_change_speed(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_c static bool ftdi_set_data_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->requested_line_coding.data_bits >= 7 && p_cdc->requested_line_coding.data_bits <= 8, 0); uint16_t value = (uint16_t) ( - ((uint32_t) p_cdc->requested_line_coding.data_bits & 0xfu) | // data bit quantity is stored in bits 0-3 - ((uint32_t) p_cdc->requested_line_coding.parity & 0x7u) << 8 | // parity is stored in bits 8-10, same coding - ((uint32_t) p_cdc->requested_line_coding.stop_bits & 0x3u) << 11 ); // stop bits quantity is stored in bits 11-12, same coding + (p_cdc->requested_line_coding.data_bits & 0xfUL) | // data bit quantity is stored in bits 0-3 + (p_cdc->requested_line_coding.parity & 0x7UL) << 8 | // parity is stored in bits 8-10, same coding + (p_cdc->requested_line_coding.stop_bits & 0x3UL) << 11 ); // stop bits quantity is stored in bits 11-12, same coding // not each FTDI supports 1.5 stop bits return ftdi_set_request(p_cdc, FTDI_SIO_SET_DATA_REQUEST, FTDI_SIO_SET_DATA_REQUEST_TYPE, @@ -1181,8 +1181,8 @@ static bool ftdi_set_data_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t comple } static inline bool ftdi_update_mctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint16_t value = (uint16_t) ((p_cdc->requested_line_state.dtr ? (uint32_t) FTDI_SIO_SET_DTR_HIGH : (uint32_t) FTDI_SIO_SET_DTR_LOW) | - (p_cdc->requested_line_state.rts ? (uint32_t) FTDI_SIO_SET_RTS_HIGH : (uint32_t) FTDI_SIO_SET_RTS_LOW)); + uint16_t value = (uint16_t) ((p_cdc->requested_line_state.dtr ? FTDI_SIO_SET_DTR_HIGH : FTDI_SIO_SET_DTR_LOW) | + (p_cdc->requested_line_state.rts ? FTDI_SIO_SET_RTS_HIGH : FTDI_SIO_SET_RTS_LOW)); return ftdi_set_request(p_cdc, FTDI_SIO_SET_MODEM_CTRL_REQUEST, FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE, value, p_cdc->ftdi.channel, complete_cb, user_data); @@ -1708,9 +1708,9 @@ static bool cp210x_set_baudrate_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t static bool cp210x_set_line_ctl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->requested_line_coding.data_bits >= 5 && p_cdc->requested_line_coding.data_bits <= 9, 0); uint16_t lcr = (uint16_t) ( - ((uint32_t) p_cdc->requested_line_coding.data_bits & 0xfu) << 8 | // data bit quantity is stored in bits 8-11 - ((uint32_t) p_cdc->requested_line_coding.parity & 0xfu) << 4 | // parity is stored in bits 4-7, same coding - ((uint32_t) p_cdc->requested_line_coding.stop_bits & 0xfu)); // parity is stored in bits 0-3, same coding + (p_cdc->requested_line_coding.data_bits & 0xfUL) << 8 | // data bit quantity is stored in bits 8-11 + (p_cdc->requested_line_coding.parity & 0xfUL) << 4 | // parity is stored in bits 4-7, same coding + (p_cdc->requested_line_coding.stop_bits & 0xfUL)); // parity is stored in bits 0-3, same coding return cp210x_set_request(p_cdc, CP210X_SET_LINE_CTL, lcr, NULL, 0, complete_cb, user_data); } @@ -1718,8 +1718,8 @@ static bool cp210x_set_line_ctl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete static inline bool cp210x_set_mhs(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // CP210x has the same bit coding return cp210x_set_request(p_cdc, CP210X_SET_MHS, - (uint16_t) ((uint32_t) CP210X_CONTROL_WRITE_DTR | - (uint32_t) CP210X_CONTROL_WRITE_RTS | p_cdc->requested_line_state.all), + (uint16_t) (CP210X_CONTROL_WRITE_DTR | CP210X_CONTROL_WRITE_RTS | + p_cdc->requested_line_state.all), NULL, 0, complete_cb, user_data); } diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h index 78c659a0a0..7d91f01fe2 100644 --- a/src/class/cdc/serial/ch34x.h +++ b/src/class/cdc/serial/ch34x.h @@ -64,8 +64,8 @@ #define CH32X_REG16_LCR2_LCR TU_U16(CH34X_REG_LCR2, CH34X_REG_LCR) // modem control bits -#define CH34X_BIT_RTS (1u << 6) -#define CH34X_BIT_DTR (1u << 5) +#define CH34X_BIT_RTS (1 << 6) +#define CH34X_BIT_DTR (1 << 5) // line control bits #define CH34X_LCR_ENABLE_RX 0x80 diff --git a/src/class/cdc/serial/cp210x.h b/src/class/cdc/serial/cp210x.h index 232c2d4b41..ac9c273307 100644 --- a/src/class/cdc/serial/cp210x.h +++ b/src/class/cdc/serial/cp210x.h @@ -61,55 +61,55 @@ #define CP210X_VENDOR_SPECIFIC 0xFF // GPIO, Recipient must be Device // SILABSER_IFC_ENABLE_REQUEST_CODE -#define CP210X_UART_ENABLE 0x0001u -#define CP210X_UART_DISABLE 0x0000u +#define CP210X_UART_ENABLE 0x0001 +#define CP210X_UART_DISABLE 0x0000 // SILABSER_SET_BAUDDIV_REQUEST_CODE -#define CP210X_BAUD_RATE_GEN_FREQ 0x384000u +#define CP210X_BAUD_RATE_GEN_FREQ 0x384000 // SILABSER_SET_LINE_CTL_REQUEST_CODE -#define CP210X_BITS_DATA_MASK 0x0f00u -#define CP210X_BITS_DATA_5 0x0500u -#define CP210X_BITS_DATA_6 0x0600u -#define CP210X_BITS_DATA_7 0x0700u -#define CP210X_BITS_DATA_8 0x0800u -#define CP210X_BITS_DATA_9 0x0900u +#define CP210X_BITS_DATA_MASK 0x0f00 +#define CP210X_BITS_DATA_5 0x0500 +#define CP210X_BITS_DATA_6 0x0600 +#define CP210X_BITS_DATA_7 0x0700 +#define CP210X_BITS_DATA_8 0x0800 +#define CP210X_BITS_DATA_9 0x0900 -#define CP210X_BITS_PARITY_MASK 0x00f0u -#define CP210X_BITS_PARITY_NONE 0x0000u -#define CP210X_BITS_PARITY_ODD 0x0010u -#define CP210X_BITS_PARITY_EVEN 0x0020u -#define CP210X_BITS_PARITY_MARK 0x0030u -#define CP210X_BITS_PARITY_SPACE 0x0040u +#define CP210X_BITS_PARITY_MASK 0x00f0 +#define CP210X_BITS_PARITY_NONE 0x0000 +#define CP210X_BITS_PARITY_ODD 0x0010 +#define CP210X_BITS_PARITY_EVEN 0x0020 +#define CP210X_BITS_PARITY_MARK 0x0030 +#define CP210X_BITS_PARITY_SPACE 0x0040 -#define CP210X_BITS_STOP_MASK 0x000fu -#define CP210X_BITS_STOP_1 0x0000u -#define CP210X_BITS_STOP_1_5 0x0001u -#define CP210X_BITS_STOP_2 0x0002u +#define CP210X_BITS_STOP_MASK 0x000f +#define CP210X_BITS_STOP_1 0x0000 +#define CP210X_BITS_STOP_1_5 0x0001 +#define CP210X_BITS_STOP_2 0x0002 // SILABSER_SET_BREAK_REQUEST_CODE -#define CP210X_BREAK_ON 0x0001u -#define CP210X_BREAK_OFF 0x0000u +#define CP210X_BREAK_ON 0x0001 +#define CP210X_BREAK_OFF 0x0000 // SILABSER_SET_MHS_REQUEST_CODE -#define CP210X_MCR_DTR 0x0001u -#define CP210X_MCR_RTS 0x0002u -#define CP210X_MCR_ALL 0x0003u -#define CP210X_MSR_CTS 0x0010u -#define CP210X_MSR_DSR 0x0020u -#define CP210X_MSR_RING 0x0040u -#define CP210X_MSR_DCD 0x0080u -#define CP210X_MSR_ALL 0x00F0u +#define CP210X_MCR_DTR 0x0001 +#define CP210X_MCR_RTS 0x0002 +#define CP210X_MCR_ALL 0x0003 +#define CP210X_MSR_CTS 0x0010 +#define CP210X_MSR_DSR 0x0020 +#define CP210X_MSR_RING 0x0040 +#define CP210X_MSR_DCD 0x0080 +#define CP210X_MSR_ALL 0x00F0 -#define CP210X_CONTROL_WRITE_DTR 0x0100u -#define CP210X_CONTROL_WRITE_RTS 0x0200u +#define CP210X_CONTROL_WRITE_DTR 0x0100UL +#define CP210X_CONTROL_WRITE_RTS 0x0200UL -#define CP210X_LSR_BREAK 0x0001u -#define CP210X_LSR_FRAMING_ERROR 0x0002u -#define CP210X_LSR_HW_OVERRUN 0x0004u -#define CP210X_LSR_QUEUE_OVERRUN 0x0008u -#define CP210X_LSR_PARITY_ERROR 0x0010u -#define CP210X_LSR_ALL 0x001Fu +#define CP210X_LSR_BREAK 0x0001 +#define CP210X_LSR_FRAMING_ERROR 0x0002 +#define CP210X_LSR_HW_OVERRUN 0x0004 +#define CP210X_LSR_QUEUE_OVERRUN 0x0008 +#define CP210X_LSR_PARITY_ERROR 0x0010 +#define CP210X_LSR_ALL 0x001F // supported baudrates // reference: datasheets and AN205 "CP210x Baud Rate Support" diff --git a/src/class/cdc/serial/ftdi_sio.h b/src/class/cdc/serial/ftdi_sio.h index 001d5ab499..9f757c7406 100644 --- a/src/class/cdc/serial/ftdi_sio.h +++ b/src/class/cdc/serial/ftdi_sio.h @@ -82,34 +82,34 @@ enum ftdi_sio_baudrate { // FTDI_SIO_SET_DATA #define FTDI_SIO_SET_DATA_REQUEST FTDI_SIO_SET_DATA #define FTDI_SIO_SET_DATA_REQUEST_TYPE 0x40 -#define FTDI_SIO_SET_DATA_PARITY_NONE (0x0u << 8) -#define FTDI_SIO_SET_DATA_PARITY_ODD (0x1u << 8) -#define FTDI_SIO_SET_DATA_PARITY_EVEN (0x2u << 8) -#define FTDI_SIO_SET_DATA_PARITY_MARK (0x3u << 8) -#define FTDI_SIO_SET_DATA_PARITY_SPACE (0x4u << 8) -#define FTDI_SIO_SET_DATA_STOP_BITS_1 (0x0u << 11) // same coding as ACM -#define FTDI_SIO_SET_DATA_STOP_BITS_15 (0x1u << 11) // 1.5 not supported, for future use? -#define FTDI_SIO_SET_DATA_STOP_BITS_2 (0x2u << 11) -#define FTDI_SIO_SET_BREAK (0x1u << 14) +#define FTDI_SIO_SET_DATA_PARITY_NONE (0x0 << 8) +#define FTDI_SIO_SET_DATA_PARITY_ODD (0x1 << 8) +#define FTDI_SIO_SET_DATA_PARITY_EVEN (0x2 << 8) +#define FTDI_SIO_SET_DATA_PARITY_MARK (0x3 << 8) +#define FTDI_SIO_SET_DATA_PARITY_SPACE (0x4 << 8) +#define FTDI_SIO_SET_DATA_STOP_BITS_1 (0x0 << 11) // same coding as ACM +#define FTDI_SIO_SET_DATA_STOP_BITS_15 (0x1 << 11) // 1.5 not supported, for future use? +#define FTDI_SIO_SET_DATA_STOP_BITS_2 (0x2 << 11) +#define FTDI_SIO_SET_BREAK (0x1 << 14) // FTDI_SIO_MODEM_CTRL #define FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE 0x40 #define FTDI_SIO_SET_MODEM_CTRL_REQUEST FTDI_SIO_MODEM_CTRL -#define FTDI_SIO_SET_DTR_MASK 0x1u -#define FTDI_SIO_SET_DTR_HIGH ((FTDI_SIO_SET_DTR_MASK << 8) | 1u) -#define FTDI_SIO_SET_DTR_LOW ((FTDI_SIO_SET_DTR_MASK << 8) | 0u) -#define FTDI_SIO_SET_RTS_MASK 0x2u -#define FTDI_SIO_SET_RTS_HIGH ((FTDI_SIO_SET_RTS_MASK << 8) | 2u) -#define FTDI_SIO_SET_RTS_LOW ((FTDI_SIO_SET_RTS_MASK << 8) | 0u) +#define FTDI_SIO_SET_DTR_MASK 0x1UL +#define FTDI_SIO_SET_DTR_HIGH ((FTDI_SIO_SET_DTR_MASK << 8) | 1UL) +#define FTDI_SIO_SET_DTR_LOW ((FTDI_SIO_SET_DTR_MASK << 8) | 0UL) +#define FTDI_SIO_SET_RTS_MASK 0x2UL +#define FTDI_SIO_SET_RTS_HIGH ((FTDI_SIO_SET_RTS_MASK << 8) | 2UL) +#define FTDI_SIO_SET_RTS_LOW ((FTDI_SIO_SET_RTS_MASK << 8) | 0UL) // FTDI_SIO_SET_FLOW_CTRL #define FTDI_SIO_SET_FLOW_CTRL_REQUEST_TYPE 0x40 #define FTDI_SIO_SET_FLOW_CTRL_REQUEST FTDI_SIO_SET_FLOW_CTRL #define FTDI_SIO_DISABLE_FLOW_CTRL 0x0 -#define FTDI_SIO_RTS_CTS_HS (0x1u << 8) -#define FTDI_SIO_DTR_DSR_HS (0x2u << 8) -#define FTDI_SIO_XON_XOFF_HS (0x4u << 8) +#define FTDI_SIO_RTS_CTS_HS (0x1 << 8) +#define FTDI_SIO_DTR_DSR_HS (0x2 << 8) +#define FTDI_SIO_XON_XOFF_HS (0x4 << 8) // FTDI_SIO_GET_LATENCY_TIMER #define FTDI_SIO_GET_LATENCY_TIMER_REQUEST FTDI_SIO_GET_LATENCY_TIMER @@ -150,19 +150,19 @@ enum ftdi_sio_baudrate { #define FTDI_FTX_CBUS_MUX_GPIO 0x8 #define FTDI_FT232R_CBUS_MUX_GPIO 0xa -#define FTDI_RS0_CTS (1u << 4) -#define FTDI_RS0_DSR (1u << 5) -#define FTDI_RS0_RI (1u << 6) -#define FTDI_RS0_RLSD (1u << 7) +#define FTDI_RS0_CTS (1 << 4) +#define FTDI_RS0_DSR (1 << 5) +#define FTDI_RS0_RI (1 << 6) +#define FTDI_RS0_RLSD (1 << 7) #define FTDI_RS_DR 1 -#define FTDI_RS_OE (1u << 1) -#define FTDI_RS_PE (1u << 2) -#define FTDI_RS_FE (1u << 3) -#define FTDI_RS_BI (1u << 4) -#define FTDI_RS_THRE (1u << 5) -#define FTDI_RS_TEMT (1u << 6) -#define FTDI_RS_FIFO (1u << 7) +#define FTDI_RS_OE (1 << 1) +#define FTDI_RS_PE (1 << 2) +#define FTDI_RS_FE (1 << 3) +#define FTDI_RS_BI (1 << 4) +#define FTDI_RS_THRE (1 << 5) +#define FTDI_RS_TEMT (1 << 6) +#define FTDI_RS_FIFO (1 << 7) // chip types and names enum ftdi_chip_type { diff --git a/src/class/cdc/serial/pl2303.h b/src/class/cdc/serial/pl2303.h index e35e2c45d0..d69bdbfae0 100644 --- a/src/class/cdc/serial/pl2303.h +++ b/src/class/cdc/serial/pl2303.h @@ -52,8 +52,8 @@ #define PL2303_BREAK_REQUEST_TYPE 0x21 // class request host to device interface #define PL2303_BREAK_REQUEST 0x23 // dec 35 -#define PL2303_BREAK_ON 0xffffu -#define PL2303_BREAK_OFF 0x0000u +#define PL2303_BREAK_ON 0xffff +#define PL2303_BREAK_OFF 0x0000 #define PL2303_GET_LINE_REQUEST_TYPE 0xa1 // class request device to host interface #define PL2303_GET_LINE_REQUEST 0x21 // dec 33 @@ -83,7 +83,7 @@ #define PL2303_CLEAR_HALT_REQUEST_TYPE 0x02 // standard request host to device endpoint // registers via vendor read/write requests -#define PL2303_READ_TYPE_HX_STATUS 0x8080u +#define PL2303_READ_TYPE_HX_STATUS 0x8080 #define PL2303_HXN_RESET_REG 0x07 #define PL2303_HXN_RESET_UPSTREAM_PIPE 0x02