calculation of config_link_rate is off for VC709

[hmaarrfk]

It seems that there is a typo here

riffa/fpga/xilinx/vc709/riffa_wrapper_vc709.v

Line 286 in 4e9d3c8

assign config_link_rate = CFG_CURRENT_SPEED[2]? 2'b11 : CFG_CURRENT_SPEED[2] ? 2'b10 : 2'b01;

I think it should be

    assign config_link_rate = CFG_CURRENT_SPEED[2]? 2'b11 : CFG_CURRENT_SPEED[1] ? 2'b10 : 2'b01;

According to the Ultrascale datasheet

Current Link Speed
This signal outputs the current link speed from Link Status
register bits 1 down to 0. This field indicates the negotiated
Link speed of the given PCI Express Link.
• 001b: 2.5 GT/s PCI Express Link
• 010b: 5.0 GT/s PCI Express Link
• 100b: 8.0 GT/s PCI Express Link

I think you are trying to change the 1 hot bits to a 2 bit unsigned number right?