From 535c8423ad239a1c42c27401d2b39b0e04df11e8 Mon Sep 17 00:00:00 2001 From: Oleksandr Shamray Date: Wed, 17 Jul 2024 16:48:28 +0000 Subject: [PATCH] hw-mgmt: patches: kernel 5.10/6.1: Fix N51XX platform patch Reduce (remove unused) regio attributes to not exeed maximum (96) Bug: 31993608 Signed-off-by: Oleksandr Shamray --- ...x-Downstream-Introduce-support-of-Nv.patch | 194 +++++++----------- ...x-Downstream-Add-dedicated-match-for.patch | 12 +- 2 files changed, 84 insertions(+), 122 deletions(-) diff --git a/recipes-kernel/linux/linux-6.1/9004-platform-mellanox-Downstream-Introduce-support-of-Nv.patch b/recipes-kernel/linux/linux-6.1/9004-platform-mellanox-Downstream-Introduce-support-of-Nv.patch index f765c378d..8ea2b8e6f 100644 --- a/recipes-kernel/linux/linux-6.1/9004-platform-mellanox-Downstream-Introduce-support-of-Nv.patch +++ b/recipes-kernel/linux/linux-6.1/9004-platform-mellanox-Downstream-Introduce-support-of-Nv.patch @@ -1,7 +1,7 @@ -From eb52869c8db74dc86cd4f9cd32c6e7ec6c4c4494 Mon Sep 17 00:00:00 2001 +From 39295cbf93c98d2da43b45ffbc0afefd60e6f0ed Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Thu, 4 Jan 2024 07:40:04 +0000 -Subject: [PATCH 08/20] platform: mellanox: Downstream: Introduce support of +Subject: [PATCH 03/15] platform: mellanox: Downstream: Introduce support of Nvidia next genration L1 tray switch Add support for new L1 tray switch node providing L1 connectivity for @@ -16,11 +16,11 @@ of the all required platform driver. Signed-off-by: Vadim Pasternak --- - drivers/platform/mellanox/mlx-platform.c | 1195 ++++++++++++++++++++-- - 1 file changed, 1085 insertions(+), 110 deletions(-) + drivers/platform/mellanox/mlx-platform.c | 1159 +++++++++++++++++++--- + 1 file changed, 1046 insertions(+), 113 deletions(-) diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index 19a98f4de83b..24e138611de2 100644 +index 02470474846e..3197f2f9b010 100644 --- a/drivers/platform/mellanox/mlx-platform.c +++ b/drivers/platform/mellanox/mlx-platform.c @@ -53,6 +53,7 @@ @@ -220,43 +220,39 @@ index 19a98f4de83b..24e138611de2 100644 { .label = "erot1_recovery", .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, -@@ -6321,151 +6442,789 @@ static struct mlxreg_core_platform_data mlxplat_smart_switch_regs_io_data = { +@@ -6315,152 +6436,748 @@ static struct mlxreg_core_platform_data mlxplat_smart_switch_regs_io_data = { .counter = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_regs_io_data), }; -/* Platform FAN default */ -static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = { -+/* Platform register access for l1_scale_out systems families data */ -+static struct mlxreg_core_data mlxplat_mlxcpld_l1_scale_out_regs_io_data[] = { - { +- { - .label = "pwm1", - .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, -+ .label = "cpld1_version", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, - }, +- }, ++/* Platform register access for l1_scale_out systems families data */ ++static struct mlxreg_core_data mlxplat_mlxcpld_l1_scale_out_regs_io_data[] = { { - .label = "pwm2", - .reg = MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, -+ .label = "cpld2_version", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, ++ .label = "cpld1_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, }, { - .label = "pwm3", - .reg = MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, -+ .label = "cpld3_version", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, ++ .label = "cpld2_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, }, { - .label = "pwm4", - .reg = MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, -+ .label = "cpld4_version", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, ++ .label = "cpld3_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, }, @@ -268,11 +264,10 @@ index 19a98f4de83b..24e138611de2 100644 - .bit = BIT(0), - .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, - -+ .label = "cpld1_pn", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, -+ .bit = GENMASK(15, 0), ++ .label = "cpld4_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, ++ .bit = GENMASK(7, 0), + .mode = 0444, -+ .regnum = 2, }, { - .label = "tacho2", @@ -281,8 +276,8 @@ index 19a98f4de83b..24e138611de2 100644 - .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, - .bit = BIT(1), - .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "cpld2_pn", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, ++ .label = "cpld1_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, + .bit = GENMASK(15, 0), + .mode = 0444, + .regnum = 2, @@ -294,8 +289,8 @@ index 19a98f4de83b..24e138611de2 100644 - .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, - .bit = BIT(2), - .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "cpld3_pn", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, ++ .label = "cpld2_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, + .bit = GENMASK(15, 0), + .mode = 0444, + .regnum = 2, @@ -307,8 +302,8 @@ index 19a98f4de83b..24e138611de2 100644 - .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, - .bit = BIT(3), - .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "cpld4_pn", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, ++ .label = "cpld3_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, + .bit = GENMASK(15, 0), + .mode = 0444, + .regnum = 2, @@ -320,10 +315,11 @@ index 19a98f4de83b..24e138611de2 100644 - .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, - .bit = BIT(4), - .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "cpld1_version_min", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, -+ .bit = GENMASK(7, 0), ++ .label = "cpld4_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, ++ .bit = GENMASK(15, 0), + .mode = 0444, ++ .regnum = 2, }, { - .label = "tacho6", @@ -332,8 +328,8 @@ index 19a98f4de83b..24e138611de2 100644 - .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, - .bit = BIT(5), - .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "cpld2_version_min", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, ++ .label = "cpld1_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, }, @@ -344,8 +340,8 @@ index 19a98f4de83b..24e138611de2 100644 - .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, - .bit = BIT(6), - .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "cpld3_version_min", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, ++ .label = "cpld2_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, }, @@ -356,8 +352,8 @@ index 19a98f4de83b..24e138611de2 100644 - .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, - .bit = BIT(7), - .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "cpld4_version_min", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, ++ .label = "cpld3_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, }, @@ -368,10 +364,9 @@ index 19a98f4de83b..24e138611de2 100644 - .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, - .bit = BIT(0), - .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "bios_status", -+ .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, -+ .mask = GENMASK(3, 1), -+ .bit = 3, ++ .label = "cpld4_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, ++ .bit = GENMASK(7, 0), + .mode = 0444, }, { @@ -381,9 +376,10 @@ index 19a98f4de83b..24e138611de2 100644 - .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, - .bit = BIT(1), - .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "bios_start_retry", ++ .label = "bios_status", + .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mask = GENMASK(3, 1), ++ .bit = 3, + .mode = 0444, }, { @@ -393,9 +389,9 @@ index 19a98f4de83b..24e138611de2 100644 - .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, - .bit = BIT(2), - .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "bios_active_image", ++ .label = "bios_start_retry", + .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0444, }, { @@ -405,9 +401,9 @@ index 19a98f4de83b..24e138611de2 100644 - .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, - .bit = BIT(3), - .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "bios_auth_fail", ++ .label = "bios_active_image", + .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, }, { @@ -416,10 +412,10 @@ index 19a98f4de83b..24e138611de2 100644 - .mask = GENMASK(7, 0), - .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, - .bit = BIT(4), -+ .label = "bios_upgrade_fail", -+ .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0444, ++ .label = "pwr_converter_prog_en", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0644, }, { - .label = "tacho14", @@ -427,18 +423,18 @@ index 19a98f4de83b..24e138611de2 100644 - .mask = GENMASK(7, 0), - .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, - .bit = BIT(5), -+ .label = "pwr_converter_prog_en", ++ .label = "cpu_mctp_ready", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0644, }, { - .label = "conf", - .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET, -+ .label = "cpu_mctp_ready", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0644, ++ .label = "cpu_shutdown_req", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, }, -}; - @@ -452,12 +448,7 @@ index 19a98f4de83b..24e138611de2 100644 -static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_data[] = { { - .label = "pwm1", -+ .label = "cpu_shutdown_req", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0444, -+ }, -+ { +- .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, + .label = "vpd_wp", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), @@ -670,7 +661,7 @@ index 19a98f4de83b..24e138611de2 100644 + .mode = 0444, + }, + { -+ .label = "reset_long_pwr_pb", ++ .label = "reset_leak_con", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, @@ -792,30 +783,6 @@ index 19a98f4de83b..24e138611de2 100644 + .mode = 0644, + }, + { -+ .label = "dbg1", -+ .reg = MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0644, -+ }, -+ { -+ .label = "dbg2", -+ .reg = MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0644, -+ }, -+ { -+ .label = "dbg3", -+ .reg = MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0644, -+ }, -+ { -+ .label = "dbg4", -+ .reg = MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0644, -+ }, -+ { + .label = "asic_health", + .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, + .mask = MLXPLAT_CPLD_ASIC_MASK, @@ -884,12 +851,6 @@ index 19a98f4de83b..24e138611de2 100644 + .mode = 0444, + }, + { -+ .label = "ufm_version", -+ .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, -+ { + .label = "fan1", + .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), @@ -1113,10 +1074,11 @@ index 19a98f4de83b..24e138611de2 100644 +static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_data[] = { + { + .label = "pwm1", - .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, ++ .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, }, { -@@ -6641,6 +7400,123 @@ static struct mlxreg_core_platform_data mlxplat_xdr_fan_data = { + .label = "tacho1", +@@ -6635,6 +7352,123 @@ static struct mlxreg_core_platform_data mlxplat_xdr_fan_data = { .version = 1, }; @@ -1240,7 +1202,7 @@ index 19a98f4de83b..24e138611de2 100644 /* Watchdog type1: hardware implementation version1 * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems). */ -@@ -6876,6 +7752,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) +@@ -6870,6 +7704,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: @@ -1248,7 +1210,7 @@ index 19a98f4de83b..24e138611de2 100644 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: -@@ -6940,6 +7817,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) +@@ -6934,6 +7769,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: @@ -1257,7 +1219,7 @@ index 19a98f4de83b..24e138611de2 100644 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT: case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: -@@ -6961,6 +7840,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) +@@ -6955,6 +7792,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: @@ -1266,7 +1228,7 @@ index 19a98f4de83b..24e138611de2 100644 case MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET ... MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET: return true; } -@@ -7003,6 +7884,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) +@@ -6997,6 +7836,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: @@ -1274,7 +1236,7 @@ index 19a98f4de83b..24e138611de2 100644 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: -@@ -7095,6 +7977,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) +@@ -7089,6 +7929,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET: case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: @@ -1284,7 +1246,7 @@ index 19a98f4de83b..24e138611de2 100644 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET: case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT: -@@ -7154,6 +8039,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) +@@ -7148,6 +7991,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET: case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: @@ -1294,7 +1256,7 @@ index 19a98f4de83b..24e138611de2 100644 case MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET ... MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET: return true; } -@@ -7196,6 +8084,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) +@@ -7190,6 +8036,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: @@ -1302,7 +1264,7 @@ index 19a98f4de83b..24e138611de2 100644 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: -@@ -7286,6 +8175,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) +@@ -7280,6 +8127,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET: case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: @@ -1312,7 +1274,7 @@ index 19a98f4de83b..24e138611de2 100644 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET: case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT: -@@ -7339,6 +8231,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) +@@ -7333,6 +8183,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET: case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: @@ -1322,7 +1284,7 @@ index 19a98f4de83b..24e138611de2 100644 case MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET ... MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET: return true; } -@@ -7407,6 +8302,17 @@ static const struct reg_default mlxplat_mlxcpld_regmap_smart_switch[] = { +@@ -7401,6 +8254,17 @@ static const struct reg_default mlxplat_mlxcpld_regmap_smart_switch[] = { MLXPLAT_CPLD_LPC_SM_SW_MASK }, }; @@ -1340,7 +1302,7 @@ index 19a98f4de83b..24e138611de2 100644 struct mlxplat_mlxcpld_regmap_context { void __iomem *base; }; -@@ -7529,6 +8435,20 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_smart_switch = { +@@ -7523,6 +8387,20 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_smart_switch = { .reg_write = mlxplat_mlxcpld_reg_write, }; @@ -1361,7 +1323,7 @@ index 19a98f4de83b..24e138611de2 100644 /* Wait completion routine for indirect access for register map */ static int mlxplat_fpga_completion_wait(struct mlxplat_mlxcpld_regmap_context *ctx) { -@@ -7654,6 +8574,8 @@ static struct spi_board_info *mlxplat_spi; +@@ -7648,6 +8526,8 @@ static struct spi_board_info *mlxplat_spi; static struct pci_dev *lpc_bridge; static struct pci_dev *i2c_bridge; static struct pci_dev *jtag_bridge; @@ -1370,7 +1332,7 @@ index 19a98f4de83b..24e138611de2 100644 /* Platform default reset function */ static int mlxplat_reboot_notifier(struct notifier_block *nb, unsigned long action, void *unused) -@@ -7686,6 +8608,17 @@ static void mlxplat_poweroff(void) +@@ -7680,6 +8560,17 @@ static void mlxplat_poweroff(void) kernel_halt(); } @@ -1388,7 +1350,7 @@ index 19a98f4de83b..24e138611de2 100644 static int __init mlxplat_register_platform_device(void) { mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, -1, -@@ -8124,6 +9057,27 @@ static int __init mlxplat_dmi_smart_switch_matched(const struct dmi_system_id *d +@@ -8118,6 +9009,27 @@ static int __init mlxplat_dmi_smart_switch_matched(const struct dmi_system_id *d return mlxplat_register_platform_device(); } @@ -1416,7 +1378,7 @@ index 19a98f4de83b..24e138611de2 100644 static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { { .callback = mlxplat_dmi_default_wc_matched, -@@ -8243,6 +9197,27 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { +@@ -8237,6 +9149,27 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { DMI_MATCH(DMI_BOARD_NAME, "VMOD0019"), }, }, @@ -1444,7 +1406,7 @@ index 19a98f4de83b..24e138611de2 100644 { .callback = mlxplat_dmi_msn274x_matched, .matches = { -@@ -8331,8 +9306,8 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr) +@@ -8325,8 +9258,8 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr) int i, shift = 0; /* Scan adapters from expected id to verify it is free. */ @@ -1455,7 +1417,7 @@ index 19a98f4de83b..24e138611de2 100644 mlxplat_max_adap_num; i++) { search_adap = i2c_get_adapter(i); if (search_adap) { -@@ -8341,7 +9316,7 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr) +@@ -8335,7 +9268,7 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr) } /* Return if expected parent adapter is free. */ @@ -1464,7 +1426,7 @@ index 19a98f4de83b..24e138611de2 100644 return 0; break; } -@@ -8363,7 +9338,7 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr) +@@ -8357,7 +9290,7 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr) } /* Shift bus only if mux provided by 'mlxplat_mux_data'. */ diff --git a/recipes-kernel/linux/linux-6.1/9005-platform-mellanox-Downstream-Add-dedicated-match-for.patch b/recipes-kernel/linux/linux-6.1/9005-platform-mellanox-Downstream-Add-dedicated-match-for.patch index d5735318f..3cea33111 100644 --- a/recipes-kernel/linux/linux-6.1/9005-platform-mellanox-Downstream-Add-dedicated-match-for.patch +++ b/recipes-kernel/linux/linux-6.1/9005-platform-mellanox-Downstream-Add-dedicated-match-for.patch @@ -1,7 +1,7 @@ -From d0b2cf10e701e5420172e16234fab0aeaa7e54b9 Mon Sep 17 00:00:00 2001 +From 55cb6b6b99024a6ca620ced3f70fafd40c896753 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Wed, 2 Aug 2023 07:43:46 +0000 -Subject: [PATCH 09/20] platform/mellanox: Downstream: Add dedicated match for +Subject: [PATCH 04/15] platform/mellanox: Downstream: Add dedicated match for system type QMB8700 Use dedicated match function for QMB8700 system in order to work-around @@ -17,7 +17,7 @@ Reviewed-by: Vadim Pasternak 1 file changed, 352 insertions(+) diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index 24e138611de2..521ffef17ab9 100644 +index 3197f2f9b010..0b7b82a07f91 100644 --- a/drivers/platform/mellanox/mlx-platform.c +++ b/drivers/platform/mellanox/mlx-platform.c @@ -1385,6 +1385,57 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_fan_items_data[] = { @@ -266,7 +266,7 @@ index 24e138611de2..521ffef17ab9 100644 /* Platform led data for chassis system */ static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = { { -@@ -7221,6 +7439,107 @@ static struct mlxreg_core_platform_data mlxplat_default_fan_data = { +@@ -7173,6 +7391,107 @@ static struct mlxreg_core_platform_data mlxplat_default_fan_data = { .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, }; @@ -374,7 +374,7 @@ index 24e138611de2..521ffef17ab9 100644 /* XDR platform fan data */ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_data[] = { { -@@ -8889,6 +9208,32 @@ static int __init mlxplat_dmi_chassis_blade_matched(const struct dmi_system_id * +@@ -8841,6 +9160,32 @@ static int __init mlxplat_dmi_chassis_blade_matched(const struct dmi_system_id * return mlxplat_register_platform_device(); } @@ -407,7 +407,7 @@ index 24e138611de2..521ffef17ab9 100644 static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dmi) { int i; -@@ -9110,6 +9455,13 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { +@@ -9062,6 +9407,13 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { DMI_MATCH(DMI_BOARD_NAME, "VMOD0004"), }, },