diff --git a/recipes-kernel/linux/linux-5.10/0299-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch b/recipes-kernel/linux/linux-5.10/0299-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch
index e6982b998..ed1d71ddd 100644
--- a/recipes-kernel/linux/linux-5.10/0299-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch
+++ b/recipes-kernel/linux/linux-5.10/0299-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch
@@ -507,50 +507,50 @@ index 785f5870d..e3cef3c6d 100644
 +		.label = "dpu1_rst",
 +		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(0),
-+		.mode = 0200,
++		.mode = 0644,
  	},
  	{
 -		.label = "tacho10",
 +		.label = "dpu2_rst",
 +		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(1),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "dpu3_rst",
 +		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(2),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "dpu4_rst",
 +		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(3),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "dpu1_pwr",
 +		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(0),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "dpu2_pwr",
 +		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(1),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "dpu3_pwr",
 +		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(2),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "dpu4_pwr",
 +		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(3),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "reset_long_pb",
@@ -800,25 +800,25 @@ index 785f5870d..e3cef3c6d 100644
 +		.label = "dpu1_pwr_force",
 +		.reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(0),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "dpu2_pwr_force",
 +		.reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(1),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "dpu3_pwr_force",
 +		.reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(2),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "dpu4_pwr_force",
 +		.reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(3),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "ufm_done",
diff --git a/recipes-kernel/linux/linux-6.1/0092-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch b/recipes-kernel/linux/linux-6.1/0092-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch
index b7435002f..98b911881 100644
--- a/recipes-kernel/linux/linux-6.1/0092-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch
+++ b/recipes-kernel/linux/linux-6.1/0092-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch
@@ -507,50 +507,50 @@ index cafa4f762..0949f32ad 100644
 +		.label = "dpu1_rst",
 +		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(0),
-+		.mode = 0200,
++		.mode = 0644,
  	},
  	{
 -		.label = "tacho10",
 +		.label = "dpu2_rst",
 +		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(1),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "dpu3_rst",
 +		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(2),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "dpu4_rst",
 +		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(3),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "dpu1_pwr",
 +		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(0),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "dpu2_pwr",
 +		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(1),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "dpu3_pwr",
 +		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(2),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "dpu4_pwr",
 +		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(3),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "reset_long_pb",
@@ -800,25 +800,25 @@ index cafa4f762..0949f32ad 100644
 +		.label = "dpu1_pwr_force",
 +		.reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(0),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "dpu2_pwr_force",
 +		.reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(1),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "dpu3_pwr_force",
 +		.reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(2),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "dpu4_pwr_force",
 +		.reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET,
 +		.mask = GENMASK(7, 0) & ~BIT(3),
-+		.mode = 0200,
++		.mode = 0644,
 +	},
 +	{
 +		.label = "ufm_done",