diff --git a/README.md b/README.md index 47c0240..b911127 100644 --- a/README.md +++ b/README.md @@ -1 +1,92 @@ -# wireless_15_4_phy_trx \ No newline at end of file +![Microchip logo](https://raw.githubusercontent.com/wiki/Microchip-MPLAB-Harmony/Microchip-MPLAB-Harmony.github.io/images/microchip_logo.png) +![Harmony logo small](https://raw.githubusercontent.com/wiki/Microchip-MPLAB-Harmony/Microchip-MPLAB-Harmony.github.io/images/microchip_mplab_harmony_logo_small.png) + +# MPLAB® Harmony 3 Standalone IEEE 802.15.4 Physical Layer + +MPLAB® Harmony 3 is an extension of the MPLAB® ecosystem for creating embedded firmware solutions for Microchip 32-bit SAM and PIC® microcontroller and microprocessor devices. Refer to the following links for more information. + +- [Microchip 32-bit MCUs](https://www.microchip.com/design-centers/32-bit) +- [Microchip 32-bit MPUs](https://www.microchip.com/design-centers/32-bit-mpus) +- [Microchip MPLAB X IDE](https://www.microchip.com/mplab/mplab-x-ide) +- [Microchip MPLAB® Harmony](https://www.microchip.com/mplab/mplab-harmony) +- [Microchip MPLAB® Harmony Pages](https://microchip-mplab-harmony.github.io/) + +This repository contains the MPLAB® Harmony 3 Module for Standalone IEEE 802.15.4 Physical Layer that provide an interface to the microcontrollers (like SAML21, SAMD21) to access the transceiver functionality of radio transceivers like AT86RF233 or AT86RF212B. +With the help of PHY layer module user can enable various functionaities of the transceiver. +reference information. + + +- [MPLAB® Harmony License](mplab_harmony_license.md) + + +# Contents Summary + +| Folder | Description | +| -----------| ------------------------------------------------------------------| +| config | Standalone IEEE 802.15.4 Physical Layer module | +| docs| [User guide](./README.md) +| drivers | phy layer files | + +- Clone the [Standalone PHY](https://github.com/MicrochipTech/wireless_15_4_phy_trx) repo to user's local Harmony Repo. +- Refer to the section 2.5, Creating a New MCC Harmony Project in the [PIC32CXBZ2 Application Developer's Guide](https://onlinedocs.microchip.com/g/GUID-A5330D3A-9F51-4A26-B71D-8503A493DF9C). +- Project Graph appears with some predefined component as shown in image below: + +![](docs/img1.jpg) + +- The IEEE 802.15.4 PHY component will appear under Wireless->Drivers->IEEE 802.15.4 in the Device Resources tab as shown in image below: + +![](docs/img2.png) + +- Select MiWi (if MiWi protocol is used as higher layer) under “Wireless->Drivers” tab. Accept all Dependencies or satisfiers, by selecting "Yes". All the necessary components will be auto populated. +- Please follow the steps in the following [link](https://github.com/MicrochipTech/MiWi/blob/main/docs/GUID-32628D58-8B41-490F-8DA4-520C34856980.md) to configure for MiWi. + +- Connect SERCOM5 and TC0 dependencies as shown in the image below: + +![](docs/img3.png) + +- Finally ensure that the project graph has all the components as depicted below. + +![](docs/img4.PNG) + +- Please follow the below steps for the “Configuration Options” changes to be done for Standalone PHY layer. +- Go to Plugins>Pin Configuration. Refer below image for the Pin configurations. Provide the same “Custom Name”, “Function” and “Direction” as depicted in image below. + +![](docs/PinCfg1.PNG) + +![](docs/pinCfg2.PNG) + +- The “Module Pin Selections” in the “Configuration Options” gets automatically populated when the correct pin configurations are configured. +- The Radio transceiver type can be changed by selecting the dropdown option availabel in “Select Transceiver Type”. At present only RF233 ans RF212B is supported. + +![](docs/phy_configuration.PNG) + +- Following are the EIC and Sercom5 configuration. + +![](docs/eic_configuration.PNG) + +![](docs/sercom_config.PNG) + +- Click on “Resource Management [MCC]” and click “Generate”. + +![](docs/mcc_code_gen.jpg) + +Note 1: After generating the code via MCC, make sure to implement the following changes. Right click on the project and go to properties. Select xc32-gcc. Under the option categories, select Preprocessing and Messages. +Double click on the Preprocessor macros and add the symbol, PHY_AT86RF212B/PHY_AT86RF233 depending on the preference. Remove ENABLE_NETWORK_FREEZER & Chimera_SOC symbol if MiWi is used. + +Note 2: To optimise the NVIC priority levels of different peripherals used such as EIC, SPI and TC, go to project source files>config>default>peripheral>plib_nvic.c, change the NVIC priority as shown in the image below: + +![](docs/nvic_priority.PNG) + +Note 3: In app.c file replace "appData.appQueue = xQueueCreate( 64, sizeof(APP_Msg_T) );" with "appData.appQueue = xQueueCreate( 5, sizeof(APP_Msg_T) );" + +Note 4: The following applies if MiWi protocol is used as higher layer : In the file tasks.c replace "#define TASK_MIWI_STACK_SIZE (8 *1024 / sizeof(portSTACK_TYPE))" with "#define TASK_MIWI_STACK_SIZE (2 *1024 / sizeof(portSTACK_TYPE))" + +Note 5: The size of lAPP_Tasks should be changed to 512 in task.c file. + +[![Follow us on Youtube](https://img.shields.io/badge/Youtube-Follow%20us%20on%20Youtube-red.svg)](https://www.youtube.com/user/MicrochipTechnology) +[![Follow us on LinkedIn](https://img.shields.io/badge/LinkedIn-Follow%20us%20on%20LinkedIn-blue.svg)](https://www.linkedin.com/company/microchip-technology) +[![Follow us on Facebook](https://img.shields.io/badge/Facebook-Follow%20us%20on%20Facebook-blue.svg)](https://www.facebook.com/microchiptechnology/) +[![Follow us on Twitter](https://img.shields.io/twitter/follow/MicrochipTech.svg?style=social)](https://twitter.com/MicrochipTech) + + + diff --git a/config/module.py b/config/module.py new file mode 100644 index 0000000..59b58d4 --- /dev/null +++ b/config/module.py @@ -0,0 +1,38 @@ +"""***************************************************************************** +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*****************************************************************************""" + + +def loadModule(): + print('Load Module: Harmony IEEE 802.15.4 PHY Standalone Library') + + + rfHostComponent = Module.CreateComponent('IEEE_802154_PHY', 'IEEE 802.15.4 PHY', 'Wireless/Drivers/IEEE 802.15.4','driver/config/drv_ieee802154phy_standalone.py') + rfHostComponent.setDisplayType('HOST<->TRANSCEIVER INTERFACE\n\n\n') + rfHostComponent.addDependency('TRANSCEIVER_SPI_Dependency', 'SPI','SERCOM',False, True) + rfHostComponent.addDependency('HarmonyCoreDependency', 'Core Service', 'Core', True, True) + rfHostComponent.addDependency('SysTimeDependency', 'SYS_TIME', 'SYS_TIME', True, True) + rfHostComponent.addDependency('FreeRtosDependency', 'RTOS', 'RTOS', True, True) + rfHostComponent.addCapability('ieee802154phy_Capability', 'IEEE 802.15.4 PHY', True) + + + diff --git a/docs/Capture.PNG b/docs/Capture.PNG new file mode 100644 index 0000000..6402426 Binary files /dev/null and b/docs/Capture.PNG differ diff --git a/docs/PinCfg1.PNG b/docs/PinCfg1.PNG new file mode 100644 index 0000000..38f26e1 Binary files /dev/null and b/docs/PinCfg1.PNG differ diff --git a/docs/eic_configuration.PNG b/docs/eic_configuration.PNG new file mode 100644 index 0000000..fefd240 Binary files /dev/null and b/docs/eic_configuration.PNG differ diff --git a/docs/img1.jpg b/docs/img1.jpg new file mode 100644 index 0000000..f4bcb73 Binary files /dev/null and b/docs/img1.jpg differ diff --git a/docs/img2.png b/docs/img2.png new file mode 100644 index 0000000..692a9ef Binary files /dev/null and b/docs/img2.png differ diff --git a/docs/img3.png b/docs/img3.png new file mode 100644 index 0000000..3caf019 Binary files /dev/null and b/docs/img3.png differ diff --git a/docs/img4.PNG b/docs/img4.PNG new file mode 100644 index 0000000..1cbd927 Binary files /dev/null and b/docs/img4.PNG differ diff --git a/docs/mcc_code_gen.jpg b/docs/mcc_code_gen.jpg new file mode 100644 index 0000000..02d3825 Binary files /dev/null and b/docs/mcc_code_gen.jpg differ diff --git a/docs/nvic_priority.PNG b/docs/nvic_priority.PNG new file mode 100644 index 0000000..0265a41 Binary files /dev/null and b/docs/nvic_priority.PNG differ diff --git a/docs/phy_configuration.PNG b/docs/phy_configuration.PNG new file mode 100644 index 0000000..b80094e Binary files /dev/null and b/docs/phy_configuration.PNG differ diff --git a/docs/pinCfg2.PNG b/docs/pinCfg2.PNG new file mode 100644 index 0000000..227d723 Binary files /dev/null and b/docs/pinCfg2.PNG differ diff --git a/docs/sercom_config.PNG b/docs/sercom_config.PNG new file mode 100644 index 0000000..e1cb0ab Binary files /dev/null and b/docs/sercom_config.PNG differ diff --git a/driver/config/drv_ieee802154phy_standalone.py b/driver/config/drv_ieee802154phy_standalone.py new file mode 100644 index 0000000..09569c0 --- /dev/null +++ b/driver/config/drv_ieee802154phy_standalone.py @@ -0,0 +1,1408 @@ +"""***************************************************************************** +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*****************************************************************************""" + + +Transceiver_Type_options = ["RF212B","RF233", "RF215"] + + +Pin_Configuration = {'IRQ':{'Pin':'', + 'Name':'IRQ', + 'Dir':'', + 'update':False}, + 'CLKM' :{'Pin':'', + 'Name':'CLKM', + 'Dir':'', + 'update':False}, + 'DIG1' :{'Pin':'', + 'Name':'DIG1', + 'Dir':'', + 'update':False}, + 'DIG2' :{'Pin':'', + 'Name':'DIG2', + 'Dir':'', + 'update':False}, + 'DIG3' :{'Pin':'', + 'Name':'DIG3', + 'Dir':'', + 'update':False}, + 'DIG4' :{'Pin':'', + 'Name':'DIG4', + 'Dir':'', + 'update':False}, + '_RST' :{'Pin':'', + 'Name':'RST', + 'Dir':'', + 'update':False}, + 'SLP_TR' :{'Pin':'', + 'Name':'SLP_TR', + 'Dir':'', + 'update':False}, + + } + +global irq_pin_config_msg +irq_pin_config_msg = "**Set the pin functionality as *EIC_EXTINT4*, Pin name as *IRQ*, pin Direction as *In***" + +global clkm_pin_config_msg +clkm_pin_config_msg = "**Set the pin functionality as *GPIO*, Pin name as *CLKM*, pin Direction as *In***" + +global dig1_pin_config_msg +dig1_pin_config_msg = "**Set the pin functionality as *GPIO*, Pin name as *DIG1*, pin Direction as *In***" + +global dig2_pin_config_msg +dig2_pin_config_msg = "**Set the pin functionality as *GPIO*, Pin name as *DIG2*, pin Direction as *In***" + +global dig3_pin_config_msg +dig3_pin_config_msg = "**Set the pin functionality as *GPIO*, Pin name as *DIG3*, pin Direction as *In***" + +global dig4_pin_config_msg +dig4_pin_config_msg = "**Set the pin functionality as *GPIO*, Pin name as *DIG4*, pin Direction as *In***" + +global rst_pin_config_msg +rst_pin_config_msg = "**Set the pin functionality as *GPIO*, Pin name as *_RST*, pin Direction as *Out***" + +global slp_tr_pin_config_msg +slp_tr_pin_config_msg = "**Set the pin functionality as *GPIO*, Pin name as *SLP_TR*, pin Direction as *Out***" + +def handleMessage(messageID, args): + print("Handle Message") + + +####################################################################################### +## GPIO Read +####################################################################################### +import re + +def sort_alphanumeric(var): + print("sort_alphanumeric") + convert = lambda text: int(text) if text.isdigit() else text.lower() + alphanum_key = lambda key: [ convert(c) for c in re.split('([0-9]+)', key) ] + return sorted(var, key = alphanum_key) + +def get_port_pin_dependencies(): + global pin_map_internal + global portPackage + pin_map_internal = {} + package = {} + global gpio_dependency + gpio_dependency = [] + global gpio_attr_sym + gpio_attr_sym = {} + global gpio_attr_update + gpio_attr_update = {} + global pin_map + pin_map = {} + # Build package pinout map + packageNode = ATDF.getNode("/avr-tools-device-file/variants") + for id in range(0,len(packageNode.getChildren())): + package[packageNode.getChildren()[id].getAttribute("package")] = packageNode.getChildren()[id].getAttribute("pinout") + + ## Find Number of unique pinouts + uniquePinout = len(set(package.values())) + ## get the pin count + pincount = int(re.findall(r'\d+', package.keys()[0])[0]) + max_index = Database.getSymbolValue("core","PORT_PIN_MAX_INDEX") + # Create portGroupName list of uppercase letters + global portGroupName + portGroupName = [] + for letter in range(65,91): + portGroupName.append(chr(letter)) + + portPackage = Database.getSymbolValue("core","COMPONENT_PACKAGE") + + pinoutNode = ATDF.getNode('/avr-tools-device-file/pinouts/pinout@[name= "' + str(package.get(portPackage)) + '"]') + for id in range(0,len(pinoutNode.getChildren())): + if pinoutNode.getChildren()[id].getAttribute("type") == None: + if "BGA" in portPackage or "WLCSP" in portPackage or "DRQFN" in portPackage: + pin_map[pinoutNode.getChildren()[id].getAttribute("position")] = pinoutNode.getChildren()[id].getAttribute("pad") + else: + pin_map[int(pinoutNode.getChildren()[id].getAttribute("position"))] = pinoutNode.getChildren()[id].getAttribute("pad") + else: + pin_map_internal[pinoutNode.getChildren()[id].getAttribute("type").split("INTERNAL_")[1]] = pinoutNode.getChildren()[id].getAttribute("pad") + + if "BGA" in portPackage or "WLCSP" in portPackage or "DRQFN" in portPackage: + pin_position = sort_alphanumeric(pin_map.keys()) + pin_position_internal = sort_alphanumeric(pin_map_internal.keys()) + else: + pin_position = sorted(pin_map.keys()) + pin_position_internal = sorted(pin_map_internal.keys()) + + internalPincount = pincount + len(pin_map_internal.keys()) + + global pin_num_ID_map + pin_num_ID_map = {} + global pin_IDS + pin_IDS = [] + for pinNumber in range(1, internalPincount + 1): + gpio_local = {} + if pinNumber < pincount + 1: + gpio_attr_sym[str(pinNumber)] = ["core."+"PORT_PIN"+str(pinNumber),"core."+"PIN_" + str(pinNumber) + "_PORT_PIN", "core."+"PIN_" + str(pinNumber) + "_PORT_GROUP","core."+"PIN_" + str(pinNumber) + "_FUNCTION_NAME","core."+"PIN_" + str(pinNumber) + "_PERIPHERAL_FUNCTION","core."+"PIN_" + str(pinNumber) + "_INEN"] + gpio_local['Pin_num'] = Database.getSymbolValue('core',"PORT_PIN"+str(pinNumber)) + gpio_local['Bit_Pos'] = Database.getSymbolValue('core',"PIN_" + str(pinNumber) + "_PORT_PIN") + gpio_local['Group'] = Database.getSymbolValue('core',"PIN_" + str(pinNumber) + "_PORT_GROUP") + gpio_local['Name'] = Database.getSymbolValue('core',"PIN_" + str(pinNumber) + "_FUNCTION_NAME") + gpio_local['Pin_Func'] = Database.getSymbolValue('core',"PIN_" + str(pinNumber) + "_PERIPHERAL_FUNCTION") + gpio_local['Dir'] = Database.getSymbolValue('core',"PIN_" + str(pinNumber) + "_DIR") + gpio_local['INEN'] = Database.getSymbolValue('core',"PIN_" + str(pinNumber) + "_INEN") + gpio_attr_update[str(pinNumber)] = gpio_local + if str(gpio_attr_update[str(pinNumber)]['Bit_Pos']) != '0': + pin_num_ID_map[pinNumber] = str('P'+str(gpio_attr_update[str(pinNumber)]['Group'])+ str(gpio_attr_update[str(pinNumber)]['Bit_Pos'])) + #pin_IDS.append(str('P'+str(gpio_attr_update[str(pinNumber)]['Group'])+ str(gpio_attr_update[str(pinNumber)]['Bit_Pos']))) + for attr in range(len(gpio_attr_sym[str(pinNumber)])): + gpio_dependency.append(gpio_attr_sym[str(pinNumber)][attr]) + check_Assigned_GPIO_Functionality(gpio_local['Name'],pinNumber) + + else: + gpio_attr_sym[str(pinNumber)] = ["core."+"PORT_PIN"+str(pinNumber),"core."+"PIN_" + str(pinNumber) + "_PORT_PIN", "core."+"PIN_" + str(pinNumber) + "_PORT_GROUP","core."+"PIN_" + str(pinNumber) + "_FUNCTION_NAME","core."+"PIN_" + str(pinNumber) + "_PERIPHERAL_FUNCTION","core."+"PIN_" + str(pinNumber) + "_DIR","core."+"PIN_" + str(pinNumber) + "_INEN"] + gpio_local['Pin_num'] = Database.getSymbolValue('core',"PORT_PIN"+str(pinNumber)) + gpio_local['Bit_Pos'] = Database.getSymbolValue('core',"PIN_" + str(pinNumber) + "_PORT_PIN") + gpio_local['Group'] = Database.getSymbolValue('core',"PIN_" + str(pinNumber) + "_PORT_GROUP") + gpio_local['Name'] = Database.getSymbolValue('core',"PIN_" + str(pinNumber) + "_FUNCTION_NAME") + gpio_local['Pin_Func'] = Database.getSymbolValue('core',"PIN_" + str(pinNumber) + "_PERIPHERAL_FUNCTION") + gpio_local['Dir'] = Database.getSymbolValue('core',"PIN_" + str(pinNumber) + "_DIR") + gpio_local['INEN'] = Database.getSymbolValue('core',"PIN_" + str(pinNumber) + "_INEN") + gpio_attr_update[str(pinNumber)] = gpio_local + if str(gpio_attr_update[str(pinNumber)]['Bit_Pos']) != '0': + pin_num_ID_map[pinNumber] = str('P'+str(gpio_attr_update[str(pinNumber)]['Group'])+ str(gpio_attr_update[str(pinNumber)]['Bit_Pos'])) + #pin_IDS.append(str('P'+str(gpio_attr_update[str(pinNumber)]['Group'])+ str(gpio_attr_update[str(pinNumber)]['Bit_Pos']))) + for attr in range(len(gpio_attr_sym[str(pinNumber)])): + gpio_dependency.append(gpio_attr_sym[str(pinNumber)][attr]) + check_Assigned_GPIO_Functionality(gpio_local['Name'],pinNumber) + + +def check_Assigned_GPIO_Functionality(GPIO_Name,pinNumber): + print("check_Assigned_GPIO_Functionality") + if GPIO_Name == 'IRQ': + print("gpio name: IRQ, function type = ", gpio_local['Pin_Func'] ) + Pin_Configuration[str(gpio_attr_update[str(pinNumber)]['Name'])].update({'Pin': 'P'+str(gpio_attr_update[str(pinNumber)]['Group'])+ str(gpio_attr_update[str(pinNumber)]['Bit_Pos'])}) + Pin_Configuration[str('IRQ')].update({'update':True}) + if GPIO_Name == 'CLKM': + print("gpio name: CLKM" ) + Pin_Configuration[str(gpio_attr_update[str(pinNumber)]['Name'])].update({'Pin': 'P'+str(gpio_attr_update[str(pinNumber)]['Group'])+ str(gpio_attr_update[str(pinNumber)]['Bit_Pos'])}) + Pin_Configuration[str('CLKM')].update({'update':True}) + if GPIO_Name == 'DIG1': + print("gpio name: DIG1" ) + Pin_Configuration[str(gpio_attr_update[str(pinNumber)]['Name'])].update({'Pin': 'P'+str(gpio_attr_update[str(pinNumber)]['Group'])+ str(gpio_attr_update[str(pinNumber)]['Bit_Pos'])}) + Pin_Configuration[str('DIG1')].update({'update':True}) + if GPIO_Name == 'DIG2': + print("gpio name: DIG2" ) + Pin_Configuration[str(gpio_attr_update[str(pinNumber)]['Name'])].update({'Pin': 'P'+str(gpio_attr_update[str(pinNumber)]['Group'])+ str(gpio_attr_update[str(pinNumber)]['Bit_Pos'])}) + Pin_Configuration[str('DIG2')].update({'update':True}) + if GPIO_Name == 'DIG3': + print("gpio name: DIG3" ) + Pin_Configuration[str(gpio_attr_update[str(pinNumber)]['Name'])].update({'Pin': 'P'+str(gpio_attr_update[str(pinNumber)]['Group'])+ str(gpio_attr_update[str(pinNumber)]['Bit_Pos'])}) + Pin_Configuration[str('DIG3')].update({'update':True}) + if GPIO_Name == 'DIG4': + print("gpio name: DIG4" ) + Pin_Configuration[str(gpio_attr_update[str(pinNumber)]['Name'])].update({'Pin': 'P'+str(gpio_attr_update[str(pinNumber)]['Group'])+ str(gpio_attr_update[str(pinNumber)]['Bit_Pos'])}) + Pin_Configuration[str('DIG4')].update({'update':True}) + if GPIO_Name == '_RST': + print("gpio name: _RST" ) + Pin_Configuration[str(gpio_attr_update[str(pinNumber)]['Name'])].update({'Pin': 'P'+str(gpio_attr_update[str(pinNumber)]['Group'])+ str(gpio_attr_update[str(pinNumber)]['Bit_Pos'])}) + Pin_Configuration[str('_RST')].update({'update':True}) + if GPIO_Name == 'SLP_TR': + print("gpio name: SLP_TR" ) + Pin_Configuration[str(gpio_attr_update[str(pinNumber)]['Name'])].update({'Pin': 'P'+str(gpio_attr_update[str(pinNumber)]['Group'])+ str(gpio_attr_update[str(pinNumber)]['Bit_Pos'])}) + Pin_Configuration[str('SLP_TR')].update({'update':True}) + + +def GPIO_Update_Callback(symbol,event): + print("GPIO_Update_Callback") + print('GPIO callback Triggered') + print("symbol:: ", symbol) + print("event:: ", event) + sym_ID = symbol.getID() + print('sym_ID',sym_ID) + + print('event_val:',event['value']) + + pin_num = (re.findall(r'\d+', event['id']))[0] + if 'PERIPHERAL_FUNCTION' in event['id']: + print("gpio_attr_update:",gpio_attr_update[str(pin_num)] ) + gpio_attr_update[str(pin_num)].update({'Pin_Func' : str(event['value'])}) + print("gpio_attr_update after pin fn update:",gpio_attr_update[str(pin_num)] ) + print("pin configuration: ", Pin_Configuration["IRQ"]) + + if 'P' + str(gpio_attr_update[str(pin_num)]['Group']) + str(gpio_attr_update[str(pin_num)]['Bit_Pos']) == Pin_Configuration["IRQ"]['Pin'] and gpio_attr_update[str(pin_num)]['Pin_Func'] != 'A': + print("PA0==IRQ[pin] and pin function != EIC_EXTINT0") + Pin_Configuration["IRQ"].update({'Pin':''}) + rfHostIrqPin.setValue('') + + if 'P' + str(gpio_attr_update[str(pin_num)]['Group']) + str(gpio_attr_update[str(pin_num)]['Bit_Pos']) == Pin_Configuration["CLKM"]['Pin'] and gpio_attr_update[str(pin_num)]['Pin_Func'] != 'GPIO': + print("PA0==CLKM[pin] and pin function != GPIO") + Pin_Configuration["CLKM"].update({'Pin':''}) + rfHostClkmPin.setValue('') + + if 'P' + str(gpio_attr_update[str(pin_num)]['Group']) + str(gpio_attr_update[str(pin_num)]['Bit_Pos']) == Pin_Configuration["DIG1"]['Pin'] and gpio_attr_update[str(pin_num)]['Pin_Func'] != 'GPIO': + print("PA0==DIG1[pin] and pin function != GPIO") + Pin_Configuration["DIG1"].update({'Pin':''}) + rfHostDig1Pin.setValue('') + + if 'P' + str(gpio_attr_update[str(pin_num)]['Group']) + str(gpio_attr_update[str(pin_num)]['Bit_Pos']) == Pin_Configuration["DIG2"]['Pin'] and gpio_attr_update[str(pin_num)]['Pin_Func'] != 'GPIO': + print("PA0==DIG2[pin] and pin function != GPIO") + Pin_Configuration["DIG2"].update({'Pin':''}) + rfHostDig2Pin.setValue('') + + if 'P' + str(gpio_attr_update[str(pin_num)]['Group']) + str(gpio_attr_update[str(pin_num)]['Bit_Pos']) == Pin_Configuration["DIG3"]['Pin'] and gpio_attr_update[str(pin_num)]['Pin_Func'] != 'GPIO': + print("PA0==DIG3[pin] and pin function != GPIO") + Pin_Configuration["DIG3"].update({'Pin':''}) + rfHostDig3Pin.setValue('') + + if 'P' + str(gpio_attr_update[str(pin_num)]['Group']) + str(gpio_attr_update[str(pin_num)]['Bit_Pos']) == Pin_Configuration["DIG4"]['Pin'] and gpio_attr_update[str(pin_num)]['Pin_Func'] != 'GPIO': + print("PA0==DIG4[pin] and pin function != GPIO") + Pin_Configuration["DIG4"].update({'Pin':''}) + rfHostDig4Pin.setValue('') + + if 'P' + str(gpio_attr_update[str(pin_num)]['Group']) + str(gpio_attr_update[str(pin_num)]['Bit_Pos']) == Pin_Configuration["_RST"]['Pin'] and gpio_attr_update[str(pin_num)]['Pin_Func'] != 'GPIO': + print("PA0==_RST[pin] and pin function != GPIO") + Pin_Configuration["_RST"].update({'Pin':''}) + rfHost_RstPin.setValue('') + + if 'P' + str(gpio_attr_update[str(pin_num)]['Group']) + str(gpio_attr_update[str(pin_num)]['Bit_Pos']) == Pin_Configuration["SLP_TR"]['Pin'] and gpio_attr_update[str(pin_num)]['Pin_Func'] != 'GPIO': + print("PA0==SLP_TR[pin] and pin function != GPIO") + Pin_Configuration["SLP_TR"].update({'Pin':''}) + rfHostSlpTrPin.setValue('') + + + elif 'FUNCTION_NAME' in event['id']: + gpio_attr_update[str(pin_num)].update({'Name' : str(event['value'])}) + if str(event['value']) == 'IRQ' and gpio_attr_update[str(pin_num)]['Pin_Func'] == 'A': + Pin_Configuration["IRQ"].update({'Pin':'P'+ str(gpio_attr_update[str(pin_num)]['Group'])+str(gpio_attr_update[str(pin_num)]['Bit_Pos'])}) + rfHostIrqPin.setValue(Pin_Configuration[str(event['value'])]['Pin']) + + + if str(event['value']) == 'CLKM' and gpio_attr_update[str(pin_num)]['Pin_Func'] == 'GPIO': + Pin_Configuration["CLKM"].update({'Pin':'P'+ str(gpio_attr_update[str(pin_num)]['Group'])+str(gpio_attr_update[str(pin_num)]['Bit_Pos'])}) + rfHostClkmPin.setValue(Pin_Configuration[str(event['value'])]['Pin']) + + if str(event['value']) == 'DIG1' and gpio_attr_update[str(pin_num)]['Pin_Func'] == 'GPIO': + Pin_Configuration["DIG1"].update({'Pin':'P'+ str(gpio_attr_update[str(pin_num)]['Group'])+str(gpio_attr_update[str(pin_num)]['Bit_Pos'])}) + rfHostDig1Pin.setValue(Pin_Configuration[str(event['value'])]['Pin']) + + if str(event['value']) == 'DIG2' and gpio_attr_update[str(pin_num)]['Pin_Func'] == 'GPIO': + Pin_Configuration["DIG2"].update({'Pin':'P'+ str(gpio_attr_update[str(pin_num)]['Group'])+str(gpio_attr_update[str(pin_num)]['Bit_Pos'])}) + rfHostDig2Pin.setValue(Pin_Configuration[str(event['value'])]['Pin']) + + if str(event['value']) == 'DIG3' and gpio_attr_update[str(pin_num)]['Pin_Func'] == 'GPIO': + Pin_Configuration["DIG3"].update({'Pin':'P'+ str(gpio_attr_update[str(pin_num)]['Group'])+str(gpio_attr_update[str(pin_num)]['Bit_Pos'])}) + rfHostDig3Pin.setValue(Pin_Configuration[str(event['value'])]['Pin']) + + if str(event['value']) == 'DIG4' and gpio_attr_update[str(pin_num)]['Pin_Func'] == 'GPIO': + + Pin_Configuration["DIG4"].update({'Pin':'P'+ str(gpio_attr_update[str(pin_num)]['Group'])+str(gpio_attr_update[str(pin_num)]['Bit_Pos'])}) + rfHostDig4Pin.setValue(Pin_Configuration[str(event['value'])]['Pin']) + + + if str(event['value']) == '_RST' and gpio_attr_update[str(pin_num)]['Pin_Func'] == 'GPIO': + + Pin_Configuration["_RST"].update({'Pin':'P'+ str(gpio_attr_update[str(pin_num)]['Group'])+str(gpio_attr_update[str(pin_num)]['Bit_Pos'])}) + rfHost_RstPin.setValue(Pin_Configuration[str(event['value'])]['Pin']) + + if str(event['value']) == 'SLP_TR' and gpio_attr_update[str(pin_num)]['Pin_Func'] == 'GPIO': + Pin_Configuration["SLP_TR"].update({'Pin':'P'+ str(gpio_attr_update[str(pin_num)]['Group'])+str(gpio_attr_update[str(pin_num)]['Bit_Pos'])}) + rfHostSlpTrPin.setValue(Pin_Configuration[str(event['value'])]['Pin']) + +def check_gpio_dir(): + print("check_gpio_dir") + reset_pin_flag = False + status1_flag = False + status2_flag = False + + if Pin_Configuration['IRQ']['Pin'] != '': + reset_pin_dir = str(Database.getSymbolValue('core','PIN_'+ str(extract_pin_num_ID(pin_ID_req=str(Pin_Configuration['IRQ']['Pin']))) + "_DIR")) + reset_pin_inen = str(Database.getSymbolValue('core','PIN_'+ str(extract_pin_num_ID(pin_ID_req=str(Pin_Configuration['IRQ']['Pin']))) + "_INEN")) + if (reset_pin_dir == '') or (reset_pin_inen == 'True'): + rnHostRstPinMsg.setLabel(rst_pin_dir_config_msg) + rnHostRstPinMsg.setVisible(True) + reset_pin_flag = True + + if Pin_Configuration['CLKM']['Pin'] != '': + reset_pin_dir = str(Database.getSymbolValue('core','PIN_'+ str(extract_pin_num_ID(pin_ID_req=str(Pin_Configuration['CLKM']['Pin']))) + "_DIR")) + reset_pin_inen = str(Database.getSymbolValue('core','PIN_'+ str(extract_pin_num_ID(pin_ID_req=str(Pin_Configuration['CLKM']['Pin']))) + "_INEN")) + if (reset_pin_dir == '') or (reset_pin_inen == 'True'): + rnHostRstPinMsg.setLabel(rst_pin_dir_config_msg) + rnHostRstPinMsg.setVisible(True) + reset_pin_flag = True + + if Pin_Configuration['DIG1']['Pin'] != '': + reset_pin_dir = str(Database.getSymbolValue('core','PIN_'+ str(extract_pin_num_ID(pin_ID_req=str(Pin_Configuration['DIG1']['Pin']))) + "_DIR")) + reset_pin_inen = str(Database.getSymbolValue('core','PIN_'+ str(extract_pin_num_ID(pin_ID_req=str(Pin_Configuration['DIG1']['Pin']))) + "_INEN")) + if (reset_pin_dir == '') or (reset_pin_inen == 'True'): + rnHostRstPinMsg.setLabel(rst_pin_dir_config_msg) + rnHostRstPinMsg.setVisible(True) + reset_pin_flag = True + + if Pin_Configuration['DIG2']['Pin'] != '': + reset_pin_dir = str(Database.getSymbolValue('core','PIN_'+ str(extract_pin_num_ID(pin_ID_req=str(Pin_Configuration['DIG2']['Pin']))) + "_DIR")) + reset_pin_inen = str(Database.getSymbolValue('core','PIN_'+ str(extract_pin_num_ID(pin_ID_req=str(Pin_Configuration['DIG2']['Pin']))) + "_INEN")) + if (reset_pin_dir == '') or (reset_pin_inen == 'True'): + rnHostRstPinMsg.setLabel(rst_pin_dir_config_msg) + rnHostRstPinMsg.setVisible(True) + reset_pin_flag = True + + if Pin_Configuration['DIG3']['Pin'] != '': + reset_pin_dir = str(Database.getSymbolValue('core','PIN_'+ str(extract_pin_num_ID(pin_ID_req=str(Pin_Configuration['DIG3']['Pin']))) + "_DIR")) + reset_pin_inen = str(Database.getSymbolValue('core','PIN_'+ str(extract_pin_num_ID(pin_ID_req=str(Pin_Configuration['DIG3']['Pin']))) + "_INEN")) + if (reset_pin_dir == '') or (reset_pin_inen == 'True'): + rnHostRstPinMsg.setLabel(rst_pin_dir_config_msg) + rnHostRstPinMsg.setVisible(True) + reset_pin_flag = True + + if Pin_Configuration['DIG4']['Pin'] != '': + reset_pin_dir = str(Database.getSymbolValue('core','PIN_'+ str(extract_pin_num_ID(pin_ID_req=str(Pin_Configuration['DIG4']['Pin']))) + "_DIR")) + reset_pin_inen = str(Database.getSymbolValue('core','PIN_'+ str(extract_pin_num_ID(pin_ID_req=str(Pin_Configuration['DIG4']['Pin']))) + "_INEN")) + if (reset_pin_dir == '') or (reset_pin_inen == 'True'): + rnHostRstPinMsg.setLabel(rst_pin_dir_config_msg) + rnHostRstPinMsg.setVisible(True) + reset_pin_flag = True + + if Pin_Configuration['_RST']['Pin'] != '': + reset_pin_dir = str(Database.getSymbolValue('core','PIN_'+ str(extract_pin_num_ID(pin_ID_req=str(Pin_Configuration['_RST']['Pin']))) + "_DIR")) + reset_pin_inen = str(Database.getSymbolValue('core','PIN_'+ str(extract_pin_num_ID(pin_ID_req=str(Pin_Configuration['_RST']['Pin']))) + "_INEN")) + if (reset_pin_dir == '') or (reset_pin_inen == 'True'): + rnHostRstPinMsg.setLabel(rst_pin_dir_config_msg) + rnHostRstPinMsg.setVisible(True) + reset_pin_flag = True + + if Pin_Configuration['SLP_TR']['Pin'] != '': + reset_pin_dir = str(Database.getSymbolValue('core','PIN_'+ str(extract_pin_num_ID(pin_ID_req=str(Pin_Configuration['SLP_TR']['Pin']))) + "_DIR")) + reset_pin_inen = str(Database.getSymbolValue('core','PIN_'+ str(extract_pin_num_ID(pin_ID_req=str(Pin_Configuration['SLP_TR']['Pin']))) + "_INEN")) + if (reset_pin_dir == '') or (reset_pin_inen == 'True'): + rnHostRstPinMsg.setLabel(rst_pin_dir_config_msg) + rnHostRstPinMsg.setVisible(True) + reset_pin_flag = True + + +def check_update_pins(): + if Pin_Configuration['IRQ']['update'] == True: + rfHostIrqPin.setValue(str(Pin_Configuration['IRQ']['Pin'])) + Pin_Configuration[str('IRQ')].update({'update':False}) + + if Pin_Configuration['CLKM']['update'] == True: + rfHostClkmPin.setValue(str(Pin_Configuration['CLKM']['Pin'])) + Pin_Configuration[str('CLKM')].update({'update':False}) + + if Pin_Configuration['DIG1']['update'] == True: + rfHostDig1Pin.setValue(str(Pin_Configuration['DIG1']['Pin'])) + Pin_Configuration[str('DIG1')].update({'update':False}) + + if Pin_Configuration['DIG2']['update'] == True: + rfHostDig2Pin.setValue(str(Pin_Configuration['DIG2']['Pin'])) + Pin_Configuration[str('DIG2')].update({'update':False}) + + if Pin_Configuration['DIG3']['update'] == True: + rfHostDig3Pin.setValue(str(Pin_Configuration['DIG3']['Pin'])) + Pin_Configuration[str('DIG3')].update({'update':False}) + + if Pin_Configuration['DIG4']['update'] == True: + rfHostDig4Pin.setValue(str(Pin_Configuration['DIG4']['Pin'])) + Pin_Configuration[str('DIG4')].update({'update':False}) + + if Pin_Configuration['_RST']['update'] == True: + rfHost_RstPin.setValue(str(Pin_Configuration['_RST']['Pin'])) + Pin_Configuration[str('_RST')].update({'update':False}) + + if Pin_Configuration['SLP_TR']['update'] == True: + rfHostSlpTrPin.setValue(str(Pin_Configuration['SLP_TR']['Pin'])) + Pin_Configuration[str('SLP_TR')].update({'update':False}) + + #check_gpio_dir() + +def extract_pin_num_ID(pin_num_req = '',pin_ID_req = '',req = 'PIN_NUM'): + print("extract_pin_num_ID") + for pin_num, pin_ID in pin_num_ID_map.items(): + if req == 'PIN_NUM': + if pin_ID_req == pin_ID: + return pin_num + elif req == 'PIN_ID': + if pin_num_req == pin_num: + return pin_ID + + + + + +###################################################################################### + +# Module Dependencies Harmony Callback +######################################################################################################### + +def trxMethodUpdate(symbol, event): + Transceiver_type = event["value"] + file_list_RF233 = [RF233_phy_tx_frame_done_cbC, RF233_phy_taskC, RF233_phy_rx_frame_cbC, RF233_phy_ed_end_cbC, RF233_tfaC, RF233_phy_txC, RF233_phy_rx_enableC, RF233_phy_rxC, RF233_phy_pwr_mgmtC, RF233_phy_pibC, RF233_phy_irq_handlerC, RF233_phy_initC, RF233_phy_helperC, RF233_phy_edC, RF233_phyC, at86rf233H, RF233_phy_txH, RF233_phy_trx_reg_accessC, RF233_phy_trx_reg_accessH, RF233_phy_rxH, RF233_phy_pibH, RF233_phy_irq_handlerH, RF233_phy_internalH, RF233_phy_tasksH, RF233_phy_constantsH, RF233_phy_configH, RF233_ieee_phy_constH, RF233_phyH] + file_list_RF212b = [RF212b_phy_tx_frame_done_cbC, RF212b_phy_taskC, RF212b_phy_rx_frame_cbC, RF212b_phy_ed_end_cbC, RF212b_tfaC, RF212b_phy_txC, RF212b_phy_rx_enableC, RF212b_phy_rxC, RF212b_phy_pwr_mgmtC, RF212b_phy_pibC, RF212b_phy_irq_handlerC, RF212b_phy_initC, RF212b_phy_helperC, RF212b_phy_edC, RF212b_phyC, at86rf212bH, RF212b_phy_txH, RF212b_phy_trx_reg_accessC, RF212b_phy_trx_reg_accessH, RF212b_phy_rxH, RF212b_phy_pibH, RF212b_phy_irq_handlerH, RF212b_phy_internalH, RF212b_phy_tasksH, RF212b_phy_constantsH, RF212b_phy_configH, RF212b_ieee_phy_constH, RF212b_phyH] + if Transceiver_type == "RF233": + print("transceiver = RF233") + for file in range(len(file_list_RF233)): + file_list_RF212b[file].setEnabled(False) + file_list_RF233[file].setEnabled(True) + elif Transceiver_type == "RF212B": + print("transceiver = RF212b") + for file in range(len(file_list_RF212b)): + file_list_RF233[file].setEnabled(False) + file_list_RF212b[file].setEnabled(True) + elif Transceiver_type == "RF215": + # To be implemented + print("transceiver = RF215") + Log.writeErrorMessage("RF215 is currently not supported. To be implemented in the future") + for file in range(len(file_list_RF212b)): + file_list_RF233[file].setEnabled(False) + file_list_RF212b[file].setEnabled(False) + + + + + +def onAttachmentConnected(source, target): + localComponent = source["component"] + remoteComponent = target["component"] + remoteID = remoteComponent.getID() + connectID = source["id"] + targetID = target["id"] + if "SERCOM" in targetID: + rfHostlibSpiSercomType.setValue(targetID) + + +def onAttachmentDisconnected(source, target): + print("SERCOM Attachment Disconnected") + + +def eic_used_callback(synbol, event): + channel_num = event["id"][9:] + if (event["value"]==True): + rfHostlibEicChannelSelected.setValue(channel_num) + elif (event["value"]==False): + rfHostlibEicChannelSelected.setValue("") + + + +##################################################################################### +# Component Generic Harmony API's +##################################################################################### + +def instantiateComponent(rfHostLib): + Log.writeInfoMessage("Initiating RF HOST LIBRARY") + configName = Variables.get("__CONFIGURATION_NAME") + processor = Variables.get("__PROCESSOR") + print("processor", processor) + + requiredComponents = [ + "HarmonyCore", + "sys_time", + "RTOS", + "eic", + "trng", + ] + + res = Database.activateComponents(requiredComponents) + + global rfHostlibSpiSercomType + rfHostlibSpiSercomType = rfHostLib.createStringSymbol("SELECTED_SERCOM", None) + rfHostlibSpiSercomType.setLabel("Selected sercom") + rfHostlibSpiSercomType.setDescription("Selected sercom type") + rfHostlibSpiSercomType.setVisible(False) + + + extIntNode = ATDF.getNode("/avr-tools-device-file/devices/device/peripherals/module@[name=\"EIC\"]/instance@[name=\"EIC\"]/parameters/param@[name=\"EXTINT_NUM\"]") + if (extIntNode is None): + extIntNode = ATDF.getNode("/avr-tools-device-file/devices/device/peripherals/module@[name=\"EIC\"]/instance@[name=\"EIC\"]/parameters/param@[name=\"CHIP_EIC_EXTINT_NUM\"]") + extIntCount = int(extIntNode.getAttribute("value")) + list_of_EicChannel_ID = [] + for extIntIndex in range(0 , extIntCount): + list_of_EicChannel_ID.append("eic.EIC_CHAN_" + str(extIntIndex)) + + + # transceiver selected + global rfHostlibEicChannelSelected + rfHostlibEicChannelSelected = rfHostLib.createStringSymbol("SELECTED_EIC_CHANNEL", None) + rfHostlibEicChannelSelected.setLabel("Eic channel selected") + rfHostlibEicChannelSelected.setDescription("Selected eic channel") + rfHostlibEicChannelSelected.setVisible(False) + rfHostlibEicChannelSelected.setDependencies(eic_used_callback, list_of_EicChannel_ID) + + #rfHostlibSelectTransceiverType + rfHostlibSelectTRX = rfHostLib.createComboSymbol("RF_HOST_SELECT_TRANSEIVER", None, Transceiver_Type_options) + rfHostlibSelectTRX.setLabel("Select Transceiver Type") + rfHostlibSelectTRX.setDescription("Select the TRANSEIVER type") + rfHostlibSelectTRX.setDefaultValue("RF233") + rfHostlibSelectTRX.setDependencies(trxMethodUpdate, ["RF_HOST_SELECT_TRANSEIVER"]) + + + ## GPIO PORT DEPENDENCIES + get_port_pin_dependencies() + + global rnHostPinConfigmenu + rnHostPinConfigmenu = rfHostLib.createMenuSymbol("RN_HOST_LIB_PIN_MENU",None) + rnHostPinConfigmenu.setLabel("Module Pin Selections") + rnHostPinConfigmenu.setDescription("Select the required Pin configuration") + + + global rfHostIrqPin + rfHostIrqPin = rfHostLib.createStringSymbol("RST_PIN_UPDATE",rnHostPinConfigmenu) + rfHostIrqPin.setLabel("Interrupt request pin") + rfHostIrqPin.setReadOnly(True) + rfHostIrqPin.setDependencies(GPIO_Update_Callback,gpio_dependency) + + global rfHostClkmPin + rfHostClkmPin = rfHostLib.createStringSymbol("CLKM_PIN_UPDATE",rnHostPinConfigmenu) + rfHostClkmPin.setLabel("Clock pin") + rfHostClkmPin.setReadOnly(True) + rfHostClkmPin.setDependencies(GPIO_Update_Callback,gpio_dependency) + + global rfHostDig1Pin + rfHostDig1Pin = rfHostLib.createStringSymbol("DIG1_PIN_UPDATE",rnHostPinConfigmenu) + rfHostDig1Pin.setLabel("DIG1 pin") + rfHostDig1Pin.setReadOnly(True) + rfHostDig1Pin.setDependencies(GPIO_Update_Callback,gpio_dependency) + + global rfHostDig2Pin + rfHostDig2Pin = rfHostLib.createStringSymbol("DIG2_PIN_UPDATE",rnHostPinConfigmenu) + rfHostDig2Pin.setLabel("DIG2 pin") + rfHostDig2Pin.setReadOnly(True) + rfHostDig2Pin.setDependencies(GPIO_Update_Callback,gpio_dependency) + + global rfHostDig3Pin + rfHostDig3Pin = rfHostLib.createStringSymbol("DIG3_PIN_UPDATE",rnHostPinConfigmenu) + rfHostDig3Pin.setLabel("DIG3 pin") + rfHostDig3Pin.setReadOnly(True) + rfHostDig3Pin.setDependencies(GPIO_Update_Callback,gpio_dependency) + + global rfHostDig4Pin + rfHostDig4Pin = rfHostLib.createStringSymbol("DIG4_PIN_UPDATE",rnHostPinConfigmenu) + rfHostDig4Pin.setLabel("DIG4 pin") + rfHostDig4Pin.setReadOnly(True) + rfHostDig4Pin.setDependencies(GPIO_Update_Callback,gpio_dependency) + + global rfHost_RstPin + rfHost_RstPin = rfHostLib.createStringSymbol("_RST_PIN_UPDATE",rnHostPinConfigmenu) + rfHost_RstPin.setLabel("Reset pin") + rfHost_RstPin.setReadOnly(True) + rfHost_RstPin.setDependencies(GPIO_Update_Callback,gpio_dependency) + + global rfHostSlpTrPin + rfHostSlpTrPin = rfHostLib.createStringSymbol("SLP_TR_PIN_UPDATE",rnHostPinConfigmenu) + rfHostSlpTrPin.setLabel("Sleep/Transmit_Receive") + rfHostSlpTrPin.setReadOnly(True) + rfHostSlpTrPin.setDependencies(GPIO_Update_Callback,gpio_dependency) + + + global rfHostIrqPinMsg + rfHostIrqPinMsg = rfHostLib.createCommentSymbol(None,rfHostIrqPin) + rfHostIrqPinMsg.setVisible(True) + rfHostIrqPinMsg.setLabel(irq_pin_config_msg) + + global rfHostClkmPinMsg + rfHostClkmPinMsg = rfHostLib.createCommentSymbol(None,rfHostClkmPin) + rfHostClkmPinMsg.setVisible(True) + rfHostClkmPinMsg.setLabel(clkm_pin_config_msg) + + global rfHostDig1PinMsg + rfHostDig1PinMsg = rfHostLib.createCommentSymbol(None,rfHostDig1Pin) + rfHostDig1PinMsg.setVisible(True) + rfHostDig1PinMsg.setLabel(dig1_pin_config_msg) + + global rfHostDig2PinMsg + rfHostDig2PinMsg = rfHostLib.createCommentSymbol(None,rfHostDig2Pin) + rfHostDig2PinMsg.setVisible(True) + rfHostDig2PinMsg.setLabel(dig2_pin_config_msg) + + global rfHostDig3PinMsg + rfHostDig3PinMsg = rfHostLib.createCommentSymbol(None,rfHostDig3Pin) + rfHostDig3PinMsg.setVisible(True) + rfHostDig3PinMsg.setLabel(dig3_pin_config_msg) + + global rfHostDig4PinMsg + rfHostDig4PinMsg = rfHostLib.createCommentSymbol(None,rfHostDig4Pin) + rfHostDig4PinMsg.setVisible(True) + rfHostDig4PinMsg.setLabel(dig4_pin_config_msg) + + global rfHostSlptrPinMsg + rfHostSlptrPinMsg = rfHostLib.createCommentSymbol(None,rfHostSlpTrPin) + rfHostSlptrPinMsg.setVisible(True) + rfHostSlptrPinMsg.setLabel(slp_tr_pin_config_msg) + + global rfHostRstPinMsg + rfHostRstPinMsg = rfHostLib.createCommentSymbol(None,rfHost_RstPin) + rfHostRstPinMsg.setVisible(True) + rfHostRstPinMsg.setLabel(rst_pin_config_msg) + + + + global rfHostBufferConfigmenu + rfHostBufferConfigmenu = rfHostLib.createMenuSymbol("BMM_BUFFER", None) + rfHostBufferConfigmenu.setLabel("Buffer Configuration") + rfHostBufferConfigmenu.setDescription("PHY Buffer configuration") + + global phyIntegerBmmLargeBuffers + phyIntegerBmmLargeBuffers = rfHostLib.createIntegerSymbol("PHY_INTEGER_BMMLARGEBUFFERS", rfHostBufferConfigmenu) + phyIntegerBmmLargeBuffers.setLabel("Large Buffers") + phyIntegerBmmLargeBuffers.setMin(3) + phyIntegerBmmLargeBuffers.setMax(50) + phyIntegerBmmLargeBuffers.setDefaultValue(3) + + global phyIntegerBmmSmallBuffers + phyIntegerBmmSmallBuffers = rfHostLib.createIntegerSymbol("PHY_INTEGER_BMMSMALLBUFFERS", rfHostBufferConfigmenu) + phyIntegerBmmSmallBuffers.setLabel("Small Buffers") + phyIntegerBmmSmallBuffers.setMin(3) + phyIntegerBmmSmallBuffers.setMax(50) + phyIntegerBmmSmallBuffers.setDefaultValue(3) + + #definitions + global rfSystemDefFile + rfSystemDefFile = rfHostLib.createFileSymbol("RFPHY_DEFINITIONS", None) + rfSystemDefFile.setType("STRING") + rfSystemDefFile.setOutputName("core.LIST_SYSTEM_DEFINITIONS_H_EXTERNS") + rfSystemDefFile.setSourcePath("driver/templates/common/RFPHY_definitions.h.ftl") + rfSystemDefFile.setOverwrite(True) + rfSystemDefFile.setMarkup(True) + + + #initialization + global phyInitFile + phyInitFile = rfHostLib.createFileSymbol("PHY_INIT", None) + phyInitFile.setType("STRING") + phyInitFile.setOutputName("core.LIST_SYSTEM_INIT_INTERRUPTS") + phyInitFile.setSourcePath("driver/templates/common/phy_initialize.c.ftl") + phyInitFile.setMarkup(True) + + global semHandleInitFile + semHandleInitFile = rfHostLib.createFileSymbol('OSAM_SEM_HANDLE_INIT', None) + semHandleInitFile.setType('STRING') + semHandleInitFile.setOutputName('core.LIST_SYSTEM_INIT_C_LIBRARY_INITIALIZATION_DATA') + semHandleInitFile.setSourcePath('driver/templates/common/sem_handle_init.c.ftl') + semHandleInitFile.setMarkup(True) + + global semCreateInitFile + semCreateInitFile = rfHostLib.createFileSymbol("OSAL_SEM_CREATE_INIT", None) + semCreateInitFile.setType("STRING") + semCreateInitFile.setOutputName("core.LIST_SYSTEM_INIT_C_INITIALIZE_SYSTEM_SERVICES") + semCreateInitFile.setSourcePath("driver/templates/common/sem_createInit.c.ftl") + semCreateInitFile.setMarkup(True) + + global phyTasksDefC + phyTasksDefC = rfHostLib.createFileSymbol('PHY_TASK_INITIALIZATION_C', None) + phyTasksDefC.setType('STRING') + phyTasksDefC.setOutputName('core.LIST_SYSTEM_RTOS_TASKS_C_DEFINITIONS') + phyTasksDefC.setSourcePath('driver/templates/common/phy_task_def.c.ftl') + phyTasksDefC.setMarkup(True) + + global phyTasksC + phyTasksC = rfHostLib.createFileSymbol('PHY_TASKS_C', None) + phyTasksC.setType('STRING') + phyTasksC.setOutputName('core.LIST_SYSTEM_TASKS_C_CALL_LIB_TASKS') + phyTasksC.setSourcePath('driver/templates/common/phy_task.c.ftl') + phyTasksC.setMarkup(True) + + + + #app.h + global rfAppH + rfAppH = rfHostLib.createFileSymbol(None, None) + rfAppH.setSourcePath('driver/templates/common/app.h.ftl') + rfAppH.setOutputName('app.h') + rfAppH.setOverwrite(True) + rfAppH.setDestPath('../../') + rfAppH.setProjectPath('') + rfAppH.setType('HEADER') + rfAppH.setMarkup(True) + rfAppH.setEnabled(True) + + phyConfHeader = rfHostLib.createFileSymbol("PHY_CONF_HEADER", None) + phyConfHeader.setSourcePath("/driver/templates/common/stack_config.h.ftl") + phyConfHeader.setOutputName("stack_config.h") + phyConfHeader.setDestPath('../../') + phyConfHeader.setProjectPath('') + phyConfHeader.setType("HEADER") + phyConfHeader.setOverwrite(True) + phyConfHeader.setMarkup(True) + phyConfHeader.setEnabled(True) + + phyConfHeader = rfHostLib.createFileSymbol("APP_CONF_HEADER", None) + phyConfHeader.setSourcePath("/driver/templates/common/app_config.h.ftl") + phyConfHeader.setOutputName("app_config.h") + phyConfHeader.setDestPath('../../') + phyConfHeader.setProjectPath('') + phyConfHeader.setType("HEADER") + phyConfHeader.setOverwrite(True) + phyConfHeader.setMarkup(True) + phyConfHeader.setEnabled(True) + + #Add Framework_defs.h + HeaderFile = rfHostLib.createFileSymbol(None, None) + HeaderFile.setSourcePath('driver/software/app_fw//framework_defs.h') + HeaderFile.setOutputName('framework_defs.h') + HeaderFile.setOverwrite(True) + HeaderFile.setDestPath('') + HeaderFile.setProjectPath('config/' + configName) + HeaderFile.setType('HEADER') + HeaderFile.setEnabled(True) + + # Add osal_freertos_extend.h + global freeRtosExtendH + freeRtosExtendH = rfHostLib.createFileSymbol(None, None) + freeRtosExtendH.setSourcePath('driver/software/app_fw/osal/osal_freertos_extend.h') + freeRtosExtendH.setOutputName('osal_freertos_extend.h') + freeRtosExtendH.setOverwrite(True) + freeRtosExtendH.setDestPath('/osal') + freeRtosExtendH.setProjectPath('config/' + configName + '/osal/') + freeRtosExtendH.setType('HEADER') + freeRtosExtendH.setEnabled(True) + + # Add osal_freertos_extend.c + global freeRtosExtendC + freeRtosExtendC = rfHostLib.createFileSymbol(None, None) + freeRtosExtendC.setSourcePath("driver/software/app_fw/osal/osal_freertos_extend.c") + freeRtosExtendC.setOutputName('osal_freertos_extend.c') + freeRtosExtendC.setOverwrite(True) + freeRtosExtendC.setDestPath('/osal') + freeRtosExtendC.setProjectPath('config/' + configName + '/osal/') + freeRtosExtendC.setType('SOURCE') + freeRtosExtendC.setEnabled(True) + + + #Add pal related files + global palH + palH = rfHostLib.createFileSymbol("pal_H", None) + palH.setSourcePath("driver/templates/common/pal.h.ftl") + palH.setOutputName("pal.h") + palH.setDestPath("driver/IEEE_802154_PHY/pal/inc/") + palH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/pal/inc/") + palH.setType("HEADER") + palH.setOverwrite(True) + palH.setMarkup(True) + + global palC + palC = rfHostLib.createFileSymbol("pal_C", None) + palC.setSourcePath("driver/software/pal/src/pal.c") + palC.setOutputName("pal.c") + palC.setDestPath("driver/IEEE_802154_PHY/pal/src/") + palC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/pal/src/") + palC.setType("SOURCE") + palC.setOverwrite(True) + + #Add resource related files + global bmmH + bmmH = rfHostLib.createFileSymbol("bmm_H", None) + bmmH.setSourcePath("driver/software/resources/buffer/inc/bmm.h") + bmmH.setOutputName("bmm.h") + bmmH.setDestPath("driver/IEEE_802154_PHY/resources/buffer/inc/") + bmmH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/resources/buffer/inc/") + bmmH.setType("HEADER") + bmmH.setOverwrite(True) + + global bmmC + bmmC = rfHostLib.createFileSymbol("bmm_C", None) + bmmC.setSourcePath("driver/software/resources/buffer/src/bmm.c") + bmmC.setOutputName("bmm.c") + bmmC.setDestPath("driver/IEEE_802154_PHY/resources/buffer/src/") + bmmC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/resources/buffer/src/") + bmmC.setType("SOURCE") + bmmC.setOverwrite(True) + + + global qmmH + qmmH = rfHostLib.createFileSymbol("qmm_H", None) + qmmH.setSourcePath("driver/software/resources/queue/inc/qmm.h") + qmmH.setOutputName("qmm.h") + qmmH.setDestPath("driver/IEEE_802154_PHY/resources/queue/inc/") + qmmH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/resources/queue/inc/") + qmmH.setType("HEADER") + qmmH.setOverwrite(True) + + global qmmC + qmmC = rfHostLib.createFileSymbol("qmm_C", None) + qmmC.setSourcePath("driver/software/resources/queue/src/qmm.c") + qmmC.setOutputName("qmm.c") + qmmC.setDestPath("driver/IEEE_802154_PHY/resources/queue/src/") + qmmC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/resources/queue/src/") + qmmC.setType("SOURCE") + qmmC.setOverwrite(True) + + + #Add RF233 phy related files + global RF233_phyH + RF233_phyH = rfHostLib.createFileSymbol("RF233_phy_H", None) + RF233_phyH.setSourcePath("driver/software/RF233/phy/inc/phy.h") + RF233_phyH.setOutputName("phy.h") + RF233_phyH.setDestPath("driver/IEEE_802154_PHY/phy/inc/") + RF233_phyH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/inc/") + RF233_phyH.setType("HEADER") + RF233_phyH.setOverwrite(True) + + global RF233_ieee_phy_constH + RF233_ieee_phy_constH = rfHostLib.createFileSymbol("RF233_ieee_phy_const_H", None) + RF233_ieee_phy_constH.setSourcePath("driver/software/RF233/phy/inc/ieee_phy_const.h") + RF233_ieee_phy_constH.setOutputName("ieee_phy_const.h") + RF233_ieee_phy_constH.setDestPath("driver/IEEE_802154_PHY/phy/inc/") + RF233_ieee_phy_constH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/inc/") + RF233_ieee_phy_constH.setType("HEADER") + RF233_ieee_phy_constH.setOverwrite(True) + + global RF233_phy_configH + RF233_phy_configH = rfHostLib.createFileSymbol("RF233_phy_config_H", None) + RF233_phy_configH.setSourcePath("driver/software/RF233/phy/inc/phy_config.h") + RF233_phy_configH.setOutputName("phy_config.h") + RF233_phy_configH.setDestPath("driver/IEEE_802154_PHY/phy/inc/") + RF233_phy_configH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/inc/") + RF233_phy_configH.setType("HEADER") + RF233_phy_configH.setOverwrite(True) + + global RF233_phy_constantsH + RF233_phy_constantsH = rfHostLib.createFileSymbol("RF233_phy_constants_H", None) + RF233_phy_constantsH.setSourcePath("driver/software/RF233/phy/inc/phy_constants.h") + RF233_phy_constantsH.setOutputName("phy_constants.h") + RF233_phy_constantsH.setDestPath("driver/IEEE_802154_PHY/phy/inc/") + RF233_phy_constantsH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/inc/") + RF233_phy_constantsH.setType("HEADER") + RF233_phy_constantsH.setOverwrite(True) + + global RF233_phy_tasksH + RF233_phy_tasksH = rfHostLib.createFileSymbol("RF233_phy_tasks_H", None) + RF233_phy_tasksH.setSourcePath("driver/software/RF233/phy/inc/phy_tasks.h") + RF233_phy_tasksH.setOutputName("phy_tasks.h") + RF233_phy_tasksH.setDestPath("driver/IEEE_802154_PHY/phy/inc/") + RF233_phy_tasksH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/inc/") + RF233_phy_tasksH.setType("HEADER") + RF233_phy_tasksH.setOverwrite(True) + + global RF233_phy_internalH + RF233_phy_internalH = rfHostLib.createFileSymbol("RF233_phy_internal_H", None) + RF233_phy_internalH.setSourcePath("driver/software/RF233/phy/at86rf233/inc/phy_internal.h") + RF233_phy_internalH.setOutputName("phy_internal.h") + RF233_phy_internalH.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF233_phy_internalH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF233_phy_internalH.setType("HEADER") + RF233_phy_internalH.setOverwrite(True) + + global RF233_phy_irq_handlerH + RF233_phy_irq_handlerH = rfHostLib.createFileSymbol("RF233_phy_irq_handler_H", None) + RF233_phy_irq_handlerH.setSourcePath("driver/software/RF233/phy/at86rf233/inc/phy_irq_handler.h") + RF233_phy_irq_handlerH.setOutputName("phy_irq_handler.h") + RF233_phy_irq_handlerH.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF233_phy_irq_handlerH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF233_phy_irq_handlerH.setType("HEADER") + RF233_phy_irq_handlerH.setOverwrite(True) + + global RF233_phy_pibH + RF233_phy_pibH = rfHostLib.createFileSymbol("RF233_phy_pib_H", None) + RF233_phy_pibH.setSourcePath("driver/software/RF233/phy/at86rf233/inc/phy_pib.h") + RF233_phy_pibH.setOutputName("phy_pib.h") + RF233_phy_pibH.setDestPath("driver/IEEE_802154_PHY\phy/at86rf/inc/") + RF233_phy_pibH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY\phy/at86rf/inc/") + RF233_phy_pibH.setType("HEADER") + RF233_phy_pibH.setOverwrite(True) + + global RF233_phy_rxH + RF233_phy_rxH = rfHostLib.createFileSymbol("RF233_phy_rx_H", None) + RF233_phy_rxH.setSourcePath("driver/software/RF233/phy/at86rf233/inc/phy_rx.h") + RF233_phy_rxH.setOutputName("phy_rx.h") + RF233_phy_rxH.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF233_phy_rxH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF233_phy_rxH.setType("HEADER") + RF233_phy_rxH.setOverwrite(True) + + + global RF233_phy_trx_reg_accessH + RF233_phy_trx_reg_accessH = rfHostLib.createFileSymbol("RF233_phy_trx_reg_access_H", None) + RF233_phy_trx_reg_accessH.setSourcePath("driver/templates/RF233/phy_trx_reg_access.h.ftl") + RF233_phy_trx_reg_accessH.setOutputName("phy_trx_reg_access.h") + RF233_phy_trx_reg_accessH.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF233_phy_trx_reg_accessH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF233_phy_trx_reg_accessH.setType("HEADER") + RF233_phy_trx_reg_accessH.setMarkup(True) + + + + global RF233_phy_txH + RF233_phy_txH = rfHostLib.createFileSymbol("RF233_phy_tx_H", None) + RF233_phy_txH.setSourcePath("driver/software/RF233/phy/at86rf233/inc/phy_tx.h") + RF233_phy_txH.setOutputName("phy_tx.h") + RF233_phy_txH.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF233_phy_txH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF233_phy_txH.setType("HEADER") + RF233_phy_txH.setOverwrite(True) + + global at86rf233H + at86rf233H = rfHostLib.createFileSymbol("at86rf233_H", None) + at86rf233H.setSourcePath("driver/software/RF233/phy/at86rf233/inc/AT86RF233.h") + at86rf233H.setOutputName("at86rf.h") + at86rf233H.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/inc/") + at86rf233H.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/inc/") + at86rf233H.setType("HEADER") + at86rf233H.setOverwrite(True) + + + global RF233_phyC + RF233_phyC = rfHostLib.createFileSymbol("RF233_phy_C", None) + RF233_phyC.setSourcePath("driver/templates/RF233/phy.c.ftl") + RF233_phyC.setOutputName("phy.c") + RF233_phyC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phyC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phyC.setType("SOURCE") + RF233_phyC.setOverwrite(True) + RF233_phyC.setMarkup(True) + + global RF233_phy_edC + RF233_phy_edC = rfHostLib.createFileSymbol("RF233_phy_ed_C", None) + RF233_phy_edC.setSourcePath("driver/software/RF233/phy/at86rf233/src/phy_ed.c") + RF233_phy_edC.setOutputName("phy_ed.c") + RF233_phy_edC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_edC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_edC.setType("SOURCE") + RF233_phy_edC.setOverwrite(True) + + global RF233_phy_helperC + RF233_phy_helperC = rfHostLib.createFileSymbol("RF233_phy_helper_C", None) + RF233_phy_helperC.setSourcePath("driver/software/RF233/phy/at86rf233/src/phy_helper.c") + RF233_phy_helperC.setOutputName("phy_helper.c") + RF233_phy_helperC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_helperC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_helperC.setType("SOURCE") + RF233_phy_helperC.setOverwrite(True) + + global RF233_phy_initC + RF233_phy_initC = rfHostLib.createFileSymbol("RF233_phy_init_C", None) + RF233_phy_initC.setSourcePath("driver/templates/RF233/phy_init.c.ftl") + RF233_phy_initC.setOutputName("phy_init.c") + RF233_phy_initC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_initC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_initC.setType("SOURCE") + RF233_phy_initC.setOverwrite(True) + RF233_phy_initC.setMarkup(True) + + global RF233_phy_irq_handlerC + RF233_phy_irq_handlerC = rfHostLib.createFileSymbol("RF233_phy_irq_handler_C", None) + RF233_phy_irq_handlerC.setSourcePath("driver/software/RF233/phy/at86rf233/src/phy_irq_handler.c") + RF233_phy_irq_handlerC.setOutputName("phy_irq_handler.c") + RF233_phy_irq_handlerC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_irq_handlerC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_irq_handlerC.setType("SOURCE") + RF233_phy_irq_handlerC.setOverwrite(True) + + global RF233_phy_trx_reg_accessC + RF233_phy_trx_reg_accessC = rfHostLib.createFileSymbol("RF233_phy_trx_reg_access_C", None) + RF233_phy_trx_reg_accessC.setSourcePath("driver/templates/RF233/phy_trx_reg_access.c.ftl") + RF233_phy_trx_reg_accessC.setOutputName("phy_trx_reg_access.c") + RF233_phy_trx_reg_accessC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_trx_reg_accessC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_trx_reg_accessC.setType("SOURCE") + RF233_phy_trx_reg_accessC.setOverwrite(True) + RF233_phy_trx_reg_accessC.setMarkup(True) + + global RF233_phy_pibC + RF233_phy_pibC = rfHostLib.createFileSymbol("RF233_phy_pib_C", None) + RF233_phy_pibC.setSourcePath("driver/software/RF233/phy/at86rf233/src/phy_pib.c") + RF233_phy_pibC.setOutputName("phy_pib.c") + RF233_phy_pibC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_pibC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_pibC.setType("SOURCE") + RF233_phy_pibC.setOverwrite(True) + + global RF233_phy_pwr_mgmtC + RF233_phy_pwr_mgmtC = rfHostLib.createFileSymbol("RF233_phy_pwr_mgmt_C", None) + RF233_phy_pwr_mgmtC.setSourcePath("driver/software/RF233/phy/at86rf233/src/phy_pwr_mgmt.c") + RF233_phy_pwr_mgmtC.setOutputName("phy_pwr_mgmt.c") + RF233_phy_pwr_mgmtC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_pwr_mgmtC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_pwr_mgmtC.setType("SOURCE") + RF233_phy_pwr_mgmtC.setOverwrite(True) + + global RF233_phy_rxC + RF233_phy_rxC = rfHostLib.createFileSymbol("RF233_phy_rx_C", None) + RF233_phy_rxC.setSourcePath("driver/software/RF233/phy/at86rf233/src/phy_rx.c") + RF233_phy_rxC.setOutputName("phy_rx.c") + RF233_phy_rxC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_rxC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_rxC.setType("SOURCE") + RF233_phy_rxC.setOverwrite(True) + + global RF233_phy_rx_enableC + RF233_phy_rx_enableC = rfHostLib.createFileSymbol("RF233_phy_rx_enable_C", None) + RF233_phy_rx_enableC.setSourcePath("driver/software/RF233/phy/at86rf233/src/phy_rx_enable.c") + RF233_phy_rx_enableC.setOutputName("phy_rx_enable.c") + RF233_phy_rx_enableC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_rx_enableC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_rx_enableC.setType("SOURCE") + RF233_phy_rx_enableC.setOverwrite(True) + + + global RF233_phy_txC + RF233_phy_txC = rfHostLib.createFileSymbol("RF233_phy_tx_C", None) + RF233_phy_txC.setSourcePath("driver/software/RF233/phy/at86rf233/src/phy_tx.c") + RF233_phy_txC.setOutputName("phy_tx.c") + RF233_phy_txC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_txC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_phy_txC.setType("SOURCE") + RF233_phy_txC.setOverwrite(True) + + global RF233_tfaC + RF233_tfaC = rfHostLib.createFileSymbol("RF233_tfa_C", None) + RF233_tfaC.setSourcePath("driver/software/RF233/phy/at86rf233/src/tfa.c") + RF233_tfaC.setOutputName("tfa.c") + RF233_tfaC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_tfaC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF233_tfaC.setType("SOURCE") + RF233_tfaC.setOverwrite(True) + + global RF233_phy_ed_end_cbC + RF233_phy_ed_end_cbC = rfHostLib.createFileSymbol("RF233_phy_ed_end_cb_C", None) + RF233_phy_ed_end_cbC.setSourcePath("driver/software/RF233/phy/src/phy_ed_end_cb.c") + RF233_phy_ed_end_cbC.setOutputName("phy_ed_end_cb.c") + RF233_phy_ed_end_cbC.setDestPath("driver/IEEE_802154_PHY/phy/src/") + RF233_phy_ed_end_cbC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/src/") + RF233_phy_ed_end_cbC.setType("SOURCE") + RF233_phy_ed_end_cbC.setOverwrite(True) + + global RF233_phy_rx_frame_cbC + RF233_phy_rx_frame_cbC = rfHostLib.createFileSymbol("RF233_phy_rx_frame_cb_C", None) + RF233_phy_rx_frame_cbC.setSourcePath("driver/software/RF233/phy/src/phy_rx_frame_cb.c") + RF233_phy_rx_frame_cbC.setOutputName("phy_rx_frame_cb.c") + RF233_phy_rx_frame_cbC.setDestPath("driver/IEEE_802154_PHY/phy/src/") + RF233_phy_rx_frame_cbC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/src/") + RF233_phy_rx_frame_cbC.setType("SOURCE") + RF233_phy_rx_frame_cbC.setOverwrite(True) + + global RF233_phy_taskC + RF233_phy_taskC = rfHostLib.createFileSymbol("RF233_phy_task_C", None) + RF233_phy_taskC.setSourcePath("driver/software/RF233/phy/src/phy_task.c") + RF233_phy_taskC.setOutputName("phy_task.c") + RF233_phy_taskC.setDestPath("driver/IEEE_802154_PHY/phy/src/") + RF233_phy_taskC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/src/") + RF233_phy_taskC.setType("SOURCE") + RF233_phy_taskC.setOverwrite(True) + + global RF233_phy_tx_frame_done_cbC + RF233_phy_tx_frame_done_cbC = rfHostLib.createFileSymbol("RF233_phy_tx_frame_done_cb_C", None) + RF233_phy_tx_frame_done_cbC.setSourcePath("driver/software/RF233/phy/src/phy_tx_frame_done_cb.c") + RF233_phy_tx_frame_done_cbC.setOutputName("phy_tx_frame_done_cb.c") + RF233_phy_tx_frame_done_cbC.setDestPath("driver/IEEE_802154_PHY/phy/src/") + RF233_phy_tx_frame_done_cbC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/src/") + RF233_phy_tx_frame_done_cbC.setType("SOURCE") + RF233_phy_tx_frame_done_cbC.setOverwrite(True) + + + + + + #Add RF212b phy related files + global RF212b_phyH + RF212b_phyH = rfHostLib.createFileSymbol("RF212b_phy_H", None) + RF212b_phyH.setSourcePath("driver/software/RF212b/phy/inc/phy.h") + RF212b_phyH.setOutputName("phy.h") + RF212b_phyH.setDestPath("driver/IEEE_802154_PHY/phy/inc/") + RF212b_phyH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/inc/") + RF212b_phyH.setType("HEADER") + RF212b_phyH.setOverwrite(True) + RF212b_phyH.setEnabled(False) + + global RF212b_ieee_phy_constH + RF212b_ieee_phy_constH = rfHostLib.createFileSymbol("RF212b_ieee_phy_const_H", None) + RF212b_ieee_phy_constH.setSourcePath("driver/software/RF212b/phy/inc/ieee_phy_const.h") + RF212b_ieee_phy_constH.setOutputName("ieee_phy_const.h") + RF212b_ieee_phy_constH.setDestPath("driver/IEEE_802154_PHY/phy/inc/") + RF212b_ieee_phy_constH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/inc/") + RF212b_ieee_phy_constH.setType("HEADER") + RF212b_ieee_phy_constH.setOverwrite(True) + RF212b_ieee_phy_constH.setEnabled(False) + + global RF212b_phy_configH + RF212b_phy_configH = rfHostLib.createFileSymbol("RF212b_phy_config_H", None) + RF212b_phy_configH.setSourcePath("driver/software/RF212b/phy/inc/phy_config.h") + RF212b_phy_configH.setOutputName("phy_config.h") + RF212b_phy_configH.setDestPath("driver/IEEE_802154_PHY/phy/inc/") + RF212b_phy_configH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/inc/") + RF212b_phy_configH.setType("HEADER") + RF212b_phy_configH.setOverwrite(True) + RF212b_phy_configH.setEnabled(False) + + global RF212b_phy_constantsH + RF212b_phy_constantsH = rfHostLib.createFileSymbol("RF212b_phy_constants_H", None) + RF212b_phy_constantsH.setSourcePath("driver/software/RF212b/phy/inc/phy_constants.h") + RF212b_phy_constantsH.setOutputName("phy_constants.h") + RF212b_phy_constantsH.setDestPath("driver/IEEE_802154_PHY/phy/inc/") + RF212b_phy_constantsH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/inc/") + RF212b_phy_constantsH.setType("HEADER") + RF212b_phy_constantsH.setOverwrite(True) + RF212b_phy_constantsH.setEnabled(False) + + global RF212b_phy_tasksH + RF212b_phy_tasksH = rfHostLib.createFileSymbol("RF212b_phy_tasks_H", None) + RF212b_phy_tasksH.setSourcePath("driver/software/RF212b/phy/inc/phy_tasks.h") + RF212b_phy_tasksH.setOutputName("phy_tasks.h") + RF212b_phy_tasksH.setDestPath("driver/IEEE_802154_PHY/phy/inc/") + RF212b_phy_tasksH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/inc/") + RF212b_phy_tasksH.setType("HEADER") + RF212b_phy_tasksH.setOverwrite(True) + RF212b_phy_tasksH.setEnabled(False) + + global RF212b_phy_internalH + RF212b_phy_internalH = rfHostLib.createFileSymbol("RF212b_phy_internal_H", None) + RF212b_phy_internalH.setSourcePath("driver/software/RF212b/phy/at86rf212b/inc/phy_internal.h") + RF212b_phy_internalH.setOutputName("phy_internal.h") + RF212b_phy_internalH.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF212b_phy_internalH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF212b_phy_internalH.setType("HEADER") + RF212b_phy_internalH.setOverwrite(True) + RF212b_phy_internalH.setEnabled(False) + + global RF212b_phy_irq_handlerH + RF212b_phy_irq_handlerH = rfHostLib.createFileSymbol("RF212b_phy_irq_handler_H", None) + RF212b_phy_irq_handlerH.setSourcePath("driver/software/RF212b/phy/at86rf212b/inc/phy_irq_handler.h") + RF212b_phy_irq_handlerH.setOutputName("phy_irq_handler.h") + RF212b_phy_irq_handlerH.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF212b_phy_irq_handlerH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF212b_phy_irq_handlerH.setType("HEADER") + RF212b_phy_irq_handlerH.setOverwrite(True) + RF212b_phy_irq_handlerH.setEnabled(False) + + global RF212b_phy_pibH + RF212b_phy_pibH = rfHostLib.createFileSymbol("RF212b_phy_pib_H", None) + RF212b_phy_pibH.setSourcePath("driver/software/RF212b/phy/at86rf212b/inc/phy_pib.h") + RF212b_phy_pibH.setOutputName("phy_pib.h") + RF212b_phy_pibH.setDestPath("driver/IEEE_802154_PHY\phy/at86rf/inc/") + RF212b_phy_pibH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF212b_phy_pibH.setType("HEADER") + RF212b_phy_pibH.setOverwrite(True) + RF212b_phy_pibH.setEnabled(False) + + global RF212b_phy_rxH + RF212b_phy_rxH = rfHostLib.createFileSymbol("RF212b_phy_rx_H", None) + RF212b_phy_rxH.setSourcePath("driver/software/RF212b/phy/at86rf212b/inc/phy_rx.h") + RF212b_phy_rxH.setOutputName("phy_rx.h") + RF212b_phy_rxH.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF212b_phy_rxH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF212b_phy_rxH.setType("HEADER") + RF212b_phy_rxH.setOverwrite(True) + RF212b_phy_rxH.setEnabled(False) + + + global RF212b_phy_trx_reg_accessH + RF212b_phy_trx_reg_accessH = rfHostLib.createFileSymbol("RF212b_phy_trx_reg_access_H", None) + RF212b_phy_trx_reg_accessH.setSourcePath("driver/templates/RF212b/phy_trx_reg_access.h.ftl") + RF212b_phy_trx_reg_accessH.setOutputName("phy_trx_reg_access.h") + RF212b_phy_trx_reg_accessH.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF212b_phy_trx_reg_accessH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF212b_phy_trx_reg_accessH.setType("HEADER") + RF212b_phy_trx_reg_accessH.setMarkup(True) + RF212b_phy_trx_reg_accessH.setEnabled(False) + + + + global RF212b_phy_txH + RF212b_phy_txH = rfHostLib.createFileSymbol("RF212b_phy_tx_H", None) + RF212b_phy_txH.setSourcePath("driver/software/RF212b/phy/at86rf212b/inc/phy_tx.h") + RF212b_phy_txH.setOutputName("phy_tx.h") + RF212b_phy_txH.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF212b_phy_txH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/inc/") + RF212b_phy_txH.setType("HEADER") + RF212b_phy_txH.setOverwrite(True) + RF212b_phy_txH.setEnabled(False) + + + + global at86rf212bH + at86rf212bH = rfHostLib.createFileSymbol("RF212b_at86rf212b_H", None) + at86rf212bH.setSourcePath("driver/software/RF212b/phy/at86rf212b/inc/AT86RF212b.h") + at86rf212bH.setOutputName("at86rf.h") + at86rf212bH.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/inc/") + at86rf212bH.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/inc/") + at86rf212bH.setType("HEADER") + at86rf212bH.setOverwrite(True) + at86rf212bH.setEnabled(False) + + + + global RF212b_phyC + RF212b_phyC = rfHostLib.createFileSymbol("RF212b_phy_C", None) + RF212b_phyC.setSourcePath("driver/templates/RF212b/phy.c.ftl") + RF212b_phyC.setOutputName("phy.c") + RF212b_phyC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phyC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phyC.setType("SOURCE") + RF212b_phyC.setOverwrite(True) + RF212b_phyC.setMarkup(True) + RF212b_phyC.setEnabled(False) + + global RF212b_phy_edC + RF212b_phy_edC = rfHostLib.createFileSymbol("RF212b_phy_ed_C", None) + RF212b_phy_edC.setSourcePath("driver/software/RF212b/phy/at86rf212b/src/phy_ed.c") + RF212b_phy_edC.setOutputName("phy_ed.c") + RF212b_phy_edC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_edC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_edC.setType("SOURCE") + RF212b_phy_edC.setOverwrite(True) + RF212b_phy_edC.setEnabled(False) + + global RF212b_phy_helperC + RF212b_phy_helperC = rfHostLib.createFileSymbol("RF212b_phy_helper_C", None) + RF212b_phy_helperC.setSourcePath("driver/software/RF212b/phy/at86rf212b/src/phy_helper.c") + RF212b_phy_helperC.setOutputName("phy_helper.c") + RF212b_phy_helperC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_helperC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_helperC.setType("SOURCE") + RF212b_phy_helperC.setOverwrite(True) + RF212b_phy_helperC.setEnabled(False) + + global RF212b_phy_initC + RF212b_phy_initC = rfHostLib.createFileSymbol("RF212b_phy_init_C", None) + RF212b_phy_initC.setSourcePath("driver/templates/RF212b/phy_init.c.ftl") + RF212b_phy_initC.setOutputName("phy_init.c") + RF212b_phy_initC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_initC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_initC.setType("SOURCE") + RF212b_phy_initC.setOverwrite(True) + RF212b_phy_initC.setMarkup(True) + RF212b_phy_initC.setEnabled(False) + + global RF212b_phy_irq_handlerC + RF212b_phy_irq_handlerC = rfHostLib.createFileSymbol("RF212b_phy_irq_handler_C", None) + RF212b_phy_irq_handlerC.setSourcePath("driver/software/RF212b/phy/at86rf212b/src/phy_irq_handler.c") + RF212b_phy_irq_handlerC.setOutputName("phy_irq_handler.c") + RF212b_phy_irq_handlerC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_irq_handlerC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_irq_handlerC.setType("SOURCE") + RF212b_phy_irq_handlerC.setOverwrite(True) + RF212b_phy_irq_handlerC.setEnabled(False) + + global RF212b_phy_trx_reg_accessC + RF212b_phy_trx_reg_accessC = rfHostLib.createFileSymbol("RF212b_phy_trx_reg_access_C", None) + RF212b_phy_trx_reg_accessC.setSourcePath("driver/templates/RF212b/phy_trx_reg_access.c.ftl") + RF212b_phy_trx_reg_accessC.setOutputName("phy_trx_reg_access.c") + RF212b_phy_trx_reg_accessC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_trx_reg_accessC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_trx_reg_accessC.setType("SOURCE") + RF212b_phy_trx_reg_accessC.setOverwrite(True) + RF212b_phy_trx_reg_accessC.setMarkup(True) + RF212b_phy_trx_reg_accessC.setEnabled(False) + + global RF212b_phy_pibC + RF212b_phy_pibC = rfHostLib.createFileSymbol("RF212b_phy_pib_C", None) + RF212b_phy_pibC.setSourcePath("driver/software/RF212b/phy/at86rf212b/src/phy_pib.c") + RF212b_phy_pibC.setOutputName("phy_pib.c") + RF212b_phy_pibC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_pibC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_pibC.setType("SOURCE") + RF212b_phy_pibC.setOverwrite(True) + RF212b_phy_pibC.setEnabled(False) + + global RF212b_phy_pwr_mgmtC + RF212b_phy_pwr_mgmtC = rfHostLib.createFileSymbol("RF212b_phy_pwr_mgmt_C", None) + RF212b_phy_pwr_mgmtC.setSourcePath("driver/software/RF212b/phy/at86rf212b/src/phy_pwr_mgmt.c") + RF212b_phy_pwr_mgmtC.setOutputName("phy_pwr_mgmt.c") + RF212b_phy_pwr_mgmtC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_pwr_mgmtC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_pwr_mgmtC.setType("SOURCE") + RF212b_phy_pwr_mgmtC.setOverwrite(True) + RF212b_phy_pwr_mgmtC.setEnabled(False) + + global RF212b_phy_rxC + RF212b_phy_rxC = rfHostLib.createFileSymbol("RF212b_phy_rx_C", None) + RF212b_phy_rxC.setSourcePath("driver/software/RF212b/phy/at86rf212b/src/phy_rx.c") + RF212b_phy_rxC.setOutputName("phy_rx.c") + RF212b_phy_rxC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_rxC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_rxC.setType("SOURCE") + RF212b_phy_rxC.setOverwrite(True) + RF212b_phy_rxC.setEnabled(False) + + global RF212b_phy_rx_enableC + RF212b_phy_rx_enableC = rfHostLib.createFileSymbol("RF212b_phy_rx_enable_C", None) + RF212b_phy_rx_enableC.setSourcePath("driver/software/RF212b/phy/at86rf212b/src/phy_rx_enable.c") + RF212b_phy_rx_enableC.setOutputName("phy_rx_enable.c") + RF212b_phy_rx_enableC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_rx_enableC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_rx_enableC.setType("SOURCE") + RF212b_phy_rx_enableC.setOverwrite(True) + RF212b_phy_rx_enableC.setEnabled(False) + + + global RF212b_phy_txC + RF212b_phy_txC = rfHostLib.createFileSymbol("RF212b_phy_tx_C", None) + RF212b_phy_txC.setSourcePath("driver/software/RF212b/phy/at86rf212b/src/phy_tx.c") + RF212b_phy_txC.setOutputName("phy_tx.c") + RF212b_phy_txC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_txC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_phy_txC.setType("SOURCE") + RF212b_phy_txC.setOverwrite(True) + RF212b_phy_txC.setEnabled(False) + + global RF212b_tfaC + RF212b_tfaC = rfHostLib.createFileSymbol("RF212b_tfa_C", None) + RF212b_tfaC.setSourcePath("driver/software/RF212b/phy/at86rf212b/src/tfa.c") + RF212b_tfaC.setOutputName("tfa.c") + RF212b_tfaC.setDestPath("driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_tfaC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/at86rf/src/") + RF212b_tfaC.setType("SOURCE") + RF212b_tfaC.setOverwrite(True) + RF212b_tfaC.setEnabled(False) + + global RF212b_phy_ed_end_cbC + RF212b_phy_ed_end_cbC = rfHostLib.createFileSymbol("RF212b_phy_ed_end_cb_C", None) + RF212b_phy_ed_end_cbC.setSourcePath("driver/software/RF212b/phy/src/phy_ed_end_cb.c") + RF212b_phy_ed_end_cbC.setOutputName("phy_ed_end_cb.c") + RF212b_phy_ed_end_cbC.setDestPath("driver/IEEE_802154_PHY/phy/src/") + RF212b_phy_ed_end_cbC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/src/") + RF212b_phy_ed_end_cbC.setType("SOURCE") + RF212b_phy_ed_end_cbC.setOverwrite(True) + RF212b_phy_ed_end_cbC.setEnabled(False) + + global RF212b_phy_rx_frame_cbC + RF212b_phy_rx_frame_cbC = rfHostLib.createFileSymbol("RF212b_phy_rx_frame_cb_C", None) + RF212b_phy_rx_frame_cbC.setSourcePath("driver/software/RF212b/phy/src/phy_rx_frame_cb.c") + RF212b_phy_rx_frame_cbC.setOutputName("phy_rx_frame_cb.c") + RF212b_phy_rx_frame_cbC.setDestPath("driver/IEEE_802154_PHY/phy/src/") + RF212b_phy_rx_frame_cbC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/src/") + RF212b_phy_rx_frame_cbC.setType("SOURCE") + RF212b_phy_rx_frame_cbC.setOverwrite(True) + RF212b_phy_rx_frame_cbC.setEnabled(False) + + global RF212b_phy_taskC + RF212b_phy_taskC = rfHostLib.createFileSymbol("RF212b_phy_task_C", None) + RF212b_phy_taskC.setSourcePath("driver/software/RF212b/phy/src/phy_task.c") + RF212b_phy_taskC.setOutputName("phy_task.c") + RF212b_phy_taskC.setDestPath("driver/IEEE_802154_PHY/phy/src/") + RF212b_phy_taskC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/src/") + RF212b_phy_taskC.setType("SOURCE") + RF212b_phy_taskC.setOverwrite(True) + RF212b_phy_taskC.setEnabled(False) + + global RF212b_phy_tx_frame_done_cbC + RF212b_phy_tx_frame_done_cbC = rfHostLib.createFileSymbol("RF212b_phy_tx_frame_done_cb_C", None) + RF212b_phy_tx_frame_done_cbC.setSourcePath("driver/software/RF212b/phy/src/phy_tx_frame_done_cb.c") + RF212b_phy_tx_frame_done_cbC.setOutputName("phy_tx_frame_done_cb.c") + RF212b_phy_tx_frame_done_cbC.setDestPath("driver/IEEE_802154_PHY/phy/src/") + RF212b_phy_tx_frame_done_cbC.setProjectPath('config/' + configName + "/driver/IEEE_802154_PHY/phy/src/") + RF212b_phy_tx_frame_done_cbC.setType("SOURCE") + RF212b_phy_tx_frame_done_cbC.setOverwrite(True) + RF212b_phy_tx_frame_done_cbC.setEnabled(False) + + + check_update_pins() + +def finalizeComponent(rfHostLib): + #print("finalizeComponent") + pass + + + + \ No newline at end of file diff --git a/driver/software/RF212b/phy/at86rf212b/inc/AT86RF212b.h b/driver/software/RF212b/phy/at86rf212b/inc/AT86RF212b.h new file mode 100644 index 0000000..4d6b548 --- /dev/null +++ b/driver/software/RF212b/phy/at86rf212b/inc/AT86RF212b.h @@ -0,0 +1,1377 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* Prevent double inclusion */ +#ifndef AT86RF212B_H +#define AT86RF212B_H + +/* === INCLUDES ============================================================ */ + + +#define TRANSCEIVER_NAME "AT86RF212B" +/* === EXTERNALS =========================================================== */ + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/** Parameter definitions */ + +/** Important parameters. */ +/* TRX Parameter: Bit mask of transceiver supported channels */ +#define TRX_SUPPORTED_CHANNELS (0x000007FF) + +/* + * TRX Parameter: Bit mask of transceiver supported channels when operating in + * the People's Republic + * of China + */ +#define TRX_SUPPORTED_CHANNELS_CHINA (0x0000000F) + +/* + * TRX Parameter: Tolerance of the phyTransmitPower PIB attribute. This is + * encoded into the two + * MSBits of the attribute, and is effectively read-only. + */ +#define TX_PWR_TOLERANCE (0x80U) + +/** Typical timing values. */ +/* TRX Parameter: t10 */ +#define RST_PULSE_WIDTH_NS (625U) +/* TRX Parameter: tTR1 */ +#define P_ON_TO_CLKM_AVAILABLE_TYP_US (420U) +/* TRX Parameter: tTR1 */ +#define P_ON_TO_CLKM_AVAILABLE_MAX_US (1000U) +/* TRX Parameter: tTR2 */ +#define SLEEP_TO_TRX_OFF_TYP_US (420U) +/* TRX Parameter: tTR2 */ +#define SLEEP_TO_TRX_OFF_MAX_US (1000U) +/* TRX Parameter: tTR3 */ +#define TRX_OFF_TO_SLEEP_TIME_CLKM_CYCLES (35U) +/* TRX Parameter: tTR4 */ +#define TRX_OFF_TO_PLL_ON_TIME_US (170U) +/* TRX Parameter: tIRQ */ +#define TRX_IRQ_DELAY_US (9U) +/* TRX Parameter: RSSIBASE_VAL */ +#define RSSI_BASE_VAL_BPSK_300_DBM (-100) +/* TRX Parameter: RSSIBASE_VAL */ +#define RSSI_BASE_VAL_BPSK_600_DBM (-99) +/* TRX Parameter: RSSIBASE_VAL */ +#define RSSI_BASE_VAL_OQPSK_400_SIN_RC_DBM (-98) +/* TRX Parameter: RSSIBASE_VAL */ +#define RSSI_BASE_VAL_OQPSK_400_RC_DBM (-98) +/* TRX Parameter: RSSIBASE_VAL */ +#define RSSI_BASE_VAL_OQPSK_1000_SIN_DBM (-99) +/* TRX Parameter: RSSIBASE_VAL */ +#define RSSI_BASE_VAL_OQPSK_1000_RC_DBM (-98) +/* TRX Parameter: 16 us processing delay + 16 us software handling duration */ +#define PRE_TX_DURATION_US (32U) +/* TRX Parameter: tCCA */ +#define CCA_DETECTION_TIME_SYMBOL (8U) +/* TRX Parameter: Duration before start of CCA */ +#define CCA_PRE_START_DURATION_US (20U) +/* TRX Parameter: CCA processing time in us */ +#define CCA_PROCESS_TIME_US (12U) +/* TRX Parameter: Preparation time for CCA */ +#define CCA_PREPARATION_DURATION_US (50U) + +/* TRX Parameter: CCA processing time in symbols */ +#define CCA_PROCESS_TIME_SYM (1U) + +/* TRX Parameter: Complete CCA Duration in symbols */ +#define CCA_DURATION_SYM ( \ + CCA_DETECTION_TIME_SYMBOL + CCA_PROCESS_TIME_SYM) +/* TRX Parameter: Round up RST_PULSE_WIDTH_NS value to us */ + +/*delay_us() for time less than 5 seems to provide wrong delay in GCC , + * hence proper reset is not done.TO be reverted back once the related bug is + * fixed */ +#define RST_PULSE_WIDTH_US (10U) /* + * + *((RST_PULSE_WIDTH_NS + * + 999) / + * 1000) */ + +/** Register addresses */ + +/** Base address for Transceiver AES address space */ +#define AES_BASE_ADDR (0x80U) + +/** Base address and size for RX frame appendix */ +#define RXAPPENDIX_BASE_ADDR (0x00U) +#define RXAPPENDIX_SIZE (3U) + +/** Offset for register LQI */ +#define RG_LQI (0x00U) +/** Sub-registers of Register @ref RG_LQI */ +/** Access parameters for sub-register LQI_APX in register @ref RG_LQI */ +#define SR_LQI_APX 0x00, 0xFF, 0 + +/** Offset for register TRX_STATUS */ +#define RG_TRX_STATUS (0x01U) +/** Sub-registers of Register @ref RG_TRX_STATUS */ + +/** Access parameters for sub-register TRX_STATUS in register @ref RG_TRX_STATUS +**/ +#define SR_TRX_STATUS 0x01, 0x1F, 0 + +/** Access parameters for sub-register CCA_STATUS in register @ref RG_TRX_STATUS +**/ +#define SR_CCA_STATUS 0x01, 0x40, 6 + +/** Constant CCA_CH_BUSY for sub-register @ref SR_CCA_STATUS in register + * TRX_STATUS */ +#define CCA_CH_BUSY (0U) + +/** Constant CCA_CH_IDLE for sub-register @ref SR_CCA_STATUS in register + * TRX_STATUS */ +#define CCA_CH_IDLE (1U) + +/** Access parameters for sub-register CCA_DONE in register @ref RG_TRX_STATUS +**/ +#define SR_CCA_DONE 0x01, 0x80, 7 + +/** Constant CCA_COMPLETED for sub-register @ref SR_CCA_DONE in register + * TRX_STATUS */ +#define CCA_COMPLETED (1U) + +/** Constant CCA_ONGOING for sub-register @ref SR_CCA_DONE in register + * TRX_STATUS */ +#define CCA_ONGOING (0U) + +/** Offset for register ED */ +#define RG_ED (0x01U) +/** Sub-registers of Register @ref RG_ED */ +/** Access parameters for sub-register ED_APX in register @ref RG_ED */ +#define SR_ED_APX 0x01, 0xFF, 0 + +/** Offset for register TRX_STATE */ +#define RG_TRX_STATE (0x02U) +/** Sub-registers of Register @ref RG_TRX_STATE */ +/** Access parameters for sub-register TRX_CMD in register @ref RG_TRX_STATE */ +#define SR_TRX_CMD 0x02, 0x1F, 0 + +/** Access parameters for sub-register TRAC_STATUS in register @ref RG_TRX_STATE +**/ +#define SR_TRAC_STATUS 0x02, 0xE0, 5 + +/** Offset for register AES_STATUS */ +#define RG_AES_STATUS (0x02U) +/** Sub-registers of Register @ref RG_AES_STATUS */ + +/** Access parameters for sub-register AES_DONE in register @ref RG_AES_STATUS +**/ +#define SR_AES_DONE 0x02, 0x01, 0 + +/** Constant AES_DONE for sub-register @ref SR_AES_DONE in register AES_STATUS +**/ +#define AES_DONE (1U) + +/** Constant AES_NOT_DONE for sub-register @ref SR_AES_DONE in register + * AES_STATUS */ +#define AES_NOT_DONE (0U) +/** Access parameters for sub-register AES_ER in register @ref RG_AES_STATUS */ +#define SR_AES_ER 0x02, 0x80, 7 +/** Constant AES_ERROR for sub-register @ref SR_AES_ER in register AES_STATUS */ +#define AES_ERROR (1U) + +/** Constant AES_NO_ERROR for sub-register @ref SR_AES_ER in register AES_STATUS +**/ +#define AES_NO_ERROR (0U) + +/** Offset for register RX_STATUS */ +#define RG_RX_STATUS (0x02U) +/** Sub-registers of Register @ref RG_RX_STATUS */ + +/** Access parameters for sub-register TRAC_STATUS_APX in register @ref + * RG_RX_STATUS */ +#define SR_TRAC_STATUS_APX 0x02, 0x70, 4 + +/** Access parameters for sub-register RX_CRC_VALID_APX in register @ref + * RG_RX_STATUS */ +#define SR_RX_CRC_VALID_APX 0x02, 0x80, 7 + +/** Offset for register TRX_CTRL_0 */ +#define RG_TRX_CTRL_0 (0x03U) +/** Sub-registers of Register @ref RG_TRX_CTRL_0 */ + +/** Access parameters for sub-register CLKM_CTRL in register @ref RG_TRX_CTRL_0 +**/ +#define SR_CLKM_CTRL 0x03, 0x07, 0 + +/** Constant CLKM_16MHZ for sub-register @ref SR_CLKM_CTRL in register + * TRX_CTRL_0 */ +#define CLKM_16MHZ (5U) + +/** Constant CLKM_1MHZ for sub-register @ref SR_CLKM_CTRL in register TRX_CTRL_0 +**/ +#define CLKM_1MHZ (1U) + +/** Constant CLKM_1_4MHZ for sub-register @ref SR_CLKM_CTRL in register + * TRX_CTRL_0 */ +#define CLKM_1_4MHZ (6U) + +/** Constant CLKM_2MHZ for sub-register @ref SR_CLKM_CTRL in register TRX_CTRL_0 +**/ +#define CLKM_2MHZ (2U) + +/** Constant CLKM_4MHZ for sub-register @ref SR_CLKM_CTRL in register TRX_CTRL_0 +**/ +#define CLKM_4MHZ (3U) + +/** Constant CLKM_8MHZ for sub-register @ref SR_CLKM_CTRL in register TRX_CTRL_0 +**/ +#define CLKM_8MHZ (4U) + +/** Constant CLKM_NO_CLOCK for sub-register @ref SR_CLKM_CTRL in register + * TRX_CTRL_0 */ +#define CLKM_NO_CLOCK (0U) + +/** Constant CLKM_SYMBOL_RATE for sub-register @ref SR_CLKM_CTRL in register + * TRX_CTRL_0 */ +#define CLKM_SYMBOL_RATE (7U) + +/** Access parameters for sub-register CLKM_SHA_SEL in register @ref + * RG_TRX_CTRL_0 */ +#define SR_CLKM_SHA_SEL 0x03, 0x08, 3 + +/** Constant CLKM_SHA_DISABLE for sub-register @ref SR_CLKM_SHA_SEL in register + * TRX_CTRL_0 */ +#define CLKM_SHA_DISABLE (0U) + +/** Constant CLKM_SHA_ENABLE for sub-register @ref SR_CLKM_SHA_SEL in register + * TRX_CTRL_0 */ +#define CLKM_SHA_ENABLE (1U) + +/** Access parameters for sub-register PAD_IO_CLKM in register @ref + * RG_TRX_CTRL_0 */ +#define SR_PAD_IO_CLKM 0x03, 0x30, 4 + +/** Constant PAD_CLKM_2_MA for sub-register @ref SR_PAD_IO_CLKM in register + * TRX_CTRL_0 */ +#define PAD_CLKM_2_MA (0U) + +/** Constant PAD_CLKM_4_MA for sub-register @ref SR_PAD_IO_CLKM in register + * TRX_CTRL_0 */ +#define PAD_CLKM_4_MA (1U) + +/** Constant PAD_CLKM_6_MA for sub-register @ref SR_PAD_IO_CLKM in register + * TRX_CTRL_0 */ +#define PAD_CLKM_6_MA (2U) + +/** Constant PAD_CLKM_8_MA for sub-register @ref SR_PAD_IO_CLKM in register + * TRX_CTRL_0 */ +#define PAD_CLKM_8_MA (3U) +/** Access parameters for sub-register PAD_IO in register @ref RG_TRX_CTRL_0 */ +#define SR_PAD_IO 0x03, 0xC0, 6 + +/** Constant PAD_IO_2_MA for sub-register @ref SR_PAD_IO in register TRX_CTRL_0 +**/ +#define PAD_IO_2_MA (0U) + +/** Constant PAD_IO_4_MA for sub-register @ref SR_PAD_IO in register TRX_CTRL_0 +**/ +#define PAD_IO_4_MA (1U) + +/** Constant PAD_IO_6_MA for sub-register @ref SR_PAD_IO in register TRX_CTRL_0 +**/ +#define PAD_IO_6_MA (2U) + +/** Constant PAD_IO_8_MA for sub-register @ref SR_PAD_IO in register TRX_CTRL_0 +**/ +#define PAD_IO_8_MA (3U) + +/** Offset for register AES_CTRL */ +#define RG_AES_CTRL (0x03) +/** Sub-registers of Register @ref RG_AES_CTRL */ +/** Access parameters for sub-register AES_DIR in register @ref RG_AES_CTRL */ +#define SR_AES_DIR 0x03, 0x08, 3 + +/** Constant AES_DIR_DECRYPT for sub-register @ref SR_AES_DIR in register + * AES_CTRL */ +#define AES_DIR_DECRYPT (1U) + +/** Constant AES_DIR_ENCRYPT for sub-register @ref SR_AES_DIR in register + * AES_CTRL */ +#define AES_DIR_ENCRYPT (0U) +/** Access parameters for sub-register AES_MODE in register @ref RG_AES_CTRL */ +#define SR_AES_MODE 0x03, 0x70, 4 + +/** Constant AES_MODE_CBC for sub-register @ref SR_AES_MODE in register AES_CTRL +**/ +#define AES_MODE_CBC (2U) + +/** Constant AES_MODE_ECB for sub-register @ref SR_AES_MODE in register AES_CTRL +**/ +#define AES_MODE_ECB (0U) + +/** Constant AES_MODE_KEY for sub-register @ref SR_AES_MODE in register AES_CTRL +**/ +#define AES_MODE_KEY (1U) + +/** Access parameters for sub-register AES_REQUEST in register @ref RG_AES_CTRL +**/ +#define SR_AES_REQUEST 0x03, 0x80, 7 + +/** Constant AES_REQUEST for sub-register @ref SR_AES_REQUEST in register + * AES_CTRL */ +#define AES_REQUEST (1U) + +/** Offset for register TRX_CTRL_1 */ +#define RG_TRX_CTRL_1 (0x04U) +/** Sub-registers of Register @ref RG_TRX_CTRL_1 */ + +/** Access parameters for sub-register IRQ_POLARITY in register @ref + * RG_TRX_CTRL_1 */ +#define SR_IRQ_POLARITY 0x04, 0x01, 0 + +/** Constant IRQ_HIGH_ACTIVE for sub-register @ref SR_IRQ_POLARITY in register + * TRX_CTRL_1 */ +#define IRQ_HIGH_ACTIVE (0U) + +/** Constant IRQ_LOW_ACTIVE for sub-register @ref SR_IRQ_POLARITY in register + * TRX_CTRL_1 */ +#define IRQ_LOW_ACTIVE (1U) + +/** Access parameters for sub-register IRQ_MASK_MODE in register @ref + * RG_TRX_CTRL_1 */ +#define SR_IRQ_MASK_MODE 0x04, 0x02, 1 + +/** Constant IRQ_MASK_MODE_OFF for sub-register @ref SR_IRQ_MASK_MODE in + * register TRX_CTRL_1 */ +#define IRQ_MASK_MODE_OFF (0U) + +/** Constant IRQ_MASK_MODE_ON for sub-register @ref SR_IRQ_MASK_MODE in register + * TRX_CTRL_1 */ +#define IRQ_MASK_MODE_ON (1U) + +/** Access parameters for sub-register SPI_CMD_MODE in register @ref + * RG_TRX_CTRL_1 */ +#define SR_SPI_CMD_MODE 0x04, 0x0C, 2 + +/** Constant SPI_CMD_MODE_DEFAULT for sub-register @ref SR_SPI_CMD_MODE in + * register TRX_CTRL_1 */ +#define SPI_CMD_MODE_DEFAULT (0U) + +/** Constant SPI_CMD_MODE_IRQ_STATUS for sub-register @ref SR_SPI_CMD_MODE in + * register TRX_CTRL_1 */ +#define SPI_CMD_MODE_IRQ_STATUS (3U) + +/** Constant SPI_CMD_MODE_PHY_RSSI for sub-register @ref SR_SPI_CMD_MODE in + * register TRX_CTRL_1 */ +#define SPI_CMD_MODE_PHY_RSSI (2U) + +/** Constant SPI_CMD_MODE_TRX_STATUS for sub-register @ref SR_SPI_CMD_MODE in + * register TRX_CTRL_1 */ +#define SPI_CMD_MODE_TRX_STATUS (1U) + +/** Access parameters for sub-register RX_BL_CTRL in register @ref RG_TRX_CTRL_1 +**/ +#define SR_RX_BL_CTRL 0x04, 0x10, 4 + +/** Constant RX_BL_CTRL_DISABLE for sub-register @ref SR_RX_BL_CTRL in register + * TRX_CTRL_1 */ +#define RX_BL_CTRL_DISABLE (0U) + +/** Constant RX_BL_CTRL_ENABLE for sub-register @ref SR_RX_BL_CTRL in register + * TRX_CTRL_1 */ +#define RX_BL_CTRL_ENABLE (1U) + +/** Access parameters for sub-register TX_AUTO_CRC_ON in register @ref + * RG_TRX_CTRL_1 */ +#define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5 + +/** Constant TX_AUTO_CRC_DISABLE for sub-register @ref SR_TX_AUTO_CRC_ON in + * register TRX_CTRL_1 */ +#define TX_AUTO_CRC_DISABLE (0U) + +/** Constant TX_AUTO_CRC_ENABLE for sub-register @ref SR_TX_AUTO_CRC_ON in + * register TRX_CTRL_1 */ +#define TX_AUTO_CRC_ENABLE (1U) + +/** Access parameters for sub-register IRQ_2_EXT_EN in register @ref + * RG_TRX_CTRL_1 */ +#define SR_IRQ_2_EXT_EN 0x04, 0x40, 6 + +/** Constant RX_TIMESTAMPING_DISABLE for sub-register @ref SR_IRQ_2_EXT_EN in + * register TRX_CTRL_1 */ +#define RX_TIMESTAMPING_DISABLE (0U) + +/** Constant RX_TIMESTAMPING_ENABLE for sub-register @ref SR_IRQ_2_EXT_EN in + * register TRX_CTRL_1 */ +#define RX_TIMESTAMPING_ENABLE (1U) + +/** Access parameters for sub-register PA_EXT_EN in register @ref RG_TRX_CTRL_1 +**/ +#define SR_PA_EXT_EN 0x04, 0x80, 7 + +/** Constant EXT_FRONTEND_DISABLE for sub-register @ref SR_PA_EXT_EN in register + * TRX_CTRL_1 */ +#define EXT_FRONTEND_DISABLE (0U) + +/** Constant EXT_FRONTEND_ENABLE for sub-register @ref SR_PA_EXT_EN in register + * TRX_CTRL_1 */ +#define EXT_FRONTEND_ENABLE (1U) + +/** Offset for register AES_STATE_KEY_0 */ +#define RG_AES_STATE_KEY_0 (0x04U) + +/** Offset for register PHY_TX_PWR */ +#define RG_PHY_TX_PWR (0x05U) +/** Sub-registers of Register @ref RG_PHY_TX_PWR */ +/** Access parameters for sub-register TX_PWR in register @ref RG_PHY_TX_PWR */ +#define SR_TX_PWR 0x05, 0x1F, 0 +/** Access parameters for sub-register GC_PA in register @ref RG_PHY_TX_PWR */ +#define SR_GC_PA 0x05, 0x60, 5 + +/** Access parameters for sub-register PA_BOOST in register @ref RG_PHY_TX_PWR +**/ +#define SR_PA_BOOST 0x05, 0x80, 7 + +/** Constant PA_BOOST_DISABLE for sub-register @ref SR_PA_BOOST in register + * PHY_TX_PWR */ +#define PA_BOOST_DISABLE (0U) + +/** Constant PA_BOOST_ENABLE for sub-register @ref SR_PA_BOOST in register + * PHY_TX_PWR */ +#define PA_BOOST_ENABLE (1U) + +/** Offset for register PHY_RSSI */ +#define RG_PHY_RSSI (0x06) +/** Sub-registers of Register @ref RG_PHY_RSSI */ +/** Access parameters for sub-register RSSI in register @ref RG_PHY_RSSI */ +#define SR_RSSI 0x06, 0x1F, 0 +/** Access parameters for sub-register RND_VALUE in register @ref RG_PHY_RSSI */ +#define SR_RND_VALUE 0x06, 0x60, 5 + +/** Access parameters for sub-register RX_CRC_VALID in register @ref RG_PHY_RSSI +**/ +#define SR_RX_CRC_VALID 0x06, 0x80, 7 + +/** Constant CRC16_NOT_VALID for sub-register @ref SR_RX_CRC_VALID in register + * PHY_RSSI */ +#define CRC16_NOT_VALID (0U) + +/** Constant CRC16_VALID for sub-register @ref SR_RX_CRC_VALID in register + * PHY_RSSI */ +#define CRC16_VALID (1U) + +/** Offset for register PHY_ED_LEVEL */ +#define RG_PHY_ED_LEVEL (0x07U) +/** Sub-registers of Register @ref RG_PHY_ED_LEVEL */ + +/** Access parameters for sub-register ED_LEVEL in register @ref RG_PHY_ED_LEVEL +**/ +#define SR_ED_LEVEL 0x07, 0xFF, 0 + +/** Offset for register PHY_CC_CCA */ +#define RG_PHY_CC_CCA (0x08U) +/** Sub-registers of Register @ref RG_PHY_CC_CCA */ +/** Access parameters for sub-register CHANNEL in register @ref RG_PHY_CC_CCA */ +#define SR_CHANNEL 0x08, 0x1F, 0 + +/** Constant IEEE_CHANNEL_0 for sub-register @ref SR_CHANNEL in register + * PHY_CC_CCA */ +#define IEEE_CHANNEL_0 (0x00U) + +/** Constant IEEE_CHANNEL_1 for sub-register @ref SR_CHANNEL in register + * PHY_CC_CCA */ +#define IEEE_CHANNEL_1 (0x01U) + +/** Constant IEEE_CHANNEL_10 for sub-register @ref SR_CHANNEL in register + * PHY_CC_CCA */ +#define IEEE_CHANNEL_10 (0x0AU) + +/** Constant IEEE_CHANNEL_2 for sub-register @ref SR_CHANNEL in register + * PHY_CC_CCA */ +#define IEEE_CHANNEL_2 (0x02U) + +/** Constant IEEE_CHANNEL_3 for sub-register @ref SR_CHANNEL in register + * PHY_CC_CCA */ +#define IEEE_CHANNEL_3 (0x03U) + +/** Constant IEEE_CHANNEL_4 for sub-register @ref SR_CHANNEL in register + * PHY_CC_CCA */ +#define IEEE_CHANNEL_4 (0x04U) + +/** Constant IEEE_CHANNEL_5 for sub-register @ref SR_CHANNEL in register + * PHY_CC_CCA */ +#define IEEE_CHANNEL_5 (0x05U) + +/** Constant IEEE_CHANNEL_6 for sub-register @ref SR_CHANNEL in register + * PHY_CC_CCA */ +#define IEEE_CHANNEL_6 (0x06U) + +/** Constant IEEE_CHANNEL_7 for sub-register @ref SR_CHANNEL in register + * PHY_CC_CCA */ +#define IEEE_CHANNEL_7 (0x07U) + +/** Constant IEEE_CHANNEL_8 for sub-register @ref SR_CHANNEL in register + * PHY_CC_CCA */ +#define IEEE_CHANNEL_8 (0x08U) + +/** Constant IEEE_CHANNEL_9 for sub-register @ref SR_CHANNEL in register + * PHY_CC_CCA */ +#define IEEE_CHANNEL_9 (0x09U) + +/** Access parameters for sub-register CCA_MODE in register @ref RG_PHY_CC_CCA +**/ +#define SR_CCA_MODE 0x08, 0x60, 5 + +/** Constant CCA_MODE_0 for sub-register @ref SR_CCA_MODE in register PHY_CC_CCA +**/ +#define CCA_MODE_0 (0U) + +/** Constant CCA_MODE_1 for sub-register @ref SR_CCA_MODE in register PHY_CC_CCA +**/ +#define CCA_MODE_1 (1U) + +/** Constant CCA_MODE_2 for sub-register @ref SR_CCA_MODE in register PHY_CC_CCA +**/ +#define CCA_MODE_2 (2U) + +/** Constant CCA_MODE_3 for sub-register @ref SR_CCA_MODE in register PHY_CC_CCA +**/ +#define CCA_MODE_3 (3U) + +/** Access parameters for sub-register CCA_REQUEST in register @ref + * RG_PHY_CC_CCA */ +#define SR_CCA_REQUEST 0x08, 0x80, 7 + +/** Constant CCA_NO_START for sub-register @ref SR_CCA_REQUEST in register + * PHY_CC_CCA */ +#define CCA_NO_START (0U) + +/** Constant CCA_START for sub-register @ref SR_CCA_REQUEST in register + * PHY_CC_CCA */ +#define CCA_START (1U) + +/** Offset for register CCA_THRES */ +#define RG_CCA_THRES (0x09) +/** Sub-registers of Register @ref RG_CCA_THRES */ + +/** Access parameters for sub-register CCA_ED_THRES in register @ref + * RG_CCA_THRES */ +#define SR_CCA_ED_THRES 0x09, 0x0F, 0 + +/** Access parameters for sub-register CCA_CS_THRES in register @ref + * RG_CCA_THRES */ +#define SR_CCA_CS_THRES 0x09, 0xF0, 4 + +/** Constant CCA_CS_THRES_15 for sub-register @ref SR_CCA_CS_THRES in register + * CCA_THRES */ +#define CCA_CS_THRES_15 (0xFU) + +/** Constant CCA_CS_THRES_7 for sub-register @ref SR_CCA_CS_THRES in register + * CCA_THRES */ +#define CCA_CS_THRES_7 (0x7U) + +/** Offset for register RX_CTRL */ +#define RG_RX_CTRL (0x0AU) +/** Sub-registers of Register @ref RG_RX_CTRL */ +/** Access parameters for sub-register JCM_EN in register @ref RG_RX_CTRL */ +#define SR_JCM_EN 0x0A, 0x20, 5 +/** Constant JCM_DISABLE for sub-register @ref SR_JCM_EN in register RX_CTRL */ +#define JCM_DISABLE (0U) +/** Constant JCM_ENABLE for sub-register @ref SR_JCM_EN in register RX_CTRL */ +#define JCM_ENABLE (1U) + +/** Offset for register SFD_VALUE */ +#define RG_SFD_VALUE (0x0BU) +/** Sub-registers of Register @ref RG_SFD_VALUE */ + +/** Access parameters for sub-register SFD_VALUE in register @ref RG_SFD_VALUE +**/ +#define SR_SFD_VALUE 0x0B, 0xFF, 0 + +/** Offset for register TRX_CTRL_2 */ +#define RG_TRX_CTRL_2 (0x0CU) +/** Sub-registers of Register @ref RG_TRX_CTRL_2 */ + +/** Access parameters for sub-register OQPSK_DATA_RATE in register @ref + * RG_TRX_CTRL_2 */ +#define SR_OQPSK_DATA_RATE 0x0C, 0x03, 0 + +/** + * Constant ALTRATE_100_KBPS_OR_250_KBPS for sub-register @ref + * SR_OQPSK_DATA_RATE in register + * TRX_CTRL_2 + */ +#define ALTRATE_100_KBPS_OR_250_KBPS (0U) + +/** + * Constant ALTRATE_200_KBPS_OR_500_KBPS for sub-register @ref + * SR_OQPSK_DATA_RATE in register + * TRX_CTRL_2 + */ +#define ALTRATE_200_KBPS_OR_500_KBPS (1U) + +/** Constant ALTRATE_400_KBPS_OR_1_MBPS for sub-register @ref SR_OQPSK_DATA_RATE + * in register TRX_CTRL_2 */ +#define ALTRATE_400_KBPS_OR_1_MBPS (2U) + +/** Constant NEWRATE_500_KBPS for sub-register @ref SR_OQPSK_DATA_RATE in + * register TRX_CTRL_2 */ +#define NEWRATE_500_KBPS (3U) + +/** Access parameters for sub-register SUB_MODE in register @ref RG_TRX_CTRL_2 +**/ +#define SR_SUB_MODE 0x0C, 0x04, 2 + +/** Constant HIGH_DATA_RATE for sub-register @ref SR_SUB_MODE in register + * TRX_CTRL_2 */ +#define HIGH_DATA_RATE (1U) + +/** Constant LOW_DATA_RATE for sub-register @ref SR_SUB_MODE in register + * TRX_CTRL_2 */ +#define LOW_DATA_RATE (0U) + +/** Access parameters for sub-register BPSK_OQPSK in register @ref RG_TRX_CTRL_2 +**/ +#define SR_BPSK_OQPSK 0x0C, 0x08, 3 + +/** Constant BPSK_MODE for sub-register @ref SR_BPSK_OQPSK in register + * TRX_CTRL_2 */ +#define BPSK_MODE (0U) + +/** Constant OQPSK_MODE for sub-register @ref SR_BPSK_OQPSK in register + * TRX_CTRL_2 */ +#define OQPSK_MODE (1U) + +/** Access parameters for sub-register ALT_SPECTRUM in register @ref + * RG_TRX_CTRL_2 */ +#define SR_ALT_SPECTRUM 0x0C, 0x10, 4 + +/** Constant ALT_SPECTRUM_DISABLE for sub-register @ref SR_ALT_SPECTRUM in + * register TRX_CTRL_2 */ +#define ALT_SPECTRUM_DISABLE (0U) + +/** Constant ALT_SPECTRUM_ENABLE for sub-register @ref SR_ALT_SPECTRUM in + * register TRX_CTRL_2 */ +#define ALT_SPECTRUM_ENABLE (1U) + +/** Access parameters for sub-register OQPSK_SCRAM_EN in register @ref + * RG_TRX_CTRL_2 */ +#define SR_OQPSK_SCRAM_EN 0x0C, 0x20, 5 + +/** Constant OQPSK_SCRAM_DISABLE for sub-register @ref SR_OQPSK_SCRAM_EN in + * register TRX_CTRL_2 */ +#define OQPSK_SCRAM_DISABLE (0U) + +/** Constant OQPSK_SCRAM_ENABLE for sub-register @ref SR_OQPSK_SCRAM_EN in + * register TRX_CTRL_2 */ +#define OQPSK_SCRAM_ENABLE (1U) + +/** Access parameters for sub-register TRX_OFF_AVDD_EN in register @ref + * RG_TRX_CTRL_2 */ +#define SR_TRX_OFF_AVDD_EN 0x0C, 0x40, 6 + +/** Constant TRX_OFF_AVDD_DISABLE for sub-register @ref SR_TRX_OFF_AVDD_EN in + * register TRX_CTRL_2 */ +#define TRX_OFF_AVDD_DISABLE (0U) + +/** Constant TRX_OFF_AVDD_ENABLE for sub-register @ref SR_TRX_OFF_AVDD_EN in + * register TRX_CTRL_2 */ +#define TRX_OFF_AVDD_ENABLE (1U) + +/** Access parameters for sub-register RX_SAFE_MODE in register @ref + * RG_TRX_CTRL_2 */ +#define SR_RX_SAFE_MODE 0x0C, 0x80, 7 + +/** Constant RX_SAFE_MODE_DISABLE for sub-register @ref SR_RX_SAFE_MODE in + * register TRX_CTRL_2 */ +#define RX_SAFE_MODE_DISABLE (0U) + +/** Constant RX_SAFE_MODE_ENABLE for sub-register @ref SR_RX_SAFE_MODE in + * register TRX_CTRL_2 */ +#define RX_SAFE_MODE_ENABLE (1U) + +/** Offset for register ANT_DIV */ +#define RG_ANT_DIV (0x0D) +/** Sub-registers of Register @ref RG_ANT_DIV */ +/** Access parameters for sub-register ANT_CTRL in register @ref RG_ANT_DIV */ +#define SR_ANT_CTRL 0x0D, 0x03, 0 +/** Constant ANT_CTRL_1 for sub-register @ref SR_ANT_CTRL in register ANT_DIV */ +#define ANT_CTRL_1 (1U) +/** Constant ANT_CTRL_2 for sub-register @ref SR_ANT_CTRL in register ANT_DIV */ +#define ANT_CTRL_2 (2U) + +/** Access parameters for sub-register ANT_EXT_SW_EN in register @ref RG_ANT_DIV +**/ +#define SR_ANT_EXT_SW_EN 0x0D, 0x04, 2 + +/** Constant ANT_EXT_SW_DISABLE for sub-register @ref SR_ANT_EXT_SW_EN in + * register ANT_DIV */ +#define ANT_EXT_SW_DISABLE (0U) + +/** Constant ANT_EXT_SW_ENABLE for sub-register @ref SR_ANT_EXT_SW_EN in + * register ANT_DIV */ +#define ANT_EXT_SW_ENABLE (1U) +/** Access parameters for sub-register ANT_DIV_EN in register @ref RG_ANT_DIV */ +#define SR_ANT_DIV_EN 0x0D, 0x08, 3 + +/** Constant ANT_DIV_DISABLE for sub-register @ref SR_ANT_DIV_EN in register + * ANT_DIV */ +#define ANT_DIV_DISABLE (0U) + +/** Constant ANT_DIV_ENABLE for sub-register @ref SR_ANT_DIV_EN in register + * ANT_DIV */ +#define ANT_DIV_ENABLE (1U) +/** Access parameters for sub-register ANT_SEL in register @ref RG_ANT_DIV */ +#define SR_ANT_SEL 0x0D, 0x80, 7 + +/** Constant ANT_SEL_ANTENNA_0 for sub-register @ref SR_ANT_SEL in register + * ANT_DIV */ +#define ANT_SEL_ANTENNA_0 (0U) + +/** Constant ANT_SEL_ANTENNA_1 for sub-register @ref SR_ANT_SEL in register + * ANT_DIV */ +#define ANT_SEL_ANTENNA_1 (1U) + +/** Offset for register IRQ_MASK */ +#define RG_IRQ_MASK (0x0EU) +/** Sub-registers of Register @ref RG_IRQ_MASK */ +/** Access parameters for sub-register IRQ_MASK in register @ref RG_IRQ_MASK */ +#define SR_IRQ_MASK 0x0E, 0xFF, 0 + +/** Offset for register IRQ_STATUS */ +#define RG_IRQ_STATUS (0x0FU) +/** Sub-registers of Register @ref RG_IRQ_STATUS */ + +/** Access parameters for sub-register IRQ_0_PLL_LOCK in register @ref + * RG_IRQ_STATUS */ +#define SR_IRQ_0_PLL_LOCK 0x0F, 0x01, 0 + +/** Access parameters for sub-register IRQ_1_PLL_UNLOCK in register @ref + * RG_IRQ_STATUS */ +#define SR_IRQ_1_PLL_UNLOCK 0x0F, 0x02, 1 + +/** Access parameters for sub-register IRQ_2_RX_START in register @ref + * RG_IRQ_STATUS */ +#define SR_IRQ_2_RX_START 0x0F, 0x04, 2 + +/** Access parameters for sub-register IRQ_3_TRX_END in register @ref + * RG_IRQ_STATUS */ +#define SR_IRQ_3_TRX_END 0x0F, 0x08, 3 + +/** Access parameters for sub-register IRQ_4_CCA_ED_DONE in register @ref + * RG_IRQ_STATUS */ +#define SR_IRQ_4_CCA_ED_DONE 0x0F, 0x10, 4 + +/** Access parameters for sub-register IRQ_5_AMI in register @ref RG_IRQ_STATUS +**/ +#define SR_IRQ_5_AMI 0x0F, 0x20, 5 + +/** Access parameters for sub-register IRQ_6_TRX_UR in register @ref + * RG_IRQ_STATUS */ +#define SR_IRQ_6_TRX_UR 0x0F, 0x40, 6 + +/** Access parameters for sub-register IRQ_7_BAT_LOW in register @ref + * RG_IRQ_STATUS */ +#define SR_IRQ_7_BAT_LOW 0x0F, 0x80, 7 + +/** Offset for register VREG_CTRL */ +#define RG_VREG_CTRL (0x10U) +/** Sub-registers of Register @ref RG_VREG_CTRL */ +/** Access parameters for sub-register DVDD_OK in register @ref RG_VREG_CTRL */ +#define SR_DVDD_OK 0x10, 0x04, 2 + +/** Access parameters for sub-register DVREG_EXT in register @ref RG_VREG_CTRL +**/ +#define SR_DVREG_EXT 0x10, 0x08, 3 +/** Access parameters for sub-register AVDD_OK in register @ref RG_VREG_CTRL */ +#define SR_AVDD_OK 0x10, 0x40, 6 + +/** Access parameters for sub-register AVREG_EXT in register @ref RG_VREG_CTRL +**/ +#define SR_AVREG_EXT 0x10, 0x80, 7 + +/** Offset for register BATMON */ +#define RG_BATMON (0x11U) +/** Sub-registers of Register @ref RG_BATMON */ +/** Access parameters for sub-register BATMON_VTH in register @ref RG_BATMON */ +#define SR_BATMON_VTH 0x11, 0x0F, 0 +/** Access parameters for sub-register BATMON_HR in register @ref RG_BATMON */ +#define SR_BATMON_HR 0x11, 0x10, 4 + +/** Constant BATMON_HR_HIGH for sub-register @ref SR_BATMON_HR in register + * BATMON */ +#define BATMON_HR_HIGH (1U) + +/** Constant BATMON_HR_LOW for sub-register @ref SR_BATMON_HR in register BATMON +**/ +#define BATMON_HR_LOW (0U) +/** Access parameters for sub-register BATMON_OK in register @ref RG_BATMON */ +#define SR_BATMON_OK 0x11, 0x20, 5 + +/** Constant BATMON_NOT_VALID for sub-register @ref SR_BATMON_OK in register + * BATMON */ +#define BATMON_NOT_VALID (0U) + +/** Constant BATMON_VALID for sub-register @ref SR_BATMON_OK in register BATMON +**/ +#define BATMON_VALID (1U) +/** Access parameters for sub-register PLL_LOCK_CP in register @ref RG_BATMON */ +#define SR_PLL_LOCK_CP 0x11, 0x80, 7 + +/** Offset for register XOSC_CTRL */ +#define RG_XOSC_CTRL (0x12U) +/** Sub-registers of Register @ref RG_XOSC_CTRL */ + +/** Access parameters for sub-register XTAL_TRIM in register @ref RG_XOSC_CTRL +**/ +#define SR_XTAL_TRIM 0x12, 0x0F, 0 + +/** Access parameters for sub-register XTAL_MODE in register @ref RG_XOSC_CTRL +**/ +#define SR_XTAL_MODE 0x12, 0xF0, 4 + +/** Offset for register CC_CTRL_0 */ +#define RG_CC_CTRL_0 (0x13U) +/** Sub-registers of Register @ref RG_CC_CTRL_0 */ + +/** Access parameters for sub-register CC_NUMBER in register @ref RG_CC_CTRL_0 +**/ +#define SR_CC_NUMBER 0x13, 0xFF, 0 + +/** Offset for register CC_CTRL_1 */ +#define RG_CC_CTRL_1 (0x14U) +/** Sub-registers of Register @ref RG_CC_CTRL_1 */ +/** Access parameters for sub-register CC_BAND in register @ref RG_CC_CTRL_1 */ +#define SR_CC_BAND 0x14, 0x07, 0 + +/** Offset for register AES_CTRL_MIRROR */ +#define RG_AES_CTRL_MIRROR (0x14U) + +/** Offset for register RX_SYN */ +#define RG_RX_SYN (0x15U) +/** Sub-registers of Register @ref RG_RX_SYN */ + +/** Access parameters for sub-register RX_PDT_LEVEL in register @ref RG_RX_SYN +**/ +#define SR_RX_PDT_LEVEL 0x15, 0x0F, 0 +/** Access parameters for sub-register RX_OVERRIDE in register @ref RG_RX_SYN */ +#define SR_RX_OVERRIDE 0x15, 0x70, 4 + +/** Constant RXO_DISABLE for sub-register @ref SR_RX_OVERRIDE in register RX_SYN +**/ +#define RXO_DISABLE (0U) + +/** Constant RXO_ENABLE for sub-register @ref SR_RX_OVERRIDE in register RX_SYN +**/ +#define RXO_ENABLE (6U) +/** Access parameters for sub-register RX_PDT_DIS in register @ref RG_RX_SYN */ +#define SR_RX_PDT_DIS 0x15, 0x80, 7 + +/** Constant RX_DISABLE for sub-register @ref SR_RX_PDT_DIS in register RX_SYN +**/ +#define RX_DISABLE (1U) +/** Constant RX_ENABLE for sub-register @ref SR_RX_PDT_DIS in register RX_SYN */ +#define RX_ENABLE (0U) + +/** Offset for register RF_CTRL_0 */ +#define RG_RF_CTRL_0 (0x16U) +/** Sub-registers of Register @ref RG_RF_CTRL_0 */ + +/** Access parameters for sub-register GC_TX_OFFS in register @ref RG_RF_CTRL_0 +**/ +#define SR_GC_TX_OFFS 0x16, 0x03, 0 + +/** Access parameters for sub-register IF_SHIFT_MODE in register @ref + * RG_RF_CTRL_0 */ +#define SR_IF_SHIFT_MODE 0x16, 0x0C, 2 + +/** Constant IF_SHIFT_MODE_AUTO for sub-register @ref SR_IF_SHIFT_MODE in + * register RF_CTRL_0 */ +#define IF_SHIFT_MODE_AUTO (1U) + +/** Constant IF_SHIFT_MODE_OFF for sub-register @ref SR_IF_SHIFT_MODE in + * register RF_CTRL_0 */ +#define IF_SHIFT_MODE_OFF (0U) +/** Access parameters for sub-register PA_LT in register @ref RG_RF_CTRL_0 */ +#define SR_PA_LT 0x16, 0xC0, 6 + +#define BPSK_TX_OFFSET (3U) + +/** Constant OQPSK_TX_OFFSET for sub-register @ref SR_GC_TX_OFFS in register + * RF_CTRL_0 */ +#define OQPSK_TX_OFFSET (2U) + +/** Offset for register XAH_CTRL_1 */ +#define RG_XAH_CTRL_1 (0x17U) +/** Sub-registers of Register @ref RG_XAH_CTRL_1 */ + +/** Access parameters for sub-register AACK_PROM_MODE in register @ref + * RG_XAH_CTRL_1 */ +#define SR_AACK_PROM_MODE 0x17, 0x02, 1 + +/** Constant PROM_MODE_DISABLE for sub-register @ref SR_AACK_PROM_MODE in + * register XAH_CTRL_1 */ +#define PROM_MODE_DISABLE (0U) + +/** Constant PROM_MODE_ENABLE for sub-register @ref SR_AACK_PROM_MODE in + * register XAH_CTRL_1 */ +#define PROM_MODE_ENABLE (1U) + +/** Access parameters for sub-register AACK_ACK_TIME in register @ref + * RG_XAH_CTRL_1 */ +#define SR_AACK_ACK_TIME 0x17, 0x04, 2 + +/** Constant ACK_TIME_12_SYMBOLS for sub-register @ref SR_AACK_ACK_TIME in + * register XAH_CTRL_1 */ +#define ACK_TIME_12_SYMBOLS (0U) + +/** Constant ACK_TIME_2_SYMBOLS for sub-register @ref SR_AACK_ACK_TIME in + * register XAH_CTRL_1 */ +#define ACK_TIME_2_SYMBOLS (1U) + +/** Access parameters for sub-register AACK_UPLD_RES_FT in register @ref + * RG_XAH_CTRL_1 */ +#define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4 + +/** Constant UPLD_RES_FT_DISABLE for sub-register @ref SR_AACK_UPLD_RES_FT in + * register XAH_CTRL_1 */ +#define UPLD_RES_FT_DISABLE (0U) + +/** Constant UPLD_RES_FT_ENABLE for sub-register @ref SR_AACK_UPLD_RES_FT in + * register XAH_CTRL_1 */ +#define UPLD_RES_FT_ENABLE (1U) + +/** Access parameters for sub-register AACK_FLTR_RES_FT in register @ref + * RG_XAH_CTRL_1 */ +#define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5 + +/** Constant FLTR_RES_FT_DISABLE for sub-register @ref SR_AACK_FLTR_RES_FT in + * register XAH_CTRL_1 */ +#define FLTR_RES_FT_DISABLE (0U) + +/** Constant FLTR_RES_FT_ENABLE for sub-register @ref SR_AACK_FLTR_RES_FT in + * register XAH_CTRL_1 */ +#define FLTR_RES_FT_ENABLE (1U) + +/** Access parameters for sub-register CSMA_LBT_MODE in register @ref + * RG_XAH_CTRL_1 */ +#define SR_CSMA_LBT_MODE 0x17, 0x40, 6 + +/** Constant CSMA_MODE_ENABLE for sub-register @ref SR_CSMA_LBT_MODE in register + * XAH_CTRL_1 */ +#define CSMA_MODE_ENABLE (0U) + +/** Constant LBT_MODE_ENABLE for sub-register @ref SR_CSMA_LBT_MODE in register + * XAH_CTRL_1 */ +#define LBT_MODE_ENABLE (1U) + +/** Offset for register FTN_CTRL */ +#define RG_FTN_CTRL (0x18U) +/** Sub-registers of Register @ref RG_FTN_CTRL */ +/** Access parameters for sub-register FTN_START in register @ref RG_FTN_CTRL */ +#define SR_FTN_START 0x18, 0x80, 7 + +/** Offset for register PLL_CF */ +#define RG_PLL_CF (0x1AU) +/** Sub-registers of Register @ref RG_PLL_CF */ + +/** Access parameters for sub-register PLL_CF_START in register @ref RG_PLL_CF +**/ +#define SR_PLL_CF_START 0x1A, 0x80, 7 + +/** Offset for register PLL_DCU */ +#define RG_PLL_DCU (0x1BU) +/** Sub-registers of Register @ref RG_PLL_DCU */ + +/** Access parameters for sub-register PLL_DCU_START in register @ref RG_PLL_DCU +**/ +#define SR_PLL_DCU_START 0x1B, 0x80, 7 + +/** Offset for register PART_NUM */ +#define RG_PART_NUM (0x1CU) +/** Sub-registers of Register @ref RG_PART_NUM */ +/** Access parameters for sub-register PART_NUM in register @ref RG_PART_NUM */ +#define SR_PART_NUM 0x1C, 0xFF, 0 + +/** Constant PART_NUM_AT86RF212B for sub-register @ref SR_PART_NUM in register + * PART_NUM */ +#define PART_NUM_AT86RF212B (0x07U) + +/** Offset for register VERSION_NUM */ +#define RG_VERSION_NUM (0x1DU) +/** Sub-registers of Register @ref RG_VERSION_NUM */ + +/** Access parameters for sub-register VERSION_NUM in register @ref + * RG_VERSION_NUM */ +#define SR_VERSION_NUM 0x1D, 0xFF, 0 + +/** Constant VERSION_NUM_AT86RF12B_C for sub-register @ref SR_VERSION_NUM in + * register VERSION_NUM */ +#define VERSION_NUM_AT86RF12B_C (0x03U) + +/** Offset for register MAN_ID_0 */ +#define RG_MAN_ID_0 (0x1EU) +/** Sub-registers of Register @ref RG_MAN_ID_0 */ +/** Access parameters for sub-register MAN_ID_0 in register @ref RG_MAN_ID_0 */ +#define SR_MAN_ID_0 0x1E, 0xFF, 0 + +/** Offset for register MAN_ID_1 */ +#define RG_MAN_ID_1 (0x1FU) +/** Sub-registers of Register @ref RG_MAN_ID_1 */ +/** Access parameters for sub-register MAN_ID_1 in register @ref RG_MAN_ID_1 */ +#define SR_MAN_ID_1 0x1F, 0xFF, 0 + +/** Offset for register SHORT_ADDR_0 */ +#define RG_SHORT_ADDR_0 (0x20U) +/** Sub-registers of Register @ref RG_SHORT_ADDR_0 */ + +/** Access parameters for sub-register SHORT_ADDR_0 in register @ref + * RG_SHORT_ADDR_0 */ +#define SR_SHORT_ADDR_0 0x20, 0xFF, 0 + +/** Offset for register SHORT_ADDR_1 */ +#define RG_SHORT_ADDR_1 (0x21U) +/** Sub-registers of Register @ref RG_SHORT_ADDR_1 */ + +/** Access parameters for sub-register SHORT_ADDR_1 in register @ref + * RG_SHORT_ADDR_1 */ +#define SR_SHORT_ADDR_1 0x21, 0xFF, 0 + +/** Offset for register PAN_ID_0 */ +#define RG_PAN_ID_0 (0x22U) +/** Sub-registers of Register @ref RG_PAN_ID_0 */ +/** Access parameters for sub-register PAN_ID_0 in register @ref RG_PAN_ID_0 */ +#define SR_PAN_ID_0 0x22, 0xFF, 0 + +/** Offset for register PAN_ID_1 */ +#define RG_PAN_ID_1 (0x23U) +/** Sub-registers of Register @ref RG_PAN_ID_1 */ +/** Access parameters for sub-register PAN_ID_1 in register @ref RG_PAN_ID_1 */ +#define SR_PAN_ID_1 0x23, 0xFF, 0 + +/** Offset for register IEEE_ADDR_0 */ +#define RG_IEEE_ADDR_0 (0x24U) +/** Sub-registers of Register @ref RG_IEEE_ADDR_0 */ + +/** Access parameters for sub-register IEEE_ADDR_0 in register @ref + * RG_IEEE_ADDR_0 */ +#define SR_IEEE_ADDR_0 0x24, 0xFF, 0 + +/** Offset for register IEEE_ADDR_1 */ +#define RG_IEEE_ADDR_1 (0x25U) +/** Sub-registers of Register @ref RG_IEEE_ADDR_1 */ + +/** Access parameters for sub-register IEEE_ADDR_1 in register @ref + * RG_IEEE_ADDR_1 */ +#define SR_IEEE_ADDR_1 0x25, 0xFF, 0 + +/** Offset for register IEEE_ADDR_2 */ +#define RG_IEEE_ADDR_2 (0x26U) +/** Sub-registers of Register @ref RG_IEEE_ADDR_2 */ + +/** Access parameters for sub-register IEEE_ADDR_2 in register @ref + * RG_IEEE_ADDR_2 */ +#define SR_IEEE_ADDR_2 0x26, 0xFF, 0 + +/** Offset for register IEEE_ADDR_3 */ +#define RG_IEEE_ADDR_3 (0x27U) +/** Sub-registers of Register @ref RG_IEEE_ADDR_3 */ + +/** Access parameters for sub-register IEEE_ADDR_3 in register @ref + * RG_IEEE_ADDR_3 */ +#define SR_IEEE_ADDR_3 0x27, 0xFF, 0 + +/** Offset for register IEEE_ADDR_4 */ +#define RG_IEEE_ADDR_4 (0x28U) +/** Sub-registers of Register @ref RG_IEEE_ADDR_4 */ + +/** Access parameters for sub-register IEEE_ADDR_4 in register @ref + * RG_IEEE_ADDR_4 */ +#define SR_IEEE_ADDR_4 0x28, 0xFF, 0 + +/** Offset for register IEEE_ADDR_5 */ +#define RG_IEEE_ADDR_5 (0x29U) +/** Sub-registers of Register @ref RG_IEEE_ADDR_5 */ + +/** Access parameters for sub-register IEEE_ADDR_5 in register @ref + * RG_IEEE_ADDR_5 */ +#define SR_IEEE_ADDR_5 0x29, 0xFF, 0 + +/** Offset for register IEEE_ADDR_6 */ +#define RG_IEEE_ADDR_6 (0x2AU) +/** Sub-registers of Register @ref RG_IEEE_ADDR_6 */ + +/** Access parameters for sub-register IEEE_ADDR_6 in register @ref + * RG_IEEE_ADDR_6 */ +#define SR_IEEE_ADDR_6 0x2A, 0xFF, 0 + +/** Offset for register IEEE_ADDR_7 */ +#define RG_IEEE_ADDR_7 (0x2BU) +/** Sub-registers of Register @ref RG_IEEE_ADDR_7 */ + +/** Access parameters for sub-register IEEE_ADDR_7 in register @ref + * RG_IEEE_ADDR_7 */ +#define SR_IEEE_ADDR_7 0x2B, 0xFF, 0 + +/** Offset for register XAH_CTRL_0 */ +#define RG_XAH_CTRL_0 (0x2CU) +/** Sub-registers of Register @ref RG_XAH_CTRL_0 */ + +/** Access parameters for sub-register SLOTTED_OPERATION in register @ref + * RG_XAH_CTRL_0 */ +#define SR_SLOTTED_OPERATION 0x2C, 0x01, 0 + +/** Access parameters for sub-register MAX_CSMA_RETRIES in register @ref + * RG_XAH_CTRL_0 */ +#define SR_MAX_CSMA_RETRIES 0x2C, 0x0E, 1 + +/** Access parameters for sub-register MAX_FRAME_RETRIES in register @ref + * RG_XAH_CTRL_0 */ +#define SR_MAX_FRAME_RETRIES 0x2C, 0xF0, 4 + +/** Offset for register CSMA_SEED_0 */ +#define RG_CSMA_SEED_0 (0x2DU) +/** Sub-registers of Register @ref RG_CSMA_SEED_0 */ + +/** Access parameters for sub-register CSMA_SEED_0 in register @ref + * RG_CSMA_SEED_0 */ +#define SR_CSMA_SEED_0 0x2D, 0xFF, 0 + +/** Offset for register CSMA_SEED_1 */ +#define RG_CSMA_SEED_1 (0x2EU) +/** Sub-registers of Register @ref RG_CSMA_SEED_1 */ + +/** Access parameters for sub-register CSMA_SEED_1 in register @ref + * RG_CSMA_SEED_1 */ +#define SR_CSMA_SEED_1 0x2E, 0x07, 0 + +/** Access parameters for sub-register AACK_I_AM_COORD in register @ref + * RG_CSMA_SEED_1 */ +#define SR_AACK_I_AM_COORD 0x2E, 0x08, 3 + +/** Constant I_AM_COORD_DISABLE for sub-register @ref SR_AACK_I_AM_COORD in + * register CSMA_SEED_1 */ +#define I_AM_COORD_DISABLE (0U) + +/** Constant I_AM_COORD_ENABLE for sub-register @ref SR_AACK_I_AM_COORD in + * register CSMA_SEED_1 */ +#define I_AM_COORD_ENABLE (1U) + +/** Access parameters for sub-register AACK_DIS_ACK in register @ref + * RG_CSMA_SEED_1 */ +#define SR_AACK_DIS_ACK 0x2E, 0x10, 4 + +/** Constant ACK_DISABLE for sub-register @ref SR_AACK_DIS_ACK in register + * CSMA_SEED_1 */ +#define ACK_DISABLE (1U) + +/** Constant ACK_ENABLE for sub-register @ref SR_AACK_DIS_ACK in register + * CSMA_SEED_1 */ +#define ACK_ENABLE (0U) + +/** Access parameters for sub-register AACK_SET_PD in register @ref + * RG_CSMA_SEED_1 */ +#define SR_AACK_SET_PD 0x2E, 0x20, 5 + +/** Constant CLEAR_PD for sub-register @ref SR_AACK_SET_PD in register + * CSMA_SEED_1 */ +#define CLEAR_PD (0U) + +/** Constant SET_PD for sub-register @ref SR_AACK_SET_PD in register CSMA_SEED_1 +**/ +#define SET_PD (1U) + +/** Access parameters for sub-register AACK_FVN_MODE in register @ref + * RG_CSMA_SEED_1 */ +#define SR_AACK_FVN_MODE 0x2E, 0xC0, 6 + +/** Constant FRAME_VERSION_00 for sub-register @ref SR_AACK_FVN_MODE in register + * CSMA_SEED_1 */ +#define FRAME_VERSION_00 (0U) + +/** Constant FRAME_VERSION_01 for sub-register @ref SR_AACK_FVN_MODE in register + * CSMA_SEED_1 */ +#define FRAME_VERSION_01 (1U) + +/** Constant FRAME_VERSION_012 for sub-register @ref SR_AACK_FVN_MODE in + * register CSMA_SEED_1 */ +#define FRAME_VERSION_012 (2U) + +/** Constant FRAME_VERSION_IGNORED for sub-register @ref SR_AACK_FVN_MODE in + * register CSMA_SEED_1 */ +#define FRAME_VERSION_IGNORED (3U) + +/** Offset for register CSMA_BE */ +#define RG_CSMA_BE (0x2F) +/** Sub-registers of Register @ref RG_CSMA_BE */ +/** Access parameters for sub-register MIN_BE in register @ref RG_CSMA_BE */ +#define SR_MIN_BE 0x2F, 0x0F, 0 +/** Access parameters for sub-register MAX_BE in register @ref RG_CSMA_BE */ +#define SR_MAX_BE 0x2F, 0xF0, 4 + +/** Enumerations */ + +/** sub-register TRX_CMD in register TRX_STATE */ +typedef enum trx_cmd_tag { + /** Constant CMD_NOP for sub-register @ref SR_TRX_CMD */ + CMD_NOP = (0x00), + + /** Constant CMD_TX_START for sub-register @ref SR_TRX_CMD */ + CMD_TX_START = (0x02), + + /** Constant CMD_FORCE_TRX_OFF for sub-register @ref SR_TRX_CMD */ + CMD_FORCE_TRX_OFF = (0x03), + + /** Constant CMD_FORCE_PLL_ON for sub-register @ref SR_TRX_CMD */ + CMD_FORCE_PLL_ON = (0x04), + + /** Constant CMD_RX_ON for sub-register @ref SR_TRX_CMD */ + CMD_RX_ON = (0x06), + + /** Constant CMD_TRX_OFF for sub-register @ref SR_TRX_CMD */ + CMD_TRX_OFF = (0x08), + + /** Constant CMD_PLL_ON for sub-register @ref SR_TRX_CMD */ + CMD_PLL_ON = (0x09), + + /** Constant CMD_RX_AACK_ON for sub-register @ref SR_TRX_CMD */ + CMD_RX_AACK_ON = (0x16), + + /** Constant CMD_TX_ARET_ON for sub-register @ref SR_TRX_CMD */ + CMD_TX_ARET_ON = (0x19), + + /** Software implemented command */ + CMD_SLEEP = (0x0F) +}trx_cmd_t; + +/** sub-register TRX_STATUS in register TRX_STATUS */ +typedef enum tal_trx_status_tag { + /** Constant P_ON for sub-register @ref SR_TRX_STATUS */ + P_ON = (0x00), + + /** Constant BUSY_RX for sub-register @ref SR_TRX_STATUS */ + BUSY_RX = (0x01), + + /** Constant BUSY_TX for sub-register @ref SR_TRX_STATUS */ + BUSY_TX = (0x02), + + /** Constant RX_ON for sub-register @ref SR_TRX_STATUS */ + RX_ON = (0x06), + + /** Constant TRX_OFF for sub-register @ref SR_TRX_STATUS */ + TRX_OFF = (0x08), + + /** Constant PLL_ON for sub-register @ref SR_TRX_STATUS */ + PLL_ON = (0x09), + + /** Constant TRX_SLEEP for sub-register @ref SR_TRX_STATUS */ + TRX_SLEEP = (0x0F), + + /** Constant BUSY_RX_AACK for sub-register @ref SR_TRX_STATUS */ + BUSY_RX_AACK = (0x11), + + /** Constant BUSY_TX_ARET for sub-register @ref SR_TRX_STATUS */ + BUSY_TX_ARET = (0x12), + + /** Constant RX_AACK_ON for sub-register @ref SR_TRX_STATUS */ + RX_AACK_ON = (0x16), + + /** Constant TX_ARET_ON for sub-register @ref SR_TRX_STATUS */ + TX_ARET_ON = (0x19), + + /** Constant RX_ON_NOCLK for sub-register @ref SR_TRX_STATUS */ + RX_ON_NOCLK = (0x1C), + + /** Constant RX_AACK_ON_NOCLK for sub-register @ref SR_TRX_STATUS */ + RX_AACK_ON_NOCLK = (0x1D), + + /** Constant BUSY_RX_AACK_NOCLK for sub-register @ref SR_TRX_STATUS */ + BUSY_RX_AACK_NOCLK = (0x1E), + + /** Constant STATE_TRANSITION_IN_PROGRESS for sub-register @ref + * SR_TRX_STATUS */ + STATE_TRANSITION_IN_PROGRESS = (0x1F) +}tal_trx_status_t; + +/** + * sub-register IRQ_7_BAT_LOW IRQ_6_TRX_UR IRQ_5_AMI IRQ_4_CCA_ED_DONE + * IRQ_3_TRX_END IRQ_2_RX_START + * IRQ_1_PLL_UNLOCK IRQ_0_PLL_LOCK in register IRQ_STATUS + */ +typedef enum trx_irq_reason_tag { + /** Constant TRX_IRQ_7_BAT_LOW for sub-register @ref SR_IRQ_7_BAT_LOW */ + TRX_IRQ_7_BAT_LOW = (0x80), + + /** Constant TRX_IRQ_6_TRX_UR for sub-register @ref SR_IRQ_6_TRX_UR */ + TRX_IRQ_6_TRX_UR = (0x40), + + /** Constant TRX_IRQ_5_AMI for sub-register @ref SR_IRQ_5_AMI */ + TRX_IRQ_5_AMI = (0x20), + + /** Constant TRX_IRQ_4_CCA_ED_DONE for sub-register @ref + * SR_IRQ_4_CCA_ED_DONE */ + TRX_IRQ_4_CCA_ED_DONE = (0x10), + + /** Constant TRX_IRQ_3_TRX_END for sub-register @ref SR_IRQ_3_TRX_END */ + TRX_IRQ_3_TRX_END = (0x08), + + /** Constant TRX_IRQ_2_RX_START for sub-register @ref SR_IRQ_2_RX_START + **/ + TRX_IRQ_2_RX_START = (0x04), + + /** Constant TRX_IRQ_1_PLL_UNLOCK for sub-register @ref + * SR_IRQ_1_PLL_UNLOCK */ + TRX_IRQ_1_PLL_UNLOCK = (0x02), + + /** Constant TRX_IRQ_0_PLL_LOCK for sub-register @ref SR_IRQ_0_PLL_LOCK + **/ + TRX_IRQ_0_PLL_LOCK = (0x01), + + /** No interrupt is indicated by IRQ_STATUS register */ + TRX_NO_IRQ = (0x00) +} trx_irq_reason_t; + +/** sub-register TRAC_STATUS in register TRX_STATE */ +typedef enum trx_trac_status_tag { + /** Constant TRAC_SUCCESS for sub-register @ref SR_TRAC_STATUS */ + TRAC_SUCCESS = (0x00), + + /** Constant TRAC_SUCCESS_DATA_PENDING for sub-register @ref + * SR_TRAC_STATUS */ + TRAC_SUCCESS_DATA_PENDING = (0x01), + + /** Constant TRAC_SUCCESS_WAIT_FOR_ACK for sub-register @ref + * SR_TRAC_STATUS */ + TRAC_SUCCESS_WAIT_FOR_ACK = (0x02), + + /** Constant TRAC_CHANNEL_ACCESS_FAILURE for sub-register @ref + * SR_TRAC_STATUS */ + TRAC_CHANNEL_ACCESS_FAILURE = (0x03), + + /** Constant TRAC_NO_ACK for sub-register @ref SR_TRAC_STATUS */ + TRAC_NO_ACK = (0x05), + + /** Constant TRAC_INVALID for sub-register @ref SR_TRAC_STATUS */ + TRAC_INVALID = (0x07) +} trx_trac_status_t; + + +#endif /* AT86RF212B_H */ diff --git a/driver/software/RF212b/phy/at86rf212b/inc/phy_internal.h b/driver/software/RF212b/phy/at86rf212b/inc/phy_internal.h new file mode 100644 index 0000000..e6d4ed8 --- /dev/null +++ b/driver/software/RF212b/phy/at86rf212b/inc/phy_internal.h @@ -0,0 +1,532 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + + +/* Prevent double inclusion */ +#ifndef PHY_INTERNAL_H +#define PHY_INTERNAL_H + +/* === INCLUDES ============================================================ */ + +#include "../../../resources/buffer/inc/bmm.h" +#include "../../../resources/queue/inc/qmm.h" +#include "../../inc/phy_constants.h" +#include "phy_trx_reg_access.h" +#include "../../inc/phy.h" +#include "at86rf.h" +#include "xc.h" +#include "definitions.h" + +/** + * \ingroup group_tal + * \defgroup group_tal_212b AT86RF212B Transceiver Abstraction Layer + * The AT86RF212B is a low-power ,low voltage 700/800/900 MHz radio transceiver + * designed for industrial + * and consumer ZigBee/IEEE 802.15.4, 6LoWPAN, RF4CE and high data rate sub 1GHz + * ISM band applications. + * The Transceiver Abstraction Layer (TAL) implements the transceiver specific + * functionalities and + * provides interfaces to the upper layers (like IEEE 802.15.4 MAC )and uses + * the services of PAL. + */ + +/** + * \ingroup group_tal_212b + * \defgroup group_tal_state_machine_212b TAL State Machine + * The different operating states of the Transceiver are controlled by the TAL + * state machine. + * + */ + +/** + * \ingroup group_tal_212b + * \defgroup group_tal_init_212b TAL Initialization and reset + * Performs initialization and reset functionalities of the transceiver + * + */ + +/** + * \ingroup group_tal_212b + * \defgroup group_tal_ed_212b TAL Energy Detection + * Performs the ED scan functionalities. + * + */ + +/** + * \ingroup group_tal_212b + * \defgroup group_tal_irq_212b Transceiver Interrupt Handling + * Handles Transceiver related Interrupts. + * + */ + +/** + * \ingroup group_tal_212b + * \defgroup group_tal_pib_212b TAL PIB Storage + * The PIB(Pan Information Base) attributes related to the TAL are Stored and + * handled by the TAL PIB storage. + * + */ + +/** + * \ingroup group_tal_212b + * \defgroup group_tal_tx_212 TAL Frame Transmission Unit + * The Frame Transmission Unit generates and transmits the frames using PAL . + * + */ + +/** + * \ingroup group_tal_tx_212b + * \defgroup group_tal_tx_csma_212b TAL CSMA/CA Module + * Performs channel access mechanism for frame transmission + * For Detailed information refer CSMA-CA algorithm section of IEEE Std + * 802.15.4-2006 + * + */ + +/** + * \ingroup group_tal_212b + * \defgroup group_tal_rx_212b TAL Frame Reception Unit + * The Frame Reception Unit reads/uploads the incoming frames . + * + */ + + +/* === TYPES =============================================================== */ + +/** TAL states */ + +typedef enum tal_state_tag { + PHY_IDLE = 0, + PHY_TX_AUTO = 1, + PHY_TX_DONE = 2, + PHY_SLOTTED_CSMA = 3, + PHY_ED_RUNNING = 4, + PHY_ED_DONE = 5, +#ifdef SW_CONTROLLED_CSMA + PHY_BACKOFF, + PHY_CCA, + PHY_CSMA_CONTINUE, + PHY_CCA_DONE +#endif + +} tal_state_t; + + +/* Structure implementing the PIB values stored in TAL */ +typedef __PACKED_STRUCT tal_pib_tag { + /** + * 64-bit (IEEE) address of the node. + */ + uint64_t IeeeAddress; + + /** + * Supported channels + * + * Legacy trx: + * Bit mask, whereas each bit position set indicates that the channel, + * corresponding to this particular bit position, is actually supported + * + * Multi-Trx devices: + * Min channel: Low word of variable SupportedChannels: + *(uint16_t)(SupportedChannels) + * Max channel: High word of variable SupportedChannels: + *(uint16_t)(SupportedChannels >> 16) + */ + uint32_t SupportedChannels; + + + /** + * 16-bit short address of the node. + */ + uint16_t ShortAddress; + + /** + * 16-bit PAN ID + */ + uint16_t PANId; + + /** + * Maximum number of symbols in a frame: + * = phySHRDuration + ceiling([aMaxPHYPacketSize + 1] x + * phySymbolsPerOctet) + */ + uint16_t MaxFrameDuration; + + /** + * CCA Mode + */ + uint8_t CCAMode; + + /** + * Current RF channel to be used for all transmissions and receptions. + */ + + uint8_t CurrentChannel; + + /** + * The maximum number of back-offs the CSMA-CA algorithm will attempt + * before declaring a CSMA_CA failure. + */ + uint8_t MaxCSMABackoffs; + + /** + * The minimum value of the backoff exponent BE in the CSMA-CA + * algorithm. + */ + uint8_t MinBE; + + /** + * Indicates if the node is a PAN coordinator or not. + */ + bool PrivatePanCoordinator; + + /** + * Default value of transmit power of transceiver + * using IEEE defined format of phyTransmitPower. + */ + uint8_t TransmitPower; + + /** + * Current channel page. + */ + uint8_t CurrentPage; + + /** + * Duration of the synchronization header (SHR) in symbols for the + * current PHY. + */ + uint8_t SHRDuration; + + /** + * Number of symbols per octet for the current PHY. + */ + uint8_t SymbolsPerOctet; + + /** + * The maximum value of the backoff exponent BE in the CSMA-CA + * algorithm. + */ + uint8_t MaxBE; + + /** + * The maximum number of retries allowed after a transmission failure. + */ + uint8_t MaxFrameRetries; + +#ifdef PROMISCUOUS_MODE + + /** + * Promiscuous Mode + */ + bool PromiscuousMode; +#endif + +} tal_pib_t; + + +/* parameter types in transceiver */ +typedef struct phy_config_param_tag { + bool antDiversity; + bool antSelect; + uint8_t antCtrl; + bool extPACtrl; + bool aackPromMode; + int8_t txPwr; + uint8_t rxSens; + bool rxSafeMode; + bool rxAutoAck; + bool rxReservedFrame; + bool reservedFrameFiltering; +}phy_config_param_t; + +typedef struct phy_info_tag{ + tal_state_t tal_state; + tal_trx_status_t tal_trx_status; + bool tal_rx_on_required; + uint8_t last_frame_length; + volatile bool tal_awake_end_flag; + phy_config_param_t phy_config_param; + uint32_t phyVersion; + uint8_t last_pkt_ed_level; + uint8_t last_pkt_lqi; +}phy_info_t; + +#define RX_PRIORITY_ARB_SET 0x01 +#define TX_PRIORITY_ARB_SET 0x01 + +#define DELAY_OK 0x00 +#define TIME_SENSITIVE 0x01 + + + + +#define TRX_SLP_TR_HIGH() SLP_TR_Set() + +#define TRX_SLP_TR_LOW() SLP_TR_Clear() + +#define TRX_RST_HIGH() _RST_Set() + +#define TRX_RST_LOW() _RST_Clear() + +#define TRX_SEL_HIGH() SPI_SS_Set() + +#define TRX_SEL_LOW() SPI_SS_Clear() + + +/* + * Default value of custom TAL PIB channel page + */ +#ifdef CHINESE_BAND +#define PHY_CURRENT_PAGE_DEFAULT (0x05) +#else +#ifdef OQPSK_TEST +#define PHY_CURRENT_PAGE_DEFAULT (0x02) +#else +#define PHY_CURRENT_PAGE_DEFAULT (0x00) +#endif /* #ifdef OQPSK_TEST */ +#endif /* #ifdef CHINESE_BAND */ + +/* + * Default value of maximum number of symbols in a frame + */ +#define PHY_MAX_FRAME_DURATION_DEFAULT (MAX_FRAME_DURATION) + +/* + * Default value of duration of the synchronization header (SHR) in symbols + * for the current PHY + */ +#define PHY_SHR_DURATION_DEFAULT (NO_OF_SYMBOLS_PREAMBLE_SFD) + +/* + * Default value of number of symbols per octet for the current PHY + */ +#define PHY_SYMBOLS_PER_OCTET_DEFAULT (SYMBOLS_PER_OCTET) + +/* + * Default value of maximum backoff exponent used while performing csma ca + */ +#define PHY_MAXBE_DEFAULT (0x05) + +/* + * Default value of PIB attribute macMaxFrameRetries + */ +#define PHY_MAXFRAMERETRIES_DEFAULT (0x03) + +/* + * Default value of maximum csma ca backoffs + */ +#define PHY_MAX_CSMA_BACKOFFS_DEFAULT (0x04) + +/* + * Default value of minimum backoff exponent used while performing csma ca + */ +#define PHY_MINBE_DEFAULT (0x03) + +/* + * Value of a broadcast PAN ID + */ +#define PHY_PANID_BC_DEFAULT (0xFFFF) + +/* + * Default value of short address + */ +#define PHY_SHORT_ADDRESS_DEFAULT (0xFFFF) + +/* + * Default value of current channel in TAL + */ +#define PHY_CURRENT_CHANNEL_DEFAULT (0x01) + +/* + * Default value of promiscuous mode in TAL + */ +#define PHY_PIB_PROMISCUOUS_MODE_DEFAULT (false) + +#ifndef CUSTOM_DEFAULT_TX_PWR + +/* + * Default value of transmit power of transceiver: Use highest tx power + */ +#define PHY_TRANSMIT_POWER_DEFAULT (TX_PWR_TOLERANCE | 0x0AU) +#endif + +/* + * Default value CCA mode + */ +#define PHY_CCA_MODE_DEFAULT (TRX_CCA_MODE1) + + +/* + * Default value beacon order set to 15 + */ +#define TAL_BEACON_ORDER_DEFAULT (15) + +/* + * Default value supeframe order set to 15 + */ +#define TAL_SUPERFRAME_ORDER_DEFAULT (15) + +/* + * Default value of BeaconTxTime + */ +#define TAL_BEACON_TX_TIME_DEFAULT (0x00000000) + +/* + * Default value of BatteryLifeExtension. + */ +#define PHY_BATTERY_LIFE_EXTENSION_DEFAULT (false) + +/* + * Default value of PAN Coordiantor custom TAL PIB + */ +#define PHY_PAN_COORDINATOR_DEFAULT (false) + +#ifndef ANTENNA_DEFAULT +#define ANTENNA_DEFAULT (ANT_CTRL_1) +#endif + +#ifdef ENABLE_QUEUE_CAPACITY +#define PHY_INCOMING_FRAME_QUEUE_CAPACITY (255) +#endif /* ENABLE_QUEUE_CAPACITY */ + +#define NUMBER_OF_PHY_TIMERS (1) + + +/* === EXTERNALS =========================================================== */ + +/* Global TAL variables */ +extern tal_pib_t tal_pib; +extern PHY_FrameInfo_t *mac_frame_ptr; +extern queue_t tal_incoming_frame_queue; +extern uint8_t *tal_frame_to_tx; +extern buffer_t *tal_rx_buffer; +extern phy_info_t phy_info; + +/* === MACROS ============================================================== */ + +/** + * Conversion of number of PSDU octets to duration in microseconds + */ +#ifdef HIGH_DATA_RATE_SUPPORT +#define TAL_PSDU_US_PER_OCTET(octets) \ + ( \ + tal_pib.CurrentPage == 0 ? \ + (tal_pib.CurrentChannel == 0 ? (uint16_t)(octets) * \ + 400 : (uint16_t)(octets) * 200) : \ + ( \ + tal_pib.CurrentPage == 2 ? \ + (tal_pib.CurrentChannel == 0 ? (uint16_t)(octets) * \ + 80 : (uint16_t)(octets) * 32) : \ + ( \ + tal_pib.CurrentPage == 5 ? \ + ((uint16_t)(octets) * 32) : \ + ( \ + tal_pib.CurrentPage == 16 ? \ + (tal_pib.CurrentChannel == \ + 0 ? (uint16_t)(octets) * \ + 40 : (uint16_t)(octets) * 16) : \ + ( \ + /* tal_pib.CurrentPage == 17 ? + **/ \ + (tal_pib.CurrentChannel == \ + 0 ? (uint16_t)(octets) * \ + 20 : (uint16_t)(octets) * 8) \ + ) \ + ) \ + ) \ + ) \ + ) +#else /* #ifdef not HIGH_DATA_RATE_SUPPORT */ +#define TAL_PSDU_US_PER_OCTET(octets) \ + ( \ + tal_pib.CurrentPage == 0 ? \ + (tal_pib.CurrentChannel == 0 ? (uint16_t)(octets) * \ + 400 : (uint16_t)(octets) * 200) : \ + ( \ + tal_pib.CurrentPage == 2 ? \ + (tal_pib.CurrentChannel == 0 ? (uint16_t)(octets) * \ + 80 : (uint16_t)(octets) * 32) : \ + ( \ + /* tal_pib.CurrentPage == 5 ? */ \ + (uint16_t)(octets) * 32 \ + ) \ + ) \ + ) +#endif + +#define TRX_IRQ_DEFAULT TRX_IRQ_3_TRX_END + + +/* === PROTOTYPES ========================================================== */ + +/* + * Prototypes from tal.c + */ + +/** + * \brief Sets transceiver state + * + * \param trx_cmd needs to be one of the trx commands + * + * \return current trx state + * \ingroup group_tal_state_machine_233 + */ +tal_trx_status_t set_trx_state(trx_cmd_t trx_cmd); + + + +tal_trx_status_t tal_get_trx_status(void); + +/* + * Prototypes from tal_ed.c + */ + + +/** + * \brief Scan done + * + * This function updates the max_ed_level and invokes the callback function + * tal_ed_end_cb(). + * + * \ingroup group_tal_ed + */ +void ed_scan_done(void); +void trx_ed_irq_handler_cb(void); +void tal_trx_wakeup(void); +void trx_delay_micros(uint32_t us); +void trx_delay_millis(uint32_t ms); +void trx_delay_loop(void *hw, uint32_t cycles); +void trx_irq_flag_clear(void); +PHY_Retval_t tal_dump_registers(uint16_t start_addr, uint16_t end_addr, + uint8_t *value); +PHY_Retval_t tal_set_frequency_regs(uint8_t cc_band, uint8_t cc_number); + +PHY_Retval_t tal_set_frequency(float frequency); + +PHY_Retval_t tal_calculate_frequency(uint8_t cc_band, uint8_t cc_number, + float *freq); + + +#endif /* TAL_INTERNAL_H */ diff --git a/driver/software/RF212b/phy/at86rf212b/inc/phy_irq_handler.h b/driver/software/RF212b/phy/at86rf212b/inc/phy_irq_handler.h new file mode 100644 index 0000000..6671820 --- /dev/null +++ b/driver/software/RF212b/phy/at86rf212b/inc/phy_irq_handler.h @@ -0,0 +1,74 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* Prevent double inclusion */ +#ifndef PHY_IRQ_HANDLER_H +#define PHY_IRQ_HANDLER_H + +/* === INCLUDES ============================================================ */ + +/* === EXTERNALS =========================================================== */ + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* === PROTOTYPES ========================================================== */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup group_tal_irq_233 + * @{ + */ + +/** + * \brief Transceiver interrupt handler + * + * This function handles the transceiver generated interrupts. + */ +void trx_irq_handler_cb(void); + +/** + * \brief Transceiver interrupt handler for awake end IRQ + * + * This function handles the transceiver awake end interrupt. + */ + +void trx_irq_awake_handler_cb(void); + +void EIC_interrupt_cb(uintptr_t context); + + +/* ! @} */ +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* TAL_IRQ_HANDLER_H */ + +/* EOF */ diff --git a/driver/software/RF212b/phy/at86rf212b/inc/phy_pib.h b/driver/software/RF212b/phy/at86rf212b/inc/phy_pib.h new file mode 100644 index 0000000..b1c6c5c --- /dev/null +++ b/driver/software/RF212b/phy/at86rf212b/inc/phy_pib.h @@ -0,0 +1,152 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* Prevent double inclusion */ +#ifndef PHY_PIB_H +#define PHY_PIB_H + +/* === INCLUDES ============================================================ */ + +/* === EXTERNALS =========================================================== */ + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +#ifndef CUSTOM_PWR_TABLE + +/** + * Tx power table + * Table maps tx power value to register value + */ +#define TX_PWR_TABLE_NA \ + /* Tx power, dBm 11 10 9 8 7 6 5 4 + * 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 + * -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 + * -19 -20 -21 -22 -23 -24 -25 */ \ + /* Register value */ 0xc0, 0xc1, 0x80, 0x82, 0x83, 0x84, 0x40, 0x86, \ + 0x00, 0x01, 0x02, 0x03, 0x04, 0x27, 0x05, 0x07, 0x08, \ + 0x91, 0x09, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, \ + 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x19, 0x1a, 0x1b, \ + 0x1c, 0x1d + +#define TX_PWR_TABLE_EU \ + /* Tx power, dBm 11 10 9 8 7 6 5 4 + * 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 + * -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 + * -19 -20 -21 -22 -23 -24 -25 */ \ + /* Register value */ 0xa0, 0x80, 0xe4, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, \ + 0xcb, 0xcc, 0xcd, 0xad, 0x47, 0x48, 0x49, 0x29, 0x90, \ + 0x91, 0x93, 0x94, 0x2f, 0x30, 0x31, 0x0f, 0x10, 0x11, \ + 0x12, 0x13, 0x14, 0x15, 0x17, 0x18, 0x19, 0x1a, 0x1b, \ + 0x1c, 0x1d + +#define TX_PWR_TABLE_CHINA \ + /* Tx power, dBm 11 10 9 8 7 6 5 4 + * 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 + * -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 + * -19 -20 -21 -22 -23 -24 -25 */ \ + /* Register value */ 0xc1, 0xe3, 0xe4, 0xc5, 0xe7, 0xe8, 0xe9, 0xea, \ + 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xaf, 0x26, 0x27, 0x28, \ + 0x29, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, \ + 0x0f, 0x10, 0x11, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, \ + 0x19, 0x1a + +#define TX_PWR_TABLE_SIZE (37) + +#define MAX_TX_PWR (11) +#define MIN_TX_PWR (-25) +#define DEFAULT_TX_PWR_CHINA_CH_0_3 (4) + +/* \todo use one max power for each band (EU, NA, China) */ +/* max power of standard compliant modes */ +#define MAX_TX_PWR_BPSK_40 MAX_TX_PWR /* NA, band: 915MHz */ +#define MAX_TX_PWR_OQPSK_SIN_250 MAX_TX_PWR /* NA, band: 915MHz */ +#define MAX_TX_PWR_BPSK_20 (MAX_TX_PWR) /* EU, band: 868MHz */ +#define DEFAULT_TX_PWR_BPSK_20 (6) /* EU, band: 868MHz */ +#define MAX_TX_PWR_OQPSK_SIN_RC_100 (MAX_TX_PWR) /* EU, band: 868MHz */ +#define MAX_TX_PWR_OQPSK_RC_250 (MAX_TX_PWR) /* China, band: 780MHz + **/ +#define DEFAULT_TX_PWR_OQPSK_RC_250_500 (10) /* China, band: 780MHz + **/ +#define DEFAULT_TX_PWR_OQPSK_SIN_RC_100_200_400 (3) /* EU, band: 868MHz + **/ + +/* max power of proprietary modes */ +#ifdef HIGH_DATA_RATE_SUPPORT +#define MAX_TX_PWR_OQPSK_SIN_500 MAX_TX_PWR /* NA, band: 915MHz */ +#define MAX_TX_PWR_OQPSK_SIN_1000 MAX_TX_PWR /* NA, band: 915MHz */ +#define MAX_TX_PWR_OQPSK_SIN_RC_200 (MAX_TX_PWR) /* EU, band: 868MHz */ +#define MAX_TX_PWR_OQPSK_SIN_RC_400 (MAX_TX_PWR) /* EU, band: 868MHz */ +#define MAX_TX_PWR_OQPSK_RC_500 (MAX_TX_PWR) /* China, band: 780MHz + **/ +#define MAX_TX_PWR_OQPSK_RC_1000 (MAX_TX_PWR) /* China, band: 780MHz + **/ + +/* old stuff + * #define MAX_TX_PWR_OQPSK_200 MAX_TX_PWR_OQPSK_100 + * #define MAX_TX_PWR_OQPSK_400 MAX_TX_PWR_OQPSK_100 + * #define MAX_TX_PWR_OQPSK_SIN_500 (7) + * #define MAX_TX_PWR_OQPSK_SIN_1000 (4) + */ +#endif /* #ifdef HIGH_DATA_RATE_SUPPORT */ + +#endif /* #ifndef CUSTOM_PWR_TABLE */ +/* === PROTOTYPES ========================================================== */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup group_tal_pib_212b + * @{ + */ + +/** + * \brief Initialize the TAL PIB + * + * This function initializes the TAL information base attributes + * to their default values. + */ +void init_tal_pib(void); + +/** + * \brief Write all shadow PIB variables to the transceiver + * + * This function writes all shadow PIB variables to the transceiver. + * It is assumed that the radio does not sleep. + */ +void write_all_tal_pib_to_trx(void); + +/* ! @} */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* TAL_PIB_H */ + +/* EOF */ diff --git a/driver/software/RF212b/phy/at86rf212b/inc/phy_rx.h b/driver/software/RF212b/phy/at86rf212b/inc/phy_rx.h new file mode 100644 index 0000000..b41050d --- /dev/null +++ b/driver/software/RF212b/phy/at86rf212b/inc/phy_rx.h @@ -0,0 +1,73 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* Prevent double inclusion */ +#ifndef PHY_RX_H +#define PHY_RX_H + +/* === INCLUDES ============================================================ */ + +/* === EXTERNALS =========================================================== */ + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* === PROTOTYPES ========================================================== */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup group_tal_rx_233 + * @{ + */ + +/** + * \brief Handle received frame interrupt + * + * This function handles transceiver interrupts for received frames and + * uploads the frames from the trx. + */ + +void handle_received_frame_irq(void); + +/** + * \brief Parses received frame and create the PHY_FrameInfo_t structure + * + * This function parses the received frame and creates the PHY_FrameInfo_t + * structure to be sent to the MAC as a parameter of tal_rx_frame_cb(). + * + * \param buf Pointer to the buffer containing the received frame + */ +void process_incoming_frame(buffer_t *buf_ptr); + +/* ! @} */ +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* TAL_RX_H */ diff --git a/driver/software/RF212b/phy/at86rf212b/inc/phy_tx.h b/driver/software/RF212b/phy/at86rf212b/inc/phy_tx.h new file mode 100644 index 0000000..3eecbcf --- /dev/null +++ b/driver/software/RF212b/phy/at86rf212b/inc/phy_tx.h @@ -0,0 +1,85 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* Prevent double inclusion */ +#ifndef PHY_TX_H +#define PHY_TX_H + +/* === INCLUDES ============================================================ */ +#include "../../../phy/inc/phy.h" +/* === EXTERNALS =========================================================== */ + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* === PROTOTYPES ========================================================== */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup group_tal_tx + * @{ + */ + +/** + * \brief Handles interrupts issued due to end of transmission + * + * \param underrun_occured true if under-run has occurred + */ + +void handle_tx_end_irq(bool underrun_occured); + +/** + * \brief Sends frame using trx features to handle CSMA and re-transmissions + * + * \param csma_mode Indicates the CSMA Mode used + * \param tx_retries Flag indicating if transmission retries are requested + * by the MAC layer + */ + +void send_frame(PHY_CSMAMode_t csmaMode, bool txRetries); + +/** + * \brief Implements the handling of the transmission end. + * + * This function handles the callback for the transmission end. + */ +void tx_done_handling(void); + + +void tal_start_retransmission_timer(uint32_t us); + +/* ! @} */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* TAL_TX_H */ + +/* EOF */ diff --git a/driver/software/RF212b/phy/at86rf212b/src/phy_ed.c b/driver/software/RF212b/phy/at86rf212b/src/phy_ed.c new file mode 100644 index 0000000..4e14dd4 --- /dev/null +++ b/driver/software/RF212b/phy/at86rf212b/src/phy_ed.c @@ -0,0 +1,217 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* === INCLUDES ============================================================ */ + +#include +#include +#include +#include "../../../pal/inc/pal.h" +#include "../../../phy/inc/phy.h" +#include "../../../phy/inc/phy_tasks.h" +#include "../../../phy/inc/ieee_phy_const.h" +#include "../../inc/phy_constants.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../at86rf/inc/phy_internal.h" +#include "../../../phy/at86rf/inc/phy_irq_handler.h" +#include "../../../phy/at86rf/inc/phy_trx_reg_access.h" +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/** + * \addtogroup group_tal_ed_212b + * @{ + */ + +/* Constant define for the ED scaling: register value at -35dBm */ +#define CLIP_VALUE_REG (62U) + +#define MIN_ED_VAL (20U) +#define MAX_ED_VAL (83U) +/* + * Scan duration formula: \f$aBaseSuperframeDuration (2^SD + 1)\f$ + * where \f$0 <= SD <= 14\f$ + */ +#define CALCULATE_SYMBOL_TIME_SCAN_DURATION(SD) \ + (aBaseSuperframeDuration * ((1UL << (SD)) + 1UL)) + +/* === GLOBALS ============================================================= */ + +/** + * The peak_ed_level is the maximum ED value received from the transceiver for + * the specified Scan Duration. + */ +static uint8_t max_ed_level; +static uint32_t sampler_counter; + +/* === PROTOTYPES ========================================================== */ + +/* ! @} */ + +/* === IMPLEMENTATION ====================================================== */ + +/* + * \brief Starts ED Scan + * + * This function starts an ED Scan for the scan duration specified by the + * MAC layer. + * + * \param scan_duration Specifies the ED scan duration in symbols + * + * \return MAC_SUCCESS - ED scan duration timer started successfully + * TAL_BUSY - TAL is busy servicing the previous request from MAC + * TAL_TRX_ASLEEP - Transceiver is currently sleeping + * FAILURE otherwise + */ +PHY_Retval_t PHY_EdStart(uint8_t scan_duration) +{ + /* + * Check if the TAL is in idle state. Only in idle state it can + * accept and ED request from the MAC. + */ + if (PHY_IDLE != phy_info.tal_state) { + if (phy_info.tal_trx_status == TRX_SLEEP) { + return PHY_TRX_ASLEEP; + } else { + + return PHY_BUSY; + } + } + /* + * Disable the transceiver interrupts to prevent frame reception + * while performing ED scan. + */ + pal_trx_irq_dis(); /* Disable transceiver main interrupt. */ + (void)set_trx_state(CMD_FORCE_PLL_ON); + (void)trx_reg_read(RG_IRQ_STATUS); /* Clear existing interrupts */ + trx_reg_bit_write(SR_RX_PDT_DIS, RX_DISABLE); + trx_reg_bit_write(SR_IRQ_MASK, (uint8_t)TRX_IRQ_4_CCA_ED_DONE); /* enable + * interrupt */ + pal_trx_irq_en(); /* Enable transceiver main interrupt. */ + + /* Make sure that receiver is switched on. */ + if (set_trx_state(CMD_RX_ON) != RX_ON) { + /* Restore previous configuration */ + trx_reg_bit_write(SR_RX_PDT_DIS, RX_ENABLE); + + trx_reg_write(RG_IRQ_MASK, (uint8_t)TRX_IRQ_DEFAULT); /* enable + * TRX_END + * interrupt */ + return PHY_FAILURE; + } + + /* Perform ED in TAL_ED_RUNNING state. */ + phy_info.tal_state = PHY_ED_RUNNING; + + /* write dummy value to start measurement */ + trx_reg_write(RG_PHY_ED_LEVEL, 0xFF); + + max_ed_level = 0; /* reset max value */ + + sampler_counter = CALCULATE_SYMBOL_TIME_SCAN_DURATION(scan_duration) / + ED_SAMPLE_DURATION_SYM; + + return PHY_SUCCESS; +} + +/** + * \brief ED Scan Interrupt + * + * This function handles an ED done interrupt from the transceiver. + * + */ +void trx_ed_irq_handler_cb(void) +{ + uint8_t ed_value; + + /* Read the ED Value. */ + ed_value = trx_reg_read(RG_PHY_ED_LEVEL); + + + /* + * Update the peak ED value received, if greater than the + * previously + * read ED value. + */ + if (ed_value > max_ed_level) { + max_ed_level = ed_value; + } + + sampler_counter--; + if (sampler_counter > 0U) { + /* write dummy value to start measurement */ + trx_reg_write(RG_PHY_ED_LEVEL, 0xFF); + } else { + + phy_info.tal_state = PHY_ED_DONE; + //OSAL_SEM_PostISR(&semPhyRxInternalHandler); + PHY_PostTask(false); + } +} + +/* + * \brief Scan done + * + * This function updates the max_ed_level and invokes the callback function + * tal_ed_end_cb(). + * + * \param parameter unused callback parameter + */ +void ed_scan_done(void) +{ + trx_reg_bit_write(SR_RX_PDT_DIS, RX_ENABLE); + + trx_reg_write(RG_IRQ_MASK, (uint8_t)TRX_IRQ_DEFAULT); /* enable TRX_END + * interrupt */ + pal_trx_irq_en(); /* Enable transceiver main interrupt. */ + + phy_info.tal_state = PHY_IDLE; /* ed scan is done */ + + (void)set_trx_state(CMD_RX_AACK_ON); + +#ifndef TRX_REG_RAW_VALUE + /* + * Scale ED result. + * Clip values to 0xFF if > -35dBm + */ + if (max_ed_level > CLIP_VALUE_REG) { + max_ed_level = 0xFF; + } else { + max_ed_level + = (uint8_t)(((uint16_t)max_ed_level * + 0xFFU) / CLIP_VALUE_REG); + } +#endif /* TRX_REG_RAW_VALUE */ + + PHY_EdEndCallback(max_ed_level); +} + + + + + + +/* EOF */ diff --git a/driver/software/RF212b/phy/at86rf212b/src/phy_helper.c b/driver/software/RF212b/phy/at86rf212b/src/phy_helper.c new file mode 100644 index 0000000..a775dec --- /dev/null +++ b/driver/software/RF212b/phy/at86rf212b/src/phy_helper.c @@ -0,0 +1,595 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* === INCLUDES ============================================================ */ + + + +#include "../../../pal/inc/pal.h" +#include "../../../phy/inc/phy.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../../phy/inc/phy_config.h" +#include "../../at86rf/inc/phy_internal.h" +#include "../../../phy/inc/ieee_phy_const.h" + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* === GLOBALS ============================================================= */ +extern int8_t tx_pwr_table[16]; + +/* === PROTOTYPES ========================================================== */ +extern uint8_t convert_phyTransmitPower_to_reg_value( + uint8_t phyTransmitPower_value); + +/* === IMPLEMENTATION ====================================================== */ + + + + +/* + * \brief Configures antenna diversity and selects antenna + * + * \param div_ctrl true/false to enable/disable antenna diversity + * \param ant_ctrl 0 or 3 when antenna diversity is enabled + * 1 or 2 to select antenna 1 or antenna 2 + * \return The value set in the TX_PWR bits + */ + +PHY_Retval_t PHY_ConfigAntennaDiversity(bool divCtrl, uint8_t antCtrl) +{ + PHY_Retval_t return_var = PHY_FAILURE; + if (true == divCtrl) { + /* do the configurations if diversity has to be enabled */ + trx_reg_bit_write(SR_ANT_CTRL, ANT_CTRL_0); + trx_reg_bit_write(SR_ANT_DIV_EN, ANT_DIV_ENABLE); + trx_reg_bit_write(SR_ANT_EXT_SW_EN, ANT_EXT_SW_ENABLE); + + /* check the values written in transceiver registers */ + if ((trx_reg_bit_read(SR_ANT_CTRL) == ANT_CTRL_0) && + (trx_reg_bit_read(SR_ANT_DIV_EN) == + ANT_DIV_ENABLE) && \ + (trx_reg_bit_read(SR_ANT_EXT_SW_EN) == + ANT_EXT_SW_ENABLE)) { + + + return_var = PHY_SUCCESS; + } else { + return_var = PHY_FAILURE; + } + } else { + /* do the configurations if diversity has to be disabled */ + trx_reg_bit_write(SR_ANT_DIV_EN, ANT_DIV_DISABLE); + trx_reg_bit_write(SR_ANT_EXT_SW_EN, ANT_EXT_SW_ENABLE); + if (antCtrl == ANT_CTRL_1) { + /* Enable A1/X2 */ + trx_reg_bit_write(SR_ANT_CTRL, ANT_CTRL_1); + phy_info.phy_config_param.antSelect = 0; + } else if (antCtrl == ANT_CTRL_2) { + /* Enable A2/X3 */ + trx_reg_bit_write(SR_ANT_CTRL, ANT_CTRL_2); + phy_info.phy_config_param.antSelect = 1; + } else if (antCtrl == ANT_CTRL_0 || antCtrl == ANT_CTRL_3) { + trx_reg_bit_write(SR_ANT_CTRL, ANT_CTRL_0); + antCtrl = 0; + } else { + return_var = PHY_INVALID_PARAMETER; + } + /* check the values written in transceiver registers */ + if ((trx_reg_bit_read(SR_ANT_CTRL) == antCtrl) && + (trx_reg_bit_read(SR_ANT_DIV_EN) == + ANT_DIV_DISABLE) && \ + (trx_reg_bit_read(SR_ANT_EXT_SW_EN) == + ANT_EXT_SW_DISABLE)) { + + return_var = PHY_SUCCESS; + } else { + return_var = PHY_FAILURE; + } + } + return return_var; +} + + + +/* + * \brief Configures the frequency to be set in transceiver + * + * \param frequency frequency value to be set + * \return PHY_SUCCESS if frequency is configured correctly + * MAC_INVALID_PARAMETER if out of range or incorrect values are + * given + * PHY_FAILURE if frequency registers are not configured properly + */ + + +PHY_Retval_t tal_set_frequency(float frequency) +{ + double epsilon = 0.000000001; + double dummy = 0.0; + uint8_t cc_number = 0; + uint8_t cc_band = 0; + tal_trx_status_t previous_trx_status = TRX_OFF; + /* frequency has to selected by CHANNEL register bits in PHY_CC_CCA*/ + if ((abs((double)frequency - dummy)) < epsilon) { + cc_band = 0; + cc_number = 0; + } + + + /* Choose CC_BAND & CC_NUMBER reg values for the input frequency */ + else if ((frequency >= CC_1_START_FREQUENCY && frequency <= + CC_1_END_FREQUENCY)) { + cc_band = CC_BAND_1; + cc_number = (uint8_t)((frequency - CC_1_START_FREQUENCY) * 10); + } else if (frequency >= CC_2_START_FREQUENCY && frequency <= + CC_2_END_FREQUENCY) { + cc_band = CC_BAND_2; + cc_number = (uint8_t)((frequency - CC_2_START_FREQUENCY) * 10); + } else if (frequency >= CC_3_START_FREQUENCY && frequency <= + CC_3_END_FREQUENCY) { + cc_band = CC_BAND_3; + cc_number = (uint8_t)((frequency - CC_3_START_FREQUENCY) * 10); + } + else if ((frequency >= CC_6_START_FREQUENCY) && + (frequency <= CC_6_END_FREQUENCY)) { + cc_band = CC_BAND_6; + cc_number = (uint8_t)((frequency - CC_6_START_FREQUENCY) * 10); + } + else if (frequency >= CC_4_START_FREQUENCY && frequency <= + CC_4_END_FREQUENCY) { + cc_band = CC_BAND_4; + } else if (frequency >= CC_5_START_FREQUENCY && frequency <= + CC_5_END_FREQUENCY) { + cc_band = CC_BAND_5; + } else { + /* input frequency did not fit in any of the bands */ + return PHY_INVALID_PARAMETER; + } + if (phy_info.tal_trx_status != TRX_OFF) { + previous_trx_status = RX_AACK_ON; /* any other than TRX_OFF + * state */ + do { + /* set TRX_OFF until it could be set; + * trx might be busy */ + } while (set_trx_state(CMD_TRX_OFF) != TRX_OFF); + } + + trx_reg_bit_write(SR_CC_BAND, cc_band); + trx_reg_write(RG_CC_CTRL_0, cc_number); + + /* Re-store previous trx state */ + if (previous_trx_status != TRX_OFF) { + /* Set to default state */ + (void)set_trx_state(CMD_RX_AACK_ON); + } + + /* check the values written in transceiver registers */ + if (trx_reg_bit_read(SR_CC_BAND) != cc_band || \ + trx_reg_read(RG_CC_CTRL_0) != cc_number) { + return PHY_FAILURE; + } else { + return PHY_SUCCESS; + } +} + + + +/** + * \brief to set the frequency based on CC_BAND and CC_NUMBER Registers + * + * \param cc_band band to be selected in cc_band register bits + * \param cc_number offset frequency to be selected in cc_number register bits + * \return PHY_SUCCESS if frequency is configured correctly + * MAC_INVALID_PARAMETER if out of range or incorrect values are + * given + * PHY_FAILURE if frequency registers are not configured properly + */ + +PHY_Retval_t tal_set_frequency_regs(uint8_t cc_band, uint8_t cc_number) +{ + tal_trx_status_t previous_trx_status = TRX_OFF; + + + /* check cc band and cc number fit in the range*/ + if (cc_band > MAX_CC_BAND) { + return PHY_INVALID_PARAMETER; + } else if (cc_band == CC_BAND_4 && cc_number > MIN_CC_BAND_4_OFFSET) { + return PHY_INVALID_PARAMETER; + } else if (cc_band == CC_BAND_5 && cc_number > MIN_CC_BAND_5_OFFSET) { + return PHY_INVALID_PARAMETER; + } + + /* + * Set trx to trx_off to avoid interruption in ongoing + * transaction + */ + if (phy_info.tal_trx_status != TRX_OFF) { + previous_trx_status = RX_AACK_ON; /* any other than TRX_OFF + * state */ + do { + /* set TRX_OFF until it could be set; + * trx might be busy */ + } while (set_trx_state(CMD_TRX_OFF) != TRX_OFF); + } + + trx_reg_bit_write(SR_CC_BAND, cc_band); + trx_reg_write(RG_CC_CTRL_0, cc_number); + + /* Re-store previous trx state */ + if (previous_trx_status != TRX_OFF) { + /* Set to default state */ + (void)set_trx_state(CMD_RX_AACK_ON); + } + + /* check the values written in transceiver registers */ + if (trx_reg_bit_read(SR_CC_BAND) != cc_band || \ + trx_reg_read(RG_CC_CTRL_0) != cc_number) { + return PHY_FAILURE; + } else { + return PHY_SUCCESS; + } +} + + + +/* + * \brief Calculate the frequency based on CC_BAND and CC_NUMBER Registers + * + * \param CC_BAND and CC_NUMBER register values to calculate the frequency + * \param *freq pointer where the calculated frequency value should be stored + * + * \return PHY_SUCCESS if frequency is configured correctly + * MAC_INVALID_PARAMETER if out of range or incorrect values are given + * PHY_FAILURE if frequency registers are not configured properly + */ + +PHY_Retval_t tal_calculate_frequency(uint8_t cc_band, uint8_t cc_number, + float *freq) +{ + + /* check cc band and cc number fit in the range*/ + if (cc_band > MAX_CC_BAND) { + return PHY_INVALID_PARAMETER; + } + + /* calculate frequency based on cc band and cc number*/ + switch (cc_band) { + case 0: + break; + + case 1: + { + *freq = CC_1_START_FREQUENCY + (0.1 * cc_number); + } + break; + + case 2: + { + *freq = CC_2_START_FREQUENCY + (0.1 * cc_number); + } + break; + + case 3: + { + *freq = CC_3_START_FREQUENCY + (0.1 * cc_number); + } + break; + + case 4: + { + if (cc_number > MIN_CC_BAND_4_OFFSET) { + return PHY_INVALID_PARAMETER; + } + + *freq = CC_4_START_FREQUENCY + cc_number; + } + break; + + case 5: + { + if (cc_number > MIN_CC_BAND_5_OFFSET) { + return PHY_INVALID_PARAMETER; + } + + *freq = CC_5_START_FREQUENCY + cc_number; + } + break; + + case 6: + *freq = CC_6_START_FREQUENCY + (0.1 * cc_number); + break; + default: + return PHY_INVALID_PARAMETER; + } + + return PHY_SUCCESS; + +} + + + +/* + * \brief Configures receiver sensitivity level + * + * \param pdt_level 0 to 15 levels of rx sensitivity + * \param PHY_SUCCESS if sensitivity level is configured correctly + * MAC_INVALID_PARAMETER pdt_level is out of range + * PHY_FAILURE otherwise + */ + +PHY_Retval_t PHY_ConfigRxSensitivity(uint8_t pdtLevel) +{ + uint8_t temp; + /* return invalid parameter if sensitivity level is out of range*/ + if (pdtLevel > MAX_PDT_LEVEL) { + return PHY_INVALID_PARAMETER; + } + /* configure sensitivity level*/ + trx_reg_bit_write(SR_RX_PDT_LEVEL, pdtLevel); + + temp = trx_reg_bit_read(SR_RX_PDT_LEVEL); + if (temp == pdtLevel) { + phy_info.phy_config_param.rxSens = pdtLevel; + return PHY_SUCCESS; + } else { + return PHY_FAILURE; + } +} + + + +/* + * \brief Configures promiscous mode in rx_aack_on mode + * + * \param prom_ctrl true/false to enable/disable prom mode + * + * \param PHY_SUCCESS if rxaack_prom_mode is configured correctly + * PHY_FAILURE otherwise + */ + +PHY_Retval_t PHY_ConfigRxPromiscuousMode(bool promCtrl) +{ + bool temp; + /* configure promiscuous mode */ + trx_reg_bit_write(SR_AACK_PROM_MODE, (uint8_t)promCtrl); + temp = (bool)trx_reg_bit_read(SR_AACK_PROM_MODE); + if (temp == promCtrl) { + phy_info.phy_config_param.aackPromMode = promCtrl; + return PHY_SUCCESS; + } else { + return PHY_FAILURE; + } +} + + + +/* + * \brief to get the current status of the transceiver + * + * \return status of the transceiver + */ +tal_trx_status_t tal_get_trx_status(void) +{ + if (phy_info.tal_trx_status == TRX_SLEEP) + { + return (TRX_SLEEP); + } + tal_trx_status_t trx_status; + /* Read the status from trx_status bits */ + trx_status = (tal_trx_status_t)trx_reg_bit_read(SR_TRX_STATUS); + return trx_status; +} + + + +/* + * \brief to read a current setting particular transceiver parameter + * \param parameter type of the parameter to be read + * \param *param_value pointer to the location where the current parameter value + * need to be + * stored + * \return MAC_INVALID_PARAMETER if the parameter is invalid + * PHY_SUCCESS otherwise + */ + +PHY_Retval_t PHY_GetTrxConfig(PHY_ConfigParam_t parameter, uint8_t *paramValue) +{ + switch (parameter) { + + case ANT_DIVERSITY: + *paramValue = trx_reg_bit_read(SR_ANT_DIV_EN); + break; + + case ANT_SELECT_: + *paramValue = trx_reg_bit_read(SR_ANT_SEL); + break; + + case ANT_CTRL_: + *paramValue = trx_reg_bit_read(SR_ANT_CTRL); + break; + + case AACK_PROMSCS_MODE: + *paramValue = trx_reg_bit_read(SR_AACK_PROM_MODE); + break; + + case CC_BAND: + *paramValue = trx_reg_bit_read(SR_CC_BAND); + break; + + case CC_NUMBER: + *paramValue = trx_reg_read(RG_CC_CTRL_0); + break; + + case TX_PWR: + *paramValue = trx_reg_bit_read(SR_TX_PWR); + break; + + case RX_SENS: + *paramValue = trx_reg_bit_read(SR_RX_PDT_LEVEL); + break; + + + case RX_AUTO_ACK: + *paramValue = trx_reg_bit_read(SR_AACK_DIS_ACK); + break; + + case RX_RESERVED_FRAME: + *paramValue = trx_reg_bit_read(SR_AACK_UPLD_RES_FT); + break; + + case FILTER_RESERVED_FRAME: + *paramValue = trx_reg_bit_read(SR_AACK_FLTR_RES_FT); + break; + + default: + return PHY_INVALID_PARAMETER; + break; + } + return PHY_SUCCESS; +} + + + + + + + +/* + * \brief This function is called to get the base RSSI value for respective + * radios + * + * \return value of the base RSSI value + */ +int8_t PHY_GetRSSIBaseVal(void) +{ + switch (tal_pib.CurrentPage) { + case 0: /* BPSK */ + if (tal_pib.CurrentChannel == 0) { + return(RSSI_BASE_VAL_BPSK_300_DBM); + } else { + return(RSSI_BASE_VAL_BPSK_300_DBM); + } + + case 2: /* O-QPSK */ + if (tal_pib.CurrentChannel == 0) { + return(RSSI_BASE_VAL_OQPSK_400_SIN_RC_DBM); + } else { + return(RSSI_BASE_VAL_OQPSK_400_SIN_RC_DBM); + } + + case 5: /* Chinese band */ + default: /* High data rate modes */ + return(RSSI_BASE_VAL_OQPSK_400_RC_DBM); + } +} + +/** + * \brief the automatic acknowledgment from Transceiver after packet reception + * + * \param enableAACK true to enable the automatic + * acknowledgment after reception + * + * \return PHY_SUCCESS if configured correctly + * PHY_FAILURE otherwise + */ + + +PHY_Retval_t PHY_ConfigAutoAck(bool enableAACK) +{ + trx_reg_bit_write(SR_AACK_DIS_ACK, (uint8_t)enableAACK); + /*check the configuration */ + if (trx_reg_bit_read(SR_AACK_DIS_ACK) == (uint8_t)enableAACK) { + phy_info.phy_config_param.rxAutoAck = enableAACK; + return PHY_SUCCESS; + } else { + return PHY_FAILURE; + } +} + + +PHY_Retval_t PHY_ConfigReservedFrameFiltering(bool recReservedFrame, bool bypassFrameFilter ) +{ + trx_reg_bit_write(SR_AACK_UPLD_RES_FT, (uint8_t)recReservedFrame); + + trx_reg_bit_write(SR_AACK_FLTR_RES_FT, (uint8_t)bypassFrameFilter); + + /*check the configuration */ + if ((trx_reg_bit_read(SR_AACK_UPLD_RES_FT) == (uint8_t)recReservedFrame) && + (trx_reg_bit_read(SR_AACK_FLTR_RES_FT) == (uint8_t)bypassFrameFilter)) + { + phy_info.phy_config_param.reservedFrameFiltering = bypassFrameFilter; + phy_info.phy_config_param.rxReservedFrame = recReservedFrame; + return PHY_SUCCESS; + } else { + return PHY_FAILURE; + } + + +} + + +/* + * \brief to read a particular range of transceiver registers + * + * \param reg_addr address of the transceiver register to be written + * \param value value to be written in the register + * + * \return PHY_SUCCESS if the register is written correctly + * MAC_INVALID_PARAMETER if the reg_addr is out of range + */ + +PHY_Retval_t tal_dump_registers(uint16_t start_addr, uint16_t end_addr, + uint8_t *value) +{ + uint16_t addr; + int8_t length; + + /*check start and end address, return invalid parameter if out of range + **/ + + if (start_addr > 0x3FU || end_addr > 0x3FU) { + return PHY_INVALID_PARAMETER; + } + + int16_t temp_length = (end_addr - start_addr); + length = (int8_t)(temp_length); + if (length < 0) { + /* return invalid parameter if start and end addresses are not + * in order*/ + return PHY_INVALID_PARAMETER; + } else { + /* Read and store the values in input address*/ + for (addr = start_addr; addr <= end_addr; addr++) { + *value = trx_reg_read((uint8_t)addr); + value++; + } + return PHY_SUCCESS; + } +} + + +/* EOF */ diff --git a/driver/software/RF212b/phy/at86rf212b/src/phy_irq_handler.c b/driver/software/RF212b/phy/at86rf212b/src/phy_irq_handler.c new file mode 100644 index 0000000..fdd4cf6 --- /dev/null +++ b/driver/software/RF212b/phy/at86rf212b/src/phy_irq_handler.c @@ -0,0 +1,127 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* === INCLUDES ============================================================ */ + +#include +#include +#include +#include "../../inc/phy.h" +#include "../../../pal/inc/pal.h" +#include "../../../phy/inc/ieee_phy_const.h" +#include "../../../resources/buffer/inc/bmm.h" +#include "../../../resources/queue/inc/qmm.h" +#include "../../../phy/at86rf/inc/phy_internal.h" +#include "../../at86rf/inc/phy_rx.h" +#include "../../at86rf/inc/at86rf.h" +#include "../inc/phy_internal.h" +#include "../../../phy/inc/phy_constants.h" +#include "../inc/phy_tx.h" +#include "../../../phy/at86rf/inc/phy_trx_reg_access.h" +#include "../../../phy/inc/phy_tasks.h" + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* === GLOBALS ============================================================= */ + +/* === PROTOTYPES ========================================================== */ + +/* === IMPLEMENTATION ====================================================== */ + +/* + * \brief Transceiver interrupt handler + * + * This function handles the transceiver generated interrupts. + */ +void trx_irq_handler_cb(void) +{ + trx_irq_reason_t trx_irq_cause; + + trx_irq_cause = (trx_irq_reason_t) trx_reg_read(RG_IRQ_STATUS); + + + if ((bool)((uint8_t)trx_irq_cause & (uint8_t)TRX_IRQ_4_CCA_ED_DONE)) { + if (phy_info.tal_state == PHY_ED_RUNNING){ + trx_ed_irq_handler_cb(); + } + + else if (phy_info.tal_trx_status == TRX_SLEEP ){ + trx_irq_awake_handler_cb(); + } + else{ + /*DO NOTHING*/ + } + + } + else if ((bool)((uint8_t)trx_irq_cause & (uint8_t)TRX_IRQ_3_TRX_END)) { + /* + * TRX_END reason depends on if the trx is currently used for + * transmission or reception. + */ + + if (phy_info.tal_state == PHY_TX_AUTO) + { + /* Get the result and push it to the queue. */ + if ((bool)((uint8_t)trx_irq_cause & (uint8_t)TRX_IRQ_6_TRX_UR)) { + handle_tx_end_irq(true); /* see tal_tx.c */ + } else { + handle_tx_end_irq(false); /* see tal_tx.c */ + } + } else { /* Other tal_state than TAL_TX_... */ + /* Handle rx interrupt. */ + handle_received_frame_irq(); /* see tal_rx.c */ + } + } + else{ + /*DO NOTHING*/ + } +} /* trx_irq_handler_cb() */ + +/* + * \brief Transceiver interrupt handler for awake end IRQ + * + * This function handles the transceiver awake end interrupt. + */ +void trx_irq_awake_handler_cb(void) +{ + /* Set the wake-up flag. */ + phy_info.tal_awake_end_flag = true; + trx_reg_write(RG_IRQ_MASK, (uint8_t)TRX_IRQ_DEFAULT); +} + + +void EIC_interrupt_cb(uintptr_t context) +{ + + TAL_PostTask(true); + +} + + + + +/* EOF */ diff --git a/driver/software/RF212b/phy/at86rf212b/src/phy_pib.c b/driver/software/RF212b/phy/at86rf212b/src/phy_pib.c new file mode 100644 index 0000000..72208b9 --- /dev/null +++ b/driver/software/RF212b/phy/at86rf212b/src/phy_pib.c @@ -0,0 +1,967 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* === INCLUDES ============================================================ */ +#include +#include +#include +#include "../../../phy/inc/phy.h" +#include "../../../phy/inc/ieee_phy_const.h" +#include "../../../phy/inc/phy_constants.h" +#include "../../at86rf/inc/phy_pib.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../../phy/at86rf/inc/phy_internal.h" + +/** + * \addtogroup group_tal_pib_212b + * @{ + */ + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + + + + +#define GET_CHINA_FREQ(x) (11 + (2 * x)) +/* === GLOBALS ============================================================= */ +/** + * Tx power table in flash. + */ +static const uint8_t tx_pwr_table_NA[TX_PWR_TABLE_SIZE] + = { TX_PWR_TABLE_NA} ; +static const uint8_t tx_pwr_table_EU[TX_PWR_TABLE_SIZE] + = { TX_PWR_TABLE_EU} ; +static const uint8_t tx_pwr_table_China[TX_PWR_TABLE_SIZE] + = { TX_PWR_TABLE_CHINA }; +/* === PROTOTYPES ========================================================== */ + +static void set_default_tx_pwr(void); + +static void limit_tx_pwr(void); + +static uint8_t convert_phyTransmitPower_to_reg_value(uint8_t phyTransmitPower_value); + +static bool apply_channel_page_configuration(uint8_t ch_page); + + + + +/* ! @} */ +/* === IMPLEMENTATION ====================================================== */ + +/* + * \brief Initialize the TAL PIB + * + * This function initializes the TAL information base attributes + * to their default values. + */ +void init_tal_pib(void) +{ + tal_pib.MaxCSMABackoffs = PHY_MAX_CSMA_BACKOFFS_DEFAULT; + tal_pib.MinBE = PHY_MINBE_DEFAULT; + tal_pib.PANId = PHY_PANID_BC_DEFAULT; + tal_pib.ShortAddress = PHY_SHORT_ADDRESS_DEFAULT; + tal_pib.CurrentChannel = PHY_CURRENT_CHANNEL_DEFAULT; + tal_pib.CurrentPage = PHY_CURRENT_PAGE_DEFAULT; + tal_pib.MaxFrameDuration = PHY_MAX_FRAME_DURATION_DEFAULT; + tal_pib.SHRDuration = PHY_SHR_DURATION_DEFAULT; + tal_pib.SymbolsPerOctet = PHY_SYMBOLS_PER_OCTET_DEFAULT; + tal_pib.MaxBE = PHY_MAXBE_DEFAULT; + tal_pib.MaxFrameRetries = PHY_MAXFRAMERETRIES_DEFAULT; + tal_pib.TransmitPower = PHY_TRANSMIT_POWER_DEFAULT; + limit_tx_pwr(); + tal_pib.CCAMode = (uint8_t)PHY_CCA_MODE_DEFAULT; + tal_pib.PrivatePanCoordinator = PHY_PAN_COORDINATOR_DEFAULT; + +#ifdef PROMISCUOUS_MODE + tal_pib.PromiscuousMode = PHY_PIB_PROMISCUOUS_MODE_DEFAULT; +#endif + +#if (defined SW_CONTROLLED_CSMA) && (defined TX_OCTET_COUNTER) + tal_tx_octet_cnt = 0; +#endif +} + +/* + * \brief Write all shadow PIB variables to the transceiver + * + * This function writes all shadow PIB variables to the transceiver. + * It is assumed that the radio does not sleep. + */ +void write_all_tal_pib_to_trx(void) +{ + uint8_t *ptr_to_reg; + + ptr_to_reg = (uint8_t *)&tal_pib.PANId; + for (uint8_t iter = 0; iter < 2U; iter++) { + trx_reg_write((RG_PAN_ID_0 + iter), *ptr_to_reg); + ptr_to_reg++; + } + + ptr_to_reg = (uint8_t *)&tal_pib.IeeeAddress; + for (uint8_t iter = 0; iter < 8U; iter++) { + trx_reg_write((RG_IEEE_ADDR_0 + iter), *ptr_to_reg); + ptr_to_reg++; + } + + ptr_to_reg = (uint8_t *)&tal_pib.ShortAddress; + for (uint8_t iter = 0; iter < 2U; iter++) { + trx_reg_write((RG_SHORT_ADDR_0 + iter), *ptr_to_reg); + ptr_to_reg++; + } + + /* configure TX_ARET; CSMA and CCA */ + trx_reg_bit_write(SR_CCA_MODE, tal_pib.CCAMode); + +#ifdef SW_CONTROLLED_CSMA + + /* + * If receiver is enabled during backoff periods, + * CSMA and frame re-transmissions are handled by software. + * Setup trx for immediate transmission. + */ + trx_reg_bit_write(SR_MAX_FRAME_RETRIES, 0); + trx_reg_bit_write(SR_MAX_CSMA_RETRIES, 7); +#else + + trx_reg_bit_write(SR_MIN_BE, tal_pib.MinBE); + trx_reg_bit_write(SR_MAX_BE, tal_pib.MaxBE); +#endif + + trx_reg_bit_write(SR_AACK_I_AM_COORD, tal_pib.PrivatePanCoordinator); + + /* set phy parameter */ + + + + apply_channel_page_configuration(tal_pib.CurrentPage); + + { + uint8_t reg_value; + + reg_value = convert_phyTransmitPower_to_reg_value( + tal_pib.TransmitPower); + trx_reg_write(RG_PHY_TX_PWR, reg_value); + } + +#ifdef PROMISCUOUS_MODE + if (tal_pib.PromiscuousMode) { + (void)set_trx_state(CMD_RX_ON); + } +#endif +} + +/* + * \brief Gets a TAL PIB attribute + * + * This function is called to retrieve the transceiver information base + * attributes. + * + * \param[in] attribute TAL infobase attribute ID + * \param[out] value TAL infobase attribute value + * + * \return MAC_UNSUPPORTED_ATTRIBUTE if the TAL infobase attribute is not found + * MAC_SUCCESS otherwise + */ + +PHY_Retval_t PHY_PibGet(uint8_t attribute, uint8_t *value) +{ + switch (attribute) { + case macMaxCSMABackoffs: + *value = tal_pib.MaxCSMABackoffs; + break; + + case macMinBE: + *value = tal_pib.MinBE; + break; + + case macPANId: + *(uint16_t *)value = tal_pib.PANId; + break; + +#ifdef PROMISCUOUS_MODE + case macPromiscuousMode: + *(uint16_t *)value = tal_pib.PromiscuousMode; + break; +#endif + case macShortAddress: + *(uint16_t *)value = tal_pib.ShortAddress; + break; + + case phyCurrentChannel: + *value = tal_pib.CurrentChannel; + break; + + case phyChannelsSupported: + *(uint32_t *)value = tal_pib.SupportedChannels; + break; + + case phyTransmitPower: + *value = tal_pib.TransmitPower; + break; + + case phyCCAMode: + *value = tal_pib.CCAMode; + break; + + case phyCurrentPage: + *value = tal_pib.CurrentPage; + break; + + case phyMaxFrameDuration: + *(uint16_t *)value = tal_pib.MaxFrameDuration; + break; + + case phySymbolsPerOctet: + *value = tal_pib.SymbolsPerOctet; + break; + + case phySHRDuration: + *value = tal_pib.SHRDuration; + break; + + case macMaxBE: + *value = tal_pib.MaxBE; + break; + + case macMaxFrameRetries: + *value = tal_pib.MaxFrameRetries; + break; + + case macIeeeAddress: + *(uint64_t *)value = tal_pib.IeeeAddress; + break; + + case mac_i_pan_coordinator: + *(bool *)value = tal_pib.PrivatePanCoordinator; + break; + + case macAckWaitDuration: + + /* + * AT86RF212B does not support changing this value w.r.t. + * compliance operation. + */ + return PHY_UNSUPPORTED_ATTRIBUTE; + break; + + default: + /* Invalid attribute id */ + return PHY_UNSUPPORTED_ATTRIBUTE; + break; + } + + return PHY_SUCCESS; +} /* tal_pib_get() */ + + + +/* + * \brief Sets a TAL PIB attribute + * + * This function is called to set the transceiver information base + * attributes. + * + * \param attribute TAL infobase attribute ID + * \param value TAL infobase attribute value to be set + * + * \return MAC_UNSUPPORTED_ATTRIBUTE if the TAL info base attribute is not found + * TAL_BUSY if the TAL is not in TAL_IDLE state. An exception is + * macBeaconTxTime which can be accepted by TAL even if TAL is not + * in TAL_IDLE state. + * PHY_SUCCESS if the attempt to set the PIB attribute was successful + * TAL_TRX_ASLEEP if trx is in SLEEP mode and access to trx is required + */ +PHY_Retval_t PHY_PibSet(uint8_t attribute, PibValue_t *value) +{ + /* + * Do not allow any changes while ED or TX is done. + * We allow changes during RX, but it's on the user's own risk. + */ + if (phy_info.tal_state == PHY_ED_RUNNING) { + return PHY_BUSY; + } + + /* + * Distinguish between PIBs that need to be changed in trx directly + * and those that are simple variable udpates. + * Ensure that the transceiver is not in SLEEP. + * If it is in SLEEP, change it to TRX_OFF. + */ + + switch (attribute) { + case macMaxFrameRetries: + + /* + * The new PIB value is not immediately written to the + * transceiver. This is done on a frame-by-frame base. + */ + tal_pib.MaxFrameRetries = value->pib_value_8bit; + break; + + case macMaxCSMABackoffs: + + /* + * The new PIB value is not immediately written to the + * transceiver. This is done on a frame-by-frame base. + */ + tal_pib.MaxCSMABackoffs = value->pib_value_8bit; + break; + + +#ifdef PROMISCUOUS_MODE + case macPromiscuousMode: + tal_pib.PromiscuousMode = value->pib_value_8bit; + if (tal_pib.PromiscuousMode) { + PHY_TrxWakeup(); + + /* Check if receive buffer is available or queue is not + * full. */ + if (NULL == tal_rx_buffer) { + (void)set_trx_state(CMD_PLL_ON); + phy_info.tal_rx_on_required = true; + } else { + (void)set_trx_state(CMD_RX_ON); + } + } else { + (void)set_trx_state(CMD_TRX_OFF); + phy_info.tal_rx_on_required = false; + } + break; +#endif + + default: + + /* + * Following PIBs require access to trx. + * Therefore trx must be at least in TRX_OFF. + */ + + if (phy_info.tal_trx_status == TRX_SLEEP) { + /* While trx is in SLEEP, register cannot be accessed. + **/ + return PHY_TRX_ASLEEP; + } + + switch (attribute) { + case macMinBE: + tal_pib.MinBE = value->pib_value_8bit; + +#ifndef REDUCED_PARAM_CHECK + + /* + * macMinBE must not be larger than macMaxBE or + * calculation + * of macMaxFrameWaitTotalTime will fail. + */ + if (tal_pib.MinBE > tal_pib.MaxBE) { + tal_pib.MinBE = tal_pib.MaxBE; + } +#endif /* REDUCED_PARAM_CHECK */ +#ifndef SW_CONTROLLED_CSMA + trx_reg_bit_write(SR_MIN_BE, tal_pib.MinBE); +#endif + + break; + + case macPANId: + tal_pib.PANId = value->pib_value_16bit; + { + uint8_t *ptr_pan; + ptr_pan = (uint8_t *)&tal_pib.PANId; + for (uint8_t iter = 0; iter < 2U; iter++) { + trx_reg_write((RG_PAN_ID_0 + iter), + *ptr_pan); + ptr_pan++; + } + } + break; + + case macShortAddress: + tal_pib.ShortAddress = value->pib_value_16bit; + { + uint8_t *ptr_shrt; + ptr_shrt = (uint8_t *)&tal_pib.ShortAddress; + for (uint8_t iter = 0; iter < 2U; iter++) { + trx_reg_write((RG_SHORT_ADDR_0 + iter), + *ptr_shrt); + ptr_shrt++; + } + } + break; + + case phyCurrentChannel: + if (phy_info.tal_state != PHY_IDLE) { + return PHY_BUSY; + } +#ifdef HIGH_DATA_RATE_SUPPORT + if ((tal_pib.CurrentPage == 5) || + (tal_pib.CurrentPage == 18) || + (tal_pib.CurrentPage == 19)) +#else + if (tal_pib.CurrentPage == 5) +#endif + { + if (((uint32_t)TRX_SUPPORTED_CHANNELS_CHINA & + ((uint32_t)0x01 << + value->pib_value_8bit)) == + false) { + return PHY_INVALID_PARAMETER; + } + }else { + if (((uint32_t)TRX_SUPPORTED_CHANNELS & + ((uint32_t)0x01 << + value->pib_value_8bit)) == + false) { + return PHY_INVALID_PARAMETER; + } + } + + { + uint8_t previous_channel; + tal_trx_status_t previous_trx_status = TRX_OFF; + + previous_channel = tal_pib.CurrentChannel; + tal_pib.CurrentChannel = value->pib_value_8bit; + + /*Set the default Power Values For the Changed + * Channel according to values in datasheet*/ + set_default_tx_pwr(); + /* + * Set trx to "soft" off avoiding that ongoing + * transaction (e.g. ACK) are interrupted. + */ + if (phy_info.tal_trx_status != TRX_OFF) { + previous_trx_status = RX_AACK_ON; /* any + * + * + * + *other + * + * + * + *than + * + * + * + *TRX_OFF + * + * + * + *state + **/ + do { + /* set TRX_OFF until it could be + * set; + * trx might be busy */ + } while (set_trx_state(CMD_TRX_OFF) != + TRX_OFF); + } + + /* Check if frequency band/modulation is + * changed. */ +#ifdef HIGH_DATA_RATE_SUPPORT + if ((tal_pib.CurrentPage == 5) || + (tal_pib.CurrentPage == 18) || + (tal_pib.CurrentPage == 19)) +#else + if (tal_pib.CurrentPage == 5) +#endif + { + trx_reg_bit_write(SR_CC_NUMBER, GET_CHINA_FREQ( + tal_pib.CurrentChannel)); + } else if ((tal_pib.CurrentChannel > 0) && + (previous_channel > 0)) { + trx_reg_bit_write(SR_CHANNEL, + tal_pib.CurrentChannel); + } else { + uint8_t reg_value; + + /* Set modulation and channel */ + apply_channel_page_configuration( + tal_pib.CurrentPage); + limit_tx_pwr(); + reg_value + = + convert_phyTransmitPower_to_reg_value( + tal_pib.TransmitPower); + trx_reg_write(RG_PHY_TX_PWR, + reg_value); + } + + /* Re-store previous trx state */ + if (previous_trx_status != TRX_OFF) { + /* Set to default state */ + (void)set_trx_state(CMD_RX_AACK_ON); + } + } + break; + + case phyCurrentPage: + if (phy_info.tal_state != PHY_IDLE) { + return PHY_BUSY; + } else { + uint8_t page; + tal_trx_status_t previous_trx_status = TRX_OFF; + bool ret_val; + + /* + * Changing the channel, channel page or + * modulation + * requires that TRX is in TRX_OFF. + * Store current trx state and return to default + * state + * after channel page has been set. + */ + if (phy_info.tal_trx_status != TRX_OFF) { + previous_trx_status = RX_AACK_ON; /* any + * + * + * + *other + * + * + * + *than + * + * + * + *TRX_OFF + * + * + * + *state + **/ + do { + /* set TRX_OFF until it could be + * set; + * trx might be busy */ + } while (set_trx_state(CMD_TRX_OFF) != + TRX_OFF); + } + + page = value->pib_value_8bit; + + ret_val + = apply_channel_page_configuration(page); + + if (previous_trx_status != TRX_OFF) { + /* Set to default state */ + (void)set_trx_state(CMD_RX_AACK_ON); + } + + if (ret_val) { + tal_pib.CurrentPage = page; + } else { + return PHY_INVALID_PARAMETER; + } + + /*Set the default Power Values For the Changed + * Channel Page according to values in + * datasheet*/ + set_default_tx_pwr(); + } + + break; + + case macMaxBE: + tal_pib.MaxBE = value->pib_value_8bit; +#ifndef REDUCED_PARAM_CHECK + + /* + * macMinBE must not be larger than macMaxBE or + * calculation + * of macMaxFrameWaitTotalTime will fail. + */ + if (tal_pib.MaxBE < tal_pib.MinBE) { + tal_pib.MinBE = tal_pib.MaxBE; + } +#endif /* REDUCED_PARAM_CHECK*/ +#ifndef SW_CONTROLLED_CSMA + trx_reg_bit_write(SR_MAX_BE, tal_pib.MaxBE); +#endif + break; + + case phyTransmitPower: + + { + tal_pib.TransmitPower = value->pib_value_8bit; + uint8_t reg_value; + /* Limit tal_pib.TransmitPower to max/min trx + * values */ + limit_tx_pwr(); + reg_value + = convert_phyTransmitPower_to_reg_value( + tal_pib.TransmitPower); + trx_reg_write(RG_PHY_TX_PWR, reg_value); + + + + } + break; + + case phyCCAMode: + tal_pib.CCAMode = value->pib_value_8bit; + trx_reg_bit_write(SR_CCA_MODE, tal_pib.CCAMode); + break; + + case macIeeeAddress: + { + tal_pib.IeeeAddress = value->pib_value_64bit; + + uint8_t *ptr; + ptr = (uint8_t *)&tal_pib.IeeeAddress; + for (uint8_t iter = 0; iter < 8U; iter++) { + trx_reg_write((RG_IEEE_ADDR_0 + iter), + *ptr); + ptr++; + } + } + break; + + case mac_i_pan_coordinator: + tal_pib.PrivatePanCoordinator = value->pib_value_bool; + trx_reg_bit_write(SR_AACK_I_AM_COORD, + tal_pib.PrivatePanCoordinator); + break; + + case macAckWaitDuration: + + /* + * AT86RF212B does not support changing this value + * w.r.t. + * compliance operation. + * The ACK timing can be reduced to 2 symbols using TFA + * function. + */ + return PHY_UNSUPPORTED_ATTRIBUTE; + break; + + default: + return PHY_UNSUPPORTED_ATTRIBUTE; + break; + } + + break; /* end of 'default' from 'switch (attribute)' */ + } + return PHY_SUCCESS; +} /* tal_pib_set() */ + +/** + * \brief Set the default Power Values For Respective Pages and Channels + */ +static void set_default_tx_pwr(void) +{ + int8_t dbm_value; + + dbm_value = CONV_phyTransmitPower_TO_DBM(tal_pib.TransmitPower); + + if ((tal_pib.CurrentPage == 5) || + (tal_pib.CurrentPage == 18) || + (tal_pib.CurrentPage == 19)) { + if ((tal_pib.CurrentChannel == 0) || + (tal_pib.CurrentChannel == 3)) { + if (dbm_value > DEFAULT_TX_PWR_CHINA_CH_0_3) { + dbm_value = DEFAULT_TX_PWR_CHINA_CH_0_3; + } + } else { + if ((tal_pib.CurrentPage == 5) || + (tal_pib.CurrentPage == 18)) { + if (dbm_value > + DEFAULT_TX_PWR_OQPSK_RC_250_500) + { + dbm_value + = + DEFAULT_TX_PWR_OQPSK_RC_250_500; + } + } + } + } else if (tal_pib.CurrentPage == 0) { + if (tal_pib.CurrentChannel == 0) { + if (dbm_value > DEFAULT_TX_PWR_BPSK_20) { + dbm_value = DEFAULT_TX_PWR_BPSK_20; + } + } + } else { + if (tal_pib.CurrentChannel == 0) { + if (dbm_value > + DEFAULT_TX_PWR_OQPSK_SIN_RC_100_200_400) + { + dbm_value + = + DEFAULT_TX_PWR_OQPSK_SIN_RC_100_200_400; + } + } + } + + tal_pib.TransmitPower = TX_PWR_TOLERANCE | CONV_DBM_TO_phyTransmitPower( + dbm_value); + + /*Handle other Channel and page combinations here*/ + limit_tx_pwr(); + + trx_reg_write(RG_PHY_TX_PWR, + convert_phyTransmitPower_to_reg_value(tal_pib. + TransmitPower)); + +} + + +/** + * \brief Limit the phyTransmitPower to the trx limits + * + * \param phyTransmitPower phyTransmitPower value + * + */ + +static void limit_tx_pwr(void) +{ + int8_t dbm_value; + + dbm_value = CONV_phyTransmitPower_TO_DBM(tal_pib.TransmitPower); + + /* Limit to the transceiver's absolute maximum/minimum. */ + if (dbm_value <= MIN_TX_PWR) { + dbm_value = MIN_TX_PWR; + } else if (dbm_value > MAX_TX_PWR) { + dbm_value = MAX_TX_PWR; + } + + tal_pib.TransmitPower = TX_PWR_TOLERANCE | CONV_DBM_TO_phyTransmitPower( + dbm_value); +} + +/** + * \brief Converts a phyTransmitPower value to a register value + * + * \param phyTransmitPower_value phyTransmitPower value + * + * \return register value + */ +static uint8_t convert_phyTransmitPower_to_reg_value( + uint8_t phyTransmitPower_value) +{ + int8_t dbm_value; + uint8_t reg_value = 0x00; + + dbm_value = CONV_phyTransmitPower_TO_DBM(phyTransmitPower_value); + + /* Select the corresponding tx_pwr_table, also valid for high data rates + **/ +#ifdef HIGH_DATA_RATE_SUPPORT + if ((tal_pib.CurrentPage == 5) || (tal_pib.CurrentPage == 18) || + (tal_pib.CurrentPage == 19)) +#else + if (tal_pib.CurrentPage == 5) +#endif + { + reg_value + = *( + &tx_pwr_table_China[MAX_TX_PWR - dbm_value]); + } else { /* concerns channel pages={0, 2, 16, 17}*/ + if (tal_pib.CurrentChannel == 0) { + reg_value + = *( + &tx_pwr_table_EU[MAX_TX_PWR - + dbm_value]); + } else { /* channels 1-10 */ + reg_value + = *( + &tx_pwr_table_NA[MAX_TX_PWR - + dbm_value]); + } + } + + return reg_value; +} + +/** + * \brief Apply channel page configuartion to transceiver + * + * \param ch_page Channel page + * + * \return true if changes could be applied else false + */ +static bool apply_channel_page_configuration(uint8_t ch_page) +{ + /* + * Before updating the transceiver a number of TAL PIB attributes need + * to be updated depending on the channel page. + */ + + /* \todo these configurations are not rate dependent here! But shall be! + **/ + tal_pib.MaxFrameDuration = MAX_FRAME_DURATION; + tal_pib.SHRDuration = NO_OF_SYMBOLS_PREAMBLE_SFD; + tal_pib.SymbolsPerOctet = SYMBOLS_PER_OCTET; + + switch (ch_page) { + case 0: /* BPSK */ + trx_reg_bit_write(SR_BPSK_OQPSK, BPSK_MODE); + trx_reg_bit_write(SR_GC_TX_OFFS, BPSK_TX_OFFSET); + trx_reg_bit_write(SR_ALT_SPECTRUM, ALT_SPECTRUM_DISABLE); + if (tal_pib.CurrentChannel == 0) { /* BPSK20, EU */ + trx_reg_bit_write(SR_SUB_MODE, LOW_DATA_RATE); + } else { /* BPSK40, NA */ + trx_reg_bit_write(SR_SUB_MODE, HIGH_DATA_RATE); + } + + /* Compliant ACK timing */ + trx_reg_bit_write(SR_AACK_ACK_TIME, ACK_TIME_12_SYMBOLS); + tal_pib.SupportedChannels = TRX_SUPPORTED_CHANNELS; + trx_reg_bit_write(SR_CC_BAND, 0); + trx_reg_bit_write(SR_CHANNEL, tal_pib.CurrentChannel); + break; + + case 2: /* O-QPSK */ + trx_reg_bit_write(SR_BPSK_OQPSK, OQPSK_MODE); + trx_reg_bit_write(SR_GC_TX_OFFS, OQPSK_TX_OFFSET); + trx_reg_bit_write(SR_OQPSK_DATA_RATE, + ALTRATE_100_KBPS_OR_250_KBPS); + trx_reg_bit_write(SR_ALT_SPECTRUM, ALT_SPECTRUM_DISABLE); + if (tal_pib.CurrentChannel == 0) { /* OQPSK100, EU */ + trx_reg_bit_write(SR_SUB_MODE, LOW_DATA_RATE); + } else { /* OQPSK250, NA */ + trx_reg_bit_write(SR_SUB_MODE, HIGH_DATA_RATE); + } + + /* Compliant ACK timing */ + trx_reg_bit_write(SR_AACK_ACK_TIME, ACK_TIME_12_SYMBOLS); + tal_pib.SupportedChannels = TRX_SUPPORTED_CHANNELS; + trx_reg_bit_write(SR_CC_BAND, 0); + trx_reg_bit_write(SR_CHANNEL, tal_pib.CurrentChannel); + break; + + case 5: /* CHINESE_BAND, O-QPSK */ + trx_reg_bit_write(SR_BPSK_OQPSK, OQPSK_MODE); + trx_reg_bit_write(SR_GC_TX_OFFS, OQPSK_TX_OFFSET); + trx_reg_bit_write(SR_OQPSK_DATA_RATE, + ALTRATE_100_KBPS_OR_250_KBPS); + trx_reg_bit_write(SR_ALT_SPECTRUM, ALT_SPECTRUM_ENABLE); + trx_reg_bit_write(SR_SUB_MODE, HIGH_DATA_RATE); + /* Compliant ACK timing */ + trx_reg_bit_write(SR_AACK_ACK_TIME, ACK_TIME_12_SYMBOLS); + tal_pib.SupportedChannels = TRX_SUPPORTED_CHANNELS_CHINA; + /* Channel Page 5 supports channels 0-3. */ + if (tal_pib.CurrentChannel > 3) { + tal_pib.CurrentChannel = 0; + } + + trx_reg_bit_write(SR_CC_BAND, 4); + trx_reg_bit_write(SR_CC_NUMBER, + GET_CHINA_FREQ(tal_pib.CurrentChannel)); + + break; + +#ifdef HIGH_DATA_RATE_SUPPORT + case 16: /* non-compliant OQPSK mode 1 */ + trx_reg_bit_write(SR_BPSK_OQPSK, OQPSK_MODE); + trx_reg_bit_write(SR_GC_TX_OFFS, OQPSK_TX_OFFSET); + trx_reg_bit_write(SR_ALT_SPECTRUM, ALT_SPECTRUM_DISABLE); + trx_reg_bit_write(SR_OQPSK_DATA_RATE, + ALTRATE_200_KBPS_OR_500_KBPS); + if (tal_pib.CurrentChannel == 0) { /* 200kbps, EU */ + trx_reg_bit_write(SR_SUB_MODE, LOW_DATA_RATE); + } else { /* 500kbps, NA */ + trx_reg_bit_write(SR_SUB_MODE, HIGH_DATA_RATE); + } + + /* Reduced ACK timing */ + trx_reg_bit_write(SR_AACK_ACK_TIME, ACK_TIME_2_SYMBOLS); + tal_pib.SupportedChannels = TRX_SUPPORTED_CHANNELS; + trx_reg_bit_write(SR_CC_BAND, 0); + trx_reg_bit_write(SR_CHANNEL, tal_pib.CurrentChannel); + break; + + case 17: /* non-compliant OQPSK mode 2 */ + trx_reg_bit_write(SR_BPSK_OQPSK, OQPSK_MODE); + trx_reg_bit_write(SR_GC_TX_OFFS, OQPSK_TX_OFFSET); + trx_reg_bit_write(SR_ALT_SPECTRUM, ALT_SPECTRUM_DISABLE); + trx_reg_bit_write(SR_OQPSK_DATA_RATE, + ALTRATE_400_KBPS_OR_1_MBPS); + if (tal_pib.CurrentChannel == 0) { /* 400kbps, EU */ + trx_reg_bit_write(SR_SUB_MODE, LOW_DATA_RATE); + } else { /* 1000kbps, NA */ + trx_reg_bit_write(SR_SUB_MODE, HIGH_DATA_RATE); + } + + /* Reduced ACK timing */ + trx_reg_bit_write(SR_AACK_ACK_TIME, ACK_TIME_2_SYMBOLS); + tal_pib.SupportedChannels = TRX_SUPPORTED_CHANNELS; + trx_reg_bit_write(SR_CC_BAND, 0); + trx_reg_bit_write(SR_CHANNEL, tal_pib.CurrentChannel); + break; + + case 18: /* Chinese band, non-compliant mode 1 using O-QPSK 500 */ + trx_reg_bit_write(SR_BPSK_OQPSK, OQPSK_MODE); + trx_reg_bit_write(SR_GC_TX_OFFS, OQPSK_TX_OFFSET); + trx_reg_bit_write(SR_OQPSK_DATA_RATE, + ALTRATE_200_KBPS_OR_500_KBPS); + trx_reg_bit_write(SR_ALT_SPECTRUM, ALT_SPECTRUM_ENABLE); + trx_reg_bit_write(SR_SUB_MODE, HIGH_DATA_RATE); + /* Reduced ACK timing */ + trx_reg_bit_write(SR_AACK_ACK_TIME, ACK_TIME_2_SYMBOLS); + tal_pib.SupportedChannels = TRX_SUPPORTED_CHANNELS_CHINA; + /* Channel Page 18 supports channels 0-3. */ + if (tal_pib.CurrentChannel > 3) { + tal_pib.CurrentChannel = 0; + } + + trx_reg_bit_write(SR_CC_BAND, 4); + trx_reg_bit_write(SR_CC_NUMBER, + GET_CHINA_FREQ(tal_pib.CurrentChannel)); + break; + + case 19: /* Chinese band, non-compliant mode 2 using O-QPSK 1000 */ + trx_reg_bit_write(SR_BPSK_OQPSK, OQPSK_MODE); + trx_reg_bit_write(SR_GC_TX_OFFS, OQPSK_TX_OFFSET); + trx_reg_bit_write(SR_OQPSK_DATA_RATE, + ALTRATE_400_KBPS_OR_1_MBPS); + trx_reg_bit_write(SR_ALT_SPECTRUM, ALT_SPECTRUM_ENABLE); + trx_reg_bit_write(SR_SUB_MODE, HIGH_DATA_RATE); + /* Reduced ACK timing */ + trx_reg_bit_write(SR_AACK_ACK_TIME, ACK_TIME_2_SYMBOLS); + tal_pib.SupportedChannels = TRX_SUPPORTED_CHANNELS_CHINA; + /* Channel Page 18 supports channels 0-3. */ + if (tal_pib.CurrentChannel > 3) { + tal_pib.CurrentChannel = 0; + } + + trx_reg_bit_write(SR_CC_BAND, 4); + trx_reg_bit_write(SR_CC_NUMBER, + GET_CHINA_FREQ(tal_pib.CurrentChannel)); + break; + +#endif /* #ifdef HIGH_DATA_RATE_SUPPORT */ + default: + return false; + } + + return true; +} + +/* EOF */ diff --git a/driver/software/RF212b/phy/at86rf212b/src/phy_pwr_mgmt.c b/driver/software/RF212b/phy/at86rf212b/src/phy_pwr_mgmt.c new file mode 100644 index 0000000..e173e60 --- /dev/null +++ b/driver/software/RF212b/phy/at86rf212b/src/phy_pwr_mgmt.c @@ -0,0 +1,153 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* === INCLUDES ============================================================ */ + +#include +#include +#include + +#include "../../../pal/inc/pal.h" +#include "../../../phy/inc/phy.h" +#include "../../../phy/inc/ieee_phy_const.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../../phy/at86rf/inc/phy_internal.h" + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* === GLOBALS ============================================================= */ + +/* === PROTOTYPES ========================================================== */ + +/* === IMPLEMENTATION ====================================================== */ + +/* + * \brief Sets the transceiver to sleep + * + * This function sets the transceiver to sleep state. + * + * \param mode Defines sleep mode of transceiver: SLEEP_MODE_1 or + * DEEP_SLEEP_MODE) + * + * \return TAL_BUSY - The transceiver is busy in TX or RX + * MAC_SUCCESS - The transceiver is put to sleep + * TAL_TRX_ASLEEP - The transceiver is already asleep; + * either in SLEEP or in DEEP_SLEEP + * MAC_INVALID_PARAMETER - The specified sleep mode is not supported + */ +PHY_Retval_t PHY_TrxSleep(PHY_SleepMode_t mode) +{ + tal_trx_status_t trx_status; + + /* Current transceiver only supports SLEEP_MODE_1 mode. */ + if (SLEEP_MODE_1 != mode) { + return PHY_INVALID_PARAMETER; + } + + if (phy_info.tal_trx_status == TRX_SLEEP) + { + return PHY_TRX_ASLEEP; + } + + /* Device can be put to sleep only when the TAL is in IDLE state. */ + if (PHY_IDLE != phy_info.tal_state) { + return PHY_BUSY; + } + + phy_info.tal_rx_on_required = false; + + /* + * First set trx to TRX_OFF. + * If trx is busy, like ACK transmission, do not interrupt it. + */ + do { + trx_status = set_trx_state(CMD_TRX_OFF); + } while (trx_status != TRX_OFF); + + + + if (mode == SLEEP_MODE_1) { + trx_status = set_trx_state(CMD_SLEEP); + } + + + if (trx_status == TRX_SLEEP) + + { + return PHY_SUCCESS; + } else { + /* State could not be set due to TAL_BUSY state. */ + return PHY_BUSY; + } +} + +/* + * \brief Wakes up the transceiver from sleep + * + * This function awakes the transceiver from sleep state. + * + * \return TAL_TRX_AWAKE - The transceiver is already awake + * MAC_SUCCESS - The transceiver is woken up from sleep + * FAILURE - The transceiver did not wake-up from sleep + */ +PHY_Retval_t PHY_TrxWakeup(void) +{ + tal_trx_status_t trx_status; + + + if ((phy_info.tal_trx_status != TRX_SLEEP)) + { + return PHY_TRX_AWAKE; + } + + trx_status = set_trx_state(CMD_TRX_OFF); + + if (trx_status == TRX_OFF) { + return PHY_SUCCESS; + } else { + return PHY_FAILURE; + } +} + + + +void tal_trx_wakeup(void) +{ + + /* The pending transceiver interrupts on the microcontroller are + * cleared. */ + /* Clear existing interrupts */ + (void)trx_reg_read(RG_IRQ_STATUS); + /* Leave trx sleep mode. */ + TRX_SLP_TR_LOW(); + /* Poll wake-up interrupt flag until set within ISR. */ + while (!phy_info.tal_awake_end_flag) { + } + +} + +/* EOF */ diff --git a/driver/software/RF212b/phy/at86rf212b/src/phy_rx.c b/driver/software/RF212b/phy/at86rf212b/src/phy_rx.c new file mode 100644 index 0000000..cb02112 --- /dev/null +++ b/driver/software/RF212b/phy/at86rf212b/src/phy_rx.c @@ -0,0 +1,396 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* === INCLUDES ============================================================ */ + +#include +#include +#include + +#include "../../../pal/inc/pal.h" +#include "../../../phy/inc/ieee_phy_const.h" +#include "../../../resources/buffer/inc/bmm.h" +#include "../../../resources/queue/inc/qmm.h" +#include "../../../phy/inc/phy_constants.h" +#include "../../at86rf/inc/phy_pib.h" +#include "../../at86rf/inc/phy_irq_handler.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../at86rf/inc/phy_rx.h" +#include "../../../phy/at86rf/inc/phy_internal.h" +#include "../../../phy/inc/phy_tasks.h" + + + + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* Constant defines for the LQI calculation */ +#define ED_THRESHOLD (60) +#define ED_MAX (-RSSI_BASE_VAL_BPSK_300_DBM - \ + ED_THRESHOLD) +#define LQI_MAX (3) + +#define ED_LEVEL_MAX_REG_VALUE (84) +#define ED_LEVEL_MULTIPLIER (255.0 / ED_LEVEL_MAX_REG_VALUE) + +#define US_PER_OCTECT (32) + + +/* === GLOBALS ============================================================= */ + +/* === PROTOTYPES ========================================================== */ + +#ifndef TRX_REG_RAW_VALUE +#ifdef RSSI_TO_LQI_MAPPING +static inline uint8_t normalize_lqi(uint8_t ed_value); + +#else +static inline uint8_t normalize_lqi(uint8_t lqi, uint8_t ed_value); + +#endif +#endif /* #ifndef TRX_REG_RAW_VALUE */ + +/* === IMPLEMENTATION ====================================================== */ + +/* + * \brief Handle received frame interrupt + * + * This function handles transceiver interrupts for received frames and + * uploads the frames from the trx. + */ + +void handle_received_frame_irq(void) +{ + uint8_t ed_value; + /* Actual frame length of received frame. */ + uint8_t phy_frame_len; + /* Extended frame length appended by LQI and ED. */ + uint8_t ext_frame_length; + PHY_FrameInfo_t *receive_frame; + uint8_t *frame_ptr; + + if (tal_rx_buffer == NULL) { + + /* + * Although the buffer protection mode is enabled and the + * receiver has + * been switched to PLL_ON, the next incoming frame was faster. + * It cannot be handled and is discarded. Reading anything from + * the + * frame resets the buffer protection mode. + */ + uint8_t dummy; + trx_frame_read(&dummy, 1); + return; + } + + receive_frame = (PHY_FrameInfo_t *)BMM_BUFFER_POINTER(tal_rx_buffer); + +#ifdef PROMISCUOUS_MODE + if (tal_pib.PromiscuousMode) { + /* Check for valid FCS */ + if (trx_reg_bit_read(SR_RX_CRC_VALID) == CRC16_NOT_VALID) { + return; + } + } +#endif + + /* Get ED value; needed to normalize LQI. */ + ed_value = trx_reg_read(RG_PHY_ED_LEVEL); + + +// phy_info.last_pkt_ed_level = trx_reg_read(RG_PHY_ED_LEVEL); + +#if (defined ENABLE_TRX_SRAM) || defined(ENABLE_TRX_SRAM_READ) + /* Use SRAM read to keep rx safe mode armed. */ + trx_sram_read(0x00, &phy_frame_len, LENGTH_FIELD_LEN); /* 0x00: SRAM + * offset + * address */ +#else + /* Get frame length from transceiver. */ + trx_frame_read(&phy_frame_len, LENGTH_FIELD_LEN); +#endif + + phy_info.last_frame_length = phy_frame_len; + /* Check for valid frame length. */ + if (phy_frame_len > 127U) { + return; + } + + /* + * The PHY header is also included in the frame (length field), hence + * the frame length + * is incremented. + * In addition to that, the LQI and ED value are uploaded, too. + */ + // phy_frame_len = 1(length byte(PHR))+9((MHR)+ 1(seq no.)+(length of data) + ext_frame_length = phy_frame_len + LENGTH_FIELD_LEN + LQI_LEN + + ED_VAL_LEN; + + /* Update payload pointer to store received frame. */ + frame_ptr = (uint8_t *)receive_frame + LARGE_BUFFER_SIZE - + ext_frame_length ; + + /* + * Note: The following code is different from single chip + * transceivers, since reading the frame via SPI contains the length + * field + * in the first octet. + */ + trx_frame_read(frame_ptr, + LENGTH_FIELD_LEN + phy_frame_len + LQI_LEN ); + + + receive_frame->mpdu = frame_ptr; + /* Add ED value at the end of the frame buffer. */ + receive_frame->mpdu[phy_frame_len + LQI_LEN + ED_VAL_LEN] = ed_value; + phy_info.last_pkt_lqi = receive_frame->mpdu[phy_frame_len + LQI_LEN]; + + + + /* Append received frame to incoming_frame_queue and get new rx buffer. + **/ + qmm_queue_append(&tal_incoming_frame_queue, tal_rx_buffer); + + /* The previous buffer is eaten up and a new buffer is not assigned yet. + **/ + tal_rx_buffer = bmm_buffer_alloc(LARGE_BUFFER_SIZE); + + +/* Check if receive buffer is available */ + if (NULL == tal_rx_buffer) { + /* + * Turn off the receiver until a buffer is available again. + * tal_task() will take care of eventually reactivating it. + * Due to ongoing ACK transmission do not force to switch it + * off. + */ + (void)set_trx_state(CMD_PLL_ON); + phy_info.tal_rx_on_required = true; + + } + PHY_PostTask(false); +} + +/* + * \brief Parses received frame and create the PHY_FrameInfo_t structure + * + * This function parses the received frame and creates the PHY_FrameInfo_t + * structure to be sent to the MAC as a parameter of tal_rx_frame_cb(). + * + * \param buf Pointer to the buffer containing the received frame + */ + +void process_incoming_frame(buffer_t *buf_ptr) +{ + +#ifndef TRX_REG_RAW_VALUE + uint8_t frame_len; + uint8_t *frame_ptr; + uint8_t ed_level; + uint8_t lqi; +#endif + + PHY_FrameInfo_t *receive_frame + = (PHY_FrameInfo_t *)BMM_BUFFER_POINTER(buf_ptr); + + + /* The frame is present towards the end of the buffer. */ + +#ifndef TRX_REG_RAW_VALUE + + /* + * Store the last frame length for IFS handling. + * Substract LQI and length fields. + */ + frame_len = phy_info.last_frame_length = receive_frame->mpdu[0]; + +#else + phy_info.last_frame_length = receive_frame->mpdu[0]; +#endif + +#ifdef PROMISCUOUS_MODE + if (tal_pib.PromiscuousMode) { +#ifndef TRX_REG_RAW_VALUE + frame_ptr = &(receive_frame->mpdu[frame_len + LQI_LEN]); + + /* + * The LQI is stored after the FCS. + * The ED value is stored after the LQI. + */ + lqi = *frame_ptr++; + phy_info.last_pkt_lqi = lqi; + ed_level = *frame_ptr; + + /* + * The LQI normalization is done using the ED level measured + * during + * the frame reception. + */ +#ifdef RSSI_TO_LQI_MAPPING + lqi = normalize_lqi(ed_level); +#else + lqi = normalize_lqi(lqi, ed_level); +#endif + + /* Store normalized LQI value again. */ + frame_ptr--; + *frame_ptr = lqi; +#endif /* #ifndef TRX_REG_RAW_VALUE */ + + receive_frame->buffer_header = buf_ptr; + + /* The callback function implemented by MAC is invoked. */ + PHY_RxFrameCallback(receive_frame); + + return; + } +#endif /* #ifdef PROMISCUOUS_MODE */ + + + +#ifndef TRX_REG_RAW_VALUE + + /* + * The LQI is stored after the FCS. + * The ED value is stored after the LQI. + */ + frame_ptr = &(receive_frame->mpdu[frame_len + LQI_LEN]); + lqi = *frame_ptr++; + ed_level = *frame_ptr; + +// *frame_ptr = ed_level = phy_info.last_pkt_ed_level; + + /* + * The LQI normalization is done using the ED level measured during + * the frame reception. + */ +#ifdef RSSI_TO_LQI_MAPPING + lqi = normalize_lqi(ed_level); +#else + lqi = normalize_lqi(lqi, ed_level); +#endif + + /* Store normalized LQI value again. */ + frame_ptr--; + *frame_ptr = lqi; +#endif /* #ifndef TRX_REG_RAW_VALUE */ + +#if (defined TX_OCTET_COUNTER) && (defined SW_CONTROLLED_CSMA) + /* Add ACK frame length to the number of transmitted bytes. */ + if (receive_frame->mpdu[PL_POS_FCF_1] & FCF_ACK_REQUEST) { + tal_tx_octet_cnt += PHY_OVERHEAD + LENGTH_FIELD_LEN + + ACK_PAYLOAD_LEN + + FCS_LEN; /* = 11 bytes */ + } +#endif + + receive_frame->buffer_header = buf_ptr; + + /* The callback function implemented by MAC is invoked. */ + PHY_RxFrameCallback(receive_frame); + +} /* process_incoming_frame() */ + +#ifndef TRX_REG_RAW_VALUE +#ifdef RSSI_TO_LQI_MAPPING + +/** + * \brief Normalize LQI + * + * This function normalizes the LQI value based on the RSSI/ED value. + * + * \param ed_value Read ED value + * + * \return The calculated/normalized LQI value: ppduLinkQuality + */ +static inline uint8_t normalize_lqi(uint8_t ed_value) +{ + /* + * Scale ED result. + */ + if (ed_value > (ED_LEVEL_MAX_REG_VALUE - 1)) { + return 0xFF; + } else { + /* Scale ED value to span up to 0xFF. */ + return (uint8_t)(ed_value * ED_LEVEL_MULTIPLIER + 0.5); + } +} + +#else /* #ifdef RSSI_TO_LQI_MAPPING */ + +/** + * \brief Normalize LQI + * + * This function normalizes the LQI value based on the ED and + * the originally appended LQI value. + * + * \param lqi Measured LQI + * \param ed_value Read ED value + * + * \return The calculated LQI value: ppduLinkQuality + */ +static inline uint8_t normalize_lqi(uint8_t lqi, uint8_t ed_value) +{ + uint16_t link_quality; + uint8_t lqi_star; + uint8_t ed_max_val = (uint8_t)ED_MAX; + +#ifdef HIGH_DATA_RATE_SUPPORT + if (tal_pib.CurrentPage == 0) { +#endif + if (ed_value > ed_max_val) { + ed_value = ed_max_val; + } else if (ed_value == 0U) { + ed_value = 1; + } + + lqi_star = lqi >> 6U; + link_quality = (uint16_t)lqi_star * (uint16_t)ed_value * 255U / + (ed_max_val * LQI_MAX); + + if (link_quality > 255U) { + return 255; + } else { + return (uint8_t)link_quality; + } + +#ifdef HIGH_DATA_RATE_SUPPORT +} else { /* if (tal_pib.CurrentPage == 0) */ + /* High data rate modes do not provide a valid LQI value. */ + if (ed_value > ed_max_val) { + return 0xFF; + } else { + return (ed_value * (255U / ed_max_val)); + } +} +#endif +} +#endif /* #ifdef RSSI_TO_LQI_MAPPING */ +#endif /* #ifndef TRX_REG_RAW_VALUE */ + +/* EOF */ diff --git a/driver/software/RF212b/phy/at86rf212b/src/phy_rx_enable.c b/driver/software/RF212b/phy/at86rf212b/src/phy_rx_enable.c new file mode 100644 index 0000000..9826654 --- /dev/null +++ b/driver/software/RF212b/phy/at86rf212b/src/phy_rx_enable.c @@ -0,0 +1,127 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* === INCLUDES ============================================================ */ + +#include +#include +#include +#include "../../../pal/inc/pal.h" +#include "../../at86rf/inc/phy_tx.h" +#include "../../../phy/inc/phy.h" +#include "../../../phy/inc/phy_constants.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../../resources/buffer/inc/bmm.h" +#include "../../../resources/queue/inc/qmm.h" +#include "../../at86rf/inc/phy_rx.h" +#include "../../../phy/at86rf/inc/phy_internal.h" +#include "../../../phy/inc/phy_tasks.h" + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* === GLOBALS ============================================================= */ + +/* === PROTOTYPES ========================================================== */ + +/* === IMPLEMENTATION ====================================================== */ + +/* + * \brief Switches receiver on or off + * + * This function switches the receiver on (PHY_RX_ON) or off (PHY_TRX_OFF). + * + * \param state New state of receiver + * + * \return TAL_BUSY if the TAL state machine cannot switch receiver on or off, + * TRX_OFF if receiver has been switched off, or + * RX_ON otherwise. + * + */ +PHY_TrxStatus_t PHY_RxEnable(PHY_TrxState_t state) +{ + + + /* + * Trx can only be enabled if TAL is not busy; + * i.e. if TAL is IDLE. + */ + if (PHY_IDLE != phy_info.tal_state) { + + return PHY_BUSY_TX; + + } + + if (state == PHY_STATE_TRX_OFF) { + /* + * If the rx needs to be switched off, we are not interested in + * a frame + * that is currently being received. + * This must not be a Forced TRX_OFF (CMD_FORCED_TRX_OFF) since + * this could + * corrupt an already outoing ACK frame. + */ + (void)set_trx_state(CMD_TRX_OFF); + phy_info.tal_rx_on_required = false; + return PHY_TRX_OFF; + } else { + if (NULL != tal_rx_buffer) { + #ifdef PROMISCUOUS_MODE + if (tal_pib.PromiscuousMode) { + (void)set_trx_state(CMD_RX_ON); + while(((uint8_t)tal_get_trx_status() & 0x1FU) != (uint8_t)RX_ON); + } else + #endif + { + (void)set_trx_state(CMD_RX_AACK_ON); + while(((uint8_t)tal_get_trx_status() & 0x1FU) != (uint8_t)RX_AACK_ON) + { + /*WAIT*/ + } + } + + } else { + /* + * If no rx buffer is available, the corresponding + * information is stored and will be used by tal_task() + * to + * switch on the receiver later. + * + * Even if a receive buffer is not available, + * the TAL returns MAC_SUCCESS. The TAL will try to + * allocate a receive + * buffer as soon as possible and will switch on the + * receiver. + */ + phy_info.tal_rx_on_required = true; + //OSAL_SEM_Post(&semPhyRxInternalHandler); + PHY_PostTask(false); + } + return PHY_RX_ON; /* MAC layer assumes RX_ON as return value */ + } +} + +/* EOF */ diff --git a/driver/software/RF212b/phy/at86rf212b/src/phy_tx.c b/driver/software/RF212b/phy/at86rf212b/src/phy_tx.c new file mode 100644 index 0000000..9445d66 --- /dev/null +++ b/driver/software/RF212b/phy/at86rf212b/src/phy_tx.c @@ -0,0 +1,366 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* === INCLUDES ============================================================ */ + +#include +#include +#include +#include "../../../pal/inc/pal.h" +#include "../../../phy/inc/phy.h" +#include "../../../phy/inc/ieee_phy_const.h" +#include "../../at86rf/inc/phy_pib.h" +#include "../../at86rf/inc/phy_irq_handler.h" +#include "../../../phy/inc/phy_constants.h" +#include "../../at86rf/inc/phy_tx.h" +#include "../../../resources/buffer/inc/bmm.h" +#include "../../../resources/queue/inc/qmm.h" +#include "../../at86rf/inc/phy_rx.h" +#include "../../../phy/at86rf/inc/phy_internal.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../../phy/at86rf/inc/phy_trx_reg_access.h" +#include "../../../phy/inc/phy_tasks.h" + + + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* === GLOBALS ============================================================= */ + +static uint8_t tal_sw_retry_count; +static bool tal_sw_retry_no_csma_ca; +static trx_trac_status_t trx_trac_status; + +void trxEIC_waitTimerCb(uintptr_t context); +SYS_TIME_HANDLE trxEIC_waitTimer; +bool TxDoneFlag = false; + +extern TimerId_t TAL_RETRY_TIMER; + +/* === PROTOTYPES ========================================================== */ +static void retransmissionTimerCallback(void); +/* === IMPLEMENTATION ====================================================== */ + +void trxEIC_waitTimerCb(uintptr_t context) +{ + TxDoneFlag = true; + PHY_PostTask(false); +} + +/* + * \brief Requests to TAL to transmit frame + * + * This function is called by the MAC to deliver a frame to the TAL + * to be transmitted by the transceiver. + * + * \param tx_frame Pointer to the PHY_FrameInfo_t structure updated by the MAC + * layer + * \param csma_mode Indicates mode of csma-ca to be performed for this frame + * \param perform_frame_retry Indicates whether to retries are to be performed + * for + * this frame + * + * \return MAC_SUCCESS if the TAL has accepted the data from the MAC for frame + * transmission + * TAL_BUSY if the TAL is busy servicing the previous MAC request + */ + PHY_Retval_t PHY_TxFrame(PHY_FrameInfo_t *txFrame, PHY_CSMAMode_t csmaMode, + bool performFrameRetry) +{ + + if (phy_info.tal_state != PHY_IDLE) { + return PHY_BUSY; + } + + /* + * Store the pointer to the provided frame structure. + * This is needed for the callback function. + */ + mac_frame_ptr = txFrame; + + /* Set pointer to actual mpdu to be downloaded to the transceiver. */ + tal_frame_to_tx = txFrame->mpdu; + /* + * In case the frame is too large, return immediately indicating + * invalid status. + */ + if (tal_frame_to_tx == NULL) { + return PHY_INVALID_PARAMETER; + } + phy_info.last_frame_length = tal_frame_to_tx[0] - 1; + + + + send_frame(csmaMode, performFrameRetry); + + + return PHY_SUCCESS; +} + + +/* + * \brief Implements the handling of the transmission end. + * + * This function handles the callback for the transmission end. + */ +void tx_done_handling(void) +{ + phy_info.tal_state = PHY_IDLE; + + PHY_Retval_t status; + + switch (trx_trac_status) { + case TRAC_SUCCESS: + status = PHY_SUCCESS; + break; + + case TRAC_SUCCESS_DATA_PENDING: + status = PHY_FRAME_PENDING; + break; + + case TRAC_CHANNEL_ACCESS_FAILURE: + status = PHY_CHANNEL_ACCESS_FAILURE; + break; + + case TRAC_NO_ACK: + status = PHY_NO_ACK; + break; + + case TRAC_INVALID: + status = PHY_FAILURE; + break; + + default: + status = PHY_FAILURE; + break; + } + + if(TxDoneFlag == true) + { + TxDoneFlag = false; + MiMac_PostTask(false); + } + + PHY_TxDoneCallback(status, mac_frame_ptr); + +} /* tx_done_handling() */ + +/* + * \brief Sends frame + * + * \param use_csma Flag indicating if CSMA is requested + * \param tx_retries Flag indicating if transmission retries are requested + * by the MAC layer + */ +void send_frame(PHY_CSMAMode_t csmaMode, bool txRetries) +{ + tal_trx_status_t trx_status; + + /* Configure tx according to tx_retries */ + if (txRetries) { + trx_reg_bit_write(SR_MAX_FRAME_RETRIES, + tal_pib.MaxFrameRetries); + } else { + trx_reg_bit_write(SR_MAX_FRAME_RETRIES, 0); + } + + /* Configure tx according to csma usage */ + if ((csmaMode == NO_CSMA_NO_IFS) || (csmaMode == NO_CSMA_WITH_IFS)) + { + trx_reg_bit_write(SR_MAX_CSMA_RETRIES, 7); /* immediate + * transmission */ + if (txRetries) { + tal_sw_retry_count = tal_pib.MaxFrameRetries; + tal_sw_retry_no_csma_ca = true; + } + } else { + trx_reg_bit_write(SR_MAX_CSMA_RETRIES, tal_pib.MaxCSMABackoffs); + } + + /* Handle interframe spacing */ + if (csmaMode == NO_CSMA_WITH_IFS) { + if (phy_info.last_frame_length > aMaxSIFSFrameSize) { + PAL_TimerDelay(PHY_CONVERT_SYMBOLS_TO_US( + macMinLIFSPeriod_def) + - TRX_IRQ_DELAY_US - + PRE_TX_DURATION_US); + phy_info.last_frame_length = 0; + } else if (phy_info.last_frame_length > 0) { + PAL_TimerDelay(PHY_CONVERT_SYMBOLS_TO_US( + macMinSIFSPeriod_def) + - TRX_IRQ_DELAY_US - + PRE_TX_DURATION_US); + phy_info.last_frame_length = 0; + }else{ + /*DO NOTHING*/ + } + } + do { + trx_status = set_trx_state(CMD_TX_ARET_ON); + } while (trx_status != TX_ARET_ON); + /* + * Send the frame to the transceiver. + * Note: The PhyHeader is the first byte of the frame to + * be sent to the transceiver and this contains the frame + * length. + * The actual length of the frame to be downloaded + * (parameter two of trx_frame_write) + * is + * 1 octet frame length octet + * + n octets frame (i.e. value of frame_tx[0]) + * + 1 extra octet (see datasheet) + * - 2 octets FCS + */ + + trx_frame_write(tal_frame_to_tx, tal_frame_to_tx[0]); + phy_info.tal_state = PHY_TX_AUTO; + + /* Toggle the SLP_TR pin triggering transmission. */ + TRX_SLP_TR_HIGH(); + trx_delay_micros(1); + TRX_SLP_TR_LOW(); + uint8_t context = 0U; + trxEIC_waitTimer = SYS_TIME_CallbackRegisterUS(&trxEIC_waitTimerCb, (uintptr_t)&context, 54000, SYS_TIME_SINGLE); + if(trxEIC_waitTimer == SYS_TIME_HANDLE_INVALID) + { + return; + } + + (void)trx_status; + + +#ifndef NON_BLOCKING_SPI + pal_trx_irq_en(); +#endif + +} + +/* + * \brief Handles interrupts issued due to end of transmission + * + * \param underrun_occured true if under-run has occurred + */ +void handle_tx_end_irq(bool underrun_occured) +{ + + { + + + /* Read trac status before enabling RX_AACK_ON. */ + if (underrun_occured) { + trx_trac_status = TRAC_INVALID; + } else { + trx_trac_status = (trx_trac_status_t) trx_reg_bit_read( + SR_TRAC_STATUS); + } + + /* Trx has handled the entire transmission incl. CSMA */ + { + if (tal_sw_retry_no_csma_ca && ((bool)tal_sw_retry_count) && + TRAC_NO_ACK == trx_trac_status ) { + tal_trx_status_t trx_status; + do { + trx_status = set_trx_state( + CMD_TX_ARET_ON); + } while (trx_status != TX_ARET_ON); + + /* Toggle the SLP_TR pin triggering + * transmission. */ + TRX_SLP_TR_HIGH(); + trx_delay_micros(1); + TRX_SLP_TR_LOW(); + uint8_t context = 0U; + trxEIC_waitTimer = SYS_TIME_CallbackRegisterUS(&trxEIC_waitTimerCb, (uintptr_t)&context, 54000, SYS_TIME_SINGLE); + if(trxEIC_waitTimer == SYS_TIME_HANDLE_INVALID) + { + return; + } + if (--tal_sw_retry_count == 0U) { + tal_sw_retry_no_csma_ca = false; + } + } else { + phy_info.tal_state = PHY_TX_DONE; /* Further handling is + * done by * tx_done_handling() + **/ + + + //tx_done_handling(); + phy_info.tal_rx_on_required = true; + + PHY_PostTask(false); + } + } + } + +} + +void tal_start_retransmission_timer(uint32_t us) +{ + + if((bool)tal_sw_retry_count) + { + tal_sw_retry_count--; + } + + if(tal_sw_retry_count > 0U) + { + if (PAL_SUCCESS == PAL_TimerStart(TAL_RETRY_TIMER, us, + TIMEOUT_RELATIVE, + (void *)retransmissionTimerCallback, + NULL, CALLBACK_SINGLE)) + { + return; + } + } + + + phy_info.tal_state = PHY_TX_DONE; /* Further handling is + * done by + * tx_done_handling() + **/ + //tx_done_handling(); + phy_info.tal_rx_on_required = true; + PHY_PostTask(false); +} + +static void retransmissionTimerCallback(void) +{ + tal_trx_status_t trx_status; + + do { + trx_status = set_trx_state( + CMD_TX_ARET_ON); + } while (trx_status != TX_ARET_ON); + + /* Toggle the SLP_TR pin triggering + * transmission. */ + TRX_SLP_TR_HIGH(); + trx_delay_micros(1); + TRX_SLP_TR_LOW(); + +} +/* EOF */ diff --git a/driver/software/RF212b/phy/at86rf212b/src/tfa.c b/driver/software/RF212b/phy/at86rf212b/src/tfa.c new file mode 100644 index 0000000..4595e96 --- /dev/null +++ b/driver/software/RF212b/phy/at86rf212b/src/tfa.c @@ -0,0 +1,466 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + + + +/* === INCLUDES ============================================================ */ + +#include +#include +#include +#include +#include "../../../pal/inc/pal.h" +#include "../../../phy/inc/phy.h" +#include "../../../phy/inc/ieee_phy_const.h" +#include "../../../phy/inc/phy_constants.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../../phy/at86rf/inc/phy_internal.h" + + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* Constant define for the ED scaling: register value at -35dBm */ +#define CLIP_VALUE_REG (62) + +/* === GLOBALS ============================================================= */ + +/** + * TFA PIB attribute to reduce the Rx sensitivity. + * Represents the Rx sensitivity value in dBm; example: -52 + */ +static int8_t tfa_pib_rx_sens; + +/* === PROTOTYPES ========================================================== */ + +static void init_tfa_pib(void); +static void write_all_tfa_pibs_to_trx(void); + +/* === IMPLEMENTATION ====================================================== */ + +uint8_t txcwdata[128]; + + + +/* + * \brief Perform a CCA + * + * This function performs a CCA request. + * + * \return phy_enum_t PHY_IDLE or PHY_BUSY + */ +PHY_Retval_t PHY_CCAPerform(void) +{ + tal_trx_status_t trx_status; + uint8_t cca_status; + uint8_t cca_done; + + /* Ensure that trx is not in SLEEP for register access */ + do { + trx_status = set_trx_state(CMD_TRX_OFF); + } while (trx_status != TRX_OFF); + + /* no interest in receiving frames while doing CCA */ + trx_reg_bit_write(SR_RX_PDT_DIS, RX_DISABLE); /* disable frame reception + * indication */ + + /* Set trx to rx mode. */ + do { + trx_status = set_trx_state(CMD_RX_ON); + } while (trx_status != RX_ON); + + /* Start CCA */ + trx_reg_bit_write(SR_CCA_REQUEST, CCA_START); + + /* wait until CCA is done */ + trx_delay_micros(PHY_CONVERT_SYMBOLS_TO_US(CCA_DURATION_SYM)); + do { + /* poll until CCA is really done */ + cca_done = trx_reg_bit_read(SR_CCA_DONE); + } while (cca_done != CCA_COMPLETED); + + (void)set_trx_state(CMD_TRX_OFF); + + /* Check if channel was idle or busy. */ + if (trx_reg_bit_read(SR_CCA_STATUS) == CCA_CH_IDLE) { + cca_status = (uint8_t)PHY_CHANNEL_IDLE; + } else { + cca_status = (uint8_t)PHY_CHANNEL_BUSY; + } + + /* Enable frame reception again. */ + trx_reg_bit_write(SR_RX_PDT_DIS, RX_ENABLE); + + return ((PHY_Retval_t)cca_status); +} + + + + + +/* + * \brief Perform a single ED measurement + * + * \return ed_value Result of the measurement + * If the build switch TRX_REG_RAW_VALUE is defined, the transceiver's + * register value is returned. + */ +uint8_t PHY_EdSample(void) +{ + trx_irq_reason_t trx_irq_cause; + uint8_t ed_value; + tal_trx_status_t trx_status; + + phy_info.tal_state = PHY_ED_RUNNING; + + /* Make sure that receiver is switched on. */ + do { + trx_status = set_trx_state(CMD_RX_ON); + } while (trx_status != RX_ON); + + /* + * Disable the transceiver interrupts to prevent frame reception + * while performing ED scan. + */ + trx_reg_bit_write(SR_RX_PDT_DIS, RX_DISABLE); + + /* Write dummy value to start measurement. */ + trx_reg_write(RG_PHY_ED_LEVEL, 0xFF); + + /* Wait for ED measurement completion. */ + trx_delay_micros(PHY_CONVERT_SYMBOLS_TO_US(ED_SAMPLE_DURATION_SYM)); + do { + trx_irq_cause + = (trx_irq_reason_t)trx_reg_read(RG_IRQ_STATUS); + } while ((trx_irq_reason_t)(((uint8_t)trx_irq_cause) & ((uint8_t)TRX_IRQ_4_CCA_ED_DONE)) != + TRX_IRQ_4_CCA_ED_DONE); + + /* Read the ED Value. */ + ed_value = trx_reg_read(RG_PHY_ED_LEVEL); + + /* Clear IRQ register */ + (void)trx_reg_read(RG_IRQ_STATUS); + /* Enable reception agian */ + trx_reg_bit_write(SR_RX_PDT_DIS, RX_ENABLE); + /* Switch receiver off again */ + (void)set_trx_state(CMD_TRX_OFF); + + phy_info.tal_state = PHY_IDLE; + return ed_value; +} + + + +/* + * \brief Starts continuous transmission on current channel + * + * \param tx_mode Mode of continuous transmission (CW or PRBS) + * \param random_content Use random content if true + */ +void PHY_StartContinuousTransmit(PHY_ContinuousTxMode_t txMode, bool randomContent) +{ + + /* step 3,6: Channel is assumed to be set before */ + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_TRX_OFF); + /* step 7: Enable continuous transmission - step #1 */ + trx_reg_write(0x36, 0x0F); + if (txMode == CW_MODE) { + /* step 8: Register access: CW at Fc +/- 0.1 MHz */ + if (((tal_pib.CurrentPage == 0) || (tal_pib.CurrentPage == 2) || \ + (tal_pib.CurrentPage == 16) || + (tal_pib.CurrentPage == 17)) && + (tal_pib.CurrentChannel == 0)) { /* + * + * + *868.3MHz + **/ + trx_reg_write(RG_TRX_CTRL_2, 0x0A); /* 400 kchip/s + * mode, step 8 + * ,SUB_MODE = 0 */ + } else { + trx_reg_write(RG_TRX_CTRL_2, 0x0E); /* 1000kchip/s */ + } + + txcwdata[0] = 1; /* length */ + txcwdata[1] = 0; + /* step 9: Frame buffer access */ + trx_frame_write(txcwdata, 2); + } else { /* PRBS mode */ + /* step 8: */ + + /* + * Step 8 is not explicitly written here, because the proper + * value is set during reset or by updating the Channel Page. + * After finishing CW/PRBS another reset is performed with + * parameter set_default_pib set to false, which restores the + * original value based on the current Channel Page. + * + * I.e., in order to use PRBS with a specific data rate, + * the Channel Page needs to be udpated before starting PRBS. + */ + + txcwdata[0] = 127U; /* = max length */ + for (uint8_t data_index = 1U; data_index < 128U; data_index++) { + if (randomContent) { + txcwdata[data_index] = (uint8_t)rand(); + } else { + txcwdata[data_index] = 0; + } + } + /* step 9: Frame buffer access */ + trx_frame_write(txcwdata, 128); + } + + /* step 10: Enable continuous transmission - step #2 */ + trx_reg_write(RG_PART_NUM, 0x54); + /* step 11: Enable continuous transmission - step #3 */ + trx_reg_write(RG_PART_NUM, 0x46); + /* step 12, 13: Stwitch PLL on */ + (void)set_trx_state(CMD_PLL_ON); + /* step 14: Initiate transmission using SLP_TR line */ + TRX_SLP_TR_HIGH(); + trx_delay_micros(1); + TRX_SLP_TR_LOW(); +} + + + +/* + * \brief Stops continuous transmission + */ +void PHY_StopContinuousTransmit(void) +{ + + + (void)PHY_Reset(false); +} + +/* + * \brief Initializes the TFA + * + * This function is called to initialize the TFA. + * + * \return MAC_SUCCESS if everything went correct; + * FAILURE otherwise + */ +PHY_Retval_t tfa_init(void) +{ + init_tfa_pib(); + write_all_tfa_pibs_to_trx(); + + return PHY_SUCCESS; +} + +/* + * \brief Reset the TFA + * + * This function is called to reset the TFA. + * + * \param set_default_pib Defines whether PIB values need to be set + * to its default values + */ +void tfa_reset(bool set_default_pib) +{ + if (set_default_pib) { + init_tfa_pib(); + } + + write_all_tfa_pibs_to_trx(); +} + +/** + * \brief Initialize the TFA PIB + * + * This function initializes the TFA information base attributes + * to their default values. + * \ingroup group_tfa + */ +static void init_tfa_pib(void) +{ + tfa_pib_rx_sens = TFA_PIB_RX_SENS_DEF; +} + +/** + * \brief Write all shadow PIB variables to the transceiver + * + * This function writes all shadow PIB variables to the transceiver. + * It is assumed that the radio does not sleep. + * \ingroup group_tfa + */ +static void write_all_tfa_pibs_to_trx(void) +{ + (void)tfa_pib_set(TFA_PIB_RX_SENS, (void *)&tfa_pib_rx_sens); +} + + + +/* + * \brief Sets a TFA PIB attribute + * + * This function is called to set the transceiver information base + * attributes. + * + * \param[in] tfa_pib_attribute TFA infobase attribute ID + * \param[in] value TFA infobase attribute value to be set + * + * \return MAC_UNSUPPORTED_ATTRIBUTE if the TFA info base attribute is not found + * TAL_BUSY if the TAL is not in TAL_IDLE state. + * MAC_SUCCESS if the attempt to set the PIB attribute was successful + */ +PHY_Retval_t tfa_pib_set(PHY_tfa_pib_t tfa_pib_attribute, void *value) +{ + switch (tfa_pib_attribute) { + case TFA_PIB_RX_SENS: + { + uint8_t reg_val; + int8_t rssi_base_val; + + switch (tal_pib.CurrentPage) { + case 0: /* BPSK */ + if (tal_pib.CurrentChannel == 0) { /* BPSK20 */ + rssi_base_val = RSSI_BASE_VAL_BPSK_300_DBM; + } else { /* BPSK40 */ + rssi_base_val = RSSI_BASE_VAL_BPSK_600_DBM; + } + + break; + + case 2: /* O-QPSK */ + if (tal_pib.CurrentChannel == 0) { /* OQPSK100 */ + rssi_base_val + = RSSI_BASE_VAL_OQPSK_400_SIN_RC_DBM; + } else { /* OQPSK250 */ + rssi_base_val + = RSSI_BASE_VAL_OQPSK_1000_SIN_DBM; + } + + break; + + case 5: /* Chinese band */ + rssi_base_val = RSSI_BASE_VAL_OQPSK_1000_RC_DBM; + break; + +#ifdef HIGH_DATA_RATE_SUPPORT + case 16: /* non-compliant OQPSK mode 1 */ + if (tal_pib.CurrentChannel == 0) { /* 200kbps, EU */ + rssi_base_val + = RSSI_BASE_VAL_OQPSK_400_SIN_RC_DBM; + } else { /* 500kbps, NA */ + rssi_base_val + = RSSI_BASE_VAL_OQPSK_1000_SIN_DBM; + } + + break; + + case 17: /* non-compliant OQPSK mode 2 */ + if (tal_pib.CurrentChannel == 0) { /* 400kbps, EU */ + rssi_base_val + = RSSI_BASE_VAL_OQPSK_400_SIN_RC_DBM; + } else { /* 1000kbps, NA */ + rssi_base_val + = RSSI_BASE_VAL_OQPSK_1000_SIN_DBM; + } + + break; + + case 18: /* Chinese band, non-compliant mode 1 using + * O-QPSK 500 */ + rssi_base_val = RSSI_BASE_VAL_OQPSK_1000_RC_DBM; + break; + + case 19: /* Chinese band, non-compliant mode 2 using + * O-QPSK 1000 */ + rssi_base_val = RSSI_BASE_VAL_OQPSK_1000_RC_DBM; + break; +#endif /* #ifdef HIGH_DATA_RATE_SUPPORT */ + default: + + /* is rather an unsupported channel page than an + * unsupported attribute + */ + return PHY_UNSUPPORTED_ATTRIBUTE; + break; + } + + tfa_pib_rx_sens = *((int8_t *)value); + + if (tfa_pib_rx_sens > (rssi_base_val + 45)) { + reg_val = 0xF; + tfa_pib_rx_sens = (rssi_base_val + 45); + } else if (tfa_pib_rx_sens <= rssi_base_val) { + reg_val = 0x0; + tfa_pib_rx_sens = rssi_base_val; + } else { + int8_t temp = ((tfa_pib_rx_sens - (rssi_base_val)) / 3) + 1; + reg_val = (uint8_t)temp; + } + + trx_reg_bit_write(SR_RX_PDT_LEVEL, reg_val); + } + break; + + default: + /* Invalid attribute id */ + return PHY_UNSUPPORTED_ATTRIBUTE; + break; + } + + return PHY_SUCCESS; +} + +/* + * \brief Gets a TFA PIB attribute + * + * This function is called to retrieve the transceiver information base + * attributes. + * + * \param[in] tfa_pib_attribute TAL infobase attribute ID + * \param[out] value TFA infobase attribute value + * + * \return MAC_UNSUPPORTED_ATTRIBUTE if the TFA infobase attribute is not found + * MAC_SUCCESS otherwise + */ +PHY_Retval_t tfa_pib_get(PHY_tfa_pib_t tfa_pib_attribute, void *value) +{ + switch (tfa_pib_attribute) { + case TFA_PIB_RX_SENS: + *(uint8_t *)value = tfa_pib_rx_sens; + break; + + default: + /* Invalid attribute id */ + return PHY_UNSUPPORTED_ATTRIBUTE; + break; + } + + return PHY_SUCCESS; +} + + + + + +/* EOF */ diff --git a/driver/software/RF212b/phy/inc/ieee_phy_const.h b/driver/software/RF212b/phy/inc/ieee_phy_const.h new file mode 100644 index 0000000..0cba625 --- /dev/null +++ b/driver/software/RF212b/phy/inc/ieee_phy_const.h @@ -0,0 +1,1702 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + + +#ifndef IEEE_PHY_CONST_H +#define IEEE_PHY_CONST_H + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* CCA Modes of the transceiver + + Summary: + CCA Modes supported by transceiver + + Description: + Following are the list of configuration parameters which can be read from the + transceiver + + Remarks: + None + */ + +typedef enum trx_cca_mode_tag { + TRX_CCA_MODE0 = 0, /** Carrier sense OR energy above threshold */ + TRX_CCA_MODE1 = 1, /** Energy above threshold */ + TRX_CCA_MODE2 = 2, /** Carrier sense only */ + TRX_CCA_MODE3 = 3 /** Carrier sense AND energy above threshold */ +} trx_cca_mode_t; + + +// ***************************************************************************** +/* CCA mode enumeration + + Summary: + CCA Modes supported by transceiver + + Description: + Following are CCA mode enumeration which can be read from the transceiver + + Remarks: + None + */ +typedef enum cca_mode_tag { + CCA_MODE_0_CS_OR_ED = 0, + CCA_MODE_1_ED = 1, /** To be conform to IEEE 15.4 and TRX register */ + CCA_MODE_2_CS, + CCA_MODE_3_CS_ED, + CCA_MODE_4_ALOHA +} cca_mode_t; + +// ***************************************************************************** +/* ch_pg enumeration + + Summary: + ch_pg_t holds ch_pg enumeration which can be read from the transceiver. + + Description: + None + + Remarks: + None + */ + +typedef enum ch_pg_tag { + CH_PG_2003 = 0, + CH_PG_2006 = 2, + CH_PG_CHINA = 5, + CH_PG_JAPAN = 6, + CH_PG_MSK = 7, + CH_PG_LRP_UWB = 8, + CH_PG_SUN = 9, + CH_PG_GENERIC_PHY = 10, + CH_PG_16 = 16, + CH_PG_18 = 18, + CH_PG_INVALID = 0xFF +} ch_pg_t; + +// ***************************************************************************** +// ***************************************************************************** +// Section: Macros +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Min Frame Length + + Summary: + This macro holds the Minimum size of a valid frame other than an Ack frame + Description: + None + Remarks: + None + */ + +#define MIN_FRAME_LENGTH (8U) + +// ***************************************************************************** +/* Max MGMT Frame Length + + Summary: + This macro holds the Maximum size of the management frame(Association Response frame) + Description: + None + Remarks: + None + */ + +#define MAX_MGMT_FRAME_LENGTH (30U) + +// ***************************************************************************** +// ***************************************************************************** +// Section: MAC Constants +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Max size of PHY packet + + Summary: + This macro holds the Maximum size of PHY packet + Description: + None + Remarks: + None + */ + +#define aMaxPHYPacketSize (127U) + +// ***************************************************************************** +/* Maximum turnaround Time + + Summary: + This macro holds Maximum turnaround Time of the radio to switch from Rx to Tx or + Tx to Rx in symbols + Description: + None + Remarks: + None + */ + +#define aTurnaroundTime (12U) + +// ***************************************************************************** +/* maximum size of an MPDU + + Summary: + This macro holds The maximum size of an MPDU, in octets, that can be followed by + a SIFS period + Description: + None + Remarks: + None + */ + +#define aMaxSIFSFrameSize (18U) + +/** + * The minimum number of symbols forming the CAP. This ensures that MAC + * commands can still be transferred to devices when GTSs are being used. + * An exception to this minimum shall be allowed for the accommodation + * of the temporary increase in the beacon frame length needed to perform GTS + * maintenance (see 7.2.2.1.3). + * @ingroup apiMacConst + */ +#define aMinCAPLength (440U) + +// ***************************************************************************** +/* + + Summary: + This macro holds The minimum number of octets added by the MAC sublayer to the PSDU + Description: + None + Remarks: + None + */ + +#define aMinMPDUOverhead (9U) + +// ***************************************************************************** +/* + + Summary: + This macro holds The number of slots contained in any superframe + Description: + None + Remarks: + None + */ + +#define aNumSuperframeSlots (16U) + +// ***************************************************************************** +/* + + Summary: + This macro holds The number of symbols forming the basic time period used by + the CSMA-CA algorithm + Description: + None + Remarks: + None + */ + +#define aUnitBackoffPeriod (20U) + + +// ***************************************************************************** +/* + + Summary: + This macro holds The number of symbols forming a superframe slot when the superframe + order is equal to 0 + Description: + None + Remarks: + None + */ + +#define aBaseSlotDuration (60U) + +// ***************************************************************************** +/* + + Summary: + This macro holds The number of symbols forming a superframe when the superframe + order is equal to 0 + Description: + None + Remarks: + None + */ + +#define aBaseSuperframeDuration (aBaseSlotDuration * \ + aNumSuperframeSlots) + +/** + * The number of superframes in which a GTS descriptor + * exists in the beacon frame of a PAN coordinator. + * @ingroup apiMacConst + */ +#define aGTSDescPersistenceTime (4U) + +/** + * The maximum number of octets added by the MAC + * sublayer to the payload of its beacon frame. + * @ingroup apiMacConst + */ +#define aMaxBeaconOverhead (75U) + +/** + * The maximum size, in octets, of a beacon payload. + * @ingroup apiMacConst + */ +#define aMaxBeaconPayloadLength (aMaxPHYPacketSize - aMaxBeaconOverhead) + +/** + * The number of consecutive lost beacons that will cause the MAC sublayer of + * a receiving device to declare a loss of synchronization. + * @ingroup apiMacConst + */ +#define aMaxLostBeacons (4U) + +/** + * The maximum number of octets that can be transmitted in the MAC Payload + * field. + * @ingroup apiMacConst + */ +#define aMaxMACPayloadSize (aMaxPHYPacketSize - aMinMPDUOverhead) + +/** + * The maximum number of octets added by the MAC sublayer to the PSDU without + * security. + * @ingroup apiMacConst + */ +#define aMaxMPDUUnsecuredOverhead (25U) + +/** + * The maximum number of octets that can be transmitted in the MAC Payload + * field of an unsecured MAC frame that will be guaranteed not to exceed + * aMaxPHYPacketSize. + * @ingroup apiMacConst + */ +#define aMaxMACSafePayloadSize (aMaxPHYPacketSize - \ + aMaxMPDUUnsecuredOverhead) +// ***************************************************************************** +// ***************************************************************************** +// Section: Standard PHY PIB attributes +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* phyCurrentChannel + + Summary: + This macro holds The RF channel to use for all following transmissions and receptions + Description: + None + Remarks: + None + */ + +#define phyCurrentChannel (0x00U) + +// ***************************************************************************** +/* phyChannelsSupported + + Summary: + This macro holds The 5 most significant bits (MSBs) (b27, ..., b31) of phyChannelsSupported + shall be reserved and set to 0, and the 27 LSBs (b0, b1, ..., b26) shall indicate + the status (1 = available, 0 = unavailable) for each of the 27 valid channels + (bk shall indicate the status of channel k). + Description: + None + Remarks: + None + */ + +#define phyChannelsSupported (0x01U) + +// ***************************************************************************** +/* phyTransmitPower + + Summary: + This macro holds The 2 MSBs represent the tolerance on the transmit power: + 00 = 1 dB 01 = 3 dB 10 = 6 dB The 6 LSBs represent a signed integer in + twos-complement format, corresponding to the nominal transmit power of the + device in decibels relative to 1 mW. The lowest value of phyTransmitPower + shall be interpreted as less than or equal to 32 dBm. + Description: + None + Remarks: + None + */ + +#define phyTransmitPower (0x02U) + +// ***************************************************************************** +/* phyCCAMode + + Summary: + This macro holds The CCA mode + - CCA Mode 1: Energy above threshold. CCA shall report a busy medium + upon detecting any energy above the ED threshold. + - CCA Mode 2: Carrier sense only. CCA shall report a busy medium only upon + the detection of a signal with the modulation and spreading characteristics + of IEEE 802.15.4. This signal may be above or below the ED threshold. + - CCA Mode 3: Carrier sense with energy above threshold. CCA shall report a + busy medium only upon the detection of a signal with the modulation and + spreading characteristics of IEEE 802.15.4 with energy above the ED threshold. + Description: + None + Remarks: + None + */ + +#define phyCCAMode (0x03U) + +// ***************************************************************************** +/* phyCurrentPage + + Summary: + This macro holds current PHY channel page. This is used in conjunction with + phyCurrentChannel to uniquely identify the channel currently being used + Description: + None + Remarks: + None + */ + +#define phyCurrentPage (0x04U) + +// ***************************************************************************** +/* phyMaxFrameDuration + + Summary: + This macro holds The maximum number of symbols in a frame: + = phySHRDuration + ceiling([aMaxPHYPacketSize + 1] x phySymbolsPerOctet) + Description: + None + Remarks: + None + */ + +#define phyMaxFrameDuration (0x05U) + +// ***************************************************************************** +/* phySHRDuration + + Summary: + This macro holds The duration of the synchronization header (SHR) in symbols + for the current PHY + Description: + None + Remarks: + None + */ + +#define phySHRDuration (0x06U) + +// ***************************************************************************** +/* phySymbolsPerOctet + + Summary: + This macro holds The number of symbols per octet for the current PHY + Description: + None + Remarks: + None + */ + +#define phySymbolsPerOctet (0x07U) + +// ***************************************************************************** +/* PHY_OVERHEAD + + Summary: + This macro holds Number of octets added by the PHY: 4 sync octets + SFD octet + Description: + None + Remarks: + None + */ + +#define PHY_OVERHEAD (5U) + +// ***************************************************************************** +// ***************************************************************************** +// Section: MAC PIB Attributes +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* macAckWaitDuration + + Summary: + This macro holds The maximum number of symbols to wait for an acknowledgment frame + to arrive following a transmitted data frame. This value is dependent on the currently + selected logical channel. For 0 <= phyCurrentChannel <= 10, this value is equal to 120. + For 11 <= phyCurrentChannel <= 26, this value is equal to 54. + Description: + None + Remarks: + None + */ + +#define macAckWaitDuration (0x40U) + +/** + * Indication of whether a coordinator is currently allowing association. + * A value of true indicates that association is permitted. + * + * - @em Type: Boolean + * - @em Range: true or false + * - @em Default: false + */ +#define macAssociationPermit (0x41U) + +/** + * Default value for PIB macAssociationPermit + */ +#define macAssociationPermit_def (false) + +/** + * Indication of whether a device automatically sends a data request command + * if its address is listed in the beacon frame. A value of true indicates + * that the data request command is automatically sent. + * + * - @em Type: Boolean + * - @em Range: true or false + * - @em Default: true + */ +#define macAutoRequest (0x42U) + +/** + * Default value for PIB macAutoRequest + */ +#define macAutoRequest_def (true) + +/** + * Indication of whether battery life extension, by reduction of coordinator + * receiver operation time during the CAP, is enabled. A value of + * true indicates that it is enabled. + * + * - @em Type: Boolean + * - @em Range: true or false + * - @em Default: false + */ +#define macBattLifeExt (0x43U) + +/** + * Default value for PIB macBattLifeExt + */ +#define macBattLifeExt_def (false) + +/** + * The number of backoff periods during which the receiver is enabled following + * a beacon in battery life extension mode. This value is dependent on the + * currently selected logical channel. For 0 <= * phyCurrentChannel <= 10, this + * value is equal to 8. For 11 <= * phyCurrentChannel <= 26, this value + * is equal to 6. + * + * - @em Type: Integer + * - @em Range: 6 or 8 + * - @em Default: 6 + */ +#define macBattLifeExtPeriods (0x44U) + +/** + * Default value for PIB macBattLifeExtPeriods + */ +#define macBattLifeExtPeriods_def (6U) + +/** + * The contents of the beacon payload. + * + * - @em Type: Set of octets + * - @em Range: -- + * - @em Default: NULL + */ +#define macBeaconPayload (0x45U) + +/** + * The length, in octets, of the beacon payload. + * + * - @em Type: Integer + * - @em Range: 0 - aMaxBeaconPayloadLength + * - @em Default: 0 + */ +#define macBeaconPayloadLength (0x46U) + +/** + * Default value for PIB macBeaconPayloadLength + */ +#define macBeaconPayloadLength_def (0U) + +/** + * Specification of how often the coordinator transmits a beacon. + * The macBeaconOrder, BO, and the beacon interval, BI, are related as + * follows: for 0 <= BO <= 14, BI = aBaseSuperframeDuration * 2^BO symbols. + * If BO = 15, the coordinator will not transmit a beacon. + * + * - @em Type: Integer + * - @em Range: 0 - 15 + * - @em Default: 15 + */ +#define macBeaconOrder (0x47U) + +/** + * Default value for PIB macBeaconOrder + */ +#define macBeaconOrder_def (15U) + +/** + * BO value for nonbeacon-enabled network + */ +#define NON_BEACON_NWK (0x0FU) + +/** + * The time that the device transmitted its last beacon frame, in symbol + * periods. The measurement shall be taken at the same symbol boundary within + * every transmitted beacon frame, the location of which is implementation + * specific. The precision of this value shall be a minimum of 20 bits, with + * the lowest four bits being the least significant. + * + * - @em Type: Integer + * - @em Range: 0x000000 - 0xffffff + * - @em Default: 0x000000 + */ +#define macBeaconTxTime (0x48U) + +/** + * Default value for PIB macBeaconTxTime + */ +#define macBeaconTxTime_def (0x000000U) + +/** + * The sequence number added to the transmitted beacon frame. + * + * - @em Type: Integer + * - @em Range: 0x00 - 0xFF + * - @em Default: Random value from within the range. + */ +#define macBSN (0x49U) + +/** + * The 64 bit address of the coordinator with which the device is associated. + * + * - @em Type: IEEE address + * - @em Range: An extended 64bit IEEE address + * - @em Default: - + */ +#define macCoordExtendedAddress (0x4AU) + +/** + * The 16 bit short address assigned to the coordinator with which the device + * is associated. A value of 0xfffe indicates that the coordinator is only + * using its 64 bit extended address. A value of 0xffff indicates that this + * value is unknown. + * + * - @em Type: Integer + * - @em Range: 0x0000 - 0xffff + * - @em Default: 0xffff + */ +#define macCoordShortAddress (0x4BU) + +/** + * Default value for PIB macCoordShortAddress + */ +#define macCoordShortAddress_def (0xFFFF) + +/** + * The sequence number added to the transmitted data or MAC command frame. + * + * - @em Type: Integer + * - @em Range: 0x00 - 0xFF + * - @em Default: Random value from within the range. + */ +#define macDSN (0x4CU) + +/** + * macGTSPermit is true if the PAN coordinator is to accept GTS requests, + * false otherwise. + * + * - @em Type: Boolean + * - @em Range: true or false + * - @em Default: true + */ +#define macGTSPermit (0x4DU) + +/** + * Default value for PIB macGTSPermit + */ +#define macGTSPermit_def (true) + +// ***************************************************************************** +/* macMaxCSMABackoffs + + Summary: + This macro holds The maximum number of backoffs the CSMA-CA algorithm will attempt + before declaring a channel access failure. + Description: + None + Remarks: + None + */ + +#define macMaxCSMABackoffs (0x4EU) + +// ***************************************************************************** +/* macMaxCSMABackoffs_def + + Summary: + This macro holds The Default value for PIB macMaxCSMABackoffs + Description: + None + Remarks: + None + */ + +#define macMaxCSMABackoffs_def (4U) + +// ***************************************************************************** +/* macMinBE + + Summary: + This macro holds The minimum value of the backoff exponent in the CSMA-CA + algorithm.Note that if this value is set to 0, collision avoidance is disabled + during the first iteration of the algorithm. Also note that for the slotted + version of the CSMACA algorithm with the battery life extension enabled, the + minimum value of the backoff exponent will be the lesser of 2 and the value of + macMinBE. + Description: + None + Remarks: + None + */ + +#define macMinBE (0x4FU) + +// ***************************************************************************** +/* macPANId + + Summary: + This macro holds The 16 bit identifier of the PAN on which the device is operating. + If this value is 0xffff, the device is not associated. + Description: + None + Remarks: + None + */ + +#define macPANId (0x50U) + +// ***************************************************************************** +/* macPANId_def + + Summary: + This macro holds The Default value for PIB macPANId + Description: + None + Remarks: + None + */ + +#define macPANId_def (0xFFFF) + +// ***************************************************************************** +/* macPromiscuousMode + + Summary: + This indicates whether the MAC sublayer is in a promiscuous (receive all) + mode. A value of true indicates that the MAC sublayer accepts all frames + received from the PHY. + Description: + None + Remarks: + None + */ + +#define macPromiscuousMode (0x51U) + +/** + * This indicates whether the MAC sublayer is to enable its receiver + * during idle periods. + * + * - @em Type: Boolean + * - @em Range: true or false + * - @em Default: false + */ +#define macRxOnWhenIdle (0x52U) + +/** + * Default value for PIB macRxOnWhenIdle + */ +#define macRxOnWhenIdle_def (false) + +// ***************************************************************************** +/* macShortAddress + + Summary: + This macro holds The 16 bit address that the device uses to communicate in + the PAN.If the device is a PAN coordinator, this value shall be chosen before + a PAN is started. Otherwise, the address is allocated by a coordinator during + association. A value of 0xfffe indicates that the device has associated but + has not been allocated an address. A value of 0xffff indicates that the device + does not have a short address. + Description: + None + Remarks: + None + */ + +#define macShortAddress (0x53U) + +// ***************************************************************************** +/* macShortAddress_def + + Summary: + This macro holds Default value for PIB macShortAddress + Description: + None + Remarks: + None + */ + +#define macShortAddress_def (0xFFFF) + +/** + * This specifies the length of the active portion of the superframe, including + * the beacon frame. The macSuperframeOrder, SO, and the superframe duration, + * SD, are related as follows: for 0 <= SO <= BO <= 14, SD = + * aBaseSuperframeDuration * 2SO symbols. If SO = 15, the superframe will + * not be active following the beacon. + * + * - @em Type: Integer + * - @em Range: 0 - 15 + * - @em Default: 15 + */ +#define macSuperframeOrder (0x54U) + +/** + * Default value for PIB macSuperframeOrder + */ +#define macSuperframeOrder_def (15U) + +/** + * The maximum time (in superframe periods) that a transaction is stored by a + * coordinator and indicated in its beacon. + * + * - @em Type: Integer + * - @em Range: 0x0000 - 0xffff + * - @em Default: 0x01f4 + */ +#define macTransactionPersistenceTime (0x55U) + +/** + * Default value for PIB macTransactionPersistenceTime + */ +#define macTransactionPersistenceTime_def (0x01F4) + +/** + * Indication of whether the device is associated to the PAN through the PAN + * coordinator. A value of TRUE indicates the device has associated through the + * PAN coordinator. Otherwise, the value is set to FALSE. + * + * - @em Type: Boolean + * - @em Range: true or false + * - @em Default: false + */ +#define macAssociatedPANCoord (0x56U) + +/** + * Default value for PIB macAssociatedPANCoord + */ +#define macAssociatedPANCoord_def (false) + + +// ***************************************************************************** +/* macMaxBE + + Summary: + This macro holds The maximum value of the backoff exponent, BE, in the CSMA-CA algorithm + Description: + None + Remarks: + None + */ + +#define macMaxBE (0x57U) + +/** + * The maximum number of CAP symbols in a beaconenabled PAN, or symbols in a + * nonbeacon-enabled PAN, to wait either for a frame intended as a response to + * a data request frame or for a broadcast frame following a beacon with the + * Frame Pending subfield set to one. + * This attribute, which shall only be set by the next higher layer, is + * dependent upon macMinBE, macMaxBE, macMaxCSMABackoffs and the number of + * symbols per octet. See 7.4.2 for the formula relating the attributes. + * + * - @em Type: Integer + * - @em Range: See equation (14) + * - @em Default: Dependent on currently selected PHY, indicated by + * phyCurrentPage + */ +#define macMaxFrameTotalWaitTime (0x58U) + +// ***************************************************************************** +/* macMaxFrameRetries + + Summary: + This macro holds The maximum number of retries allowed after a transmission failure + Description: + None + Remarks: + None + */ + +#define macMaxFrameRetries (0x59U) + +// ***************************************************************************** +/* macMaxFrameRetries + + Summary: + This macro holds PIB attribute without relevant index, i.e. PIB attribute not + contained in 802.15.4-2006 table 88. + Description: + None + Remarks: + None + */ + +#define NO_PIB_INDEX (0U) + +// ***************************************************************************** +/* macMinLIFSPeriod + + Summary: + This macro holds The minimum number of symbols forming a LIFS period. + Description: + None + Remarks: + None + */ + +#define macMinLIFSPeriod (0x5EU) + +// ***************************************************************************** +/* macMinLIFSPeriod_def + + Summary: + This macro holds The Default value for PIB macMinLIFSPeriod. + Description: + None + Remarks: + None + */ + +#define macMinLIFSPeriod_def (40U) + +// ***************************************************************************** +/* macMinSIFSPeriod + + Summary: + This macro holds The minimum number of symbols forming a SIFS period. + Description: + None + Remarks: + None + */ + +#define macMinSIFSPeriod (0x5FU) + +// ***************************************************************************** +/* macMinSIFSPeriod_def + + Summary: + This macro holds Default value for PIB macMinSIFSPeriod + Description: + None + Remarks: + None + */ + +#define macMinSIFSPeriod_def (12U) + +// ***************************************************************************** +/* macMinSIFSPeriod_def + + Summary: + This macro holds Private MAC PIB attribute to allow setting the MAC address + in test mode + Description: + None + Remarks: + None + */ + +#define macIeeeAddress (0xF0U) + +// ***************************************************************************** +// ***************************************************************************** +// Section: Non-standard values / extensions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* PHY_SUCCESS_DATA_PENDING + + Summary: + This macro holds PHY_SUCCESS in phyAutoCSMACA when received ACK frame had the + pending bit set + Description: + None + Remarks: + None + */ + +#define PHY_SUCCESS_DATA_PENDING (0x10U) + +// ***************************************************************************** +/* ED_SAMPLE_DURATION_SYM + + Summary: + This macro holds ED scan/sampling duration + Description: + None + Remarks: + None + */ + +#define ED_SAMPLE_DURATION_SYM (8U) + +// ***************************************************************************** +/* FCF_FRAMETYPE_BEACON + + Summary: + This macro holds Defines the beacon frame type. + Description: + None + Remarks: + None + */ + +#define FCF_FRAMETYPE_BEACON (0x00U) + +// ***************************************************************************** +/* FCF_FRAMETYPE_DATA + + Summary: + This macro holds Define the data frame type. + Description: + None + Remarks: + None + */ + +#define FCF_FRAMETYPE_DATA (0x01U) + +// ***************************************************************************** +/* FCF_FRAMETYPE_ACK + + Summary: + This macro holds Define the ACK frame type. + Description: + None + Remarks: + None + */ + +#define FCF_FRAMETYPE_ACK (0x02U) + +// ***************************************************************************** +/* FCF_FRAMETYPE_ACK + + Summary: + This macro holds Define the command frame type. + Description: + None + Remarks: + None + */ + +#define FCF_FRAMETYPE_MAC_CMD (0x03U) + +// ***************************************************************************** +/* FCF_FRAMETYPE_LLDN + + Summary: + This macro holds Define the LLDN frame type. + Description: + None + Remarks: + None + */ + +#define FCF_FRAMETYPE_LLDN (0x04U) + +// ***************************************************************************** +/* FCF_FRAMETYPE_MP + + Summary: + This macro holds Define the multipurpose frame type. + Description: + None + Remarks: + None + */ + +#define FCF_FRAMETYPE_MP (0x05U) + +// ***************************************************************************** +/* FCF_SET_FRAMETYPE + + Summary: + This macro holds to set the frame type. + Description: + None + Remarks: + None + */ + +#define FCF_SET_FRAMETYPE(x) (x) + +// ***************************************************************************** +/* FCF_SECURITY_ENABLED + + Summary: + This macro holds The mask for the security enable bit of the FCF. + Description: + None + Remarks: + None + */ + +#define FCF_SECURITY_ENABLED (1U << 3U) + +// ***************************************************************************** +/* FCF_FRAME_PENDING + + Summary: + This macro holds The mask for the frame pending bit of the FCF. + Description: + None + Remarks: + None + */ + +#define FCF_FRAME_PENDING (1U << 4U) + +// ***************************************************************************** +/* FCF_ACK_REQUEST + + Summary: + This macro holds The mask for the ACK request bit of the FCF. + Description: + None + Remarks: + None + */ + +#define FCF_ACK_REQUEST (1U << 5U) + +// ***************************************************************************** +/* FCF_PAN_ID_COMPRESSION + + Summary: + This macro holds The mask for the PAN ID compression bit of the FCF. + Description: + None + Remarks: + None + */ + +#define FCF_PAN_ID_COMPRESSION (1U << 6U) + +// ***************************************************************************** +/* FCF_FRAME_VERSION_2003 + + Summary: + This macro holds The mask for a IEEE 802.15.4-2003 compatible frame in the + frame version subfield. + Description: + None + Remarks: + None + */ + +#define FCF_FRAME_VERSION_2003 (0U << 12U) + +// ***************************************************************************** +/* FCF_FRAME_VERSION_2006 + + Summary: + This macro holds The mask for a IEEE 802.15.4-2006 compatible frame in the + frame version subfield. + Description: + None + Remarks: + None + */ + +#define FCF_FRAME_VERSION_2006 (1U << 12U) + +// ***************************************************************************** +/* FCF_FRAME_VERSION_2012 + + Summary: + This macro holds The mask for a IEEE 802.15.4-2012 compatible frame in the + frame version subfield. + Description: + None + Remarks: + None + */ + +#define FCF_FRAME_VERSION_2012 (2U << 12U) + +// ***************************************************************************** +/* FCF1_FV_SHIFT + + Summary: + This macro holds Shift value for the frame version subfield fcf1 + Description: + None + Remarks: + None + */ + +#define FCF1_FV_SHIFT (4U) + +// ***************************************************************************** +/* FCF1_FV_MASK + + Summary: + This macro holds The mask for the frame version subfield fcf1 + Description: + None + Remarks: + None + */ + +#define FCF1_FV_MASK (3U << FCF1_FV_SHIFT) + +// ***************************************************************************** +/* FCF1_FV_2003 + + Summary: + This macro holds The mask for a IEEE 802.15.4-2003 compatible frame in the + frame version subfield fcf1 + Description: + None + Remarks: + None + */ + +#define FCF1_FV_2003 (0U) + +// ***************************************************************************** +/* FCF1_FV_2006 + + Summary: + This macro holds The mask for a IEEE 802.15.4-2006 compatible frame in the + frame version subfield fcf1 + Description: + None + Remarks: + None + */ + +#define FCF1_FV_2006 (1U) + +// ***************************************************************************** +/* FCF1_FV_2012 + + Summary: + This macro holds The mask for a IEEE 802.15.4-2012 compatible frame in the + frame version subfield fcf1 + Description: + None + Remarks: + None + */ + +#define FCF1_FV_2012 (2U) + +// ***************************************************************************** +/* FCF_NO_ADDR + + Summary: + This macro holds Address Mode: NO ADDRESS + Description: + None + Remarks: + None + */ + +#define FCF_NO_ADDR (0x00U) + +// ***************************************************************************** +/* FCF_RESERVED_ADDR + + Summary: + This macro holds Address Mode: RESERVED + Description: + None + Remarks: + None + */ + +#define FCF_RESERVED_ADDR (0x01U) + +// ***************************************************************************** +/* FCF_SHORT_ADDR + + Summary: + This macro holds Address Mode: SHORT + Description: + None + Remarks: + None + */ + +#define FCF_SHORT_ADDR (0x02U) + +// ***************************************************************************** +/* FCF_LONG_ADDR + + Summary: + This macro holds Address Mode: LONG + Description: + None + Remarks: + None + */ + +#define FCF_LONG_ADDR (0x03U) + +// ***************************************************************************** +/* FCF_DEST_ADDR_OFFSET + + Summary: + This macro holds Defines the offset of the destination address + Description: + None + Remarks: + None + */ + +#define FCF_DEST_ADDR_OFFSET (10U) + +// ***************************************************************************** +/* FCF_SOURCE_ADDR_OFFSET + + Summary: + This macro holds Defines the offset of the source address + Description: + None + Remarks: + None + */ + +#define FCF_SOURCE_ADDR_OFFSET (14U) + +// ***************************************************************************** +/* FCF_SET_SOURCE_ADDR_MODE + + Summary: + This macro holds to set the source address mode + Description: + None + Remarks: + None + */ + +#define FCF_SET_SOURCE_ADDR_MODE(x) ((unsigned int)((x) << \ + FCF_SOURCE_ADDR_OFFSET)) + +// ***************************************************************************** +/* FCF_SET_DEST_ADDR_MODE + + Summary: + This macro holds to set the destination address mode + Description: + None + Remarks: + None + */ + +#define FCF_SET_DEST_ADDR_MODE(x) ((unsigned int)((x) << \ + FCF_DEST_ADDR_OFFSET)) + +// ***************************************************************************** +/* FCF_FRAMETYPE_MASK + + Summary: + This macro holds Defines a mask for the frame type + Description: + None + Remarks: + None + */ + +#define FCF_FRAMETYPE_MASK (0x07U) + +// ***************************************************************************** +/* FCF_GET_FRAMETYPE + + Summary: + This macro holds to get the frame type + Description: + None + Remarks: + None + */ + +#define FCF_GET_FRAMETYPE(x) ((x) & FCF_FRAMETYPE_MASK) + +/** + * Mask for the number of short addresses pending + */ +#define NUM_SHORT_PEND_ADDR(x) ((x) & 0x07U) + +/** + * Mask for the number of long addresses pending + */ +#define NUM_LONG_PEND_ADDR(x) (((x) & 0x70U) >> 4U) + +// ***************************************************************************** +/* BROADCAST + + Summary: + This macro holds Generic 16 bit broadcast address + Description: + None + Remarks: + None + */ + +#define BROADCAST (0xFFFF) + +// ***************************************************************************** +/* FCF_2_DEST_ADDR_OFFSET + + Summary: + This macro holds Offset of Destination Addressing Mode of octet two of MHR. + Description: + None + Remarks: + None + */ + +#define FCF_2_DEST_ADDR_OFFSET (2U) + +// ***************************************************************************** +/* FCF_2_SOURCE_ADDR_OFFSET + + Summary: + This macro holds Offset of Source Addressing Mode of octet two of MHR. + Description: + None + Remarks: + None + */ + +#define FCF_2_SOURCE_ADDR_OFFSET (6U) + + +// ***************************************************************************** +// Octet position within PHY_FrameInfo_t->payload array +// ***************************************************************************** + +// ***************************************************************************** +/* PL_POS_FCF_1 + + Summary: + This macro holds Octet position of FCF octet one within payload array of PHY_FrameInfo_t. + Description: + None + Remarks: + None + */ + +#define PL_POS_FCF_1 (1U) + +// ***************************************************************************** +/* PL_POS_FCF_2 + + Summary: + This macro holds Octet position of FCF octet two within payload array of PHY_FrameInfo_t. + Description: + None + Remarks: + None + */ + +#define PL_POS_FCF_2 (2U) + +// ***************************************************************************** +/* PL_POS_SEQ_NUM + + Summary: + This macro holds Octet position of Sequence Number octet within payload array of + PHY_FrameInfo_t. + Description: + None + Remarks: + None + */ + +#define PL_POS_SEQ_NUM (3U) + +// ***************************************************************************** +/* PL_POS_DST_PAN_ID_START + + Summary: + This macro holds Octet start position of Destination PAN-Id field within payload array of + PHY_FrameInfo_t. + Description: + None + Remarks: + None + */ + +#define PL_POS_DST_PAN_ID_START (4U) + +// ***************************************************************************** +/* PL_POS_DST_ADDR_START + + Summary: + This macro holds Octet start position of Destination Address field within payload array of + PHY_FrameInfo_t. + Description: + None + Remarks: + None + */ + +#define PL_POS_DST_ADDR_START (6U) + +// ***************************************************************************** +/* LENGTH_FIELD_LEN + + Summary: + This macro holds Size of the length parameter + Description: + None + Remarks: + None + */ + +#define LENGTH_FIELD_LEN (1U) + +// ***************************************************************************** +/* LQI_LEN + + Summary: + This macro holds Length of the LQI number field + Description: + None + Remarks: + None + */ + +#define LQI_LEN (1U) + +// ***************************************************************************** +/* ED_VAL_LEN + + Summary: + This macro holds Length of the ED value parameter number field + Description: + None + Remarks: + None + */ + +#define ED_VAL_LEN (1U) + +// ***************************************************************************** +/* FCF_LEN + + Summary: + This macro holds Length (in octets) of FCF + Description: + None + Remarks: + None + */ + +#define FCF_LEN (2U) + +// ***************************************************************************** +/* FCS_LEN + + Summary: + This macro holds Length (in octets) of FCS + Description: + None + Remarks: + None + */ + +#define FCS_LEN (2U) + +// ***************************************************************************** +/* SEQ_NUM_LEN + + Summary: + This macro holds Length of the sequence number field + Description: + None + Remarks: + None + */ + +#define SEQ_NUM_LEN (1U) + +// ***************************************************************************** +/* EXT_ADDR_LEN + + Summary: + This macro holds Length (in octets) of extended address + Description: + None + Remarks: + None + */ + +#define EXT_ADDR_LEN (8U) + +// ***************************************************************************** +/* SHORT_ADDR_LEN + + Summary: + This macro holds Length (in octets) of short address + Description: + None + Remarks: + None + */ + +#define SHORT_ADDR_LEN (2U) + +// ***************************************************************************** +/* PAN_ID_LEN + + Summary: + This macro holds Length (in octets) of PAN ID + Description: + None + Remarks: + None + */ + +#define PAN_ID_LEN (2U) + +// ***************************************************************************** +/* ACK_PAYLOAD_LEN + + Summary: + This macro holds Length (in octets) of ACK payload + Description: + None + Remarks: + None + */ + +#define ACK_PAYLOAD_LEN (0x03U) + +// ***************************************************************************** +/* CONV_phyTransmitPower_TO_DBM + + Summary: + This macro holds Converts a phyTransmitPower value to a dBm value + return dBm using signed integer format + Description: + None + Remarks: + None + */ + +#define CONV_phyTransmitPower_TO_DBM(phyTransmitPower_value) \ + ( \ + ((phyTransmitPower_value & 0x20U) == 0x00U) ? \ + ((int8_t)(phyTransmitPower_value & 0x3FU)) : \ + ((-1) * \ + (int8_t)((~((uint8_t)((phyTransmitPower_value & \ + 0x1FU) - 1U))) & 0x1FU)) \ + ) + +// ***************************************************************************** +/* CONV_DBM_TO_phyTransmitPower + + Summary: + This macro Converts a dBm value to a phyTransmitPower value + and return phyTransmitPower_value using IEEE-defined format + Description: + None + Remarks: + None + */ + +#define CONV_DBM_TO_phyTransmitPower(dbm_value) \ + ( \ + dbm_value < -32 ? \ + 0x20U : \ + ( \ + dbm_value > 31 ? \ + 0x1FU : \ + ( \ + dbm_value < 0 ? \ + (((~((uint8_t)(((uint8_t)((-1) * dbm_value)) - 1U))) & 0x1FU) | 0x20U) : \ + (uint8_t)dbm_value \ + ) \ + ) \ + ) + + + +//DOM-IGNORE-BEGIN +#ifdef __cplusplus +} +#endif +//DOM-IGNORE-END + +#endif /* IEEE_CONST_H */ +/* EOF */ diff --git a/driver/software/RF212b/phy/inc/phy.h b/driver/software/RF212b/phy/inc/phy.h new file mode 100644 index 0000000..39191eb --- /dev/null +++ b/driver/software/RF212b/phy/inc/phy.h @@ -0,0 +1,2000 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +#ifndef PHY_H +#define PHY_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: File includes +// ***************************************************************************** +// ***************************************************************************** + +#include +#include +#include "phy_config.h" +#include "../../resources/buffer/inc/bmm.h" +#include "../../resources/queue/inc/qmm.h" +#include "ieee_phy_const.h" + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* PIB value types + + Summary: + Union of different PHY Pib value types + + Description: + PibValue_t is used as the data type to set/get the different PHY Information + Base value + + Remarks: + None +*/ + +typedef union { + /** PIB Attribute Bool */ + bool pib_value_bool; + /** PIB Attribute 8-bit */ + uint8_t pib_value_8bit; + /** PIB Attribute 16-bit */ + uint16_t pib_value_16bit; + /** PIB Attribute 32-bit */ + uint32_t pib_value_32bit; + /** PIB Attribute 64-bit */ + uint64_t pib_value_64bit; +} PibValue_t; + +// ***************************************************************************** +/* PHY Configuration Parameters + + Summary: + PHY Configuration parameters supported by transceiver + + Description: + Following are the list of configuration parameters which can be read from the + transceiver + + Remarks: + None + */ + +typedef enum param_tag { + /** Antenna Diversity */ + ANT_DIVERSITY = 0x00, + /** Antenna Configured - ANTENNA_1/ANTENNA_2*/ + ANT_SELECT_ = 0x01, + /** Antenna Control */ + ANT_CTRL_ = 0x02, + /** Promiscuous Mode*/ + AACK_PROMSCS_MODE = 0x03, + CC_BAND = 0x04, + CC_NUMBER = 0x05, + /** Tx Power Configured*/ + TX_PWR = 0x06, + /** Rx Sensitivity*/ + RX_SENS = 0x07, + /** Automatic acknowledgement*/ + RX_AUTO_ACK = 0x09, + /** Reserved frame reception*/ + RX_RESERVED_FRAME = 0x0A, + /** Filter reserved frame*/ + FILTER_RESERVED_FRAME = 0x0B, +}PHY_ConfigParam_t; + +// ***************************************************************************** +/* PHY Frame information structure + + Summary: + PHY_FrameInfo_t holds the data to be transmitted or the data being received + by the transceiver. + + Description: + None + + Remarks: + None + */ + +typedef struct frame_info_tag +{ + /** Pointer to buffer header of frame */ + buffer_t *buffer_header; + /** Pointer to MPDU */ + uint8_t *mpdu; +} PHY_FrameInfo_t; + +// ***************************************************************************** +/* PHY Sleep Modes + + Summary: + Sleep Modes supported by transceiver + + Description: + List of sleep modes supported by the transceiver. If, TRX is set to SLEEP_MODE_1, + the TRX register contents are retained. If, TRX is set to DEEP_SLEEP_Mode + state the register contents are cleared + + Remarks: + None + */ + +typedef enum sleep_mode_tag { + SLEEP_MODE_1, +} PHY_SleepMode_t; + +// ***************************************************************************** +/* PHY CSMA Modes + + Summary: + List of carrier sense multiple access with collision avoidance + supported by PHY Layer + + Description: + When Transmit function is called with PHYCSMAMode of + NO_CSMA_NO_IFS - Immediate Tx and SIFS(Short InterFrameSpacing) between + subsequent frames + NO_CSMA_WITH_IFS - Immediate Tx and LIFS (Long InterFrameSpacing) between + subsequent frames + CSMA_UNSLOTTED - Hardware CSMA will be performed before packet transmission + with number of retries configured + CSMA_SLOTTED - Hardware CSMA will be performed - Used with Beacon + Enabled network - Currently not supported by PHY + Remarks: + None + */ + +typedef enum csma_mode_tag { + NO_CSMA_NO_IFS, + NO_CSMA_WITH_IFS, + CSMA_UNSLOTTED, + CSMA_SLOTTED +} PHY_CSMAMode_t; + +// ***************************************************************************** +/** Transceiver commands */ +typedef enum tfa_pib_tag { + TFA_PIB_RX_SENS = 0 +} PHY_tfa_pib_t; + +/* PHY Continuous Transmission test Modes + + Summary: + List of Continuous Transmission Test Modes supported by transceiver + + Description: + CW_MODE - Continuous Wave mode to transmit the signal at Fc +&- 0.5MHz frequency + PRBS_MODE - PRBS mode to Pseudorandom Binary Sequence frame continuously + + Remarks: + None + */ + +typedef enum continuous_tx_mode_tag { + /* Continuous Wave mode to transmit + * the signal at Fc +&- 0.5MHz frequency */ + CW_MODE = 0, + /* PRBS mode to Pseudorandom Binary Sequence frame continuously */ + PRBS_MODE = 1, + CW_MODE_2 = 2, + CW_ALL_ZEROS_MODE = 3 +} PHY_ContinuousTxMode_t; + + +// ***************************************************************************** +/* PHY Return Values + + Summary: + List of return status for the PHY functions + + Description: + None + Remarks: + None + */ + +typedef enum phy_return_value_tag { + /* General Success condition*/ + PHY_SUCCESS = 0x00, + /* Transceiver is currently sleeping */ + PHY_TRX_ASLEEP = 0x81, + /* Transceiver is currently awake */ + PHY_TRX_AWAKE = 0x82, + /* General failure condition */ + PHY_FAILURE = 0x85, + /* PHY busy condition */ + PHY_BUSY = 0x86, + /* Frame pending at PHY */ + PHY_FRAME_PENDING = 0x87, + /*A parameter in the set/get request is either not supported or is out ofthe valid range*/ + PHY_INVALID_PARAMETER = 0x88, + /*A SET/GET request was issued with the identifier of a PIB attribute that is not supported */ + PHY_UNSUPPORTED_ATTRIBUTE = 0x89, + /* The CCA attempt has detected a busy channel.*/ + PHY_CHANNEL_BUSY = 0x8A, + /* The CCA attempt has detected an idle channel.*/ + PHY_CHANNEL_IDLE = 0x8B, + /* TRX received no ack for the previously sent packet*/ + PHY_NO_ACK = 0x8C, + /* Transmit is failed due to Channel access failure*/ + PHY_CHANNEL_ACCESS_FAILURE = 0x8D + +}PHY_Retval_t; + + // ***************************************************************************** +/* PHY Transceiver State Values + + Summary: + Enumeration for Transceiver States that can be set + + Description: + None + Remarks: + None + */ + +typedef enum phy_trx_state_tag{ + /* Transceiver to be configured to Transceiver OFF state*/ + PHY_STATE_TRX_OFF, + /* Transceiver to be configured to Receiver ON state */ + PHY_STATE_RX_ON +}PHY_TrxState_t; + + // ***************************************************************************** +/* PHY Transceiver Status Values + + Summary: + Enumeration for current state of the Transceiver + Description: + None + Remarks: + None + */ + +typedef enum phy_trx_status_tag{ + /* Transceiver is in Transceiver OFF state*/ + PHY_TRX_OFF = 0x08, + /* Transceiver is in Receiver ON state */ + PHY_RX_ON = 0x16, + /* Transceiver is in Transmit ON state */ + PHY_TX_ON = 0x19, + /* Transceiver is currently receiving the packet*/ + PHY_BUSY_RX = 0x11, + /* Transceiver is currently transmitting the packet */ + PHY_BUSY_TX = 0x12, + /* Transceiver is in sleep state */ + PHY_TRX_SLEEP = 0x0F, + /* Transceiver is in Deep sleep state */ + PHY_TRX_DEEP_SLEEP = 0x20 +}PHY_TrxStatus_t; + +// ***************************************************************************** +// ***************************************************************************** +// Section: Macros +// ***************************************************************************** +#define TFA_PIB_RX_SENS_DEF (RSSI_BASE_VAL_BPSK_600_DBM) +// ***************************************************************************** + +// ***************************************************************************** +/* Custom PHY PIB attribute ID + + Summary: + Seting this attribute enables the device as PAN Coordinator + Description: + if only source addressing fields are included in a data or MAC command frame, + the frame shall be accepted only if the device is the PAN coordinator and + the source PAN identifier matches macPANId, for details refer to + IEEE 802.15.4-2006, Section 7.5.6.2 (third-level filter rule six + Remarks: + None + */ + +#define mac_i_pan_coordinator (0x0B) + +// ***************************************************************************** +/* Macro to convert Symbols to Microsecond + + Summary: + This macro function converts the given symbol value to microseconds + Description: + None + Remarks: + None + */ +#define PHY_CONVERT_SYMBOLS_TO_US(symbols) \ + (tal_pib.CurrentPage == 0 ? \ + (tal_pib.CurrentChannel == \ + 0 ? ((uint32_t)(symbols) * 50) : ((uint32_t)(symbols) * \ + 25)) : \ + (tal_pib.CurrentChannel == \ + 0 ? ((uint32_t)(symbols) * 40) : ((uint32_t)(symbols) << \ + 4)) \ + ) + +// ***************************************************************************** +/* Macro to convert Microsecond to symbols + + Summary: + This macro function converts the given time in microseconds to symbols + Description: + None + Remarks: + None + */ +#define PHY_CONVERT_US_TO_SYMBOLS(time) \ + (tal_pib.CurrentPage == 0 ? \ + (tal_pib.CurrentChannel == 0 ? ((time) / 50) : ((time) / 25)) : \ + (tal_pib.CurrentChannel == 0 ? ((time) / 40) : ((time) >> 4)) \ + ) +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +// Section: Release Version Macros +// ***************************************************************************** +// ***************************************************************************** + + +/* Major Number + + Summary: + This macro holds the stack Major number + Description: + None + Remarks: + None + */ +#define MAJOR_NUM "1" + + +/* Minor Number + + Summary: + This macro holds the stack Minor number + Description: + None + Remarks: + None + */ +#define MINOR_NUM "0" + +/* Patch Number + + Summary: + This macro holds the stack patch number + Description: + None + Remarks: + None + */ +#define PATCH_NUM "0" + + +/* PHY Version + + Summary: + This macro holds the PHY SW version as a String + Description: + None + Remarks: + None + */ +#if (defined RC_NUM) +#define PHY_VER "802.15.4-PHY v" MAJOR_NUM"." MINOR_NUM"." PATCH_NUM"-rc." RC_NUM +#else +#define PHY_VER "802.15.4-PHY v" MAJOR_NUM"." MINOR_NUM"." PATCH_NUM +#endif + +/* Release version information in 32-bit bitfield + +| bit pos | field name | meaning | +|---------|-----------------|------------------------------ | +| 0-13 | reserved | NA | +| 14-17 | build itreation | running version of this release| +| 18-19 | qualifier | 00 - reserved | +| | | 01 - Production (P) | +| | | 10 - Engineering (E) | +| | | 11 - reserved | +| 20-23 | stack minor | minor version | +| 24-27 | stack major | major version | +| 28-31 | reserved | NA | + + +Example: + 802.15.4-PHY v1.0.0 is represented as 0x01040000 + +|0000 |0001 | 0000 | 01 | 0000 | 00000000000000| +|-----------|------------|-------------|-----------|----------------|---------------| +|Reserved | Stack Major| Stack Minor | Qualifier | Build Iteration| Reserved | +*/ + + +/* PHY Software Version Information in 32-bit bitfield + + Summary: + This macro holds PHY Software Version Information in 32-bit bitfield + Description: + None + Remarks: + None +*/ +#define PHY_VERSION_VALUE (0x01040000) + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY PIB Attribute List +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* PHY Information Base (PIB) Attribute list + +| PIB Attribute |AccessType| Type | DefaultValue | Range | +|---------------------|----------|---------|------------------|-----------------| +| phyCurrentChannel | Get/Set | uint8_t | 01 | 00 - 10 | +| phyChannelsSupported| Get | uint32_t| 0x000007FF | NA | +| phyCurrentPage | Get/Set | uint8_t | 0 |0,2,5,16,17,18,19| +| phyTransmitPower | Get/Set | uint8_t | | | +| phyCCAMode | Get/Set | uint8_t | 1 | 0 - 3 | +| macIeeeAddress | Get/Set | uint64_t| All 0's | NA | +| macShortAddress | Get/Set | uint16_t| 0xFFFF | 0x0000 - 0xFFFF | +| macPANId | Get/Set | uint16_t| 0xFFFF | 0x0000 - 0xFFFF | +| macMinBE | Get/Set | uint8_t | 3 | 0 - 3 | +| macMaxBE | Get/Set | uint8_t | 5 | 3 - 8 | +| macMaxCSMABackoffs | Get/Set | uint8_t | 4 | 0 - 5 | +| macMaxFrameRetries | Get/Set | uint8_t | 3 | 0 - 7 | +| macPromiscuousMode | Get/Set | bool | 0 | 0 or 1 | +| phySHRDuration | Get | uint8_t |pg0-40sym/10Symbols| NA | +| phySymbolsPerOctet | Get | uint8_t |pg0-8sym else 2Symbol| NA | +| phyMaxFrameDuration | Get | uint16_t| | NA | +| macIpanCoordinator | Get/Set | bool | 0 | 0 or 1 | + */ + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY Task Handler Funtions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + void PHY_TaskHandler ( void ) + + Summary: + PHY Task Handling routine + + Description: + This function + - Checks and allocates the receive buffer. + - Processes the PHY incoming frame queue. + - Implements the PHY state machine. + + Precondition: + PHY_Init should be called before calling this function + + Parameters: + None. + + Returns: + None. + + Example: + + PHY_TaskHandler(); + + + Remarks: + This routine must be called from the RTOS Task function incase of any + RTOS is used. +*/ +void PHY_TaskHandler(void); + +// ***************************************************************************** +/* + Function: + void TAL_TaskHandler ( void ) + + Summary: + TAL Task Handling routine + + Description: + This function handles the transceiver interrupts + + Precondition: + PHY_Init should be called before calling this function + + Parameters: + None. + + Returns: + None. + + Example: + + TAL_TaskHandler(); + + + Remarks: + This routine must be called from the RTOS Task function incase of any + RTOS is used. +*/ +void TAL_TaskHandler(void); + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY Initialization and Reset Routines +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_Init( void ) + + Summary: + Initialization of PHY Layer + + Description: + This function is called to initialize the PHY layer. The transceiver is + initialized and it will be in PHY_STATE_TRX_OFF, the PHY PIBs are set to + their default values. PAL layer is initialized + + Precondition: + SYS_Load_Cal(WSS_ENABLE_ZB) function of device support library should be + called before calling this function. + + Parameters: + None. + + Returns: + PHY_SUCCESS - If the transceiver state is changed to TRX_OFF + PHY_FAILURE - Otherwise + + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + + retVal = PHY_Init(); + if (PHY_SUCCESS =! retVal) + { + while(1); + } + + + Remarks: + This routine must be called before any of the PHY function is called +*/ +PHY_Retval_t PHY_Init(void); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_Reset( bool setDefaultPibs ) + + Summary: + Resets the PHY Layer + + Description: + This function is called to Resets PHY state machine + and sets the default PIB values if requested + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + setDefaultPibs - Defines whether PIB values need to be set + to its default values + + Returns: + PHY_SUCCESS - If the transceiver state is changed to TRX_OFF and PIBs are set + to their default value + PHY_FAILURE - Otherwise + + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + bool setDefault = false; + + retVal = PHY_Reset(setDefault); + if (PHY_SUCCESS =! retVal) + { + while(1); + } + + + Remarks: + None +*/ + +PHY_Retval_t PHY_Reset(bool set_default_pib); + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY Tranmission Routines +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_TxFrame(PHY_FrameInfo_t *txFrame, PHY_CSMAMode_t csmaMode, + bool performFrameRetry) + + Summary: + Request to PHY to transmit frame + + Description: + This function is called by the upper layer (MAC/Application) to deliver a + frame to the PHY to be transmitted by the transceiver. + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + txFrame - Pointer to the PHY_FrameInfo_t structure or + to frame array to be transmitted + txFrame->mpdu - Pointer to the PHY Payload. mpdu[0] should hold + the length of the payload(N) + 1 (for length field length) + txFrame->mpdu[1-N] - Hold the phyPayload + + csmaMode - Indicates mode of csma-ca to be performed for this frame + NO_CSMA_NO_IFS - Immediate Tx and SIFS(Short InterFrameSpacing) + between subsequent frames + NO_CSMA_WITH_IFS - Immediate Tx and LIFS (Long InterFrameSpacing) + between subsequent frames + CSMA_UNSLOTTED - Hardware CSMA will be performed before packet + transmission with number of retries configured + CSMA_SLOTTED - Hardware CSMA will be performed - Used with + Beacon Enabled network - Currently not supported + by PHY + performFrameRetry - Indicates whether to retries are to be performed + for this frame + true - SW retry will be performed for macMaxFrameRetries + value + false- SW retry is disabled + + Returns: + PHY_SUCCESS - If PHY has accepted the data from the MAC for frame + transmission + PHY_BUSY - If PHY is busy servicing the previous MAC request + + Example: + + uint8_t txBuffer[LARGE_BUFFER_SIZE]; + uint8_t txData[] = "Wireless!!!"; + PHY_CSMAMode_t csmaMode = CSMA_UNSLOTTED; + bool performRetry = true; + PHY_FrameInfo_t txFrame; + + txFrame.mpdu = txBuffer; + txBuffer[0] = sizeof(txData); + memcpy((uint8_t *)&txBuffer[1], txData, sizeof(txData)); + + if(PHY_SUCCESS == PHY_TxFrame(&txFrame, csmaMode, performRetry)) + { + Frame transmitted successfully + } + + + Remarks: + None +*/ +PHY_Retval_t PHY_TxFrame(PHY_FrameInfo_t *txFrame, PHY_CSMAMode_t csmaMode, + bool performFrameRetry); + +// ***************************************************************************** +/* + Function: + void PHY_TxDoneCallback(PHY_Retval_t status, PHY_FrameInfo_t *frame) + + Summary: + User callback function for the transmission of a frame + + Description: + This callback function SHOULD be defined by the upper layer(Application/MAC) + for getting the status of last transmitted packet. + + Precondition: + This is a Asynchronous function call for the transmission of a frame + + Parameters: + status - Status of frame transmission attempt + PHY_SUCCESS - The transaction was responded to by a valid ACK, + or, if no ACK is requested, after a successful + frame transmission. + PHY_FRAME_PENDING - Equivalent to SUCCESS and indicating that + the ?Frame Pending? bit of the received + acknowledgment frame was set. + PHY_CHANNEL_ACCESS_FAILURE - Channel is still busy after attempting + MAX_CSMA_RETRIES of CSMA-CA. + PHY_NO_ACK - No acknowledgement frames were received + during all retry attempts. + PHY_FAILURE - Transaction not yet finished. + PHY_RF_REQ_ABORTED - RF is busy performing Higher priority BLE task + and the transmission is aborted + PHY_RF_UNAVAILABLE - RF is currently unavailable for 15.4 subsystem + + frame - Pointer to the PHY_FrameInfo_t structure or + to frame array to be transmitted + txFrame->mpdu - Pointer to the PHY Payload. mpdu[0] should hold + the length of the payload(N) + 1 (for length field length) + txFrame->mpdu[1-N] - Hold the phyPayload + + Returns: + None + + Example: + + void PHY_TxDoneCallback(PHY_Retval_t status, PHY_FrameInfo_t *frame) + { + Keep compiler happy. + status = status; + frame = frame; + } + + + Remarks: + None +*/ +void PHY_TxDoneCallback(PHY_Retval_t status, PHY_FrameInfo_t *frame); + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY Energy Detaction Functions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_EdStart(uint8_t scan_duration) + + Summary: + Starts ED Scan + + Description: + This function starts an ED Scan for the scan duration specified by the + upper layer. Actual ED result of Energy level on current channel will be + indicated by PHY_EdEndCallback(eneryLevel). + Scan duration formula: aBaseSuperframeDuration * (2^SD + 1) symbols + where SD - scanDuration parameter (0 - 14) + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + scanDuration - Specifies the ED scan duration in symbols + Range - (0 to 14) + + Returns: + PHY_SUCCESS - ED scan is started successfully + PHY_BUSY - PHY is busy servicing the previous request + PHY_TRX_ASLEEP - Transceiver is currently sleeping, wakeup the transceiver + using PHY_TrxWakeup() function + PHY_FAILURE otherwise + + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + uint8_t scanDurationSym = 1; + + retVal = PHY_EdStart(scanDurationSym); + if (PHY_SUCCESS =! retVal) + { + ED scan cannot be started at this moment + } + + + Remarks: + PHY_EdEndCallback(energyLevel) will be called after scanning the current + channel for a time period of aBaseSuperframeDuration * (2^scanDuration + 1) symbols + For scanDuration of value 0, ScanTime = 960 *(2^0 +1) + = 1920 symbols = 30720 us +*/ +PHY_Retval_t PHY_EdStart(uint8_t scan_duration); + +// ***************************************************************************** +/* + Function: + void PHY_EdEndCallback(uint8_t energyLevel) + + Summary: + User callback function for Energy detection + + Description: + This function SHOULD be defined by the upperlayer (Application/MAC layer) + in order to get the energyLevel on the current channel which is being scanned + for a period of scanDuration symbols + + Precondition: + This is an Asynchronous function call for the energy scan complete + + Parameters: + energyLevel - Measured energy level during ED Scan + + With energy_level, the RF input power can be calculated as follows + PRF[dBm] = RSSI_BASE_VAL[dBm] + 1[dB] x energy_level + + Returns: + None + + Example: + + void PHY_EdEndCallback(uint8_t energyLevel) + { + int8_t energyLeveldBm = (int8_t) (PHY_GetRSSIBaseVal() + energyLevel); + energyLevel = energyLevel; + } + + + Remarks: + None +*/ +void PHY_EdEndCallback(uint8_t energyLevel); + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY Information Base Set/Get Functions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_PibGet(uint8_t attribute, uint8_t *value) + + Summary: + Gets a PHY PIB attribute + + Description: + This function is called to retrieve the transceiver information base + attributes. The list of PHY PIB attributes, its default values and + range are described in the above table. + For more information refer ieee_phy_const.h file + + Precondition: + PHY_init() should have been called before calling this function. + + Parameters: + attribute - PHY infobase attribute ID + value - Pointer to the PHY infobase attribute value + + Returns: + PHY_UNSUPPORTED_ATTRIBUTE - If the PHY infobase attribute is not found + PHY_SUCCESS - otherwise + + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + uint8_t phyChannel; + uint8_t shortAddr; + + Getting Current channel + retVal = PHY_PibGet(phyCurrentChannel, &phyChannel); + if(PHY_SUCCESS == retVal) + { + printf("\r\n PHY Current Channel - %d",phyChannel ); + } + + Getting short Address + retVal = PHY_PibGet(macShortAddr, &shortAddr); + if(PHY_SUCCESS == retVal) + { + printf("\r\n Device short addr - 0x%x",shortAddr ); + } + + + + Remarks: + None +*/ +PHY_Retval_t PHY_PibGet(uint8_t attribute, uint8_t *value); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_PibSet(uint8_t attribute, PibValue_t *value) + + Summary: + Sets the PHY PIB attribute with value + + Description: + This function is called to set the transceiver information base + attributes. The list of PHY PIB attributes, its default values and + range are described in the above table. + For more information refer ieee_phy_const.h file + + Precondition: + PHY_init() should have been called before calling this function. + + Parameters: + attribute - PHY infobase attribute ID + value - Pointer to the PHY infobase attribute value to be set + + Returns: + PHY_UNSUPPORTED_ATTRIBUTE - if the PHY info base attribute is not + found + PHY_BUSY - If the PHY is not in PHY_IDLE state. An exception is + macBeaconTxTime which can be accepted by PHY even if PHY is not + in PHY_IDLE state. + PHY_SUCCESS - If the attempt to set the PIB attribute was successful + PHY_TRX_ASLEEP - If trx is in SLEEP mode and access to trx is + required + + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + uint8_t phyChannel = 15; + uint8_t shortAddr = 0x1234; + PibValue_t pibValue; + + Setting Current channel + pibValue.pib_value_8bit = phyChannel; + retVal = PHY_PibSet(phyCurrentChannel, &pibValue); + if(PHY_SUCCESS == retVal) + { + Channel is configured + } + + Setting short Address + pibValue.pib_value_16bit = shortAddr; + retVal = PHY_PibSet(macShortAddr, &pibValue); + if(PHY_SUCCESS == retVal) + { + Short Address is configured + } + + + + Remarks: + None +*/ +PHY_Retval_t PHY_PibSet(uint8_t attribute, PibValue_t *value); + + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY Reception Functions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + PHY_TrxStatus_t PHY_RxEnable(PHY_TrxState_t state) + + Summary: + Switches receiver on or off + + Description: + This function switches the receiver on (PHY_STATE_RX_ON) or off (PHY_STATE_TRX_OFF) + + Precondition: + PHY_init() should have been called before calling this function. + + Parameters: + state - State of the Transceiver to be set + PHY_STATE_RX_ON - Transceiver will be put into Receive state + PHY_STATE_TRX_OFF - Transceiver will be put into OFF state + + Returns: + PHY_TRX_OFF- If receiver has been switched off, or + PHY_RX_ON - otherwise. + + Example: + + PHY_TrxStatus_t trxStatus; + PHY_TrxState_t trxState = PHY_STATE_RX_ON; + + trxStatus = PHY_RxEnable(trxState); + if(PHY_RX_ON == trxStatus) + { + TRX is in receive state + } + + + Remarks: + None +*/ +PHY_TrxStatus_t PHY_RxEnable(PHY_TrxState_t state); + +// ***************************************************************************** +/* + Function: + void PHY_RxFrameCallback(PHY_FrameInfo_t *rxFrame) + + Summary: + User callback function for the reception of a frame + + Description: + This callback function SHOULD be defined by the upper layer(Application/MAC) + for getting the received frame details + + Precondition: + This is a Asynchronous function call for the reception of a frame + + Parameters: + rxFrame - Pointer to received frame structure of type PHY_FrameInfo_t + or to received frame array + rxFrame->buffer_header - BMM Buffer Header of the frame + rxFrame->mpdu - Actual MPDU comprises of + mpdu[0] - Payload Length(N) + mpdu[1-N]- Payload + mpdu[N+1]- LQI of received packet + mpdu[N+2]- ED_LEVEL of received packet + + Returns: + None + + Example: + + uint8_t rxBuffer[LARGE_BUFFER_SIZE]; + uint8_t frameLen, frameLQI, frameED; + int8_t frameRSSI; + void PHY_RxFrameCallback(PHY_FrameInfo_t *frame) + { + printf("\n--RxCallbackreceived--"); + frameLen = frame->mpdu[0]; + Copy the payload + memcpy(rxBuffer, (uint8_t *)&(frame->mpdu[1]), frameLen); + Copy the LQI + frameLQI = frame->mpdu[frameLen+LQI_LEN]; + Copy the RSSI + frameED = frame->mpdu[frameLen+LQI_LEN+ED_VAL_LEN]; + + frameRSSI = (int8_t)(frameED + PHY_GetRSSIBaseVal()); + + free the buffer that was used for frame reception + bmm_buffer_free((buffer_t *)(frame->buffer_header)); + } + + + Remarks: + None +*/ +void PHY_RxFrameCallback(PHY_FrameInfo_t *rxFrame); + + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY TRX Power Management Functions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_TrxSleep(PHY_SleepMode_t mode) + + Summary: + Sets the transceiver to sleep + + Description: + This function sets the transceiver to sleep or deep sleep state. + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + mode - Defines sleep mode of transceiver SLEEP or DEEP_SLEEP + + Returns: + PHY_BUSY - The transceiver is busy in TX or RX + PHY_SUCCESS - The transceiver is put to sleep + PHY_TRX_ASLEEP - The transceiver is already asleep + + Example: + + PHY_SleepMode_t sleepMode = SLEEP_MODE_1; + bool trxSleepStatus = false; + + if (PHY_SUCCESS == PHY_TrxSleep(sleepMode)) + { + trxSleepStatus = true; + } + + + Remarks: + When TRX is put into DeepSleep, the TRX registers are reset and it will hold + default values, PIB values are getting written by PHY layer when Wakeup + function is called.User has to reconfigure the configuration parameters + (PHY_ConfigParam_t) which are set by application. This procedure is not + needed for SLEEP mode as the TRX register values are retained. +*/ +PHY_Retval_t PHY_TrxSleep(PHY_SleepMode_t mode); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_TrxWakeup(void) + + Summary: + Wakes up the transceiver from sleep + + Description: + This function awakes the transceiver from sleep state. + + Precondition: + PHY_TrxSleep() should have been called before calling this function + + Parameters: + None + + Returns: + PHY_TRX_AWAKE - The transceiver is already awake + PHY_SUCCESS - The transceiver is woken up from sleep + PHY_FAILURE - The transceiver did not wake-up from sleep + + Example: + + PHY_SleepMode_t sleepMode = SLEEP_MODE_1; + bool trxSleepStatus = false; + Set Transceiver to sleep + if (PHY_SUCCESS == PHY_TrxSleep(sleepMode)) + { + trxSleepStatus = true; + } + wakeup the transceiver + if (PHY_SUCCESS == PHY_TrxWakeup()) + { + trxSleepStatus = false; + } + + + Remarks: + When TRX is put into DeepSleep, the TRX registers are reset and it will hold + default values, PIB values are getting written by PHY layer when Wakeup + function is called.User has to reconfigure the configuration parameters + (PHY_ConfigParam_t) which are set by application. This procedure is not + needed for SLEEP mode as the TRX register values are retained. +*/ +PHY_Retval_t PHY_TrxWakeup(void); + +/* + * \brief Generates a 16-bit random number used as initial seed for srand() + * + * This function generates a 16-bit random number by means of using the + * Random Number Generator from the transceiver. + * The Random Number Generator generates 2-bit random values. These 2-bit + * random values are concatenated to the required 16-bit random seed. + * + * The generated random 16-bit number is feed into function srand() + * as initial seed. + * + * The transceiver state is initally set to RX_ON. + * After the completion of the random seed generation, the + * trancseiver is set to TRX_OFF. + * + * As a prerequisite the preamble detector must not be disabled. + * + * Also in case the function is called from a different state than TRX_OFF, + * additional trx state handling is required, such as reading the original + * value and restoring this state after finishing the sequence. + * Since in our case the function is called from TRX_OFF, this is not required + * here. + */ + + void tal_generate_rand_seed(void); + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY TRX Feature Access Functions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + uint8_t PHY_EdSample(void) + + Summary: + Perform a single ED measurement on current channel + + Description: + This function is used to measure the energy level on current channel + + Precondition: + PHY_Init() should have been called before calling this function. + + Parameters: + None + + Returns: + edValue - Result of the measurement + + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + uint8_t phyChannel = 15; + uint8_t edLevel; + int8_t pwrDbm; + PibValue_t pibValue; + + Setting Current channel + pibValue.pib_value_8bit = phyChannel; + retVal = PHY_PibSet(phyCurrentChannel, &pibValue); + if(PHY_SUCCESS == retVal) + { + Take the Ed sample + edLevel = PHY_EdSample(); + Convert the energy level to input power in Dbm + pwrDbm = (int8_t)(edLevel + PHY_GetRSSIBaseVal()); + } + + + + Remarks: + PHY_EdSample scans the channel for 8 symbols(128us) and returns the energy level +*/ +uint8_t PHY_EdSample(void); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_CCAPerform(void) + + Summary: + Perform a clear channel assessment + + Description: + This function is used to perform a clear channel assessment on current channel. + using configured CCA mode (can be set using PHY_PibSet of phyCCAMode). + This results in the status of channel is current busy or Idle. + + The different CCA modes supported by Transceiver are + The CCA mode + - CCA Mode 1: Energy above threshold. CCA shall report a busy medium + upon detecting any energy above the ED threshold. + - CCA Mode 2: Carrier sense only. CCA shall report a busy medium only upon + the detection of a signal with the modulation and spreading characteristics + of IEEE 802.15.4. This signal may be above or below the ED threshold. + - CCA Mode 3: Carrier sense with energy above threshold. CCA shall report a + busy medium only upon the detection of a signal with the modulation and + spreading characteristics of IEEE 802.15.4 with energy above the ED + threshold. + + Precondition: + PHY_Init() should have been called before calling this function. + + Parameters: + None + + Returns: + PHY_Retval_t - PHY_CHANNEL_IDLE or PHY_CHANNEL_BUSY + PHY_CHANNEL_IDLE - The CCA attempt has detected an idle channel + PHY_CHANNEL_BUSY - The CCA attempt has detected a busy channel + + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + uint8_t phyChannel = 15; + PibValue_t pibValue; + bool isChIdle = false; + + Setting Current channel + pibValue.pib_value_8bit = phyChannel; + retVal = PHY_PibSet(phyCurrentChannel, &pibValue); + if(PHY_SUCCESS == retVal) + { + Take the Ed sample + retVal = PHY_CCAPerform(); + if (PHY_CHANNEL_IDLE == retVal) + { + isChIdle = true; + } + } + + + + Remarks: + None +*/ +PHY_Retval_t PHY_CCAPerform(void); + + + +// ***************************************************************************** +/** + * @brief Initializes the TFA + * + * This function is called to initialize the TFA. + * + * @return MAC_SUCCESS if everything went correct; + * FAILURE otherwise + * + * @ingroup apiTfaApi + */ +PHY_Retval_t tfa_init(void); + +/** + * @brief Reset the TFA + * + * This function is called to reset the TFA. + * + * @param set_default_pib Defines whether PIB values need to be set + * to its default values + * + * @ingroup apiTfaApi + */ +void tfa_reset(bool set_default_pib); + +/** + * @brief Gets a TFA PIB attribute + * + * This function is called to retrieve the transceiver information base + * attributes. + * + * @param[in] tfa_pib_attribute TAL infobase attribute ID + * @param[out] value TFA infobase attribute value + * + * @return MAC_UNSUPPORTED_ATTRIBUTE if the TFA infobase attribute is not found + * MAC_SUCCESS otherwise + * + * @ingroup apiTfaApi + */ +PHY_Retval_t tfa_pib_get(PHY_tfa_pib_t tfa_pib_attribute, void *value); + +/** + * @brief Sets a TFA PIB attribute + * + * This function is called to set the transceiver information base + * attributes. + * + * @param[in] tfa_pib_attribute TFA infobase attribute ID + * @param[in] value TFA infobase attribute value to be set + * + * @return MAC_UNSUPPORTED_ATTRIBUTE if the TFA info base attribute is not found + * TAL_BUSY if the TAL is not in TAL_IDLE state. + * MAC_SUCCESS if the attempt to set the PIB attribute was successful + * + * @ingroup apiTfaApi + */ +PHY_Retval_t tfa_pib_set(PHY_tfa_pib_t tfa_pib_attribute, void *value); + +/* + Function: + void PHY_StartContinuousTransmit(PHY_ContinuousTxMode_t txMode, + bool randomContent) + + Summary: + Starts continuous transmission on current channel + + Description: + This function is called to start the continuous transmission on current + channel. + + Precondition: + PHY_Init() should have been called before calling this function. + + Parameters: + txMode - Mode of continuous transmission + CW_MODE - Continuous Wave mode to transmit + the signal at Fc +&- 0.5MHz frequency + PRBS_MODE - PRBS mode to Pseudorandom Binary Sequence frame + continuously + randomContent - Use random content if true + + Returns: + None + + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + uint8_t phyChannel = 15; + PHY_ContinuousTxMode_t txMode = CW_MODE; + bool useRandomContent = false; + PibValue_t pibValue; + + Setting Current channel + pibValue.pib_value_8bit = phyChannel; + retVal = PHY_PibSet(phyCurrentChannel, &pibValue); + if(PHY_SUCCESS == retVal) + { + Start continuous tx in CW mode + PHY_StartContinuousTransmit(txMode, useRandomContent); + } + + + + Remarks: + None +*/ +void PHY_StartContinuousTransmit(PHY_ContinuousTxMode_t txMode, + bool randomContent); +// ***************************************************************************** +/* + Function: + void PHY_StopContinuousTransmit(void) + + Summary: + Stops the continuous transmission on the current channel + + Description: + This function is called to stop the continuous transmission + + Precondition: + PHY_Init() should have been called before calling this function. + This function will stop the continuous transmission which is started by + PHY_StartContinuousTransmit()function. + + Parameters: + None + + Returns: + None + + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + uint8_t phyChannel = 15; + PHY_ContinuousTxMode_t txMode = PRBS_MODE; + bool useRandomContent = true; + bool contTxStarted = false; + PibValue_t pibValue; + + Setting Current channel + pibValue.pib_value_8bit = phyChannel; + retVal = PHY_PibSet(phyCurrentChannel, &pibValue); + if(PHY_SUCCESS == retVal) + { + Start continuous tx in CW mode + PHY_StartContinuousTransmit(txMode, useRandomContent); + contTxStarted = true; + } + + if(contTxStarted) + { + Stop continuous tx + PHY_StopContinuousTransmit(); + } + + + Remarks: + When continuous tx is stopped, the PHY_Reset function is called. + User has to reconfigure the configuration parameters + (PHY_ConfigParam_t) which are set by application. +*/ +void PHY_StopContinuousTransmit(void); + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY TRX Configuration Functions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_ConfigAntennaDiversity(bool divCtrl, uint8_t antCtrl) + + Summary: + Configures antenna diversity and selects antenna + + Description: + This function is used to enable the Antenna Diversity feature and + to select the antenna path if the feature is disabled. + Antenna Diversity uses two antennas to select the most reliable RF signal path. + To ensure highly independent receive signals on both antennas, + the antennas should be carefully separated from each other. + If a valid IEEE 802.15.4 frame is detected on one antenna, this antenna is + selected for reception. Otherwise the search is continued on the other antenna + and vice versa. + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + divCtrl - true/false to enable/disable antenna diversity algorithm + antCtrl - 0 or 3 when antenna diversity is enabled + 1 or 2 to select antenna 1 or antenna 2 + + Returns: + PHY_SUCCESS - If Antenna Diversity/ Control bits are configured correctly + PHY_FAILURE - otherwise + + Example: + + bool antDiv = ANTENNA_DIVERSITY_DISABLE; + uint8_t antennaSel = ANTENNA_CTRL_1; + + Antenna Diversity is disabled and Antenna 1 is selected for rx/tx path + PHY_ConfigAntennaDiversity(antDiv, antennaSel); + + To get the antenna diversity value configured in the TRX + PHY_GetTrxConfig(ANT_DIV, &antDiv); + To get antenna selected for rx/tx + PHY_GetTrxConfig(ANT_SELECT, &antennaSel); + + + Remarks: + None +*/ +PHY_Retval_t PHY_ConfigAntennaDiversity(bool divCtrl, uint8_t antCtrl); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_ConfigRxSensitivity(uint8_t pdtLevel) + + Summary: + Configures receiver sensitivity level. This is used to desensitize + the receiver + + Description: + This function is used to reduce the sensitivity of the receiver. + The input pdtLevel(Power Detect Level) desensitize the receiver such that + frames with an RSSI level below the pdtLevel threshold level (if pdtLevel > 0) + are not received. For a pdtLevel > 0 value the threshold level can be + calculated according to the following formula: + PRF[dBm] > RSSIBASE_VAL[dBm] + 3[dB] x (pdtLevel - 1) + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + pdtLevel - 0 to 15 levels of rx sensitivity(RX_PDT_LEVEL) + + + Returns: + PHY_SUCCESS - If pdtLevel bits are configured correctly + PHY_FAILURE - otherwise + + Example: + + uint8_t pdtLevel = 0x03; + + Reduce the PDT level + PHY_ConfigRxSensitivity(pdtLevel); + + To get the PDT level configured + PHY_GetTrxConfig(RX_SENS, &pdtLevel); + + + + Remarks: + None +*/ +PHY_Retval_t PHY_ConfigRxSensitivity(uint8_t pdtLevel); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_ConfigRxPromiscuousMode(bool promCtrl) + + Summary: + Configures RX promiscuous mode + + Description: + This function is used to enable the RX promiscuous mode. The TRX will receive + all frames even with FCS failure, PHY layer will discard the CRC invalid packet + and TRX will not acknowledge even ack is requested by the received + packet(auto ack is disabled in this mode). + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + promCtrl - true - To enable promiscuous mode + false - To disable promiscuous mode + + Returns: + PHY_SUCCESS - If promCtrl bits are configured correctly + PHY_FAILURE - otherwise + + Example: + + bool promCtrl = true; + + Enable Promiscuous mode + PHY_ConfigRxPromiscuousMode(promCtrl); + + To get the PDT level configured + PHY_GetTrxConfig(AACK_PROMSCS_MODE, &promCtrl); + + + + Remarks: + None +*/ +PHY_Retval_t PHY_ConfigRxPromiscuousMode(bool promCtrl); + + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_ConfigAutoAck(bool enableAACK) + + Summary: + Configures TRX for auto acknowledging the reserved frame + + Description: + The function is used to configure the automatic acknowledgment from + Transceiver after packet reception. + + Precondition: + PHY_Init() should have been called before calling this function. + + Parameters: + nableAACK - true - to enable the automatic + acknowledgment after reception + false - to disable the automatic + acknowledgment after reception + + + Returns: + PHY_Retval_t - PHY_SUCCESS If trx is configured correctly + * PHY_FAILURE otherwise + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + bool isEnableAACK = true; + + retVal = PHY_ConfigAutoAck(isEnableAACK); + if(PHY_SUCCESS == retVal) + { + Trx is configured to auto acknowledge for the received packet + } + + + Remarks: + None +*/ +PHY_Retval_t PHY_ConfigAutoAck(bool enableAACK); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_ConfigReservedFrameFiltering(bool recReservedFrame, + bool bypassFrameFilter ) + + Summary: + Configures TRX for receiving reserved frame + + Description: + This function is used to configure the trx for receiving the reserved frame + type frames and to enable/disable the frame filtering . + + Precondition: + PHY_Init() should have been called before calling this function. + + Parameters: + recReservedFrame - true to enable the reception of reserved frame types + acknowledgment after reception + bypassFrameFilter - true to bypass the frame filtering at the hardware + level like data frame as specified in IEEE specification + + Returns: + PHY_Retval_t - PHY_SUCCESS If trx is configured correctly + * PHY_FAILURE otherwise + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + bool rxResFrame = true; + bool bypassFrameFiltering = false; + + retVal = PHY_ConfigReservedFrameFiltering(rxResFrame, bypassFrameFiltering); + if(PHY_SUCCESS == retVal) + { + Trx is configured to receive the reserved frame and to do the frame + filtering as stated in IEEE Spec + } + + + Remarks: + None +*/ +PHY_Retval_t PHY_ConfigReservedFrameFiltering(bool recReservedFrame, + bool bypassFrameFilter ); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_GetTrxConfig(PHY_ConfigParam_t parameter, uint8_t *paramValue) + + Summary: + To read a current setting of particular transceiver parameter + + Description: + The function is used to read the current of particular parameter. + The following parameters can be read from TRX, + Antenna Diversity + ANT_DIVERSITY + Antenna Configured - ANTENNA_1/ANTENNA_2 + ANT_SELECT + Antenna Control + ANT_CTRL + Promiscuous Mode + AACK_PROMSCS_MODE + Tx Power Configured + TX_PWR + Rx Sensitivity + RX_SENS + RX Reduced Power Consumption + RX_RPC + Automatic acknowledgement + RX_AUTO_ACK + Reserved frame reception + RX_RESERVED_FRAME + Filter reserved frame + FILTER_RESERVED_FRAME + + Precondition: + PHY_Init() should have been called before calling this function. + + Parameters: + parameter - Type of the parameter to be read + paramValue - Pointer to the current parameter value + + Returns: + PHY_Retval_t - PHY_INVALID_PARAMETER If the parameter is invalid + - PHY_SUCCESS otherwise + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + bool promCtrl = true; + + To get the promiscuous mode configured + PHY_GetTrxConfig(AACK_PROMSCS_MODE, (uint8_t *)&promCtrl); + + + Remarks: + None +*/ +PHY_Retval_t PHY_GetTrxConfig(PHY_ConfigParam_t parameter, uint8_t *paramValue); + + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY Utility Functions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + PHY_TrxStatus_t PHY_GetTrxStatus(void) + + Summary: + Returns the current status of the Transceiver + + Description: + This function gets the status of the transceiver + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + None + + Returns: + PHY_TRX_OFF - The transceiver is in TRX_OFF state + PHY_RX_ON - The transceiver is in receive state + PHY_TX_ON - The transceiver is in Transmit state + PHY_BUSY_RX - The transceiver currently receiving the packet + PHY_BUSY_TX - The transceiver is currently transmitting the packet + PHY_TRX_SLEEP - The transceiver is in sleep state + PHY_DEEP_SLEEP - The transceiver is in Deep sleep state + + Example: + + PHY_TrxStatus_t trxStatus; + Gets the current status of trx + trxStatus = PHY_GetTrxStatus(); + + + + Remarks: + None . +*/ +PHY_TrxStatus_t PHY_GetTrxStatus(void); + +// ***************************************************************************** +/* + Function: + int8_t PHY_GetRSSIBaseVal(void) + + Summary: + Get RSSI base value of TRX + + Description: + This function is called to get the base RSSI value for respective + radios + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + None + + Returns: + 32-bit PHY SW version value + + Example: + + int8_t trxBaseRSSI; + + Get RSSI base value of TRX + trxBaseRSSI = PHY_GetRSSIBaseVal(); + + + + Remarks: + None +*/ +int8_t PHY_GetRSSIBaseVal(void); + +// ***************************************************************************** +/* + Function: + uint32_t PHY_GetSWVersion(void) + + Summary: + To Get the current Software version of PHY + + Description: + This function is used Get the current Software version of PHY + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + None + + Returns: + 32-bit PHY SW version value + + Example: + + uint32_t phySwVersion; + + Get sw version of the PHY + phySwVersion = PHY_GetSWVersion(); + + + + Remarks: + None +*/ +uint32_t PHY_GetSWVersion(void); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_ConvertTxPwrRegValToDbm(uint8_t regValue, int8_t *dbmValue) + + Summary: + To convert the Tx Power Register index value to dbm Value + + Description: + This function is used to convert Tx Power Register index value to dbm Value + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + regVaue - Index of the Power register value (Range 0-15) + dbmValue - Corresponding dbm value to the Pwr register value + + Returns: + PHY_SUCCESS - If reg value can be converted into dBm value + PHY_FAILURE - If regVaue is holding the invalid value + + Example: + + uint8_t pwrRegIndex = 0x04; + int8_t pwrDbm; + + To get the dBm value corresponding to power register index + PHY_ConvertTxPwrRegValToDbm(pwrRegIndex, &pwrDbm); + + + + Remarks: + None +*/ +PHY_Retval_t PHY_ConvertTxPwrRegValToDbm(uint8_t regValue, int8_t *dbmValue); + +/** + * @brief Conversion of symbols to microseconds + */ +uint32_t tal_convert_symbols_to_us_def(uint32_t symbols); + +/** + * @brief Conversion of microseconds to symbols + */ +uint32_t tal_convert_us_to_symbols_def(uint32_t time_); + + + +#define ANT_CTRL_0 (0U) +#define ANT_CTRL_1 (1U) +#define ANT_CTRL_2 (2U) +#define ANT_CTRL_3 (3U) + +// #define ANT_EXTERNAL_SW_ENABLE (1) +// #define ANT_EXTERNAL_SW_DISABLE (0) +// #define ANT_AUTO_SEL (0) + +#define MAX_PDT_LEVEL (0x0FU) + +#define REGISTER_VALUE (0x01U) +#define DBM_VALUE (0x00) + +#define AACK_PROM_ENABLE (0x01U) +#define AACK_PROM_DISABLE (0x00U) + + +#define CC_1_START_FREQUENCY (769.0f) +#define CC_1_END_FREQUENCY (794.5f) +#define CC_2_START_FREQUENCY (857.0f) +#define CC_2_END_FREQUENCY (882.5f) +#define CC_3_START_FREQUENCY (903.0f) +#define CC_3_END_FREQUENCY (928.5f) +#define CC_4_START_FREQUENCY (769.0f) +#define CC_4_END_FREQUENCY (863.0f) +#define CC_5_START_FREQUENCY (833.0f) +#define CC_5_END_FREQUENCY (935.0f) +#define CC_6_START_FREQUENCY (902.0f) +#define CC_6_END_FREQUENCY (927.5f) + +#define CC_BAND_0 (0x00U) +#define CC_BAND_1 (0x01U) +#define CC_BAND_2 (0x02U) +#define CC_BAND_3 (0x03U) +#define CC_BAND_4 (0x04U) +#define CC_BAND_5 (0x05U) +#define CC_BAND_6 (0x06U) + +#define MIN_CC_BAND_4_OFFSET (0x5EU) +#define MIN_CC_BAND_5_OFFSET (0x66U) + +#define MAX_CC_BAND (0x06U) + + + + + +//DOM-IGNORE-BEGIN +#ifdef __cplusplus +} +#endif +//DOM-IGNORE-END + +#endif /* PHY_H */ +/* EOF */ diff --git a/driver/software/RF212b/phy/inc/phy_config.h b/driver/software/RF212b/phy/inc/phy_config.h new file mode 100644 index 0000000..cea898d --- /dev/null +++ b/driver/software/RF212b/phy/inc/phy_config.h @@ -0,0 +1,62 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* Prevent double inclusion */ +#ifndef PHY_CONFIG_H +#define PHY_CONFIG_H + +// **************************************************************************** +// **************************************************************************** +// Section: Macros +// **************************************************************************** +// **************************************************************************** + +// **************************************************************************** +#define PHY_RADIO_WAKEUP_TIME_SYM (PHY_CONVERT_US_TO_SYMBOLS( \ + SLEEP_TO_TRX_OFF_TYP_US)) + + + +#ifdef ENABLE_FTN_PLL_CALIBRATION + +/* + * PLL calibration and filter tuning timer timeout in minutes + */ +#define TAL_CALIBRATION_TIMEOUT_MIN (5UL) + +/* + * PLL calibration and filter tuning timer timeout in us, + */ +#define TAL_CALIBRATION_TIMEOUT_US ((TAL_CALIBRATION_TIMEOUT_MIN) * \ + (60UL) * (1000UL) * (1000UL)) +#endif /* ENABLE_FTN_PLL_CALIBRATION */ + +/* === TYPES =============================================================== */ +#ifdef ENABLE_QUEUE_CAPACITY +#define TAL_INCOMING_FRAME_QUEUE_CAPACITY (255) +#endif /* ENABLE_QUEUE_CAPACITY */ + + +#endif diff --git a/driver/software/RF212b/phy/inc/phy_constants.h b/driver/software/RF212b/phy/inc/phy_constants.h new file mode 100644 index 0000000..7379803 --- /dev/null +++ b/driver/software/RF212b/phy/inc/phy_constants.h @@ -0,0 +1,242 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +#ifndef PHY_CONSTANTS_H +#define PHY_CONSTANTS_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Macros +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Minimum channel + + Summary: + This macro defines the Minimum channel number of Transciver + Description: + None + Remarks: + None + */ + +#define MIN_CHANNEL (0U) + +// ***************************************************************************** +/* Maximum channel + + Summary: + This macro defines the Maximum channel number of Transciver + Description: + None + Remarks: + None + */ +#define MAX_CHANNEL (10U) + +// ***************************************************************************** +/* Valid Channel Mask + + Summary: + This macro defines the Valid Channel Mask used for ED Scanning + Description: + None + Remarks: + None + */ +#define VALID_CHANNEL_MASK (0x000007FFUL) + +// ***************************************************************************** +/* Symbols per Octet + + Summary: + This macro defines the number of symbols per octet + Description: + Depending on the channel page either + 1 bit forms one symbol (BPSK in channel page 0) or + 4 bit form one symbol (O-QPSK in channel page 2). + Remarks: + None + */ + +#define SYMBOLS_PER_OCTET (tal_pib.CurrentPage == 0 ? 8 : 2) + +// ***************************************************************************** +/* No of Symbols included in the preamble + + Summary: + This macro defines the number of symbols includes in the preamble + Description: + None + Remarks: + None + */ + +#define NO_SYMBOLS_PREAMBLE (tal_pib.CurrentPage == 0 ? 32U : 8U) + +// ***************************************************************************** +/* Number of symbols included in the SFD field + + Summary: + This macro defines the number of symbols includes in SFD Field + Description: + None + Remarks: + None + */ + +#define NO_SYMBOLS_SFD (tal_pib.CurrentPage == 0 ? 8U : 2U) + +// ***************************************************************************** +/* Number of symbols forming the synchronization header (SHR) for the current + PHY. + + Summary: + This macro defines the number of symbols forming the synchronization header + (SHR) for the current PHY. This value is the base for the PHY PIB attribute + phySHRDuration. + Description: + None + Remarks: + None + */ + +#define NO_OF_SYMBOLS_PREAMBLE_SFD (NO_SYMBOLS_PREAMBLE + \ + NO_SYMBOLS_SFD) + +// ***************************************************************************** +/* Maximum number of symbols in a frame for the current PHY. + + Summary: + This macro defines the Maximum number of symbols in a frame for the current PHY + This value is the base for the PHY PIB attribute phyMaxFrameDuration. + Description: + None + Remarks: + None + */ + +#define MAX_FRAME_DURATION \ + (NO_OF_SYMBOLS_PREAMBLE_SFD + \ + (aMaxPHYPacketSize + 1U) * SYMBOLS_PER_OCTET) + +// ***************************************************************************** +/* Maximum Symbol Time + + Summary: + The maximum time in symbols for a 32 bit timer + Description: + None + Remarks: + None + */ + +#define MAX_SYMBOL_TIME (0x0FFFFFFF) + +// ***************************************************************************** +/* Symbol Mask + + Summary: + Symbol mask for ignoring most significant nibble + Description: + None + Remarks: + None + */ + +#define SYMBOL_MASK (0x0FFFFFFF) + +// ***************************************************************************** + + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Constants +// ***************************************************************************** +// ***************************************************************************** + + + + + + + + +// ***************************************************************************** +/* PWR_REGISTER_VALUE + + Summary: + Macro for selecting power configuration mode as Register set + Remarks: + None + */ +#define PWR_REGISTER_VALUE (1) + +// ***************************************************************************** +/* PWR_DBM_VALUE + + Summary: + Macro for selecting power configuration mode as Dbm set + Remarks: + None + */ +#define PWR_DBM_VALUE (0) + +// ***************************************************************************** +/* PROMISCUOUS_ENABLE + + Summary: + Macro for enabling promiscuous mode + Remarks: + None + */ +#define PROMISCUOUS_ENABLE (1) + +// ***************************************************************************** +/* PROMISCUOUS_DISABLE + + Summary: + Macro for disabling promiscuous mode + Remarks: + None + */ +#define PROMISCUOUS_DISABLE (0) + +// ***************************************************************************** +/* NUMBER_OF_TOTAL_PHY_TIMERS + + Summary: + Total numbers of software timer instance used by PHY Layer + Remarks: + None + */ +#define NUMBER_OF_TOTAL_PHY_TIMERS (1) + +#endif /* PHY_CONSTANTS_H */ + +/* EOF */ diff --git a/driver/software/RF212b/phy/inc/phy_tasks.h b/driver/software/RF212b/phy/inc/phy_tasks.h new file mode 100644 index 0000000..11b1870 --- /dev/null +++ b/driver/software/RF212b/phy/inc/phy_tasks.h @@ -0,0 +1,197 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* Prevent double inclusion */ +#ifndef PHY_TASKS_H +#define PHY_TASKS_H + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Prototypes +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + void PHY_Tasks(void) + + Summary: + RTOS task for the PHY Layer + + Description: + This function inturn calls the PHY layer task handler upon reception of + Semaphore signal + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + None + + Returns: + None + + Example: + + xTaskCreate((TaskFunction_t) _PHY_Tasks, + "PHY_Tasks", + 1024, + NULL, + 1, + &xPHY_Tasks); + + Handle for the PHY_Tasks. + TaskHandle_t xPHY_Tasks; + + void _PHY_Tasks( void *pvParameters ) + { + while(1) + { + PHY_Tasks(); + } + } + + + + Remarks: + None +*/ + +void PHY_Tasks(void); + +// ***************************************************************************** +/* + Function: + void TAL_Tasks(void) + + Summary: + RTOS task for the TAL Layer + + Description: + This function inturn calls the TAL layer task handler upon reception of + Semaphore signal + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + None + + Returns: + None + + Example: + + xTaskCreate((TaskFunction_t) _TAL_Tasks, + "TAL_Tasks", + 1024, + NULL, + 1, + &xTAL_Tasks); + + Handle for the TAL_Tasks. + TaskHandle_t xTAL_Tasks; + + void _TAL_Tasks( void *pvParameters ) + { + while(1) + { + TAL_Tasks(); + } + } + + + + Remarks: + None +*/ + +void TAL_Tasks(void); + + +// ***************************************************************************** +/* + Function: + void PHY_PostTask(bool isISRContext) + + Summary: + This function is used to invoke the PHY RTOS task + + Description: + This function is used to invoke the PHY RTOS task. This will be used + by the PHY layer for signaling the task done status + + Precondition: + This function gets called from the PHY Library. + + Parameters: + isISRContext true - Task is called from the ISR context false - otherwise + + Returns: + None + + Example: + None + + Remarks: + None +*/ + +void PHY_PostTask(bool isISRContext); + +// ***************************************************************************** +/* + Function: + void TAL_PostTask(bool isISRContext) + + Summary: + This function is used to invoke the TAL RTOS task + + Description: + This function is used to invoke the TAL RTOS task. This will be used + by the TAL layer to handle the transceiver interrupt + + + Parameters: + isISRContext true - Task is called from the ISR context false - otherwise + + Returns: + None + + Example: + None + + Remarks: + None +*/ + +void TAL_PostTask(bool isISRContext); + + +#endif /* PHY_TASKS_H */ + +/* EOF */ diff --git a/driver/software/RF212b/phy/src/phy_ed_end_cb.c b/driver/software/RF212b/phy/src/phy_ed_end_cb.c new file mode 100644 index 0000000..1e796cb --- /dev/null +++ b/driver/software/RF212b/phy/src/phy_ed_end_cb.c @@ -0,0 +1,66 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Included Files */ +/* ************************************************************************** */ +/* ************************************************************************** */ +#include +#include +#include "../../phy/inc/phy.h" + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Macros */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Globals */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Prototypes */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Functions */ +/* ************************************************************************** */ +/* ************************************************************************** */ +__attribute__((weak)) void PHY_EdEndCallback(uint8_t energyLevel) +{ + energyLevel = energyLevel; /* Keep compiler happy. */ +} + +/* EOF */ diff --git a/driver/software/RF212b/phy/src/phy_rx_frame_cb.c b/driver/software/RF212b/phy/src/phy_rx_frame_cb.c new file mode 100644 index 0000000..3e88d3b --- /dev/null +++ b/driver/software/RF212b/phy/src/phy_rx_frame_cb.c @@ -0,0 +1,68 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Included Files */ +/* ************************************************************************** */ +/* ************************************************************************** */ +#include +#include +#include "../../phy/inc/phy.h" + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Macros */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Globals */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Prototypes */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Functions */ +/* ************************************************************************** */ +/* ************************************************************************** */ + +__attribute__((weak)) void PHY_RxFrameCallback(PHY_FrameInfo_t *rxFrame) +{ + /* Keep compiler happy. */ + rxFrame = rxFrame; +} + +/* EOF */ diff --git a/driver/software/RF212b/phy/src/phy_task.c b/driver/software/RF212b/phy/src/phy_task.c new file mode 100644 index 0000000..2b31568 --- /dev/null +++ b/driver/software/RF212b/phy/src/phy_task.c @@ -0,0 +1,111 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Included Files */ +/* ************************************************************************** */ +/* ************************************************************************** */ + +/* This section lists the other files that are included in this file. + */ +#include "../../phy/inc/phy.h" +#include "definitions.h" + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Externals */ +/* ************************************************************************** */ +/* ************************************************************************** */ + +extern OSAL_SEM_HANDLE_TYPE semPhyInternalHandler; +extern OSAL_SEM_HANDLE_TYPE semTalInternalHandler; + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Prototypes */ +/* ************************************************************************** */ +/* ************************************************************************** */ +void PHY_Tasks(void) +{ + if (semPhyInternalHandler != NULL) + { + OSAL_SEM_Pend(&semPhyInternalHandler, OSAL_WAIT_FOREVER); + PHY_TaskHandler(); + } +} +/* ************************************************************************** */ +void TAL_Tasks(void) +{ + if (semTalInternalHandler != NULL) + { + OSAL_SEM_Pend(&semTalInternalHandler, OSAL_WAIT_FOREVER); + TAL_TaskHandler(); + } +} + +/* ************************************************************************** */ +void PHY_PostTask(bool isISRContext) +{ + if(semPhyInternalHandler != NULL) + { + if(isISRContext) + { + OSAL_SEM_PostISR(&semPhyInternalHandler); + } + else + { + OSAL_SEM_Post(&semPhyInternalHandler); + } + } + else + { + PHY_TaskHandler(); + } +} + +/* ************************************************************************** */ +void TAL_PostTask(bool isISRContext) +{ + if(semTalInternalHandler != NULL) + { + if(isISRContext) + { + OSAL_SEM_PostISR(&semTalInternalHandler); + } + else + { + OSAL_SEM_Post(&semTalInternalHandler); + } + } + else + { + TAL_TaskHandler(); + } +} + +/* ***************************************************************************** + End of File + */ diff --git a/driver/software/RF212b/phy/src/phy_tx_frame_done_cb.c b/driver/software/RF212b/phy/src/phy_tx_frame_done_cb.c new file mode 100644 index 0000000..7282abd --- /dev/null +++ b/driver/software/RF212b/phy/src/phy_tx_frame_done_cb.c @@ -0,0 +1,68 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Included Files */ +/* ************************************************************************** */ +/* ************************************************************************** */ +#include +#include +#include "../../phy/inc/phy.h" + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Macros */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Globals */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Prototypes */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Functions */ +/* ************************************************************************** */ +/* ************************************************************************** */ +__attribute__((weak)) void PHY_TxDoneCallback(PHY_Retval_t status, PHY_FrameInfo_t *frame) +{ + /* Keep compiler happy. */ + status = status; + frame = frame; +} + +/* EOF */ diff --git a/driver/software/RF233/phy/at86rf233/inc/AT86RF233.h b/driver/software/RF233/phy/at86rf233/inc/AT86RF233.h new file mode 100644 index 0000000..deb006a --- /dev/null +++ b/driver/software/RF233/phy/at86rf233/inc/AT86RF233.h @@ -0,0 +1,1241 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* Prevent double inclusion */ +#ifndef AT86RF233_H +#define AT86RF233_H + +/* === INCLUDES ============================================================ */ + +#define TRANSCEIVER_NAME "AT86RF233" +/* === EXTERNALS =========================================================== */ + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/** Parameter definitions */ + +/** Important parameters. */ +/* TRX Parameter: Bit mask of transceiver supported channel */ +#define TRX_SUPPORTED_CHANNELS (0x07FFF800) + +/* TRX Parameter: Tolerance of the phyTransmitPower PIB attribute. + * This is encoded into the two MSBits of the attribute, + * and is effectively read-only. + */ +#define TX_PWR_TOLERANCE (0x80U) + +/** Typical timing values. */ +/* TRX Parameter: t10 */ +#define RST_PULSE_WIDTH_NS (625U) +/* TRX Parameter: tTR1 typical value */ +#define P_ON_TO_CLKM_AVAILABLE_TYP_US (330U) +/* TRX Parameter: tTR1 max. value */ +#define P_ON_TO_CLKM_AVAILABLE_MAX_US (1000U) +/* TRX Parameter: tTR2 typical value */ +#define SLEEP_TO_TRX_OFF_TYP_US (210U) +/* TRX Parameter: tTR2 max. value */ +#define SLEEP_TO_TRX_OFF_MAX_US (1000U) +/* TRX Parameter: tTR3 */ +#define TRX_OFF_TO_SLEEP_TIME_CLKM_CYCLES (35U) +/* TRX Parameter: tTR4 */ +#define TRX_OFF_TO_PLL_ON_TIME_US (80U) +/* TRX Parameter: tPLL_INIT max value */ +#define PLL_LOCK_DURATION_MAX_US (250U) +/* TRX Parameter: tTR15 typical value */ +#define PON_TO_TRXOFF_AFTER_CLKM_TYP_US (360U) +/* TRX Parameter: tTR15 max. value */ +#define PON_TO_TRXOFF_AFTER_CLKM_MAX_US (1000U) +/* TRX Parameter: tIRQ */ +#define TRX_IRQ_DELAY_US (9U) +/* TRX Parameter: RSSIBASE_VAL */ +#define RSSI_BASE_VAL_DBM (-91) +/* TRX Parameter: tCCA */ +#define CCA_DETECTION_TIME_US (135U) +/* TRX Parameter: Duration of an octet for 250kb/s OQPSK mode */ +#define T_OCT_US (32U) +/* TRX Parameter: Duration of an symbol for 250kb/s OQPSK mode */ +#define T_SYM_US (16U) +/* TRX Parameter: 16 us processing delay + 16 us software handling duration */ +#define PRE_TX_DURATION_US (32U) +/* TRX Parameter: Duration before start of CCA */ +#define CCA_PRE_START_DURATION_US (20U) +/* TRX Parameter: CCA processing time in symbols */ +#define CCA_PROCESS_TIME_SYM (1U) +/* TRX Parameter: Preparation time for CCA */ +#define CCA_PREPARATION_DURATION_US (50U) +/* TRX Parameter: Complete CCA Duration in symbols */ +#define CCA_DURATION_SYM (PHY_CONVERT_US_TO_SYMBOLS(CCA_DETECTION_TIME_US) + \ + CCA_PROCESS_TIME_SYM) +/* TRX Parameter: Round up RST_PULSE_WIDTH_NS value to us */ + +/*delay_us() for time less than 5 seems to provide wrong delay in GCC , + * hence proper reset is not done.TO be reverted back once the related bug is + * fixed */ +#define RST_PULSE_WIDTH_US (10U) /* ((RST_PULSE_WIDTH_NS + 999) / 1000) */ + +/** Register addresses */ + +/** Base address for Transceiver register address space **/ +#define REG_BASE_ADDR (0x00U) + +/** Base address for Transceiver AES address space **/ +#define AES_BASE_ADDR (0x80U) + +/** Base address and size for RX frame appendix **/ +#define RXAPPENDIX_BASE_ADDR (0x00U) +#define RXAPPENDIX_SIZE (3U) + +/** Offset for register AES_CTRL */ +#define RG_AES_CTRL (0x03U) + +/** Offset for register AES_CTRL_MIRROR */ +#define RG_AES_CTRL_MIRROR (0x14U) + +/** Offset for register AES_STATE_KEY_0 */ +#define RG_AES_STATE_KEY_0 (0x04U) + +/** Offset for register AES_STATUS */ +#define RG_AES_STATUS (0x02U) + +/** Offset for register ANT_DIV */ +#define RG_ANT_DIV (0x0DU) + +/** Offset for register BATMON */ +#define RG_BATMON (0x11U) + +/** Offset for register CCA_THRES */ +#define RG_CCA_THRES (0x09U) + +/** Offset for register CC_CTRL_0 */ +#define RG_CC_CTRL_0 (0x13U) + +/** Offset for register CC_CTRL_1 */ +#define RG_CC_CTRL_1 (0x14U) + +/** Offset for register CSMA_BE */ +#define RG_CSMA_BE (0x2FU) + +/** Offset for register CSMA_SEED_0 */ +#define RG_CSMA_SEED_0 (0x2DU) + +/** Offset for register CSMA_SEED_1 */ +#define RG_CSMA_SEED_1 (0x2EU) + +/** Offset for register ED */ +#define RG_ED (0x01U) + +/** Offset for register FTN_CTRL */ +#define RG_FTN_CTRL (0x18U) + +/** Offset for register IEEE_ADDR_0 */ +#define RG_IEEE_ADDR_0 (0x24U) + +/** Offset for register IEEE_ADDR_1 */ +#define RG_IEEE_ADDR_1 (0x25U) + +/** Offset for register IEEE_ADDR_2 */ +#define RG_IEEE_ADDR_2 (0x26U) + +/** Offset for register IEEE_ADDR_3 */ +#define RG_IEEE_ADDR_3 (0x27U) + +/** Offset for register IEEE_ADDR_4 */ +#define RG_IEEE_ADDR_4 (0x28U) + +/** Offset for register IEEE_ADDR_5 */ +#define RG_IEEE_ADDR_5 (0x29U) + +/** Offset for register IEEE_ADDR_6 */ +#define RG_IEEE_ADDR_6 (0x2AU) + +/** Offset for register IEEE_ADDR_7 */ +#define RG_IEEE_ADDR_7 (0x2BU) + +/** Offset for register IRQ_MASK */ +#define RG_IRQ_MASK (0x0EU) + +/** Offset for register IRQ_STATUS */ +#define RG_IRQ_STATUS (0x0FU) + +/** Offset for register LQI */ +#define RG_LQI (0x00U) + +/** Offset for register MAN_ID_0 */ +#define RG_MAN_ID_0 (0x1EU) + +/** Offset for register MAN_ID_1 */ +#define RG_MAN_ID_1 (0x1FU) + +/** Offset for register PAN_ID_0 */ +#define RG_PAN_ID_0 (0x22U) + +/** Offset for register PAN_ID_1 */ +#define RG_PAN_ID_1 (0x23U) + +/** Offset for register PART_NUM */ +#define RG_PART_NUM (0x1CU) + +/** Offset for register PHY_CC_CCA */ +#define RG_PHY_CC_CCA (0x08U) + +/** Offset for register PHY_ED_LEVEL */ +#define RG_PHY_ED_LEVEL (0x07U) + +/** Offset for register PHY_PMU_VALUE */ +#define RG_PHY_PMU_VALUE (0x3BU) + +/** Offset for register PHY_RSSI */ +#define RG_PHY_RSSI (0x06U) + +/** Offset for register PHY_TX_PWR */ +#define RG_PHY_TX_PWR (0x05U) + +/** Offset for register PLL_CF */ +#define RG_PLL_CF (0x1AU) + +/** Offset for register PLL_DCU */ +#define RG_PLL_DCU (0x1BU) + +/** Offset for register RX_CTRL */ +#define RG_RX_CTRL (0x0AU) + +/** Offset for register RX_STATUS */ +#define RG_RX_STATUS (0x02U) + +/** Offset for register RX_SYN */ +#define RG_RX_SYN (0x15U) + +/** Offset for register SFD_VALUE */ +#define RG_SFD_VALUE (0x0BU) + +/** Offset for register SHORT_ADDR_0 */ +#define RG_SHORT_ADDR_0 (0x20U) + +/** Offset for register SHORT_ADDR_1 */ +#define RG_SHORT_ADDR_1 (0x21U) + +/** Offset for register TRX_CTRL_0 */ +#define RG_TRX_CTRL_0 (0x03U) + +/** Offset for register TRX_CTRL_1 */ +#define RG_TRX_CTRL_1 (0x04U) + +/** Offset for register TRX_CTRL_2 */ +#define RG_TRX_CTRL_2 (0x0CU) + +/** Offset for register TRX_PAGE */ +#define RG_TRX_PAGE (0x00U) + +/** Offset for register TRX_RPC */ +#define RG_TRX_RPC (0x16U) + +/** Offset for register TRX_STATE */ +#define RG_TRX_STATE (0x02U) + +/** Offset for register TRX_STATUS */ +#define RG_TRX_STATUS (0x01U) + +/** Offset for register TST_CTRL_DIGI */ +#define RG_TST_CTRL_DIGI (0x36U) + +/** Offset for register VERSION_NUM */ +#define RG_VERSION_NUM (0x1DU) + +/** Offset for register VREG_CTRL */ +#define RG_VREG_CTRL (0x10U) + +/** Offset for register XAH_CTRL_0 */ +#define RG_XAH_CTRL_0 (0x2CU) + +/** Offset for register XAH_CTRL_1 */ +#define RG_XAH_CTRL_1 (0x17U) + +/** Offset for register XAH_CTRL_2 */ +#define RG_XAH_CTRL_2 (0x19U) + +/** Offset for register XOSC_CTRL */ +#define RG_XOSC_CTRL (0x12U) + +/** Sub-register access */ + +/** Access parameters for sub-register AACK_ACK_TIME in register @ref + * RG_XAH_CTRL_1 */ +#define SR_AACK_ACK_TIME 0x17, 0x04, 2 + +/** Access parameters for sub-register AACK_DIS_ACK in register @ref + * RG_CSMA_SEED_1 */ +#define SR_AACK_DIS_ACK 0x2E, 0x10, 4 + +/** Access parameters for sub-register AACK_FLTR_RES_FT in register @ref + * RG_XAH_CTRL_1 */ +#define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5 + +/** Access parameters for sub-register AACK_FVN_MODE in register @ref + * RG_CSMA_SEED_1 */ +#define SR_AACK_FVN_MODE 0x2E, 0xC0, 6 + +/** Access parameters for sub-register AACK_I_AM_COORD in register @ref + * RG_CSMA_SEED_1 */ +#define SR_AACK_I_AM_COORD 0x2E, 0x08, 3 + +/** Access parameters for sub-register AACK_PROM_MODE in register @ref + * RG_XAH_CTRL_1 */ +#define SR_AACK_PROM_MODE 0x17, 0x02, 1 + +/** Access parameters for sub-register AACK_SET_PD in register @ref + * RG_CSMA_SEED_1 */ +#define SR_AACK_SET_PD 0x2E, 0x20, 5 + +/** Access parameters for sub-register AACK_SPC_EN in register @ref + * RG_XAH_CTRL_1 */ +#define SR_AACK_SPC_EN 0x17, 0x01, 0 + +/** Access parameters for sub-register AACK_UPLD_RES_FT in register @ref + * RG_XAH_CTRL_1 */ +#define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4 + +/** Access parameters for sub-register AES_DIR in register @ref RG_AES_CTRL */ +#define SR_AES_DIR 0x03, 0x08, 3 + +/** Access parameters for sub-register AES_DONE in register @ref RG_AES_STATUS +**/ +#define SR_AES_DONE 0x02, 0x01, 0 + +/** Access parameters for sub-register AES_ER in register @ref RG_AES_STATUS */ +#define SR_AES_ER 0x02, 0x80, 7 + +/** Access parameters for sub-register AES_MODE in register @ref RG_AES_CTRL */ +#define SR_AES_MODE 0x03, 0x70, 4 + +/** Access parameters for sub-register AES_REQUEST in register @ref RG_AES_CTRL +**/ +#define SR_AES_REQUEST 0x03, 0x80, 7 + +/** Access parameters for sub-register ANT_CTRL in register @ref RG_ANT_DIV */ +#define SR_ANT_CTRL 0x0D, 0x03, 0 + +/** Access parameters for sub-register ANT_DIV_EN in register @ref RG_ANT_DIV */ +#define SR_ANT_DIV_EN 0x0D, 0x08, 3 + +/** Access parameters for sub-register ANT_EXT_SW_EN in register @ref RG_ANT_DIV +**/ +#define SR_ANT_EXT_SW_EN 0x0D, 0x04, 2 + +/** Access parameters for sub-register ANT_SEL in register @ref RG_ANT_DIV */ +#define SR_ANT_SEL 0x0D, 0x80, 7 + +/** Access parameters for sub-register ARET_CSMA_RETRIES in register @ref + * RG_XAH_CTRL_2 */ +#define SR_ARET_CSMA_RETRIES 0x19, 0x0E, 1 + +/** Access parameters for sub-register ARET_FRAME_RETRIES in register @ref + * RG_XAH_CTRL_2 */ +#define SR_ARET_FRAME_RETRIES 0x19, 0xF0, 4 + +/** Access parameters for sub-register ARET_TX_TS_EN in register @ref + * RG_XAH_CTRL_1 */ +#define SR_ARET_TX_TS_EN 0x17, 0x80, 7 + +/** Access parameters for sub-register AVDD_OK in register @ref RG_VREG_CTRL */ +#define SR_AVDD_OK 0x10, 0x40, 6 + +/** Access parameters for sub-register AVREG_EXT in register @ref RG_VREG_CTRL +**/ +#define SR_AVREG_EXT 0x10, 0x80, 7 + +/** Access parameters for sub-register BATMON_HR in register @ref RG_BATMON */ +#define SR_BATMON_HR 0x11, 0x10, 4 + +/** Access parameters for sub-register BATMON_OK in register @ref RG_BATMON */ +#define SR_BATMON_OK 0x11, 0x20, 5 + +/** Access parameters for sub-register BATMON_VTH in register @ref RG_BATMON */ +#define SR_BATMON_VTH 0x11, 0x0F, 0 + +/** Access parameters for sub-register CCA_DONE in register @ref RG_TRX_STATUS +**/ +#define SR_CCA_DONE 0x01, 0x80, 7 + +/** Access parameters for sub-register CCA_ED_THRES in register @ref + * RG_CCA_THRES */ +#define SR_CCA_ED_THRES 0x09, 0x0F, 0 + +/** Access parameters for sub-register CCA_MODE in register @ref RG_PHY_CC_CCA +**/ +#define SR_CCA_MODE 0x08, 0x60, 5 + +/** Access parameters for sub-register CCA_REQUEST in register @ref + * RG_PHY_CC_CCA */ +#define SR_CCA_REQUEST 0x08, 0x80, 7 + +/** Access parameters for sub-register CCA_STATUS in register @ref RG_TRX_STATUS +**/ +#define SR_CCA_STATUS 0x01, 0x40, 6 + +/** Access parameters for sub-register CC_BAND in register @ref RG_CC_CTRL_1 */ +#define SR_CC_BAND 0x14, 0x0F, 0 + +/** Access parameters for sub-register CC_NUMBER in register @ref RG_CC_CTRL_0 +**/ +#define SR_CC_NUMBER 0x13, 0xFF, 0 + +/** Access parameters for sub-register CHANNEL in register @ref RG_PHY_CC_CCA */ +#define SR_CHANNEL 0x08, 0x1F, 0 + +/** Access parameters for sub-register CLKM_CTRL in register @ref RG_TRX_CTRL_0 +**/ +#define SR_CLKM_CTRL 0x03, 0x07, 0 + +/** Access parameters for sub-register CLKM_SHA_SEL in register @ref + * RG_TRX_CTRL_0 */ +#define SR_CLKM_SHA_SEL 0x03, 0x08, 3 + +/** Access parameters for sub-register CSMA_SEED_0 in register @ref + * RG_CSMA_SEED_0 */ +#define SR_CSMA_SEED_0 0x2D, 0xFF, 0 + +/** Access parameters for sub-register CSMA_SEED_1 in register @ref + * RG_CSMA_SEED_1 */ +#define SR_CSMA_SEED_1 0x2E, 0x07, 0 + +/** Access parameters for sub-register DVDD_OK in register @ref RG_VREG_CTRL */ +#define SR_DVDD_OK 0x10, 0x04, 2 + +/** Access parameters for sub-register DVREG_EXT in register @ref RG_VREG_CTRL +**/ +#define SR_DVREG_EXT 0x10, 0x08, 3 + +/** Access parameters for sub-register ED_APX in register @ref RG_ED */ +#define SR_ED_APX 0x01, 0xFF, 0 + +/** Access parameters for sub-register ED_LEVEL in register @ref RG_PHY_ED_LEVEL +**/ +#define SR_ED_LEVEL 0x07, 0xFF, 0 + +/** Access parameters for sub-register FTN_START in register @ref RG_FTN_CTRL */ +#define SR_FTN_START 0x18, 0x80, 7 + +/** Access parameters for sub-register IEEE_ADDR_0 in register @ref + * RG_IEEE_ADDR_0 */ +#define SR_IEEE_ADDR_0 0x24, 0xFF, 0 + +/** Access parameters for sub-register IEEE_ADDR_1 in register @ref + * RG_IEEE_ADDR_1 */ +#define SR_IEEE_ADDR_1 0x25, 0xFF, 0 + +/** Access parameters for sub-register IEEE_ADDR_2 in register @ref + * RG_IEEE_ADDR_2 */ +#define SR_IEEE_ADDR_2 0x26, 0xFF, 0 + +/** Access parameters for sub-register IEEE_ADDR_3 in register @ref + * RG_IEEE_ADDR_3 */ +#define SR_IEEE_ADDR_3 0x27, 0xFF, 0 + +/** Access parameters for sub-register IEEE_ADDR_4 in register @ref + * RG_IEEE_ADDR_4 */ +#define SR_IEEE_ADDR_4 0x28, 0xFF, 0 + +/** Access parameters for sub-register IEEE_ADDR_5 in register @ref + * RG_IEEE_ADDR_5 */ +#define SR_IEEE_ADDR_5 0x29, 0xFF, 0 + +/** Access parameters for sub-register IEEE_ADDR_6 in register @ref + * RG_IEEE_ADDR_6 */ +#define SR_IEEE_ADDR_6 0x2A, 0xFF, 0 + +/** Access parameters for sub-register IEEE_ADDR_7 in register @ref + * RG_IEEE_ADDR_7 */ +#define SR_IEEE_ADDR_7 0x2B, 0xFF, 0 + +/** Access parameters for sub-register IPAN_RPC_EN in register @ref RG_TRX_RPC +**/ +#define SR_IPAN_RPC_EN 0x16, 0x02, 1 + +/** Access parameters for sub-register IRQ_0_PLL_LOCK in register @ref + * RG_IRQ_STATUS */ +#define SR_IRQ_0_PLL_LOCK 0x0F, 0x01, 0 + +/** Access parameters for sub-register IRQ_1_PLL_UNLOCK in register @ref + * RG_IRQ_STATUS */ +#define SR_IRQ_1_PLL_UNLOCK 0x0F, 0x02, 1 + +/** Access parameters for sub-register IRQ_2_EXT_EN in register @ref + * RG_TRX_CTRL_1 */ +#define SR_IRQ_2_EXT_EN 0x04, 0x40, 6 + +/** Access parameters for sub-register IRQ_2_RX_START in register @ref + * RG_IRQ_STATUS */ +#define SR_IRQ_2_RX_START 0x0F, 0x04, 2 + +/** Access parameters for sub-register IRQ_3_TRX_END in register @ref + * RG_IRQ_STATUS */ +#define SR_IRQ_3_TRX_END 0x0F, 0x08, 3 + +/** Access parameters for sub-register IRQ_4_CCA_ED_DONE in register @ref + * RG_IRQ_STATUS */ +#define SR_IRQ_4_CCA_ED_DONE 0x0F, 0x10, 4 + +/** Access parameters for sub-register IRQ_5_AMI in register @ref RG_IRQ_STATUS +**/ +#define SR_IRQ_5_AMI 0x0F, 0x20, 5 + +/** Access parameters for sub-register IRQ_6_TRX_UR in register @ref + * RG_IRQ_STATUS */ +#define SR_IRQ_6_TRX_UR 0x0F, 0x40, 6 + +/** Access parameters for sub-register IRQ_7_BAT_LOW in register @ref + * RG_IRQ_STATUS */ +#define SR_IRQ_7_BAT_LOW 0x0F, 0x80, 7 + +/** Access parameters for sub-register IRQ_MASK in register @ref RG_IRQ_MASK */ +#define SR_IRQ_MASK 0x0E, 0xFF, 0 + +/** Access parameters for sub-register IRQ_MASK_MODE in register @ref + * RG_TRX_CTRL_1 */ +#define SR_IRQ_MASK_MODE 0x04, 0x02, 1 + +/** Access parameters for sub-register IRQ_POLARITY in register @ref + * RG_TRX_CTRL_1 */ +#define SR_IRQ_POLARITY 0x04, 0x01, 0 + +/** Access parameters for sub-register LQI_APX in register @ref RG_LQI */ +#define SR_LQI_APX 0x00, 0xFF, 0 + +/** Access parameters for sub-register MAN_ID_0 in register @ref RG_MAN_ID_0 */ +#define SR_MAN_ID_0 0x1E, 0xFF, 0 + +/** Access parameters for sub-register MAN_ID_1 in register @ref RG_MAN_ID_1 */ +#define SR_MAN_ID_1 0x1F, 0xFF, 0 + +/** Access parameters for sub-register MAX_BE in register @ref RG_CSMA_BE */ +#define SR_MAX_BE 0x2F, 0xF0, 4 + +/** Access parameters for sub-register MAX_CSMA_RETRIES in register @ref + * RG_XAH_CTRL_0 */ +#define SR_MAX_CSMA_RETRIES 0x2C, 0x0E, 1 + +/** Access parameters for sub-register MAX_FRAME_RETRIES in register @ref + * RG_XAH_CTRL_0 */ +#define SR_MAX_FRAME_RETRIES 0x2C, 0xF0, 4 + +/** Access parameters for sub-register MIN_BE in register @ref RG_CSMA_BE */ +#define SR_MIN_BE 0x2F, 0x0F, 0 + +/** Access parameters for sub-register OQPSK_DATA_RATE in register @ref + * RG_TRX_CTRL_2 */ +#define SR_OQPSK_DATA_RATE 0x0C, 0x07, 0 + +/** Access parameters for sub-register OQPSK_SCRAM_EN in register @ref + * RG_TRX_CTRL_2 */ +#define SR_OQPSK_SCRAM_EN 0x0C, 0x20, 5 + +/** Access parameters for sub-register PAN_ID_0 in register @ref RG_PAN_ID_0 */ +#define SR_PAN_ID_0 0x22, 0xFF, 0 + +/** Access parameters for sub-register PAN_ID_1 in register @ref RG_PAN_ID_1 */ +#define SR_PAN_ID_1 0x23, 0xFF, 0 + +/** Access parameters for sub-register PART_NUM in register @ref RG_PART_NUM */ +#define SR_PART_NUM 0x1C, 0xFF, 0 + +/** Access parameters for sub-register PA_EXT_EN in register @ref RG_TRX_CTRL_1 +**/ +#define SR_PA_EXT_EN 0x04, 0x80, 7 + +/** Access parameters for sub-register PDT_RPC_EN in register @ref RG_TRX_RPC */ +#define SR_PDT_RPC_EN 0x16, 0x10, 4 + +/** Access parameters for sub-register PDT_THRES in register @ref RG_RX_CTRL */ +#define SR_PDT_THRES 0x0A, 0x0F, 0 + +/** Access parameters for sub-register PLL_CF in register @ref RG_PLL_CF */ +#define SR_PLL_CF 0x1A, 0x0F, 0 + +/** Access parameters for sub-register PLL_CF_START in register @ref RG_PLL_CF +**/ +#define SR_PLL_CF_START 0x1A, 0x80, 7 + +/** Access parameters for sub-register PLL_DCU_START in register @ref RG_PLL_DCU +**/ +#define SR_PLL_DCU_START 0x1B, 0x80, 7 + +/** Access parameters for sub-register PLL_RPC_EN in register @ref RG_TRX_RPC */ +#define SR_PLL_RPC_EN 0x16, 0x08, 3 + +/** Access parameters for sub-register PMU_VALUE in register @ref + * RG_PHY_PMU_VALUE */ +#define SR_PMU_VALUE 0x3B, 0xFF, 0 + +/** Access parameters for sub-register RND_VALUE in register @ref RG_PHY_RSSI */ +#define SR_RND_VALUE 0x06, 0x60, 5 + +/** Access parameters for sub-register RSSI in register @ref RG_PHY_RSSI */ +#define SR_RSSI 0x06, 0x1F, 0 + +/** Access parameters for sub-register RX_BL_CTRL in register @ref RG_TRX_CTRL_1 +**/ +#define SR_RX_BL_CTRL 0x04, 0x10, 4 + +/** Access parameters for sub-register RX_CRC_VALID in register @ref RG_PHY_RSSI +**/ +#define SR_RX_CRC_VALID 0x06, 0x80, 7 + +/** Access parameters for sub-register RX_CRC_VALID_APX in register @ref + * RG_RX_STATUS */ +#define SR_RX_CRC_VALID_APX 0x02, 0x80, 7 + +/** Access parameters for sub-register RX_PDT_DIS in register @ref RG_RX_SYN */ +#define SR_RX_PDT_DIS 0x15, 0x80, 7 + +/** Access parameters for sub-register RX_PDT_LEVEL in register @ref RG_RX_SYN +**/ +#define SR_RX_PDT_LEVEL 0x15, 0x0F, 0 + +/** Access parameters for sub-register RX_RPC_CTRL in register @ref RG_TRX_RPC +**/ +#define SR_RX_RPC_CTRL 0x16, 0xC0, 6 + +/** Access parameters for sub-register RX_RPC_EN in register @ref RG_TRX_RPC */ +#define SR_RX_RPC_EN 0x16, 0x20, 5 + +/** Access parameters for sub-register RX_SAFE_MODE in register @ref + * RG_TRX_CTRL_2 */ +#define SR_RX_SAFE_MODE 0x0C, 0x80, 7 + +/** Access parameters for sub-register SFD_VALUE in register @ref RG_SFD_VALUE +**/ +#define SR_SFD_VALUE 0x0B, 0xFF, 0 + +/** Access parameters for sub-register SHORT_ADDR_0 in register @ref + * RG_SHORT_ADDR_0 */ +#define SR_SHORT_ADDR_0 0x20, 0xFF, 0 + +/** Access parameters for sub-register SHORT_ADDR_1 in register @ref + * RG_SHORT_ADDR_1 */ +#define SR_SHORT_ADDR_1 0x21, 0xFF, 0 + +/** Access parameters for sub-register SLOTTED_OPERATION in register @ref + * RG_XAH_CTRL_0 */ +#define SR_SLOTTED_OPERATION 0x2C, 0x01, 0 + +/** Access parameters for sub-register SPI_CMD_MODE in register @ref + * RG_TRX_CTRL_1 */ +#define SR_SPI_CMD_MODE 0x04, 0x0C, 2 + +/** Access parameters for sub-register TRAC_STATUS in register @ref RG_TRX_STATE +**/ +#define SR_TRAC_STATUS 0x02, 0xE0, 5 + +/** Access parameters for sub-register TRAC_STATUS_APX in register @ref + * RG_RX_STATUS */ +#define SR_TRAC_STATUS_APX 0x02, 0x70, 4 + +/** Access parameters for sub-register TRX_CMD in register @ref RG_TRX_STATE */ +#define SR_TRX_CMD 0x02, 0x1F, 0 + +/** Access parameters for sub-register TRX_STATUS in register @ref RG_TRX_STATUS +**/ +#define SR_TRX_STATUS 0x01, 0x1F, 0 + +/** Access parameters for sub-register TST_CTRL_DIG in register @ref + * RG_TST_CTRL_DIGI */ +#define SR_TST_CTRL_DIG 0x36, 0x0F, 0 + +/** Access parameters for sub-register TX_AUTO_CRC_ON in register @ref + * RG_TRX_CTRL_1 */ +#define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5 + +/** Access parameters for sub-register TX_PWR in register @ref RG_PHY_TX_PWR */ +#define SR_TX_PWR 0x05, 0x0F, 0 + +/** Access parameters for sub-register VERSION_NUM in register @ref + * RG_VERSION_NUM */ +#define SR_VERSION_NUM 0x1D, 0xFF, 0 + +/** Access parameters for sub-register XAH_TX_RPC_EN in register @ref RG_TRX_RPC +**/ +#define SR_XAH_TX_RPC_EN 0x16, 0x04, 2 + +/** Access parameters for sub-register XTAL_MODE in register @ref RG_XOSC_CTRL +**/ +#define SR_XTAL_MODE 0x12, 0xF0, 4 + +/** Access parameters for sub-register XTAL_TRIM in register @ref RG_XOSC_CTRL +**/ +#define SR_XTAL_TRIM 0x12, 0x0F, 0 + +/** Constants */ + +/** Constant PA_EXT_disable for sub-register SR_PA_EXT_EN */ +#define PA_EXT_DISABLE (0U) + +/** Constant PA_EXT_enable for sub-register SR_PA_EXT_EN */ +#define PA_EXT_ENABLE (1U) + +/** Constant AACK_SPC_DISABLE for sub-register @ref SR_AACK_SPC_EN in register + * XAH_CTRL_1 */ +#define AACK_SPC_DISABLE (0U) + +/** Constant AACK_SPC_ENABLE for sub-register @ref SR_AACK_SPC_EN in register + * XAH_CTRL_1 */ +#define AACK_SPC_ENABLE (1U) + +/** Constant ACK_DISABLE for sub-register @ref SR_AACK_DIS_ACK in register + * CSMA_SEED_1 */ +#define ACK_DISABLE (1U) + +/** Constant ACK_ENABLE for sub-register @ref SR_AACK_DIS_ACK in register + * CSMA_SEED_1 */ +#define ACK_ENABLE (0U) + +/** Constant ACK_TIME_12_SYMBOLS for sub-register @ref SR_AACK_ACK_TIME in + * register XAH_CTRL_1 */ +#define ACK_TIME_12_SYMBOLS (0U) + +/** Constant ACK_TIME_2_SYMBOLS for sub-register @ref SR_AACK_ACK_TIME in + * register XAH_CTRL_1 */ +#define ACK_TIME_2_SYMBOLS (1U) + +/** Constant AES_DIR_DECRYPT for sub-register @ref SR_AES_DIR in register + * AES_CTRL */ +#define AES_DIR_DECRYPT (1U) + +/** Constant AES_DIR_ENCRYPT for sub-register @ref SR_AES_DIR in register + * AES_CTRL */ +#define AES_DIR_ENCRYPT (0U) + +/** Constant AES_DONE for sub-register @ref SR_AES_DONE in register AES_STATUS +**/ +#define AES_DONE (1U) + +/** Constant AES_ERROR for sub-register @ref SR_AES_ER in register AES_STATUS */ +#define AES_ERROR (1U) + +/** Constant AES_MODE_CBC for sub-register @ref SR_AES_MODE in register AES_CTRL +**/ +#define AES_MODE_CBC (2U) + +/** Constant AES_MODE_ECB for sub-register @ref SR_AES_MODE in register AES_CTRL +**/ +#define AES_MODE_ECB (0U) + +/** Constant AES_MODE_KEY for sub-register @ref SR_AES_MODE in register AES_CTRL +**/ +#define AES_MODE_KEY (1U) + +/** Constant AES_NOT_DONE for sub-register @ref SR_AES_DONE in register + * AES_STATUS */ +#define AES_NOT_DONE (0U) + +/** Constant AES_NO_ERROR for sub-register @ref SR_AES_ER in register AES_STATUS +**/ +#define AES_NO_ERROR (0U) + +/** Constant AES_REQUEST for sub-register @ref SR_AES_REQUEST in register + * AES_CTRL */ +#define AES_REQUEST (1U) + +/** Constant ALTRATE_1_MBPS for sub-register @ref SR_OQPSK_DATA_RATE in register + * TRX_CTRL_2 */ +#define ALTRATE_1_MBPS (2U) + +/** Constant ALTRATE_250_KBPS for sub-register @ref SR_OQPSK_DATA_RATE in + * register TRX_CTRL_2 */ +#define ALTRATE_250_KBPS (0U) + +/** Constant ALTRATE_2_MBPS for sub-register @ref SR_OQPSK_DATA_RATE in register + * TRX_CTRL_2 */ +#define ALTRATE_2_MBPS (3U) + +/** Constant ALTRATE_500_KBPS for sub-register @ref SR_OQPSK_DATA_RATE in + * register TRX_CTRL_2 */ +#define ALTRATE_500_KBPS (1U) + +/** Constant ANT_CTRL_0 for sub-register @ref SR_ANT_CTRL in register ANT_DIV */ +#define ANT_CTRL_0 (0U) + +/** Constant ANT_CTRL_1 for sub-register @ref SR_ANT_CTRL in register ANT_DIV */ +#define ANT_CTRL_1 (1U) + +/** Constant ANT_CTRL_2 for sub-register @ref SR_ANT_CTRL in register ANT_DIV */ +#define ANT_CTRL_2 (2U) + +/** Constant ANT_CTRL_3 for sub-register @ref SR_ANT_CTRL in register ANT_DIV */ +#define ANT_CTRL_3 (3U) + +/** Constant ANT_DIV_DISABLE for sub-register @ref SR_ANT_DIV_EN in register + * ANT_DIV */ +#define ANT_DIV_DISABLE (0U) + +/** Constant ANT_DIV_ENABLE for sub-register @ref SR_ANT_DIV_EN in register + * ANT_DIV */ +#define ANT_DIV_ENABLE (1U) + +/** Constant ANT_EXT_SW_DISABLE for sub-register @ref SR_ANT_EXT_SW_EN in + * register ANT_DIV */ +#define ANT_EXT_SW_DISABLE (0U) + +/** Constant ANT_EXT_SW_ENABLE for sub-register @ref SR_ANT_EXT_SW_EN in + * register ANT_DIV */ +#define ANT_EXT_SW_ENABLE (1U) + +/** Constant ANT_SEL_ANTENNA_0 for sub-register @ref SR_ANT_SEL in register + * ANT_DIV */ +#define ANT_SEL_ANTENNA_0 (0U) + +/** Constant ANT_SEL_ANTENNA_1 for sub-register @ref SR_ANT_SEL in register + * ANT_DIV */ +#define ANT_SEL_ANTENNA_1 (1U) + +/** Constant BATMON_HR_HIGH for sub-register @ref SR_BATMON_HR in register + * BATMON */ +#define BATMON_HR_HIGH (1U) + +/** Constant BATMON_HR_LOW for sub-register @ref SR_BATMON_HR in register BATMON +**/ +#define BATMON_HR_LOW (0U) + +/** Constant BATMON_NOT_VALID for sub-register @ref SR_BATMON_OK in register + * BATMON */ +#define BATMON_NOT_VALID (0U) + +/** Constant BATMON_VALID for sub-register @ref SR_BATMON_OK in register BATMON +**/ +#define BATMON_VALID (1U) + +/** Constant CCA_CH_BUSY for sub-register @ref SR_CCA_STATUS in register + * TRX_STATUS */ +#define CCA_CH_BUSY (0U) + +/** Constant CCA_CH_IDLE for sub-register @ref SR_CCA_STATUS in register + * TRX_STATUS */ +#define CCA_CH_IDLE (1U) + +/** Constant CCA_COMPLETED for sub-register @ref SR_CCA_DONE in register + * TRX_STATUS */ +#define CCA_COMPLETED (1U) + +/** Constant CCA_MODE_0 for sub-register @ref SR_CCA_MODE in register PHY_CC_CCA +**/ +#define CCA_MODE_0 (0U) + +/** Constant CCA_MODE_1 for sub-register @ref SR_CCA_MODE in register PHY_CC_CCA +**/ +#define CCA_MODE_1 (1U) + +/** Constant CCA_MODE_2 for sub-register @ref SR_CCA_MODE in register PHY_CC_CCA +**/ +#define CCA_MODE_2 (2U) + +/** Constant CCA_MODE_3 for sub-register @ref SR_CCA_MODE in register PHY_CC_CCA +**/ +#define CCA_MODE_3 (3U) + +/** Constant CCA_NO_START for sub-register @ref SR_CCA_REQUEST in register + * PHY_CC_CCA */ +#define CCA_NO_START (0U) + +/** Constant CCA_ONGOING for sub-register @ref SR_CCA_DONE in register + * TRX_STATUS */ +#define CCA_ONGOING (0U) + +/** Constant CCA_START for sub-register @ref SR_CCA_REQUEST in register + * PHY_CC_CCA */ +#define CCA_START (1U) + +/** Constant CLEAR_PD for sub-register @ref SR_AACK_SET_PD in register + * CSMA_SEED_1 */ +#define CLEAR_PD (0U) + +/** Constant CLKM_16MHZ for sub-register @ref SR_CLKM_CTRL in register + * TRX_CTRL_0 */ +#define CLKM_16MHZ (5U) + +/** Constant CLKM_1MHZ for sub-register @ref SR_CLKM_CTRL in register TRX_CTRL_0 +**/ +#define CLKM_1MHZ (1U) + +/** Constant CLKM_1_16MHZ for sub-register @ref SR_CLKM_CTRL in register + * TRX_CTRL_0 */ +#define CLKM_1_16MHZ (7U) + +/** Constant CLKM_1_4MHZ for sub-register @ref SR_CLKM_CTRL in register + * TRX_CTRL_0 */ +#define CLKM_1_4MHZ (6U) + +/** Constant CLKM_2MHZ for sub-register @ref SR_CLKM_CTRL in register TRX_CTRL_0 +**/ +#define CLKM_2MHZ (2U) + +/** Constant CLKM_4MHZ for sub-register @ref SR_CLKM_CTRL in register TRX_CTRL_0 +**/ +#define CLKM_4MHZ (3U) + +/** Constant CLKM_8MHZ for sub-register @ref SR_CLKM_CTRL in register TRX_CTRL_0 +**/ +#define CLKM_8MHZ (4U) + +/** Constant CLKM_NO_CLOCK for sub-register @ref SR_CLKM_CTRL in register + * TRX_CTRL_0 */ +#define CLKM_NO_CLOCK (0U) + +/** Constant CLKM_SHA_DISABLE for sub-register @ref SR_CLKM_SHA_SEL in register + * TRX_CTRL_0 */ +#define CLKM_SHA_DISABLE (0U) + +/** Constant CLKM_SHA_ENABLE for sub-register @ref SR_CLKM_SHA_SEL in register + * TRX_CTRL_0 */ +#define CLKM_SHA_ENABLE (1U) + +/** Constant CRC16_NOT_VALID for sub-register @ref SR_RX_CRC_VALID in register + * PHY_RSSI */ +#define CRC16_NOT_VALID (0U) + +/** Constant CRC16_VALID for sub-register @ref SR_RX_CRC_VALID in register + * PHY_RSSI */ +#define CRC16_VALID (1U) + +/** Constant FLTR_RES_FT_DISABLE for sub-register @ref SR_AACK_FLTR_RES_FT in + * register XAH_CTRL_1 */ +#define FLTR_RES_FT_DISABLE (0U) + +/** Constant FLTR_RES_FT_ENABLE for sub-register @ref SR_AACK_FLTR_RES_FT in + * register XAH_CTRL_1 */ +#define FLTR_RES_FT_ENABLE (1U) + +/** Constant FRAME_VERSION_00 for sub-register @ref SR_AACK_FVN_MODE in register + * CSMA_SEED_1 */ +#define FRAME_VERSION_00 (0U) + +/** Constant FRAME_VERSION_01 for sub-register @ref SR_AACK_FVN_MODE in register + * CSMA_SEED_1 */ +#define FRAME_VERSION_01 (1U) + +/** Constant FRAME_VERSION_012 for sub-register @ref SR_AACK_FVN_MODE in + * register CSMA_SEED_1 */ +#define FRAME_VERSION_012 (2U) + +/** Constant FRAME_VERSION_IGNORED for sub-register @ref SR_AACK_FVN_MODE in + * register CSMA_SEED_1 */ +#define FRAME_VERSION_IGNORED (3U) + +/** Constant IRQ_HIGH_ACTIVE for sub-register @ref SR_IRQ_POLARITY in register + * TRX_CTRL_1 */ +#define IRQ_HIGH_ACTIVE (0U) + +/** Constant IRQ_LOW_ACTIVE for sub-register @ref SR_IRQ_POLARITY in register + * TRX_CTRL_1 */ +#define IRQ_LOW_ACTIVE (1U) + +/** Constant IRQ_MASK_MODE_OFF for sub-register @ref SR_IRQ_MASK_MODE in + * register TRX_CTRL_1 */ +#define IRQ_MASK_MODE_OFF (0U) + +/** Constant IRQ_MASK_MODE_ON for sub-register @ref SR_IRQ_MASK_MODE in register + * TRX_CTRL_1 */ +#define IRQ_MASK_MODE_ON (1U) + +/** Constant I_AM_COORD_DISABLE for sub-register @ref SR_AACK_I_AM_COORD in + * register CSMA_SEED_1 */ +#define I_AM_COORD_DISABLE (0U) + +/** Constant I_AM_COORD_ENABLE for sub-register @ref SR_AACK_I_AM_COORD in + * register CSMA_SEED_1 */ +#define I_AM_COORD_ENABLE (1U) + +/** Constant NORMAL for sub-register @ref SR_TST_CTRL_DIG in register + * TST_CTRL_DIGI */ +#define NORMAL (0x0U) + +/** Constant OQPSK_SCRAM_DISABLE for sub-register @ref SR_OQPSK_SCRAM_EN in + * register TRX_CTRL_2 */ +#define OQPSK_SCRAM_DISABLE (0U) + +/** Constant OQPSK_SCRAM_ENABLE for sub-register @ref SR_OQPSK_SCRAM_EN in + * register TRX_CTRL_2 */ +#define OQPSK_SCRAM_ENABLE (1U) + +/** Constant PART_NUM_AT86RF233 for sub-register @ref SR_PART_NUM in register + * PART_NUM */ +#define PART_NUM_AT86RF233 (0x0BU) + +/** Constant PROM_MODE_DISABLE for sub-register @ref SR_AACK_PROM_MODE in + * register XAH_CTRL_1 */ +#define PROM_MODE_DISABLE (0U) + +/** Constant PROM_MODE_ENABLE for sub-register @ref SR_AACK_PROM_MODE in + * register XAH_CTRL_1 */ +#define PROM_MODE_ENABLE (1U) + +/** Constant RX_BL_CTRL_DISABLE for sub-register @ref SR_RX_BL_CTRL in register + * TRX_CTRL_1 */ +#define RX_BL_CTRL_DISABLE (0U) + +/** Constant RX_BL_CTRL_ENABLE for sub-register @ref SR_RX_BL_CTRL in register + * TRX_CTRL_1 */ +#define RX_BL_CTRL_ENABLE (1U) + +/** Constant RX_DISABLE for sub-register @ref SR_RX_PDT_DIS in register RX_SYN +**/ +#define RX_DISABLE (1U) + +/** Constant RX_ENABLE for sub-register @ref SR_RX_PDT_DIS in register RX_SYN */ +#define RX_ENABLE (0U) + +/** Constant RX_OFFSET_16US for sub-register @ref SR_RX_RPC_CTRL in register + * TRX_RPC */ +#define RX_OFFSET_16US (3U) + +/** Constant RX_OFFSET_MIN for sub-register @ref SR_RX_RPC_CTRL in register + * TRX_RPC */ +#define RX_OFFSET_MIN (0U) + +/** Constant RX_SAFE_MODE_DISABLE for sub-register @ref SR_RX_SAFE_MODE in + * register TRX_CTRL_2 */ +#define RX_SAFE_MODE_DISABLE (0U) + +/** Constant RX_SAFE_MODE_ENABLE for sub-register @ref SR_RX_SAFE_MODE in + * register TRX_CTRL_2 */ +#define RX_SAFE_MODE_ENABLE (1U) + +/** Constant RX_TIMESTAMPING_DISABLE for sub-register @ref SR_IRQ_2_EXT_EN in + * register TRX_CTRL_1 */ +#define RX_TIMESTAMPING_DISABLE (0U) + +/** Constant RX_TIMESTAMPING_ENABLE for sub-register @ref SR_IRQ_2_EXT_EN in + * register TRX_CTRL_1 */ +#define RX_TIMESTAMPING_ENABLE (1U) + +/** Constant SET_PD for sub-register @ref SR_AACK_SET_PD in register CSMA_SEED_1 +**/ +#define SET_PD (1U) + +/** Constant SPI_CMD_MODE_DEFAULT for sub-register @ref SR_SPI_CMD_MODE in + * register TRX_CTRL_1 */ +#define SPI_CMD_MODE_DEFAULT (0U) + +/** Constant SPI_CMD_MODE_IRQ_STATUS for sub-register @ref SR_SPI_CMD_MODE in + * register TRX_CTRL_1 */ +#define SPI_CMD_MODE_IRQ_STATUS (3U) + +/** Constant SPI_CMD_MODE_PHY_RSSI for sub-register @ref SR_SPI_CMD_MODE in + * register TRX_CTRL_1 */ +#define SPI_CMD_MODE_PHY_RSSI (2U) + +/** Constant SPI_CMD_MODE_TRX_STATUS for sub-register @ref SR_SPI_CMD_MODE in + * register TRX_CTRL_1 */ +#define SPI_CMD_MODE_TRX_STATUS (1U) + +/** Constant THRES_ANT_DIV_DISABLE for sub-register @ref SR_PDT_THRES in + * register RX_CTRL */ +#define THRES_ANT_DIV_DISABLE (0x7U) + +/** Constant THRES_ANT_DIV_ENABLE for sub-register @ref SR_PDT_THRES in register + * RX_CTRL */ +#define THRES_ANT_DIV_ENABLE (0x3U) + +/** Constant TST_CONT_TX for sub-register @ref SR_TST_CTRL_DIG in register + * TST_CTRL_DIGI */ +#define TST_CONT_TX (0xFU) + +/** Constant TX_ARET_TIMESTAMPING_DISABLE for sub-register @ref SR_ARET_TX_TS_EN + * in register XAH_CTRL_1 */ +#define TX_ARET_TIMESTAMPING_DISABLE (0U) + +/** Constant TX_ARET_TIMESTAMPING_ENABLE for sub-register @ref SR_ARET_TX_TS_EN + * in register XAH_CTRL_1 */ +#define TX_ARET_TIMESTAMPING_ENABLE (1U) + +/** Constant TX_AUTO_CRC_DISABLE for sub-register @ref SR_TX_AUTO_CRC_ON in + * register TRX_CTRL_1 */ +#define TX_AUTO_CRC_DISABLE (0U) + +/** Constant TX_AUTO_CRC_ENABLE for sub-register @ref SR_TX_AUTO_CRC_ON in + * register TRX_CTRL_1 */ +#define TX_AUTO_CRC_ENABLE (1U) + +/** Constant UPLD_RES_FT_DISABLE for sub-register @ref SR_AACK_UPLD_RES_FT in + * register XAH_CTRL_1 */ +#define UPLD_RES_FT_DISABLE (0U) + +/** Constant UPLD_RES_FT_ENABLE for sub-register @ref SR_AACK_UPLD_RES_FT in + * register XAH_CTRL_1 */ +#define UPLD_RES_FT_ENABLE (1U) + +/** Constant VERSION_NUM_AT86RF233 for sub-register @ref SR_VERSION_NUM in + * register VERSION_NUM */ +#define VERSION_NUM_AT86RF233 (0x01U) + +/** Enumerations */ + +/** sub-register TRX_CMD in register TRX_STATE */ +typedef enum trx_cmd_tag { + /** Constant CMD_NOP for sub-register @ref SR_TRX_CMD */ + CMD_NOP = (0x00), + + /** Constant CMD_TX_START for sub-register @ref SR_TRX_CMD */ + CMD_TX_START = (0x02), + + /** Constant CMD_FORCE_TRX_OFF for sub-register @ref SR_TRX_CMD */ + CMD_FORCE_TRX_OFF = (0x03), + + /** Constant CMD_FORCE_PLL_ON for sub-register @ref SR_TRX_CMD */ + CMD_FORCE_PLL_ON = (0x04), + + /** Constant CMD_RX_ON for sub-register @ref SR_TRX_CMD */ + CMD_RX_ON = (0x06), + + /** Constant CMD_TRX_OFF for sub-register @ref SR_TRX_CMD */ + CMD_TRX_OFF = (0x08), + + /** Constant CMD_PLL_ON for sub-register @ref SR_TRX_CMD */ + CMD_PLL_ON = (0x09), + + /** Constant CMD_PREP_DEEP_SLEEP for sub-register @ref SR_TRX_CMD */ + CMD_PREP_DEEP_SLEEP = (0x10), + + /** Constant CMD_RX_AACK_ON for sub-register @ref SR_TRX_CMD */ + CMD_RX_AACK_ON = (0x16), + + /** Constant CMD_TX_ARET_ON for sub-register @ref SR_TRX_CMD */ + CMD_TX_ARET_ON = (0x19), + + /** Software implemented command */ + CMD_SLEEP = (0x0F), + + /** Software implemented command */ + CMD_DEEP_SLEEP = (0x20) +} trx_cmd_t; + +/** sub-register TRX_STATUS in register TRX_STATUS */ +typedef enum tal_trx_status_tag { + /** Constant P_ON for sub-register @ref SR_TRX_STATUS */ + P_ON = (0x00), + + /** Constant BUSY_RX for sub-register @ref SR_TRX_STATUS */ + BUSY_RX = (0x01), + + /** Constant BUSY_TX for sub-register @ref SR_TRX_STATUS */ + BUSY_TX = (0x02), + + /** Constant RX_ON for sub-register @ref SR_TRX_STATUS */ + RX_ON = (0x06), + + /** Constant TRX_OFF for sub-register @ref SR_TRX_STATUS */ + TRX_OFF = (0x08), + + /** Constant PLL_ON for sub-register @ref SR_TRX_STATUS */ + PLL_ON = (0x09), + + /** Constant TRX_SLEEP for sub-register @ref SR_TRX_STATUS */ + TRX_SLEEP = (0x0F), + + /** Constant PREP_DEEP_SLEEP for sub-register @ref SR_TRX_STATUS */ + PREP_DEEP_SLEEP = (0x10), + + /** Constant BUSY_RX_AACK for sub-register @ref SR_TRX_STATUS */ + BUSY_RX_AACK = (0x11), + + /** Constant BUSY_TX_ARET for sub-register @ref SR_TRX_STATUS */ + BUSY_TX_ARET = (0x12), + + /** Constant RX_AACK_ON for sub-register @ref SR_TRX_STATUS */ + RX_AACK_ON = (0x16), + + /** Constant TX_ARET_ON for sub-register @ref SR_TRX_STATUS */ + TX_ARET_ON = (0x19), + + /** Constant STATE_TRANSITION_IN_PROGRESS for sub-register @ref + * SR_TRX_STATUS */ + STATE_TRANSITION_IN_PROGRESS = (0x1F), + + /** Software implemented state */ + TRX_DEEP_SLEEP = (0x20) +} tal_trx_status_t; + +/** sub-register IRQ_7_BAT_LOW IRQ_6_TRX_UR IRQ_5_AMI IRQ_4_CCA_ED_DONE + * IRQ_3_TRX_END IRQ_2_RX_START IRQ_1_PLL_UNLOCK IRQ_0_PLL_LOCK in register + * IRQ_STATUS */ +typedef enum trx_irq_reason_tag { + /** Constant TRX_IRQ_7_BAT_LOW for sub-register @ref SR_IRQ_7_BAT_LOW */ + TRX_IRQ_7_BAT_LOW = (0x80), + + /** Constant TRX_IRQ_6_TRX_UR for sub-register @ref SR_IRQ_6_TRX_UR */ + TRX_IRQ_6_TRX_UR = (0x40), + + /** Constant TRX_IRQ_5_AMI for sub-register @ref SR_IRQ_5_AMI */ + TRX_IRQ_5_AMI = (0x20), + + /** Constant TRX_IRQ_4_CCA_ED_DONE for sub-register @ref + * SR_IRQ_4_CCA_ED_DONE */ + TRX_IRQ_4_CCA_ED_DONE = (0x10), + + /** Constant TRX_IRQ_3_TRX_END for sub-register @ref SR_IRQ_3_TRX_END */ + TRX_IRQ_3_TRX_END = (0x08), + + /** Constant TRX_IRQ_2_RX_START for sub-register @ref SR_IRQ_2_RX_START + **/ + TRX_IRQ_2_RX_START = (0x04), + + /** Constant TRX_IRQ_1_PLL_UNLOCK for sub-register @ref + * SR_IRQ_1_PLL_UNLOCK */ + TRX_IRQ_1_PLL_UNLOCK = (0x02), + + /** Constant TRX_IRQ_0_PLL_LOCK for sub-register @ref SR_IRQ_0_PLL_LOCK + **/ + TRX_IRQ_0_PLL_LOCK = (0x01), + + /** No interrupt is indicated by IRQ_STATUS register */ + TRX_NO_IRQ = (0x00) +} trx_irq_reason_t; + +/** sub-register TRAC_STATUS in register TRX_STATE */ +typedef enum trx_trac_status_tag { + /** Constant TRAC_SUCCESS for sub-register @ref SR_TRAC_STATUS */ + TRAC_SUCCESS = (0U), + + /** Constant TRAC_SUCCESS_DATA_PENDING for sub-register @ref + * SR_TRAC_STATUS */ + TRAC_SUCCESS_DATA_PENDING = (1U), + + /** Constant TRAC_SUCCESS_WAIT_FOR_ACK for sub-register @ref + * SR_TRAC_STATUS */ + TRAC_SUCCESS_WAIT_FOR_ACK = (2U), + + /** Constant TRAC_CHANNEL_ACCESS_FAILURE for sub-register @ref + * SR_TRAC_STATUS */ + TRAC_CHANNEL_ACCESS_FAILURE = (3U), + + /** Constant TRAC_NO_ACK for sub-register @ref SR_TRAC_STATUS */ + TRAC_NO_ACK = (5U), + + /** Constant TRAC_INVALID for sub-register @ref SR_TRAC_STATUS */ + TRAC_INVALID = (7U) +} trx_trac_status_t; + + +#endif /* AT86RF233_H */ diff --git a/driver/software/RF233/phy/at86rf233/inc/phy_internal.h b/driver/software/RF233/phy/at86rf233/inc/phy_internal.h new file mode 100644 index 0000000..7d8de5f --- /dev/null +++ b/driver/software/RF233/phy/at86rf233/inc/phy_internal.h @@ -0,0 +1,490 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* Prevent double inclusion */ +#ifndef PHY_INTERNAL_H +#define PHY_INTERNAL_H + +/* === INCLUDES ============================================================ */ + +#include "../../../resources/buffer/inc/bmm.h" +#include "../../../resources/queue/inc/qmm.h" +#include "../../../phy/inc/phy_constants.h" +#include "phy_trx_reg_access.h" +#include "../../../phy/inc/phy.h" +#include "at86rf.h" +#include "xc.h" +#include "definitions.h" + + + +/** + * \ingroup group_tal + * \defgroup group_tal_233 AT86RF233 Transceiver Abstraction Layer + * The AT86RF233 is a feature rich, low-power 2.4 GHz radio transceiver designed + * for industrial + * and consumer ZigBee/IEEE 802.15.4, 6LoWPAN, RF4CE and high data rate sub + * 1GHz ISM band applications + * The Transceiver Abstraction Layer (TAL) implements the transceiver specific + * functionalities and + * provides interfaces to the upper layers (like IEEE 802.15.4 MAC )and uses + * the services of PAL. + */ + +/** + * \ingroup group_tal_233 + * \defgroup group_tal_state_machine_233 TAL State Machine + * The different operating states of the Transceiver are controlled by the TAL + * state machine. + * + */ + +/** + * \ingroup group_tal_233 + * \defgroup group_tal_init_233 TAL Initialization and reset + * Performs initialization and reset functionalities of the transceiver + * + */ + +/** + * \ingroup group_tal_233 + * \defgroup group_tal_ed_233 TAL Energy Detection + * Performs the ED scan functionalities. + * + */ + +/** + * \ingroup group_tal_233 + * \defgroup group_tal_irq_233 Transceiver Interrupt Handling + * Handles Transceiver related Interrupts. + * + */ + +/** + * \ingroup group_tal_233 + * \defgroup group_tal_pib_233 TAL PIB Storage + * The PIB(Pan Information Base) attributes related to the TAL are Stored and + * handled by the TAL PIB storage. + * + */ + +/** + * \ingroup group_tal_233 + * \defgroup group_tal_tx_233 TAL Frame Transmission Unit + * The Frame Transmission Unit generates and transmits the frames using PAL . + * + */ + +/** + * \ingroup group_tal_tx_233 + * \defgroup group_tal_tx_csma_233 TAL CSMA/CA Module + * Performs channel access mechanism for frame transmission + * For Detailed information refer CSMA-CA algorithm section of IEEE Std + * 802.15.4-2006 + * + */ + +/** + * \ingroup group_tal_233 + * \defgroup group_tal_rx_233 TAL Frame Reception Unit + * The Frame Reception Unit reads/uploads the incoming frames . + * + */ + +/* === TYPES =============================================================== */ + +/** TAL states */ + +typedef enum tal_state_tag { + PHY_IDLE = 0, + PHY_TX_AUTO = 1, + PHY_TX_DONE = 2, + PHY_SLOTTED_CSMA = 3, + PHY_ED_RUNNING = 4, + PHY_ED_DONE = 5 + +} tal_state_t; + + +/* Structure implementing the PIB values stored in TAL */ +typedef __PACKED_STRUCT tal_pib_tag { + /** + * 64-bit (IEEE) address of the node. + */ + uint64_t IeeeAddress; + + /** + * Supported channels + * + * Legacy trx: + * Bit mask, whereas each bit position set indicates that the channel, + * corresponding to this particular bit position, is actually supported + * + * Multi-Trx devices: + * Min channel: Low word of variable SupportedChannels: + *(uint16_t)(SupportedChannels) + * Max channel: High word of variable SupportedChannels: + *(uint16_t)(SupportedChannels >> 16) + */ + uint32_t SupportedChannels; + + /** + * 16-bit short address of the node. + */ + uint16_t ShortAddress; + + /** + * 16-bit PAN ID + */ + uint16_t PANId; + + /** + * Maximum number of symbols in a frame: + * = phySHRDuration + ceiling([aMaxPHYPacketSize + 1] x + * phySymbolsPerOctet) + */ + uint16_t MaxFrameDuration; + + /** + * CCA Mode + */ + uint8_t CCAMode; + + /** + * Current RF channel to be used for all transmissions and receptions. + */ + + uint8_t CurrentChannel; + + /** + * The maximum number of back-offs the CSMA-CA algorithm will attempt + * before declaring a CSMA_CA failure. + */ + uint8_t MaxCSMABackoffs; + + /** + * The minimum value of the backoff exponent BE in the CSMA-CA + * algorithm. + */ + uint8_t MinBE; + + /** + * Indicates if the node is a PAN coordinator or not. + */ + bool PrivatePanCoordinator; + + /** + * Default value of transmit power of transceiver + * using IEEE defined format of phyTransmitPower. + */ + uint8_t TransmitPower; + + /** + * Current channel page. + */ + uint8_t CurrentPage; + + /** + * Duration of the synchronization header (SHR) in symbols for the + * current PHY. + */ + uint8_t SHRDuration; + + /** + * Number of symbols per octet for the current PHY. + */ + uint8_t SymbolsPerOctet; + + /** + * The maximum value of the backoff exponent BE in the CSMA-CA + * algorithm. + */ + uint8_t MaxBE; + + /** + * The maximum number of retries allowed after a transmission failure. + */ + uint8_t MaxFrameRetries; + +#ifdef PROMISCUOUS_MODE + + /** + * Promiscuous Mode + */ + bool PromiscuousMode; +#endif + +} tal_pib_t; + + +/* parameter types in transceiver */ +typedef struct phy_config_param_tag { + bool antDiversity; + bool antSelect; + uint8_t antCtrl; + bool extPACtrl; + bool aackPromMode; + int8_t txPwr; + uint8_t rxSens; + bool rxRPC; + bool rxSafeMode; + bool rxAutoAck; + bool rxReservedFrame; + bool reservedFrameFiltering; +}phy_config_param_t; + +typedef struct phy_info_tag{ + tal_state_t tal_state; + tal_trx_status_t tal_trx_status; + bool tal_rx_on_required; + uint8_t last_frame_length; + volatile bool tal_awake_end_flag; + phy_config_param_t phy_config_param; + uint32_t phyVersion; + uint8_t last_pkt_ed_level; + uint8_t last_pkt_lqi; +}phy_info_t; + +#define RX_PRIORITY_ARB_SET 0x01 +#define TX_PRIORITY_ARB_SET 0x01 + +#define DELAY_OK 0x00 +#define TIME_SENSITIVE 0x01 + + + + +#define TRX_SLP_TR_HIGH() SLP_TR_Set() + +#define TRX_SLP_TR_LOW() SLP_TR_Clear() + +#define TRX_RST_HIGH() _RST_Set() + +#define TRX_RST_LOW() _RST_Clear() + +#define TRX_SEL_HIGH() SPI_SS_Set() + +#define TRX_SEL_LOW() SPI_SS_Clear() + + +/* + * Default value of custom TAL PIB channel page + */ +#define PHY_CURRENT_PAGE_DEFAULT (0x00) + +/* + * Default value of maximum number of symbols in a frame + */ +#define PHY_MAX_FRAME_DURATION_DEFAULT (MAX_FRAME_DURATION) + +/* + * Default value of duration of the synchronization header (SHR) in symbols + * for the current PHY + */ +#define PHY_SHR_DURATION_DEFAULT (NO_OF_SYMBOLS_PREAMBLE_SFD) + +/* + * Default value of number of symbols per octet for the current PHY + */ +#define PHY_SYMBOLS_PER_OCTET_DEFAULT (SYMBOLS_PER_OCTET) + +/* + * Default value of maximum backoff exponent used while performing csma ca + */ +#define PHY_MAXBE_DEFAULT (0x05) + +/* + * Default value of PIB attribute macMaxFrameRetries + */ +#define PHY_MAXFRAMERETRIES_DEFAULT (0x03) + +/* + * Default value of maximum csma ca backoffs + */ +#define PHY_MAX_CSMA_BACKOFFS_DEFAULT (0x04) + +/* + * Default value of minimum backoff exponent used while performing csma ca + */ +#define PHY_MINBE_DEFAULT (0x03) + +/* + * Value of a broadcast PAN ID + */ +#define PHY_PANID_BC_DEFAULT (0xFFFF) + +/* + * Default value of short address + */ +#define PHY_SHORT_ADDRESS_DEFAULT (0xFFFF) + +/* + * Default value of current channel in TAL + */ +#define PHY_CURRENT_CHANNEL_DEFAULT (0x0B) + +/* + * Default value of promiscuous mode in TAL + */ +#define PHY_PIB_PROMISCUOUS_MODE_DEFAULT (false) + +#ifndef CUSTOM_DEFAULT_TX_PWR + +/* + * Default value of transmit power of transceiver: Use highest tx power + */ +#define PHY_TRANSMIT_POWER_DEFAULT (TX_PWR_TOLERANCE | 0x04U) +#endif + +/* + * Default value CCA mode + */ +#define PHY_CCA_MODE_DEFAULT (TRX_CCA_MODE1) + + +/* + * Default value beacon order set to 15 + */ +#define TAL_BEACON_ORDER_DEFAULT (15) + +/* + * Default value supeframe order set to 15 + */ +#define TAL_SUPERFRAME_ORDER_DEFAULT (15) + +/* + * Default value of BeaconTxTime + */ +#define TAL_BEACON_TX_TIME_DEFAULT (0x00000000) + +/* + * Default value of BatteryLifeExtension. + */ +#define PHY_BATTERY_LIFE_EXTENSION_DEFAULT (false) + +/* + * Default value of PAN Coordiantor custom TAL PIB + */ +#define PHY_PAN_COORDINATOR_DEFAULT (false) + +#ifndef ANTENNA_DEFAULT +#define ANTENNA_DEFAULT (ANT_CTRL_1) +#endif + +#ifdef ENABLE_QUEUE_CAPACITY +#define PHY_INCOMING_FRAME_QUEUE_CAPACITY (255) +#endif /* ENABLE_QUEUE_CAPACITY */ + +#define NUMBER_OF_PHY_TIMERS (1) + + +/* === EXTERNALS =========================================================== */ + +/* Global TAL variables */ +extern tal_pib_t tal_pib; +extern PHY_FrameInfo_t *mac_frame_ptr; +extern queue_t tal_incoming_frame_queue; +extern uint8_t *tal_frame_to_tx; +extern buffer_t *tal_rx_buffer; +extern phy_info_t phy_info; + +/* === MACROS ============================================================== */ + +/** + * Conversion of number of PSDU octets to duration in microseconds + */ +#ifdef HIGH_DATA_RATE_SUPPORT +#define TAL_PSDU_US_PER_OCTET(octets) \ + ( \ + tal_pib.CurrentPage == 0 ? ((uint16_t)(octets) * 32) : \ + ( \ + tal_pib.CurrentPage == 2 ? ((uint16_t)(octets) * 16) : \ + ( \ + tal_pib.CurrentPage == \ + 16 ? ((uint16_t)(octets) * \ + 8) : ((uint16_t)(octets) * 4) \ + ) \ + ) \ + ) +#else /* #ifdef not HIGH_DATA_RATE_SUPPORT */ +#define TAL_PSDU_US_PER_OCTET(octets) ((uint16_t)(octets) * 32) +#endif + +#define TRX_IRQ_DEFAULT TRX_IRQ_3_TRX_END + + +/* === PROTOTYPES ========================================================== */ + +/* + * Prototypes from tal.c + */ + +/** + * \brief Sets transceiver state + * + * \param trx_cmd needs to be one of the trx commands + * + * \return current trx state + * \ingroup group_tal_state_machine_233 + */ +tal_trx_status_t set_trx_state(trx_cmd_t trx_cmd); + +/* + * Prototypes from tal_init.c + */ +void trx_config(void); + +tal_trx_status_t tal_get_trx_status(void); + +/* + * Prototypes from tal_ed.c + */ + + +/** + * \brief Scan done + * + * This function updates the max_ed_level and invokes the callback function + * tal_ed_end_cb(). + * + * \ingroup group_tal_ed + */ +void ed_scan_done(void); +void trx_ed_irq_handler_cb(void); +void tal_trx_wakeup(void); +void trx_delay_micros(uint32_t us); +void trx_delay_millis(uint32_t ms); +void trx_delay_loop(void *hw, uint32_t cycles); +void trx_irq_flag_clear(void); +PHY_Retval_t tal_dump_registers(uint16_t start_addr, uint16_t end_addr, + uint8_t *value); +PHY_Retval_t tal_set_frequency_regs(uint8_t cc_band, uint8_t cc_number); + +PHY_Retval_t tal_set_frequency(float frequency); + +PHY_Retval_t tal_calculate_frequency(uint8_t cc_band, uint8_t cc_number, + float *freq); + +#endif /* TAL_INTERNAL_H */ diff --git a/driver/software/RF233/phy/at86rf233/inc/phy_irq_handler.h b/driver/software/RF233/phy/at86rf233/inc/phy_irq_handler.h new file mode 100644 index 0000000..0bb2310 --- /dev/null +++ b/driver/software/RF233/phy/at86rf233/inc/phy_irq_handler.h @@ -0,0 +1,73 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* Prevent double inclusion */ +#ifndef PHY_IRQ_HANDLER_H +#define PHY_IRQ_HANDLER_H + +/* === INCLUDES ============================================================ */ + +/* === EXTERNALS =========================================================== */ + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* === PROTOTYPES ========================================================== */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup group_tal_irq_233 + * @{ + */ + +/** + * \brief Transceiver interrupt handler + * + * This function handles the transceiver generated interrupts. + */ +void trx_irq_handler_cb(void); + +/** + * \brief Transceiver interrupt handler for awake end IRQ + * + * This function handles the transceiver awake end interrupt. + */ + +void trx_irq_awake_handler_cb(void); + +void EIC_interrupt_cb(uintptr_t context); + +/* ! @} */ +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* TAL_IRQ_HANDLER_H */ + +/* EOF */ diff --git a/driver/software/RF233/phy/at86rf233/inc/phy_pib.h b/driver/software/RF233/phy/at86rf233/inc/phy_pib.h new file mode 100644 index 0000000..4aafb08 --- /dev/null +++ b/driver/software/RF233/phy/at86rf233/inc/phy_pib.h @@ -0,0 +1,73 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* Prevent double inclusion */ +#ifndef PHY_PIB_H +#define PHY_PIB_H + +/* === INCLUDES ============================================================ */ + +/* === EXTERNALS =========================================================== */ + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* === PROTOTYPES ========================================================== */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup group_tal_pib_233 + * @{ + */ + +/** + * \brief Initialize the TAL PIB + * + * This function initializes the TAL information base attributes + * to their default values. + */ +void init_tal_pib(void); + +/** + * \brief Write all shadow PIB variables to the transceiver + * + * This function writes all shadow PIB variables to the transceiver. + * It is assumed that the radio does not sleep. + */ +void write_all_tal_pib_to_trx(void); + +/* ! @} */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* TAL_PIB_H */ + +/* EOF */ diff --git a/driver/software/RF233/phy/at86rf233/inc/phy_rx.h b/driver/software/RF233/phy/at86rf233/inc/phy_rx.h new file mode 100644 index 0000000..b41050d --- /dev/null +++ b/driver/software/RF233/phy/at86rf233/inc/phy_rx.h @@ -0,0 +1,73 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* Prevent double inclusion */ +#ifndef PHY_RX_H +#define PHY_RX_H + +/* === INCLUDES ============================================================ */ + +/* === EXTERNALS =========================================================== */ + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* === PROTOTYPES ========================================================== */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup group_tal_rx_233 + * @{ + */ + +/** + * \brief Handle received frame interrupt + * + * This function handles transceiver interrupts for received frames and + * uploads the frames from the trx. + */ + +void handle_received_frame_irq(void); + +/** + * \brief Parses received frame and create the PHY_FrameInfo_t structure + * + * This function parses the received frame and creates the PHY_FrameInfo_t + * structure to be sent to the MAC as a parameter of tal_rx_frame_cb(). + * + * \param buf Pointer to the buffer containing the received frame + */ +void process_incoming_frame(buffer_t *buf_ptr); + +/* ! @} */ +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* TAL_RX_H */ diff --git a/driver/software/RF233/phy/at86rf233/inc/phy_tx.h b/driver/software/RF233/phy/at86rf233/inc/phy_tx.h new file mode 100644 index 0000000..3eecbcf --- /dev/null +++ b/driver/software/RF233/phy/at86rf233/inc/phy_tx.h @@ -0,0 +1,85 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* Prevent double inclusion */ +#ifndef PHY_TX_H +#define PHY_TX_H + +/* === INCLUDES ============================================================ */ +#include "../../../phy/inc/phy.h" +/* === EXTERNALS =========================================================== */ + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* === PROTOTYPES ========================================================== */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup group_tal_tx + * @{ + */ + +/** + * \brief Handles interrupts issued due to end of transmission + * + * \param underrun_occured true if under-run has occurred + */ + +void handle_tx_end_irq(bool underrun_occured); + +/** + * \brief Sends frame using trx features to handle CSMA and re-transmissions + * + * \param csma_mode Indicates the CSMA Mode used + * \param tx_retries Flag indicating if transmission retries are requested + * by the MAC layer + */ + +void send_frame(PHY_CSMAMode_t csmaMode, bool txRetries); + +/** + * \brief Implements the handling of the transmission end. + * + * This function handles the callback for the transmission end. + */ +void tx_done_handling(void); + + +void tal_start_retransmission_timer(uint32_t us); + +/* ! @} */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* TAL_TX_H */ + +/* EOF */ diff --git a/driver/software/RF233/phy/at86rf233/src/phy_ed.c b/driver/software/RF233/phy/at86rf233/src/phy_ed.c new file mode 100644 index 0000000..3ba7b3c --- /dev/null +++ b/driver/software/RF233/phy/at86rf233/src/phy_ed.c @@ -0,0 +1,215 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* === INCLUDES ============================================================ */ + +#include +#include +#include +#include "../../../pal/inc/pal.h" +#include "../../../phy/inc/phy.h" +#include "../../../phy/inc/phy_tasks.h" +#include "../../../phy/inc/ieee_phy_const.h" +#include "../../../phy/inc/phy_constants.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../at86rf/inc/phy_internal.h" +#include "../../../phy/at86rf/inc/phy_irq_handler.h" +#include "../../../phy/at86rf/inc/phy_trx_reg_access.h" +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/** + * \addtogroup group_tal_ed_233 + * @{ + */ + +/* Constant define for the ED scaling: register value at -35dBm */ +#define CLIP_VALUE_REG (56U) + +#define MIN_ED_VAL (20U) +#define MAX_ED_VAL (83U) +/* + * Scan duration formula: \f$aBaseSuperframeDuration (2^SD + 1)\f$ + * where \f$0 <= SD <= 14\f$ + */ +#define CALCULATE_SYMBOL_TIME_SCAN_DURATION(SD) \ + (aBaseSuperframeDuration * ((1UL << (SD)) + 1UL)) + +/* === GLOBALS ============================================================= */ + +/** + * The peak_ed_level is the maximum ED value received from the transceiver for + * the specified Scan Duration. + */ +static uint8_t max_ed_level; +static uint32_t sampler_counter; + +/* === PROTOTYPES ========================================================== */ + +/* ! @} */ + +/* === IMPLEMENTATION ====================================================== */ + +/* + * \brief Starts ED Scan + * + * This function starts an ED Scan for the scan duration specified by the + * MAC layer. + * + * \param scan_duration Specifies the ED scan duration in symbols + * + * \return MAC_SUCCESS - ED scan duration timer started successfully + * TAL_BUSY - TAL is busy servicing the previous request from MAC + * TAL_TRX_ASLEEP - Transceiver is currently sleeping + * FAILURE otherwise + */ +PHY_Retval_t PHY_EdStart(uint8_t scan_duration) +{ + /* + * Check if the TAL is in idle state. Only in idle state it can + * accept and ED request from the MAC. + */ + if (PHY_IDLE != phy_info.tal_state) { + if (phy_info.tal_trx_status == TRX_SLEEP) { + return PHY_TRX_ASLEEP; + } else { + + return PHY_BUSY; + } + } + /* + * Disable the transceiver interrupts to prevent frame reception + * while performing ED scan. + */ + pal_trx_irq_dis(); /* Disable transceiver main interrupt. */ + (void)set_trx_state(CMD_FORCE_PLL_ON); + (void)trx_reg_read(RG_IRQ_STATUS); /* Clear existing interrupts */ + trx_reg_bit_write(SR_RX_PDT_DIS, RX_DISABLE); + trx_reg_bit_write(SR_IRQ_MASK, (uint8_t)TRX_IRQ_4_CCA_ED_DONE); /* enable + * interrupt */ + pal_trx_irq_en(); /* Enable transceiver main interrupt. */ + + /* Make sure that receiver is switched on. */ + if (set_trx_state(CMD_RX_ON) != RX_ON) { + /* Restore previous configuration */ + trx_reg_bit_write(SR_RX_PDT_DIS, RX_ENABLE); + + trx_reg_write(RG_IRQ_MASK, (uint8_t)TRX_IRQ_DEFAULT); /* enable + * TRX_END + * interrupt */ + return PHY_FAILURE; + } + + /* Perform ED in TAL_ED_RUNNING state. */ + phy_info.tal_state = PHY_ED_RUNNING; + + /* write dummy value to start measurement */ + trx_reg_write(RG_PHY_ED_LEVEL, 0xFF); + + max_ed_level = 0; /* reset max value */ + + sampler_counter = CALCULATE_SYMBOL_TIME_SCAN_DURATION(scan_duration) / + ED_SAMPLE_DURATION_SYM; + + return PHY_SUCCESS; +} + +/** + * \brief ED Scan Interrupt + * + * This function handles an ED done interrupt from the transceiver. + * + */ +void trx_ed_irq_handler_cb(void) +{ + uint8_t ed_value; + + /* Read the ED Value. */ + ed_value = trx_reg_read(RG_PHY_ED_LEVEL); + /* + * Update the peak ED value received, if greater than the + * previously + * read ED value. + */ + if (ed_value > max_ed_level) { + max_ed_level = ed_value; + } + + sampler_counter--; + if (sampler_counter > 0U) { + /* write dummy value to start measurement */ + trx_reg_write(RG_PHY_ED_LEVEL, 0xFF); + } else { + + phy_info.tal_state = PHY_ED_DONE; + //OSAL_SEM_PostISR(&semPhyRxInternalHandler); + PHY_PostTask(false); + } +} + +/* + * \brief Scan done + * + * This function updates the max_ed_level and invokes the callback function + * tal_ed_end_cb(). + * + * \param parameter unused callback parameter + */ +void ed_scan_done(void) +{ + trx_reg_bit_write(SR_RX_PDT_DIS, RX_ENABLE); + + trx_reg_write(RG_IRQ_MASK, (uint8_t)TRX_IRQ_DEFAULT); /* enable TRX_END + * interrupt */ + pal_trx_irq_en(); /* Enable transceiver main interrupt. */ + + phy_info.tal_state = PHY_IDLE; /* ed scan is done */ + + (void)set_trx_state(CMD_RX_AACK_ON); + +#ifndef TRX_REG_RAW_VALUE + /* + * Scale ED result. + * Clip values to 0xFF if > -35dBm + */ + if (max_ed_level > CLIP_VALUE_REG) { + max_ed_level = 0xFF; + } else { + max_ed_level + = (uint8_t)(((uint16_t)max_ed_level * + 0xFFU) / CLIP_VALUE_REG); + } +#endif /* TRX_REG_RAW_VALUE */ + + PHY_EdEndCallback(max_ed_level); +} + + + + + + +/* EOF */ diff --git a/driver/software/RF233/phy/at86rf233/src/phy_helper.c b/driver/software/RF233/phy/at86rf233/src/phy_helper.c new file mode 100644 index 0000000..be9f426 --- /dev/null +++ b/driver/software/RF233/phy/at86rf233/src/phy_helper.c @@ -0,0 +1,645 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* === INCLUDES ============================================================ */ + + + +#include "../../../pal/inc/pal.h" +#include "../../../phy/inc/phy.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../../phy/inc/phy_config.h" +#include "../../at86rf/inc/phy_internal.h" +#include "../../../phy/inc/ieee_phy_const.h" + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* === GLOBALS ============================================================= */ +extern const int8_t tx_pwr_table[16]; + +/* === PROTOTYPES ========================================================== */ +extern uint8_t convert_phyTransmitPower_to_reg_value( + uint8_t phyTransmitPower_value); + +/* === IMPLEMENTATION ====================================================== */ + +/** + * \brief Enable/Disable the external RF front end control + * + * \param pa_ext_sw_ctrl true if external rf front end control has to be + * enabled + * + * \return PHY_SUCCESS if PA_EXT_EN bit is configured correctly + * PHY_FAILURE otherwise + */ + + +PHY_Retval_t PHY_ConfigTxPwr(bool type, int8_t pwrValue) +{ + uint64_t temp_var; + int8_t tx_pwr_dbm = 0; + /* modify the register for tx_pwr and set the tal_pib accordingly */ + if (true == type) { + if (PHY_SUCCESS == + PHY_ConvertTxPwrRegValToDbm((uint8_t)pwrValue, + &tx_pwr_dbm)) { + temp_var = CONV_DBM_TO_phyTransmitPower(tx_pwr_dbm); + (void)PHY_PibSet(phyTransmitPower, (PibValue_t *)&temp_var); + + /* To make sure that TX_PWR register is updated with the + * value whatever user povided.Otherwise lowest dBm + * power + * (highest reg value will be taken) + */ + trx_reg_bit_write(SR_TX_PWR, (uint8_t)pwrValue); + + return PHY_SUCCESS; + } else { + /* return invalid parameter if out of range */ + return PHY_INVALID_PARAMETER; + } + } else { + temp_var = CONV_DBM_TO_phyTransmitPower(pwrValue); + (void)PHY_PibSet(phyTransmitPower, (PibValue_t *)&temp_var); + } + + + + uint8_t reg_value = convert_phyTransmitPower_to_reg_value( + tal_pib.TransmitPower); + /* check the value written in the transceiver register */ + uint8_t temp = trx_reg_bit_read(SR_TX_PWR); + + + if (temp == reg_value) { + phy_info.phy_config_param.txPwr = pwrValue; + return PHY_SUCCESS; + } else { + return PHY_FAILURE; + } +} + + + +/* + * \brief Configures antenna diversity and selects antenna + * + * \param div_ctrl true/false to enable/disable antenna diversity + * \param ant_ctrl 0 or 3 when antenna diversity is enabled + * 1 or 2 to select antenna 1 or antenna 2 + * \return The value set in the TX_PWR bits + */ + +PHY_Retval_t PHY_ConfigAntennaDiversity(bool divCtrl, uint8_t antCtrl) +{ + PHY_Retval_t return_var = PHY_FAILURE; + if (true == divCtrl) { + /* do the configurations if diversity has to be enabled */ + trx_reg_bit_write(SR_ANT_CTRL, ANT_CTRL_0); + trx_reg_bit_write(SR_ANT_DIV_EN, ANT_DIV_ENABLE); + trx_reg_bit_write(SR_PDT_THRES, THRES_ANT_DIV_ENABLE); + trx_reg_bit_write(SR_ANT_EXT_SW_EN, ANT_EXT_SW_ENABLE); + + /* check the values written in transceiver registers */ + if ((trx_reg_bit_read(SR_ANT_CTRL) == ANT_CTRL_0) && + (trx_reg_bit_read(SR_ANT_DIV_EN) == + ANT_DIV_ENABLE) && \ + (trx_reg_bit_read(SR_ANT_EXT_SW_EN) == + ANT_EXT_SW_ENABLE)) { + + + if ((trx_reg_bit_read(SR_PDT_THRES) == + THRES_ANT_DIV_ENABLE)){ + + phy_info.phy_config_param.antDiversity = divCtrl; + phy_info.phy_config_param.antCtrl = antCtrl; + + return_var = PHY_SUCCESS; + } + } else { + return_var = PHY_FAILURE; + } + } else { + /* do the configurations if diversity has to be disabled */ + trx_reg_bit_write(SR_ANT_DIV_EN, ANT_DIV_DISABLE); + trx_reg_bit_write(SR_PDT_THRES, THRES_ANT_DIV_DISABLE); + trx_reg_bit_write(SR_ANT_EXT_SW_EN, ANT_EXT_SW_ENABLE); + if (antCtrl == ANT_CTRL_1) { + /* Enable A1/X2 */ + trx_reg_bit_write(SR_ANT_CTRL, ANT_CTRL_1); + phy_info.phy_config_param.antSelect = 0; + } else if (antCtrl == ANT_CTRL_2) { + /* Enable A2/X3 */ + trx_reg_bit_write(SR_ANT_CTRL, ANT_CTRL_2); + phy_info.phy_config_param.antSelect = 1; + } else if (antCtrl == ANT_CTRL_0 || antCtrl == ANT_CTRL_3) { + trx_reg_bit_write(SR_ANT_CTRL, ANT_CTRL_0); + antCtrl = 0; + } else { + return_var = PHY_INVALID_PARAMETER; + } + /* check the values written in transceiver registers */ + if ((trx_reg_bit_read(SR_ANT_CTRL) == antCtrl) && + (trx_reg_bit_read(SR_ANT_DIV_EN) == + ANT_DIV_DISABLE) && \ + (trx_reg_bit_read(SR_ANT_EXT_SW_EN) == + ANT_EXT_SW_DISABLE)) { + + if ((trx_reg_bit_read(SR_PDT_THRES) == + THRES_ANT_DIV_ENABLE)) + { + phy_info.phy_config_param.antDiversity = divCtrl; + phy_info.phy_config_param.antCtrl = antCtrl; + + return_var = PHY_SUCCESS; + } + } else { + return_var = PHY_FAILURE; + } + } + return return_var; +} + + + +/* + * \brief Configures the frequency to be set in transceiver + * + * \param frequency frequency value to be set + * \return PHY_SUCCESS if frequency is configured correctly + * MAC_INVALID_PARAMETER if out of range or incorrect values are + * given + * PHY_FAILURE if frequency registers are not configured properly + */ + + +PHY_Retval_t tal_set_frequency(float frequency) +{ + double epsilon = 0.000000001; + double dummy = 0.0; + uint8_t cc_number = 0; + uint8_t cc_band = 0; + tal_trx_status_t previous_trx_status = TRX_OFF; + /* frequency has to selected by CHANNEL register bits in PHY_CC_CCA*/ + if ((abs((double)frequency - dummy)) < epsilon) { + cc_band = 0; + cc_number = 0; + } + /* return invalid parameter if input frequency is out of range */ + else if ((frequency < MIN_ISM_FREQUENCY_MHZ) || + (frequency > MAX_ISM_FREQUENCY_MHZ)) { + return PHY_INVALID_PARAMETER; + } + /* Choose CC_BAND & CC_NUMBER reg values for the input frequency */ + else if (frequency < MID_ISM_FREQUENCY_MHZ) { + /* required frequency maps to band 8 */ + cc_band = CC_BAND_8; + cc_number = (uint8_t)((frequency - BASE_ISM_FREQUENCY_MHZ) * 2.0f); + } else { + /* required frequency maps to band 9 */ + cc_band = CC_BAND_9; + cc_number = (uint8_t)((frequency - MID_ISM_FREQUENCY_MHZ) * 2.0f); + } + + if (phy_info.tal_trx_status != TRX_OFF) { + previous_trx_status = RX_AACK_ON; /* any other than TRX_OFF + * state */ + do { + /* set TRX_OFF until it could be set; + * trx might be busy */ + } while (set_trx_state(CMD_TRX_OFF) != TRX_OFF); + } + + trx_reg_bit_write(SR_CC_BAND, cc_band); + trx_reg_write(RG_CC_CTRL_0, cc_number); + + /* Re-store previous trx state */ + if (previous_trx_status != TRX_OFF) { + /* Set to default state */ + (void)set_trx_state(CMD_RX_AACK_ON); + } + + /* check the values written in transceiver registers */ + if (trx_reg_bit_read(SR_CC_BAND) != cc_band || \ + trx_reg_read(RG_CC_CTRL_0) != cc_number) { + return PHY_FAILURE; + } else { + return PHY_SUCCESS; + } +} + + + +/** + * \brief to set the frequency based on CC_BAND and CC_NUMBER Registers + * + * \param cc_band band to be selected in cc_band register bits + * \param cc_number offset frequency to be selected in cc_number register bits + * \return PHY_SUCCESS if frequency is configured correctly + * MAC_INVALID_PARAMETER if out of range or incorrect values are + * given + * PHY_FAILURE if frequency registers are not configured properly + */ + +PHY_Retval_t tal_set_frequency_regs(uint8_t cc_band, uint8_t cc_number) +{ + tal_trx_status_t previous_trx_status = TRX_OFF; + + + /* check cc band and cc number fit in the range*/ + if ((cc_band != CC_BAND_8) && (cc_band != CC_BAND_9)) { + return PHY_INVALID_PARAMETER; + } else if ((cc_band == CC_BAND_8) && + (cc_number < MIN_CC_BAND_8_OFFSET)) { + return PHY_INVALID_PARAMETER; + } else if ((cc_band == CC_BAND_9) && + (cc_number > MIN_CC_BAND_9_OFFSET)) { + return PHY_INVALID_PARAMETER; + } else{ + /*DO NOTHING*/ + } + + /* + * Set trx to trx_off to avoid interruption in ongoing + * transaction + */ + if (phy_info.tal_trx_status != TRX_OFF) { + previous_trx_status = RX_AACK_ON; /* any other than TRX_OFF + * state */ + do { + /* set TRX_OFF until it could be set; + * trx might be busy */ + } while (set_trx_state(CMD_TRX_OFF) != TRX_OFF); + } + + trx_reg_bit_write(SR_CC_BAND, cc_band); + trx_reg_write(RG_CC_CTRL_0, cc_number); + + /* Re-store previous trx state */ + if (previous_trx_status != TRX_OFF) { + /* Set to default state */ + (void)set_trx_state(CMD_RX_AACK_ON); + } + + /* check the values written in transceiver registers */ + if (trx_reg_bit_read(SR_CC_BAND) != cc_band || \ + trx_reg_read(RG_CC_CTRL_0) != cc_number) { + return PHY_FAILURE; + } else { + return PHY_SUCCESS; + } +} + + + +/* + * \brief Calculate the frequency based on CC_BAND and CC_NUMBER Registers + * + * \param CC_BAND and CC_NUMBER register values to calculate the frequency + * \param *freq pointer where the calculated frequency value should be stored + * + * \return PHY_SUCCESS if frequency is configured correctly + * MAC_INVALID_PARAMETER if out of range or incorrect values are given + * PHY_FAILURE if frequency registers are not configured properly + */ + +PHY_Retval_t tal_calculate_frequency(uint8_t cc_band, uint8_t cc_number, + float *freq) +{ + + /* check cc band and cc number fit in the range*/ + if ((cc_band != CC_BAND_8) && (cc_band != CC_BAND_9)) { + return PHY_INVALID_PARAMETER; + } else if ((cc_band == CC_BAND_8) && + (cc_number < MIN_CC_BAND_8_OFFSET)) { + return PHY_INVALID_PARAMETER; + } else if ((cc_band == CC_BAND_9) && + (cc_number > MIN_CC_BAND_9_OFFSET)) { + return PHY_INVALID_PARAMETER; + } else{ + /*DO NOTHING*/ + } + + *freq = (float)((cc_band == CC_BAND_8) ? + (BASE_ISM_FREQUENCY_MHZ + 0.5 * ((float)cc_number)) : + (MID_ISM_FREQUENCY_MHZ + 0.5 * ((float)cc_number))); + + return PHY_SUCCESS; +} + + + +/* + * \brief Configures receiver sensitivity level + * + * \param pdt_level 0 to 15 levels of rx sensitivity + * \param PHY_SUCCESS if sensitivity level is configured correctly + * MAC_INVALID_PARAMETER pdt_level is out of range + * PHY_FAILURE otherwise + */ + +PHY_Retval_t PHY_ConfigRxSensitivity(uint8_t pdtLevel) +{ + uint8_t temp; + /* return invalid parameter if sensitivity level is out of range*/ + if (pdtLevel > MAX_PDT_LEVEL) { + return PHY_INVALID_PARAMETER; + } + /* configure sensitivity level*/ + trx_reg_bit_write(SR_RX_PDT_LEVEL, pdtLevel); + + temp = trx_reg_bit_read(SR_RX_PDT_LEVEL); + if (temp == pdtLevel) { + phy_info.phy_config_param.rxSens = pdtLevel; + return PHY_SUCCESS; + } else { + return PHY_FAILURE; + } +} + + + +/* + * \brief Configures promiscous mode in rx_aack_on mode + * + * \param prom_ctrl true/false to enable/disable prom mode + * + * \param PHY_SUCCESS if rxaack_prom_mode is configured correctly + * PHY_FAILURE otherwise + */ + +PHY_Retval_t PHY_ConfigRxPromiscuousMode(bool promCtrl) +{ + bool temp; + /* configure promiscuous mode */ + trx_reg_bit_write(SR_AACK_PROM_MODE, (uint8_t)promCtrl); + temp = (bool)trx_reg_bit_read(SR_AACK_PROM_MODE); + if (temp == promCtrl) { + phy_info.phy_config_param.aackPromMode = promCtrl; + return PHY_SUCCESS; + } else { + return PHY_FAILURE; + } +} + + + +/* + * \brief to get the current status of the transceiver + * + * \return status of the transceiver + */ +tal_trx_status_t tal_get_trx_status(void) +{ + if (phy_info.tal_trx_status == TRX_SLEEP) + { + return (TRX_SLEEP); + } + tal_trx_status_t trx_status; + /* Read the status from trx_status bits */ + trx_status = (tal_trx_status_t)trx_reg_bit_read(SR_TRX_STATUS); + return trx_status; +} + + + +/* + * \brief to read a current setting particular transceiver parameter + * \param parameter type of the parameter to be read + * \param *param_value pointer to the location where the current parameter value + * need to be + * stored + * \return MAC_INVALID_PARAMETER if the parameter is invalid + * PHY_SUCCESS otherwise + */ + +PHY_Retval_t PHY_GetTrxConfig(PHY_ConfigParam_t parameter, uint8_t *paramValue) +{ + switch (parameter) { + + case ANT_DIVERSITY: + *paramValue = trx_reg_bit_read(SR_ANT_DIV_EN); + break; + + case ANT_SELECT_: + *paramValue = trx_reg_bit_read(SR_ANT_SEL); + break; + + case ANT_CTRL_: + *paramValue = trx_reg_bit_read(SR_ANT_CTRL); + break; + + case AACK_PROMSCS_MODE: + *paramValue = trx_reg_bit_read(SR_AACK_PROM_MODE); + break; + + case CC_BAND: + *paramValue = trx_reg_bit_read(SR_CC_BAND); + break; + + case CC_NUMBER: + *paramValue = trx_reg_read(RG_CC_CTRL_0); + break; + + case TX_PWR: + *paramValue = trx_reg_bit_read(SR_TX_PWR); + break; + + case RX_SENS: + *paramValue = trx_reg_bit_read(SR_RX_PDT_LEVEL); + break; + + case RX_RPC: + *paramValue = trx_reg_bit_read(SR_RX_RPC_EN); + break; + + case RX_AUTO_ACK: + *paramValue = trx_reg_bit_read(SR_AACK_DIS_ACK); + break; + + case RX_RESERVED_FRAME: + *paramValue = trx_reg_bit_read(SR_AACK_UPLD_RES_FT); + break; + + case FILTER_RESERVED_FRAME: + *paramValue = trx_reg_bit_read(SR_AACK_FLTR_RES_FT); + break; + + default: + return PHY_INVALID_PARAMETER; + break; + } + return PHY_SUCCESS; +} + + +/* + * \brief to configure the reduced power consumption mode + * + * \param rpc_mode_sel value to be written in the TRX_RPC bits + * + * \return PHY_SUCCESS if the register is written correctly + * PHY_FAILURE otherwise + */ + +PHY_Retval_t PHY_ConfigRxRPCMode(uint8_t rxRPCEnable) +{ + bool rxRPC = false; + if(rxRPCEnable != 0U) + {rxRPC = true;} + + /*configure the rpc modes*/ + trx_reg_bit_write(SR_RX_RPC_EN, (uint8_t)rxRPC); + /*check whether the configuration is done properly*/ + if (trx_reg_bit_read(SR_RX_RPC_EN) == (uint8_t)rxRPC) { + phy_info.phy_config_param.rxRPC = rxRPC; + return PHY_SUCCESS; + } else { + return PHY_FAILURE; + } + +} + +/* + * \brief Converts a register value to a dBm value + * + * \param reg_value TransmitPower register value, + * + * \param *dbm_value pointer to dbm_value + * + * \return PHY_SUCCESS or PHY_FAILURE based on conversion is done or not + */ + +PHY_Retval_t PHY_ConvertTxPwrRegValToDbm(uint8_t regValue, int8_t *dbmValue) +{ + if (regValue < sizeof(tx_pwr_table)) { + *dbmValue = (int8_t)*(&tx_pwr_table[regValue]); + return PHY_SUCCESS; + } else { + return PHY_FAILURE; + } +} + + + +/* + * \brief This function is called to get the base RSSI value for respective + * radios + * + * \return value of the base RSSI value + */ +int8_t PHY_GetRSSIBaseVal(void) +{ + return (RSSI_BASE_VAL_DBM); +} + +/** + * \brief the automatic acknowledgment from Transceiver after packet reception + * + * \param enableAACK true to enable the automatic + * acknowledgment after reception + * + * \return PHY_SUCCESS if configured correctly + * PHY_FAILURE otherwise + */ + + +PHY_Retval_t PHY_ConfigAutoAck(bool enableAACK) +{ + trx_reg_bit_write(SR_AACK_DIS_ACK, (uint8_t)enableAACK); + /*check the configuration */ + if (trx_reg_bit_read(SR_AACK_DIS_ACK) == (uint8_t)enableAACK) { + phy_info.phy_config_param.rxAutoAck = enableAACK; + return PHY_SUCCESS; + } else { + return PHY_FAILURE; + } +} + + +PHY_Retval_t PHY_ConfigReservedFrameFiltering(bool recReservedFrame, bool bypassFrameFilter ) +{ + trx_reg_bit_write(SR_AACK_UPLD_RES_FT, (uint8_t)recReservedFrame); + + trx_reg_bit_write(SR_AACK_FLTR_RES_FT, (uint8_t)bypassFrameFilter); + + /*check the configuration */ + if ((trx_reg_bit_read(SR_AACK_UPLD_RES_FT) == (uint8_t)recReservedFrame) && + (trx_reg_bit_read(SR_AACK_FLTR_RES_FT) == (uint8_t)bypassFrameFilter)) + { + phy_info.phy_config_param.reservedFrameFiltering = bypassFrameFilter; + phy_info.phy_config_param.rxReservedFrame = recReservedFrame; + return PHY_SUCCESS; + } else { + return PHY_FAILURE; + } + + +} + + +/* + * \brief to read a particular range of transceiver registers + * + * \param reg_addr address of the transceiver register to be written + * \param value value to be written in the register + * + * \return PHY_SUCCESS if the register is written correctly + * MAC_INVALID_PARAMETER if the reg_addr is out of range + */ + +PHY_Retval_t tal_dump_registers(uint16_t start_addr, uint16_t end_addr, + uint8_t *value) +{ + uint16_t addr; + int8_t length; + + /*check start and end address, return invalid parameter if out of range + **/ + + if (start_addr > 0x3FU || end_addr > 0x3FU) { + return PHY_INVALID_PARAMETER; + } + + int16_t temp_length = (end_addr - start_addr); + length = (int8_t)(temp_length); + if (length < 0) { + /* return invalid parameter if start and end addresses are not + * in order*/ + return PHY_INVALID_PARAMETER; + } else { + /* Read and store the values in input address*/ + for (addr = start_addr; addr <= end_addr; addr++) { + *value = trx_reg_read((uint8_t)addr); + value++; + } + return PHY_SUCCESS; + } +} + + +/* EOF */ diff --git a/driver/software/RF233/phy/at86rf233/src/phy_irq_handler.c b/driver/software/RF233/phy/at86rf233/src/phy_irq_handler.c new file mode 100644 index 0000000..1d3f180 --- /dev/null +++ b/driver/software/RF233/phy/at86rf233/src/phy_irq_handler.c @@ -0,0 +1,130 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* === INCLUDES ============================================================ */ + +#include +#include +#include +#include "../../../pal/inc/pal.h" +#include "../../../phy/inc/phy.h" +#include "../../../phy/inc/ieee_phy_const.h" +#include "../../../resources/buffer/inc/bmm.h" +#include "../../../resources/queue/inc/qmm.h" +#include "../../../phy/at86rf/inc/phy_irq_handler.h" +#include "../../at86rf/inc/phy_rx.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../../phy/at86rf/inc/phy_internal.h" +#include "../../../phy/inc/phy_constants.h" +#include "../../at86rf/inc/phy_tx.h" +#include "../../../phy/at86rf/inc/phy_trx_reg_access.h" +#include "../../../phy/inc/phy_tasks.h" + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* === GLOBALS ============================================================= */ + +/* === PROTOTYPES ========================================================== */ + +/* === IMPLEMENTATION ====================================================== */ + +/* + * \brief Transceiver interrupt handler + * + * This function handles the transceiver generated interrupts. + */ +void trx_irq_handler_cb(void) +{ + trx_irq_reason_t trx_irq_cause; + + trx_irq_cause = (trx_irq_reason_t) trx_reg_read(RG_IRQ_STATUS); + + + if ((bool)((uint8_t)trx_irq_cause & (uint8_t)TRX_IRQ_4_CCA_ED_DONE)) { + if (phy_info.tal_state == PHY_ED_RUNNING){ + trx_ed_irq_handler_cb(); + } + + else if (phy_info.tal_trx_status == TRX_SLEEP ){ + trx_irq_awake_handler_cb(); + } + else{ + /*DO NOTHING*/ + } + + } + else if ((bool)((uint8_t)trx_irq_cause & (uint8_t)TRX_IRQ_3_TRX_END)) { + /* + * TRX_END reason depends on if the trx is currently used for + * transmission or reception. + */ + + if (phy_info.tal_state == PHY_TX_AUTO) + { + /* Get the result and push it to the queue. */ + if ((bool)((uint8_t)trx_irq_cause & (uint8_t)TRX_IRQ_6_TRX_UR)) { + handle_tx_end_irq(true); /* see tal_tx.c */ + } else { + handle_tx_end_irq(false); /* see tal_tx.c */ + } + } else { /* Other tal_state than TAL_TX_... */ + /* Handle rx interrupt. */ + handle_received_frame_irq(); /* see tal_rx.c */ + } + } + else{ + /*DO NOTHING*/ + } +} /* trx_irq_handler_cb() */ + + +/* + * \brief Transceiver interrupt handler for awake end IRQ + * + * This function handles the transceiver awake end interrupt. + */ +void trx_irq_awake_handler_cb(void) +{ + + /* Set the wake-up flag. */ + phy_info.tal_awake_end_flag = true; + trx_reg_write(RG_IRQ_MASK, (uint8_t)TRX_IRQ_DEFAULT); + +} + + +void EIC_interrupt_cb(uintptr_t context) +{ + + TAL_PostTask(true); + +} + + + + +/* EOF */ diff --git a/driver/software/RF233/phy/at86rf233/src/phy_pib.c b/driver/software/RF233/phy/at86rf233/src/phy_pib.c new file mode 100644 index 0000000..8df0a5a --- /dev/null +++ b/driver/software/RF233/phy/at86rf233/src/phy_pib.c @@ -0,0 +1,748 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* === INCLUDES ============================================================ */ +#include +#include +#include +#include "../../../phy/inc/phy.h" +#include "../../../phy/inc/ieee_phy_const.h" +#include "../../../phy/inc/phy_constants.h" +#include "../../at86rf/inc/phy_pib.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../../phy/at86rf/inc/phy_internal.h" + +/** + * \addtogroup group_tal_pib_233 + * @{ + */ + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + + + +/* + * Default translation table converting register values to power levels (dBm). + */ +const int8_t tx_pwr_table[16] = { + 4, /* 4 */ + 3, /* 3.7 */ + 3, /* 3.4 */ + 3, /* 3 */ + 3, /* 2.5 */ + 2, /* 2 */ + 1, /* 1 */ + 0, /* 0 */ + -1, /* -1 */ + -2, /* -2 */ + -3, /* -3 */ + -4, /* -4 */ + -6, /* -6 */ + -8, /* -8 */ + -12, /* -12 */ + -17, /* -17 */ +}; + + + +/* === GLOBALS ============================================================= */ + +/* === PROTOTYPES ========================================================== */ + + +static uint8_t limit_tx_pwr(uint8_t curr_transmit_power); + +uint8_t convert_phyTransmitPower_to_reg_value(uint8_t phyTransmitPower_value); + +#ifdef HIGH_DATA_RATE_SUPPORT +static bool apply_channel_page_configuration(uint8_t ch_page); +#endif + + + +/* ! @} */ +/* === IMPLEMENTATION ====================================================== */ + +/* + * \brief Initialize the TAL PIB + * + * This function initializes the TAL information base attributes + * to their default values. + */ +void init_tal_pib(void) +{ + tal_pib.MaxCSMABackoffs = PHY_MAX_CSMA_BACKOFFS_DEFAULT; + tal_pib.MinBE = PHY_MINBE_DEFAULT; + tal_pib.PANId = PHY_PANID_BC_DEFAULT; + tal_pib.ShortAddress = PHY_SHORT_ADDRESS_DEFAULT; + tal_pib.CurrentChannel = PHY_CURRENT_CHANNEL_DEFAULT; + tal_pib.SupportedChannels = TRX_SUPPORTED_CHANNELS; + tal_pib.CurrentPage = PHY_CURRENT_PAGE_DEFAULT; + tal_pib.MaxFrameDuration = PHY_MAX_FRAME_DURATION_DEFAULT; + tal_pib.SHRDuration = PHY_SHR_DURATION_DEFAULT; + tal_pib.SymbolsPerOctet = PHY_SYMBOLS_PER_OCTET_DEFAULT; + tal_pib.MaxBE = PHY_MAXBE_DEFAULT; + tal_pib.MaxFrameRetries = PHY_MAXFRAMERETRIES_DEFAULT; + tal_pib.TransmitPower = limit_tx_pwr(PHY_TRANSMIT_POWER_DEFAULT); + tal_pib.CCAMode = (uint8_t)PHY_CCA_MODE_DEFAULT; + tal_pib.PrivatePanCoordinator = PHY_PAN_COORDINATOR_DEFAULT; + +#ifdef PROMISCUOUS_MODE + tal_pib.PromiscuousMode = PHY_PIB_PROMISCUOUS_MODE_DEFAULT; +#endif +} + +/* + * \brief Write all shadow PIB variables to the transceiver + * + * This function writes all shadow PIB variables to the transceiver. + * It is assumed that the radio does not sleep. + */ +void write_all_tal_pib_to_trx(void) +{ + uint8_t *ptr_to_reg; + + ptr_to_reg = (uint8_t *)&tal_pib.PANId; + for (uint8_t i = 0; i < 2; i++) { + trx_reg_write((RG_PAN_ID_0 + i), *ptr_to_reg); + ptr_to_reg++; + } + + ptr_to_reg = (uint8_t *)&tal_pib.IeeeAddress; + for (uint8_t i = 0; i < 8; i++) { + trx_reg_write((RG_IEEE_ADDR_0 + i), *ptr_to_reg); + ptr_to_reg++; + } + + ptr_to_reg = (uint8_t *)&tal_pib.ShortAddress; + for (uint8_t i = 0; i < 2; i++) { + trx_reg_write((RG_SHORT_ADDR_0 + i), *ptr_to_reg); + ptr_to_reg++; + } + + /* configure TX_ARET; CSMA and CCA */ + trx_reg_bit_write(SR_CCA_MODE, tal_pib.CCAMode); + trx_reg_bit_write(SR_MIN_BE, tal_pib.MinBE); + + trx_reg_bit_write(SR_AACK_I_AM_COORD, tal_pib.PrivatePanCoordinator); + + /* set phy parameter */ + trx_reg_bit_write(SR_MAX_BE, tal_pib.MaxBE); + +#ifdef HIGH_DATA_RATE_SUPPORT + apply_channel_page_configuration(tal_pib.CurrentPage); +#endif + + trx_reg_bit_write(SR_CHANNEL, tal_pib.CurrentChannel); + + + + { + uint8_t reg_value; + + reg_value = convert_phyTransmitPower_to_reg_value( + tal_pib.TransmitPower); + trx_reg_bit_write(SR_TX_PWR, reg_value); + } + +#ifdef PROMISCUOUS_MODE + if (tal_pib.PromiscuousMode) { + (void)set_trx_state(CMD_RX_ON); + } +#endif +} + +/* + * \brief Gets a TAL PIB attribute + * + * This function is called to retrieve the transceiver information base + * attributes. + * + * \param[in] attribute TAL infobase attribute ID + * \param[out] value TAL infobase attribute value + * + * \return MAC_UNSUPPORTED_ATTRIBUTE if the TAL infobase attribute is not found + * MAC_SUCCESS otherwise + */ + +PHY_Retval_t PHY_PibGet(uint8_t attribute, uint8_t *value) +{ + switch (attribute) { + case macMaxCSMABackoffs: + *value = tal_pib.MaxCSMABackoffs; + break; + + case macMinBE: + *value = tal_pib.MinBE; + break; + + case macPANId: + *(uint16_t *)value = tal_pib.PANId; + break; + +#ifdef PROMISCUOUS_MODE + case macPromiscuousMode: + *(uint16_t *)value = tal_pib.PromiscuousMode; + break; +#endif + case macShortAddress: + *(uint16_t *)value = tal_pib.ShortAddress; + break; + + case phyCurrentChannel: + *value = tal_pib.CurrentChannel; + break; + + case phyChannelsSupported: + *(uint32_t *)value = tal_pib.SupportedChannels; + break; + + case phyTransmitPower: + *value = tal_pib.TransmitPower; + break; + + case phyCCAMode: + *value = tal_pib.CCAMode; + break; + + case phyCurrentPage: + *value = tal_pib.CurrentPage; + break; + + case phyMaxFrameDuration: + *(uint16_t *)value = tal_pib.MaxFrameDuration; + break; + + case phySymbolsPerOctet: + *value = tal_pib.SymbolsPerOctet; + break; + + case phySHRDuration: + *value = tal_pib.SHRDuration; + break; + + case macMaxBE: + *value = tal_pib.MaxBE; + break; + + case macMaxFrameRetries: + *value = tal_pib.MaxFrameRetries; + break; + + case macIeeeAddress: + (void)memcpy((uint8_t *)value, (uint8_t *)&tal_pib.IeeeAddress, + sizeof(tal_pib.IeeeAddress)); + break; + + + case mac_i_pan_coordinator: + *(bool *)value = tal_pib.PrivatePanCoordinator; + break; + + case macAckWaitDuration: + + /* + * AT86RF233 does not support changing this value w.r.t. + * compliance operation. + */ + return PHY_UNSUPPORTED_ATTRIBUTE; + + default: + /* Invalid attribute id */ + return PHY_UNSUPPORTED_ATTRIBUTE; + break; + } + + return PHY_SUCCESS; +} /* tal_pib_get() */ + + + +/* + * \brief Sets a TAL PIB attribute + * + * This function is called to set the transceiver information base + * attributes. + * + * \param attribute TAL infobase attribute ID + * \param value TAL infobase attribute value to be set + * + * \return MAC_UNSUPPORTED_ATTRIBUTE if the TAL info base attribute is not found + * TAL_BUSY if the TAL is not in TAL_IDLE state. An exception is + * macBeaconTxTime which can be accepted by TAL even if TAL is not + * in TAL_IDLE state. + * PHY_SUCCESS if the attempt to set the PIB attribute was successful + * TAL_TRX_ASLEEP if trx is in SLEEP mode and access to trx is required + */ +PHY_Retval_t PHY_PibSet(uint8_t attribute, PibValue_t *value) +{ + /* + * Do not allow any changes while ED or TX is done. + * We allow changes during RX, but it's on the user's own risk. + */ + if (phy_info.tal_state == PHY_ED_RUNNING) { + return PHY_BUSY; + } + + /* + * Distinguish between PIBs that need to be changed in trx directly + * and those that are simple variable udpates. + * Ensure that the transceiver is not in SLEEP. + * If it is in SLEEP, change it to TRX_OFF. + */ + + switch (attribute) { + case macMaxFrameRetries: + + /* + * The new PIB value is not immediately written to the + * transceiver. This is done on a frame-by-frame base. + */ + tal_pib.MaxFrameRetries = value->pib_value_8bit; + break; + + case macMaxCSMABackoffs: + + /* + * The new PIB value is not immediately written to the + * transceiver. This is done on a frame-by-frame base. + */ + tal_pib.MaxCSMABackoffs = value->pib_value_8bit; + break; + +#ifdef PROMISCUOUS_MODE + case macPromiscuousMode: + tal_pib.PromiscuousMode = value->pib_value_8bit; + if (tal_pib.PromiscuousMode) { + PHY_TrxWakeup(); + + /* Check if receive buffer is available or queue is not + * full. */ + if (NULL == tal_rx_buffer) { + (void)set_trx_state(CMD_PLL_ON); + phy_info.tal_rx_on_required = true; + } else { + (void)set_trx_state(CMD_RX_ON); + } + } else { + (void)set_trx_state(CMD_TRX_OFF); + phy_info.tal_rx_on_required = false; + } + break; +#endif + + default: + + /* + * Following PIBs require access to trx. + * Therefore trx must be at least in TRX_OFF. + */ + + if (phy_info.tal_trx_status == TRX_SLEEP) { + /* While trx is in SLEEP, register cannot be accessed. + **/ + return PHY_TRX_ASLEEP; + } + + switch (attribute) { + case macMinBE: + tal_pib.MinBE = value->pib_value_8bit; + +#ifndef REDUCED_PARAM_CHECK + + /* + * macMinBE must not be larger than macMaxBE or + * calculation + * of macMaxFrameWaitTotalTime will fail. + */ + if (tal_pib.MinBE > tal_pib.MaxBE) { + tal_pib.MinBE = tal_pib.MaxBE; + } +#endif /* REDUCED_PARAM_CHECK */ + + trx_reg_bit_write(SR_MIN_BE, tal_pib.MinBE); + break; + + case macPANId: + tal_pib.PANId = value->pib_value_16bit; + { + uint8_t *ptr_pan; + ptr_pan = (uint8_t *)&tal_pib.PANId; + for (uint8_t iter = 0; iter < 2U; iter++) { + trx_reg_write((RG_PAN_ID_0 + iter), + *ptr_pan); + ptr_pan++; + } + } + break; + + case macShortAddress: + tal_pib.ShortAddress = value->pib_value_16bit; + { + uint8_t *ptr_shrt; + ptr_shrt = (uint8_t *)&tal_pib.ShortAddress; + for (uint8_t iter = 0; iter < 2U; iter++) { + trx_reg_write((RG_SHORT_ADDR_0 + iter), + *ptr_shrt); + ptr_shrt++; + } + } + break; + + case phyCurrentChannel: + if (phy_info.tal_state != PHY_IDLE) { + return PHY_BUSY; + } + + if ((bool)((uint32_t)TRX_SUPPORTED_CHANNELS & + ((uint32_t)0x01 << + value->pib_value_8bit))) { + tal_trx_status_t previous_trx_status = TRX_OFF; + + /* + * Set trx to "soft" off avoiding that ongoing + * transaction (e.g. ACK) are interrupted. + */ + if (phy_info.tal_trx_status != TRX_OFF) { + previous_trx_status = RX_AACK_ON; /* any + * + * + * + *other + * + * + * + *than + * + * + * + *TRX_OFF + * + * + * + *state + **/ + do { + /* set TRX_OFF until it could be + * set; + * trx might be busy */ + } while (set_trx_state(CMD_TRX_OFF) != + TRX_OFF); + } + + tal_pib.CurrentChannel = value->pib_value_8bit; + trx_reg_bit_write(SR_CHANNEL, + tal_pib.CurrentChannel); + + + + + /* Re-store previous trx state */ + if (previous_trx_status != TRX_OFF) { + /* Set to default state */ + (void)set_trx_state(CMD_RX_AACK_ON); + + } + } else { + return PHY_INVALID_PARAMETER; + } + + break; + + case phyCurrentPage: +#ifdef HIGH_DATA_RATE_SUPPORT + if (phy_info.tal_state != PHY_IDLE) { + return PHY_BUSY; + } else { + uint8_t page; + tal_trx_status_t previous_trx_status = TRX_OFF; + bool ret_val; + + /* + * Changing the channel, channel page or + * modulation + * requires that TRX is in TRX_OFF. + * Store current trx state and return to default + * state + * after channel page has been set. + */ + if (phy_info.tal_trx_status != TRX_OFF) { + previous_trx_status = RX_AACK_ON; /* any + * + * + * + *other + * + * + * + *than + * + * + * + *TRX_OFF + * + * + * + *state + **/ + do { + /* set TRX_OFF until it could be + * set; + * trx might be busy */ + } while (set_trx_state(CMD_TRX_OFF) != + TRX_OFF); + } + + page = value->pib_value_8bit; + + ret_val + = apply_channel_page_configuration(page); + + if (previous_trx_status != TRX_OFF) { + /* Set to default state */ + (void)set_trx_state(CMD_RX_AACK_ON); + + + } + + if (ret_val) { + tal_pib.CurrentPage = page; + } else { + return PHY_INVALID_PARAMETER; + } + } + +#else + if (phy_info.tal_state != PHY_IDLE) { + return PHY_BUSY; + } else { + uint8_t page; + + page = value->pib_value_8bit; + if (page != 0U) { + return PHY_INVALID_PARAMETER; + } + } +#endif /* #ifdef HIGH_DATA_RATE_SUPPORT */ + break; + + case macMaxBE: + tal_pib.MaxBE = value->pib_value_8bit; +#ifndef REDUCED_PARAM_CHECK + + /* + * macMinBE must not be larger than macMaxBE or + * calculation + * of macMaxFrameWaitTotalTime will fail. + */ + if (tal_pib.MaxBE < tal_pib.MinBE) { + tal_pib.MinBE = tal_pib.MaxBE; + } +#endif /* REDUCED_PARAM_CHECK */ + trx_reg_bit_write(SR_MAX_BE, tal_pib.MaxBE); + break; + + case phyTransmitPower: + tal_pib.TransmitPower = value->pib_value_8bit; + { + /* Limit tal_pib.TransmitPower to max/min trx + * values */ + tal_pib.TransmitPower = limit_tx_pwr( + tal_pib.TransmitPower); + uint8_t reg_value + = convert_phyTransmitPower_to_reg_value( + tal_pib.TransmitPower); + trx_reg_bit_write(SR_TX_PWR, reg_value); + + + + } + break; + + case phyCCAMode: + tal_pib.CCAMode = value->pib_value_8bit; + trx_reg_bit_write(SR_CCA_MODE, tal_pib.CCAMode); + break; + + case macIeeeAddress: + tal_pib.IeeeAddress = value->pib_value_64bit; + { + uint8_t *ptr; + ptr = (uint8_t *)&tal_pib.IeeeAddress; + for (uint8_t iter = 0; iter < 8U; iter++) { + trx_reg_write((RG_IEEE_ADDR_0 + iter), + *ptr); + ptr++; + } + } + break; + + case mac_i_pan_coordinator: + tal_pib.PrivatePanCoordinator = value->pib_value_bool; + trx_reg_bit_write(SR_AACK_I_AM_COORD, + tal_pib.PrivatePanCoordinator); + break; + + case macAckWaitDuration: + + /* + * AT86RF233 does not support changing this value w.r.t. + * compliance operation. + * The ACK timing can be reduced to 2 symbols using TFA + * function. + */ + return PHY_UNSUPPORTED_ATTRIBUTE; + break; + + default: + return PHY_UNSUPPORTED_ATTRIBUTE; + break; + } + + break; /* end of 'default' from 'switch (attribute)' */ + } + return PHY_SUCCESS; +} /* tal_pib_set() */ + +/** + * \brief Limit the phyTransmitPower to the trx limits + * + * \param phyTransmitPower phyTransmitPower value + * + * \return limited tal_pib_TransmitPower + */ + +static uint8_t limit_tx_pwr(uint8_t curr_transmit_power) +{ + uint8_t ret_val = curr_transmit_power; + int8_t dbm_value; + + dbm_value = (int8_t)CONV_phyTransmitPower_TO_DBM(curr_transmit_power); + if (dbm_value > (int8_t)*(&tx_pwr_table[0])) { + dbm_value = (int8_t)*(&tx_pwr_table[0]); + ret_val = (uint8_t)CONV_DBM_TO_phyTransmitPower(dbm_value); + } else if (dbm_value < + (int8_t)*(&tx_pwr_table[sizeof(tx_pwr_table) + - 1U])) { + dbm_value + = (int8_t)*(&tx_pwr_table[sizeof( + tx_pwr_table) + - 1U]); + ret_val = (uint8_t)CONV_DBM_TO_phyTransmitPower(dbm_value); + }else{ + /*DO NOTHING*/ + } + + return (ret_val | TX_PWR_TOLERANCE); +} + +/** + * \brief Converts a phyTransmitPower value to a register value + * + * \param phyTransmitPower_value phyTransmitPower value + * + * \return register value + */ +uint8_t convert_phyTransmitPower_to_reg_value(uint8_t phyTransmitPower_value) +{ + int8_t dbm_value; + uint8_t index; + int8_t trx_tx_level; + + dbm_value = CONV_phyTransmitPower_TO_DBM(phyTransmitPower_value); + + /* Compare to the register value to identify the value that matches. */ + for (index = 0; index < sizeof(tx_pwr_table); index++) { + trx_tx_level = (int8_t)*(&tx_pwr_table[index]); + if (trx_tx_level <= dbm_value) { + if (trx_tx_level < dbm_value) { + return (index - 1U); + } + + return index; + } + } + + /* This code should never be reached. */ + return 0; +} + + +#ifdef HIGH_DATA_RATE_SUPPORT + +/** + * \brief Apply channel page configuartion to transceiver + * + * \param ch_page Channel page + * + * \return true if changes could be applied else false + */ +static bool apply_channel_page_configuration(uint8_t ch_page) +{ + /* + * Before updating the transceiver a number of TAL PIB attributes need + * to be updated depending on the channel page. + */ + tal_pib.MaxFrameDuration = MAX_FRAME_DURATION; + tal_pib.SHRDuration = NO_OF_SYMBOLS_PREAMBLE_SFD; + tal_pib.SymbolsPerOctet = SYMBOLS_PER_OCTET; + + switch (ch_page) { + case 0: /* compliant O-QPSK */ + trx_reg_bit_write(SR_OQPSK_DATA_RATE, ALTRATE_250_KBPS); + /* Apply compliant ACK timing */ + trx_reg_bit_write(SR_AACK_ACK_TIME, ACK_TIME_12_SYMBOLS); + break; + + case 2: /* non-compliant OQPSK mode 1 */ + trx_reg_bit_write(SR_OQPSK_DATA_RATE, ALTRATE_500_KBPS); + /* Apply reduced ACK timing */ + trx_reg_bit_write(SR_AACK_ACK_TIME, ACK_TIME_2_SYMBOLS); + break; + + case 16: /* non-compliant OQPSK mode 2 */ + trx_reg_bit_write(SR_OQPSK_DATA_RATE, ALTRATE_1_MBPS); + /* Apply reduced ACK timing */ + trx_reg_bit_write(SR_AACK_ACK_TIME, ACK_TIME_2_SYMBOLS); + break; + + case 17: /* non-compliant OQPSK mode 3 */ + trx_reg_bit_write(SR_OQPSK_DATA_RATE, ALTRATE_2_MBPS); + /* Apply reduced ACK timing */ + trx_reg_bit_write(SR_AACK_ACK_TIME, ACK_TIME_2_SYMBOLS); + break; + + default: + return false; + } + + return true; +} + +#endif + +/* EOF */ diff --git a/driver/software/RF233/phy/at86rf233/src/phy_pwr_mgmt.c b/driver/software/RF233/phy/at86rf233/src/phy_pwr_mgmt.c new file mode 100644 index 0000000..756322f --- /dev/null +++ b/driver/software/RF233/phy/at86rf233/src/phy_pwr_mgmt.c @@ -0,0 +1,174 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* === INCLUDES ============================================================ */ + +#include +#include +#include + +#include "../../../pal/inc/pal.h" +#include "../../../phy/inc/phy.h" +#include "../../../phy/inc/ieee_phy_const.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../../phy/at86rf/inc/phy_internal.h" + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* === GLOBALS ============================================================= */ + +/* === PROTOTYPES ========================================================== */ + +/* === IMPLEMENTATION ====================================================== */ + +/* + * \brief Sets the transceiver to sleep + * + * This function sets the transceiver to sleep state. + * + * \param mode Defines sleep mode of transceiver: SLEEP_MODE_1 or + * DEEP_SLEEP_MODE) + * + * \return TAL_BUSY - The transceiver is busy in TX or RX + * MAC_SUCCESS - The transceiver is put to sleep + * TAL_TRX_ASLEEP - The transceiver is already asleep; + * either in SLEEP or in DEEP_SLEEP + * MAC_INVALID_PARAMETER - The specified sleep mode is not supported + */ +PHY_Retval_t PHY_TrxSleep(PHY_SleepMode_t mode) +{ + tal_trx_status_t trx_status; + +#ifndef ENABLE_DEEP_SLEEP + if (SLEEP_MODE_1 != mode) +#else + if ((SLEEP_MODE_1 != mode) && (DEEP_SLEEP_MODE != mode)) +#endif + { + return PHY_INVALID_PARAMETER; + } + + +#ifdef ENABLE_DEEP_SLEEP + if (((phy_info.tal_trx_status == TRX_SLEEP) && (mode == SLEEP_MODE_1)) || \ + ((phy_info.tal_trx_status == TRX_DEEP_SLEEP) && + (mode == DEEP_SLEEP_MODE))) +#else + if (phy_info.tal_trx_status == TRX_SLEEP) +#endif + { + return PHY_TRX_ASLEEP; + } + + /* Device can be put to sleep only when the TAL is in IDLE state. */ + if (PHY_IDLE != phy_info.tal_state) { + return PHY_BUSY; + } + + phy_info.tal_rx_on_required = false; + + /* + * First set trx to TRX_OFF. + * If trx is busy, like ACK transmission, do not interrupt it. + */ + do { + trx_status = set_trx_state(CMD_TRX_OFF); + } while (trx_status != TRX_OFF); + + +#ifndef ENABLE_DEEP_SLEEP + trx_status = set_trx_state(CMD_SLEEP); +#else + if (mode == SLEEP_MODE_1) { + trx_status = set_trx_state(CMD_SLEEP); + } else { /* deep sleep */ + trx_status = set_trx_state(CMD_DEEP_SLEEP); + } +#endif + +#ifndef ENABLE_DEEP_SLEEP + if (trx_status == TRX_SLEEP) +#else + if ((trx_status == TRX_SLEEP) || (trx_status == TRX_DEEP_SLEEP)) +#endif + { + return PHY_SUCCESS; + } else { + /* State could not be set due to TAL_BUSY state. */ + return PHY_BUSY; + } +} + +/* + * \brief Wakes up the transceiver from sleep + * + * This function awakes the transceiver from sleep state. + * + * \return TAL_TRX_AWAKE - The transceiver is already awake + * MAC_SUCCESS - The transceiver is woken up from sleep + * FAILURE - The transceiver did not wake-up from sleep + */ +PHY_Retval_t PHY_TrxWakeup(void) +{ + tal_trx_status_t trx_status; + +#ifndef ENABLE_DEEP_SLEEP + if (phy_info.tal_trx_status != TRX_SLEEP) +#else + if ((phy_info.tal_trx_status != TRX_SLEEP) && (phy_info.tal_trx_status != TRX_DEEP_SLEEP)) +#endif + { + return PHY_TRX_AWAKE; + } + + + trx_status = set_trx_state(CMD_TRX_OFF); + + if (trx_status == TRX_OFF) { + return PHY_SUCCESS; + } else { + return PHY_FAILURE; + } +} + + + + +void tal_trx_wakeup(void) +{ + /* The pending transceiver interrupts on the microcontroller are + * cleared. */ + /* Clear existing interrupts */ + (void)trx_reg_read(RG_IRQ_STATUS); + /* Leave trx sleep mode. */ + TRX_SLP_TR_LOW(); + /* Poll wake-up interrupt flag until set within ISR. */ + while (!phy_info.tal_awake_end_flag) { + } + +} +/* EOF */ diff --git a/driver/software/RF233/phy/at86rf233/src/phy_rx.c b/driver/software/RF233/phy/at86rf233/src/phy_rx.c new file mode 100644 index 0000000..5615533 --- /dev/null +++ b/driver/software/RF233/phy/at86rf233/src/phy_rx.c @@ -0,0 +1,377 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* === INCLUDES ============================================================ */ + +#include +#include +#include + +#include "../../../pal/inc/pal.h" +#include "../../../phy/inc/ieee_phy_const.h" +#include "../../../resources/buffer/inc/bmm.h" +#include "../../../resources/queue/inc/qmm.h" +#include "../../../phy/inc/phy_constants.h" +#include "../../at86rf/inc/phy_pib.h" +#include "../../at86rf/inc/phy_irq_handler.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../at86rf/inc/phy_rx.h" +#include "../../../phy/at86rf/inc/phy_internal.h" +#include "../../../phy/inc/phy_tasks.h" + + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* Constant defines for the LQI calculation */ +#define ED_THRESHOLD (60) +#define ED_MAX (-RSSI_BASE_VAL_DBM - ED_THRESHOLD) +#define LQI_MAX (3) + +#define ED_LEVEL_MAX_REG_VALUE (84) +#define ED_LEVEL_MULTIPLIER (255.0 / ED_LEVEL_MAX_REG_VALUE) + +#define US_PER_OCTECT (32) + + +/* === GLOBALS ============================================================= */ + +/* === PROTOTYPES ========================================================== */ + +#ifndef TRX_REG_RAW_VALUE +#ifdef RSSI_TO_LQI_MAPPING +static inline uint8_t normalize_lqi(uint8_t ed_value); + +#else +static inline uint8_t normalize_lqi(uint8_t lqi, uint8_t ed_value); + +#endif +#endif /* #ifndef TRX_REG_RAW_VALUE */ + +/* === IMPLEMENTATION ====================================================== */ + +/* + * \brief Handle received frame interrupt + * + * This function handles transceiver interrupts for received frames and + * uploads the frames from the trx. + */ +void handle_received_frame_irq(void) +{ + /* Actual frame length of received frame. */ + uint8_t phy_frame_len; + /* Extended frame length appended by LQI and ED. */ + uint8_t ext_frame_length; + PHY_FrameInfo_t *receive_frame; + uint8_t *frame_ptr; + + if (tal_rx_buffer == NULL) { + + /* + * Although the buffer protection mode is enabled and the + * receiver has + * been switched to PLL_ON, the next incoming frame was faster. + * It cannot be handled and is discarded. Reading anything from + * the + * frame resets the buffer protection mode. + */ + uint8_t dummy; + trx_frame_read(&dummy, 1); + return; + } + + receive_frame = (PHY_FrameInfo_t *)BMM_BUFFER_POINTER(tal_rx_buffer); + +#ifdef PROMISCUOUS_MODE + if (tal_pib.PromiscuousMode) { + /* Check for valid FCS */ + if (trx_reg_bit_read(SR_RX_CRC_VALID) == CRC16_NOT_VALID) { + return; + } + } +#endif + +#if (defined ENABLE_TRX_SRAM) || defined(ENABLE_TRX_SRAM_READ) + /* Use SRAM read to keep rx safe mode armed. */ + trx_sram_read(0x00, &phy_frame_len, LENGTH_FIELD_LEN); /* 0x00: SRAM + * offset + * address */ +#else + + /* Get frame length from transceiver. */ + trx_frame_read(&phy_frame_len, LENGTH_FIELD_LEN); + +#endif + + phy_info.last_frame_length = phy_frame_len; + /* Check for valid frame length. */ + if (phy_frame_len > 127U) { + return; + } + + /* + * The PHY header is also included in the frame (length field), hence + * the frame length + * is incremented. + * In addition to that, the LQI and ED value are uploaded, too. + */ + // phy_frame_len = 1(length byte(PHR))+9((MHR)+ 1(seq no.)+(length of data) + ext_frame_length = phy_frame_len + LENGTH_FIELD_LEN + LQI_LEN + + ED_VAL_LEN; + + /* Update payload pointer to store received frame. */ + frame_ptr = (uint8_t *)receive_frame + LARGE_BUFFER_SIZE - + ext_frame_length ; + + /* + * Note: The following code is different from single chip + * transceivers, since reading the frame via SPI contains the length + * field + * in the first octet. RF233's frame buffer includes ED value too. + */ + trx_frame_read(frame_ptr, + LENGTH_FIELD_LEN + phy_frame_len + LQI_LEN + ED_VAL_LEN); + + + receive_frame->mpdu = frame_ptr; + + + + + /* Append received frame to incoming_frame_queue and get new rx buffer. + **/ + qmm_queue_append(&tal_incoming_frame_queue, tal_rx_buffer); + + /* The previous buffer is eaten up and a new buffer is not assigned yet. + **/ + tal_rx_buffer = bmm_buffer_alloc(LARGE_BUFFER_SIZE); +/* Check if receive buffer is available */ + if (NULL == tal_rx_buffer) { + /* + * Turn off the receiver until a buffer is available again. + * tal_task() will take care of eventually reactivating it. + * Due to ongoing ACK transmission do not force to switch it + * off. + */ + (void)set_trx_state(CMD_PLL_ON); + phy_info.tal_rx_on_required = true; + + } + PHY_PostTask(false); +} + +/* + * \brief Parses received frame and create the PHY_FrameInfo_t structure + * + * This function parses the received frame and creates the PHY_FrameInfo_t + * structure to be sent to the MAC as a parameter of tal_rx_frame_cb(). + * + * \param buf Pointer to the buffer containing the received frame + */ + +void process_incoming_frame(buffer_t *buf_ptr) +{ + +#ifndef TRX_REG_RAW_VALUE + uint8_t frame_len; + uint8_t *frame_ptr; + uint8_t ed_level; + uint8_t lqi; +#endif + + PHY_FrameInfo_t *receive_frame + = (PHY_FrameInfo_t *)BMM_BUFFER_POINTER(buf_ptr); + + + /* The frame is present towards the end of the buffer. */ + +#ifndef TRX_REG_RAW_VALUE + + /* + * Store the last frame length for IFS handling. + * Substract LQI and length fields. + */ + frame_len = phy_info.last_frame_length = receive_frame->mpdu[0]; + +#else + phy_info.last_frame_length = receive_frame->mpdu[0]; +#endif + +#ifdef PROMISCUOUS_MODE + if (tal_pib.PromiscuousMode) { +#ifndef TRX_REG_RAW_VALUE + frame_ptr = &(receive_frame->mpdu[frame_len + LQI_LEN]); + + /* + * The LQI is stored after the FCS. + * The ED value is stored after the LQI. + */ + lqi = *frame_ptr++; + phy_info.last_pkt_lqi = lqi; + ed_level = *frame_ptr; + + /* + * The LQI normalization is done using the ED level measured + * during + * the frame reception. + */ +#ifdef RSSI_TO_LQI_MAPPING + lqi = normalize_lqi(ed_level); +#else + lqi = normalize_lqi(lqi, ed_level); +#endif + + /* Store normalized LQI value again. */ + frame_ptr--; + *frame_ptr = lqi; + phy_info.last_pkt_lqi = lqi; +#endif /* #ifndef TRX_REG_RAW_VALUE */ + + receive_frame->buffer_header = buf_ptr; + + /* The callback function implemented by MAC is invoked. */ + PHY_RxFrameCallback(receive_frame); + + return; + } +#endif /* #ifdef PROMISCUOUS_MODE */ + + + +#ifndef TRX_REG_RAW_VALUE + + /* + * The LQI is stored after the FCS. + * The ED value is stored after the LQI. + */ + frame_ptr = &(receive_frame->mpdu[frame_len + LQI_LEN]); + lqi = *frame_ptr++; + ed_level = *frame_ptr; + +// *frame_ptr = ed_level = phy_info.last_pkt_ed_level; + + /* + * The LQI normalization is done using the ED level measured during + * the frame reception. + */ +#ifdef RSSI_TO_LQI_MAPPING + lqi = normalize_lqi(ed_level); +#else + lqi = normalize_lqi(lqi, ed_level); +#endif + + /* Store normalized LQI value again. */ + frame_ptr--; + *frame_ptr = lqi; +#endif /* #ifndef TRX_REG_RAW_VALUE */ + + receive_frame->buffer_header = buf_ptr; + + /* The callback function implemented by MAC is invoked. */ + PHY_RxFrameCallback(receive_frame); + +} /* process_incoming_frame() */ + +#ifndef TRX_REG_RAW_VALUE +#ifdef RSSI_TO_LQI_MAPPING + +/** + * \brief Normalize LQI + * + * This function normalizes the LQI value based on the RSSI/ED value. + * + * \param ed_value Read ED value + * + * \return The calculated/normalized LQI value: ppduLinkQuality + */ +static inline uint8_t normalize_lqi(uint8_t ed_value) +{ + /* + * Scale ED result. + */ + if (ed_value > (ED_LEVEL_MAX_REG_VALUE - 1)) { + return 0xFF; + } else { + /* Scale ED value to span up to 0xFF. */ + return (uint8_t)(ed_value * ED_LEVEL_MULTIPLIER + 0.5); + } +} + +#else /* #ifdef RSSI_TO_LQI_MAPPING */ + +/** + * \brief Normalize LQI + * + * This function normalizes the LQI value based on the ED and + * the originally appended LQI value. + * + * \param lqi Measured LQI + * \param ed_value Read ED value + * + * \return The calculated LQI value: ppduLinkQuality + */ +static inline uint8_t normalize_lqi(uint8_t lqi, uint8_t ed_value) +{ + uint16_t link_quality; + uint8_t lqi_star; + uint8_t ed_max_val = (uint8_t)ED_MAX; + +#ifdef HIGH_DATA_RATE_SUPPORT + if (tal_pib.CurrentPage == 0) { +#endif + if (ed_value > ed_max_val) { + ed_value = ed_max_val; + } else if (ed_value == 0U) { + ed_value = 1; + }else{ + /*DO NOTHING*/ + } + + lqi_star = lqi >> 6U; + link_quality = (uint16_t)lqi_star * (uint16_t)ed_value * 255U / + (ed_max_val * LQI_MAX); + + if (link_quality > 255U) { + return 255; + } else { + return (uint8_t)link_quality; + } + +#ifdef HIGH_DATA_RATE_SUPPORT +} else { /* if (tal_pib.CurrentPage == 0) */ + /* High data rate modes do not provide a valid LQI value. */ + if (ed_value > ed_max_val) { + return 0xFF; + } else { + return (ed_value * (255U / ed_max_val)); + } +} +#endif +} +#endif /* #ifdef RSSI_TO_LQI_MAPPING */ +#endif /* #ifndef TRX_REG_RAW_VALUE */ + +/* EOF */ diff --git a/driver/software/RF233/phy/at86rf233/src/phy_rx_enable.c b/driver/software/RF233/phy/at86rf233/src/phy_rx_enable.c new file mode 100644 index 0000000..65fbacc --- /dev/null +++ b/driver/software/RF233/phy/at86rf233/src/phy_rx_enable.c @@ -0,0 +1,131 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* === INCLUDES ============================================================ */ + +#include +#include +#include +#include "../../../pal/inc/pal.h" +#include "../../at86rf/inc/phy_tx.h" +#include "../../../phy/inc/phy.h" +#include "../../../phy/inc/phy_constants.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../../resources/buffer/inc/bmm.h" +#include "../../../resources/queue/inc/qmm.h" +#include "../../at86rf/inc/phy_rx.h" +#include "../../../phy/at86rf/inc/phy_internal.h" +#include "../../../phy/inc/phy_tasks.h" + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* === GLOBALS ============================================================= */ + +/* === PROTOTYPES ========================================================== */ + +/* === IMPLEMENTATION ====================================================== */ + +/* + * \brief Switches receiver on or off + * + * This function switches the receiver on (PHY_RX_ON) or off (PHY_TRX_OFF). + * + * \param state New state of receiver + * + * \return TAL_BUSY if the TAL state machine cannot switch receiver on or off, + * TRX_OFF if receiver has been switched off, or + * RX_ON otherwise. + * + */ +PHY_TrxStatus_t PHY_RxEnable(PHY_TrxState_t state) +{ + + + /* + * Trx can only be enabled if TAL is not busy; + * i.e. if TAL is IDLE. + */ + if (PHY_IDLE != phy_info.tal_state) { + + return PHY_BUSY_TX; + + } + + if (state == PHY_STATE_TRX_OFF) { + /* + * If the rx needs to be switched off, we are not interested in + * a frame + * that is currently being received. + * This must not be a Forced TRX_OFF (CMD_FORCED_TRX_OFF) since + * this could + * corrupt an already outoing ACK frame. + */ + (void)set_trx_state(CMD_TRX_OFF); + phy_info.tal_rx_on_required = false; + return PHY_TRX_OFF; + } else { + if (NULL != tal_rx_buffer) { +#ifdef PROMISCUOUS_MODE + if (tal_pib.PromiscuousMode) { + (void)set_trx_state(CMD_RX_ON); + while(((uint8_t)tal_get_trx_status() & 0x1FU) != (uint8_t)RX_ON); + } else { + (void)set_trx_state(CMD_RX_AACK_ON); + while(((uint8_t)tal_get_trx_status() & 0x1FU) != (uint8_t)RX_AACK_ON) + { + /*WAIT*/ + } + } +#else /* Normal operation */ + (void)set_trx_state(CMD_RX_AACK_ON); + while(((uint8_t)tal_get_trx_status() & 0x1FU) != (uint8_t)RX_AACK_ON) + { + /*WAIT*/ + } +#endif /* PROMISCUOUS_MODE */ + + } else { + /* + * If no rx buffer is available, the corresponding + * information is stored and will be used by tal_task() + * to + * switch on the receiver later. + * + * Even if a receive buffer is not available, + * the TAL returns MAC_SUCCESS. The TAL will try to + * allocate a receive + * buffer as soon as possible and will switch on the + * receiver. + */ + phy_info.tal_rx_on_required = true; + PHY_PostTask(false); + } + return PHY_RX_ON; /* MAC layer assumes RX_ON as return value */ + } +} + +/* EOF */ diff --git a/driver/software/RF233/phy/at86rf233/src/phy_tx.c b/driver/software/RF233/phy/at86rf233/src/phy_tx.c new file mode 100644 index 0000000..a871bb7 --- /dev/null +++ b/driver/software/RF233/phy/at86rf233/src/phy_tx.c @@ -0,0 +1,351 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* === INCLUDES ============================================================ */ + +#include +#include +#include +#include "../../../pal/inc/pal.h" +#include "../../../phy/inc/phy.h" +#include "../../../phy/inc/ieee_phy_const.h" +#include "../../at86rf/inc/phy_pib.h" +#include "../../at86rf/inc/phy_irq_handler.h" +#include "../../../phy/inc/phy_constants.h" +#include "../../at86rf/inc/phy_tx.h" +#include "../../../resources/buffer/inc/bmm.h" +#include "../../../resources/queue/inc/qmm.h" +#include "../../at86rf/inc/phy_rx.h" +#include "../../../phy/at86rf/inc/phy_internal.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../../phy/at86rf/inc/phy_trx_reg_access.h" +#include "../../../phy/inc/phy_tasks.h" + + + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* === GLOBALS ============================================================= */ + +static uint8_t tal_sw_retry_count; +static bool tal_sw_retry_no_csma_ca; +static trx_trac_status_t trx_trac_status; + +extern TimerId_t TAL_RETRY_TIMER; + +void trxEIC_waitTimerCb(uintptr_t context); +SYS_TIME_HANDLE trxEIC_waitTimer; + +/* === PROTOTYPES ========================================================== */ +static void retransmissionTimerCallback(void); +/* === IMPLEMENTATION ====================================================== */ + +void trxEIC_waitTimerCb(uintptr_t context) +{ + PHY_PostTask(false); +} + + +/* + * \brief Requests to TAL to transmit frame + * + * This function is called by the MAC to deliver a frame to the TAL + * to be transmitted by the transceiver. + * + * \param tx_frame Pointer to the PHY_FrameInfo_t structure updated by the MAC + * layer + * \param csma_mode Indicates mode of csma-ca to be performed for this frame + * \param perform_frame_retry Indicates whether to retries are to be performed + * for + * this frame + * + * \return MAC_SUCCESS if the TAL has accepted the data from the MAC for frame + * transmission + * TAL_BUSY if the TAL is busy servicing the previous MAC request + */ + PHY_Retval_t PHY_TxFrame(PHY_FrameInfo_t *txFrame, PHY_CSMAMode_t csmaMode, + bool performFrameRetry) +{ + + if (phy_info.tal_state != PHY_IDLE) { + return PHY_BUSY; + } + + /* + * Store the pointer to the provided frame structure. + * This is needed for the callback function. + */ + mac_frame_ptr = txFrame; + + /* Set pointer to actual mpdu to be downloaded to the transceiver. */ + tal_frame_to_tx = txFrame->mpdu; + phy_info.last_frame_length = tal_frame_to_tx[0] - 1U; + /* + * In case the frame is too large, return immediately indicating + * invalid status. + */ + if (tal_frame_to_tx == NULL) { + return PHY_INVALID_PARAMETER; + } + + send_frame(csmaMode, performFrameRetry); + + return PHY_SUCCESS; +} + + +/* + * \brief Implements the handling of the transmission end. + * + * This function handles the callback for the transmission end. + */ +void tx_done_handling(void) +{ + phy_info.tal_state = PHY_IDLE; + + PHY_Retval_t status; + + switch (trx_trac_status) { + case TRAC_SUCCESS: + status = PHY_SUCCESS; + break; + + case TRAC_SUCCESS_DATA_PENDING: + status = PHY_FRAME_PENDING; + break; + + case TRAC_CHANNEL_ACCESS_FAILURE: + status = PHY_CHANNEL_ACCESS_FAILURE; + break; + + case TRAC_NO_ACK: + status = PHY_NO_ACK; + break; + + case TRAC_INVALID: + status = PHY_FAILURE; + break; + + default: + status = PHY_FAILURE; + break; + } + + PHY_TxDoneCallback(status, mac_frame_ptr); + +} /* tx_done_handling() */ + +/* + * \brief Sends frame + * + * \param use_csma Flag indicating if CSMA is requested + * \param tx_retries Flag indicating if transmission retries are requested + * by the MAC layer + */ +void send_frame(PHY_CSMAMode_t csmaMode, bool txRetries) +{ + tal_trx_status_t trx_status; + + /* Configure tx according to tx_retries */ + if (txRetries) { + trx_reg_bit_write(SR_MAX_FRAME_RETRIES, + tal_pib.MaxFrameRetries); + } else { + trx_reg_bit_write(SR_MAX_FRAME_RETRIES, 0); + } + + /* Configure tx according to csma usage */ + if ((csmaMode == NO_CSMA_NO_IFS) || (csmaMode == NO_CSMA_WITH_IFS)) + { + trx_reg_bit_write(SR_MAX_CSMA_RETRIES, 7); /* immediate + * transmission */ + if (txRetries) { + tal_sw_retry_count = tal_pib.MaxFrameRetries; + tal_sw_retry_no_csma_ca = true; + } + } else { + trx_reg_bit_write(SR_MAX_CSMA_RETRIES, tal_pib.MaxCSMABackoffs); + } + + /* Handle interframe spacing */ + if (csmaMode == NO_CSMA_WITH_IFS) { + if (phy_info.last_frame_length > aMaxSIFSFrameSize) { + PAL_TimerDelay(PHY_CONVERT_SYMBOLS_TO_US( + macMinLIFSPeriod_def) + - TRX_IRQ_DELAY_US - + PRE_TX_DURATION_US); + phy_info.last_frame_length = 0; + } else if (phy_info.last_frame_length > 0) { + PAL_TimerDelay(PHY_CONVERT_SYMBOLS_TO_US( + macMinSIFSPeriod_def) + - TRX_IRQ_DELAY_US - + PRE_TX_DURATION_US); + phy_info.last_frame_length = 0; + }else{ + /*DO NOTHING*/ + } + } + do { + trx_status = set_trx_state(CMD_TX_ARET_ON); + } while (trx_status != TX_ARET_ON); + /* + * Send the frame to the transceiver. + * Note: The PhyHeader is the first byte of the frame to + * be sent to the transceiver and this contains the frame + * length. + * The actual length of the frame to be downloaded + * (parameter two of trx_frame_write) + * is + * 1 octet frame length octet + * + n octets frame (i.e. value of frame_tx[0]) + * - 2 octets FCS + */ + + trx_frame_write(tal_frame_to_tx, tal_frame_to_tx[0] - 1U); + phy_info.tal_state = PHY_TX_AUTO; + + /* Toggle the SLP_TR pin triggering transmission. */ + TRX_SLP_TR_HIGH(); + trx_delay_micros(1); + TRX_SLP_TR_LOW(); + + uint8_t context = 0U; + trxEIC_waitTimer = SYS_TIME_CallbackRegisterUS(&trxEIC_waitTimerCb, (uintptr_t)&context, 54000, SYS_TIME_SINGLE); + if(trxEIC_waitTimer == SYS_TIME_HANDLE_INVALID) + { + return; + } + + (void)trx_status; + +} + +/* + * \brief Handles interrupts issued due to end of transmission + * + * \param underrun_occured true if under-run has occurred + */ +void handle_tx_end_irq(bool underrun_occured) +{ + + + { + + /* Read trac status before enabling RX_AACK_ON. */ + if (underrun_occured) { + trx_trac_status = TRAC_INVALID; + } else { + trx_trac_status = (trx_trac_status_t)trx_reg_bit_read( + SR_TRAC_STATUS); + } + + /* Trx has handled the entire transmission incl. CSMA */ + { + if (tal_sw_retry_no_csma_ca && ((bool)tal_sw_retry_count) && + TRAC_NO_ACK == trx_trac_status ) { + tal_trx_status_t trx_status; + do { + trx_status = set_trx_state( + CMD_TX_ARET_ON); + } while (trx_status != TX_ARET_ON); + + /* Toggle the SLP_TR pin triggering + * transmission. */ + TRX_SLP_TR_HIGH(); + trx_delay_micros(1); + TRX_SLP_TR_LOW(); + uint8_t context = 0U; + trxEIC_waitTimer = SYS_TIME_CallbackRegisterUS(&trxEIC_waitTimerCb, (uintptr_t)&context, 54000, SYS_TIME_SINGLE); + if(trxEIC_waitTimer == SYS_TIME_HANDLE_INVALID) + { + return; + } + if (--tal_sw_retry_count == 0U) { + tal_sw_retry_no_csma_ca = false; + } + } else { + phy_info.tal_state = PHY_TX_DONE; /* Further handling is + * done by * tx_done_handling() + **/ + + + //tx_done_handling(); + phy_info.tal_rx_on_required = true; + PHY_PostTask(false); + } + } + } + +} + + +void tal_start_retransmission_timer(uint32_t us) +{ + + if((bool)tal_sw_retry_count) + { + tal_sw_retry_count--; + } + + if(tal_sw_retry_count > 0U) + { + if (PAL_SUCCESS == PAL_TimerStart(TAL_RETRY_TIMER, us, + TIMEOUT_RELATIVE, + (void *)retransmissionTimerCallback, + NULL, CALLBACK_SINGLE)) + { + return; + } + } + + + phy_info.tal_state = PHY_TX_DONE; /* Further handling is + * done by + * tx_done_handling() + **/ + //tx_done_handling(); + phy_info.tal_rx_on_required = true; + PHY_PostTask(false); +} + +static void retransmissionTimerCallback(void) +{ + tal_trx_status_t trx_status; + + do { + trx_status = set_trx_state( + CMD_TX_ARET_ON); + } while (trx_status != TX_ARET_ON); + + /* Toggle the SLP_TR pin triggering + * transmission. */ + TRX_SLP_TR_HIGH(); + trx_delay_micros(1); + TRX_SLP_TR_LOW(); + +} +/* EOF */ diff --git a/driver/software/RF233/phy/at86rf233/src/tfa.c b/driver/software/RF233/phy/at86rf233/src/tfa.c new file mode 100644 index 0000000..3602e54 --- /dev/null +++ b/driver/software/RF233/phy/at86rf233/src/tfa.c @@ -0,0 +1,373 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + + + +/* === INCLUDES ============================================================ */ + +#include +#include +#include +#include +#include "../../../pal/inc/pal.h" +#include "../../../phy/inc/phy.h" +#include "../../../phy/inc/ieee_phy_const.h" +#include "../../../phy/inc/phy_constants.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../../phy/at86rf/inc/phy_internal.h" + + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + +/* Constant define for the ED scaling: register value at -35dBm */ +#define CLIP_VALUE_REG (56) + +/* === GLOBALS ============================================================= */ + +/** + * TFA PIB attribute to reduce the Rx sensitivity. + * Represents the Rx sensitivity value in dBm; example: -52 + */ +static int8_t tfa_pib_rx_sens; + +/* === PROTOTYPES ========================================================== */ + +static void init_tfa_pib(void); +static void write_all_tfa_pibs_to_trx(void); + +/* === IMPLEMENTATION ====================================================== */ + +uint8_t txcwdata[128]; + + +/* + * \brief Perform a CCA + * + * This function performs a CCA request. + * + * \return phy_enum_t PHY_IDLE or PHY_BUSY + */ +PHY_Retval_t PHY_CCAPerform(void) +{ + tal_trx_status_t trx_status; + uint8_t cca_status; + uint8_t cca_done; + + /* Ensure that trx is not in SLEEP for register access */ + do { + trx_status = set_trx_state(CMD_TRX_OFF); + } while (trx_status != TRX_OFF); + + /* no interest in receiving frames while doing CCA */ + trx_reg_bit_write(SR_RX_PDT_DIS, RX_DISABLE); /* disable frame reception + * indication */ + + /* Set trx to rx mode. */ + do { + trx_status = set_trx_state(CMD_RX_ON); + } while (trx_status != RX_ON); + + /* Start CCA */ + trx_reg_bit_write(SR_CCA_REQUEST, CCA_START); + + /* wait until CCA is done */ + trx_delay_micros(PHY_CONVERT_SYMBOLS_TO_US(CCA_DURATION_SYM)); + do { + /* poll until CCA is really done */ + cca_done = trx_reg_bit_read(SR_CCA_DONE); + } while (cca_done != CCA_COMPLETED); + + (void)set_trx_state(CMD_TRX_OFF); + + /* Check if channel was idle or busy. */ + if (trx_reg_bit_read(SR_CCA_STATUS) == CCA_CH_IDLE) { + cca_status = (uint8_t)PHY_CHANNEL_IDLE; + } else { + cca_status = (uint8_t)PHY_CHANNEL_BUSY; + } + + /* Enable frame reception again. */ + trx_reg_bit_write(SR_RX_PDT_DIS, RX_ENABLE); + + return ((PHY_Retval_t)cca_status); +} + + + + + +/* + * \brief Perform a single ED measurement + * + * \return ed_value Result of the measurement + * If the build switch TRX_REG_RAW_VALUE is defined, the transceiver's + * register value is returned. + */ +uint8_t PHY_EdSample(void) +{ + trx_irq_reason_t trx_irq_cause; + uint8_t ed_value; + tal_trx_status_t trx_status; + + phy_info.tal_state = PHY_ED_RUNNING; + + /* Make sure that receiver is switched on. */ + do { + trx_status = set_trx_state(CMD_RX_ON); + } while (trx_status != RX_ON); + + /* + * Disable the transceiver interrupts to prevent frame reception + * while performing ED scan. + */ + trx_reg_bit_write(SR_RX_PDT_DIS, RX_DISABLE); + + /* Write dummy value to start measurement. */ + trx_reg_write(RG_PHY_ED_LEVEL, 0xFF); + + /* Wait for ED measurement completion. */ + trx_delay_micros(PHY_CONVERT_SYMBOLS_TO_US(ED_SAMPLE_DURATION_SYM)); + do { + trx_irq_cause + = (trx_irq_reason_t)trx_reg_read(RG_IRQ_STATUS); + } while ((trx_irq_reason_t)(((uint8_t)trx_irq_cause) & ((uint8_t)TRX_IRQ_4_CCA_ED_DONE)) != + TRX_IRQ_4_CCA_ED_DONE); + + /* Read the ED Value. */ + ed_value = trx_reg_read(RG_PHY_ED_LEVEL); + + /* Clear IRQ register */ + (void)trx_reg_read(RG_IRQ_STATUS); + /* Enable reception agian */ + trx_reg_bit_write(SR_RX_PDT_DIS, RX_ENABLE); + /* Switch receiver off again */ + (void)set_trx_state(CMD_TRX_OFF); + + phy_info.tal_state = PHY_IDLE; + return ed_value; +} + + + +/* + * \brief Starts continuous transmission on current channel + * + * \param tx_mode Mode of continuous transmission (CW or PRBS) + * \param random_content Use random content if true + */ +void PHY_StartContinuousTransmit(PHY_ContinuousTxMode_t txMode, bool randomContent) +{ + + + trx_reg_bit_write(SR_TX_AUTO_CRC_ON, TX_AUTO_CRC_DISABLE); + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_TRX_OFF); + trx_reg_bit_write(SR_TST_CTRL_DIG, TST_CONT_TX); //enable continuous transmit + + /* Here: use 2MBPS mode for PSD measurements. + * Omit the two following lines, if 250k mode is desired for PRBS mode. + **/ + trx_reg_write(RG_TRX_CTRL_2, 0x03); + trx_reg_write(RG_RX_CTRL, 0x37); + + if (txMode == CW_MODE) { + txcwdata[0] = 1; /* length */ + /* Step 12 - frame buffer write access */ + txcwdata[1] = 0x00; /* f=fch-0.5 MHz; set value to 0xFF for + * f=fch+0.5MHz */ + trx_frame_write(txcwdata, 2); + } else { /* PRBS mode */ + txcwdata[0] = 127U; /* = max length */ + for (uint8_t data_index = 1U; data_index < 128U; data_index++) { + if (randomContent) { + txcwdata[data_index] = (uint8_t)rand(); + } else { + txcwdata[data_index] = 0; + } + } + trx_frame_write(txcwdata, 128); + } + + trx_reg_write(RG_PART_NUM, 0x54); + trx_reg_write(RG_PART_NUM, 0x46); + (void)set_trx_state(CMD_PLL_ON); + + TRX_SLP_TR_HIGH(); + trx_delay_micros(1); + TRX_SLP_TR_LOW(); + + +} + + + +/* + * \brief Stops continuous transmission + */ +void PHY_StopContinuousTransmit(void) +{ + + + (void)PHY_Reset(false); +} +/* + * \brief Initializes the TFA + * + * This function is called to initialize the TFA. + * + * \return MAC_SUCCESS if everything went correct; + * FAILURE otherwise + */ +PHY_Retval_t tfa_init(void) +{ + init_tfa_pib(); + write_all_tfa_pibs_to_trx(); + + return PHY_SUCCESS; +} + +/* + * \brief Reset the TFA + * + * This function is called to reset the TFA. + * + * \param set_default_pib Defines whether PIB values need to be set + * to its default values + */ +void tfa_reset(bool set_default_pib) +{ + if (set_default_pib) { + init_tfa_pib(); + } + + write_all_tfa_pibs_to_trx(); +} + +/** + * \brief Initialize the TFA PIB + * + * This function initializes the TFA information base attributes + * to their default values. + * \ingroup group_tfa + */ +static void init_tfa_pib(void) +{ + tfa_pib_rx_sens = TFA_PIB_RX_SENS_DEF; +} + +/** + * \brief Write all shadow PIB variables to the transceiver + * + * This function writes all shadow PIB variables to the transceiver. + * It is assumed that the radio does not sleep. + * \ingroup group_tfa + */ +static void write_all_tfa_pibs_to_trx(void) +{ + (void)tfa_pib_set(TFA_PIB_RX_SENS, (void *)&tfa_pib_rx_sens); +} + + +/* + * \brief Sets a TFA PIB attribute + * + * This function is called to set the transceiver information base + * attributes. + * + * \param[in] tfa_pib_attribute TFA infobase attribute ID + * \param[in] value TFA infobase attribute value to be set + * + * \return MAC_UNSUPPORTED_ATTRIBUTE if the TFA info base attribute is not found + * TAL_BUSY if the TAL is not in TAL_IDLE state. + * MAC_SUCCESS if the attempt to set the PIB attribute was successful + */ +PHY_Retval_t tfa_pib_set(PHY_tfa_pib_t tfa_pib_attribute, void *value) +{ + switch (tfa_pib_attribute) { + case TFA_PIB_RX_SENS: + { + uint8_t reg_val; + + tfa_pib_rx_sens = *((int8_t *)value); + if (tfa_pib_rx_sens > -49) { + reg_val = 0xF; + tfa_pib_rx_sens = -49; + } else if (tfa_pib_rx_sens <= RSSI_BASE_VAL_DBM) { + reg_val = 0x0; + tfa_pib_rx_sens = RSSI_BASE_VAL_DBM; + } else { + int8_t temp = (((tfa_pib_rx_sens - + (RSSI_BASE_VAL_DBM)) / 3) + 1); + reg_val + = (uint8_t)temp; + + } + + trx_reg_bit_write(SR_RX_PDT_LEVEL, reg_val); + } + break; + + default: + /* Invalid attribute id */ + return PHY_UNSUPPORTED_ATTRIBUTE; + break; + } + + return PHY_SUCCESS; +} + +/* + * \brief Gets a TFA PIB attribute + * + * This function is called to retrieve the transceiver information base + * attributes. + * + * \param[in] tfa_pib_attribute TAL infobase attribute ID + * \param[out] value TFA infobase attribute value + * + * \return MAC_UNSUPPORTED_ATTRIBUTE if the TFA infobase attribute is not found + * MAC_SUCCESS otherwise + */ +PHY_Retval_t tfa_pib_get(PHY_tfa_pib_t tfa_pib_attribute, void *value) +{ + switch (tfa_pib_attribute) { + case TFA_PIB_RX_SENS: + *(uint8_t *)value = tfa_pib_rx_sens; + break; + + default: + /* Invalid attribute id */ + return PHY_UNSUPPORTED_ATTRIBUTE; + break; + } + + return PHY_SUCCESS; +} + + + + +/* EOF */ diff --git a/driver/software/RF233/phy/inc/ieee_phy_const.h b/driver/software/RF233/phy/inc/ieee_phy_const.h new file mode 100644 index 0000000..0cba625 --- /dev/null +++ b/driver/software/RF233/phy/inc/ieee_phy_const.h @@ -0,0 +1,1702 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + + +#ifndef IEEE_PHY_CONST_H +#define IEEE_PHY_CONST_H + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* CCA Modes of the transceiver + + Summary: + CCA Modes supported by transceiver + + Description: + Following are the list of configuration parameters which can be read from the + transceiver + + Remarks: + None + */ + +typedef enum trx_cca_mode_tag { + TRX_CCA_MODE0 = 0, /** Carrier sense OR energy above threshold */ + TRX_CCA_MODE1 = 1, /** Energy above threshold */ + TRX_CCA_MODE2 = 2, /** Carrier sense only */ + TRX_CCA_MODE3 = 3 /** Carrier sense AND energy above threshold */ +} trx_cca_mode_t; + + +// ***************************************************************************** +/* CCA mode enumeration + + Summary: + CCA Modes supported by transceiver + + Description: + Following are CCA mode enumeration which can be read from the transceiver + + Remarks: + None + */ +typedef enum cca_mode_tag { + CCA_MODE_0_CS_OR_ED = 0, + CCA_MODE_1_ED = 1, /** To be conform to IEEE 15.4 and TRX register */ + CCA_MODE_2_CS, + CCA_MODE_3_CS_ED, + CCA_MODE_4_ALOHA +} cca_mode_t; + +// ***************************************************************************** +/* ch_pg enumeration + + Summary: + ch_pg_t holds ch_pg enumeration which can be read from the transceiver. + + Description: + None + + Remarks: + None + */ + +typedef enum ch_pg_tag { + CH_PG_2003 = 0, + CH_PG_2006 = 2, + CH_PG_CHINA = 5, + CH_PG_JAPAN = 6, + CH_PG_MSK = 7, + CH_PG_LRP_UWB = 8, + CH_PG_SUN = 9, + CH_PG_GENERIC_PHY = 10, + CH_PG_16 = 16, + CH_PG_18 = 18, + CH_PG_INVALID = 0xFF +} ch_pg_t; + +// ***************************************************************************** +// ***************************************************************************** +// Section: Macros +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Min Frame Length + + Summary: + This macro holds the Minimum size of a valid frame other than an Ack frame + Description: + None + Remarks: + None + */ + +#define MIN_FRAME_LENGTH (8U) + +// ***************************************************************************** +/* Max MGMT Frame Length + + Summary: + This macro holds the Maximum size of the management frame(Association Response frame) + Description: + None + Remarks: + None + */ + +#define MAX_MGMT_FRAME_LENGTH (30U) + +// ***************************************************************************** +// ***************************************************************************** +// Section: MAC Constants +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Max size of PHY packet + + Summary: + This macro holds the Maximum size of PHY packet + Description: + None + Remarks: + None + */ + +#define aMaxPHYPacketSize (127U) + +// ***************************************************************************** +/* Maximum turnaround Time + + Summary: + This macro holds Maximum turnaround Time of the radio to switch from Rx to Tx or + Tx to Rx in symbols + Description: + None + Remarks: + None + */ + +#define aTurnaroundTime (12U) + +// ***************************************************************************** +/* maximum size of an MPDU + + Summary: + This macro holds The maximum size of an MPDU, in octets, that can be followed by + a SIFS period + Description: + None + Remarks: + None + */ + +#define aMaxSIFSFrameSize (18U) + +/** + * The minimum number of symbols forming the CAP. This ensures that MAC + * commands can still be transferred to devices when GTSs are being used. + * An exception to this minimum shall be allowed for the accommodation + * of the temporary increase in the beacon frame length needed to perform GTS + * maintenance (see 7.2.2.1.3). + * @ingroup apiMacConst + */ +#define aMinCAPLength (440U) + +// ***************************************************************************** +/* + + Summary: + This macro holds The minimum number of octets added by the MAC sublayer to the PSDU + Description: + None + Remarks: + None + */ + +#define aMinMPDUOverhead (9U) + +// ***************************************************************************** +/* + + Summary: + This macro holds The number of slots contained in any superframe + Description: + None + Remarks: + None + */ + +#define aNumSuperframeSlots (16U) + +// ***************************************************************************** +/* + + Summary: + This macro holds The number of symbols forming the basic time period used by + the CSMA-CA algorithm + Description: + None + Remarks: + None + */ + +#define aUnitBackoffPeriod (20U) + + +// ***************************************************************************** +/* + + Summary: + This macro holds The number of symbols forming a superframe slot when the superframe + order is equal to 0 + Description: + None + Remarks: + None + */ + +#define aBaseSlotDuration (60U) + +// ***************************************************************************** +/* + + Summary: + This macro holds The number of symbols forming a superframe when the superframe + order is equal to 0 + Description: + None + Remarks: + None + */ + +#define aBaseSuperframeDuration (aBaseSlotDuration * \ + aNumSuperframeSlots) + +/** + * The number of superframes in which a GTS descriptor + * exists in the beacon frame of a PAN coordinator. + * @ingroup apiMacConst + */ +#define aGTSDescPersistenceTime (4U) + +/** + * The maximum number of octets added by the MAC + * sublayer to the payload of its beacon frame. + * @ingroup apiMacConst + */ +#define aMaxBeaconOverhead (75U) + +/** + * The maximum size, in octets, of a beacon payload. + * @ingroup apiMacConst + */ +#define aMaxBeaconPayloadLength (aMaxPHYPacketSize - aMaxBeaconOverhead) + +/** + * The number of consecutive lost beacons that will cause the MAC sublayer of + * a receiving device to declare a loss of synchronization. + * @ingroup apiMacConst + */ +#define aMaxLostBeacons (4U) + +/** + * The maximum number of octets that can be transmitted in the MAC Payload + * field. + * @ingroup apiMacConst + */ +#define aMaxMACPayloadSize (aMaxPHYPacketSize - aMinMPDUOverhead) + +/** + * The maximum number of octets added by the MAC sublayer to the PSDU without + * security. + * @ingroup apiMacConst + */ +#define aMaxMPDUUnsecuredOverhead (25U) + +/** + * The maximum number of octets that can be transmitted in the MAC Payload + * field of an unsecured MAC frame that will be guaranteed not to exceed + * aMaxPHYPacketSize. + * @ingroup apiMacConst + */ +#define aMaxMACSafePayloadSize (aMaxPHYPacketSize - \ + aMaxMPDUUnsecuredOverhead) +// ***************************************************************************** +// ***************************************************************************** +// Section: Standard PHY PIB attributes +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* phyCurrentChannel + + Summary: + This macro holds The RF channel to use for all following transmissions and receptions + Description: + None + Remarks: + None + */ + +#define phyCurrentChannel (0x00U) + +// ***************************************************************************** +/* phyChannelsSupported + + Summary: + This macro holds The 5 most significant bits (MSBs) (b27, ..., b31) of phyChannelsSupported + shall be reserved and set to 0, and the 27 LSBs (b0, b1, ..., b26) shall indicate + the status (1 = available, 0 = unavailable) for each of the 27 valid channels + (bk shall indicate the status of channel k). + Description: + None + Remarks: + None + */ + +#define phyChannelsSupported (0x01U) + +// ***************************************************************************** +/* phyTransmitPower + + Summary: + This macro holds The 2 MSBs represent the tolerance on the transmit power: + 00 = 1 dB 01 = 3 dB 10 = 6 dB The 6 LSBs represent a signed integer in + twos-complement format, corresponding to the nominal transmit power of the + device in decibels relative to 1 mW. The lowest value of phyTransmitPower + shall be interpreted as less than or equal to 32 dBm. + Description: + None + Remarks: + None + */ + +#define phyTransmitPower (0x02U) + +// ***************************************************************************** +/* phyCCAMode + + Summary: + This macro holds The CCA mode + - CCA Mode 1: Energy above threshold. CCA shall report a busy medium + upon detecting any energy above the ED threshold. + - CCA Mode 2: Carrier sense only. CCA shall report a busy medium only upon + the detection of a signal with the modulation and spreading characteristics + of IEEE 802.15.4. This signal may be above or below the ED threshold. + - CCA Mode 3: Carrier sense with energy above threshold. CCA shall report a + busy medium only upon the detection of a signal with the modulation and + spreading characteristics of IEEE 802.15.4 with energy above the ED threshold. + Description: + None + Remarks: + None + */ + +#define phyCCAMode (0x03U) + +// ***************************************************************************** +/* phyCurrentPage + + Summary: + This macro holds current PHY channel page. This is used in conjunction with + phyCurrentChannel to uniquely identify the channel currently being used + Description: + None + Remarks: + None + */ + +#define phyCurrentPage (0x04U) + +// ***************************************************************************** +/* phyMaxFrameDuration + + Summary: + This macro holds The maximum number of symbols in a frame: + = phySHRDuration + ceiling([aMaxPHYPacketSize + 1] x phySymbolsPerOctet) + Description: + None + Remarks: + None + */ + +#define phyMaxFrameDuration (0x05U) + +// ***************************************************************************** +/* phySHRDuration + + Summary: + This macro holds The duration of the synchronization header (SHR) in symbols + for the current PHY + Description: + None + Remarks: + None + */ + +#define phySHRDuration (0x06U) + +// ***************************************************************************** +/* phySymbolsPerOctet + + Summary: + This macro holds The number of symbols per octet for the current PHY + Description: + None + Remarks: + None + */ + +#define phySymbolsPerOctet (0x07U) + +// ***************************************************************************** +/* PHY_OVERHEAD + + Summary: + This macro holds Number of octets added by the PHY: 4 sync octets + SFD octet + Description: + None + Remarks: + None + */ + +#define PHY_OVERHEAD (5U) + +// ***************************************************************************** +// ***************************************************************************** +// Section: MAC PIB Attributes +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* macAckWaitDuration + + Summary: + This macro holds The maximum number of symbols to wait for an acknowledgment frame + to arrive following a transmitted data frame. This value is dependent on the currently + selected logical channel. For 0 <= phyCurrentChannel <= 10, this value is equal to 120. + For 11 <= phyCurrentChannel <= 26, this value is equal to 54. + Description: + None + Remarks: + None + */ + +#define macAckWaitDuration (0x40U) + +/** + * Indication of whether a coordinator is currently allowing association. + * A value of true indicates that association is permitted. + * + * - @em Type: Boolean + * - @em Range: true or false + * - @em Default: false + */ +#define macAssociationPermit (0x41U) + +/** + * Default value for PIB macAssociationPermit + */ +#define macAssociationPermit_def (false) + +/** + * Indication of whether a device automatically sends a data request command + * if its address is listed in the beacon frame. A value of true indicates + * that the data request command is automatically sent. + * + * - @em Type: Boolean + * - @em Range: true or false + * - @em Default: true + */ +#define macAutoRequest (0x42U) + +/** + * Default value for PIB macAutoRequest + */ +#define macAutoRequest_def (true) + +/** + * Indication of whether battery life extension, by reduction of coordinator + * receiver operation time during the CAP, is enabled. A value of + * true indicates that it is enabled. + * + * - @em Type: Boolean + * - @em Range: true or false + * - @em Default: false + */ +#define macBattLifeExt (0x43U) + +/** + * Default value for PIB macBattLifeExt + */ +#define macBattLifeExt_def (false) + +/** + * The number of backoff periods during which the receiver is enabled following + * a beacon in battery life extension mode. This value is dependent on the + * currently selected logical channel. For 0 <= * phyCurrentChannel <= 10, this + * value is equal to 8. For 11 <= * phyCurrentChannel <= 26, this value + * is equal to 6. + * + * - @em Type: Integer + * - @em Range: 6 or 8 + * - @em Default: 6 + */ +#define macBattLifeExtPeriods (0x44U) + +/** + * Default value for PIB macBattLifeExtPeriods + */ +#define macBattLifeExtPeriods_def (6U) + +/** + * The contents of the beacon payload. + * + * - @em Type: Set of octets + * - @em Range: -- + * - @em Default: NULL + */ +#define macBeaconPayload (0x45U) + +/** + * The length, in octets, of the beacon payload. + * + * - @em Type: Integer + * - @em Range: 0 - aMaxBeaconPayloadLength + * - @em Default: 0 + */ +#define macBeaconPayloadLength (0x46U) + +/** + * Default value for PIB macBeaconPayloadLength + */ +#define macBeaconPayloadLength_def (0U) + +/** + * Specification of how often the coordinator transmits a beacon. + * The macBeaconOrder, BO, and the beacon interval, BI, are related as + * follows: for 0 <= BO <= 14, BI = aBaseSuperframeDuration * 2^BO symbols. + * If BO = 15, the coordinator will not transmit a beacon. + * + * - @em Type: Integer + * - @em Range: 0 - 15 + * - @em Default: 15 + */ +#define macBeaconOrder (0x47U) + +/** + * Default value for PIB macBeaconOrder + */ +#define macBeaconOrder_def (15U) + +/** + * BO value for nonbeacon-enabled network + */ +#define NON_BEACON_NWK (0x0FU) + +/** + * The time that the device transmitted its last beacon frame, in symbol + * periods. The measurement shall be taken at the same symbol boundary within + * every transmitted beacon frame, the location of which is implementation + * specific. The precision of this value shall be a minimum of 20 bits, with + * the lowest four bits being the least significant. + * + * - @em Type: Integer + * - @em Range: 0x000000 - 0xffffff + * - @em Default: 0x000000 + */ +#define macBeaconTxTime (0x48U) + +/** + * Default value for PIB macBeaconTxTime + */ +#define macBeaconTxTime_def (0x000000U) + +/** + * The sequence number added to the transmitted beacon frame. + * + * - @em Type: Integer + * - @em Range: 0x00 - 0xFF + * - @em Default: Random value from within the range. + */ +#define macBSN (0x49U) + +/** + * The 64 bit address of the coordinator with which the device is associated. + * + * - @em Type: IEEE address + * - @em Range: An extended 64bit IEEE address + * - @em Default: - + */ +#define macCoordExtendedAddress (0x4AU) + +/** + * The 16 bit short address assigned to the coordinator with which the device + * is associated. A value of 0xfffe indicates that the coordinator is only + * using its 64 bit extended address. A value of 0xffff indicates that this + * value is unknown. + * + * - @em Type: Integer + * - @em Range: 0x0000 - 0xffff + * - @em Default: 0xffff + */ +#define macCoordShortAddress (0x4BU) + +/** + * Default value for PIB macCoordShortAddress + */ +#define macCoordShortAddress_def (0xFFFF) + +/** + * The sequence number added to the transmitted data or MAC command frame. + * + * - @em Type: Integer + * - @em Range: 0x00 - 0xFF + * - @em Default: Random value from within the range. + */ +#define macDSN (0x4CU) + +/** + * macGTSPermit is true if the PAN coordinator is to accept GTS requests, + * false otherwise. + * + * - @em Type: Boolean + * - @em Range: true or false + * - @em Default: true + */ +#define macGTSPermit (0x4DU) + +/** + * Default value for PIB macGTSPermit + */ +#define macGTSPermit_def (true) + +// ***************************************************************************** +/* macMaxCSMABackoffs + + Summary: + This macro holds The maximum number of backoffs the CSMA-CA algorithm will attempt + before declaring a channel access failure. + Description: + None + Remarks: + None + */ + +#define macMaxCSMABackoffs (0x4EU) + +// ***************************************************************************** +/* macMaxCSMABackoffs_def + + Summary: + This macro holds The Default value for PIB macMaxCSMABackoffs + Description: + None + Remarks: + None + */ + +#define macMaxCSMABackoffs_def (4U) + +// ***************************************************************************** +/* macMinBE + + Summary: + This macro holds The minimum value of the backoff exponent in the CSMA-CA + algorithm.Note that if this value is set to 0, collision avoidance is disabled + during the first iteration of the algorithm. Also note that for the slotted + version of the CSMACA algorithm with the battery life extension enabled, the + minimum value of the backoff exponent will be the lesser of 2 and the value of + macMinBE. + Description: + None + Remarks: + None + */ + +#define macMinBE (0x4FU) + +// ***************************************************************************** +/* macPANId + + Summary: + This macro holds The 16 bit identifier of the PAN on which the device is operating. + If this value is 0xffff, the device is not associated. + Description: + None + Remarks: + None + */ + +#define macPANId (0x50U) + +// ***************************************************************************** +/* macPANId_def + + Summary: + This macro holds The Default value for PIB macPANId + Description: + None + Remarks: + None + */ + +#define macPANId_def (0xFFFF) + +// ***************************************************************************** +/* macPromiscuousMode + + Summary: + This indicates whether the MAC sublayer is in a promiscuous (receive all) + mode. A value of true indicates that the MAC sublayer accepts all frames + received from the PHY. + Description: + None + Remarks: + None + */ + +#define macPromiscuousMode (0x51U) + +/** + * This indicates whether the MAC sublayer is to enable its receiver + * during idle periods. + * + * - @em Type: Boolean + * - @em Range: true or false + * - @em Default: false + */ +#define macRxOnWhenIdle (0x52U) + +/** + * Default value for PIB macRxOnWhenIdle + */ +#define macRxOnWhenIdle_def (false) + +// ***************************************************************************** +/* macShortAddress + + Summary: + This macro holds The 16 bit address that the device uses to communicate in + the PAN.If the device is a PAN coordinator, this value shall be chosen before + a PAN is started. Otherwise, the address is allocated by a coordinator during + association. A value of 0xfffe indicates that the device has associated but + has not been allocated an address. A value of 0xffff indicates that the device + does not have a short address. + Description: + None + Remarks: + None + */ + +#define macShortAddress (0x53U) + +// ***************************************************************************** +/* macShortAddress_def + + Summary: + This macro holds Default value for PIB macShortAddress + Description: + None + Remarks: + None + */ + +#define macShortAddress_def (0xFFFF) + +/** + * This specifies the length of the active portion of the superframe, including + * the beacon frame. The macSuperframeOrder, SO, and the superframe duration, + * SD, are related as follows: for 0 <= SO <= BO <= 14, SD = + * aBaseSuperframeDuration * 2SO symbols. If SO = 15, the superframe will + * not be active following the beacon. + * + * - @em Type: Integer + * - @em Range: 0 - 15 + * - @em Default: 15 + */ +#define macSuperframeOrder (0x54U) + +/** + * Default value for PIB macSuperframeOrder + */ +#define macSuperframeOrder_def (15U) + +/** + * The maximum time (in superframe periods) that a transaction is stored by a + * coordinator and indicated in its beacon. + * + * - @em Type: Integer + * - @em Range: 0x0000 - 0xffff + * - @em Default: 0x01f4 + */ +#define macTransactionPersistenceTime (0x55U) + +/** + * Default value for PIB macTransactionPersistenceTime + */ +#define macTransactionPersistenceTime_def (0x01F4) + +/** + * Indication of whether the device is associated to the PAN through the PAN + * coordinator. A value of TRUE indicates the device has associated through the + * PAN coordinator. Otherwise, the value is set to FALSE. + * + * - @em Type: Boolean + * - @em Range: true or false + * - @em Default: false + */ +#define macAssociatedPANCoord (0x56U) + +/** + * Default value for PIB macAssociatedPANCoord + */ +#define macAssociatedPANCoord_def (false) + + +// ***************************************************************************** +/* macMaxBE + + Summary: + This macro holds The maximum value of the backoff exponent, BE, in the CSMA-CA algorithm + Description: + None + Remarks: + None + */ + +#define macMaxBE (0x57U) + +/** + * The maximum number of CAP symbols in a beaconenabled PAN, or symbols in a + * nonbeacon-enabled PAN, to wait either for a frame intended as a response to + * a data request frame or for a broadcast frame following a beacon with the + * Frame Pending subfield set to one. + * This attribute, which shall only be set by the next higher layer, is + * dependent upon macMinBE, macMaxBE, macMaxCSMABackoffs and the number of + * symbols per octet. See 7.4.2 for the formula relating the attributes. + * + * - @em Type: Integer + * - @em Range: See equation (14) + * - @em Default: Dependent on currently selected PHY, indicated by + * phyCurrentPage + */ +#define macMaxFrameTotalWaitTime (0x58U) + +// ***************************************************************************** +/* macMaxFrameRetries + + Summary: + This macro holds The maximum number of retries allowed after a transmission failure + Description: + None + Remarks: + None + */ + +#define macMaxFrameRetries (0x59U) + +// ***************************************************************************** +/* macMaxFrameRetries + + Summary: + This macro holds PIB attribute without relevant index, i.e. PIB attribute not + contained in 802.15.4-2006 table 88. + Description: + None + Remarks: + None + */ + +#define NO_PIB_INDEX (0U) + +// ***************************************************************************** +/* macMinLIFSPeriod + + Summary: + This macro holds The minimum number of symbols forming a LIFS period. + Description: + None + Remarks: + None + */ + +#define macMinLIFSPeriod (0x5EU) + +// ***************************************************************************** +/* macMinLIFSPeriod_def + + Summary: + This macro holds The Default value for PIB macMinLIFSPeriod. + Description: + None + Remarks: + None + */ + +#define macMinLIFSPeriod_def (40U) + +// ***************************************************************************** +/* macMinSIFSPeriod + + Summary: + This macro holds The minimum number of symbols forming a SIFS period. + Description: + None + Remarks: + None + */ + +#define macMinSIFSPeriod (0x5FU) + +// ***************************************************************************** +/* macMinSIFSPeriod_def + + Summary: + This macro holds Default value for PIB macMinSIFSPeriod + Description: + None + Remarks: + None + */ + +#define macMinSIFSPeriod_def (12U) + +// ***************************************************************************** +/* macMinSIFSPeriod_def + + Summary: + This macro holds Private MAC PIB attribute to allow setting the MAC address + in test mode + Description: + None + Remarks: + None + */ + +#define macIeeeAddress (0xF0U) + +// ***************************************************************************** +// ***************************************************************************** +// Section: Non-standard values / extensions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* PHY_SUCCESS_DATA_PENDING + + Summary: + This macro holds PHY_SUCCESS in phyAutoCSMACA when received ACK frame had the + pending bit set + Description: + None + Remarks: + None + */ + +#define PHY_SUCCESS_DATA_PENDING (0x10U) + +// ***************************************************************************** +/* ED_SAMPLE_DURATION_SYM + + Summary: + This macro holds ED scan/sampling duration + Description: + None + Remarks: + None + */ + +#define ED_SAMPLE_DURATION_SYM (8U) + +// ***************************************************************************** +/* FCF_FRAMETYPE_BEACON + + Summary: + This macro holds Defines the beacon frame type. + Description: + None + Remarks: + None + */ + +#define FCF_FRAMETYPE_BEACON (0x00U) + +// ***************************************************************************** +/* FCF_FRAMETYPE_DATA + + Summary: + This macro holds Define the data frame type. + Description: + None + Remarks: + None + */ + +#define FCF_FRAMETYPE_DATA (0x01U) + +// ***************************************************************************** +/* FCF_FRAMETYPE_ACK + + Summary: + This macro holds Define the ACK frame type. + Description: + None + Remarks: + None + */ + +#define FCF_FRAMETYPE_ACK (0x02U) + +// ***************************************************************************** +/* FCF_FRAMETYPE_ACK + + Summary: + This macro holds Define the command frame type. + Description: + None + Remarks: + None + */ + +#define FCF_FRAMETYPE_MAC_CMD (0x03U) + +// ***************************************************************************** +/* FCF_FRAMETYPE_LLDN + + Summary: + This macro holds Define the LLDN frame type. + Description: + None + Remarks: + None + */ + +#define FCF_FRAMETYPE_LLDN (0x04U) + +// ***************************************************************************** +/* FCF_FRAMETYPE_MP + + Summary: + This macro holds Define the multipurpose frame type. + Description: + None + Remarks: + None + */ + +#define FCF_FRAMETYPE_MP (0x05U) + +// ***************************************************************************** +/* FCF_SET_FRAMETYPE + + Summary: + This macro holds to set the frame type. + Description: + None + Remarks: + None + */ + +#define FCF_SET_FRAMETYPE(x) (x) + +// ***************************************************************************** +/* FCF_SECURITY_ENABLED + + Summary: + This macro holds The mask for the security enable bit of the FCF. + Description: + None + Remarks: + None + */ + +#define FCF_SECURITY_ENABLED (1U << 3U) + +// ***************************************************************************** +/* FCF_FRAME_PENDING + + Summary: + This macro holds The mask for the frame pending bit of the FCF. + Description: + None + Remarks: + None + */ + +#define FCF_FRAME_PENDING (1U << 4U) + +// ***************************************************************************** +/* FCF_ACK_REQUEST + + Summary: + This macro holds The mask for the ACK request bit of the FCF. + Description: + None + Remarks: + None + */ + +#define FCF_ACK_REQUEST (1U << 5U) + +// ***************************************************************************** +/* FCF_PAN_ID_COMPRESSION + + Summary: + This macro holds The mask for the PAN ID compression bit of the FCF. + Description: + None + Remarks: + None + */ + +#define FCF_PAN_ID_COMPRESSION (1U << 6U) + +// ***************************************************************************** +/* FCF_FRAME_VERSION_2003 + + Summary: + This macro holds The mask for a IEEE 802.15.4-2003 compatible frame in the + frame version subfield. + Description: + None + Remarks: + None + */ + +#define FCF_FRAME_VERSION_2003 (0U << 12U) + +// ***************************************************************************** +/* FCF_FRAME_VERSION_2006 + + Summary: + This macro holds The mask for a IEEE 802.15.4-2006 compatible frame in the + frame version subfield. + Description: + None + Remarks: + None + */ + +#define FCF_FRAME_VERSION_2006 (1U << 12U) + +// ***************************************************************************** +/* FCF_FRAME_VERSION_2012 + + Summary: + This macro holds The mask for a IEEE 802.15.4-2012 compatible frame in the + frame version subfield. + Description: + None + Remarks: + None + */ + +#define FCF_FRAME_VERSION_2012 (2U << 12U) + +// ***************************************************************************** +/* FCF1_FV_SHIFT + + Summary: + This macro holds Shift value for the frame version subfield fcf1 + Description: + None + Remarks: + None + */ + +#define FCF1_FV_SHIFT (4U) + +// ***************************************************************************** +/* FCF1_FV_MASK + + Summary: + This macro holds The mask for the frame version subfield fcf1 + Description: + None + Remarks: + None + */ + +#define FCF1_FV_MASK (3U << FCF1_FV_SHIFT) + +// ***************************************************************************** +/* FCF1_FV_2003 + + Summary: + This macro holds The mask for a IEEE 802.15.4-2003 compatible frame in the + frame version subfield fcf1 + Description: + None + Remarks: + None + */ + +#define FCF1_FV_2003 (0U) + +// ***************************************************************************** +/* FCF1_FV_2006 + + Summary: + This macro holds The mask for a IEEE 802.15.4-2006 compatible frame in the + frame version subfield fcf1 + Description: + None + Remarks: + None + */ + +#define FCF1_FV_2006 (1U) + +// ***************************************************************************** +/* FCF1_FV_2012 + + Summary: + This macro holds The mask for a IEEE 802.15.4-2012 compatible frame in the + frame version subfield fcf1 + Description: + None + Remarks: + None + */ + +#define FCF1_FV_2012 (2U) + +// ***************************************************************************** +/* FCF_NO_ADDR + + Summary: + This macro holds Address Mode: NO ADDRESS + Description: + None + Remarks: + None + */ + +#define FCF_NO_ADDR (0x00U) + +// ***************************************************************************** +/* FCF_RESERVED_ADDR + + Summary: + This macro holds Address Mode: RESERVED + Description: + None + Remarks: + None + */ + +#define FCF_RESERVED_ADDR (0x01U) + +// ***************************************************************************** +/* FCF_SHORT_ADDR + + Summary: + This macro holds Address Mode: SHORT + Description: + None + Remarks: + None + */ + +#define FCF_SHORT_ADDR (0x02U) + +// ***************************************************************************** +/* FCF_LONG_ADDR + + Summary: + This macro holds Address Mode: LONG + Description: + None + Remarks: + None + */ + +#define FCF_LONG_ADDR (0x03U) + +// ***************************************************************************** +/* FCF_DEST_ADDR_OFFSET + + Summary: + This macro holds Defines the offset of the destination address + Description: + None + Remarks: + None + */ + +#define FCF_DEST_ADDR_OFFSET (10U) + +// ***************************************************************************** +/* FCF_SOURCE_ADDR_OFFSET + + Summary: + This macro holds Defines the offset of the source address + Description: + None + Remarks: + None + */ + +#define FCF_SOURCE_ADDR_OFFSET (14U) + +// ***************************************************************************** +/* FCF_SET_SOURCE_ADDR_MODE + + Summary: + This macro holds to set the source address mode + Description: + None + Remarks: + None + */ + +#define FCF_SET_SOURCE_ADDR_MODE(x) ((unsigned int)((x) << \ + FCF_SOURCE_ADDR_OFFSET)) + +// ***************************************************************************** +/* FCF_SET_DEST_ADDR_MODE + + Summary: + This macro holds to set the destination address mode + Description: + None + Remarks: + None + */ + +#define FCF_SET_DEST_ADDR_MODE(x) ((unsigned int)((x) << \ + FCF_DEST_ADDR_OFFSET)) + +// ***************************************************************************** +/* FCF_FRAMETYPE_MASK + + Summary: + This macro holds Defines a mask for the frame type + Description: + None + Remarks: + None + */ + +#define FCF_FRAMETYPE_MASK (0x07U) + +// ***************************************************************************** +/* FCF_GET_FRAMETYPE + + Summary: + This macro holds to get the frame type + Description: + None + Remarks: + None + */ + +#define FCF_GET_FRAMETYPE(x) ((x) & FCF_FRAMETYPE_MASK) + +/** + * Mask for the number of short addresses pending + */ +#define NUM_SHORT_PEND_ADDR(x) ((x) & 0x07U) + +/** + * Mask for the number of long addresses pending + */ +#define NUM_LONG_PEND_ADDR(x) (((x) & 0x70U) >> 4U) + +// ***************************************************************************** +/* BROADCAST + + Summary: + This macro holds Generic 16 bit broadcast address + Description: + None + Remarks: + None + */ + +#define BROADCAST (0xFFFF) + +// ***************************************************************************** +/* FCF_2_DEST_ADDR_OFFSET + + Summary: + This macro holds Offset of Destination Addressing Mode of octet two of MHR. + Description: + None + Remarks: + None + */ + +#define FCF_2_DEST_ADDR_OFFSET (2U) + +// ***************************************************************************** +/* FCF_2_SOURCE_ADDR_OFFSET + + Summary: + This macro holds Offset of Source Addressing Mode of octet two of MHR. + Description: + None + Remarks: + None + */ + +#define FCF_2_SOURCE_ADDR_OFFSET (6U) + + +// ***************************************************************************** +// Octet position within PHY_FrameInfo_t->payload array +// ***************************************************************************** + +// ***************************************************************************** +/* PL_POS_FCF_1 + + Summary: + This macro holds Octet position of FCF octet one within payload array of PHY_FrameInfo_t. + Description: + None + Remarks: + None + */ + +#define PL_POS_FCF_1 (1U) + +// ***************************************************************************** +/* PL_POS_FCF_2 + + Summary: + This macro holds Octet position of FCF octet two within payload array of PHY_FrameInfo_t. + Description: + None + Remarks: + None + */ + +#define PL_POS_FCF_2 (2U) + +// ***************************************************************************** +/* PL_POS_SEQ_NUM + + Summary: + This macro holds Octet position of Sequence Number octet within payload array of + PHY_FrameInfo_t. + Description: + None + Remarks: + None + */ + +#define PL_POS_SEQ_NUM (3U) + +// ***************************************************************************** +/* PL_POS_DST_PAN_ID_START + + Summary: + This macro holds Octet start position of Destination PAN-Id field within payload array of + PHY_FrameInfo_t. + Description: + None + Remarks: + None + */ + +#define PL_POS_DST_PAN_ID_START (4U) + +// ***************************************************************************** +/* PL_POS_DST_ADDR_START + + Summary: + This macro holds Octet start position of Destination Address field within payload array of + PHY_FrameInfo_t. + Description: + None + Remarks: + None + */ + +#define PL_POS_DST_ADDR_START (6U) + +// ***************************************************************************** +/* LENGTH_FIELD_LEN + + Summary: + This macro holds Size of the length parameter + Description: + None + Remarks: + None + */ + +#define LENGTH_FIELD_LEN (1U) + +// ***************************************************************************** +/* LQI_LEN + + Summary: + This macro holds Length of the LQI number field + Description: + None + Remarks: + None + */ + +#define LQI_LEN (1U) + +// ***************************************************************************** +/* ED_VAL_LEN + + Summary: + This macro holds Length of the ED value parameter number field + Description: + None + Remarks: + None + */ + +#define ED_VAL_LEN (1U) + +// ***************************************************************************** +/* FCF_LEN + + Summary: + This macro holds Length (in octets) of FCF + Description: + None + Remarks: + None + */ + +#define FCF_LEN (2U) + +// ***************************************************************************** +/* FCS_LEN + + Summary: + This macro holds Length (in octets) of FCS + Description: + None + Remarks: + None + */ + +#define FCS_LEN (2U) + +// ***************************************************************************** +/* SEQ_NUM_LEN + + Summary: + This macro holds Length of the sequence number field + Description: + None + Remarks: + None + */ + +#define SEQ_NUM_LEN (1U) + +// ***************************************************************************** +/* EXT_ADDR_LEN + + Summary: + This macro holds Length (in octets) of extended address + Description: + None + Remarks: + None + */ + +#define EXT_ADDR_LEN (8U) + +// ***************************************************************************** +/* SHORT_ADDR_LEN + + Summary: + This macro holds Length (in octets) of short address + Description: + None + Remarks: + None + */ + +#define SHORT_ADDR_LEN (2U) + +// ***************************************************************************** +/* PAN_ID_LEN + + Summary: + This macro holds Length (in octets) of PAN ID + Description: + None + Remarks: + None + */ + +#define PAN_ID_LEN (2U) + +// ***************************************************************************** +/* ACK_PAYLOAD_LEN + + Summary: + This macro holds Length (in octets) of ACK payload + Description: + None + Remarks: + None + */ + +#define ACK_PAYLOAD_LEN (0x03U) + +// ***************************************************************************** +/* CONV_phyTransmitPower_TO_DBM + + Summary: + This macro holds Converts a phyTransmitPower value to a dBm value + return dBm using signed integer format + Description: + None + Remarks: + None + */ + +#define CONV_phyTransmitPower_TO_DBM(phyTransmitPower_value) \ + ( \ + ((phyTransmitPower_value & 0x20U) == 0x00U) ? \ + ((int8_t)(phyTransmitPower_value & 0x3FU)) : \ + ((-1) * \ + (int8_t)((~((uint8_t)((phyTransmitPower_value & \ + 0x1FU) - 1U))) & 0x1FU)) \ + ) + +// ***************************************************************************** +/* CONV_DBM_TO_phyTransmitPower + + Summary: + This macro Converts a dBm value to a phyTransmitPower value + and return phyTransmitPower_value using IEEE-defined format + Description: + None + Remarks: + None + */ + +#define CONV_DBM_TO_phyTransmitPower(dbm_value) \ + ( \ + dbm_value < -32 ? \ + 0x20U : \ + ( \ + dbm_value > 31 ? \ + 0x1FU : \ + ( \ + dbm_value < 0 ? \ + (((~((uint8_t)(((uint8_t)((-1) * dbm_value)) - 1U))) & 0x1FU) | 0x20U) : \ + (uint8_t)dbm_value \ + ) \ + ) \ + ) + + + +//DOM-IGNORE-BEGIN +#ifdef __cplusplus +} +#endif +//DOM-IGNORE-END + +#endif /* IEEE_CONST_H */ +/* EOF */ diff --git a/driver/software/RF233/phy/inc/phy.h b/driver/software/RF233/phy/inc/phy.h new file mode 100644 index 0000000..6f487ff --- /dev/null +++ b/driver/software/RF233/phy/inc/phy.h @@ -0,0 +1,2058 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +#ifndef PHY_H +#define PHY_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: File includes +// ***************************************************************************** +// ***************************************************************************** + +#include +#include +#include "phy_config.h" +#include "../../resources/buffer/inc/bmm.h" +#include "../../resources/queue/inc/qmm.h" +#include "ieee_phy_const.h" + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* PIB value types + + Summary: + Union of different PHY Pib value types + + Description: + PibValue_t is used as the data type to set/get the different PHY Information + Base value + + Remarks: + None +*/ + +typedef union { + /** PIB Attribute Bool */ + bool pib_value_bool; + /** PIB Attribute 8-bit */ + uint8_t pib_value_8bit; + /** PIB Attribute 16-bit */ + uint16_t pib_value_16bit; + /** PIB Attribute 32-bit */ + uint32_t pib_value_32bit; + /** PIB Attribute 64-bit */ + uint64_t pib_value_64bit; +} PibValue_t; + +// ***************************************************************************** +/* PHY Configuration Parameters + + Summary: + PHY Configuration parameters supported by transceiver + + Description: + Following are the list of configuration parameters which can be read from the + transceiver + + Remarks: + None + */ + +typedef enum param_tag { + /** Antenna Diversity */ + ANT_DIVERSITY = 0x00, + /** Antenna Configured - ANTENNA_1/ANTENNA_2*/ + ANT_SELECT_ = 0x01, + /** Antenna Control */ + ANT_CTRL_ = 0x02, + /** Promiscuous Mode*/ + AACK_PROMSCS_MODE = 0x03, + CC_BAND = 0x04, + CC_NUMBER = 0x05, + /** Tx Power Configured*/ + TX_PWR = 0x06, + /** Rx Sensitivity*/ + RX_SENS = 0x07, + /** RX Reduced Power Consumption*/ + RX_RPC = 0x08, + /** Automatic acknowledgement*/ + RX_AUTO_ACK = 0x09, + /** Reserved frame reception*/ + RX_RESERVED_FRAME = 0x0A, + /** Filter reserved frame*/ + FILTER_RESERVED_FRAME = 0x0B, +}PHY_ConfigParam_t; + +// ***************************************************************************** +/* PHY Frame information structure + + Summary: + PHY_FrameInfo_t holds the data to be transmitted or the data being received + by the transceiver. + + Description: + None + + Remarks: + None + */ + +typedef struct frame_info_tag +{ + /** Pointer to buffer header of frame */ + buffer_t *buffer_header; + /** Pointer to MPDU */ + uint8_t *mpdu; +} PHY_FrameInfo_t; + +// ***************************************************************************** +/* PHY Sleep Modes + + Summary: + Sleep Modes supported by transceiver + + Description: + List of sleep modes supported by the transceiver. If, TRX is set to SLEEP_MODE_1, + the TRX register contents are retained. If, TRX is set to DEEP_SLEEP_Mode + state the register contents are cleared + + Remarks: + None + */ + +typedef enum sleep_mode_tag { + SLEEP_MODE_1, +#ifdef ENABLE_DEEP_SLEEP + DEEP_SLEEP_MODE, +#endif +} PHY_SleepMode_t; + +// ***************************************************************************** +/* PHY CSMA Modes + + Summary: + List of carrier sense multiple access with collision avoidance + supported by PHY Layer + + Description: + When Transmit function is called with PHYCSMAMode of + NO_CSMA_NO_IFS - Immediate Tx and SIFS(Short InterFrameSpacing) between + subsequent frames + NO_CSMA_WITH_IFS - Immediate Tx and LIFS (Long InterFrameSpacing) between + subsequent frames + CSMA_UNSLOTTED - Hardware CSMA will be performed before packet transmission + with number of retries configured + CSMA_SLOTTED - Hardware CSMA will be performed - Used with Beacon + Enabled network - Currently not supported by PHY + Remarks: + None + */ + +typedef enum csma_mode_tag { + NO_CSMA_NO_IFS, + NO_CSMA_WITH_IFS, + CSMA_UNSLOTTED, + CSMA_SLOTTED +} PHY_CSMAMode_t; + +// ***************************************************************************** +/** Transceiver commands */ +typedef enum tfa_pib_tag { + TFA_PIB_RX_SENS = 0 +} PHY_tfa_pib_t; + +/* PHY Continuous Transmission test Modes + + Summary: + List of Continuous Transmission Test Modes supported by transceiver + + Description: + CW_MODE - Continuous Wave mode to transmit the signal at Fc +&- 0.5MHz frequency + PRBS_MODE - PRBS mode to Pseudorandom Binary Sequence frame continuously + + Remarks: + None + */ + +typedef enum continuous_tx_mode_tag { + /* Continuous Wave mode to transmit + * the signal at Fc +&- 0.5MHz frequency */ + CW_MODE = 0, + /* PRBS mode to Pseudorandom Binary Sequence frame continuously */ + PRBS_MODE = 1 +} PHY_ContinuousTxMode_t; + + +// ***************************************************************************** +/* PHY Return Values + + Summary: + List of return status for the PHY functions + + Description: + None + Remarks: + None + */ + +typedef enum phy_return_value_tag { + /* General Success condition*/ + PHY_SUCCESS = 0x00, + /* Transceiver is currently sleeping */ + PHY_TRX_ASLEEP = 0x81, + /* Transceiver is currently awake */ + PHY_TRX_AWAKE = 0x82, + /* General failure condition */ + PHY_FAILURE = 0x85, + /* PHY busy condition */ + PHY_BUSY = 0x86, + /* Frame pending at PHY */ + PHY_FRAME_PENDING = 0x87, + /*A parameter in the set/get request is either not supported or is out ofthe valid range*/ + PHY_INVALID_PARAMETER = 0x88, + /*A SET/GET request was issued with the identifier of a PIB attribute that is not supported */ + PHY_UNSUPPORTED_ATTRIBUTE = 0x89, + /* The CCA attempt has detected a busy channel.*/ + PHY_CHANNEL_BUSY = 0x8A, + /* The CCA attempt has detected an idle channel.*/ + PHY_CHANNEL_IDLE = 0x8B, + /* TRX received no ack for the previously sent packet*/ + PHY_NO_ACK = 0x8C, + /* Transmit is failed due to Channel access failure*/ + PHY_CHANNEL_ACCESS_FAILURE = 0x8D + +}PHY_Retval_t; + + // ***************************************************************************** +/* PHY Transceiver State Values + + Summary: + Enumeration for Transceiver States that can be set + + Description: + None + Remarks: + None + */ + +typedef enum phy_trx_state_tag{ + /* Transceiver to be configured to Transceiver OFF state*/ + PHY_STATE_TRX_OFF, + /* Transceiver to be configured to Receiver ON state */ + PHY_STATE_RX_ON +}PHY_TrxState_t; + + // ***************************************************************************** +/* PHY Transceiver Status Values + + Summary: + Enumeration for current state of the Transceiver + Description: + None + Remarks: + None + */ + +typedef enum phy_trx_status_tag{ + /* Transceiver is in Transceiver OFF state*/ + PHY_TRX_OFF = 0x08, + /* Transceiver is in Receiver ON state */ + PHY_RX_ON = 0x16, + /* Transceiver is in Transmit ON state */ + PHY_TX_ON = 0x19, + /* Transceiver is currently receiving the packet*/ + PHY_BUSY_RX = 0x11, + /* Transceiver is currently transmitting the packet */ + PHY_BUSY_TX = 0x12, + /* Transceiver is in sleep state */ + PHY_TRX_SLEEP = 0x0F, + /* Transceiver is in Deep sleep state */ + PHY_TRX_DEEP_SLEEP = 0x20 +}PHY_TrxStatus_t; + +// ***************************************************************************** +// ***************************************************************************** +// Section: Macros +// ***************************************************************************** +#define TFA_PIB_RX_SENS_DEF (RSSI_BASE_VAL_DBM) +// ***************************************************************************** + +// ***************************************************************************** +/* Custom PHY PIB attribute ID + + Summary: + Seting this attribute enables the device as PAN Coordinator + Description: + if only source addressing fields are included in a data or MAC command frame, + the frame shall be accepted only if the device is the PAN coordinator and + the source PAN identifier matches macPANId, for details refer to + IEEE 802.15.4-2006, Section 7.5.6.2 (third-level filter rule six + Remarks: + None + */ + +#define mac_i_pan_coordinator (0x0B) + +// ***************************************************************************** +/* Macro to convert Symbols to Microsecond + + Summary: + This macro function converts the given symbol value to microseconds + Description: + None + Remarks: + None + */ +#define PHY_CONVERT_SYMBOLS_TO_US(symbols) ((uint32_t)(symbols) << 4) + +// ***************************************************************************** +/* Macro to convert Microsecond to symbols + + Summary: + This macro function converts the given time in microseconds to symbols + Description: + None + Remarks: + None + */ +#define PHY_CONVERT_US_TO_SYMBOLS(time) ((time) >> 4) +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +// Section: Release Version Macros +// ***************************************************************************** +// ***************************************************************************** + + +/* Major Number + + Summary: + This macro holds the stack Major number + Description: + None + Remarks: + None + */ +#define MAJOR_NUM "1" + + +/* Minor Number + + Summary: + This macro holds the stack Minor number + Description: + None + Remarks: + None + */ +#define MINOR_NUM "0" + +/* Patch Number + + Summary: + This macro holds the stack patch number + Description: + None + Remarks: + None + */ +#define PATCH_NUM "0" + + +/* PHY Version + + Summary: + This macro holds the PHY SW version as a String + Description: + None + Remarks: + None + */ +#if (defined RC_NUM) +#define PHY_VER "802.15.4-PHY v" MAJOR_NUM"." MINOR_NUM"." PATCH_NUM"-rc." RC_NUM +#else +#define PHY_VER "802.15.4-PHY v" MAJOR_NUM"." MINOR_NUM"." PATCH_NUM +#endif + +/* Release version information in 32-bit bitfield + +| bit pos | field name | meaning | +|---------|-----------------|------------------------------ | +| 0-13 | reserved | NA | +| 14-17 | build itreation | running version of this release| +| 18-19 | qualifier | 00 - reserved | +| | | 01 - Production (P) | +| | | 10 - Engineering (E) | +| | | 11 - reserved | +| 20-23 | stack minor | minor version | +| 24-27 | stack major | major version | +| 28-31 | reserved | NA | + + +Example: + 802.15.4-PHY v1.0.0 is represented as 0x01040000 + +|0000 |0001 | 0000 | 01 | 0000 | 00000000000000| +|-----------|------------|-------------|-----------|----------------|---------------| +|Reserved | Stack Major| Stack Minor | Qualifier | Build Iteration| Reserved | +*/ + + +/* PHY Software Version Information in 32-bit bitfield + + Summary: + This macro holds PHY Software Version Information in 32-bit bitfield + Description: + None + Remarks: + None +*/ +#define PHY_VERSION_VALUE (0x01040000) + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY PIB Attribute List +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* PHY Information Base (PIB) Attribute list + +| PIB Attribute |AccessType| Type | DefaultValue | Range | +|---------------------|----------|---------|------------------|-----------------| +| phyCurrentChannel | Get/Set | uint8_t | 11 | 11 - 26 | +| phyChannelsSupported| Get | uint32_t| 0x07FFF800 | NA | +| phyCurrentPage | Get/Set | uint8_t | 0 | 0,2,16,17 | +| phyTransmitPower | Get/Set | uint8_t | 4 | | +| phyCCAMode | Get/Set | uint8_t | 1 | 0 - 3 | +| macIeeeAddress | Get/Set | uint64_t| All 0's | NA | +| macShortAddress | Get/Set | uint16_t| 0xFFFF | 0x0000 - 0xFFFF | +| macPANId | Get/Set | uint16_t| 0xFFFF | 0x0000 - 0xFFFF | +| macMinBE | Get/Set | uint8_t | 3 | 0 - 3 | +| macMaxBE | Get/Set | uint8_t | 5 | 3 - 8 | +| macMaxCSMABackoffs | Get/Set | uint8_t | 4 | 0 - 5 | +| macMaxFrameRetries | Get/Set | uint8_t | 3 | 0 - 7 | +| macPromiscuousMode | Get/Set | bool | 0 | 0 or 1 | +| phySHRDuration | Get | uint8_t | 10 Symbols | NA | +| phySymbolsPerOctet | Get | uint8_t | 2 Symbols | NA | +| phyMaxFrameDuration | Get | uint16_t| 266 Symbols | NA | +| macIpanCoordinator | Get/Set | bool | 0 | 0 or 1 | + */ + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY Task Handler Funtions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + void PHY_TaskHandler ( void ) + + Summary: + PHY Task Handling routine + + Description: + This function + - Checks and allocates the receive buffer. + - Processes the PHY incoming frame queue. + - Implements the PHY state machine. + + Precondition: + PHY_Init should be called before calling this function + + Parameters: + None. + + Returns: + None. + + Example: + + PHY_TaskHandler(); + + + Remarks: + This routine must be called from the RTOS Task function incase of any + RTOS is used. +*/ +void PHY_TaskHandler(void); + +// ***************************************************************************** +/* + Function: + void TAL_TaskHandler ( void ) + + Summary: + TAL Task Handling routine + + Description: + This function handles the transceiver interrupt + + Precondition: + PHY_Init should be called before calling this function + + Parameters: + None. + + Returns: + None. + + Example: + + TAL_TaskHandler(); + + + Remarks: + This routine must be called from the RTOS Task function incase of any + RTOS is used. +*/ +void TAL_TaskHandler(void); + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY Initialization and Reset Routines +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_Init( void ) + + Summary: + Initialization of PHY Layer + + Description: + This function is called to initialize the PHY layer. The transceiver is + initialized and it will be in PHY_STATE_TRX_OFF, the PHY PIBs are set to + their default values. PAL layer is initialized + + Precondition: + SYS_Load_Cal(WSS_ENABLE_ZB) function of device support library should be + called before calling this function. + + Parameters: + None. + + Returns: + PHY_SUCCESS - If the transceiver state is changed to TRX_OFF + PHY_FAILURE - Otherwise + + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + + retVal = PHY_Init(); + if (PHY_SUCCESS =! retVal) + { + while(1); + } + + + Remarks: + This routine must be called before any of the PHY function is called +*/ +PHY_Retval_t PHY_Init(void); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_Reset( bool setDefaultPibs ) + + Summary: + Resets the PHY Layer + + Description: + This function is called to Resets PHY state machine + and sets the default PIB values if requested + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + setDefaultPibs - Defines whether PIB values need to be set + to its default values + + Returns: + PHY_SUCCESS - If the transceiver state is changed to TRX_OFF and PIBs are set + to their default value + PHY_FAILURE - Otherwise + + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + bool setDefault = false; + + retVal = PHY_Reset(setDefault); + if (PHY_SUCCESS =! retVal) + { + while(1); + } + + + Remarks: + None +*/ + +PHY_Retval_t PHY_Reset(bool set_default_pib); + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY Tranmission Routines +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_TxFrame(PHY_FrameInfo_t *txFrame, PHY_CSMAMode_t csmaMode, + bool performFrameRetry) + + Summary: + Request to PHY to transmit frame + + Description: + This function is called by the upper layer (MAC/Application) to deliver a + frame to the PHY to be transmitted by the transceiver. + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + txFrame - Pointer to the PHY_FrameInfo_t structure or + to frame array to be transmitted + txFrame->mpdu - Pointer to the PHY Payload. mpdu[0] should hold + the length of the payload(N) + 1 (for length field length) + txFrame->mpdu[1-N] - Hold the phyPayload + + csmaMode - Indicates mode of csma-ca to be performed for this frame + NO_CSMA_NO_IFS - Immediate Tx and SIFS(Short InterFrameSpacing) + between subsequent frames + NO_CSMA_WITH_IFS - Immediate Tx and LIFS (Long InterFrameSpacing) + between subsequent frames + CSMA_UNSLOTTED - Hardware CSMA will be performed before packet + transmission with number of retries configured + CSMA_SLOTTED - Hardware CSMA will be performed - Used with + Beacon Enabled network - Currently not supported + by PHY + performFrameRetry - Indicates whether to retries are to be performed + for this frame + true - SW retry will be performed for macMaxFrameRetries + value + false- SW retry is disabled + + Returns: + PHY_SUCCESS - If PHY has accepted the data from the MAC for frame + transmission + PHY_BUSY - If PHY is busy servicing the previous MAC request + + Example: + + uint8_t txBuffer[LARGE_BUFFER_SIZE]; + uint8_t txData[] = "Wireless!!!"; + PHY_CSMAMode_t csmaMode = CSMA_UNSLOTTED; + bool performRetry = true; + PHY_FrameInfo_t txFrame; + + txFrame.mpdu = txBuffer; + txBuffer[0] = sizeof(txData); + memcpy((uint8_t *)&txBuffer[1], txData, sizeof(txData)); + + if(PHY_SUCCESS == PHY_TxFrame(&txFrame, csmaMode, performRetry)) + { + Frame transmitted successfully + } + + + Remarks: + None +*/ +PHY_Retval_t PHY_TxFrame(PHY_FrameInfo_t *txFrame, PHY_CSMAMode_t csmaMode, + bool performFrameRetry); + +// ***************************************************************************** +/* + Function: + void PHY_TxDoneCallback(PHY_Retval_t status, PHY_FrameInfo_t *frame) + + Summary: + User callback function for the transmission of a frame + + Description: + This callback function SHOULD be defined by the upper layer(Application/MAC) + for getting the status of last transmitted packet. + + Precondition: + This is a Asynchronous function call for the transmission of a frame + + Parameters: + status - Status of frame transmission attempt + PHY_SUCCESS - The transaction was responded to by a valid ACK, + or, if no ACK is requested, after a successful + frame transmission. + PHY_FRAME_PENDING - Equivalent to SUCCESS and indicating that + the ?Frame Pending? bit of the received + acknowledgment frame was set. + PHY_CHANNEL_ACCESS_FAILURE - Channel is still busy after attempting + MAX_CSMA_RETRIES of CSMA-CA. + PHY_NO_ACK - No acknowledgement frames were received + during all retry attempts. + PHY_FAILURE - Transaction not yet finished. + PHY_RF_REQ_ABORTED - RF is busy performing Higher priority BLE task + and the transmission is aborted + PHY_RF_UNAVAILABLE - RF is currently unavailable for 15.4 subsystem + + frame - Pointer to the PHY_FrameInfo_t structure or + to frame array to be transmitted + txFrame->mpdu - Pointer to the PHY Payload. mpdu[0] should hold + the length of the payload(N) + 1 (for length field length) + txFrame->mpdu[1-N] - Hold the phyPayload + + Returns: + None + + Example: + + void PHY_TxDoneCallback(PHY_Retval_t status, PHY_FrameInfo_t *frame) + { + Keep compiler happy. + status = status; + frame = frame; + } + + + Remarks: + None +*/ +void PHY_TxDoneCallback(PHY_Retval_t status, PHY_FrameInfo_t *frame); + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY Energy Detaction Functions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_EdStart(uint8_t scan_duration) + + Summary: + Starts ED Scan + + Description: + This function starts an ED Scan for the scan duration specified by the + upper layer. Actual ED result of Energy level on current channel will be + indicated by PHY_EdEndCallback(eneryLevel). + Scan duration formula: aBaseSuperframeDuration * (2^SD + 1) symbols + where SD - scanDuration parameter (0 - 14) + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + scanDuration - Specifies the ED scan duration in symbols + Range - (0 to 14) + + Returns: + PHY_SUCCESS - ED scan is started successfully + PHY_BUSY - PHY is busy servicing the previous request + PHY_TRX_ASLEEP - Transceiver is currently sleeping, wakeup the transceiver + using PHY_TrxWakeup() function + PHY_FAILURE otherwise + + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + uint8_t scanDurationSym = 1; + + retVal = PHY_EdStart(scanDurationSym); + if (PHY_SUCCESS =! retVal) + { + ED scan cannot be started at this moment + } + + + Remarks: + PHY_EdEndCallback(energyLevel) will be called after scanning the current + channel for a time period of aBaseSuperframeDuration * (2^scanDuration + 1) symbols + For scanDuration of value 0, ScanTime = 960 *(2^0 +1) + = 1920 symbols = 30720 us +*/ +PHY_Retval_t PHY_EdStart(uint8_t scan_duration); + +// ***************************************************************************** +/* + Function: + void PHY_EdEndCallback(uint8_t energyLevel) + + Summary: + User callback function for Energy detection + + Description: + This function SHOULD be defined by the upperlayer (Application/MAC layer) + in order to get the energyLevel on the current channel which is being scanned + for a period of scanDuration symbols + + Precondition: + This is an Asynchronous function call for the energy scan complete + + Parameters: + energyLevel - Measured energy level during ED Scan + + With energy_level, the RF input power can be calculated as follows + PRF[dBm] = RSSI_BASE_VAL[dBm] + 1[dB] x energy_level + + Returns: + None + + Example: + + void PHY_EdEndCallback(uint8_t energyLevel) + { + int8_t energyLeveldBm = (int8_t) (PHY_GetRSSIBaseVal() + energyLevel); + energyLevel = energyLevel; + } + + + Remarks: + None +*/ +void PHY_EdEndCallback(uint8_t energyLevel); + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY Information Base Set/Get Functions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_PibGet(uint8_t attribute, uint8_t *value) + + Summary: + Gets a PHY PIB attribute + + Description: + This function is called to retrieve the transceiver information base + attributes. The list of PHY PIB attributes, its default values and + range are described in the above table. + For more information refer ieee_phy_const.h file + + Precondition: + PHY_init() should have been called before calling this function. + + Parameters: + attribute - PHY infobase attribute ID + value - Pointer to the PHY infobase attribute value + + Returns: + PHY_UNSUPPORTED_ATTRIBUTE - If the PHY infobase attribute is not found + PHY_SUCCESS - otherwise + + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + uint8_t phyChannel; + uint8_t shortAddr; + + Getting Current channel + retVal = PHY_PibGet(phyCurrentChannel, &phyChannel); + if(PHY_SUCCESS == retVal) + { + printf("\r\n PHY Current Channel - %d",phyChannel ); + } + + Getting short Address + retVal = PHY_PibGet(macShortAddr, &shortAddr); + if(PHY_SUCCESS == retVal) + { + printf("\r\n Device short addr - 0x%x",shortAddr ); + } + + + + Remarks: + None +*/ +PHY_Retval_t PHY_PibGet(uint8_t attribute, uint8_t *value); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_PibSet(uint8_t attribute, PibValue_t *value) + + Summary: + Sets the PHY PIB attribute with value + + Description: + This function is called to set the transceiver information base + attributes. The list of PHY PIB attributes, its default values and + range are described in the above table. + For more information refer ieee_phy_const.h file + + Precondition: + PHY_init() should have been called before calling this function. + + Parameters: + attribute - PHY infobase attribute ID + value - Pointer to the PHY infobase attribute value to be set + + Returns: + PHY_UNSUPPORTED_ATTRIBUTE - if the PHY info base attribute is not + found + PHY_BUSY - If the PHY is not in PHY_IDLE state. An exception is + macBeaconTxTime which can be accepted by PHY even if PHY is not + in PHY_IDLE state. + PHY_SUCCESS - If the attempt to set the PIB attribute was successful + PHY_TRX_ASLEEP - If trx is in SLEEP mode and access to trx is + required + + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + uint8_t phyChannel = 15; + uint8_t shortAddr = 0x1234; + PibValue_t pibValue; + + Setting Current channel + pibValue.pib_value_8bit = phyChannel; + retVal = PHY_PibSet(phyCurrentChannel, &pibValue); + if(PHY_SUCCESS == retVal) + { + Channel is configured + } + + Setting short Address + pibValue.pib_value_16bit = shortAddr; + retVal = PHY_PibSet(macShortAddr, &pibValue); + if(PHY_SUCCESS == retVal) + { + Short Address is configured + } + + + + Remarks: + None +*/ +PHY_Retval_t PHY_PibSet(uint8_t attribute, PibValue_t *value); + + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY Reception Functions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + PHY_TrxStatus_t PHY_RxEnable(PHY_TrxState_t state) + + Summary: + Switches receiver on or off + + Description: + This function switches the receiver on (PHY_STATE_RX_ON) or off (PHY_STATE_TRX_OFF) + + Precondition: + PHY_init() should have been called before calling this function. + + Parameters: + state - State of the Transceiver to be set + PHY_STATE_RX_ON - Transceiver will be put into Receive state + PHY_STATE_TRX_OFF - Transceiver will be put into OFF state + + Returns: + PHY_TRX_OFF- If receiver has been switched off, or + PHY_RX_ON - otherwise. + + Example: + + PHY_TrxStatus_t trxStatus; + PHY_TrxState_t trxState = PHY_STATE_RX_ON; + + trxStatus = PHY_RxEnable(trxState); + if(PHY_RX_ON == trxStatus) + { + TRX is in receive state + } + + + Remarks: + None +*/ +PHY_TrxStatus_t PHY_RxEnable(PHY_TrxState_t state); + +// ***************************************************************************** +/* + Function: + void PHY_RxFrameCallback(PHY_FrameInfo_t *rxFrame) + + Summary: + User callback function for the reception of a frame + + Description: + This callback function SHOULD be defined by the upper layer(Application/MAC) + for getting the received frame details + + Precondition: + This is a Asynchronous function call for the reception of a frame + + Parameters: + rxFrame - Pointer to received frame structure of type PHY_FrameInfo_t + or to received frame array + rxFrame->buffer_header - BMM Buffer Header of the frame + rxFrame->mpdu - Actual MPDU comprises of + mpdu[0] - Payload Length(N) + mpdu[1-N]- Payload + mpdu[N+1]- LQI of received packet + mpdu[N+2]- ED_LEVEL of received packet + + Returns: + None + + Example: + + uint8_t rxBuffer[LARGE_BUFFER_SIZE]; + uint8_t frameLen, frameLQI, frameED; + int8_t frameRSSI; + void PHY_RxFrameCallback(PHY_FrameInfo_t *frame) + { + printf("\n--RxCallbackreceived--"); + frameLen = frame->mpdu[0]; + Copy the payload + memcpy(rxBuffer, (uint8_t *)&(frame->mpdu[1]), frameLen); + Copy the LQI + frameLQI = frame->mpdu[frameLen+LQI_LEN]; + Copy the RSSI + frameED = frame->mpdu[frameLen+LQI_LEN+ED_VAL_LEN]; + + frameRSSI = (int8_t)(frameED + PHY_GetRSSIBaseVal()); + + free the buffer that was used for frame reception + bmm_buffer_free((buffer_t *)(frame->buffer_header)); + } + + + Remarks: + None +*/ +void PHY_RxFrameCallback(PHY_FrameInfo_t *rxFrame); + + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY TRX Power Management Functions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_TrxSleep(PHY_SleepMode_t mode) + + Summary: + Sets the transceiver to sleep + + Description: + This function sets the transceiver to sleep or deep sleep state. + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + mode - Defines sleep mode of transceiver SLEEP or DEEP_SLEEP + + Returns: + PHY_BUSY - The transceiver is busy in TX or RX + PHY_SUCCESS - The transceiver is put to sleep + PHY_TRX_ASLEEP - The transceiver is already asleep + + Example: + + PHY_SleepMode_t sleepMode = SLEEP_MODE_1; + bool trxSleepStatus = false; + + if (PHY_SUCCESS == PHY_TrxSleep(sleepMode)) + { + trxSleepStatus = true; + } + + + Remarks: + When TRX is put into DeepSleep, the TRX registers are reset and it will hold + default values, PIB values are getting written by PHY layer when Wakeup + function is called.User has to reconfigure the configuration parameters + (PHY_ConfigParam_t) which are set by application. This procedure is not + needed for SLEEP mode as the TRX register values are retained. +*/ +PHY_Retval_t PHY_TrxSleep(PHY_SleepMode_t mode); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_TrxWakeup(void) + + Summary: + Wakes up the transceiver from sleep + + Description: + This function awakes the transceiver from sleep state. + + Precondition: + PHY_TrxSleep() should have been called before calling this function + + Parameters: + None + + Returns: + PHY_TRX_AWAKE - The transceiver is already awake + PHY_SUCCESS - The transceiver is woken up from sleep + PHY_FAILURE - The transceiver did not wake-up from sleep + + Example: + + PHY_SleepMode_t sleepMode = SLEEP_MODE_1; + bool trxSleepStatus = false; + Set Transceiver to sleep + if (PHY_SUCCESS == PHY_TrxSleep(sleepMode)) + { + trxSleepStatus = true; + } + wakeup the transceiver + if (PHY_SUCCESS == PHY_TrxWakeup()) + { + trxSleepStatus = false; + } + + + Remarks: + When TRX is put into DeepSleep, the TRX registers are reset and it will hold + default values, PIB values are getting written by PHY layer when Wakeup + function is called.User has to reconfigure the configuration parameters + (PHY_ConfigParam_t) which are set by application. This procedure is not + needed for SLEEP mode as the TRX register values are retained. +*/ +PHY_Retval_t PHY_TrxWakeup(void); + +/* + * \brief Generates a 16-bit random number used as initial seed for srand() + * + * This function generates a 16-bit random number by means of using the + * Random Number Generator from the transceiver. + * The Random Number Generator generates 2-bit random values. These 2-bit + * random values are concatenated to the required 16-bit random seed. + * + * The generated random 16-bit number is feed into function srand() + * as initial seed. + * + * The transceiver state is initally set to RX_ON. + * After the completion of the random seed generation, the + * trancseiver is set to TRX_OFF. + * + * As a prerequisite the preamble detector must not be disabled. + * + * Also in case the function is called from a different state than TRX_OFF, + * additional trx state handling is required, such as reading the original + * value and restoring this state after finishing the sequence. + * Since in our case the function is called from TRX_OFF, this is not required + * here. + */ + + void tal_generate_rand_seed(void); + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY TRX Feature Access Functions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + uint8_t PHY_EdSample(void) + + Summary: + Perform a single ED measurement on current channel + + Description: + This function is used to measure the energy level on current channel + + Precondition: + PHY_Init() should have been called before calling this function. + + Parameters: + None + + Returns: + edValue - Result of the measurement + + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + uint8_t phyChannel = 15; + uint8_t edLevel; + int8_t pwrDbm; + PibValue_t pibValue; + + Setting Current channel + pibValue.pib_value_8bit = phyChannel; + retVal = PHY_PibSet(phyCurrentChannel, &pibValue); + if(PHY_SUCCESS == retVal) + { + Take the Ed sample + edLevel = PHY_EdSample(); + Convert the energy level to input power in Dbm + pwrDbm = (int8_t)(edLevel + PHY_GetRSSIBaseVal()); + } + + + + Remarks: + PHY_EdSample scans the channel for 8 symbols(128us) and returns the energy level +*/ +uint8_t PHY_EdSample(void); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_CCAPerform(void) + + Summary: + Perform a clear channel assessment + + Description: + This function is used to perform a clear channel assessment on current channel. + using configured CCA mode (can be set using PHY_PibSet of phyCCAMode). + This results in the status of channel is current busy or Idle. + + The different CCA modes supported by Transceiver are + The CCA mode + - CCA Mode 1: Energy above threshold. CCA shall report a busy medium + upon detecting any energy above the ED threshold. + - CCA Mode 2: Carrier sense only. CCA shall report a busy medium only upon + the detection of a signal with the modulation and spreading characteristics + of IEEE 802.15.4. This signal may be above or below the ED threshold. + - CCA Mode 3: Carrier sense with energy above threshold. CCA shall report a + busy medium only upon the detection of a signal with the modulation and + spreading characteristics of IEEE 802.15.4 with energy above the ED + threshold. + + Precondition: + PHY_Init() should have been called before calling this function. + + Parameters: + None + + Returns: + PHY_Retval_t - PHY_CHANNEL_IDLE or PHY_CHANNEL_BUSY + PHY_CHANNEL_IDLE - The CCA attempt has detected an idle channel + PHY_CHANNEL_BUSY - The CCA attempt has detected a busy channel + + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + uint8_t phyChannel = 15; + PibValue_t pibValue; + bool isChIdle = false; + + Setting Current channel + pibValue.pib_value_8bit = phyChannel; + retVal = PHY_PibSet(phyCurrentChannel, &pibValue); + if(PHY_SUCCESS == retVal) + { + Take the Ed sample + retVal = PHY_CCAPerform(); + if (PHY_CHANNEL_IDLE == retVal) + { + isChIdle = true; + } + } + + + + Remarks: + None +*/ +PHY_Retval_t PHY_CCAPerform(void); + + + +// ***************************************************************************** +/** + * @brief Initializes the TFA + * + * This function is called to initialize the TFA. + * + * @return MAC_SUCCESS if everything went correct; + * FAILURE otherwise + * + * @ingroup apiTfaApi + */ +PHY_Retval_t tfa_init(void); + +/** + * @brief Reset the TFA + * + * This function is called to reset the TFA. + * + * @param set_default_pib Defines whether PIB values need to be set + * to its default values + * + * @ingroup apiTfaApi + */ +void tfa_reset(bool set_default_pib); + +/** + * @brief Gets a TFA PIB attribute + * + * This function is called to retrieve the transceiver information base + * attributes. + * + * @param[in] tfa_pib_attribute TAL infobase attribute ID + * @param[out] value TFA infobase attribute value + * + * @return MAC_UNSUPPORTED_ATTRIBUTE if the TFA infobase attribute is not found + * MAC_SUCCESS otherwise + * + * @ingroup apiTfaApi + */ +PHY_Retval_t tfa_pib_get(PHY_tfa_pib_t tfa_pib_attribute, void *value); + +/** + * @brief Sets a TFA PIB attribute + * + * This function is called to set the transceiver information base + * attributes. + * + * @param[in] tfa_pib_attribute TFA infobase attribute ID + * @param[in] value TFA infobase attribute value to be set + * + * @return MAC_UNSUPPORTED_ATTRIBUTE if the TFA info base attribute is not found + * TAL_BUSY if the TAL is not in TAL_IDLE state. + * MAC_SUCCESS if the attempt to set the PIB attribute was successful + * + * @ingroup apiTfaApi + */ +PHY_Retval_t tfa_pib_set(PHY_tfa_pib_t tfa_pib_attribute, void *value); + +/* + Function: + void PHY_StartContinuousTransmit(PHY_ContinuousTxMode_t txMode, + bool randomContent) + + Summary: + Starts continuous transmission on current channel + + Description: + This function is called to start the continuous transmission on current + channel. + + Precondition: + PHY_Init() should have been called before calling this function. + + Parameters: + txMode - Mode of continuous transmission + CW_MODE - Continuous Wave mode to transmit + the signal at Fc +&- 0.5MHz frequency + PRBS_MODE - PRBS mode to Pseudorandom Binary Sequence frame + continuously + randomContent - Use random content if true + + Returns: + None + + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + uint8_t phyChannel = 15; + PHY_ContinuousTxMode_t txMode = CW_MODE; + bool useRandomContent = false; + PibValue_t pibValue; + + Setting Current channel + pibValue.pib_value_8bit = phyChannel; + retVal = PHY_PibSet(phyCurrentChannel, &pibValue); + if(PHY_SUCCESS == retVal) + { + Start continuous tx in CW mode + PHY_StartContinuousTransmit(txMode, useRandomContent); + } + + + + Remarks: + None +*/ +void PHY_StartContinuousTransmit(PHY_ContinuousTxMode_t txMode, + bool randomContent); +// ***************************************************************************** +/* + Function: + void PHY_StopContinuousTransmit(void) + + Summary: + Stops the continuous transmission on the current channel + + Description: + This function is called to stop the continuous transmission + + Precondition: + PHY_Init() should have been called before calling this function. + This function will stop the continuous transmission which is started by + PHY_StartContinuousTransmit()function. + + Parameters: + None + + Returns: + None + + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + uint8_t phyChannel = 15; + PHY_ContinuousTxMode_t txMode = PRBS_MODE; + bool useRandomContent = true; + bool contTxStarted = false; + PibValue_t pibValue; + + Setting Current channel + pibValue.pib_value_8bit = phyChannel; + retVal = PHY_PibSet(phyCurrentChannel, &pibValue); + if(PHY_SUCCESS == retVal) + { + Start continuous tx in CW mode + PHY_StartContinuousTransmit(txMode, useRandomContent); + contTxStarted = true; + } + + if(contTxStarted) + { + Stop continuous tx + PHY_StopContinuousTransmit(); + } + + + Remarks: + When continuous tx is stopped, the PHY_Reset function is called. + User has to reconfigure the configuration parameters + (PHY_ConfigParam_t) which are set by application. +*/ +void PHY_StopContinuousTransmit(void); + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY TRX Configuration Functions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_ConfigTxPwr(bool type, int8_t pwrValue) + + Summary: + Configures the TX Power in Transceiver + + Description: + This function is used to configure the Transmit power of the transceiver + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + type - PWR_REGISTER_VALUE or PWR_DBM_VALUE + pwrValue - Index of the power register value (0-15) or Power value in dBm + If LPA is enabled - Pmax - +5.5 dBm to Pmin - (-14)dbm + If LPA&MPA enabled - Pmax - +12 dBm to Pmin - (-16)dbm + + Returns: + PHY_SUCCESS - If pwrValue bit is configured correctly + PHY_FAILURE - Otherwise + + Example: + + bool pwrType = PWR_REGISTER_VALUE; + uint8_t pwrIndex = 0x00; + bool configStatus = false; + Set Tx Power with Register Index value + if (PHY_SUCCESS == PHY_ConfigTxPwr(pwrType, int8_t (pwrIndex))) + { + configStatus = true; + } + + Set Tx Power with dBm value + int8_t pwrDbm = -17; + pwrType = PWR_DBM_VALUE; + if (PHY_SUCCESS == PHY_ConfigTxPwr(pwrType, int8_t (pwrDbm))) + { + configStatus = true; + } + + uint8_t pwrReg; + To get the tx power index value configured in the TRX + PHY_GetTrxConfig(TX_PWR, &pwrReg); + + + Remarks: + None . +*/ +PHY_Retval_t PHY_ConfigTxPwr(bool type, int8_t pwrValue); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_ConfigAntennaDiversity(bool divCtrl, uint8_t antCtrl) + + Summary: + Configures antenna diversity and selects antenna + + Description: + This function is used to enable the Antenna Diversity feature and + to select the antenna path if the feature is disabled. + Antenna Diversity uses two antennas to select the most reliable RF signal path. + To ensure highly independent receive signals on both antennas, + the antennas should be carefully separated from each other. + If a valid IEEE 802.15.4 frame is detected on one antenna, this antenna is + selected for reception. Otherwise the search is continued on the other antenna + and vice versa. + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + divCtrl - true/false to enable/disable antenna diversity algorithm + antCtrl - 0 or 3 when antenna diversity is enabled + 1 or 2 to select antenna 1 or antenna 2 + + Returns: + PHY_SUCCESS - If Antenna Diversity/ Control bits are configured correctly + PHY_FAILURE - otherwise + + Example: + + bool antDiv = ANTENNA_DIVERSITY_DISABLE; + uint8_t antennaSel = ANTENNA_CTRL_1; + + Antenna Diversity is disabled and Antenna 1 is selected for rx/tx path + PHY_ConfigAntennaDiversity(antDiv, antennaSel); + + To get the antenna diversity value configured in the TRX + PHY_GetTrxConfig(ANT_DIV, &antDiv); + To get antenna selected for rx/tx + PHY_GetTrxConfig(ANT_SELECT, &antennaSel); + + + Remarks: + None +*/ +PHY_Retval_t PHY_ConfigAntennaDiversity(bool divCtrl, uint8_t antCtrl); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_ConfigRxSensitivity(uint8_t pdtLevel) + + Summary: + Configures receiver sensitivity level. This is used to desensitize + the receiver + + Description: + This function is used to reduce the sensitivity of the receiver. + The input pdtLevel(Power Detect Level) desensitize the receiver such that + frames with an RSSI level below the pdtLevel threshold level (if pdtLevel > 0) + are not received. For a pdtLevel > 0 value the threshold level can be + calculated according to the following formula: + PRF[dBm] > RSSIBASE_VAL[dBm] + 3[dB] x (pdtLevel - 1) + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + pdtLevel - 0 to 15 levels of rx sensitivity(RX_PDT_LEVEL) + + + Returns: + PHY_SUCCESS - If pdtLevel bits are configured correctly + PHY_FAILURE - otherwise + + Example: + + uint8_t pdtLevel = 0x03; + + Reduce the PDT level + PHY_ConfigRxSensitivity(pdtLevel); + + To get the PDT level configured + PHY_GetTrxConfig(RX_SENS, &pdtLevel); + + + + Remarks: + None +*/ +PHY_Retval_t PHY_ConfigRxSensitivity(uint8_t pdtLevel); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_ConfigRxPromiscuousMode(bool promCtrl) + + Summary: + Configures RX promiscuous mode + + Description: + This function is used to enable the RX promiscuous mode. The TRX will receive + all frames even with FCS failure, PHY layer will discard the CRC invalid packet + and TRX will not acknowledge even ack is requested by the received + packet(auto ack is disabled in this mode). + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + promCtrl - true - To enable promiscuous mode + false - To disable promiscuous mode + + Returns: + PHY_SUCCESS - If promCtrl bits are configured correctly + PHY_FAILURE - otherwise + + Example: + + bool promCtrl = true; + + Enable Promiscuous mode + PHY_ConfigRxPromiscuousMode(promCtrl); + + To get the PDT level configured + PHY_GetTrxConfig(AACK_PROMSCS_MODE, &promCtrl); + + + + Remarks: + None +*/ +PHY_Retval_t PHY_ConfigRxPromiscuousMode(bool promCtrl); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_ConfigRxRPCMode(uint8_t rxRPCEnable) + + Summary: + Configures the reduced power consumption mode + + Description: + The function is used to configure the reduced power consumption mode of the receiver + + Precondition: + PHY_Init() should have been called before calling this function. + + Parameters: + rxRPCEnable - 0x01 - to enable the rx RPC mode + 0x00 - to disable the rx RPC mode + + + Returns: + PHY_Retval_t - PHY_SUCCESS If trx is configured correctly + * PHY_FAILURE otherwise + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + uint8_t rxRPCEnable = 0x01; + + retVal = PHY_ConfigRxRPCMode(rxRPCEnable); + if(PHY_SUCCESS == retVal) + { + Trx is configured to reduced power consumption mode + } + + + Remarks: + None +*/ +PHY_Retval_t PHY_ConfigRxRPCMode(uint8_t rxRPCEnable); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_ConfigAutoAck(bool enableAACK) + + Summary: + Configures TRX for auto acknowledging the reserved frame + + Description: + The function is used to configure the automatic acknowledgment from + Transceiver after packet reception. + + Precondition: + PHY_Init() should have been called before calling this function. + + Parameters: + nableAACK - true - to enable the automatic + acknowledgment after reception + false - to disable the automatic + acknowledgment after reception + + + Returns: + PHY_Retval_t - PHY_SUCCESS If trx is configured correctly + * PHY_FAILURE otherwise + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + bool isEnableAACK = true; + + retVal = PHY_ConfigAutoAck(isEnableAACK); + if(PHY_SUCCESS == retVal) + { + Trx is configured to auto acknowledge for the received packet + } + + + Remarks: + None +*/ +PHY_Retval_t PHY_ConfigAutoAck(bool enableAACK); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_ConfigReservedFrameFiltering(bool recReservedFrame, + bool bypassFrameFilter ) + + Summary: + Configures TRX for receiving reserved frame + + Description: + This function is used to configure the trx for receiving the reserved frame + type frames and to enable/disable the frame filtering . + + Precondition: + PHY_Init() should have been called before calling this function. + + Parameters: + recReservedFrame - true to enable the reception of reserved frame types + acknowledgment after reception + bypassFrameFilter - true to bypass the frame filtering at the hardware + level like data frame as specified in IEEE specification + + Returns: + PHY_Retval_t - PHY_SUCCESS If trx is configured correctly + * PHY_FAILURE otherwise + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + bool rxResFrame = true; + bool bypassFrameFiltering = false; + + retVal = PHY_ConfigReservedFrameFiltering(rxResFrame, bypassFrameFiltering); + if(PHY_SUCCESS == retVal) + { + Trx is configured to receive the reserved frame and to do the frame + filtering as stated in IEEE Spec + } + + + Remarks: + None +*/ +PHY_Retval_t PHY_ConfigReservedFrameFiltering(bool recReservedFrame, + bool bypassFrameFilter ); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_GetTrxConfig(PHY_ConfigParam_t parameter, uint8_t *paramValue) + + Summary: + To read a current setting of particular transceiver parameter + + Description: + The function is used to read the current of particular parameter. + The following parameters can be read from TRX, + Antenna Diversity + ANT_DIVERSITY + Antenna Configured - ANTENNA_1/ANTENNA_2 + ANT_SELECT + Antenna Control + ANT_CTRL + Promiscuous Mode + AACK_PROMSCS_MODE + Tx Power Configured + TX_PWR + Rx Sensitivity + RX_SENS + RX Reduced Power Consumption + RX_RPC + Automatic acknowledgement + RX_AUTO_ACK + Reserved frame reception + RX_RESERVED_FRAME + Filter reserved frame + FILTER_RESERVED_FRAME + + Precondition: + PHY_Init() should have been called before calling this function. + + Parameters: + parameter - Type of the parameter to be read + paramValue - Pointer to the current parameter value + + Returns: + PHY_Retval_t - PHY_INVALID_PARAMETER If the parameter is invalid + - PHY_SUCCESS otherwise + Example: + + PHY_Retval_t retVal = PHY_FAILURE; + bool promCtrl = true; + + To get the promiscuous mode configured + PHY_GetTrxConfig(AACK_PROMSCS_MODE, (uint8_t *)&promCtrl); + + + Remarks: + None +*/ +PHY_Retval_t PHY_GetTrxConfig(PHY_ConfigParam_t parameter, uint8_t *paramValue); + + +// ***************************************************************************** +// ***************************************************************************** +// Section: PHY Utility Functions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + PHY_TrxStatus_t PHY_GetTrxStatus(void) + + Summary: + Returns the current status of the Transceiver + + Description: + This function gets the status of the transceiver + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + None + + Returns: + PHY_TRX_OFF - The transceiver is in TRX_OFF state + PHY_RX_ON - The transceiver is in receive state + PHY_TX_ON - The transceiver is in Transmit state + PHY_BUSY_RX - The transceiver currently receiving the packet + PHY_BUSY_TX - The transceiver is currently transmitting the packet + PHY_TRX_SLEEP - The transceiver is in sleep state + PHY_DEEP_SLEEP - The transceiver is in Deep sleep state + + Example: + + PHY_TrxStatus_t trxStatus; + Gets the current status of trx + trxStatus = PHY_GetTrxStatus(); + + + + Remarks: + None . +*/ +PHY_TrxStatus_t PHY_GetTrxStatus(void); + +// ***************************************************************************** +/* + Function: + int8_t PHY_GetRSSIBaseVal(void) + + Summary: + Get RSSI base value of TRX + + Description: + This function is called to get the base RSSI value for respective + radios + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + None + + Returns: + 32-bit PHY SW version value + + Example: + + int8_t trxBaseRSSI; + + Get RSSI base value of TRX + trxBaseRSSI = PHY_GetRSSIBaseVal(); + + + + Remarks: + None +*/ +int8_t PHY_GetRSSIBaseVal(void); + +// ***************************************************************************** +/* + Function: + uint32_t PHY_GetSWVersion(void) + + Summary: + To Get the current Software version of PHY + + Description: + This function is used Get the current Software version of PHY + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + None + + Returns: + 32-bit PHY SW version value + + Example: + + uint32_t phySwVersion; + + Get sw version of the PHY + phySwVersion = PHY_GetSWVersion(); + + + + Remarks: + None +*/ +uint32_t PHY_GetSWVersion(void); + +// ***************************************************************************** +/* + Function: + PHY_Retval_t PHY_ConvertTxPwrRegValToDbm(uint8_t regValue, int8_t *dbmValue) + + Summary: + To convert the Tx Power Register index value to dbm Value + + Description: + This function is used to convert Tx Power Register index value to dbm Value + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + regVaue - Index of the Power register value (Range 0-15) + dbmValue - Corresponding dbm value to the Pwr register value + + Returns: + PHY_SUCCESS - If reg value can be converted into dBm value + PHY_FAILURE - If regVaue is holding the invalid value + + Example: + + uint8_t pwrRegIndex = 0x04; + int8_t pwrDbm; + + To get the dBm value corresponding to power register index + PHY_ConvertTxPwrRegValToDbm(pwrRegIndex, &pwrDbm); + + + + Remarks: + None +*/ +PHY_Retval_t PHY_ConvertTxPwrRegValToDbm(uint8_t regValue, int8_t *dbmValue); + +/** + * @brief Conversion of symbols to microseconds + */ +uint32_t tal_convert_symbols_to_us_def(uint32_t symbols); + +/** + * @brief Conversion of microseconds to symbols + */ +uint32_t tal_convert_us_to_symbols_def(uint32_t time_); + + + +#define MAX_PDT_LEVEL (0x0FU) + +#define REGISTER_VALUE (0x01U) +#define DBM_VALUE (0x00) + +#define AACK_PROM_ENABLE (0x01U) +#define AACK_PROM_DISABLE (0x00U) + + +#define BASE_ISM_FREQUENCY_MHZ (2306.0f) +#define MIN_ISM_FREQUENCY_MHZ (2322.0f) +#define MAX_ISM_FREQUENCY_MHZ (2527.0f) +#define MID_ISM_FREQUENCY_MHZ (2434.0f) + +#define CC_BAND_0 (0x00U) +#define CC_BAND_8 (0x08U) +#define CC_BAND_9 (0x09U) +#define CC_NUMBER_0 (0x00U) + +#define MIN_CC_BAND_8_OFFSET (0x20U) +#define MIN_CC_BAND_9_OFFSET (0xBAU) + + + +//DOM-IGNORE-BEGIN +#ifdef __cplusplus +} +#endif +//DOM-IGNORE-END + +#endif /* PHY_H */ +/* EOF */ diff --git a/driver/software/RF233/phy/inc/phy_config.h b/driver/software/RF233/phy/inc/phy_config.h new file mode 100644 index 0000000..7ff2995 --- /dev/null +++ b/driver/software/RF233/phy/inc/phy_config.h @@ -0,0 +1,38 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* Prevent double inclusion */ +#ifndef PHY_CONFIG_H +#define PHY_CONFIG_H + +// **************************************************************************** +// **************************************************************************** +// Section: Macros +// **************************************************************************** +// **************************************************************************** + + + +#endif diff --git a/driver/software/RF233/phy/inc/phy_constants.h b/driver/software/RF233/phy/inc/phy_constants.h new file mode 100644 index 0000000..64cf43d --- /dev/null +++ b/driver/software/RF233/phy/inc/phy_constants.h @@ -0,0 +1,251 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +#ifndef PHY_CONSTANTS_H +#define PHY_CONSTANTS_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Macros +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Minimum channel + + Summary: + This macro defines the Minimum channel number of Transciver + Description: + None + Remarks: + None + */ + +#define MIN_CHANNEL (11U) + +// ***************************************************************************** +/* Maximum channel + + Summary: + This macro defines the Maximum channel number of Transciver + Description: + None + Remarks: + None + */ +#define MAX_CHANNEL (26U) + +// ***************************************************************************** +/* Valid Channel Mask + + Summary: + This macro defines the Valid Channel Mask used for ED Scanning + Description: + None + Remarks: + None + */ +#define VALID_CHANNEL_MASK (0x07FFF800UL) + +// ***************************************************************************** +/* Symbols per Octet + + Summary: + This macro defines the number of symbols per octet + Description: + 4 bits form one symbol since O-QPSK is used. + Remarks: + None + */ + +#define SYMBOLS_PER_OCTET (2U) + +// ***************************************************************************** +/* No of Symbols included in the preamble + + Summary: + This macro defines the number of symbols includes in the preamble + Description: + None + Remarks: + None + */ + +#define NO_SYMBOLS_PREAMBLE (8U) + +// ***************************************************************************** +/* Number of symbols included in the SFD field + + Summary: + This macro defines the number of symbols includes in SFD Field + Description: + None + Remarks: + None + */ + +#define NO_SYMBOLS_SFD (2U) + +// ***************************************************************************** +/* Number of symbols forming the synchronization header (SHR) for the current + PHY. + + Summary: + This macro defines the number of symbols forming the synchronization header + (SHR) for the current PHY. This value is the base for the PHY PIB attribute + phySHRDuration. + Description: + None + Remarks: + None + */ + +#define NO_OF_SYMBOLS_PREAMBLE_SFD (NO_SYMBOLS_PREAMBLE + \ + NO_SYMBOLS_SFD) + +// ***************************************************************************** +/* Maximum number of symbols in a frame for the current PHY. + + Summary: + This macro defines the Maximum number of symbols in a frame for the current PHY + This value is the base for the PHY PIB attribute phyMaxFrameDuration. + Description: + None + Remarks: + None + */ + +#define MAX_FRAME_DURATION \ + (NO_OF_SYMBOLS_PREAMBLE_SFD + \ + (aMaxPHYPacketSize + 1U) * SYMBOLS_PER_OCTET) + +// ***************************************************************************** +/* Maximum Symbol Time + + Summary: + The maximum time in symbols for a 32 bit timer + Description: + None + Remarks: + None + */ + +#define MAX_SYMBOL_TIME (0x0FFFFFFF) + +// ***************************************************************************** +/* Symbol Mask + + Summary: + Symbol mask for ignoring most significant nibble + Description: + None + Remarks: + None + */ + +#define SYMBOL_MASK (0x0FFFFFFF) + +// ***************************************************************************** + + +// ***************************************************************************** +/* Default Tx Power Channel 26 + + Summary: + Default tx power for Ch26 to meet FCC compliance + Description: + None + Remarks: + None + */ + +#define DEFAULT_TX_POWER_CH26 (TX_PWR_TOLERANCE | 0x0d) + +// ***************************************************************************** +// ***************************************************************************** +// Section: Constants +// ***************************************************************************** +// ***************************************************************************** + + + + + + + + +// ***************************************************************************** +/* PWR_REGISTER_VALUE + + Summary: + Macro for selecting power configuration mode as Register set + Remarks: + None + */ +#define PWR_REGISTER_VALUE (1) + +// ***************************************************************************** +/* PWR_DBM_VALUE + + Summary: + Macro for selecting power configuration mode as Dbm set + Remarks: + None + */ +#define PWR_DBM_VALUE (0) + +// ***************************************************************************** +/* PROMISCUOUS_ENABLE + + Summary: + Macro for enabling promiscuous mode + Remarks: + None + */ +#define PROMISCUOUS_ENABLE (1) + +// ***************************************************************************** +/* PROMISCUOUS_DISABLE + + Summary: + Macro for disabling promiscuous mode + Remarks: + None + */ +#define PROMISCUOUS_DISABLE (0) + +// ***************************************************************************** +/* NUMBER_OF_TOTAL_PHY_TIMERS + + Summary: + Total numbers of software timer instance used by PHY Layer + Remarks: + None + */ +#define NUMBER_OF_TOTAL_PHY_TIMERS (1) + +#endif /* PHY_CONSTANTS_H */ + +/* EOF */ diff --git a/driver/software/RF233/phy/inc/phy_tasks.h b/driver/software/RF233/phy/inc/phy_tasks.h new file mode 100644 index 0000000..e096c88 --- /dev/null +++ b/driver/software/RF233/phy/inc/phy_tasks.h @@ -0,0 +1,196 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* Prevent double inclusion */ +#ifndef PHY_TASKS_H +#define PHY_TASKS_H + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Prototypes +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* + Function: + void PHY_Tasks(void) + + Summary: + RTOS task for the PHY Layer + + Description: + This function inturn calls the PHY layer task handler upon reception of + Semaphore signal + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + None + + Returns: + None + + Example: + + xTaskCreate((TaskFunction_t) _PHY_Tasks, + "PHY_Tasks", + 1024, + NULL, + 1, + &xPHY_Tasks); + + Handle for the PHY_Tasks. + TaskHandle_t xPHY_Tasks; + + void _PHY_Tasks( void *pvParameters ) + { + while(1) + { + PHY_Tasks(); + } + } + + + + Remarks: + None +*/ + +void PHY_Tasks(void); + +// ***************************************************************************** +/* + Function: + void TAL_Tasks(void) + + Summary: + RTOS task for the PHY Layer + + Description: + This function inturn calls the TAL layer task handler upon reception of + Semaphore signal + + Precondition: + PHY_Init() should have been called before calling this function + + Parameters: + None + + Returns: + None + + Example: + + xTaskCreate((TaskFunction_t) _TAL_Tasks, + "TAL_Tasks", + 1024, + NULL, + 1, + &xTAL_Tasks); + + Handle for the TAL_Tasks. + TaskHandle_t xTAL_Tasks; + + void _TAL_Tasks( void *pvParameters ) + { + while(1) + { + TAL_Tasks(); + } + } + + + + Remarks: + None +*/ + +void TAL_Tasks(void); + +// ***************************************************************************** +/* + Function: + void PHY_PostTask(bool isISRContext) + + Summary: + This function is used to invoke the PHY RTOS task + + Description: + This function is used to invoke the PHY RTOS task. This will be used + by the PHY layer for signaling the task done status + + Precondition: + This function gets called from the PHY Library. + + Parameters: + isISRContext true - Task is called from the ISR context false - otherwise + + Returns: + None + + Example: + None + + Remarks: + None +*/ + +void PHY_PostTask(bool isISRContext); + +// ***************************************************************************** +/* + Function: + void TAL_PostTask(bool isISRContext) + + Summary: + This function is used to invoke the TAL RTOS task + + Description: + This function is used to invoke the TAL RTOS task. This task is used to handle + the transceiver interrupts + + + Parameters: + isISRContext true - Task is called from the ISR context false - otherwise + + Returns: + None + + Example: + None + + Remarks: + None +*/ + +void TAL_PostTask(bool isISRContext); + + +#endif /* PHY_TASKS_H */ + +/* EOF */ diff --git a/driver/software/RF233/phy/src/phy_ed_end_cb.c b/driver/software/RF233/phy/src/phy_ed_end_cb.c new file mode 100644 index 0000000..1e796cb --- /dev/null +++ b/driver/software/RF233/phy/src/phy_ed_end_cb.c @@ -0,0 +1,66 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Included Files */ +/* ************************************************************************** */ +/* ************************************************************************** */ +#include +#include +#include "../../phy/inc/phy.h" + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Macros */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Globals */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Prototypes */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Functions */ +/* ************************************************************************** */ +/* ************************************************************************** */ +__attribute__((weak)) void PHY_EdEndCallback(uint8_t energyLevel) +{ + energyLevel = energyLevel; /* Keep compiler happy. */ +} + +/* EOF */ diff --git a/driver/software/RF233/phy/src/phy_rx_frame_cb.c b/driver/software/RF233/phy/src/phy_rx_frame_cb.c new file mode 100644 index 0000000..3e88d3b --- /dev/null +++ b/driver/software/RF233/phy/src/phy_rx_frame_cb.c @@ -0,0 +1,68 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Included Files */ +/* ************************************************************************** */ +/* ************************************************************************** */ +#include +#include +#include "../../phy/inc/phy.h" + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Macros */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Globals */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Prototypes */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Functions */ +/* ************************************************************************** */ +/* ************************************************************************** */ + +__attribute__((weak)) void PHY_RxFrameCallback(PHY_FrameInfo_t *rxFrame) +{ + /* Keep compiler happy. */ + rxFrame = rxFrame; +} + +/* EOF */ diff --git a/driver/software/RF233/phy/src/phy_task.c b/driver/software/RF233/phy/src/phy_task.c new file mode 100644 index 0000000..d57ec40 --- /dev/null +++ b/driver/software/RF233/phy/src/phy_task.c @@ -0,0 +1,124 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Included Files */ +/* ************************************************************************** */ +/* ************************************************************************** */ + +/* This section lists the other files that are included in this file. + */ +#include "../../phy/inc/phy.h" +#include "definitions.h" + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Externals */ +/* ************************************************************************** */ +/* ************************************************************************** */ + +extern OSAL_SEM_HANDLE_TYPE semPhyInternalHandler; +extern OSAL_SEM_HANDLE_TYPE semTalInternalHandler; + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Prototypes */ +/* ************************************************************************** */ +/* ************************************************************************** */ +void PHY_Tasks(void) +{ + OSAL_RESULT result = OSAL_RESULT_TRUE; + if (semPhyInternalHandler != NULL) + { + result = OSAL_SEM_Pend(&semPhyInternalHandler, OSAL_WAIT_FOREVER); + PHY_TaskHandler(); + } + (void)result; +} + +/* ************************************************************************** */ +void TAL_Tasks(void) +{ + OSAL_RESULT result = OSAL_RESULT_TRUE; + if (semTalInternalHandler != NULL) + { + result = OSAL_SEM_Pend(&semTalInternalHandler, OSAL_WAIT_FOREVER); + TAL_TaskHandler(); + } + (void)result; +} + +/* ************************************************************************** */ +void PHY_PostTask(bool isISRContext) +{ + OSAL_RESULT result = OSAL_RESULT_TRUE; + if(semPhyInternalHandler != NULL) + { + if(isISRContext) + { + result = OSAL_SEM_PostISR(&semPhyInternalHandler); + } + else + { + result = OSAL_SEM_Post(&semPhyInternalHandler); + } + } + else + { + PHY_TaskHandler(); + } + + (void)result; +} + +/* ************************************************************************** */ +void TAL_PostTask(bool isISRContext) +{ + OSAL_RESULT result = OSAL_RESULT_TRUE; + if(semTalInternalHandler != NULL) + { + if(isISRContext) + { + result = OSAL_SEM_PostISR(&semTalInternalHandler); + } + else + { + result = OSAL_SEM_Post(&semTalInternalHandler); + } + } + else + { + TAL_TaskHandler(); + } + + (void)result; +} +/* ***************************************************************************** + + + + End of File + */ diff --git a/driver/software/RF233/phy/src/phy_tx_frame_done_cb.c b/driver/software/RF233/phy/src/phy_tx_frame_done_cb.c new file mode 100644 index 0000000..7282abd --- /dev/null +++ b/driver/software/RF233/phy/src/phy_tx_frame_done_cb.c @@ -0,0 +1,68 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Included Files */ +/* ************************************************************************** */ +/* ************************************************************************** */ +#include +#include +#include "../../phy/inc/phy.h" + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Macros */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Globals */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Prototypes */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Functions */ +/* ************************************************************************** */ +/* ************************************************************************** */ +__attribute__((weak)) void PHY_TxDoneCallback(PHY_Retval_t status, PHY_FrameInfo_t *frame) +{ + /* Keep compiler happy. */ + status = status; + frame = frame; +} + +/* EOF */ diff --git a/driver/software/app_fw/framework_defs.h b/driver/software/app_fw/framework_defs.h new file mode 100644 index 0000000..90b6b5e --- /dev/null +++ b/driver/software/app_fw/framework_defs.h @@ -0,0 +1,90 @@ +/******************************************************************************* + Framework Defines Header File + + File Name: + framework_defs.h + + Summary: + + Description: + + Remarks: + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef FRAMEWORK_DEFS_H +#define FRAMEWORK_DEFS_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "osal/osal_freertos_extend.h" +#include "framework_defs.h" + +typedef struct +{ + OSAL_CRITSECT_DATA_TYPE(*OSAL_CRIT_Enter)(OSAL_CRIT_TYPE); + void (*OSAL_CRIT_Leave)(OSAL_CRIT_TYPE, OSAL_CRITSECT_DATA_TYPE); + + OSAL_RESULT(*OSAL_SEM_Create)(OSAL_SEM_HANDLE_TYPE *, OSAL_SEM_TYPE, uint8_t, uint8_t); + OSAL_RESULT(*OSAL_SEM_Pend)(OSAL_SEM_HANDLE_TYPE *, uint32_t); + OSAL_RESULT(*OSAL_SEM_Post)(OSAL_SEM_HANDLE_TYPE *); + OSAL_RESULT(*OSAL_SEM_PostISR)(OSAL_SEM_HANDLE_TYPE *); + uint8_t(*OSAL_SEM_GetCount)(OSAL_SEM_HANDLE_TYPE *); + + OSAL_RESULT(*OSAL_QUEUE_Create)(OSAL_QUEUE_HANDLE_TYPE *, uint32_t, uint32_t); + OSAL_RESULT(*OSAL_QUEUE_Send)(OSAL_QUEUE_HANDLE_TYPE *, void *, uint32_t); + OSAL_RESULT(*OSAL_QUEUE_SendISR)(OSAL_QUEUE_HANDLE_TYPE *, void *); + OSAL_RESULT(*OSAL_QUEUE_Receive)(OSAL_QUEUE_HANDLE_TYPE *, void *, uint32_t); + OSAL_RESULT(*OSAL_QUEUE_IsFullISR)(OSAL_QUEUE_HANDLE_TYPE *); + + OSAL_RESULT(*OSAL_QUEUE_CreateSet)(OSAL_QUEUE_SET_HANDLE_TYPE *, uint32_t); + OSAL_RESULT(*OSAL_QUEUE_AddToSet)(OSAL_QUEUE_SET_MEMBER_HANDLE_TYPE *, OSAL_QUEUE_SET_HANDLE_TYPE *); + OSAL_RESULT(*OSAL_QUEUE_SelectFromSet)(OSAL_QUEUE_SET_MEMBER_HANDLE_TYPE *, OSAL_QUEUE_SET_HANDLE_TYPE *, uint32_t); + + void* (*OSAL_MemAlloc)(size_t size); + void (*OSAL_MemFree)(void* ); + +} OSAL_API_LIST_TYPE; + +typedef void (*unpack_fn_t)(void *); + +typedef struct +{ + unpack_fn_t unpack_fn; +} Request; + +typedef struct +{ + uint32_t operation; +} Response; + +typedef void (*app_cb_t)(Response *); + +#endif // FRAMEWORK_DEFS_H diff --git a/driver/software/app_fw/osal/osal_freertos_extend.c b/driver/software/app_fw/osal/osal_freertos_extend.c new file mode 100644 index 0000000..366f658 --- /dev/null +++ b/driver/software/app_fw/osal/osal_freertos_extend.c @@ -0,0 +1,329 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. + */ + +#include "osal_freertos_extend.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: OSAL Routines +// ***************************************************************************** +// ***************************************************************************** +/* These routines implement the OSAL for the chosen RTOS. +*/ + +// Queue group +// ***************************************************************************** +/******************************************************************************* + Function: + OSAL_RESULT OSAL_QUEUE_Create(OSAL_QUEUE_HANDLE_TYPE *queID, uint32_t queueLength, uint32_t itemSize) + + Summary: + Create an OSAL Queue + + Description: + Creates a new queue instance, and returns a handle by which the new queue + can be referenced. + + Parameters: + queID - A pointer to the queue ID + + queueLength - The maximum number of items that the queue can contain. + + itemSize - The number of bytes each item in the queue will require. + Items are queued by copy, not by reference, so this is the number of bytes + that will be copied for each posted item. + Each item in the queue must be the same size. + + Returns: + OSAL_RESULT_TRUE - A queue had been created + OSAL_RESULT_FALSE - Queue creation failed + + Example: + + OSAL_QUEUE_HANDLE_TYPE queID; + OSAL_RESULT result = OSAL_QUEUE_Create(&queID, 16, 8); + + + Remarks: +*/ +OSAL_RESULT OSAL_QUEUE_Create(OSAL_QUEUE_HANDLE_TYPE *queID, uint32_t queueLength, uint32_t itemSize) +{ + *queID = xQueueCreate(queueLength, itemSize); + + if (NULL == *queID) + { + return OSAL_RESULT_FALSE; + } + + return OSAL_RESULT_TRUE; +} + +OSAL_RESULT OSAL_QUEUE_CreateSet(OSAL_QUEUE_SET_HANDLE_TYPE *queSetID, uint32_t queueLength) +{ + *queSetID = xQueueCreateSet(queueLength); + + if (NULL == *queSetID) + { + return OSAL_RESULT_FALSE; + } + + return OSAL_RESULT_TRUE; +} + +OSAL_RESULT OSAL_QUEUE_AddToSet(OSAL_QUEUE_SET_MEMBER_HANDLE_TYPE *queSetMember, OSAL_QUEUE_SET_HANDLE_TYPE *queSetID) +{ + + if (pdTRUE == xQueueAddToSet(*queSetMember, *queSetID)) + { + return OSAL_RESULT_TRUE; + } + + return OSAL_RESULT_FALSE; +} + +OSAL_RESULT OSAL_QUEUE_SelectFromSet(OSAL_QUEUE_SET_MEMBER_HANDLE_TYPE *queSetMember, OSAL_QUEUE_SET_HANDLE_TYPE *queSetID, uint16_t waitMS) +{ + *queSetMember = xQueueSelectFromSet(*queSetID, waitMS); + + if (NULL == *queSetMember) + { + return OSAL_RESULT_FALSE; + } + + return OSAL_RESULT_TRUE; +} + +/******************************************************************************* + Function: + OSAL_RESULT OSAL_QUEUE_Send(OSAL_QUEUE_HANDLE_TYPE *queID, void *itemToQueue, uint16_t waitMS) + + Summary: + Post an item into an OSAL Queue. + + Description: + Post an item into an OSAL Queue. The item is queued by copy, not by reference. + This function must not be called from an interrupt service routine. + See OSAL_QUEUE_SendISR() for an alternative which may be used in an ISR. + + Parameters: + queID - A pointer to the queue ID + + itemToQueue - A pointer to the item that is to be placed on the queue. + The size of the items the queue will hold was defined when the queue was created, + so this many bytes will be copied from itemToQueue into the queue storage area. + + waitMS - Time limit to wait in milliseconds. + 0 - do not wait + OSAL_WAIT_FOREVER - return only when semaphore is obtained + Other values - timeout delay + + Returns: + OSAL_RESULT_TRUE - Item copied to the queue + OSAL_RESULT_FALSE - Item not copied to the queue or timeout occurred + + Example: + + OSAL_RESULT result = OSAL_QUEUE_Create(&queID, &itemToQueue, OSAL_WAIT_FOREVER); + + + Remarks: +*/ +OSAL_RESULT OSAL_QUEUE_Send(OSAL_QUEUE_HANDLE_TYPE *queID, void *itemToQueue, uint16_t waitMS) +{ + TickType_t timeout = 0; + + if (OSAL_WAIT_FOREVER == waitMS) + { + timeout = portMAX_DELAY; + } + else + { + timeout = (TickType_t)(waitMS / portTICK_PERIOD_MS); + } + if (pdTRUE == xQueueSend(*queID, itemToQueue, timeout)) + { + return OSAL_RESULT_TRUE; + } + else + { + return OSAL_RESULT_FALSE; + } +} + +/******************************************************************************* + Function: + OSAL_RESULT OSAL_QUEUE_SendISR(OSAL_QUEUE_HANDLE_TYPE *queID, void *itemToQueue) + + Summary: + Post an item into an OSAL Queue from within an ISR + + Description: + Post an item into an OSAL Queue. The item is queued by copy, not by reference. + The highest priority task currently blocked on the queue will be released and + made ready to run. + This form of the send function should be used witin an ISR. + + Parameters: + queID - A pointer to the queue ID + + itemToQueue - A pointer to the item that is to be placed on the queue. + The size of the items the queue will hold was defined when the queue was created, + so this many bytes will be copied from itemToQueue into the queue storage area. + + Returns: + OSAL_RESULT_TRUE - Item copied to the queue + OSAL_RESULT_FALSE - Item not copied to the queue + + Example: + + OSAL_RESULT result = OSAL_QUEUE_Create(&queID, &itemToQueue, OSAL_WAIT_FOREVER); + + + Remarks: +*/ +OSAL_RESULT OSAL_QUEUE_SendISR(OSAL_QUEUE_HANDLE_TYPE *queID, void *itemToQueue) +{ + BaseType_t _taskWoken = pdFALSE; + + if (pdTRUE == xQueueSendFromISR(*queID, itemToQueue, &_taskWoken)) + { + portYIELD_FROM_ISR(_taskWoken); + return OSAL_RESULT_TRUE; + } + else + { + return OSAL_RESULT_FALSE; + } +} + +/******************************************************************************* + Function: + OSAL_RESULT OSAL_QUEUE_Receive(OSAL_QUEUE_HANDLE_TYPE *queID, void *buffer, uint16_t waitMS) + + Summary: + Receive an item from an OSAL Queue. + + Description: + Receive an item from an OSAL Queue. The item is received by copy so a buffer of + adequate size must be provided. The number of bytes copied into the buffer + was defined when the queue was created. + Successfully received items are removed from the queue. + This function must not be used in an interrupt service routine. + + Parameters: + queID - A pointer to the queue ID + + buffer - A pointer to the buffer into which the received item will be copied. + The size of the items the queue hold was defined when the queue was created, + so this many bytes will be copied from the queue storage area into the buffer. + + waitMS - Time limit to wait in milliseconds. + 0 - do not wait + OSAL_WAIT_FOREVER - return only when semaphore is obtained + Other values - timeout delay + + Returns: + OSAL_RESULT_TRUE - An item was successfully received from the queue. + OSAL_RESULT_FALSE - An item was not successfully received from the queue + or timeout occurred + + Example: + + OSAL_RESULT result = OSAL_QUEUE_Receive(&queID, &buffer, OSAL_WAIT_FOREVER); + + + Remarks: +*/ +OSAL_RESULT OSAL_QUEUE_Receive(OSAL_QUEUE_HANDLE_TYPE *queID, void *buffer, uint16_t waitMS) +{ + TickType_t timeout = 0; + + if (OSAL_WAIT_FOREVER == waitMS) + { + timeout = portMAX_DELAY; + } + else + { + timeout = (TickType_t)(waitMS / portTICK_PERIOD_MS); + } + if (pdTRUE == xQueueReceive(*queID, buffer, timeout)) + { + return OSAL_RESULT_TRUE; + } + else + { + return OSAL_RESULT_FALSE; + } +} + +/******************************************************************************* + Function: + OSAL_RESULT OSAL_QUEUE_IsFullISR(OSAL_QUEUE_HANDLE_TYPE *queID) + + Summary: + Query if an OSAL Queue is full. + + Description: + Query if an OSAL Queue is full. + These function should be used only from witin an ISR, or within a critical section. + + Parameters: + queID - A pointer to the queue ID + + Returns: + OSAL_RESULT_TRUE - The queue is Full. + OSAL_RESULT_FALSE - The queue is not Full. + + Example: + + OSAL_RESULT result = OSAL_QUEUE_IsFullISR(&queID); + + + Remarks: +*/ +OSAL_RESULT OSAL_QUEUE_IsFullISR(OSAL_QUEUE_HANDLE_TYPE *queID) +{ + if (pdTRUE == xQueueIsQueueFullFromISR(*queID)) + { + return OSAL_RESULT_TRUE; + } + else + { + return OSAL_RESULT_FALSE; + } +} + +/******************************************************************************* + End of File +*/ + diff --git a/driver/software/app_fw/osal/osal_freertos_extend.h b/driver/software/app_fw/osal/osal_freertos_extend.h new file mode 100644 index 0000000..be9f88c --- /dev/null +++ b/driver/software/app_fw/osal/osal_freertos_extend.h @@ -0,0 +1,237 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +// DOM-IGNORE-BEGIN +#ifndef _OSAL_FREERTOS_EXTEND_H +#define _OSAL_FREERTOS_EXTEND_H + +#ifdef __cplusplus +extern "C" { +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "osal_freertos.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* declare default data type handles. Any RTOS port must define it's own copy of these */ +/* + * Type by which queues are referenced. For example, a call to xQueueCreate() + * returns an QueueHandle_t variable that can then be used as a parameter to + * xQueueSend(), xQueueReceive(), etc. + */ +typedef QueueHandle_t OSAL_QUEUE_HANDLE_TYPE; + +/* + * Type by which queue sets are referenced. For example, a call to + * xQueueCreateSet() returns an xQueueSet variable that can then be used as a + * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc. + */ +typedef QueueSetHandle_t OSAL_QUEUE_SET_HANDLE_TYPE; + +/* + * Queue sets can contain both queues and semaphores, so the + * QueueSetMemberHandle_t is defined as a type to be used where a parameter or + * return value can be either an QueueHandle_t or an SemaphoreHandle_t. + */ +typedef QueueSetMemberHandle_t OSAL_QUEUE_SET_MEMBER_HANDLE_TYPE; + +// ***************************************************************************** +/* OSAL Result type + + Summary: + Enumerated type representing the general return value from OSAL functions. + + Description: + This enum represents possible return types from OSAL functions. + + Remarks: + These enum values are the possible return values from OSAL functions + where a standard success/fail type response is required. The majority + of OSAL functions will return this type with a few exceptions. +*/ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Section: Interface Routines Group +// ***************************************************************************** + +// ***************************************************************************** +/** +*@brief Creates a new queue instance, and returns a handle by which the new queue +* can be referenced +* +*@param queID - A pointer to the queue ID +* queueLength - The maximum number of items that the queue can contain. +* itemSize - The number of bytes each item in the queue will require. +* Items are queued by copy, not by reference, so this is the number of bytes +* that will be copied for each posted item. +* Each item in the queue must be the same size. +* +*@retval OSAL_RESULT_TRUE - A queue had been created +* OSAL_RESULT_FALSE - Queue creation failed +*/ +OSAL_RESULT OSAL_QUEUE_Create(OSAL_QUEUE_HANDLE_TYPE *queID, uint32_t queueLength, uint32_t itemSize); + +// ***************************************************************************** +/** +*@brief Creates a new queue set instance, and returns a handle by which the new queue + can be referenced +* +*@param queID - A pointer to the queue ID +* queueLength - The maximum number of items that the queue can contain. +* +*@retval OSAL_RESULT_TRUE - A queue set had been created +* OSAL_RESULT_FALSE - Queue creation failed +*/ +OSAL_RESULT OSAL_QUEUE_CreateSet(OSAL_QUEUE_SET_HANDLE_TYPE *queID, uint32_t queueLength); + +// ***************************************************************************** +/** +*@brief Add the queues and semaphores to the set.Reading from these queues and semaphore can +* only be performed after a call to xQueueSelectFromSet() has +* returned the queue or semaphore handle from this point on. +* +*@param queSetMember - Member queue or semaphore to be added in the set +* queSetID - A pointer to the queue ID +* +*@retval OSAL_RESULT_TRUE - A queue had been created +* OSAL_RESULT_FALSE - Queue creation failed +*/ +OSAL_RESULT OSAL_QUEUE_AddToSet(OSAL_QUEUE_SET_MEMBER_HANDLE_TYPE *queSetMember, OSAL_QUEUE_SET_HANDLE_TYPE *queSetID); + +// ***************************************************************************** +/** +*@brief Block to wait for something to be available from the queues or semaphore that have been added to the set. +* +*@param queSetMember - Member queue or semaphore to be added in the set +* queSetID - A pointer to the queue ID +* waitMS - wait time in milliseconds. other value OSAL_WAIT_FOREVER - wait indefinitely +* +*@retval OSAL_RESULT_TRUE - A queue had been created +* OSAL_RESULT_FALSE - Queue creation failed +*/ +OSAL_RESULT OSAL_QUEUE_SelectFromSet(OSAL_QUEUE_SET_MEMBER_HANDLE_TYPE *queSetMember, OSAL_QUEUE_SET_HANDLE_TYPE *queSetID, uint16_t waitMS); + +// ***************************************************************************** +/** +*@brief Post an item into an OSAL Queue. The item is queued by copy, not by reference. +* This function must not be called from an interrupt service routine. +* See OSAL_QUEUE_SendISR() for an alternative which may be used in an ISR. +* +*@param queID - A pointer to the queue ID +* +* itemToQueue - A pointer to the item that is to be placed on the queue. +* The size of the items the queue will hold was defined when the queue was created, +* so this many bytes will be copied from itemToQueue into the queue storage area. +* +* waitMS - Time limit to wait in milliseconds. +* 0 - do not wait +* OSAL_WAIT_FOREVER - return only when semaphore is obtained +* Other values - timeout delay +* +*@retval OSAL_RESULT_TRUE - Item copied to the queue +* OSAL_RESULT_FALSE - Item not copied to the queue or timeout occurred +*/ +OSAL_RESULT OSAL_QUEUE_Send(OSAL_QUEUE_HANDLE_TYPE *queID, void *itemToQueue, uint16_t waitMS); + +// ***************************************************************************** +/** +*@brief Post an item into an OSAL Queue. The item is queued by copy, not by reference. +* The highest priority task currently blocked on the queue will be released and +* made ready to run. This form of the send function should be used witin an ISR. +* +*@param queID - A pointer to the queue ID +* +* itemToQueue - A pointer to the item that is to be placed on the queue. +* The size of the items the queue will hold was defined when the queue was created, +* so this many bytes will be copied from itemToQueue into the queue storage area. +* +* waitMS - Time limit to wait in milliseconds. +* 0 - do not wait +* OSAL_WAIT_FOREVER - return only when semaphore is obtained +* Other values - timeout delay +* +*@retval OSAL_RESULT_TRUE - Item copied to the queue +* OSAL_RESULT_FALSE - Item not copied to the queue or timeout occurred +*/ +OSAL_RESULT OSAL_QUEUE_SendISR(OSAL_QUEUE_HANDLE_TYPE *queID, void *itemToQueue); + +// ***************************************************************************** +/** +*@brief Receive an item from an OSAL Queue. The item is received by copy so a buffer of +* adequate size must be provided. The number of bytes copied into the buffer +* was defined when the queue was created. +* Successfully received items are removed from the queue. +* This function must not be used in an interrupt service routine. +* +*@param queID - A pointer to the queue ID +* +* buffer - A pointer to the buffer into which the received item will be copied. +* The size of the items the queue hold was defined when the queue was created, +* so this many bytes will be copied from the queue storage area into the buffer. +* +* waitMS - Time limit to wait in milliseconds. +* 0 - do not wait +* OSAL_WAIT_FOREVER - return only when semaphore is obtained +* Other values - timeout delay +* +*@retval OSAL_RESULT_TRUE - An item was successfully received from the queue +* OSAL_RESULT_FALSE - An item was not successfully received from the queue +* or timeout occurred +*/ +OSAL_RESULT OSAL_QUEUE_Receive(OSAL_QUEUE_HANDLE_TYPE *queID, void *pBuffer, uint16_t waitMS); + +// ***************************************************************************** +/** +*@brief Query if an OSAL Queue is full. +* These function should be used only from witin an ISR, or within a critical section. +* +*@param queID - A pointer to the queue ID +* +*@retval OSAL_RESULT_TRUE - The queue is Full +* OSAL_RESULT_FALSE - The queue is not Full +*/ +OSAL_RESULT OSAL_QUEUE_IsFullISR(OSAL_QUEUE_HANDLE_TYPE *queID); + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus +} +#endif +// DOM-IGNORE-END + +#endif // _OSAL_FREERTOS_EXTEND_H + +/******************************************************************************* + End of File +*/ diff --git a/driver/software/pal/src/pal.c b/driver/software/pal/src/pal.c new file mode 100644 index 0000000..9a4e9f9 --- /dev/null +++ b/driver/software/pal/src/pal.c @@ -0,0 +1,451 @@ +/******************************************************************************* + PAL Source + + File Name: + pal.c + + Summary: + Performs interface functionalities between the PHY layer and Harmony + drivers + + Description: + * None +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Included Files */ +/* ************************************************************************** */ +/* ************************************************************************** */ +#include +#include +#include "../../pal/inc/pal.h" +#include "system/time/sys_time.h" + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Types */ +/* ************************************************************************** */ +/* ************************************************************************** */ + + + +/* Structure holding the PAL Timer details*/ +typedef struct pal_timers_tag +{ + /* Sys Timer Handle*/ + SYS_TIME_HANDLE timerId; + /* Callback handler invoked upon timer expiry*/ + appCallback_t appCallback; + /* Argument for the callback handler*/ + void *param_cb; + /* Status of timer start*/ + bool isTimerStarted; +}PAL_Timers_t; + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Macros */ +/* ************************************************************************** */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Prototypes */ +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Helper function to find the timer is started or not*/ +static bool palTimerIsStarted(TimerId_t timerId); + +/* Variable holding number of PAL Timers*/ +static uint8_t numOfTimers = 0; + +/* PAL Timer Callback Handler through which app/stack timer + * callbacks will be called*/ +static void palTimerCallback(uintptr_t paramCb); + +/* Max number of software timers*/ +static uint8_t numMaxTimers = (uint8_t)SYS_TIME_MAX_TIMERS; + +/* PAL timer array holding timer details*/ +static PAL_Timers_t palTimers[SYS_TIME_MAX_TIMERS]; + +/* + * Function to initialize the PAL Timer array + */ +static PAL_Status_t PAL_TimerInit(void); + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Function Implementation */ +/* ************************************************************************** */ +/* ************************************************************************** */ +/** + * @brief Initialization of PAL + * + * This function initializes the PAL. . + * + * @return PAL_SUCCESS if PAL initialization is successful, PAL_FAILURE otherwise + */ +PAL_Status_t PAL_Init(void) +{ + PAL_Status_t status = PAL_SUCCESS; + + status = PAL_TimerInit(); + + return status; +} + +/** + * @brief Initialization of PAL Timer array + * + * This function initializes the PAL Timer array. . + * + * @return PAL_SUCCESS if PAL initialization is successful, PAL_FAILURE otherwise + */ +static PAL_Status_t PAL_TimerInit(void) +{ + PAL_Status_t status = PAL_SUCCESS; + SYS_TIME_RESULT sysStatus = SYS_TIME_ERROR; + numOfTimers = 0; + /* Variable holding the status of Timer initialization*/ + static bool palTimerInitialized = false; + + for (uint8_t i = 0; i < numMaxTimers; i++) + { + palTimers[i].isTimerStarted = false; + if(palTimerInitialized) + { + if(palTimers[i].timerId != SYS_TIME_HANDLE_INVALID) + { + sysStatus = SYS_TIME_TimerDestroy(palTimers[i].timerId); + } + } + } + + palTimerInitialized = true; + (void)sysStatus; + return status; +} + +/** + * @brief Start regular timer + * + * This function starts a regular timer and installs the corresponding + * callback function handle the timeout event. + * + * @param timer_id Timer identifier + * @param timer_count Timeout in microseconds + * @param timeout_type @ref TIMEOUT_RELATIVE or @ref TIMEOUT_ABSOLUTE + * @param timer_cb Callback handler invoked upon timer expiry + * @param param_cb Argument for the callback handler + * @param callback_type @ref CALLBACK_SINGLE or @ref CALLBACK_PERIODIC + * + * @return + * - @ref PAL_TMR_INVALID_ID if the timer identifier is undefined, + * - @ref PAL_INVALID_PARAMETER if the callback function for this timer + * is NULL, + * - @ref PAL_TMR_ALREADY_RUNNING if the timer is already running. + * - @ref PAL_SUCCESS if timer is started or + * - @ref PAL_TMR_INVALID_TIMEOUT if timeout is not within timeout + * range. + */ +PAL_Status_t PAL_TimerStart(TimerId_t timerId, + uint32_t timerCount, + TimeoutType_t timeoutType, + appCallback_t timerCb, + void *paramCb, CallbackType_t callbackType) +{ + + SYS_TIME_RESULT status = SYS_TIME_ERROR; + SYS_TIME_HANDLE timerHandle = SYS_TIME_HANDLE_INVALID; + SYS_TIME_CALLBACK_TYPE type = (SYS_TIME_CALLBACK_TYPE)callbackType; + + PAL_Status_t retStatus = PAL_FAILURE; + + + if (timeoutType == TIMEOUT_RELATIVE) + { + timerHandle = SYS_TIME_TimerCreate(0, SYS_TIME_USToCount(timerCount), + &palTimerCallback, (uintptr_t)&palTimers[timerId].timerId, type ); + } + else + { + timerHandle = SYS_TIME_TimerCreate(SYS_TIME_USToCount(timerCount), 0, + &palTimerCallback, (uintptr_t)&palTimers[timerId].timerId, type ); + } + + + if(timerHandle != SYS_TIME_HANDLE_INVALID) + { + palTimers[timerId].timerId = timerHandle; + status = SYS_TIME_TimerStart(timerHandle); + palTimers[timerId].appCallback = timerCb; + palTimers[timerId].param_cb = paramCb; + + } + else + { + retStatus = PAL_FAILURE; + } + + if (SYS_TIME_SUCCESS == status) { + palTimers[timerId].isTimerStarted = true; + retStatus = PAL_SUCCESS; + } + else{ + palTimers[timerId].isTimerStarted = false; + retStatus = PAL_FAILURE; + } + + return retStatus; + +} + +/** + * @brief Stops a running timer + * + * This function stops a running timer with specified timer_id + * + * @param timer_id Timer identifier + * + * @return + * - @ref PAL_SUCCESS if timer stopped successfully, + * - @ref PAL_TMR_INVALID_ID if the specifed timer id is undefined. + */ +PAL_Status_t PAL_TimerStop(TimerId_t timerId) +{ + PAL_Status_t status = PAL_SUCCESS; + SYS_TIME_RESULT sysStatus = SYS_TIME_ERROR; + + if(timerId <= numOfTimers) + { + sysStatus = SYS_TIME_TimerDestroy(palTimers[timerId].timerId); + palTimers[timerId].isTimerStarted = false; + } + else + { + status = PAL_TMR_INVALID_ID; + } + + (void)sysStatus; + return status; +} + +/** + * @brief Returns a timer id to be used before starting a timer + * @param timer_id Value of the id returned by the function + */ +PAL_Status_t PAL_TimerGetId(TimerId_t *timerId) +{ + PAL_Status_t status = PAL_FAILURE; + + if (numOfTimers < numMaxTimers) { + *timerId = numOfTimers; + numOfTimers++; + status = PAL_SUCCESS; + + } + return status; +} + +/** + * @brief Checks if the timer of requested timer identifier is running + * + * This function checks if the timer of requested timer identifier is running. + * + * @param timer_id Timer identifier + * + * @return + * - true if timer with requested timer id is running, + * - false otherwise. + */ +bool PAL_TimerIsRunning(TimerId_t timerId) +{ + bool isRunning = false; + + if(palTimerIsStarted(timerId)) + { + isRunning = !SYS_TIME_TimerPeriodHasExpired(palTimers[timerId].timerId); + } + + return isRunning; +} + +/** + * @brief Generates blocking delay + * + * This functions generates a blocking delay of specified time. + * + * @param delay in microseconds + */ +void PAL_TimerDelay(uint32_t delay) +{ + SYS_TIME_HANDLE delay_timer = SYS_TIME_HANDLE_INVALID; + SYS_TIME_RESULT sysStatus = SYS_TIME_ERROR; + + sysStatus = SYS_TIME_DelayUS(delay, &delay_timer); + if(delay_timer != SYS_TIME_HANDLE_INVALID && (sysStatus != SYS_TIME_ERROR)) + { + while (SYS_TIME_DelayIsComplete(delay_timer) == false) + { + ; + } + } + + return; +} + +/** + * @brief Gets current time + * + * This function returns the current time. + * + * @param[out] current_time Returns current system time + */ +uint32_t PAL_GetCurrentTime(void) +{ + uint32_t countVal; + + /* This will avoid the hard faults, due to aligned nature of access */ + countVal = SYS_TIME_CounterGet(); + + return SYS_TIME_CountToUS(countVal); +} + +/* + * @brief Helper function to find the timer is started or not + * @param timer_id Identifier of the timer which is being started/not + */ +static bool palTimerIsStarted(TimerId_t timerId) +{ + bool isTimerStarted = false; + + isTimerStarted = palTimers[timerId].isTimerStarted; + + return isTimerStarted; +} + +/* + * @brief PAL Timer Callback Handler through which app/stack timer + * callbacks will be called + * @param param_cb - Callback parameter holding the timer_id of expired timer + */ +static void palTimerCallback(uintptr_t paramCb) +{ + SYS_TIME_HANDLE *timerId = (SYS_TIME_HANDLE *)paramCb; + appCallback_t appCallback; + + if(timerId != NULL) + { + for (uint8_t i =0; i < numOfTimers; i++) + { + if((palTimers[i].timerId == (*timerId)) && (palTimers[i].isTimerStarted)) + { + palTimers[i].isTimerStarted = false; + appCallback = palTimers[i].appCallback; + if(appCallback != NULL) + { + appCallback(palTimers[i].param_cb); + } + } + } + } +} + +/** + * @brief Gets Random number + * @param[rnOutput] random number @param[rnLength] size of Random number + */ + +PAL_Status_t PAL_GetRandomNumber(uint8_t *rnOutput, uint16_t rnLength) +{ + uint32_t random_num; + uint32_t remBytes; + uint8_t *end = rnOutput; + end += rnLength; + for (uint16_t i = 0; i < (rnLength / sizeof(uint32_t)); i++) + { + random_num = TRNG_ReadData(); + (void)memcpy((uint8_t *)rnOutput, (uint8_t *)&random_num, sizeof(uint32_t)); + rnOutput += sizeof(uint32_t); + } + + if ((remBytes = (rnLength % sizeof(uint32_t))) != 0U){ + random_num = TRNG_ReadData(); + (void)memcpy((uint8_t *)rnOutput, (uint8_t *)&random_num, remBytes); + } + + return PAL_SUCCESS; +} + +/** +* @brief Gets the Antenna gain from the information block of device support library +* @param[antGain] - Pointer holding the module's antenna gain value +*/ +//PAL_Status_t PAL_GetTrxAntennaGain(int8_t *antGain) +//{ +// bool valid = false; +// int8_t antennaGain = INT8_MAX; +// +//#ifndef CUSTOM_ANT_GAIN +// valid = IB_GetAntennaGain(&antennaGain); +// +// if(valid) +// { +// //If infoBlock having valid antennaGain value +// *antGain = antennaGain; +// } +// else +// { +// //If InfoBlock is not having valid antennaGain value, +// //return default gain of WBZ45x +// *antGain = DEFAULT_ANT_GAIN; +// } +//#else +// *antGain = CUSTOM_ANT_GAIN; +// +//#endif +// +// return PAL_SUCCESS; +//} +// +/** +* @brief Gets the Transceiver's maximum transmit power +* @param[out] Integer value returning maximum tx power value that can be +* set by higher layer in dBm +*/ +//int8_t PAL_GetTrxTransmitPowerMax(void) +//{ +// int8_t txPwrMax = INT8_MAX; +// +// txPwrMax = PHY_TX_PWR_MAX; +// +// return txPwrMax; +//} diff --git a/driver/software/resources/buffer/inc/bmm.h b/driver/software/resources/buffer/inc/bmm.h new file mode 100644 index 0000000..36b5838 --- /dev/null +++ b/driver/software/resources/buffer/inc/bmm.h @@ -0,0 +1,248 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* Prevent double inclusion */ +#ifndef BMM_INTERFACE_H +#define BMM_INTERFACE_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: File includes +// ***************************************************************************** +// ***************************************************************************** + +#include +#include + +/* + * Buffer Management (large and small buffers): provides services for + * dynamically allocating and freeing memory buffers. + */ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Macros +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* BMM Buffer Pointer + + Summary: + This macro provides the pointer to the corresponding body of the supplied + buffer header + + Description: + None + + Remarks: + None +*/ + +#define BMM_BUFFER_POINTER(buf) ((buf)->body) + +// ***************************************************************************** +// ***************************************************************************** +// Section: Types +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Structure Holding the Buffer Details + + Summary: + Buffer structure holding information of each buffer + + Description: + buffer_t is used as the data type to get the buffer pointer + + Remarks: + None +*/ + +typedef struct buffer_tag +{ + /** Pointer to the buffer body */ + uint8_t *body; + + /** Pointer to next free buffer */ + struct buffer_tag *next; +} buffer_t; + +// ***************************************************************************** +// ***************************************************************************** +// Section: Externals +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +// ***************************************************************************** +// Section: Prototypes +// ***************************************************************************** +// ***************************************************************************** + +#ifdef __cplusplus +extern "C" { +#endif + +// ***************************************************************************** +/* + Function: + void bmm_buffer_init(void) + + Summary: + Initializes the buffer module + + Description: + This function initializes the buffer module. + This function should be called before using any other functionality + of buffer module + + Precondition: + None + + Parameters: + None. + + Returns: + None. + + Example: + + bmm_buffer_init(); + + + Remarks: + This routine is called by the PHY Layer during PHY Initialization (PHY_Init). + Application can directly allocate the buffer and use it. Number of Buffers should + be defined as per application needs before ausing the buffer +*/ + +void bmm_buffer_init(void); + +// ***************************************************************************** +/* + Function: + buffer_t* bmm_buffer_alloc(uint16_t size) + + Summary: + Allocates a buffer + + Description: + This function allocates a buffer and returns a pointer to the buffer. + The same pointer should be used while freeing the buffer.User should + call BMM_BUFFER_POINTER(buf) to get the pointer to buffer user area + + Precondition: + bmm_buffer_init should have been called before using this function + + Parameters: + param - size size of buffer to be allocated. + + Returns: + return- pointer to the buffer allocated, + NULL if buffer not available + + Example: + + buffer_t *buffer; + buffer = bmm_buffer_alloc(LARGE_BUFFER_SIZE); + + if (buffer == NULL) + { + Buffer is unavailable + } + + + + Remarks: + This routine is used by the PHY Layer for allocating the buffer for reception. + Number of Buffers should be defined as per application needs before the buffer + allocation function. If application allocates the buffer and not freeing them, + Trx may not able to continuously receive the packet. So care should be taken when + defining the Number of Buffers. +*/ + +#if defined(ENABLE_LARGE_BUFFER) +buffer_t* bmm_buffer_alloc(uint16_t size); + +#else +buffer_t* bmm_buffer_alloc(uint8_t size); + +#endif + +// ***************************************************************************** +/* + Function: + void bmm_buffer_free(buffer_t *pbuffer) + + Summary: + Frees up a buffer + + Description: + This function frees up a buffer. The pointer passed to this function + should be the pointer returned during buffer allocation. The result is + unpredictable if an incorrect pointer is passed. + + Precondition: + bmm_buffer_init should have been called before using this function + + Parameters: + pbuffer - Pointer to buffer that has to be freed + + Returns: + None + + Example: + + buffer_t *buffer; + buffer = bmm_buffer_alloc(LARGE_BUFFER_SIZE); + + if (buffer != NULL) + { + Use the buffer + } + + Buffer Freeing + bmm_buffer_free(buffer); + + + Remarks: + This routine is used by the PHY Layer for allocating the buffer for reception. + Number of Buffers should be defined as per application needs before the buffer + allocation function. If application allocates the buffer and not freeing them, + Trx may not able to continuously receive the packet. So care should be taken when + defining the Number of Buffers. +*/ + +void bmm_buffer_free(buffer_t *pbuffer); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* BMM_INTERFACE_H */ + +/* EOF */ diff --git a/driver/software/resources/buffer/src/bmm.c b/driver/software/resources/buffer/src/bmm.c new file mode 100644 index 0000000..a2cc049 --- /dev/null +++ b/driver/software/resources/buffer/src/bmm.c @@ -0,0 +1,284 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* === Includes ============================================================ */ + +#include +#include +#include +#include "../../../pal/inc/pal.h" +#include "../../../resources/buffer/inc/bmm.h" +#include "../../../resources/queue/inc/qmm.h" +#include "../../../phy/at86rf/inc/phy_internal.h" +#include "app_config.h" +#include "../../../phy/inc/phy.h" + + + +#if (TOTAL_NUMBER_OF_BUFS > 0) + +/* + * Check if the buffer configuration does not exceed the queue limits. + * Note: The queue's size parameter is a 8bit value. + */ +#if (TOTAL_NUMBER_OF_BUFS > 255) +#error "Number of buffer exceeds its limit" +#endif + +/* === Types =============================================================== */ + +/* === Macros ============================================================== */ + +#if (TOTAL_NUMBER_OF_SMALL_BUFS > 0) + +/** + * Checks whether the buffer pointer provided is of small buffer or of a large + * buffer + */ +#define IS_SMALL_BUF(p) ((p)->body >= (buf_pool + \ + LARGE_BUFFER_SIZE * TOTAL_NUMBER_OF_LARGE_BUFS)) +#endif + +/* === Globals ============================================================= */ + +/** + * Common Buffer pool holding the buffer user area + */ +#if (TOTAL_NUMBER_OF_SMALL_BUFS > 0) +static uint8_t buf_pool[(((TOTAL_NUMBER_OF_LARGE_BUFS * LARGE_BUFFER_SIZE) + +(TOTAL_NUMBER_OF_SMALL_BUFS * SMALL_BUFFER_SIZE)))]; +#else +static uint8_t buf_pool[((TOTAL_NUMBER_OF_LARGE_BUFS * LARGE_BUFFER_SIZE))]; +#endif + +/* + * Array of buffer headers + */ +static buffer_t buf_header[TOTAL_NUMBER_OF_LARGE_BUFS + +TOTAL_NUMBER_OF_SMALL_BUFS]; + +/* + * Queue of free large buffers + */ +#if (TOTAL_NUMBER_OF_LARGE_BUFS > 0) +static queue_t free_large_buffer_q; +#endif + +/* + * Queue of free small buffers + */ +#if (TOTAL_NUMBER_OF_SMALL_BUFS > 0) +static queue_t free_small_buffer_q; +#endif + +/* === Prototypes ========================================================== */ + +/* === Implementation ====================================================== */ + +/** + * @brief Initializes the buffer module. + * + * This function initializes the buffer module. + * This function should be called before using any other functionality + * of buffer module. + */ +void bmm_buffer_init(void) +{ + uint8_t index; + + /* Initialize free buffer queue for large buffers */ +#if (TOTAL_NUMBER_OF_LARGE_BUFS > 0) + #ifdef ENABLE_QUEUE_CAPACITY + qmm_queue_init(&free_large_buffer_q, TOTAL_NUMBER_OF_LARGE_BUFS); + #else + qmm_queue_init(&free_large_buffer_q); + #endif /* ENABLE_QUEUE_CAPACITY */ +#endif + + /* Initialize free buffer queue for small buffers */ +#if (TOTAL_NUMBER_OF_SMALL_BUFS > 0) + #ifdef ENABLE_QUEUE_CAPACITY + qmm_queue_init(&free_small_buffer_q, TOTAL_NUMBER_OF_SMALL_BUFS); + #else + qmm_queue_init(&free_small_buffer_q); + #endif /* ENABLE_QUEUE_CAPACITY */ +#endif + +#if (TOTAL_NUMBER_OF_LARGE_BUFS > 0) + for (index = 0; index < TOTAL_NUMBER_OF_LARGE_BUFS; index++) { + /* + * Initialize the buffer body pointer with address of the + * buffer body + */ + buf_header[index].body = buf_pool + (index * LARGE_BUFFER_SIZE); + + /* Append the buffer to free large buffer queue */ + qmm_queue_append(&free_large_buffer_q, &buf_header[index]); + } +#endif + +#if (TOTAL_NUMBER_OF_SMALL_BUFS > 0) + for (index = 0; index < TOTAL_NUMBER_OF_SMALL_BUFS; index++) { + /* + * Initialize the buffer body pointer with address of the + * buffer body + */ + buf_header[index + TOTAL_NUMBER_OF_LARGE_BUFS].body \ + = buf_pool + + (TOTAL_NUMBER_OF_LARGE_BUFS * + LARGE_BUFFER_SIZE) + \ + (index * SMALL_BUFFER_SIZE); + + /* Append the buffer to free small buffer queue */ + qmm_queue_append(&free_small_buffer_q, &buf_header[index + \ + TOTAL_NUMBER_OF_LARGE_BUFS]); + } +#endif +} + +/** + * @brief Allocates a buffer + * + * This function allocates a buffer and returns a pointer to the buffer. + * The same pointer should be used while freeing the buffer.User should + * call BMM_BUFFER_POINTER(buf) to get the pointer to buffer user area. + * + * @param size size of buffer to be allocated. + * + * @return pointer to the buffer allocated, + * NULL if buffer not available. + */ +#if defined(ENABLE_LARGE_BUFFER) +buffer_t *bmm_buffer_alloc(uint16_t size) +#else +buffer_t * bmm_buffer_alloc(uint8_t size) +#endif +{ + buffer_t *pfree_buffer = NULL; + +#if (TOTAL_NUMBER_OF_SMALL_BUFS > 0) + + /* + * Allocate buffer only if size requested is less than or equal to + * maximum + * size that can be allocated. + */ + if (size <= LARGE_BUFFER_SIZE) { + /* + * Allocate small buffer if size is less than small buffer size + * and if + * small buffer is available allocate from small buffer pool. + */ + if ((size <= SMALL_BUFFER_SIZE)) { + /* Allocate buffer from free small buffer queue */ + pfree_buffer = qmm_queue_remove(&free_small_buffer_q, + NULL); + } + + /* + * Allocate buffer only if size requested is less than or equal + * to + * maximum + * size that can be allocated. + */ + if (size <= LARGE_BUFFER_SIZE) { + /* + * Allocate small buffer if size is less than small + * buffer size + * and if + * small buffer is available allocate from small buffer + * pool. + */ + if ((size <= SMALL_BUFFER_SIZE)) { + /* Allocate buffer from free small buffer queue + **/ + pfree_buffer = qmm_queue_remove( + &free_small_buffer_q, + NULL); + } + + /* + * If size is greater than small buffer size or no free + * small + * buffer is + * available, allocate a buffer from large buffer pool + * if + * avialable + */ + if (NULL == pfree_buffer) { + /* Allocate buffer from free large buffer queue + **/ + pfree_buffer = qmm_queue_remove( + &free_large_buffer_q, + NULL); + } + } + } + +#else /* no small buffers available at all */ + /* Allocate buffer from free large buffer queue */ + pfree_buffer = qmm_queue_remove(&free_large_buffer_q, NULL); + + size = size; /* Keep compiler happy. */ + +#endif + + return pfree_buffer; +} + + /** + * @brief Frees up a buffer. + * + * This function frees up a buffer. The pointer passed to this function + * should be the pointer returned during buffer allocation. The result + * is + * unpredictable if an incorrect pointer is passed. + * + * @param pbuffer Pointer to buffer that has to be freed. + */ +void bmm_buffer_free(buffer_t *pbuffer) +{ + if (NULL == pbuffer) { + /* If the buffer pointer is NULL abort free operation */ + return; + } + +#if (TOTAL_NUMBER_OF_SMALL_BUFS > 0) + if (IS_SMALL_BUF(pbuffer)) { + /* Append the buffer into free small buffer queue */ + qmm_queue_append(&free_small_buffer_q, pbuffer); + } else { + /* Append the buffer into free large buffer queue */ + qmm_queue_append(&free_large_buffer_q, pbuffer); + } + +#else /* no small buffers available at all */ + /* Append the buffer into free large buffer queue */ + qmm_queue_append(&free_large_buffer_q, pbuffer); +#endif +} + +#endif /* (TOTAL_NUMBER_OF_BUFS > 0) */ +/* EOF */ diff --git a/driver/software/resources/queue/inc/qmm.h b/driver/software/resources/queue/inc/qmm.h new file mode 100644 index 0000000..4ea6f8f --- /dev/null +++ b/driver/software/resources/queue/inc/qmm.h @@ -0,0 +1,382 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* Prevent double inclusion */ +#ifndef QMM_INTERFACE_H +#define QMM_INTERFACE_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: File includes +// ***************************************************************************** +// ***************************************************************************** +#include "../../buffer/inc/bmm.h" + +/* + * Queue Management: provides services for creating and maintaining the queues. + * + */ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Macros +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +// ***************************************************************************** +// Section: Types +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Structure used for searching + + Summary: + Structure to search for a buffer to be removed from a queue + + Description: + search_t is used for searching the buffer in a queue + + Remarks: + None +*/ + +typedef struct search_tag +{ + /** Pointer to search criteria function */ + uint8_t (*criteria_func)(void *buf, void *handle); + /** Handle to callbck parameter */ + void *handle; +} search_t; + +// ***************************************************************************** +/* Structure holding the Queue details + + Summary: + This structure defines the queue structure + + Description: + The application should declare the queue of type queue_t + and call qmm_queue_init before invoking any other functionality of qmm. + + Remarks: + None +*/ + +typedef struct queue_tag +{ + /** Pointer to head of queue */ + buffer_t *head; + /** Pointer to tail of queue */ + buffer_t *tail; +#ifdef ENABLE_QUEUE_CAPACITY + + /** + * Maximum number of buffers that can be accomodated in the current + * queue + * Note: This is only required if the queue capacity shall be different + * from 255. + */ + uint8_t capacity; +#endif /* ENABLE_QUEUE_CAPACITY */ + + /** + * Number of buffers present in the current queue + */ + uint8_t size; +} queue_t; + + +// ***************************************************************************** +/* Enum holding the Queue layer status + + Summary: + This enum hold the different status from the queue management service + + Description: + QMM_SUCCESS - Requst to Queue layer processed successfully + QMM_QUEUE_FULL - The designated queue is full to add more buffers + + Remarks: + None +*/ + +typedef enum qmm_status_tag{ + /** Success Status */ + QMM_SUCCESS = 0x00, + /** Queue is full */ + QMM_QUEUE_FULL = 0x01 +}qmm_status_t; + +// ***************************************************************************** +// ***************************************************************************** +// Section: Externals +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +// ***************************************************************************** +// Section: Prototypes +// ***************************************************************************** +// ***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +// ***************************************************************************** +/* + Function: + void qmm_queue_init(queue_t *q, uint8_t capacity) + + Summary: + Initializes the queue + + Description: + This function initializes the queue. Note that this function + should be called before invoking any other functionality of QMM. + + Precondition: + None + + Parameters: + q - The queue which should be initialized + capacity - Queue length (Max No of buffers which can be accomodated + in the queue) + + Returns: + None. + + Example: + + queue_t app_queue; + uint8_t queue_size = 10; + qmm_queue_init(&app_queue, queue_size); + + + Remarks: + None +*/ + +#ifdef ENABLE_QUEUE_CAPACITY +void qmm_queue_init(queue_t *q, uint8_t capacity); + +#else +void qmm_queue_init(queue_t *q); + +#endif /* ENABLE_QUEUE_CAPACITY */ + +// ***************************************************************************** +/* + Function: + qmm_status_t qmm_queue_append(queue_t *q, buffer_t *buf) + + Summary: + Appends a buffer into the queue + + Description: + This function appends a buffer into the designated queue + + Precondition: + qmm_queue_init should have called for initilazing the particular queue before + using it + + Parameters: + q - Queue into which buffer should be appended + buf - Pointer to the buffer that should be appended into the queue. + Note that this pointer should be same as the + pointer returned by bmm_buffer_alloc. + + Returns: + qmm_status_t - Status of Queue request + + Example: + + queue_t app_queue; + buffer_t *app_buf; + Allocate the buffer + app_buf = bmm_buffer_alloc(LARGE_BUFFER_SIZE); + + uint8_t queue_size = 10; + qmm_queue_init(&app_queue, queue_size); + Append buffer in queue + qmm_queue_append(&app_queue, app_buf); + + + + Remarks: + None +*/ + +#ifdef ENABLE_QUEUE_CAPACITY +qmm_status_t qmm_queue_append(queue_t *q, buffer_t *buf); + +#else +void qmm_queue_append(queue_t *q, buffer_t *buf); + +#endif /* ENABLE_QUEUE_CAPACITY */ + +// ***************************************************************************** +/* + Function: + buffer_t* qmm_queue_remove(queue_t *q, search_t *search) + + Summary: + Removes a buffer from queue. + + Description: + This function removes a buffer from queue + + Precondition: + qmm_queue_init should have called for initilazing the particular queue before + using it and buffer should be appended before removing it + + Parameters: + q - Queue from which buffer should be removed + buf - Search criteria. If this parameter is NULL, first buffer in the + queue will be removed. Otherwise buffer matching the criteria will be + removed + + Returns: + return - Pointer to the buffer header, if the buffer is + successfully removed, NULL otherwise. + + Example: + + queue_t app_queue; + buffer_t *app_buf; + Allocate the buffer + app_buf = bmm_buffer_alloc(LARGE_BUFFER_SIZE); + + uint8_t queue_size = 10; + qmm_queue_init(&app_queue, queue_size); + Append buffer in queue + qmm_queue_append(&app_queue, app_buf); + //Remove buffer from queue + app_buf = qmm_queue_remove(&app_queue, NULL); + + + Remarks: + None +*/ + +buffer_t* qmm_queue_remove(queue_t *q, search_t *search); + +// ***************************************************************************** +/* + Function: + buffer_t* qmm_queue_read(queue_t *q, search_t *search) + + Summary: + Reads a buffer from queue + + Description: + This function reads either the first buffer if search is NULL or buffer + matching the given criteria from queue. + + Precondition: + qmm_queue_init should have called for initilazing the particular queue before + using it and buffer should be appended before reading it + + Parameters: + q - Queue from which buffer should be read + buf - Search criteria. If this parameter is NULL, first buffer in the + queue will be read. Otherwise buffer matching the criteria will be + read + + Returns: + return - Pointer to the buffer header, if the buffer is + successfully read, NULL otherwise. + + Example: + + queue_t app_queue; + buffer_t *app_buf; + Allocate the buffer + app_buf = bmm_buffer_alloc(LARGE_BUFFER_SIZE); + + uint8_t queue_size = 10; + qmm_queue_init(&app_queue, queue_size); + Append buffer in queue + qmm_queue_append(&app_queue, app_buf); + //Read buffer from queue + app_buf = qmm_queue_read(&app_queue, NULL); + + + Remarks: + None +*/ + +buffer_t* qmm_queue_read(queue_t *q, search_t *search); + +// ***************************************************************************** +/* + Function: + void qmm_queue_flush(queue_t *q) + + Summary: + Internal function for flushing a specific queue + + Description: + This function flushes the entire queue + + Precondition: + qmm_queue_init should have called for initilazing the particular queue before + using it. + + Parameters: + q - Queue to be flushed + + Returns: + None + + Example: + + queue_t app_queue; + buffer_t *app_buf; + Allocate the buffer + app_buf = bmm_buffer_alloc(LARGE_BUFFER_SIZE); + + uint8_t queue_size = 10; + qmm_queue_init(&app_queue, queue_size); + + qmm_queue_flush(&app_queue); + + + Remarks: + None +*/ + +void qmm_queue_flush(queue_t *q); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +/* ! @} */ +#endif /* QMM_INTERFACE_H */ + +/* EOF */ diff --git a/driver/software/resources/queue/src/qmm.c b/driver/software/resources/queue/src/qmm.c new file mode 100644 index 0000000..d29660f --- /dev/null +++ b/driver/software/resources/queue/src/qmm.c @@ -0,0 +1,305 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* === Includes ============================================================ */ + +#include +#include +#include +#include "../../../pal/inc/pal.h" +#include "../../../resources/buffer/inc/bmm.h" +#include "../../../resources/queue/inc/qmm.h" +#include "config/default/configuration.h" +#include "app_config.h" + +#if (TOTAL_NUMBER_OF_BUFS > 0) + +/* === Types =============================================================== */ + +/* + * Specifies whether the buffer needs to be read from the queue or to be + * removed from the queue. + */ +typedef enum buffer_mode_tag { + REMOVE_MODE, + READ_MODE +} buffer_mode_t; + +/* === Macros ============================================================== */ + +/* === Prototypes ========================================================== */ + +static buffer_t *queue_read_or_remove(queue_t *q, + buffer_mode_t mode, + search_t *search); + +/* === Implementation ====================================================== */ + +/** + * @brief Initializes the queue. + * + * This function initializes the queue. Note that this function + * should be called before invoking any other functionality of QMM. + * + * @param q The queue which should be initialized. + */ +#ifdef ENABLE_QUEUE_CAPACITY +void qmm_queue_init(queue_t *q, uint8_t capacity) +#else +void qmm_queue_init(queue_t *q) +#endif /* ENABLE_QUEUE_CAPACITY */ +{ + q->head = NULL; + q->tail = NULL; + q->size = 0; +#ifdef ENABLE_QUEUE_CAPACITY + q->capacity = capacity; +#endif /* ENABLE_QUEUE_CAPACITY */ +} + +/** + * @brief Appends a buffer into the queue. + * + * This function appends a buffer into the queue. + * + * @param q Queue into which buffer should be appended + * + * @param buf Pointer to the buffer that should be appended into the queue. + * Note that this pointer should be same as the + * pointer returned by bmm_buffer_alloc. + */ +#ifdef ENABLE_QUEUE_CAPACITY +qmm_status_t qmm_queue_append(queue_t *q, buffer_t *buf) +#else +void qmm_queue_append(queue_t *q, buffer_t *buf) +#endif /* ENABLE_QUEUE_CAPACITY */ +{ +#ifdef ENABLE_QUEUE_CAPACITY + qmm_status_t status; +#endif /* ENABLE_QUEUE_CAPACITY */ + + + +#ifdef ENABLE_QUEUE_CAPACITY + /* Check if queue is full */ + if (q->size == q->capacity) { + /* Buffer cannot be appended as queue is full */ + status = QMM_QUEUE_FULL; + } else +#endif /* ENABLE_QUEUE_CAPACITY */ + { + /* Check whether queue is empty */ + if (q->size == 0) { + /* Add the buffer at the head */ + q->head = buf; + } else { + /* Add the buffer at the end */ + q->tail->next = buf; + } + + /* Update the list */ + q->tail = buf; + + /* Terminate the list */ + buf->next = NULL; + + /* Update size */ + q->size++; + + + +#ifdef ENABLE_QUEUE_CAPACITY + status = QMM_SUCCESS; +#endif /* ENABLE_QUEUE_CAPACITY */ + } + + + +#ifdef ENABLE_QUEUE_CAPACITY + return (status); +#endif +} /* qmm_queue_append */ + +/* + * @brief Reads or removes a buffer from queue + * + * This function reads or removes a buffer from a queue as per + * the search criteria provided. If search criteria is NULL, then the first + * buffer is returned, otherwise buffer matching the given criteria is returned + * + * @param q Queue from which buffer is to be read or removed. + * + * @param mode Mode of operations. If this parameter has value REMOVE_MODE, + * buffer will be removed from queue and returned. If this parameter + * is + * READ_MODE, buffer pointer will be returned without + * removing from queue. + * + * @param search Search criteria structure pointer. + * + * @return Buffer header pointer, if the buffer is successfully + * removed or read, otherwise NULL is returned. + * \ingroup group_qmm + */ +static buffer_t *queue_read_or_remove(queue_t *q, + buffer_mode_t mode, + search_t *search) +{ + buffer_t *buffer_current = NULL; + buffer_t *buffer_previous; + + + /* Check whether queue is empty */ + if (q->size != 0) { + buffer_current = q->head; + buffer_previous = q->head; + + /* First get buffer matching with criteria */ + if (NULL != search) { + uint8_t match; + /* Search for all buffers in the queue */ + while (NULL != buffer_current) { + match = search->criteria_func( + (void *)buffer_current->body, + search->handle); + + if (match) { + /* Break, if search criteria matches */ + break; + } + + buffer_previous = buffer_current; + buffer_current = buffer_current->next; + } + } + + /* Buffer matching with search criteria found */ + if (NULL != buffer_current) { + /* Remove buffer from the queue */ + if (REMOVE_MODE == mode) { + /* Update head if buffer removed is first node + **/ + if (buffer_current == q->head) { + q->head = buffer_current->next; + } else { + /* Update the link by removing the + * buffer */ + buffer_previous->next + = buffer_current->next; + } + + /* Update tail if buffer removed is last node */ + if (buffer_current == q->tail) { + q->tail = buffer_previous; + } + + /* Update size */ + q->size--; + + if (NULL == q->head) { + q->tail = NULL; + } + } + /* Read buffer from the queue */ + else { + /* Nothing needs done if the mode is READ_MODE + **/ + } + } + } /* q->size != 0 */ + + + + /* Return the buffer. note that pointer to header of buffer is returned + **/ + return (buffer_current); +} /* queue_read_or_remove */ + +/** + * @brief Removes a buffer from queue. + * + * This function removes a buffer from queue + * + * @param q Queue from which buffer should be removed + * + * @param search Search criteria. If this parameter is NULL, first buffer in the + * queue will be removed. Otherwise buffer matching the criteria will be + * removed. + * + * @return Pointer to the buffer header, if the buffer is + * successfully removed, NULL otherwise. + */ +buffer_t *qmm_queue_remove(queue_t *q, search_t *search) +{ + return (queue_read_or_remove(q, REMOVE_MODE, search)); +} + +/** + * @brief Reads a buffer from queue. + * + * This function reads either the first buffer if search is NULL or buffer + * matching the given criteria from queue. + * + * @param q The queue from which buffer should be read. + * + * @param search If this parameter is NULL first buffer in the queue will be + * read. Otherwise buffer matching the criteria will be read + * + * @return Pointer to the buffer header which is to be read, NULL if the buffer + * is not available + */ +buffer_t *qmm_queue_read(queue_t *q, search_t *search) +{ + return (queue_read_or_remove(q, READ_MODE, search)); +} + +/** + * @brief Internal function for flushing a specific queue + * + * @param q Queue to be flushed + */ +void qmm_queue_flush(queue_t *q) +{ + buffer_t *buf_to_free; + + while (q->size > 0) { + /* Remove the buffer from the queue and free it */ + buf_to_free = qmm_queue_remove(q, NULL); + + if (NULL == buf_to_free) { +#if (_DEBUG_ > 0) + ABORT("Corrupted queue"); +#endif + q->size = 0; + return; + } + + bmm_buffer_free(buf_to_free); + } +} + +#endif /* (TOTAL_NUMBER_OF_BUFS > 0) */ + +/* EOF */ diff --git a/driver/templates/RF212b/phy.c.ftl b/driver/templates/RF212b/phy.c.ftl new file mode 100644 index 0000000..acfbded --- /dev/null +++ b/driver/templates/RF212b/phy.c.ftl @@ -0,0 +1,686 @@ +<#-- +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +--> + + +/* === INCLUDES ============================================================ */ + +#include +#include +#include +#include +#include "../../../pal/inc/pal.h" +#include "../../../phy/inc/phy.h" +#include "../../../phy/inc/ieee_phy_const.h" +#include "../../at86rf/inc/phy_pib.h" +#include "../../at86rf/inc/phy_irq_handler.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../../resources/buffer/inc/bmm.h" +#include "../../../resources/queue/inc/qmm.h" +#include "../../at86rf/inc/phy_rx.h" +#include "../../at86rf/inc/phy_tx.h" +#include "../../../phy/inc/phy_constants.h" +#include "../../../phy/at86rf/inc/phy_internal.h" +#include "../../../phy/at86rf/inc/phy_trx_reg_access.h" +#include "../../../phy/at86rf/inc/phy_internal.h" +#include"definitions.h" + +extern SYS_TIME_HANDLE trxEIC_waitTimer; +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + + /* Value used for checking proper locking of PLL during switch from + * TRX_PFF to PLL_ON. + */ +#define PLL_LOCK_ATTEMPTS (3) + +/* === GLOBALS ============================================================= */ + +/* + * PHY Information Base + */ +phy_info_t phy_info; + +/* + * TAL PIBs + */ +tal_pib_t tal_pib; + +/* + * Global TAL variables + * These variables are only to be used by the TAL internally. + */ + +/** + * Current state of the TAL state machine. + * \ingroup group_tal_state_machine_212b + */ +//tal_state_t tal_state; + +/** + * Current state of the transceiver. + * \ingroup group_tal_state_machine_212b + */ +//tal_trx_status_t tal_trx_status; + +/** + * Indicates if the transceiver needs to switch on its receiver by tal_task(), + * because it could not be switched on due to buffer shortage. + * \ingroup group_tal_state_machine_212b + */ +//bool tal_rx_on_required; + +/** + * Pointer to the 15.4 frame created by the TAL to be handed over + * to the transceiver. + */ +uint8_t *tal_frame_to_tx; + +/** + * Pointer to receive buffer that can be used to upload a frame from the trx. + */ +buffer_t *tal_rx_buffer = NULL; + +/** + * Queue that contains all frames that are uploaded from the trx, but have not + * be processed by the MCL yet. + */ +queue_t tal_incoming_frame_queue; + +/** + * Frame pointer for the frame structure provided by the MCL. + */ +PHY_FrameInfo_t *mac_frame_ptr; + +/* Last frame length for IFS handling. */ +//uint8_t last_frame_length; + +/* Flag indicating awake end irq at successful wake-up from sleep. */ +//volatile bool tal_awake_end_flag; + +#if (defined SW_CONTROLLED_CSMA) && (defined TX_OCTET_COUNTER) +/* Counter of transmitted octets */ +uint32_t tal_tx_octet_cnt; +#endif + + + +/* === PROTOTYPES ========================================================== */ + +static void switch_pll_on(void); + +#ifdef ENABLE_FTN_PLL_CALIBRATION +static void handle_ftn_pll_calibration(void); + +#endif /* ENABLE_FTN_PLL_CALIBRATION */ + +/* === IMPLEMENTATION ====================================================== */ +/* TODO: Include other files here if needed. */ +/* + * \brief PHY task handling + * + * This function + * - Checks and allocates the receive buffer. + * - Processes the TAL incoming frame queue. + * - Implements the TAL state machine. + */ +void PHY_TaskHandler(void) +{ + /* Check if the receiver needs to be switched on. */ + if (phy_info.tal_rx_on_required && ((phy_info.tal_state == PHY_IDLE) || (phy_info.tal_state == PHY_TX_DONE))) + { + /* Check if a receive buffer has not been available before. */ + if (tal_rx_buffer == NULL) { + tal_rx_buffer = bmm_buffer_alloc(LARGE_BUFFER_SIZE); + } + + /* Check if buffer could be allocated */ + if (NULL != tal_rx_buffer) { + /* + * Note: + * This flag needs to be reset BEFORE the received is + * switched on. + */ + phy_info.tal_rx_on_required = false; + +#ifdef PROMISCUOUS_MODE + if (tal_pib.PromiscuousMode) { + do + { + (void)set_trx_state(CMD_RX_ON); + }while (tal_get_trx_status() != RX_ON); + + } else { + do + { + (void)set_trx_state(CMD_RX_AACK_ON); + }while (tal_get_trx_status() != RX_AACK_ON); + } + +#else /* Normal operation */ + + do + { + (void)set_trx_state(CMD_RX_AACK_ON); + }while (tal_get_trx_status() != RX_AACK_ON); +#endif + } + else { + + /* no free buffer is available; try next time again */ + } + } + + /* + * If the transceiver has received a frame and it has been placed + * into the queue of the TAL, the frame needs to be processed further. + */ + if (tal_incoming_frame_queue.size > 0U) { + buffer_t *rx_frame; + + /* Check if there are any pending data in the + * incoming_frame_queue. */ + rx_frame = qmm_queue_remove(&tal_incoming_frame_queue, NULL); + if (NULL != rx_frame) { + process_incoming_frame(rx_frame); + } + } + + /* Handle the TAL state machines */ + switch (phy_info.tal_state) { + + case PHY_TX_AUTO: + (void)trx_reg_read(RG_IRQ_STATUS); + PHY_TxDoneCallback(PHY_FAILURE, mac_frame_ptr); + break; + + case PHY_IDLE: + + break; + /* Do nothing, but fall through... */ + +#ifdef SW_CONTROLLED_CSMA + case PHY_BACKOFF: + /* Do nothing, but fall through... */ + case PHY_CCA: + /* Do nothing */ + break; + + case PHY_CSMA_CONTINUE: + csma_continue(); + break; + + case PHY_CCA_DONE: + cca_done_handling(); + break; +#endif + + case PHY_TX_DONE: + tx_done_handling(); /* see tal_tx.c */ + break; + + + case PHY_ED_DONE: + ed_scan_done(); + break; + + + default: + /* Nothing to do */ + break; + } +} /* PHY_TaskHandler() */ + + +/* \brief TAL Task handling + * + * \This function handles the transceiver interrupt + * + */ + + void TAL_TaskHandler(void) + { + if (phy_info.tal_state == PHY_TX_AUTO) + { + SYS_TIME_TimerDestroy(trxEIC_waitTimer); + } + trx_irq_handler_cb(); + } + +/* + * \brief Sets transceiver state + * + * \param trx_cmd needs to be one of the trx commands + * + * \return current trx state + */ +tal_trx_status_t set_trx_state(trx_cmd_t trx_cmd) +{ + + if (phy_info.tal_trx_status == TRX_SLEEP) { + /* + * Since the wake-up procedure relies on the Awake IRQ and + * the global interrupts may be disabled at this point of time, + * we need to make sure that the global interrupts are enabled + * during wake-up procedure. + * Once the TRX is awake, the original state of the global + * interrupts + * will be restored. + */ + /* Reset wake-up interrupt flag. */ + if (CMD_SLEEP == trx_cmd) { + return TRX_SLEEP; + } + + phy_info.tal_awake_end_flag = false; + + /* Set callback function for the awake interrupt. */ + tal_trx_wakeup(); + +#if (ANTENNA_DIVERSITY == 1) + /* Enable antenna diversity. */ + trx_reg_bit_write(SR_ANT_EXT_SW_EN, ANT_EXT_SW_ENABLE); +#endif + phy_info.tal_trx_status = TRX_OFF; + + if ((trx_cmd == CMD_TRX_OFF) || + (trx_cmd == CMD_FORCE_TRX_OFF)) { + return TRX_OFF; + } + } + + + switch (trx_cmd) { /* requested state */ + case CMD_SLEEP: + + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_FORCE_TRX_OFF); +#if (ANTENNA_DIVERSITY == 1) + + /* + * Disable antenna diversity: to reduce the power consumption + * or + * avoid leakage current of an external RF switch during SLEEP. + */ + trx_reg_bit_write(SR_ANT_EXT_SW_EN, ANT_EXT_SW_DISABLE); +#endif +#ifndef SW_CONTROLLED_CSMA + { + uint16_t rand_value; + + /* + * Init the SEED value of the CSMA backoff algorithm. + */ + rand_value = (uint16_t)rand(); + trx_reg_write(RG_CSMA_SEED_0, (uint8_t)rand_value); + trx_reg_bit_write(SR_CSMA_SEED_1, + (uint8_t)(rand_value >> 8)); + } +#endif + /* Clear existing interrupts */ + (void)trx_reg_read(RG_IRQ_STATUS); + + /* + * Enable Awake_end interrupt. + * This is used for save wake-up from sleep later. + */ + //ToDO + trx_reg_write(RG_IRQ_MASK, (uint8_t)TRX_IRQ_4_CCA_ED_DONE); + trx_delay_micros(1); + TRX_SLP_TR_HIGH(); + trx_delay_micros(TRX_OFF_TO_SLEEP_TIME_CLKM_CYCLES); + phy_info.tal_trx_status = TRX_SLEEP; + return TRX_SLEEP; + break; + + + case CMD_TRX_OFF: + switch (phy_info.tal_trx_status) { + case TRX_OFF: + break; + + default: + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_TRX_OFF); + trx_delay_micros(1); + break; + } + break; + + case CMD_FORCE_TRX_OFF: + switch (phy_info.tal_trx_status) { + case TRX_OFF: + break; + + default: + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_FORCE_TRX_OFF); + trx_delay_micros(1); + break; + } + break; + + case CMD_PLL_ON: + switch (phy_info.tal_trx_status) { + + case PLL_ON: + break; + + case TRX_OFF: + switch_pll_on(); + break; + + case RX_ON: + case RX_AACK_ON: + case TX_ARET_ON: + trx_reg_write(RG_TRX_STATE, (uint8_t)TRX_OFF); + trx_delay_micros(1); + switch_pll_on(); + break; + + case BUSY_RX: + case BUSY_TX: + case BUSY_RX_AACK: + case BUSY_TX_ARET: + /* do nothing if trx is busy */ + break; + + default: + /* Nothing to do */ + break; + } + break; + + case CMD_FORCE_PLL_ON: + switch (phy_info.tal_trx_status) { + case TRX_OFF: + switch_pll_on(); + break; + + case PLL_ON: + break; + + default: + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_FORCE_PLL_ON); + break; + } + break; + + case CMD_RX_ON: + switch (phy_info.tal_trx_status) { + case RX_ON: + break; + case PLL_ON: + case RX_AACK_ON: + case TX_ARET_ON: + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_TRX_OFF); + trx_delay_micros(1); + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_RX_ON); + trx_delay_micros(1); + break; + + case TRX_OFF: + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_RX_ON); + trx_delay_micros(1); + break; + + case BUSY_RX: + case BUSY_TX: + case BUSY_RX_AACK: + case BUSY_TX_ARET: + /* do nothing if trx is busy */ + break; + + default: + /* Nothing to do */ + break; + } + break; + + case CMD_RX_AACK_ON: + switch (phy_info.tal_trx_status) { + case RX_AACK_ON: + break; + case TX_ARET_ON: + case PLL_ON: + case RX_ON: + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_TRX_OFF); + trx_delay_micros(1); + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_RX_AACK_ON); + trx_delay_micros(1); + break; + + case TRX_OFF: + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_RX_AACK_ON); + trx_delay_micros(1); + break; + + case BUSY_RX: + case BUSY_RX_AACK: + case BUSY_TX: + case BUSY_TX_ARET: + /* do nothing if trx is busy */ + break; + + default: + /* Nothing to do */ + break; + } + break; + + case CMD_TX_ARET_ON: + switch (phy_info.tal_trx_status) { + case TX_ARET_ON: + break; + + case PLL_ON: + case RX_ON: + case RX_AACK_ON: + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_TRX_OFF); + trx_delay_micros(1); + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_TX_ARET_ON); + trx_delay_micros(1); + break; + + case TRX_OFF: + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_TX_ARET_ON); + trx_delay_micros(1); + break; + + case BUSY_RX: + case BUSY_TX: + case BUSY_RX_AACK: + case BUSY_TX_ARET: + /* do nothing if trx is busy */ + break; + + default: + /* Nothing to do */ + break; + } + break; + + default: + /* Nothing to do */ + break; + } + + uint8_t count = 0; + + do { + count++; + uint8_t temp = (0x1FU) & (trx_reg_read(RG_TRX_STATUS)); + phy_info.tal_trx_status = (tal_trx_status_t)temp; + if (count == 100) + { + break; + } + } while (phy_info.tal_trx_status == STATE_TRANSITION_IN_PROGRESS); + + return phy_info.tal_trx_status; +} /* set_trx_state() */ + +/** + * \brief Switches the PLL on + * \ingroup group_tal_state_machine + */ +static void switch_pll_on(void) +{ + trx_irq_reason_t irq_status; + uint8_t poll_counter = 0; + + /* Check if trx is in TRX_OFF; only from PLL_ON the following procedure + * is applicable */ + if (trx_reg_bit_read(SR_TRX_STATUS) != (uint8_t)TRX_OFF) { + + return; + } + + (void)trx_reg_read(RG_IRQ_STATUS); /* clear PLL lock bit */ + /* Switch PLL on */ + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_PLL_ON); + + /* Check if PLL has been locked. */ + do { + irq_status = (trx_irq_reason_t)trx_reg_read(RG_IRQ_STATUS); + + if (irq_status & TRX_IRQ_0_PLL_LOCK) { + return; /* PLL is locked now */ + } + + /* Wait a time interval of typical value for timer TR4. */ + trx_delay_micros(TRX_OFF_TO_PLL_ON_TIME_US); + + poll_counter++; + } while (poll_counter < PLL_LOCK_ATTEMPTS); +} + + +PHY_TrxStatus_t PHY_GetTrxStatus(void) +{ + tal_trx_status_t trx_status = tal_get_trx_status(); + PHY_TrxStatus_t trx_state; + + switch(trx_status) + { + case TRX_OFF: + case P_ON: + case PLL_ON: + trx_state = PHY_TRX_OFF; + break; + + case RX_ON: + case RX_AACK_ON: + trx_state = PHY_RX_ON; + break; + + case TX_ARET_ON: + trx_state = PHY_TX_ON; + break; + + case BUSY_RX: + case BUSY_RX_AACK: + trx_state = PHY_BUSY_RX; + break; + + case BUSY_TX: + case BUSY_TX_ARET: + trx_state = PHY_BUSY_TX; + break; + + case TRX_SLEEP: + trx_state = PHY_TRX_SLEEP; + break; + + + default: + trx_state = PHY_TRX_OFF; + break; + } + + return trx_state; +} + + +uint32_t PHY_GetSWVersion(void) +{ + uint32_t phyVersion; + + phyVersion = phy_info.phyVersion; + + return phyVersion; +} + + +/** + * @brief Conversion of symbols to microseconds + */ +uint32_t tal_convert_symbols_to_us_def(uint32_t symbols) +{ + return (PHY_CONVERT_SYMBOLS_TO_US(symbols)); +} + +/** + * @brief Conversion of microseconds to symbols + */ +uint32_t tal_convert_us_to_symbols_def(uint32_t time_) +{ + return (PHY_CONVERT_US_TO_SYMBOLS(time_)); +} + +void trx_delay_loop(void *hw, uint32_t cycles) +{ + (void) hw; + (void) cycles; + + /* + * SUBS instruction - 1 cycle + * BHI instruction - 2 cycles if taken; 1 if not taken + * + * In most case: 3 cycles is the loop time + */ + + __asm__( + ".syntax unified\n" + "__dly:\n" + "subs r1, r1, #1\n" + "bhi __dly\n" + ".syntax divided" + ); +} + +void trx_delay_millis(uint32_t ms) +{ + uint32_t cycles = ((uint32_t)PAL_CPU_CLOCK_FREQUENCY / 1000UL) * ms; + cycles /= 3UL; + trx_delay_loop(NULL, cycles); +} + +void trx_delay_micros(uint32_t us) +{ + uint32_t cycles = ((uint32_t)PAL_CPU_CLOCK_FREQUENCY / 1000000UL) * us; + cycles /= 3UL; + trx_delay_loop(NULL, cycles); +} + + +/* EOF */ diff --git a/driver/templates/RF212b/phy_init.c.ftl b/driver/templates/RF212b/phy_init.c.ftl new file mode 100644 index 0000000..aa6cda9 --- /dev/null +++ b/driver/templates/RF212b/phy_init.c.ftl @@ -0,0 +1,651 @@ +<#-- +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +--> + + +/* === INCLUDES ============================================================ */ + +#include +#include +#include +#include +#include +#include + +#include "../../../phy/inc/phy.h" +#include "../../../resources/buffer/inc/bmm.h" +#include "../../../resources/queue/inc/qmm.h" + +#include "../../../phy/inc/ieee_phy_const.h" +#include "../../at86rf/inc/phy_pib.h" +#include "../../at86rf/inc/phy_irq_handler.h" +#include "../../at86rf/inc/phy_tx.h" +#include "../../at86rf/inc/phy_rx.h" + + +#include "../../../pal/inc/pal.h" + +#include "../../at86rf/inc/phy_internal.h" +#include "../../../phy/inc/phy_constants.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../../phy/at86rf/inc/phy_trx_reg_access.h" + + + + + + + +/** + * \addtogroup group_tal_init_233 + * @{ + */ + +/* === MACROS ============================================================== */ + +/* Value in us used for delay between poll attempts for transceiver access. */ +#define TRX_POLL_WAIT_TIME_US (100U) + +/* Ratio between max time of TR1 / transceiver poll delay */ +#define P_ON_TO_CLKM_ATTEMPTS ((uint8_t) \ + (P_ON_TO_CLKM_AVAILABLE_MAX_US / TRX_POLL_WAIT_TIME_US)) + +/* Ratio between max time of TR2 / transceiver poll delay */ +#define SLEEP_TO_TRX_OFF_ATTEMPTS ((uint8_t) \ + (SLEEP_TO_TRX_OFF_MAX_US / TRX_POLL_WAIT_TIME_US)) + + + +#define VECTOR_TABLE_SIZE 128 + +/* === GLOBALS ============================================================= */ + + + + +TimerId_t TAL_RETRY_TIMER; + +/* === PROTOTYPES ========================================================== */ + +static PHY_Retval_t trx_init(void); +static void trx_config(void); +static PHY_Retval_t trx_reset(void); +static PHY_Retval_t internal_tal_reset(bool set_default_pib); + +/** + * \brief Initializes all timers used by the TAL module by assigning id's to + * each of them + */ +static PHY_Retval_t tal_timer_init(void); + +/** + * \brief Stops all initialized TAL timers + */ +static void tal_timers_stop(void); + + + +/* ! @} */ + +/* === IMPLEMENTATION ====================================================== */ + +/* + * \brief Initializes the TAL + * + * This function is called to initialize the TAL. The transceiver is + * initialized, the TAL PIBs are set to their default values, and the TAL state + * machine is set to TAL_IDLE state. + * + * \return PHY_SUCCESS if the transceiver state is changed to TRX_OFF and the + * current device part number and version number are correct; + * PHY_FAILURE otherwise + */ +PHY_Retval_t PHY_Init(void) +{ + + /* Init the PAL and by this means also the transceiver interface */ + if (PAL_Init() != PAL_SUCCESS) { + return PHY_FAILURE; + } + + if (trx_init() != PHY_SUCCESS) { + return PHY_FAILURE; + } + + + if (tal_timer_init() != PHY_SUCCESS) { + return PHY_FAILURE; + } + + /* + * Do the reset stuff. + * Set the default PIBs. + * Generate random seed. + */ + if (internal_tal_reset(true) != PHY_SUCCESS) { + return PHY_FAILURE; + } + +#ifndef DISABLE_IEEE_ADDR_CHECK + /* Check if a valid IEEE address is available. */ + + /* + * This while loop is on purpose, since just in the + * rare case that such an address is randomly + * generated again, we must repeat this. + */ + uint64_t invalid_ieee_address; + (void)memset((uint8_t *)&invalid_ieee_address, 0xFF, + sizeof(invalid_ieee_address)); + while ((tal_pib.IeeeAddress == 0x0000000000000000U) || + (tal_pib.IeeeAddress == invalid_ieee_address)) { + /* + * In case no valid IEEE address is available, a random + * IEEE address will be generated to be able to run the + * applications for demonstration purposes. + * In production code this can be omitted. + */ + + /* + * The proper seed for function rand() has already been + * generated + * in function tal_generate_rand_seed(). + */ + uint8_t *ptr_pib = (uint8_t *)&(tal_pib.IeeeAddress); + + for (uint8_t i = 0; i < 8; i++) { + *ptr_pib++ = (uint8_t)rand(); + + /* + * Note: + * Even if casting the 16 bit rand value back to 8 bit, + * and running the loop 8 timers (instead of only 4 + * times) + * may look cumbersome, it turns out that the code gets + * smaller using 8-bit here. + * And timing is not an issue at this place... + */ + } + } +#endif /* #ifndef DISABLE_IEEE_ADDR_CHECK */ + /* + * Configure interrupt handling. + * Install a handler for the transceiver interrupt. + */ + EIC_CallbackRegister(EIC_PIN_${SELECTED_EIC_CHANNEL}, EIC_interrupt_cb, 0); + + pal_trx_irq_en(); /* Enable transceiver main interrupt. */ + + + /* Initialize the buffer management module and get a buffer to store + * received frames. */ + bmm_buffer_init(); + tal_rx_buffer = bmm_buffer_alloc(LARGE_BUFFER_SIZE); + + if (tal_rx_buffer == NULL) { + return PHY_FAILURE; + } + + + /* Init incoming frame queue */ +#ifdef ENABLE_QUEUE_CAPACITY + qmm_queue_init(&tal_incoming_frame_queue, + PHY_INCOMING_FRAME_QUEUE_CAPACITY); +#else + qmm_queue_init(&tal_incoming_frame_queue); +#endif /* ENABLE_QUEUE_CAPACITY */ + + tfa_init(); + + phy_info.phyVersion = PHY_VERSION_VALUE; + + return PHY_SUCCESS; +} /* tal_init() */ + +/** + * \brief Initializes the transceiver + * + * This function is called to initialize the transceiver. + * + * \return PHY_SUCCESS if the transceiver state is changed to TRX_OFF and the + * current device part number and version number are correct; + * PHY_FAILURE otherwise + */ +static PHY_Retval_t trx_init(void) +{ + volatile tal_trx_status_t trx_status; + uint8_t poll_counter = 0; + + + /* Wait typical time of timer TR1. */ + trx_delay_micros(P_ON_TO_CLKM_AVAILABLE_TYP_US); + + /* make sure SPI is working properly */ + /* while ((tal_trx_status_t)trx_bit_read(SR_TRX_STATUS) != P_ON); */ + + + /* Apply reset pulse Ensure control lines have correct levels */ + TRX_SEL_HIGH(); + TRX_RST_LOW(); + TRX_SLP_TR_LOW(); + trx_delay_micros(RST_PULSE_WIDTH_US); + TRX_RST_HIGH(); + + /* Wait typical time of timer TR13. */ + trx_delay_micros(30); + + trx_status = (tal_trx_status_t)trx_reg_bit_read(SR_TRX_STATUS); + + /* Dummy assignment, to avoid compiler warning */ + trx_status = trx_status; + +#if !(defined FPGA_EMULATION) + do { + /* Wait not more than max. value of TR1. */ + if (poll_counter == P_ON_TO_CLKM_ATTEMPTS) { + + return PHY_FAILURE; + } + /* Wait a short time interval. */ + trx_delay_micros(TRX_POLL_WAIT_TIME_US); + poll_counter++; + + /* Check if AT86RF212B is connected; omit manufacturer id check + **/ + } while (trx_reg_read(RG_PART_NUM) != PART_NUM_AT86RF212B); +#endif /* !defined FPGA_EMULATION */ + + /* Verify that TRX_OFF can be written */ + + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_TRX_OFF); + + /* Verify that the trx has reached TRX_OFF. */ + tal_trx_status_t trx_status_check; + trx_status_check = (tal_trx_status_t)trx_reg_bit_read(SR_TRX_STATUS); + if (trx_status_check != TRX_OFF) { + return PHY_FAILURE; + } + + + trx_reg_write(RG_IRQ_MASK, TRX_NO_IRQ); + phy_info.tal_trx_status = TRX_OFF; + + + return PHY_SUCCESS; +} + +/** + * \brief Internal TAL reset function + * + * \param set_default_pib Defines whether PIB values need to be set + * to its default values + * + * \return PHY_SUCCESS if the transceiver state is changed to TRX_OFF and the + * current device part number and version number are correct; + * PHY_PHY_FAILURE otherwise + */ +static PHY_Retval_t internal_tal_reset(bool set_default_pib) +{ + if (trx_reset() != PHY_SUCCESS) { + return PHY_FAILURE; + } + + /* + * Generate a seed for the random number generator in function rand(). + * This is required (for example) as seed for the CSMA-CA algorithm. + */ + tal_generate_rand_seed(); + + + /* Configure the transceiver register values. */ + trx_config(); + + if (set_default_pib) { + /* Set the default PIB values */ + init_tal_pib(); /* implementation can be found in 'tal_pib.c' */ + } else { + /* nothing to do - the current TAL PIB attribute values are used + **/ + } + + /* + * Write all PIB values to the transceiver + * that are needed by the transceiver itself. + */ + write_all_tal_pib_to_trx(); /* implementation can be found in + *'tal_pib.c' */ + + /* Reset TAL variables. */ + phy_info.tal_state = PHY_IDLE; + + + + + + phy_info.tal_rx_on_required = false; + + return PHY_SUCCESS; +} + +/** + * \brief Configures the transceiver + * + * This function is called to configure the transceiver after reset. + */ +void trx_config(void) +{ + + + + /* Set pin driver strength */ + trx_reg_bit_write(SR_PAD_IO_CLKM, PAD_CLKM_2_MA); + trx_reg_bit_write(SR_CLKM_SHA_SEL, CLKM_SHA_DISABLE); + +#ifndef SW_CONTROLLED_CSMA + /* + * After we have initialized a proper seed for rand(), + * the transceiver's CSMA seed can be initialized. + * It needs to be assured that a seed for function rand() + * had been generated before. + */ + + /* + * Init the SEED value of the CSMA backoff algorithm. + */ + uint16_t rand_value = (uint16_t)rand(); + trx_reg_write(RG_CSMA_SEED_0, (uint8_t)rand_value); + trx_reg_bit_write(SR_CSMA_SEED_1, (uint8_t)(rand_value >> 8)); + +// /* +// * To make sure that the CSMA seed is properly set within the +// * transceiver, +// * put the trx to sleep briefly and wake it up again. +// */ +// PHY_TrxSleep(SLEEP_MODE_1); +// PHY_TrxWakeup(); +#endif + + + trx_reg_bit_write(SR_AACK_SET_PD, SET_PD); /* ACKs for data requests, + * indicate pending data */ + trx_reg_bit_write(SR_RX_SAFE_MODE, RX_SAFE_MODE_ENABLE); /* Enable + * buffer + * protection + * mode */ + trx_reg_bit_write(SR_IRQ_MASK_MODE, IRQ_MASK_MODE_ON); /* Enable poll + * mode */ + trx_reg_write(RG_IRQ_MASK, (uint8_t)TRX_IRQ_DEFAULT); /* The TRX_END + * interrupt of the + * transceiver is + * enabled. */ + + + +#if (ANTENNA_DIVERSITY == 1) + trx_reg_bit_write(SR_ANT_EXT_SW_EN, ANT_EXT_SW_ENABLE); /* Enable + * antenna + * diversity. */ +#if (ANTENNA_DEFAULT != ANT_CTRL_1) + trx_reg_bit_write(SR_ANT_CTRL, ANTENNA_DEFAULT); +#endif /* ANTENNA_DEFAULT */ +#endif /* ANTENNA_DIVERSITY */ + + +#ifdef CCA_ED_THRESHOLD + + /* + * Set CCA ED Threshold to other value than standard register due to + * board specific loss (see pal_config.h). */ + trx_reg_bit_write(SR_CCA_ED_THRES, CCA_ED_THRESHOLD); +#endif + +#ifndef ENABLE_RX_OVERRIDE + trx_reg_bit_write(SR_RX_OVERRIDE, RXO_ENABLE); +#else + + /* + * Allow overriding of a 'weak' frame when another frame with stronger + * signal power arrives during the reception of this 'weak' frame. + */ + trx_reg_bit_write(SR_RX_OVERRIDE, ENABLE_RX_OVERRIDE); +#endif /* ENABLE_RX_OVERRIDE */ +} + +/** + * \brief Reset transceiver + * + * \return PHY_SUCCESS if the transceiver state is changed to TRX_OFF + * PHY_FAILURE otherwise + */ +static PHY_Retval_t trx_reset(void) +{ + tal_trx_status_t trx_status; + uint8_t poll_counter = 0; + /* trx might sleep, so wake it up */ + TRX_SLP_TR_LOW(); + trx_delay_micros(SLEEP_TO_TRX_OFF_TYP_US); + /* Apply reset pulse */ + TRX_RST_LOW(); + trx_delay_micros(RST_PULSE_WIDTH_US); + TRX_RST_HIGH(); + + /* verify that trx has reached TRX_OFF */ + do { + /* Wait a short time interval. */ + trx_delay_micros(TRX_POLL_WAIT_TIME_US); + + trx_status =(tal_trx_status_t)trx_reg_bit_read(SR_TRX_STATUS); + + /* Wait not more than max. value of TR2. */ + if (poll_counter == SLEEP_TO_TRX_OFF_ATTEMPTS) { + + return PHY_FAILURE; + } + + poll_counter++; + } while (trx_status != TRX_OFF); + + phy_info.tal_trx_status = TRX_OFF; + + + return PHY_SUCCESS; +} + +/* + * \brief Resets TAL state machine and sets the default PIB values if requested + * + * \param set_default_pib Defines whether PIB values need to be set + * to its default values + * + * \return PHY_SUCCESS if the transceiver state is changed to TRX_OFF + * PHY_FAILURE otherwise + */ +PHY_Retval_t PHY_Reset(bool set_default_pib) +{ + /* + * Do the reset stuff. + * Set the default PIBs depending on the given parameter + * set_default_pib. + * Do NOT generate random seed again. + */ + if (internal_tal_reset(set_default_pib) != PHY_SUCCESS) { + return PHY_FAILURE; + } + + ENTER_CRITICAL_REGION(); + tal_timers_stop(); + LEAVE_CRITICAL_REGION(); + + /* Clear TAL Incoming Frame queue and free used buffers. */ + while (tal_incoming_frame_queue.size > 0U) { + buffer_t *frame = qmm_queue_remove(&tal_incoming_frame_queue, + NULL); + if (NULL != frame) { + bmm_buffer_free(frame); + } + } + tfa_reset(set_default_pib); + /* + * Configure interrupt handling. + * Install a handler for the transceiver interrupt. + */ + EIC_CallbackRegister(EIC_PIN_${SELECTED_EIC_CHANNEL}, EIC_interrupt_cb, 0); + /* The pending transceiver interrupts on the microcontroller are + * cleared. */ + pal_trx_irq_en(); /* Enable transceiver main interrupt. */ + + return PHY_SUCCESS; +} + +/* + * \brief Generates a 16-bit random number used as initial seed for srand() + * + * This function generates a 16-bit random number by means of using the + * Random Number Generator from the transceiver. + * The Random Number Generator generates 2-bit random values. These 2-bit + * random values are concatenated to the required 16-bit random seed. + * + * The generated random 16-bit number is feed into function srand() + * as initial seed. + * + * The transceiver state is initally set to RX_ON. + * After the completion of the random seed generation, the + * trancseiver is set to TRX_OFF. + * + * As a prerequisite the preamble detector must not be disabled. + * + * Also in case the function is called from a different state than TRX_OFF, + * additional trx state handling is required, such as reading the original + * value and restoring this state after finishing the sequence. + * Since in our case the function is called from TRX_OFF, this is not required + * here. + */ + +void tal_generate_rand_seed(void) +{ + uint16_t seed = 0; + uint8_t cur_random_val = 0; + + /* Ensure that PLL has locked and receive mode is reached. */ + tal_trx_status_t trx_state; + do { + trx_state = set_trx_state(CMD_RX_ON); + } while (trx_state != RX_ON); + + /* Ensure that register bit RX_PDT_DIS is set to 0. */ + trx_reg_bit_write(SR_RX_PDT_DIS, RX_ENABLE); + + /* + * We need to disable TRX IRQs while generating random values in RX_ON, + * we do not want to receive frames at this point of time at all. + */ + EIC_InterruptDisable(EIC_PIN_${SELECTED_EIC_CHANNEL}); + + /* + * The 16-bit random value is generated from various 2-bit random + * values. + */ + for (uint8_t i = 0; i < 8; i++) { + /* Now we can safely read the 2-bit random number. */ + cur_random_val = trx_reg_bit_read(SR_RND_VALUE); + seed = seed << 2; + seed |= cur_random_val; + trx_delay_micros(1); /* wait that the random value gets updated */ + } + + (void)set_trx_state(CMD_FORCE_TRX_OFF); + + /* + * Now we need to clear potential pending TRX IRQs and + * enable the TRX IRQs again. + */ + (void)trx_reg_read(RG_IRQ_STATUS); + EIC_REGS->EIC_INTFLAG = (1UL << EIC_PIN_${SELECTED_EIC_CHANNEL}); + EIC_InterruptEnable(EIC_PIN_${SELECTED_EIC_CHANNEL}); + + /* Set the seed for the random number generator. */ + srand(seed); +} + +static PHY_Retval_t tal_timer_init(void) +{ + /* Timer used for Retransmission caused by Arbiter Abort failure*/ + if (PAL_SUCCESS != PAL_TimerGetId(&TAL_RETRY_TIMER)) { + return PHY_FAILURE; + } +#ifdef ENABLE_FTN_PLL_CALIBRATION + if (PAL_SUCCESS != PAL_TimerGetId(&TAL_CALIBRATION)) { + return PHY_FAILURE; + } + +#ifdef SW_CONTROLLED_CSMA + if (PAL_SUCCESS != PAL_TimerGetId(&TAL_T_BOFF)) { + return PHY_FAILURE; + } +#endif + +#else +#ifdef SW_CONTROLLED_CSMA + if (PAL_SUCCESS != PAL_TimerGetId(&TAL_T_BOFF)) { + return PHY_FAILURE; + } +#endif +#endif /* ENABLE_FTN_PLL_CALIBRATION */ + return PHY_SUCCESS; +} + +static void tal_timers_stop(void) +{ +#if (NUMBER_OF_PHY_TIMERS > 0) + (void)PAL_TimerStop(TAL_RETRY_TIMER); + +#ifdef ENABLE_FTN_PLL_CALIBRATION + (void)PAL_TimerStop(TAL_CALIBRATION); +#ifdef SW_CONTROLLED_CSMA + (void)PAL_TimerStop(TAL_T_BOFF); +#endif + +#else +#ifdef SW_CONTROLLED_CSMA + (void)PAL_TimerStop(TAL_T_BOFF); +#endif +#endif /* ENABLE_FTN_PLL_CALIBRATION */ +#endif /* (NUMBER_OF_TAL_TIMERS > 0)*/ +} + +void trx_irq_flag_clear(void) +{ + uint8_t trx_irq_cause; + + trx_irq_cause = trx_reg_read(RG_IRQ_STATUS); + + (void)trx_irq_cause; +} + + + + + +/**************************/ +/* EOF */ diff --git a/driver/templates/RF212b/phy_trx_reg_access.c.ftl b/driver/templates/RF212b/phy_trx_reg_access.c.ftl new file mode 100644 index 0000000..dd8aac9 --- /dev/null +++ b/driver/templates/RF212b/phy_trx_reg_access.c.ftl @@ -0,0 +1,218 @@ +<#-- +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +--> + + +/* === INCLUDES ============================================================ */ + + + +#include "definitions.h" +#include "../../../pal/inc/pal.h" +#include "../../at86rf/inc/phy_trx_reg_access.h" + + + +void trx_reg_write(uint8_t addr, uint8_t value) +{ + pal_trx_irq_dis(); + /* Prepare the command byte */ + addr |= WRITE_ACCESS_COMMAND; + + /* Start SPI transaction by pulling SEL low */ + SPI_SS_Clear(); + + /* Send the Read command byte */ + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Write(&addr, 1); + + /* Write the byte in the transceiver data register */ + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Write(&value, 1); + + while (${SELECTED_SERCOM}_IsBusy()){} + + /* Stop the SPI transaction by setting SEL high */ + SPI_SS_Set(); + pal_trx_irq_en(); +} + + +uint8_t trx_reg_read(uint8_t addr) +{ + pal_trx_irq_dis(); + + uint16_t register_value; + + /* Prepare the command byte */ + addr |= READ_ACCESS_COMMAND; + + /* Start SPI transaction by pulling SEL low */ + SPI_SS_Clear(); + + /* Send the Read command byte */ + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Write(&addr, 1); + + /* Read the byte from the transceiver data register */ + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Read(®ister_value, 1); + + while(${SELECTED_SERCOM}_IsBusy()){} + + /* Stop the SPI transaction by setting SEL high */ + SPI_SS_Set(); + + pal_trx_irq_en(); + + return register_value; +} + + +void trx_reg_bit_write(uint8_t addr, uint8_t mask, uint8_t pos, uint8_t value) +{ + uint8_t reg; + reg = trx_reg_read(addr); + reg = ((reg & ~mask) | (((value) << pos) & mask)); + trx_reg_write(addr, reg); +} + + +uint8_t trx_reg_bit_read(uint8_t addr, uint8_t mask, uint8_t pos) +{ + uint8_t reg; + reg = trx_reg_read(addr); + reg = (reg & mask) >> (pos); + return reg; +} + + + + +void trx_frame_write(uint8_t* buf, uint8_t length) +{ + pal_trx_irq_dis(); + uint8_t temp; + + /* Start SPI transaction by pulling SEL low */ + SPI_SS_Clear(); + temp = TRX_CMD_FW; + + while (${SELECTED_SERCOM}_IsBusy()){} + /* Send the command byte */ + ${SELECTED_SERCOM}_Write(&temp, 1); + while (${SELECTED_SERCOM}_IsBusy()){} + /* Write into the buffer */ + ${SELECTED_SERCOM}_Write(buf, length); + + while (${SELECTED_SERCOM}_IsBusy()){} + + /* Stop the SPI transaction by setting SEL high */ + SPI_SS_Set(); + pal_trx_irq_en(); +} + + + + +void trx_frame_read(uint8_t* buf, uint8_t length) +{ + pal_trx_irq_dis(); + + uint16_t temp; + /* Start SPI transaction by pulling SEL low */ + SPI_SS_Clear(); + + temp = TRX_CMD_FR; + + while (${SELECTED_SERCOM}_IsBusy()){} + /* Send the command byte */ + ${SELECTED_SERCOM}_Write(&temp, 1); + while (${SELECTED_SERCOM}_IsBusy()){} + + ${SELECTED_SERCOM}_Read(buf, length); + + while (${SELECTED_SERCOM}_IsBusy()){} + + /* Stop the SPI transaction by setting SEL high */ + SPI_SS_Set(); + pal_trx_irq_en(); +} + +void trx_sram_write(uint8_t addr, uint8_t *data, uint8_t length) +{ + pal_trx_irq_dis(); + uint8_t temp; + + /* Start SPI transaction by pulling SEL low */ + SPI_SS_Clear(); + + temp = TRX_CMD_SW; + + /* Send the command byte */ + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Write(&temp, 1); + + /* Send the address from which the write operation should start */ + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Write(&addr, 1); + + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Write(data, length); + + while (${SELECTED_SERCOM}_IsBusy()){} + + /* Stop the SPI transaction by setting SEL high */ + SPI_SS_Set(); + pal_trx_irq_en(); +} + +void trx_sram_read(uint8_t addr, uint8_t *data, uint8_t length) +{ + pal_trx_irq_dis(); + uint16_t temp; + + /* Start SPI transaction by pulling SEL low */ + SPI_SS_Clear(); + + temp = TRX_CMD_SR; + + /* Send the command byte */ + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Write(&temp, 1); + + /* Send the address from which the read operation should start */ + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Write(&addr, 1); + + /* Upload the received byte in the user provided location */ + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Read(data, length); + + while (${SELECTED_SERCOM}_IsBusy()){} + + /* Stop the SPI transaction by setting SEL high */ + SPI_SS_Set(); + pal_trx_irq_en(); +} diff --git a/driver/templates/RF212b/phy_trx_reg_access.h.ftl b/driver/templates/RF212b/phy_trx_reg_access.h.ftl new file mode 100644 index 0000000..da004d8 --- /dev/null +++ b/driver/templates/RF212b/phy_trx_reg_access.h.ftl @@ -0,0 +1,110 @@ +<#-- +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +--> + + +#ifndef TRX_REG_ACCESS_H /* Guard against multiple inclusion */ +#define TRX_REG_ACCESS_H + + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Included Files */ +/* ************************************************************************** */ +/* ************************************************************************** */ +#include "at86rf.h" +#include "../default/definitions.h" +#include "../../../pal/inc/pal.h" +/* Provide C++ Compatibility */ +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * Write access command of the transceiver + */ +#define WRITE_ACCESS_COMMAND (0xC0U) + +/** + * Read access command to the tranceiver + */ +#define READ_ACCESS_COMMAND (0x80U) + +/** + * Frame write command of transceiver + */ +#define TRX_CMD_FW (0x60U) + +/** + * Frame read command of transceiver + */ +#define TRX_CMD_FR (0x20U) + +/** + * SRAM write command of transceiver + */ +#define TRX_CMD_SW (0x40U) + +/** + * SRAM read command of transceiver + */ +#define TRX_CMD_SR (0x00U) + +#define TRX_TRIG_DELAY() {nop(); nop(); } + +void trx_reg_write(uint8_t addr, uint8_t value); + +uint8_t trx_reg_read(uint8_t addr); + +void trx_reg_bit_write(uint8_t addr, uint8_t mask, uint8_t pos, uint8_t value); + +uint8_t trx_reg_bit_read(uint8_t addr, uint8_t mask, uint8_t pos); + +void trx_frame_write(uint8_t* buf, uint8_t length); + +void trx_frame_read(uint8_t* buf, uint8_t length); + +void trx_sram_write(uint8_t addr, uint8_t *data, uint8_t length); + +void trx_sram_read(uint8_t addr, uint8_t *data, uint8_t length); + + + + /* Provide C++ Compatibility */ +#ifdef __cplusplus +} +#endif + +/* ***************************************************************************** + End of File + */ + + +#endif /* _EXAMPLE_FILE_NAME_H */ + +/* ***************************************************************************** + End of File + */ \ No newline at end of file diff --git a/driver/templates/RF233/phy.c.ftl b/driver/templates/RF233/phy.c.ftl new file mode 100644 index 0000000..ace8fca --- /dev/null +++ b/driver/templates/RF233/phy.c.ftl @@ -0,0 +1,765 @@ +<#-- +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +--> + + +/* === INCLUDES ============================================================ */ + +#include +#include +#include +#include +#include "../../../pal/inc/pal.h" +#include "../../../phy/inc/phy.h" +#include "../../../phy/inc/ieee_phy_const.h" +#include "../../at86rf/inc/phy_pib.h" +#include "../../at86rf/inc/phy_irq_handler.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../../resources/buffer/inc/bmm.h" +#include "../../../resources/queue/inc/qmm.h" +#include "../../at86rf/inc/phy_rx.h" +#include "../../at86rf/inc/phy_tx.h" +#include "../../../phy/inc/phy_constants.h" +#include "../../../phy/at86rf/inc/phy_internal.h" +#include "../../../phy/at86rf/inc/phy_trx_reg_access.h" +#include "../../../phy/at86rf/inc/phy_internal.h" +#include"definitions.h" + +extern SYS_TIME_HANDLE trxEIC_waitTimer; + +/* === TYPES =============================================================== */ + +/* === MACROS ============================================================== */ + + /* Value used for checking proper locking of PLL during switch from + * TRX_PFF to PLL_ON. + */ +#define PLL_LOCK_ATTEMPTS (3) + +/* === GLOBALS ============================================================= */ + +/* + * PHY Information Base + */ +phy_info_t phy_info; + +/* + * TAL PIBs + */ +tal_pib_t tal_pib; + +/* + * Global TAL variables + * These variables are only to be used by the TAL internally. + */ + +/** + * Current state of the TAL state machine. + * \ingroup group_tal_state_machine_233 + */ +//tal_state_t tal_state; + +/** + * Current state of the transceiver. + * \ingroup group_tal_state_machine_233 + */ +//tal_trx_status_t tal_trx_status; + +/** + * Indicates if the transceiver needs to switch on its receiver by tal_task(), + * because it could not be switched on due to buffer shortage. + * \ingroup group_tal_state_machine_233 + */ +//bool tal_rx_on_required; + +/** + * Pointer to the 15.4 frame created by the TAL to be handed over + * to the transceiver. + */ +uint8_t *tal_frame_to_tx; + +/** + * Pointer to receive buffer that can be used to upload a frame from the trx. + */ +buffer_t *tal_rx_buffer = NULL; + +/** + * Queue that contains all frames that are uploaded from the trx, but have not + * be processed by the MCL yet. + */ +queue_t tal_incoming_frame_queue; + +/** + * Frame pointer for the frame structure provided by the MCL. + */ +PHY_FrameInfo_t *mac_frame_ptr; + +/* Last frame length for IFS handling. */ +//uint8_t last_frame_length; + +/* Flag indicating awake end irq at successful wake-up from sleep. */ +//volatile bool tal_awake_end_flag; + + + + +/* === PROTOTYPES ========================================================== */ + +static void switch_pll_on(void); + +#ifdef ENABLE_FTN_PLL_CALIBRATION +static void handle_ftn_pll_calibration(void); + +#endif /* ENABLE_FTN_PLL_CALIBRATION */ + +/* === IMPLEMENTATION ====================================================== */ +/* TODO: Include other files here if needed. */ +/* + * \brief TAL task handling + * + * This function + * - Checks and allocates the receive buffer. + * - Processes the TAL incoming frame queue. + * - Implements the TAL state machine. + */ +void PHY_TaskHandler(void) +{ + /* Check if the receiver needs to be switched on. */ + if (phy_info.tal_rx_on_required && ((phy_info.tal_state == PHY_IDLE) || (phy_info.tal_state == PHY_TX_DONE))) + { + /* Check if a receive buffer has not been available before. */ + if (tal_rx_buffer == NULL) { + tal_rx_buffer = bmm_buffer_alloc(LARGE_BUFFER_SIZE); + } + + /* Check if buffer could be allocated */ + if (NULL != tal_rx_buffer) { + /* + * Note: + * This flag needs to be reset BEFORE the received is + * switched on. + */ + phy_info.tal_rx_on_required = false; + +#ifdef PROMISCUOUS_MODE + if (tal_pib.PromiscuousMode) { + do + { + (void)set_trx_state(CMD_RX_ON); + }while (tal_get_trx_status() != RX_ON); + + } else { + do + { + (void)set_trx_state(CMD_RX_AACK_ON); + }while (tal_get_trx_status() != RX_AACK_ON); + } + +#else /* Normal operation */ + + do + { + (void)set_trx_state(CMD_RX_AACK_ON); + }while (tal_get_trx_status() != RX_AACK_ON); +#endif + } + else { + + /* no free buffer is available; try next time again */ + } + } + /* + * If the transceiver has received a frame and it has been placed + * into the queue of the TAL, the frame needs to be processed further. + */ + if (tal_incoming_frame_queue.size > 0U) { + buffer_t *rx_frame; + + /* Check if there are any pending data in the + * incoming_frame_queue. */ + rx_frame = qmm_queue_remove(&tal_incoming_frame_queue, NULL); + if (NULL != rx_frame) { + process_incoming_frame(rx_frame); + } + } + + /* Handle the TAL state machines */ + switch (phy_info.tal_state) { + + case PHY_TX_AUTO: + (void)trx_reg_read(RG_IRQ_STATUS); + PHY_TxDoneCallback(PHY_FAILURE, mac_frame_ptr); + break; + + case PHY_IDLE: + + break; + /* Do nothing, but fall through... */ + + + case PHY_TX_DONE: + tx_done_handling(); /* see tal_tx.c */ + break; + + + case PHY_ED_DONE: + ed_scan_done(); + break; + + + default: + /* Nothing to do */ + break; + } +} /* PHY_TaskHandler() */ + +/* \brief TAL Task handling + * + * \This function handles the transceiver interrupt + * + */ + + void TAL_TaskHandler(void) + { + if (phy_info.tal_state == PHY_TX_AUTO) + { + SYS_TIME_TimerDestroy(trxEIC_waitTimer); + } + trx_irq_handler_cb(); + } + + +/* + * \brief Sets transceiver state + * + * \param trx_cmd needs to be one of the trx commands + * + * \return current trx state + */ +tal_trx_status_t set_trx_state(trx_cmd_t trx_cmd) +{ + + if (phy_info.tal_trx_status == TRX_SLEEP) { + /* + * Since the wake-up procedure relies on the Awake IRQ and + * the global interrupts may be disabled at this point of time, + * we need to make sure that the global interrupts are enabled + * during wake-up procedure. + * Once the TRX is awake, the original state of the global + * interrupts + * will be restored. + */ + /* Reset wake-up interrupt flag. */ + if (CMD_SLEEP == trx_cmd) { + return TRX_SLEEP; + } + + phy_info.tal_awake_end_flag = false; + + /* Set callback function for the awake interrupt. */ + tal_trx_wakeup(); + +#if (ANTENNA_DIVERSITY == 1) + /* Enable antenna diversity. */ + trx_reg_bit_write(SR_ANT_EXT_SW_EN, ANT_EXT_SW_ENABLE); +#endif + +#ifdef EXT_RF_FRONT_END_CTRL + /* Enable RF front end control */ + trx_reg_bit_write(SR_PA_EXT_EN, PA_EXT_ENABLE); +#endif + + phy_info.tal_trx_status = TRX_OFF; + + if ((trx_cmd == CMD_TRX_OFF) || + (trx_cmd == CMD_FORCE_TRX_OFF)) { + return TRX_OFF; + } + } + +#ifdef ENABLE_DEEP_SLEEP + else if (phy_info.tal_trx_status == TRX_DEEP_SLEEP) { + if (CMD_DEEP_SLEEP == trx_cmd) { + return TRX_DEEP_SLEEP; + } + + tal_trx_wakeup(); + + /* Check if trx has left deep sleep. */ + tal_trx_status_t trx_state; + do { + trx_state = trx_reg_read( + RG_TRX_STATUS); + } while (trx_state != TRX_OFF); + + phy_info.tal_trx_status = TRX_OFF; + + /* Using deep sleep, the transceiver's registers need to be + * restored. */ + trx_config(); + + /* + * Write all PIB values to the transceiver + * that are needed by the transceiver itself. + */ + write_all_tal_pib_to_trx(); /* implementation can be found in + *'tal_pib.c' */ + if ((trx_cmd == CMD_TRX_OFF) || + (trx_cmd == CMD_FORCE_TRX_OFF)) { + return TRX_OFF; + } + } +#endif + + switch (trx_cmd) { /* requested state */ + case CMD_SLEEP: +#ifdef ENABLE_DEEP_SLEEP + /* Fall through. */ + case CMD_DEEP_SLEEP: +#endif + + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_FORCE_TRX_OFF); +#if (ANTENNA_DIVERSITY == 1) + + /* + * Disable antenna diversity: to reduce the power consumption + * or + * avoid leakage current of an external RF switch during SLEEP. + */ + trx_reg_bit_write(SR_ANT_EXT_SW_EN, ANT_EXT_SW_DISABLE); +#endif +#ifdef EXT_RF_FRONT_END_CTRL + /* Disable RF front end control */ + trx_reg_bit_write(SR_PA_EXT_EN, PA_EXT_DISABLE); +#endif + /* Clear existing interrupts */ + (void)trx_reg_read(RG_IRQ_STATUS); + +#ifdef ENABLE_DEEP_SLEEP + if (trx_cmd == CMD_DEEP_SLEEP) { + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_PREP_DEEP_SLEEP); + phy_info.tal_trx_status = TRX_DEEP_SLEEP; + } else { + /* + * Enable Awake_end interrupt. + * This is used for save wake-up from sleep later. + */ + trx_reg_write(RG_IRQ_MASK, (uint8_t)TRX_IRQ_4_CCA_ED_DONE); + phy_info.tal_trx_status = TRX_SLEEP; + } + +#else + + /* + * Enable Awake_end interrupt. + * This is used for save wake-up from sleep later. + */ + trx_reg_write(RG_IRQ_MASK, (uint8_t)TRX_IRQ_4_CCA_ED_DONE); + phy_info.tal_trx_status = TRX_SLEEP; +#endif + + trx_delay_micros(1); + TRX_SLP_TR_HIGH(); + trx_delay_micros(TRX_OFF_TO_SLEEP_TIME_CLKM_CYCLES); + return phy_info.tal_trx_status; + break; + + + case CMD_TRX_OFF: + switch (phy_info.tal_trx_status) { + case TRX_OFF: + break; + + default: + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_TRX_OFF); + trx_delay_micros(1); + break; + } + break; + + case CMD_FORCE_TRX_OFF: + switch (phy_info.tal_trx_status) { + case TRX_OFF: + break; + + default: + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_FORCE_TRX_OFF); + trx_delay_micros(1); + break; + } + break; + + case CMD_PLL_ON: + switch (phy_info.tal_trx_status) { + + case PLL_ON: + break; + + case TRX_OFF: + + switch_pll_on(); + break; + + case RX_ON: + case RX_AACK_ON: + case TX_ARET_ON: + trx_reg_write(RG_TRX_STATE, (uint8_t)TRX_OFF); + trx_delay_micros(1); + switch_pll_on(); + break; + + case BUSY_RX: + case BUSY_TX: + case BUSY_RX_AACK: + case BUSY_TX_ARET: + /* do nothing if trx is busy */ + break; + + default: + /* Nothing to do */ + break; + } + break; + + case CMD_FORCE_PLL_ON: + switch (phy_info.tal_trx_status) { + case TRX_OFF: + switch_pll_on(); + break; + + case PLL_ON: + break; + + default: + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_FORCE_PLL_ON); + break; + } + break; + + case CMD_RX_ON: + switch (phy_info.tal_trx_status) { + case RX_ON: + break; + case PLL_ON: + case RX_AACK_ON: + case TX_ARET_ON: + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_TRX_OFF); + //switch_pll_on(); + //trx_delay_micros(TRX_OFF_TO_PLL_ON_TIME_US); + do{ + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_RX_ON); + }while((((uint8_t)tal_get_trx_status())& 0x1fU) != ((uint8_t)RX_ON)); + break; + + case TRX_OFF: + //switch_pll_on(); + //trx_delay_micros(TRX_OFF_TO_PLL_ON_TIME_US); + do{ + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_RX_ON); + }while((((uint8_t)tal_get_trx_status())& 0x1fU) != ((uint8_t)RX_ON)); + + break; + + case BUSY_RX: + case BUSY_TX: + case BUSY_RX_AACK: + case BUSY_TX_ARET: + /* do nothing if trx is busy */ + break; + + default: + /* Nothing to do */ + break; + } + break; + + case CMD_RX_AACK_ON: + switch (phy_info.tal_trx_status) { + case RX_AACK_ON: + break; + case TX_ARET_ON: + case PLL_ON: + case RX_ON: + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_TRX_OFF); + //switch_pll_on(); + do{ + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_RX_AACK_ON); + }while((((uint8_t)tal_get_trx_status())& 0x1fU) != ((uint8_t)RX_AACK_ON)); + + break; + + case TRX_OFF: + //switch_pll_on(); /* state change from TRX_OFF to + // * RX_AACK_ON can be done directly, too + // **/ + //trx_delay_micros(TRX_OFF_TO_PLL_ON_TIME_US); + do{ + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_RX_AACK_ON); + }while((((uint8_t)tal_get_trx_status())& 0x1fU) != ((uint8_t)RX_AACK_ON)); + + break; + + case BUSY_RX: + case BUSY_RX_AACK: + case BUSY_TX: + case BUSY_TX_ARET: + /* do nothing if trx is busy */ + break; + + default: + /* Nothing to do */ + break; + } + break; + + case CMD_TX_ARET_ON: + switch (phy_info.tal_trx_status) { + case TX_ARET_ON: + break; + + case PLL_ON: + case RX_ON: + case RX_AACK_ON: + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_TRX_OFF); + //switch_pll_on(); + //trx_delay_micros(TRX_OFF_TO_PLL_ON_TIME_US); + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_TX_ARET_ON); + + break; + + case TRX_OFF: + //switch_pll_on(); /* state change from TRX_OFF to + // * TX_ARET_ON can be done directly, too + // **/ + //trx_delay_micros(TRX_OFF_TO_PLL_ON_TIME_US); + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_TX_ARET_ON); + break; + + case BUSY_RX: + case BUSY_TX: + case BUSY_RX_AACK: + case BUSY_TX_ARET: + /* do nothing if trx is busy */ + break; + + default: + /* Nothing to do */ + break; + } + break; + + default: + /* Nothing to do */ + break; + } + uint8_t count = 0; + + do { + count++; + uint8_t temp = (0x1FU) & (trx_reg_read(RG_TRX_STATUS)); + phy_info.tal_trx_status = (tal_trx_status_t)temp; + if (count == 100) + { + break; + } + } while (phy_info.tal_trx_status == STATE_TRANSITION_IN_PROGRESS); + + return phy_info.tal_trx_status; +} /* set_trx_state() */ + +/** + * \brief Switches the PLL on + * \ingroup group_tal_state_machine + */ +static void switch_pll_on(void) +{ + + uint32_t start_time; + uint32_t current_time; + + /* Check if trx is in TRX_OFF; only from PLL_ON the following procedure + * is applicable */ + if (trx_reg_bit_read(SR_TRX_STATUS) != (uint8_t)TRX_OFF) { + + return; + } + + /* Clear all pending trx interrupts */ + (void)trx_reg_read(RG_IRQ_STATUS); + /* Get current IRQ mask */ + uint8_t trx_irq_mask = trx_reg_read(RG_IRQ_MASK); + /* Enable transceiver's PLL lock interrupt */ + trx_reg_write(RG_IRQ_MASK, (uint8_t)TRX_IRQ_0_PLL_LOCK); + /* Disable trx interrupt handling */ + EIC_InterruptDisable(EIC_PIN_${SELECTED_EIC_CHANNEL}); + + /* Switch PLL on */ + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_PLL_ON); + start_time = PAL_GetCurrentTime(); + + /* Wait for transceiver interrupt: check for IRQ line */ + while ((bool)IRQ_Get() == false) { + /* Handle errata "potential long PLL settling duration". */ + current_time = PAL_GetCurrentTime(); + if (pal_sub_time_us(current_time, + start_time) > PLL_LOCK_DURATION_MAX_US) { + uint8_t reg_value; + + reg_value = trx_reg_read(RG_PLL_CF); + if ((bool)(reg_value & (0x01U))) { + reg_value &= 0xFEU; + } else { + reg_value |= 0x01U; + } + + trx_reg_write(RG_PLL_CF, reg_value); + start_time = PAL_GetCurrentTime(); + } + + /* Wait until trx line has been raised. */ + } + + /* Clear PLL lock interrupt at trx */ + (void)trx_reg_read(RG_IRQ_STATUS); + /* Clear MCU's interrupt flag */ + EIC_REGS->EIC_INTFLAG = (1UL << EIC_PIN_${SELECTED_EIC_CHANNEL}); + /* Enable trx interrupt handling again */ + EIC_InterruptEnable(EIC_PIN_${SELECTED_EIC_CHANNEL}); + /* Restore transceiver's interrupt mask. */ + trx_reg_write(RG_IRQ_MASK, trx_irq_mask); +} + + +PHY_TrxStatus_t PHY_GetTrxStatus(void) +{ + tal_trx_status_t trx_status = tal_get_trx_status(); + PHY_TrxStatus_t trx_state; + + switch(trx_status) + { + case TRX_OFF: + case P_ON: + case PLL_ON: + trx_state = PHY_TRX_OFF; + break; + + case RX_ON: + case RX_AACK_ON: + trx_state = PHY_RX_ON; + break; + + case TX_ARET_ON: + trx_state = PHY_TX_ON; + break; + + case BUSY_RX: + case BUSY_RX_AACK: + trx_state = PHY_BUSY_RX; + break; + + case BUSY_TX: + case BUSY_TX_ARET: + trx_state = PHY_BUSY_TX; + break; + + case TRX_SLEEP: + trx_state = PHY_TRX_SLEEP; + break; + + case PREP_DEEP_SLEEP: + trx_state = PHY_TRX_DEEP_SLEEP; + break; + + default: + trx_state = PHY_TRX_OFF; + break; + } + + return trx_state; +} + + +uint32_t PHY_GetSWVersion(void) +{ + uint32_t phyVersion; + + phyVersion = phy_info.phyVersion; + + return phyVersion; +} + + +/** + * @brief Conversion of symbols to microseconds + */ +uint32_t tal_convert_symbols_to_us_def(uint32_t symbols) +{ + return (PHY_CONVERT_SYMBOLS_TO_US(symbols)); +} + +/** + * @brief Conversion of microseconds to symbols + */ +uint32_t tal_convert_us_to_symbols_def(uint32_t time_) +{ + return (PHY_CONVERT_US_TO_SYMBOLS(time_)); +} + +void trx_delay_loop(void *hw, uint32_t cycles) +{ + (void) hw; + (void) cycles; + + /* + * SUBS instruction - 1 cycle + * BHI instruction - 2 cycles if taken; 1 if not taken + * + * In most case: 3 cycles is the loop time + */ + + __asm__( + ".syntax unified\n" + "__dly:\n" + "subs r1, r1, #1\n" + "bhi __dly\n" + ".syntax divided" + ); +} + +void trx_delay_millis(uint32_t ms) +{ + uint32_t cycles = ((uint32_t)PAL_CPU_CLOCK_FREQUENCY / 1000UL) * ms; + cycles /= 3UL; + trx_delay_loop(NULL, cycles); +} + +void trx_delay_micros(uint32_t us) +{ + uint32_t cycles = ((uint32_t)PAL_CPU_CLOCK_FREQUENCY / 1000000UL) * us; + cycles /= 3UL; + trx_delay_loop(NULL, cycles); +} + + +/* EOF */ diff --git a/driver/templates/RF233/phy_init.c.ftl b/driver/templates/RF233/phy_init.c.ftl new file mode 100644 index 0000000..82b10aa --- /dev/null +++ b/driver/templates/RF233/phy_init.c.ftl @@ -0,0 +1,705 @@ +<#-- +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +--> + + + + +/* === INCLUDES ============================================================ */ + +#include +#include +#include +#include +#include +#include + +#include "../../../phy/inc/phy.h" +#include "../../../resources/buffer/inc/bmm.h" +#include "../../../resources/queue/inc/qmm.h" + +#include "../../../phy/inc/ieee_phy_const.h" +#include "../../at86rf/inc/phy_pib.h" +#include "../../at86rf/inc/phy_irq_handler.h" +#include "../../at86rf/inc/phy_tx.h" +#include "../../at86rf/inc/phy_rx.h" + + +#include "../../../pal/inc/pal.h" + +#include "../../at86rf/inc/phy_internal.h" +#include "../../../phy/inc/phy_constants.h" +#include "../../at86rf/inc/at86rf.h" +#include "../../../phy/at86rf/inc/phy_trx_reg_access.h" + + + + + + +/** + * \addtogroup group_tal_init_233 + * @{ + */ + +/* === MACROS ============================================================== */ + +/* Value in us used for delay between poll attempts for transceiver access. */ +#define TRX_POLL_WAIT_TIME_US (100U) + +/* Ratio between max time of TR1 / transceiver poll delay */ +#define P_ON_TO_CLKM_ATTEMPTS ((uint8_t) \ + (P_ON_TO_CLKM_AVAILABLE_MAX_US / TRX_POLL_WAIT_TIME_US)) + +/* Ratio between max time of TR2 / transceiver poll delay */ +#define SLEEP_TO_TRX_OFF_ATTEMPTS ((uint8_t) \ + (SLEEP_TO_TRX_OFF_MAX_US / TRX_POLL_WAIT_TIME_US)) + +/* Ratio between max time of TR15 / transceiver poll delay */ +#define P_ON_TO_TRX_OFF_ATTEMPTS ((uint8_t) \ + (PON_TO_TRXOFF_AFTER_CLKM_MAX_US / \ + TRX_POLL_WAIT_TIME_US)) + +#define VECTOR_TABLE_SIZE 128 + +/* === GLOBALS ============================================================= */ + + + +TimerId_t TAL_RETRY_TIMER; + +/* === PROTOTYPES ========================================================== */ + +static PHY_Retval_t trx_init(void); +static PHY_Retval_t trx_reset(void); +static PHY_Retval_t internal_tal_reset(bool set_default_pib); + +/** + * \brief Initializes all timers used by the TAL module by assigning id's to + * each of them + */ +static PHY_Retval_t tal_timer_init(void); + +/** + * \brief Stops all initialized TAL timers + */ +static void tal_timers_stop(void); + + + +/* ! @} */ + +/* === IMPLEMENTATION ====================================================== */ + +/* + * \brief Initializes the TAL + * + * This function is called to initialize the TAL. The transceiver is + * initialized, the TAL PIBs are set to their default values, and the TAL state + * machine is set to TAL_IDLE state. + * + * \return PHY_SUCCESS if the transceiver state is changed to TRX_OFF and the + * current device part number and version number are correct; + * PHY_FAILURE otherwise + */ +PHY_Retval_t PHY_Init(void) +{ + + /* Init the PAL and by this means also the transceiver interface */ + if (PAL_Init() != PAL_SUCCESS) { + return PHY_FAILURE; + } + + if (trx_init() != PHY_SUCCESS) { + return PHY_FAILURE; + } + + + if (tal_timer_init() != PHY_SUCCESS) { + return PHY_FAILURE; + } + + /* + * Do the reset stuff. + * Set the default PIBs. + * Generate random seed. + */ + if (internal_tal_reset(true) != PHY_SUCCESS) { + return PHY_FAILURE; + } + +#ifndef DISABLE_IEEE_ADDR_CHECK + /* Check if a valid IEEE address is available. */ + + /* + * This while loop is on purpose, since just in the + * rare case that such an address is randomly + * generated again, we must repeat this. + */ + uint64_t invalid_ieee_address; + (void)memset((uint8_t *)&invalid_ieee_address, 0xFF, + sizeof(invalid_ieee_address)); + while ((tal_pib.IeeeAddress == 0x0000000000000000U) || + (tal_pib.IeeeAddress == invalid_ieee_address)) { + /* + * In case no valid IEEE address is available, a random + * IEEE address will be generated to be able to run the + * applications for demonstration purposes. + * In production code this can be omitted. + */ + + /* + * The proper seed for function rand() has already been + * generated + * in function tal_generate_rand_seed(). + */ + uint8_t *ptr_pib = (uint8_t *)&(tal_pib.IeeeAddress); + + for (uint8_t iter = 0; iter < 8U; iter++) { + *ptr_pib++ = (uint8_t)rand(); + + /* + * Note: + * Even if casting the 16 bit rand value back to 8 bit, + * and running the loop 8 timers (instead of only 4 + * times) + * may look cumbersome, it turns out that the code gets + * smaller using 8-bit here. + * And timing is not an issue at this place... + */ + } + } +#endif /* #ifndef DISABLE_IEEE_ADDR_CHECK */ + /* + * Configure interrupt handling. + * Install a handler for the transceiver interrupt. + */ + EIC_CallbackRegister(EIC_PIN_${SELECTED_EIC_CHANNEL}, EIC_interrupt_cb, 0); + + pal_trx_irq_en(); /* Enable transceiver main interrupt. */ + + + + /* Initialize the buffer management module and get a buffer to store + * received frames. */ + bmm_buffer_init(); + tal_rx_buffer = bmm_buffer_alloc(LARGE_BUFFER_SIZE); + + if (tal_rx_buffer == NULL) { + return PHY_FAILURE; + } + + + /* Init incoming frame queue */ +#ifdef ENABLE_QUEUE_CAPACITY + qmm_queue_init(&tal_incoming_frame_queue, + PHY_INCOMING_FRAME_QUEUE_CAPACITY); +#else + qmm_queue_init(&tal_incoming_frame_queue); +#endif /* ENABLE_QUEUE_CAPACITY */ + + phy_info.phyVersion = PHY_VERSION_VALUE; + + return PHY_SUCCESS; +} /* tal_init() */ + +/** + * \brief Initializes the transceiver + * + * This function is called to initialize the transceiver. + * + * \return PHY_SUCCESS if the transceiver state is changed to TRX_OFF and the + * current device part number and version number are correct; + * PHY_FAILURE otherwise + */ +static PHY_Retval_t trx_init(void) +{ + tal_trx_status_t trx_status; + uint8_t poll_counter = 0; + + /*Ensure control lines have correct levels*/ + TRX_SEL_HIGH(); + TRX_RST_HIGH(); + TRX_SLP_TR_LOW(); + + /* Wait typical time of timer TR1. */ + trx_delay_micros(P_ON_TO_CLKM_AVAILABLE_TYP_US); + + + /* Apply reset pulse */ + TRX_RST_LOW(); + trx_delay_micros(RST_PULSE_WIDTH_US); + TRX_RST_HIGH(); + +#if !(defined FPGA_EMULATION) + do { + /* Wait not more than max. value of TR1. */ + if (poll_counter == P_ON_TO_CLKM_ATTEMPTS) { + return PHY_FAILURE; + } + /* Wait a short time interval. */ + trx_delay_micros(TRX_POLL_WAIT_TIME_US); + poll_counter++; + + /* Check if AT86RF233 is connected; omit manufacturer id check + **/ + } while (trx_reg_read(RG_PART_NUM) != PART_NUM_AT86RF233); +#endif /* !defined FPGA_EMULATION */ + + /* Verify that TRX_OFF can be written */ + + trx_reg_write(RG_TRX_STATE, (uint8_t)CMD_TRX_OFF); + + /* Verify that the trx has reached TRX_OFF. */ + poll_counter = 0; + do { + /* Wait a short time interval. */ + trx_delay_micros(TRX_POLL_WAIT_TIME_US); + trx_status = trx_reg_bit_read(SR_TRX_STATUS); + + /* Wait not more than max. value of TR15. */ + if (poll_counter == P_ON_TO_TRX_OFF_ATTEMPTS) { + + return PHY_FAILURE; + } + + poll_counter++; + } while (trx_status != TRX_OFF); + + phy_info.tal_trx_status = TRX_OFF; + + + return PHY_SUCCESS; +} + +/** + * \brief Internal TAL reset function + * + * \param set_default_pib Defines whether PIB values need to be set + * to its default values + * + * \return PHY_SUCCESS if the transceiver state is changed to TRX_OFF and the + * current device part number and version number are correct; + * PHY_PHY_FAILURE otherwise + */ +static PHY_Retval_t internal_tal_reset(bool set_default_pib) +{ + if (trx_reset() != PHY_SUCCESS) { + return PHY_FAILURE; + } + + /* + * Generate a seed for the random number generator in function rand(). + * This is required (for example) as seed for the CSMA-CA algorithm. + */ + tal_generate_rand_seed(); + + + /* Configure the transceiver register values. */ + trx_config(); + + if (set_default_pib) { + /* Set the default PIB values */ + init_tal_pib(); /* implementation can be found in 'tal_pib.c' */ + } else { + /* nothing to do - the current TAL PIB attribute values are used + **/ + } + + /* + * Write all PIB values to the transceiver + * that are needed by the transceiver itself. + */ + write_all_tal_pib_to_trx(); /* implementation can be found in + *'tal_pib.c' */ + + /* Reset TAL variables. */ + phy_info.tal_state = PHY_IDLE; + + + + + + phy_info.tal_rx_on_required = false; + + return PHY_SUCCESS; +} + +/** + * \brief Configures the transceiver + * + * This function is called to configure the transceiver after reset. + */ +void trx_config(void) +{ + + + + /* Set pin driver strength */ + + trx_reg_bit_write(SR_CLKM_SHA_SEL, CLKM_SHA_DISABLE); + trx_reg_bit_write(SR_CLKM_CTRL,CLKM_1MHZ); + + /* + * After we have initialized a proper seed for rand(), + * the transceiver's CSMA seed can be initialized. + * It needs to be assured that a seed for function rand() + * had been generated before. + */ + + /* + * Init the SEED value of the CSMA backoff algorithm. + */ + uint16_t rand_value = (uint16_t)rand(); + trx_reg_write(RG_CSMA_SEED_0, (uint8_t)rand_value); + trx_reg_bit_write(SR_CSMA_SEED_1, (uint8_t)(rand_value >> 8)); + + + /* + * Since the TAL is supporting 802.15.4-2006, + * frames with version number 0 (compatible to 802.15.4-2003) and + * with version number 1 (compatible to 802.15.4-2006) are acknowledged. + */ + + + + trx_reg_bit_write(SR_AACK_FVN_MODE, FRAME_VERSION_01); + trx_reg_bit_write(SR_AACK_SET_PD, SET_PD); /* ACKs for data requests, + * indicate pending data */ + trx_reg_bit_write(SR_RX_SAFE_MODE, RX_SAFE_MODE_ENABLE); /* Enable + * buffer + * protection + * mode */ + trx_reg_write(RG_IRQ_MASK, (uint8_t)TRX_IRQ_DEFAULT); /* The TRX_END + * interrupt of the + * transceiver is + * enabled. */ + trx_reg_write(RG_TRX_RPC, 0xFF); /* RPC feature configuration. */ + + + +#if (ANTENNA_DIVERSITY == 1) + /* Use antenna diversity */ + trx_reg_bit_write(SR_ANT_CTRL, ANTENNA_DEFAULT); + trx_reg_bit_write(SR_PDT_THRES, THRES_ANT_DIV_ENABLE); + trx_reg_bit_write(SR_ANT_DIV_EN, ANT_DIV_ENABLE); + trx_reg_bit_write(SR_ANT_EXT_SW_EN, ANT_EXT_SW_ENABLE); +#endif /* ANTENNA_DIVERSITY */ + + +#ifdef CCA_ED_THRESHOLD + + /* + * Set CCA ED Threshold to other value than standard register due to + * board specific loss (see pal_config.h). */ + trx_reg_bit_write(SR_CCA_ED_THRES, CCA_ED_THRESHOLD); +#endif + +#ifdef EXT_RF_FRONT_END_CTRL + /* Enable RF front end control */ + trx_reg_bit_write(SR_PA_EXT_EN, PA_EXT_ENABLE); +#endif +} + +/** + * \brief Reset transceiver + * + * \return PHY_SUCCESS if the transceiver state is changed to TRX_OFF + * PHY_FAILURE otherwise + */ +static PHY_Retval_t trx_reset(void) +{ + tal_trx_status_t trx_status; + uint8_t poll_counter = 0; + /* trx might sleep, so wake it up */ + TRX_SLP_TR_LOW(); + trx_delay_micros(SLEEP_TO_TRX_OFF_TYP_US); + /* Apply reset pulse */ + TRX_RST_LOW(); + trx_delay_micros(RST_PULSE_WIDTH_US); + TRX_RST_HIGH(); + + /* verify that trx has reached TRX_OFF */ + do { + /* Wait a short time interval. */ + trx_delay_micros(TRX_POLL_WAIT_TIME_US); + + trx_status = (tal_trx_status_t)trx_reg_bit_read(SR_TRX_STATUS); + + /* Wait not more than max. value of TR2. */ + if (poll_counter == SLEEP_TO_TRX_OFF_ATTEMPTS) { + + return PHY_FAILURE; + } + + poll_counter++; + } while (trx_status != TRX_OFF); + + phy_info.tal_trx_status = TRX_OFF; + + + return PHY_SUCCESS; +} + +/* + * \brief Resets TAL state machine and sets the default PIB values if requested + * + * \param set_default_pib Defines whether PIB values need to be set + * to its default values + * + * \return PHY_SUCCESS if the transceiver state is changed to TRX_OFF + * PHY_FAILURE otherwise + */ +PHY_Retval_t PHY_Reset(bool set_default_pib) +{ + /* + * Do the reset stuff. + * Set the default PIBs depending on the given parameter + * set_default_pib. + * Do NOT generate random seed again. + */ + if (internal_tal_reset(set_default_pib) != PHY_SUCCESS) { + return PHY_FAILURE; + } + + ENTER_CRITICAL_REGION(); + tal_timers_stop(); + LEAVE_CRITICAL_REGION(); + + /* Clear TAL Incoming Frame queue and free used buffers. */ + while (tal_incoming_frame_queue.size > 0U) { + buffer_t *frame = qmm_queue_remove(&tal_incoming_frame_queue, + NULL); + if (NULL != frame) { + bmm_buffer_free(frame); + } + } + /* + * Configure interrupt handling. + * Install a handler for the transceiver interrupt. + */ + EIC_CallbackRegister(EIC_PIN_${SELECTED_EIC_CHANNEL}, EIC_interrupt_cb, 0); + /* The pending transceiver interrupts on the microcontroller are + * cleared. */ + pal_trx_irq_en(); /* Enable transceiver main interrupt. */ + +#ifdef ENABLE_FTN_PLL_CALIBRATION + { + /* Handle PLL calibration and filter tuning. */ + retval_t timer_status; + + /* Calibration timer has already been stopped within this + * function. */ + + /* Start periodic calibration timer. */ + timer_status = pal_timer_start(TAL_CALIBRATION, + TAL_CALIBRATION_TIMEOUT_US, + TIMEOUT_RELATIVE, + (FUNC_PTR)calibration_timer_handler_cb, + NULL); + + if (timer_status != MAC_SUCCESS) { + ASSERT("PLL calibration timer start problem" == 0); + } + } +#endif /* ENABLE_FTN_PLL_CALIBRATION */ + + return PHY_SUCCESS; +} + +/* + * \brief Generates a 16-bit random number used as initial seed for srand() + * + * This function generates a 16-bit random number by means of using the + * Random Number Generator from the transceiver. + * The Random Number Generator generates 2-bit random values. These 2-bit + * random values are concatenated to the required 16-bit random seed. + * + * The generated random 16-bit number is feed into function srand() + * as initial seed. + * + * The transceiver state is initally set to RX_ON. + * After the completion of the random seed generation, the + * trancseiver is set to TRX_OFF. + * + * As a prerequisite the preamble detector must not be disabled. + * + * Also in case the function is called from a different state than TRX_OFF, + * additional trx state handling is required, such as reading the original + * value and restoring this state after finishing the sequence. + * Since in our case the function is called from TRX_OFF, this is not required + * here. + */ + +void tal_generate_rand_seed(void) +{ + uint16_t seed = 0; + uint8_t cur_random_val = 0; + + /* RPC could influence the randomness; therefore disable it here. */ + uint8_t previous_RPC_value = trx_reg_read(RG_TRX_RPC); + trx_reg_write(RG_TRX_RPC, 0xC1); + + /* + * We need to disable TRX IRQs while generating random values in RX_ON, + * we do not want to receive frames at this point of time at all. + */ + EIC_InterruptDisable(EIC_PIN_${SELECTED_EIC_CHANNEL}); + + /* Ensure that PLL has locked and receive mode is reached. */ + tal_trx_status_t trx_state; + do { + trx_state = set_trx_state(CMD_RX_ON); + } while (trx_state != RX_ON); + + /* Ensure that register bit RX_PDT_DIS is set to 0. */ + trx_reg_bit_write(SR_RX_PDT_DIS, RX_ENABLE); + + /* + * The 16-bit random value is generated from various 2-bit random + * values. + */ + for (uint8_t i = 0; i < 8; i++) { + /* Now we can safely read the 2-bit random number. */ + cur_random_val = trx_reg_bit_read(SR_RND_VALUE); + seed = seed << 2; + seed |= cur_random_val; + trx_delay_micros(1); /* wait that the random value gets updated */ + } + + (void)set_trx_state(CMD_FORCE_TRX_OFF); + + /* + * Now we need to clear potential pending TRX IRQs and + * enable the TRX IRQs again. + */ + (void)trx_reg_read(RG_IRQ_STATUS); + EIC_REGS->EIC_INTFLAG = (1UL << EIC_PIN_${SELECTED_EIC_CHANNEL}); + EIC_InterruptEnable(EIC_PIN_${SELECTED_EIC_CHANNEL}); + + /* Set the seed for the random number generator. */ + srand(seed); + + /* Restore RPC settings. */ + trx_reg_write(RG_TRX_RPC, previous_RPC_value); +} + +static PHY_Retval_t tal_timer_init(void) +{ + /* Timer used for Retransmission caused by Arbiter Abort failure*/ + if (PAL_SUCCESS != PAL_TimerGetId(&TAL_RETRY_TIMER)) { + return PHY_FAILURE; + } +#ifdef BEACON_SUPPORT + /* Beacon Support */ +#ifdef ENABLE_FTN_PLL_CALIBRATION + if (PHY_SUCCESS != PAL_TimerGetId(&TAL_CSMA_CCA)) { + return PHY_FAILURE; + } + + if (PHY_SUCCESS != PAL_TimerGetId(&TAL_CSMA_BEACON_LOSS_TIMER)) { + return PHY_FAILURE; + } + + if (PHY_SUCCESS != PAL_TimerGetId(&TAL_CALIBRATION)) { + return PHY_FAILURE; + } + +#ifdef SW_CONTROLLED_CSMA + if (PHY_SUCCESS != PAL_TimerGetId(&TAL_T_BOFF)) { + return PHY_FAILURE; + } +#endif + +#else + if (PHY_SUCCESS != PAL_TimerGetId(&TAL_CSMA_CCA)) { + return PHY_FAILURE; + } + + if (PHY_SUCCESS != PAL_TimerGetId(&TAL_CSMA_BEACON_LOSS_TIMER)) { + return PHY_FAILURE; + } + +#ifdef SW_CONTROLLED_CSMA + if (PHY_SUCCESS != PAL_TimerGetId(&TAL_T_BOFF)) { + return PHY_FAILURE; + } +#endif +#endif /* ENABLE_FTN_PLL_CALIBRATION */ +#else /* No BEACON_SUPPORT */ +#ifdef ENABLE_FTN_PLL_CALIBRATION + if (PHY_SUCCESS != PAL_TimerGetId(&TAL_CALIBRATION)) { + return PHY_FAILURE; + } + +#ifdef SW_CONTROLLED_CSMA + if (PHY_SUCCESS != PAL_TimerGetId(&TAL_T_BOFF)) { + return PHY_FAILURE; + } +#endif + +#else +#ifdef SW_CONTROLLED_CSMA + if (PHY_SUCCESS != PAL_TimerGetId(&TAL_T_BOFF)) { + return PHY_FAILURE; + } +#endif +#endif /* ENABLE_FTN_PLL_CALIBRATION */ +#endif /* BEACON_SUPPORT */ + return PHY_SUCCESS; +} + +static void tal_timers_stop(void) +{ +#if (NUMBER_OF_PHY_TIMERS > 0) + (void)(PAL_TimerStop(TAL_RETRY_TIMER)); +#ifdef ENABLE_FTN_PLL_CALIBRATION + (void)PAL_TimerStop(TAL_CALIBRATION); +#ifdef SW_CONTROLLED_CSMA + (void)PAL_TimerStop(TAL_T_BOFF); +#endif + +#else +#ifdef SW_CONTROLLED_CSMA + (void)PAL_TimerStop(TAL_T_BOFF); +#endif +#endif /* ENABLE_FTN_PLL_CALIBRATION */ +#endif /* (NUMBER_OF_TAL_TIMERS > 0)*/ +} + +void trx_irq_flag_clear(void) +{ + uint8_t trx_irq_cause; + + trx_irq_cause = trx_reg_read(RG_IRQ_STATUS); + + (void)trx_irq_cause; +} + + + + + +/**************************/ +/* EOF */ diff --git a/driver/templates/RF233/phy_trx_reg_access.c.ftl b/driver/templates/RF233/phy_trx_reg_access.c.ftl new file mode 100644 index 0000000..07e0784 --- /dev/null +++ b/driver/templates/RF233/phy_trx_reg_access.c.ftl @@ -0,0 +1,215 @@ +<#-- +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +--> + + +/* === INCLUDES ============================================================ */ +#include "definitions.h" +#include "../../../pal/inc/pal.h" +#include "../../at86rf/inc/phy_trx_reg_access.h" + + +void trx_reg_write(uint8_t addr, uint8_t value) +{ + pal_trx_irq_dis(); + /* Prepare the command byte */ + addr |= WRITE_ACCESS_COMMAND; + + /* Start SPI transaction by pulling SEL low */ + SPI_SS_Clear(); + + /* Send the Read command byte */ + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Write(&addr, 1); + + /* Write the byte in the transceiver data register */ + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Write(&value, 1); + + while (${SELECTED_SERCOM}_IsBusy()){} + + /* Stop the SPI transaction by setting SEL high */ + SPI_SS_Set(); + pal_trx_irq_en(); +} + + +uint8_t trx_reg_read(uint8_t addr) +{ + pal_trx_irq_dis(); + uint16_t register_value; + + /* Prepare the command byte */ + addr |= READ_ACCESS_COMMAND; + + /* Start SPI transaction by pulling SEL low */ + SPI_SS_Clear(); + + /* Send the Read command byte */ + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Write(&addr, 1); + + /* Read the byte from the transceiver data register */ + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Read(®ister_value, 1); + + while(${SELECTED_SERCOM}_IsBusy()){} + + /* Stop the SPI transaction by setting SEL high */ + SPI_SS_Set(); + pal_trx_irq_en(); + + return register_value; +} + + +void trx_reg_bit_write(uint8_t addr, uint8_t mask, uint8_t pos, uint8_t value) +{ + uint8_t reg; + reg = trx_reg_read(addr); + reg = ((reg & ~mask) | (((value) << pos) & mask)); + trx_reg_write(addr, reg); +} + + +uint8_t trx_reg_bit_read(uint8_t addr, uint8_t mask, uint8_t pos) +{ + uint8_t reg; + reg = trx_reg_read(addr); + reg = (reg & mask) >> (pos); + return reg; +} + + + + +void trx_frame_write(uint8_t* buf, uint8_t length) +{ + pal_trx_irq_dis(); + uint8_t temp; + + /* Start SPI transaction by pulling SEL low */ + SPI_SS_Clear(); + temp = TRX_CMD_FW; + + while (${SELECTED_SERCOM}_IsBusy()){} + /* Send the command byte */ + ${SELECTED_SERCOM}_Write(&temp, 1); + while (${SELECTED_SERCOM}_IsBusy()){} + /* Write into the buffer */ + ${SELECTED_SERCOM}_Write(buf, length); + + while (${SELECTED_SERCOM}_IsBusy()){} + + /* Stop the SPI transaction by setting SEL high */ + SPI_SS_Set(); + pal_trx_irq_en(); + +} + + + + +void trx_frame_read(uint8_t* buf, uint8_t length) +{ + pal_trx_irq_dis(); + uint16_t temp; + /* Start SPI transaction by pulling SEL low */ + SPI_SS_Clear(); + + temp = TRX_CMD_FR; + + while (${SELECTED_SERCOM}_IsBusy()){} + /* Send the command byte */ + ${SELECTED_SERCOM}_Write(&temp, 1); + while (${SELECTED_SERCOM}_IsBusy()){} + + ${SELECTED_SERCOM}_Read(buf, length); + + while (${SELECTED_SERCOM}_IsBusy()){} + + /* Stop the SPI transaction by setting SEL high */ + SPI_SS_Set(); + pal_trx_irq_en(); + +} + +void trx_sram_write(uint8_t addr, uint8_t *data, uint8_t length) +{ + pal_trx_irq_dis(); + uint8_t temp; + + /* Start SPI transaction by pulling SEL low */ + SPI_SS_Clear(); + + temp = TRX_CMD_SW; + + /* Send the command byte */ + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Write(&temp, 1); + + /* Send the address from which the write operation should start */ + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Write(&addr, 1); + + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Write(data, length); + + while (${SELECTED_SERCOM}_IsBusy()){} + + /* Stop the SPI transaction by setting SEL high */ + SPI_SS_Set(); + pal_trx_irq_en(); + +} + +void trx_sram_read(uint8_t addr, uint8_t *data, uint8_t length) +{ + pal_trx_irq_dis(); + uint16_t temp; + + /* Start SPI transaction by pulling SEL low */ + SPI_SS_Clear(); + + temp = TRX_CMD_SR; + + /* Send the command byte */ + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Write(&temp, 1); + + /* Send the address from which the read operation should start */ + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Write(&addr, 1); + + /* Upload the received byte in the user provided location */ + while (${SELECTED_SERCOM}_IsBusy()){} + ${SELECTED_SERCOM}_Read(data, length); + + while (${SELECTED_SERCOM}_IsBusy()){} + + /* Stop the SPI transaction by setting SEL high */ + SPI_SS_Set(); + pal_trx_irq_en(); + +} diff --git a/driver/templates/RF233/phy_trx_reg_access.h.ftl b/driver/templates/RF233/phy_trx_reg_access.h.ftl new file mode 100644 index 0000000..79dad21 --- /dev/null +++ b/driver/templates/RF233/phy_trx_reg_access.h.ftl @@ -0,0 +1,110 @@ +<#-- +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +--> + + +#ifndef TRX_REG_ACCESS_H /* Guard against multiple inclusion */ +#define TRX_REG_ACCESS_H + + + +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Section: Included Files */ +/* ************************************************************************** */ +/* ************************************************************************** */ +#include "at86rf.h" +#include "../default/definitions.h" +#include "../../../pal/inc/pal.h" +/* Provide C++ Compatibility */ +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * Write access command of the transceiver + */ +#define WRITE_ACCESS_COMMAND (0xC0U) + +/** + * Read access command to the tranceiver + */ +#define READ_ACCESS_COMMAND (0x80U) + +/** + * Frame write command of transceiver + */ +#define TRX_CMD_FW (0x60U) + +/** + * Frame read command of transceiver + */ +#define TRX_CMD_FR (0x20U) + +/** + * SRAM write command of transceiver + */ +#define TRX_CMD_SW (0x40U) + +/** + * SRAM read command of transceiver + */ +#define TRX_CMD_SR (0x00U) + +#define TRX_TRIG_DELAY() {nop(); nop(); } + +void trx_reg_write(uint8_t addr, uint8_t value); + +uint8_t trx_reg_read(uint8_t addr); + +void trx_reg_bit_write(uint8_t addr, uint8_t mask, uint8_t pos, uint8_t value); + +uint8_t trx_reg_bit_read(uint8_t addr, uint8_t mask, uint8_t pos); + +void trx_frame_write(uint8_t* buf, uint8_t length); + +void trx_frame_read(uint8_t* buf, uint8_t length); + +void trx_sram_write(uint8_t addr, uint8_t *data, uint8_t length); + +void trx_sram_read(uint8_t addr, uint8_t *data, uint8_t length); + + + + /* Provide C++ Compatibility */ +#ifdef __cplusplus +} +#endif + +/* ***************************************************************************** + End of File + */ + + +#endif /* _EXAMPLE_FILE_NAME_H */ + +/* ***************************************************************************** + End of File + */ \ No newline at end of file diff --git a/driver/templates/common/RFPHY_definitions.h.ftl b/driver/templates/common/RFPHY_definitions.h.ftl new file mode 100644 index 0000000..dd24302 --- /dev/null +++ b/driver/templates/common/RFPHY_definitions.h.ftl @@ -0,0 +1,28 @@ +<#-- +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +--> +#include "driver/IEEE_802154_PHY/pal/inc/pal.h" +#include "driver/IEEE_802154_PHY/phy/inc/phy.h" +#include "driver/IEEE_802154_PHY/phy/inc/phy_tasks.h" +#include "framework_defs.h" \ No newline at end of file diff --git a/driver/templates/common/app.h.ftl b/driver/templates/common/app.h.ftl new file mode 100644 index 0000000..196d693 --- /dev/null +++ b/driver/templates/common/app.h.ftl @@ -0,0 +1,219 @@ +<#-- +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +--> +/******************************************************************************* + MPLAB Harmony Application Header File + + Company: + Microchip Technology Inc. + + File Name: + app.h + + Summary: + This header file provides prototypes and definitions for the application. + + Description: + This header file provides function prototypes and data type definitions for + the application. Some of these are required by the system (such as the + "APP_Initialize" and "APP_Tasks" prototypes) and some of them are only used + internally by the application (such as the "APP_STATES" definition). Both + are defined here for convenience. +*******************************************************************************/ + +#ifndef _APP_H +#define _APP_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include +#include +#include +#include +#include "configuration.h" +#include "osal/osal_freertos_extend.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + +extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Type Definitions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Application states + + Summary: + Application states enumeration + + Description: + This enumeration defines the valid application states. These states + determine the behavior of the application at various times. +*/ + +typedef enum +{ + /* Application's state machine's initial state. */ + APP_STATE_INIT=0, + APP_STATE_SERVICE_TASKS, + /* TODO: Define states used by the application state machine. */ + +} APP_STATES; + + +typedef struct APP_Msg_T +{ + uint8_t msgId; + uint8_t msgData[256]; +} APP_Msg_T; + + + +// ***************************************************************************** +/* Application Data + + Summary: + Holds application data + + Description: + This structure holds the application's data. + + Remarks: + Application strings and buffers are be defined outside this structure. + */ + +typedef struct +{ + /* The application's current state */ + APP_STATES state; + + /* TODO: Define any additional data used by the application. */ + OSAL_QUEUE_HANDLE_TYPE appQueue; + +} APP_DATA; +extern APP_DATA appData; + +// ***************************************************************************** +// ***************************************************************************** +// Section: Application Callback Routines +// ***************************************************************************** +// ***************************************************************************** +/* These routines are called by drivers when certain events occur. +*/ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Application Initialization and State Machine Functions +// ***************************************************************************** +// ***************************************************************************** + +/******************************************************************************* + Function: + void APP_Initialize ( void ) + + Summary: + MPLAB Harmony application initialization routine. + + Description: + This function initializes the Harmony application. It places the + application in its initial state and prepares it to run so that its + APP_Tasks function can be called. + + Precondition: + All other system initialization routines should be called before calling + this routine (in "SYS_Initialize"). + + Parameters: + None. + + Returns: + None. + + Example: + + APP_Initialize(); + + + Remarks: + This routine must be called from the SYS_Initialize function. +*/ + +void APP_Initialize ( void ); + + +/******************************************************************************* + Function: + void APP_Tasks ( void ) + + Summary: + MPLAB Harmony Demo application tasks function + + Description: + This routine is the Harmony Demo application's tasks function. It + defines the application's state machine and core logic. + + Precondition: + The system and application initialization ("SYS_Initialize") should be + called before calling this. + + Parameters: + None. + + Returns: + None. + + Example: + + APP_Tasks(); + + + Remarks: + This routine must be called from SYS_Tasks() routine. + */ + +void APP_Tasks( void ); + +//DOM-IGNORE-BEGIN +#ifdef __cplusplus +} +#endif +//DOM-IGNORE-END + +#endif /* _APP_H */ + +/******************************************************************************* + End of File + */ + diff --git a/driver/templates/common/app_config.h.ftl b/driver/templates/common/app_config.h.ftl new file mode 100644 index 0000000..cc50829 --- /dev/null +++ b/driver/templates/common/app_config.h.ftl @@ -0,0 +1,80 @@ +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + + + +/* Prevent double inclusion */ +#ifndef APP_CONFIG_H +#define APP_CONFIG_H + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Macros +// ***************************************************************************** +// ***************************************************************************** + +/** Defines the number of timers used by the application. */ +#define NUMBER_OF_APP_TIMERS (0) + +#define NUMBER_OF_TOTAL_STACK_TIMERS 1 + +#if (!defined TOTAL_NUMBER_OF_TIMERS) + +/** Defines the total number of timers used by the application and the layers + * below. */ +#define TOTAL_NUMBER_OF_TIMERS (NUMBER_OF_APP_TIMERS + \ + NUMBER_OF_TOTAL_STACK_TIMERS) +#endif /* (!define TOTAL_NUMBER_OF_TIMERS) */ + +/** Defines the number of additional large buffers used by the application */ +#define NUMBER_OF_LARGE_APP_BUFS (0) + +/** Defines the number of additional small buffers used by the application */ +#define NUMBER_OF_SMALL_APP_BUFS (0) + +#define NUMBER_OF_LARGE_STACK_BUFS (${PHY_INTEGER_BMMLARGEBUFFERS}U) + +#define NUMBER_OF_SMALL_STACK_BUFS (${PHY_INTEGER_BMMSMALLBUFFERS}U) + +/** + * Defines the total number of large buffers used by the application and the + * layers below. + */ +#define TOTAL_NUMBER_OF_LARGE_BUFS (NUMBER_OF_LARGE_APP_BUFS + \ + NUMBER_OF_LARGE_STACK_BUFS) + +/** + * Defines the total number of small buffers used by the application and the + * layers below. + */ +#define TOTAL_NUMBER_OF_SMALL_BUFS (NUMBER_OF_SMALL_APP_BUFS + \ + NUMBER_OF_SMALL_STACK_BUFS) + +#define TOTAL_NUMBER_OF_BUFS (TOTAL_NUMBER_OF_LARGE_BUFS + \ + TOTAL_NUMBER_OF_SMALL_BUFS) + + +#endif /* APP_CONFIG_H */ +/* EOF */ diff --git a/driver/templates/common/pal.h.ftl b/driver/templates/common/pal.h.ftl new file mode 100644 index 0000000..d3820f3 --- /dev/null +++ b/driver/templates/common/pal.h.ftl @@ -0,0 +1,761 @@ +/******************************************************************************* + PAL Header + + File Name: + pal.h + + Summary: + This file contains Platform Abstraction Layer API function declarations + + Description: + PAL Layer provides the interface to Timers, Interrupts and other platform + related resources. PHY layer is using PAL for its internal operations +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +/* Prevent double inclusion */ +#ifndef PAL_H +#define PAL_H + +/* + * This module acts as a wrapper layer between the Wireless stack and the Harmony + * drivers and peripherals + * All hardware level access to the Harmony drivers from the stack happens through + * this module + */ +// ***************************************************************************** +// ***************************************************************************** +// Section: File includes +// ***************************************************************************** +// ***************************************************************************** +#include "definitions.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: Macros +// ***************************************************************************** +// ***************************************************************************** +/* + * Adds two time values + */ +#define ADD_TIME(a, b) ((a) + (b)) + +/* + * Subtracts two time values + */ +#define SUB_TIME(a, b) ((a) - (b)) + +/* Wait for 65 ns. */ +#define PAL_WAIT_65_NS() {__NOP(); __NOP();} + +/* Enables the global interrupt */ +#define ENABLE_GLOBAL_IRQ() NVIC_INT_Enable(); + +/* Disables the global interrupt */ +#define DISABLE_GLOBAL_IRQ() NVIC_INT_Disable(); + +/* This macro saves the global interrupt status */ +#define ENTER_CRITICAL_REGION() {bool flags = NVIC_INT_Disable(); + +/* This macro restores the global interrupt status */ +#define LEAVE_CRITICAL_REGION() NVIC_INT_Restore(flags); } + +/* This macro defines the CPU clock frequency */ +#define PAL_CPU_CLOCK_FREQUENCY CPU_CLOCK_FREQUENCY + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Types +// ***************************************************************************** +// ***************************************************************************** + /* PAL Timer Callback type + + Summary: + Function Pointer holding application callback + + Description: + None + + Remarks: + None + */ +typedef void (*appCallback_t) (void *context); + +// ***************************************************************************** + /* PAL Timer Timeout type + + Summary: + Enum holding the types of timer timeout + + Description: + None + + Remarks: + None + */ +typedef enum timeout_type_tag { + /** The timeout is relative to the current time. */ + TIMEOUT_RELATIVE, + /** The timeout is an absolute value. */ + TIMEOUT_ABSOLUTE +} TimeoutType_t; + +// ***************************************************************************** + /* PAL Timer Callback type + + Summary: + Enum holding the types of callback methods + + Description: + Type of callbacks, + CALLBACK_SINGLE - Single Shot Timers - Callback called once the timer is + expired + CALLBACK_PERIODIC - Periodic Timer - Callback called continously on every timer expire + till the timer is stopped. + + Remarks: + None + */ + +typedef enum callback_type_tag { + /** Single Shot timer. */ + CALLBACK_SINGLE, + /** Periodic Timer. */ + CALLBACK_PERIODIC +} CallbackType_t; + +/* + * PAL Timer Id type + */ +typedef uint8_t TimerId_t; + +// ***************************************************************************** + /* PAL layer Return Status + + Summary: + Enum holding the return status of PAL layer + + Description: + + PAL_SUCCESS - Success status for the request + PAL_TMR_ALREADY_RUNNING - Received the request to start the timer, but the timer + is already running + PAL_TMR_NOT_RUNNING - PAL Timer is not running now. It got expired + PAL_TIMER_INVALID_ID - Timer ID given is not valid or out of range + PAL_TIMER_INVALID_TIMEOUT - Timer=out given is not valid + PAL_FAILURE - Failure status for the request + + Remarks: + None + */ +typedef enum pal_status_tag { + PAL_SUCCESS = 0x00, + PAL_TMR_ALREADY_RUNNING = 0x10, /**< Timer is already running */ + PAL_TMR_NOT_RUNNING = 0x11, /**< Timer is not running */ + PAL_TMR_INVALID_ID = 0x12, /**< Invalid timer ID*/ + PAL_TMR_INVALID_TIMEOUT = 0x13, /**< Requested Timeout is out of + * range or too short */ + PAL_FAILURE = 0x14, +} PAL_Status_t; + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Externals +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +// ***************************************************************************** +// Section: Function Prototypes +// ***************************************************************************** +// ***************************************************************************** + +#ifdef __cplusplus +extern "C" { +#endif + +// ***************************************************************************** +/* + Function: + PAL_Status_t PAL_Init(void) + + Summary: + Initialization of PAL + + Description: + This function initializes the timers array and initializes the PAL layer + variables + + Precondition: + SYS_TIME_Initialize() should have been called before calling this function. + + Parameters: + None. + + Returns: + PAL_SUCCESS - if PAL initialization is successful + PAL_FAILURE - otherwise + + Example: + + PAL_Status_t retVal = PAL_FAILURE; + + retVal = PAL_Init(); + if (PAL_SUCCESS =! retVal) + { + while(1); + } + + + Remarks: + This routine is called by the PHY layer during initialization. So, user can directly uses + PAL APIs. +*/ + +PAL_Status_t PAL_Init(void); + +// ***************************************************************************** +/* + Function: + PAL_Status_t PAL_TimerGetId(TimerId_t *timer_id) + + Summary: + Gets the Timer Id + + Description: + Returns a timer id to be used before starting a timer + + Precondition: + PAL_Init() should have been called before calling this function. + + Parameters: + timer_id - Value of the id returned by the function + + Returns: + PAL_Status_t - PAL_SUCCESS - If timer Id is allocated successfully + PAL_FAILURE - If there are no timer unused + + Example: + + TimerId_t appTimer; + + PAL_TimerGetId(&appTimer); + + + Remarks: + None +*/ + +PAL_Status_t PAL_TimerGetId(TimerId_t *timerId); + +// ***************************************************************************** +/* + Function: + PAL_Status_t PAL_TimerStart(TimerId_t timerId, + uint32_t timerCount, + TimeoutType_t timeoutType, + void * timerCb, + void *paramCb, + CallbackType_t callbackType) + + Summary: + Start regular timer + + Description: + This function starts a regular timer and installs the corresponding + callback function handle the timeout event + + Precondition: + PAL_Init() should have been called before calling this function. + PAL_TimerGetId() routine should be called to get the timer Id before starting it + + Parameters: + timerId - Timer identifier + timerCount - Timeout in microseconds + timeoutType - TIMEOUT_RELATIVE or @ref TIMEOUT_ABSOLUTE + timerCb - Callback handler invoked upon timer expiry + paramCb - Argument for the callback handler + callbackType- CALLBACK_SINGLE or @ref CALLBACK_PERIODIC. + + Returns: + PAL_TMR_INVALID_ID - if the timer identifier is undefined + PAL_INVALID_PARAMETER - if the callback function for this timer + is NULL, + PAL_TMR_ALREADY_RUNNING - if the timer is already running + PAL_SUCCESS - if timer is started or + PAL_TMR_INVALID_TIMEOUT - if timeout is not within timeout + + Example: + + PAL_Status_t retVal = PAL_FAILURE; + TimerId_t appTimer; + + static void AppTimerCallback(void *paramCb) + { + + } + + PAL_TimerGetId(&appTimer); + + if (PAL_SUCCESS == PAL_TimerStart(appTimer, + 5000, + TIMEOUT_RELATIVE, + (void *)AppTimerCallback, + NULL, CALLBACK_SINGLE)) + { + printf("Timer Started"); + } + + + + Remarks: + Starting PAL_Timer before getting the Id of timer will lead to unpredicted behaviour +*/ + +PAL_Status_t PAL_TimerStart(TimerId_t timerId, + uint32_t timerCount, + TimeoutType_t timeoutType, + appCallback_t timerCb, + void *paramCb, + CallbackType_t callbackType); + +// ***************************************************************************** +/* + Function: + PAL_Status_t PAL_TimerStop(TimerId_t timerId) + + Summary: + Stops a running timer + + Description: + This function stops a running timer with specified timer_id + + Precondition: + Timer should have been started before using this function + + Parameters: + timerId - Timer identifier + + Returns: + PAL_TMR_INVALID_ID - if the timer identifier is undefined + PAL_SUCCESS - if timer is stopped successfully + + Example: + + PAL_Status_t retVal = PAL_FAILURE; + TimerId_t appTimer; + + static void AppTimerCallback(void *paramCb) + { + LED_Off(); + } + + PAL_TimerGetId(&appTimer); + + if (PAL_SUCCESS == PAL_TimerStart(appTimer, + 5000, + TIMEOUT_RELATIVE, + (void *)AppTimerCallback, + NULL, CALLBACK_SINGLE)) + { + printf("Timer Started"); + LED_On(); + } + + if (PAL_SUCCESS == PAL_TimerStop(appTimer)) + { + printf("Timer Stopped"); + LED_Toggle(); + } + + + + Remarks: + Timer should be started before stopping it +*/ + +PAL_Status_t PAL_TimerStop(TimerId_t timerId); + +// ***************************************************************************** +/* + Function: + uint32_t PAL_GetCurrentTime(void) + + Summary: + Gets current time + + Description: + This function returns the current time. + + Precondition: + None + + Parameters: + None + + Returns: + None + + Example: + + uint32_t currTime ; + currTime = PAL_GetCurrentTimer(); + return currTime; + + + Remarks: + None +*/ + +uint32_t PAL_GetCurrentTime(void); + + +// ***************************************************************************** +/* + Function: + bool PAL_TimerIsRunning(TimerId_t timer_id) + + Summary: + Gets the status of running timer + + Description: + Checks if the timer of requested timer identifier is running + + Precondition: + Timer should have been started before using this function + + Parameters: + timer_id - Timer identifier + + Returns: + bool - true - If timer with requested timer id is running, + - false otherwise. + + Example: + + PAL_Status_t retVal = PAL_FAILURE; + TimerId_t appTimer; + bool IsTimerRunning = false; + + static void AppTimerCallback(void *paramCb) + { + LED_Toggle(); + } + + PAL_TimerGetId(&appTimer); + + if (PAL_SUCCESS == PAL_TimerStart(appTimer, + 5000, + TIMEOUT_RELATIVE, + (void *)AppTimerCallback, + NULL, CALLBACK_SINGLE)) + { + printf("Timer Started"); + LED_Toggle(); + } + + IsTimerRunning = PAL_TimerIsRunning(appTimer); + + if(IsTimerRunning) + { + printf("Timer is Running"); + } + + + + Remarks: + None +*/ + +bool PAL_TimerIsRunning(TimerId_t timerId); + +// ***************************************************************************** +/* + Function: + void PAL_TimerDelay(uint32_t delay) + + Summary: + Routine to introduce blocking delay + + Description: + This function is used to create the blocking delay in us + + Precondition: + None + + Parameters: + delay - Blocking delay value in microseconds + + Returns: + None + Example: + + uint32_t delayUs = 5000; + + RGB_GREEN_LED_ON(); + PAL_TimerDelay(delayUs); + RGB_GREEN_LED_OFF(); + + + Remarks: + None +*/ + +void PAL_TimerDelay(uint32_t delay); + +// ***************************************************************************** +/* + Function: + static inline uint32_t pal_add_time_us(uint32_t a, uint32_t b) + + Summary: + Routine to add two time values + + Description: + Helper function to add two time values + + Precondition: + None + + Parameters: + a - Time 1 value + b - Time 2 value + + Returns: + return - Addition of a and b + + Example: + None + + Remarks: + None +*/ + +static inline uint32_t pal_add_time_us(uint32_t a, uint32_t b) +{ + return (ADD_TIME(a, b)); +} + +// ***************************************************************************** +/* + Function: + static inline uint32_t pal_sub_time_us(uint32_t a, uint32_t b) + + Summary: + Routine to substract two time values + + Description: + Helper function to substract two time values + + Precondition: + None + + Parameters: + a - Time 1 value + b - Time 2 value + + Returns: + return - Difference between a and b + + Example: + None + + Remarks: + None +*/ +static inline uint32_t pal_sub_time_us(uint32_t a, uint32_t b) +{ + return (SUB_TIME(a, b)); +} + +// ***************************************************************************** +/* + * \brief Enables the transceiver main interrupt + * + * This macro is only available for non-single chip transceivers, since + * in single chip transceivers there is no separation between enabling + * transceiver interrupts at the transceiver, and setting the IRQ mask + * at the MCU. Therefore the transceiver interrupts in single chips are + * enabled by setting the MCU IRQ mask. + * + */ +#define pal_trx_irq_en() EIC_InterruptEnable (EIC_PIN_${SELECTED_EIC_CHANNEL}) + + + + +// ***************************************************************************** +/* + * \brief Disables the transceiver main interrupt + * + * This macro is only available for non-single chip transceivers, since + * in single chip transceivers there is no separation between disabling + * transceiver interrupts at the transceiver, and clearing the IRQ mask + * at the MCU. Therefore the transceiver interrupts in single chips are + * disabled by clearing the MCU IRQ mask. + * + */ + +#define pal_trx_irq_dis() EIC_InterruptDisable(EIC_PIN_${SELECTED_EIC_CHANNEL}); + +// ***************************************************************************** +/* + * \brief Enables the global interrupt + */ +static inline void pal_global_irq_enable(void) +{ + (void)ENABLE_GLOBAL_IRQ(); +} + +// ***************************************************************************** +/* + * \brief Disables the global interrupt + */ +static inline void pal_global_irq_disable(void) +{ + (void)DISABLE_GLOBAL_IRQ(); +} + +// ***************************************************************************** + +/* + Function: + PAL_Status_t PAL_GetRandomNumber(uint8_t *rnOutput, uint16_t rnLength) + + Summary: + Random number generation + + Description: + This function is used to generate random number + + Precondition: + None + + Parameters: + rnOutput - random number + rnLength - size of random number + + Returns: + None + Example: + + uint64_t randomNumber; + if (PAL_SUCCESS != PAL_GetRandomNumber((uint8_t*)&randomNumber, sizeof(randomNumber))) { + return PAL_FAILURE; + } + PHY_PibSet(macIeeeAddress,(PibValue_t *) &randomNumber); + + + Remarks: + None +*/ + +PAL_Status_t PAL_GetRandomNumber(uint8_t *rnOutput, uint16_t rnLength); + +// ***************************************************************************** + +/* + Function: + PAL_Status_t PAL_GetTrxAntennaGain(int8_t *antGain) + + Summary: + Gets the Antenna gain from the information block of device support library + + Description: + This function is used to get the antenna gain either from the information + block of device support library or the user specified custom antenna gain + + Precondition: + None + + Parameters: + antGain - Pointer holding the module's antenna gain value + + Returns: + None + + Example: + + int8_t antGain = INT8_MAX; + + PAL_GetTrxAntennaGain(&antGain); + printf ("Antenna Gain of the module - %i", antGain); + + + Remarks: + If customer provides the antenna gain of the module, this function returns CUSTOM_ANT_GAIN value + or it will read from the information block of device support library if valid. + Otherwise, DEFAULT_ANT_GAIN value is returned. +*/ +//PAL_Status_t PAL_GetTrxAntennaGain(int8_t *antGain); + +/* + Function: + int8_t PAL_GetTrxTransmitPowerMax(void) + + Summary: + Gets the transceiver's maximum transmit power in dBm + + Description: + This function returns the maximum transmit power that can be set in the Transceiver + as per Regulatory region selected in Device support + library. User cannot set the Tx power beyond this value. + + Precondition: + None + + Parameters: + Output - Integer value holding the maximum transmit power of the transceiver + that can be set by higher layer. + + Returns: + None + + Example: + + int8_t txpwrMax = INT8_MAX; + + txpwrMax = PAL_GetTrxTransmitPowerMax(); + printf ("Maximum Tx Pwr Value - %i", txpwrMax); + + + Remarks: + Transmit Power Max value as per Regulatory region +*/ +//int8_t PAL_GetTrxTransmitPowerMax(void); + +/* ! @} */ +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* PAL_H */ +/* EOF */ + + diff --git a/driver/templates/common/phy_initialize.c.ftl b/driver/templates/common/phy_initialize.c.ftl new file mode 100644 index 0000000..4b3c321 --- /dev/null +++ b/driver/templates/common/phy_initialize.c.ftl @@ -0,0 +1,26 @@ +<#-- +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +--> + NVIC_Initialize(); + PHY_Init(); \ No newline at end of file diff --git a/driver/templates/common/phy_task.c.ftl b/driver/templates/common/phy_task.c.ftl new file mode 100644 index 0000000..5ecacd7 --- /dev/null +++ b/driver/templates/common/phy_task.c.ftl @@ -0,0 +1,48 @@ +<#-- +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +--> +<#if HarmonyCore.SELECT_RTOS == "BareMetal"> + /* Call the IEEE_802154_PHY Task Handler function */ + PHY_TaskHandler(); +<#else> +<#if HarmonyCore.SELECT_RTOS == "FreeRTOS"> + + /* Create FreeRTOS task for IEEE_802154_PHY */ + (void)xTaskCreate((TaskFunction_t) _PHY_Tasks, + "PHY_Tasks", + 256, + NULL, + 4, + &xPHY_Tasks); + + /* Create FreeRTOS task for IEEE_802154_PHY */ + (void)xTaskCreate((TaskFunction_t) _TAL_Tasks, + "TAL_Tasks", + 256, + NULL, + 5, + &xTAL_Tasks); + + + \ No newline at end of file diff --git a/driver/templates/common/phy_task_def.c.ftl b/driver/templates/common/phy_task_def.c.ftl new file mode 100644 index 0000000..e4d9b99 --- /dev/null +++ b/driver/templates/common/phy_task_def.c.ftl @@ -0,0 +1,49 @@ +<#-- +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +--> +<#if HarmonyCore.SELECT_RTOS == "FreeRTOS"> + +/* Handle for the PHY_Tasks. */ +TaskHandle_t xPHY_Tasks; + +static void _PHY_Tasks( void *pvParameters ) +{ + while(true) + { + PHY_Tasks(); + } +} + +/* Handle for the TAL_Tasks. */ +TaskHandle_t xTAL_Tasks; + +static void _TAL_Tasks( void *pvParameters ) +{ + while(true) + { + TAL_Tasks(); + } +} + + diff --git a/driver/templates/common/sem_createInit.c.ftl b/driver/templates/common/sem_createInit.c.ftl new file mode 100644 index 0000000..2e4338c --- /dev/null +++ b/driver/templates/common/sem_createInit.c.ftl @@ -0,0 +1,52 @@ +<#-- +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +--> + + // Set up OSAL for RF Stack Library usage + osalAPIList.OSAL_CRIT_Enter = OSAL_CRIT_Enter; + osalAPIList.OSAL_CRIT_Leave = OSAL_CRIT_Leave; + + osalAPIList.OSAL_SEM_Create = OSAL_SEM_Create; + osalAPIList.OSAL_SEM_Pend = OSAL_SEM_Pend; + osalAPIList.OSAL_SEM_Post = OSAL_SEM_Post; + osalAPIList.OSAL_SEM_PostISR = OSAL_SEM_PostISR; + osalAPIList.OSAL_SEM_GetCount = OSAL_SEM_GetCount; + + osalAPIList.OSAL_QUEUE_Create = OSAL_QUEUE_Create; + osalAPIList.OSAL_QUEUE_Send = OSAL_QUEUE_Send; + osalAPIList.OSAL_QUEUE_SendISR = OSAL_QUEUE_SendISR; + osalAPIList.OSAL_QUEUE_Receive = OSAL_QUEUE_Receive; + osalAPIList.OSAL_QUEUE_IsFullISR = OSAL_QUEUE_IsFullISR; + osalAPIList.OSAL_QUEUE_CreateSet = OSAL_QUEUE_CreateSet; + osalAPIList.OSAL_QUEUE_AddToSet = OSAL_QUEUE_AddToSet; + osalAPIList.OSAL_QUEUE_SelectFromSet = OSAL_QUEUE_SelectFromSet; + + osalAPIList.OSAL_MemAlloc = OSAL_Malloc; + osalAPIList.OSAL_MemFree = OSAL_Free; + + //Create the semmaphore + OSAL_SEM_Create(&semPhyInternalHandler, OSAL_SEM_TYPE_COUNTING, 20, 0); + OSAL_SEM_Create(&semTalInternalHandler, OSAL_SEM_TYPE_COUNTING, 20, 0); + + \ No newline at end of file diff --git a/driver/templates/common/sem_handle_init.c.ftl b/driver/templates/common/sem_handle_init.c.ftl new file mode 100644 index 0000000..dba2d4e --- /dev/null +++ b/driver/templates/common/sem_handle_init.c.ftl @@ -0,0 +1,28 @@ +<#-- +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +--> + +OSAL_SEM_HANDLE_TYPE semPhyInternalHandler; +OSAL_SEM_HANDLE_TYPE semTalInternalHandler; +OSAL_API_LIST_TYPE osalAPIList; diff --git a/driver/templates/common/stack_config.h.ftl b/driver/templates/common/stack_config.h.ftl new file mode 100644 index 0000000..6e060b9 --- /dev/null +++ b/driver/templates/common/stack_config.h.ftl @@ -0,0 +1,103 @@ +/******************************************************************************* + Stack Config Header + + File Name: + stack_config.h + + Summary: + This file contains the application specific definitions for + Resource management + + Description: + These are application-specific resources which are used in the example + application of the coordinator in addition to the underlaying stack. +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +/* Prevent double inclusion */ +#ifndef STACK_CONFIG_H +#define STACK_CONFIG_H + +/* === INCLUDES ============================================================ */ +#include "config/default/driver/IEEE_802154_PHY/phy/inc/phy.h" + +/* === EXTERNALS =========================================================== */ + +/* === MACROS ============================================================== */ +/* LARGE_BUFFER_SIZE + + Summary: + This macro hold the Large buffer size value used in PHY library + Description: + The following macros hold the size of a large buffer. + Additional octets for the length of the frame, the LQI + and the ED value are required. + Size of PHY_FrameInfo_t + max number of payload octets + + 1 octet LQI + 1 octet ED value + 1 octet Length field. + Remarks: + None + */ + +#ifndef LARGE_BUFFER_SIZE +#define LARGE_BUFFER_SIZE (((sizeof(PHY_FrameInfo_t) + \ + aMaxPHYPacketSize + \ + LENGTH_FIELD_LEN + LQI_LEN + ED_VAL_LEN) / 4U + 1U) * 4U) +#endif + +// ***************************************************************************** +/* SMALL_BUFFER_SIZE + + Summary: + This macro hold the small buffer size value + Description: + The following macros hold the size of a small buffer. + Additional octets for the length of the frame, the LQI + and the ED value are required. + Size of PHY_FrameInfo_t + max number of mac management frame len + + 1 octet LQI + 1 octet ED value + 1 octet Length field. + Remarks: + None + */ + +#ifndef SMALL_BUFFER_SIZE +#define SMALL_BUFFER_SIZE (((sizeof(PHY_FrameInfo_t) + \ + MAX_MGMT_FRAME_LENGTH + \ + LENGTH_FIELD_LEN + LQI_LEN + ED_VAL_LEN) / 4U + 1U) * 4U) +#endif + +/* + * Configuration of Large and Small Buffers Used in Radio Layer + */ +#define NUMBER_OF_LARGE_PHY_BUFS (${PHY_INTEGER_BMMLARGEBUFFERS}U) +#define NUMBER_OF_SMALL_PHY_BUFS (${PHY_INTEGER_BMMSMALLBUFFERS}U) + +/* === TYPES =============================================================== */ + + +/* === PROTOTYPES ========================================================== */ + +#endif /* STACK_CONFIG_H */ diff --git a/module.xml b/module.xml new file mode 100644 index 0000000..0ebc6a3 --- /dev/null +++ b/module.xml @@ -0,0 +1,4 @@ + + + + diff --git a/mplab_harmony_license.md b/mplab_harmony_license.md new file mode 100644 index 0000000..1550525 --- /dev/null +++ b/mplab_harmony_license.md @@ -0,0 +1,63 @@ +MICROCHIP SOFTWARE IS PROVIDED SOLELY TO ASSIST YOU IN DEVELOPING PRODUCTS AND SYSTEMS THAT USE MICROCHIP PRODUCTS. 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WHERE LICENSEE IS A CONSUMER LOCATED IN EUROPE, THE FOLLOWING PROVISIONS APPLY INSTEAD OF SECTIONS 9 AND 10 BELOW: Microchip and its licensors will not be liable (a) for any loss suffered by Licensee in connection with the Software where such loss was not reasonably foreseeable when the Software was first downloaded by Licensee, even if such loss was the result of negligence or the failure of Microchip and its licensors to comply with this Agreement; or (b) irrespective of the basis of claim, for any loss of revenue, profit or other business or economic loss suffered. Some Software is made available to Licensee free of charge, and Licensee may at any time download further copies without charge to replace the Software initially downloaded and others may require a fee to be downloaded, or to download any further copies. In all circumstances, to the extent liability may lawfully be limited or excluded, the cumulative liability of Microchip and its licensors will not exceed USD$1,000 (or equivalent sum in the currency of the country in which Licensee resides). However, none of the foregoing limits or excludes any liability for death or personal injury arising from negligence, or for fraud, fraudulent misrepresentation or any other cause that by law cannot be excluded and limited. + + 10. Warranty Disclaimers. EXCEPT FOR CONSUMERS TO WHOM SECTION 8 APPLIES, THE SOFTWARE IS LICENSED ON AN "AS-IS" BASIS. MICROCHIP MAKES NO WARRANTIES OF ANY KIND WITH RESPECT TO THE SOFTWARE, WHETHER EXPRESS, IMPLIED, STAUTORY OR OTHERWISE, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE OR NON-INFRINGEMENT AND ANY WARRANTIES THAT MAY ARISE FROM USAGE OF TRADE OR COURSE OF DEALING. MICROCHIP AND ITS LICENSORS HAVE NO OBLIGATION TO CORRECT ANY DEFECTS IN THE SOFTWARE. TECHNICAL ASSISTANCE, IF PROVIDED, WILL NOT EXPAND THESE WARRANTIES. IF CUSTOMER IS A CONSUMER, THE ABOVE WILL NOT ACT TO EXCLUDE YOUR STATUTORY RIGHTS. + + 11. Limited Liability. EXCEPT FOR CONSUMERS TO WHOM SECTION 8 APPLIES, IN NO EVENT WILL MICROCHIP BE LIABLE, WHETHER IN CONTRACT, WARRANTY, REPRESENTATION, TORT, STRICT LIABILITY, INDEMNITY, CONTRIBUTION OR OTHERWISE, FOR ANY INDIRECT, SPECIAL, PUNITIVE, EXEMPLARY, INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER, HOWEVER CAUSED, OR ANY LOSS OF PRODUCTION, COST OF PROCUREMENT OF SUBSTITUTE PRODUCTS OR SERVICES, ANY LOSS OF PROFITS, LOSS OF BUSINESS, LOSS OF USE OR LOSS OF DATA, OR INTERRUPTION OF BUSINESS ARISING OUT OF THIS AGREEMENT, HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSS, AND NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY. MICROCHIP'S TOTAL AGGREGATE LIABILITY UNDER THIS AGREEMENT WILL NOT EXCEED USD$1,000. + + 12. General. + + (a) This Agreement will be governed by and construed in accordance with the laws of the State of Arizona and the United States, without regard to conflicts of law provisions. The parties hereby irrevocably consent to the exclusive personal jurisdiction and venue of the state and federal courts in Maricopa County, Arizona for any dispute relating to this Agreement. WHERE LICENSEE IS A CONSUMER LOCATED IN EUROPE, this Agreement is subject to the laws of the country in which the Software is downloaded, and, to the extent so mandated by such laws, subject to the jurisdiction of the courts of that country. The parties expressly disclaim the applicability of the United Nations Convention on Contracts for the International Sale of Goods in connection with this Agreement. + + (b) Unless the parties have a mutually executed agreement relating to the licensing of this Software by Microchip to Licensee ("Signed Agreement"), this Agreement constitutes the entire agreement between the parties with respect to the Software, and supersedes and replaces prior or contemporaneous written or verbal agreements or communications between the parties regarding the Software, including any purchase orders. If the parties have a Signed Agreement, this Agreement does not supersede or replace that Signed Agreement. This Agreement will not be modified except by a written agreement signed by an authorized representative of Microchip. If any provision of this Agreement is held by a court of competent jurisdiction to be illegal, invalid, or unenforceable, that provision will be limited or eliminated to the minimum extent necessary so that this Agreement will otherwise remain in full force and effect and enforceable. No waiver of any breach of any provision of this Agreement constitutes a waiver of any prior, concurrent, or subsequent breach of the same or any other provisions of this Agreement, and no waiver will be effective unless made in writing and signed by an authorized representative of the waiving party. + + (c) Licensee agrees to comply with all import and export laws and restrictions and regulations of the Department of Commerce or other United States or foreign agency or authority. + + (d) This Agreement will bind and inure to the benefit of each party's permitted successors and assigns. Licensee may not assign this Agreement in whole or in part, whether by law or otherwise, without Microchip's prior written consent. Any merger, consolidation, amalgamation, reorganization, transfer of all or substantially all assets or other change in control or majority ownership ("Change of Control") is considered an assignment for the purpose of this Section. Any attempt to assign this Agreement without such consent will be null and void. However, Microchip may assign this Agreement to an affiliate, or to another entity in the event of a Change of Control. + + (e) Licensee acknowledges its breach of any confidentiality or proprietary rights provision of this Agreement would cause Microchip irreparable damage, for which the award of damages would not be an adequate remedy. Licensee, therefore, agrees if Microchip alleges that Licensee has breached or violated any such provisions then Microchip may seek equitable relief, in addition to all other remedies at law or in equity. + + (f) Authorized representatives of Microchip shall have the right to reasonably inspect Licensee's premises and to audit Licensee's records and inventory of Licensee Products, whether located on Licensee's premises or elsewhere at any time, announced or unannounced, and in its sole and absolute discretion, in order to ensure Licensee's adherence to the terms of this Agreement. + + (g) Consistent with 48 C.F.R. §12.212 or 48 C.F.R. §227.7202-1 through 227.7202-4, as applicable, the Software is being licensed to U.S. Government end users (i) only as Commercial Items, and (ii) with only those rights as are granted to all other end users pursuant to the terms and conditions of the applicable Microchip licenses. To the extent the Software (or a portion thereof) qualifies as 'technical data' as such term is defined in 48 C.F.R. §252.227-7015(a)(5), then its use, duplication, or disclosure by the U.S. Government is subject to the restrictions set forth in subparagraphs (a) through (e) of the Rights in Technical Data clause at 48 C.F.R. §252.227-7015. Contractor/manufacturer is Microchip Technology Inc., 2355 W. Chandler Blvd., Chandler, AZ 85224-6199. + +Questions about this Agreement should be sent to: Microchip Technology Inc., 2355 W. Chandler Blvd., Chandler, AZ 85224-6199 USA. ATTN: Marketing. + +v.3.3.2021 diff --git a/package.xml b/package.xml new file mode 100644 index 0000000..beca403 --- /dev/null +++ b/package.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/package.yml b/package.yml new file mode 100644 index 0000000..9dd42c0 --- /dev/null +++ b/package.yml @@ -0,0 +1,27 @@ +package: + format-version: "1.0.0" + name: "standalone_PHY" + type: "api" + status: "beta" + required: false + version: "1.0.0" + + dependencies: + - name: "core" + type: "package" + version: "3.13.0" + - name: "csp" + type: "package" + version: "3.18.0" + - name: "bsp" + type: "package" + version: "3.17.0" + - name: "CMSIS-FreeRTOS" + type: "package" + version: "10.3.1" + - name: "dev_packs" + type: "package" + version: "3.17.0" + - name: "wireless_system_pic32cxbz_wbz" + type: "package" + version: "1.3.0" diff --git a/release_notes.md b/release_notes.md new file mode 100644 index 0000000..0340ba2 --- /dev/null +++ b/release_notes.md @@ -0,0 +1,40 @@ +![Microchip logo](https://raw.githubusercontent.com/wiki/Microchip-MPLAB-Harmony/Microchip-MPLAB-Harmony.github.io/images/microchip_logo.png) +![Harmony logo small](https://raw.githubusercontent.com/wiki/Microchip-MPLAB-Harmony/Microchip-MPLAB-Harmony.github.io/images/microchip_mplab_harmony_logo_small.png) + +# Microchip Standalone IEEE 802.15.4 Physical Layer Release Notes + + +## Release v1.0.0 + +The physical layer contains the transceiver specific functionalities as mentioned as the requirements of IEEE 802.15.4 specification. It gives the interface to the MAC core layer which is independent of the underlying transceiver. +Besides that, the PHY layer provides the set of APIs which can be used to interface a basic application. +The following are the funcionalities of PHY layer + +- Frame Transmission (including automatic frame retries) +- Frame reception (including automatic acknowledgement handling) +- PHY PIB storage +- CSMA module +- Energy detection +- Power management(Trx Sleep) +- Interrupt handling +- Initialization and Reset +- Enabling High Datarate Support +- Enabling Promiscuous Mode +- Enabling Antenna Diversity +- Enabling Reduced Power consumption modes (Only for RF233. Not supported by RF212B) + + +## Known Issues / Limitations + +- Deep Sleep feature is not implemented. + +## Development Tools +- MPLAB X v6.15 +- MPLAB® XC32 C/C++ Compiler v4.35 +- MPLAB® X IDE plug-ins: MPLAB® Code Configurator (MCC) v5.3.7 and above +- Device Pack: SAML21_DFP (3.7.217) + +## Notes +- None + +