{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":21527084,"defaultBranch":"MrChromebox-2408","name":"coreboot","ownerLogin":"MrChromebox","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2014-07-05T19:48:17.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/948902?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1724450595.0","currentOid":""},"activityList":{"items":[{"before":"ea72ff0bb40a9d0e97e256a9477319d2c32216c7","after":"9e73de01e60843e43e07038e6da52665c77bbc1c","ref":"refs/heads/next","pushedAt":"2024-09-22T23:15:35.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"mb/google: Correct number of jacks in hda_verb.c\n\nThis corrects the mismatch found in the verb tables of Monroe Chromebase\nand Link Chromebook.\n\nThe verb data was not aligned to a multiple of 4, therefore an entry was\nrepeated as padding. This has not been tested.\n\nThis was found due to the `_Static_assert()` from CB:84360 failing.\n\nChange-Id: Id377281af310642a6ba77e5a0002ca1dfca38827\nSigned-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>","shortMessageHtmlLink":"mb/google: Correct number of jacks in hda_verb.c"}},{"before":"e187645fb0bed11954eaf1155f8f1f33160131d6","after":"ea72ff0bb40a9d0e97e256a9477319d2c32216c7","ref":"refs/heads/next","pushedAt":"2024-09-17T20:28:31.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"mb/google/dedede: Select INTEL_CRASHLOG only for ChromeOS builds\n\nSelecting this option for non-ChromeOS builds significantly impacts\nboot time negatively and breaks USB detection in edk2 payload.\n\nTEST=build/boot google/maglia, verify boot time normal and USB\ndetection working as expected with multiple devices connected.\n\nChange-Id: I53be4befe9a04bdaece21f40f93af6599baa7e0b\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"mb/google/dedede: Select INTEL_CRASHLOG only for ChromeOS builds"}},{"before":"5adabe12eaf29163a6d2ce1fc57b30b16e178666","after":"259b01deb790f93c326a00c123c6bab7372a35ed","ref":"refs/heads/MrChromebox-2408","pushedAt":"2024-09-13T14:16:16.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"ec/google/chromeec: Ensure pre-CR50 devices use \"short\" battery strings\n\nCommit b97ec4f0166b (\"chromeec: support reading long battery strings\")\nadded support for reading long battery strings, but the method used to\ndetermine if this feature is supported causes Windows to hang when\nbooting on older pre-CR50 ChromeOS devices. Add a short circuit to the\nBRSX method to ensure that pre-CR50 devices use older/shorter strings.\n\nIn testing, affected platforms were Broadwell/Braswell and earlier.\nSkylake is pre-CR50 as well, but unaffected. No adverse impact to\ngrouping it with the others as those boards do not support or use\nlonger battery strings.\n\nTEST=build/boot Windows on google link, wolf, samus, chell and others.\nVerify boot successful and battery info populated correctly.\n\nChange-Id: If3686dc9b82b44202947081ec7e253317deb8fff\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"ec/google/chromeec: Ensure pre-CR50 devices use \"short\" battery strings"}},{"before":"df3f5db88a70f9ac73965616b75e353da0e02db1","after":"e187645fb0bed11954eaf1155f8f1f33160131d6","ref":"refs/heads/next","pushedAt":"2024-09-10T16:14:31.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"build: add configs, build scripts, cfbs files for supported boards\n\nChange-Id: I9ba1b3dc448cc447ab83d64f08d14406826fcede\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"build: add configs, build scripts, cfbs files for supported boards"}},{"before":"1b3587c2fc828da359bb93b928abbd3ddf75ce16","after":"5adabe12eaf29163a6d2ce1fc57b30b16e178666","ref":"refs/heads/MrChromebox-2408","pushedAt":"2024-08-21T17:49:36.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"mb/google/*: Add GOOG0005 as CID for SPI-attached CR50 TPM\n\nEnables coolstar's Windows drivers to automatically attach.\n\nChange-Id: Ifbd47b5f35169b8d11284b2a85b11deed30c8ec9\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"mb/google/*: Add GOOG0005 as CID for SPI-attached CR50 TPM"}},{"before":"c3ec42e3a440dd866a51c2f2c0d9d384eb026f0b","after":"59d3c94f5d612402308f73bc125becf64df84dee","ref":"refs/heads/MrChromebox-2405","pushedAt":"2024-08-20T14:39:17.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"mb/google/byra/var/kinox: Add/update VBT files\n\nKinox has two VBT options, selected via fw_config. Add the second\noption to CBFS, and update the original file.\n\nExtracted from Google_Kinox.14505.704.0.bin.\n\nTEST=build/boot kinix, verify firmware display init successful and\npayload menu visible. Verify correct VBT selected via cbmem log.\n\nChange-Id: I01c19222628fee3874ef592ec40b40d9bd679dce\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"mb/google/byra/var/kinox: Add/update VBT files"}},{"before":"29194f669212f0e86db8b9c3ae78aef0fc95e06a","after":"1b3587c2fc828da359bb93b928abbd3ddf75ce16","ref":"refs/heads/MrChromebox-2408","pushedAt":"2024-08-19T16:58:30.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"mb/google/byra/var/kinox: Add/update VBT files\n\nKinox has two VBT options, selected via fw_config. Add the second\noption to CBFS, and update the original file.\n\nExtracted from Google_Kinox.14505.704.0.bin.\n\nTEST=build/boot kinix, verify firmware display init successful and\npayload menu visible. Verify correct VBT selected via cbmem log.\n\nChange-Id: I01c19222628fee3874ef592ec40b40d9bd679dce\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"mb/google/byra/var/kinox: Add/update VBT files"}},{"before":"8cccda0abf39eea8be01d9943ab4b20088a31a51","after":"29194f669212f0e86db8b9c3ae78aef0fc95e06a","ref":"refs/heads/MrChromebox-2408","pushedAt":"2024-08-14T20:51:17.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"update to HEAD of master branch\n\nChange-Id: I0f7f8a2f38fbf86fff257a121ee5d7b7ca45349e\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"update to HEAD of master branch"}},{"before":"ab1432886bf671acb9e88dcb7268ea44a560713b","after":"8cccda0abf39eea8be01d9943ab4b20088a31a51","ref":"refs/heads/MrChromebox-2408","pushedAt":"2024-08-14T20:08:49.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":" [NOT_FOR_MERGE] MRC debugging\n\nChange-Id: I1b05d230f9c594eb099f5aa7f91dcca5ea17e91c\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":" [NOT_FOR_MERGE] MRC debugging"}},{"before":null,"after":"ab1432886bf671acb9e88dcb7268ea44a560713b","ref":"refs/heads/MrChromebox-2408","pushedAt":"2024-08-07T22:34:43.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"SL: update edk2 branch to uefipayload_2408\n\nChange-Id: I7b09844745465d2b6fbe7c1f2054dd2e5a09c1ff\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"SL: update edk2 branch to uefipayload_2408"}},{"before":"403979cf385d42178a19abfaf908682b5e6e1134","after":"c3ec42e3a440dd866a51c2f2c0d9d384eb026f0b","ref":"refs/heads/MrChromebox-2405","pushedAt":"2024-07-15T18:05:12.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"payloads/edk2/Makefile: Add $(EDK2_PATH) as dependency for 'gop_driver' target\n\nWithout this, when doing a clean build with 'make j$(nproc)`, the build\ncan fail copying the GOP driver file since the target directory does\nnot exist yet.\n\nTEST=build/boot google/hatch (akemi) w/edk2 payload and GOP driver init\non a clean git checkout.\n\nChange-Id: Ic510d70041dc099e6bc469528b80d1e271976655\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"payloads/edk2/Makefile: Add $(EDK2_PATH) as dependency for 'gop_drive…"}},{"before":"7e73aa8bfdc0765aa334c5604a5c9c0f0eb2281d","after":"403979cf385d42178a19abfaf908682b5e6e1134","ref":"refs/heads/MrChromebox-2405","pushedAt":"2024-07-15T18:04:00.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"payloads/edk2/Makefile: Add $(EDK2_PATH) as dependency for 'gop_driver' target\n\nWithout this, when doing a clean build with 'make j$(nproc)`, the build\ncan fail copying the GOP driver file since the target directory does\n not exist yet.\n\nTEST=build/boot google/hatch (akemi) w/edk2 payload and GOP driver init\non a clean git checkout.\n\nChange-Id: Ic510d70041dc099e6bc469528b80d1e271976655\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"payloads/edk2/Makefile: Add $(EDK2_PATH) as dependency for 'gop_drive…"}},{"before":"2caa715d941490e92c55e9aeb975d27775cb75d2","after":"7e73aa8bfdc0765aa334c5604a5c9c0f0eb2281d","ref":"refs/heads/MrChromebox-2405","pushedAt":"2024-07-13T16:50:49.000Z","pushType":"push","commitsCount":4,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"mb/google/byra: Add VBTs for variants missing them\n\nSeveral brya variants were missing VBT files, add and select them in\nKconfig.\n\nAlso select in Kconfig for VELL, which already had a VBT but was not\nusing/selecting it.\n\nTEST=build/boot google/brya (marasov), verify display init functional\n/ payload screen shown.\n\nChange-Id: I6848c2b78cf37157299d94bf12c0b6d925ea1432\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"mb/google/byra: Add VBTs for variants missing them"}},{"before":"e1b9e324740f740351a51c5980459b994cf93fc6","after":null,"ref":"refs/heads/x220-2017.02.18","pushedAt":"2024-07-10T14:47:36.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"}},{"before":"77d3dc805323b402f8d2acbf73c08bbf607083e3","after":null,"ref":"refs/heads/master","pushedAt":"2024-07-10T14:47:27.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"}},{"before":"596e18c35e14bcd5ba81d533d914d5bc82c88e63","after":null,"ref":"refs/heads/working","pushedAt":"2024-07-10T14:47:21.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"}},{"before":"d477980712d743afe1e298a5a8d722468ab42b3f","after":null,"ref":"refs/heads/starlite_adl_brightness","pushedAt":"2024-07-10T14:46:52.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"}},{"before":"140dd8d96c77088618fb4c4c714731f7138652b5","after":null,"ref":"refs/heads/MrChromebox-2405_MDN","pushedAt":"2024-07-10T14:46:48.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"}},{"before":null,"after":"140dd8d96c77088618fb4c4c714731f7138652b5","ref":"refs/heads/MrChromebox-2405_MDN","pushedAt":"2024-07-08T21:30:40.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"Workarounds for older vboot\n\nChange-Id: I9ab5166524a5bbb0b70a9173988c5c6b3e2dd756\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"Workarounds for older vboot"}},{"before":"e935ce180ec1fc62417c13d42f2b6fb822594dd4","after":"2caa715d941490e92c55e9aeb975d27775cb75d2","ref":"refs/heads/MrChromebox-2405","pushedAt":"2024-06-26T02:20:19.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"mb/google/drallion: Don't enable DPTF PCI device\n\nEnabling the DPTF device causes the cmoon/block/dtt driver to generate a\n2nd TCPU ACPI device in the SSDT, causing the entire SSDT to be ignored\nunder Windows, leading to many devices (like touchpad/touchscreen) not\nworking at all.\n\nTEST=build/boot Win11 on google/drallion, verify SSDT able to be parsed,\nno duplicate TCPU device, and touchpad/touchscreen work properly.\n\nChange-Id: Ic0e07d9d64c543121aa51a7cfd63fe3686192825\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"mb/google/drallion: Don't enable DPTF PCI device"}},{"before":null,"after":"d477980712d743afe1e298a5a8d722468ab42b3f","ref":"refs/heads/starlite_adl_brightness","pushedAt":"2024-06-24T21:10:15.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"mb/starlabs/starlite_adl: Re-add GMA default panel to iGPU\n\nEnables ACPI brightness controls under Windows/Linux.\n\nTEST=build/boot Win11, Linux on Lite5, verify brightness controls\nfunctional, proper brightness levels set on resume.\n\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"mb/starlabs/starlite_adl: Re-add GMA default panel to iGPU"}},{"before":"345f48275a2a4331edd3ff23ad9fd5b3e848db5b","after":"e935ce180ec1fc62417c13d42f2b6fb822594dd4","ref":"refs/heads/MrChromebox-2405","pushedAt":"2024-06-19T20:10:21.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"cfgs: add/update adl-n cfgs\n\nChange-Id: I96105837db53f984067ec0c5d6603d199bcf3303\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"cfgs: add/update adl-n cfgs"}},{"before":"c8342a6ee0dedecd131f77d9d9f33f322f9f1e7b","after":"345f48275a2a4331edd3ff23ad9fd5b3e848db5b","ref":"refs/heads/MrChromebox-2405","pushedAt":"2024-06-15T17:33:15.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"build: add configs, build scripts, cfbs files for supported boards\n\nChange-Id: I9ba1b3dc448cc447ab83d64f08d14406826fcede\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"build: add configs, build scripts, cfbs files for supported boards"}},{"before":"a6fd5719b61f5fbf5991f2eb9a2fa402c3b64892","after":"c8342a6ee0dedecd131f77d9d9f33f322f9f1e7b","ref":"refs/heads/MrChromebox-2405","pushedAt":"2024-06-14T17:54:18.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"ec sync cleanup\n\nChange-Id: I1bd7678f2a534cb9ee498e7de07c60f2225217e2\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"ec sync cleanup"}},{"before":"86a37a86a3f6a4294793e5380d12a242b8149d5a","after":"a6fd5719b61f5fbf5991f2eb9a2fa402c3b64892","ref":"refs/heads/MrChromebox-2405","pushedAt":"2024-06-12T14:22:37.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"soc/intel/apollolake: Add SoC-specific microcode update check for GLK\n\nWhile both APL and GLK load the CPU microcode from FIT, only GLK\nsupports the PRMRR/SGX feature. When this feature is supported, the\nFIT microcode load will set the msr (0x08b) with the patch id/revision\none less than the revision in the microcode binary. This results in\ncoreboot attempting (and failing) to reload the microcode again in\nramstage. Avoid the microcode reload attempt for GLK by using a SoC-\nspecific microcode update check which accounts for the off-by-1 when\ncomparing versions.\n\nImplementation is based on the one used for SKL and CNL, but modified\nbased on feedback in comments on Gerrit.\n\nTEST=build/boot google/reef (electro) and google/octopus (ampton),\nverify in cbmem console log that CPU microcode update in ramstage is\nskipped due to already being up to date, and that GLK uses the\nSoC-specific check and APL uses the non-specific/general one.\n\nChange-Id: Iab97f23d4388d5057797bb13f585db821c735bd0\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"soc/intel/apollolake: Add SoC-specific microcode update check for GLK"}},{"before":"6d5b0a94cff478e57351e66ace88d632e4b91396","after":"86a37a86a3f6a4294793e5380d12a242b8149d5a","ref":"refs/heads/MrChromebox-2405","pushedAt":"2024-05-15T00:25:40.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"[NOT FOR RELEASE] CREC hacks\n\nChange-Id: Ia61ddfa8f32ef8ff715b095b2ad9039239993ba2\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"[NOT FOR RELEASE] CREC hacks"}},{"before":"6f6434fa92fd689ddc548fe46f1301034b12ea9a","after":"6d5b0a94cff478e57351e66ace88d632e4b91396","ref":"refs/heads/MrChromebox-2405","pushedAt":"2024-05-07T03:01:44.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"build: add configs, build scripts, cfbs files for supported boards\n\nChange-Id: I9ba1b3dc448cc447ab83d64f08d14406826fcede\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"build: add configs, build scripts, cfbs files for supported boards"}},{"before":"80de2f3d79ef8f4acfbc760dda69bc00e7d8c312","after":"6f6434fa92fd689ddc548fe46f1301034b12ea9a","ref":"refs/heads/MrChromebox-2405","pushedAt":"2024-05-07T02:47:05.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"ec/google/chromeec: Re-scope CREC under \\_SB so that the Sync IRQ is accessible\n\nSync IRQ is not accessible under the limited resources of LPCB\nin Windows.\n\nIRQ is accessible under \\_SB or \\_SB.PCI0. However, since the EC\nis not a PCIe device, it makes more sense under \\_SB.\n\nMove to \\_SB so that sync IRQ doesn't cause a Code 12 in Windows\n\nTEST=build+boot google/nocturne to Win11 and verify EC device shows\nup and sync IRQ works for volume buttons in Windows\n\nChange-Id: Ib7d6ef8214e72590851487f62faa96842814db3d\nSigned-off-by: CoolStar <coolstarorganization@gmail.com>","shortMessageHtmlLink":"ec/google/chromeec: Re-scope CREC under \\_SB so that the Sync IRQ is …"}},{"before":null,"after":"80de2f3d79ef8f4acfbc760dda69bc00e7d8c312","ref":"refs/heads/MrChromebox-2405","pushedAt":"2024-05-06T21:56:59.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"ec/google/chromeec: Re-scope CREC under \\_SB so that the Sync IRQ is accessible\n\nSync IRQ is not accessible under the limited resources of LPCB\nin Windows.\n\nIRQ is accessible under \\_SB or \\_SB.PCI0. However, since the EC\nis not a PCIe device, it makes more sense under \\_SB.\n\nMove to \\_SB so that sync IRQ doesn't cause a Code 12 in Windows\n\nTEST=build+boot google/nocturne to Win11 and verify EC device shows\nup and sync IRQ works for volume buttons in Windows\n\nChange-Id: Ib7d6ef8214e72590851487f62faa96842814db3d\nSigned-off-by: CoolStar <coolstarorganization@gmail.com>","shortMessageHtmlLink":"ec/google/chromeec: Re-scope CREC under \\_SB so that the Sync IRQ is …"}},{"before":"0ce8c39f0a084a5a93d76d7fd3d36b0d665149f9","after":"9071e69522e38bef841253dc5970ca6b806d2e55","ref":"refs/heads/MrChromebox-4.22","pushedAt":"2024-04-16T16:18:06.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"MrChromebox","name":"MrChromebox","path":"/MrChromebox","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/948902?s=80&v=4"},"commit":{"message":"mb/google/brya: Enable UFS driver for edk2 payload\n\nSeveral brya-based boards use UFS for storage, so enable the edk2 UFS\ndriver when using the edk2 payload.\n\nTEST=build/boot google/brya (banshee, craaskov), verify internal boot\nmedia functional with edk2 payload.\n\nChange-Id: I3dc018582e974bf73c7668f78da9b81eeb038c01\nSigned-off-by: Matt DeVillier <matt.devillier@gmail.com>","shortMessageHtmlLink":"mb/google/brya: Enable UFS driver for edk2 payload"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"Y3Vyc29yOnYyOpK7MjAyNC0wOS0yMlQyMzoxNTozNS4wMDAwMDBazwAAAAS9aPnY","startCursor":"Y3Vyc29yOnYyOpK7MjAyNC0wOS0yMlQyMzoxNTozNS4wMDAwMDBazwAAAAS9aPnY","endCursor":"Y3Vyc29yOnYyOpK7MjAyNC0wNC0xNlQxNjoxODowNi4wMDAwMDBazwAAAAQyOKIC"}},"title":"Activity · MrChromebox/coreboot"}