From fb0ea9169624e494fb661b5642be682d749f31f6 Mon Sep 17 00:00:00 2001 From: MrTJP Date: Sun, 27 Mar 2022 15:25:12 -0400 Subject: [PATCH] fix: bus converter off by 1 when reading redwires --- .../textures/gui/ic_workbench.png | Bin .../projectred/integration/gatepartbundled.scala | 2 +- .../mrtjp/projectred/integration/gatepartrs.scala | 4 ++++ .../mrtjp/projectred/integration/gatepartseq.scala | 6 ++---- 4 files changed, 7 insertions(+), 5 deletions(-) rename src/{unported/resources/assets/projectred => fabrication/resources/assets/projectred-fabrication}/textures/gui/ic_workbench.png (100%) diff --git a/src/unported/resources/assets/projectred/textures/gui/ic_workbench.png b/src/fabrication/resources/assets/projectred-fabrication/textures/gui/ic_workbench.png similarity index 100% rename from src/unported/resources/assets/projectred/textures/gui/ic_workbench.png rename to src/fabrication/resources/assets/projectred-fabrication/textures/gui/ic_workbench.png diff --git a/src/integration/scala/mrtjp/projectred/integration/gatepartbundled.scala b/src/integration/scala/mrtjp/projectred/integration/gatepartbundled.scala index 2dc942022..7e40dd6ea 100644 --- a/src/integration/scala/mrtjp/projectred/integration/gatepartbundled.scala +++ b/src/integration/scala/mrtjp/projectred/integration/gatepartbundled.scala @@ -380,7 +380,7 @@ class BusConverter extends BundledGatePart(GateType.BUS_CONVERTER) var changed = false val oldRSIn = rsIn - rsIn = if (shape == 0) getRedstoneInput(2)/17 else 0 + rsIn = if (shape == 0) getAnalogRedstoneInput(2) else 0 if (oldRSIn != rsIn) changed = true val oldBIn = bIn diff --git a/src/integration/scala/mrtjp/projectred/integration/gatepartrs.scala b/src/integration/scala/mrtjp/projectred/integration/gatepartrs.scala index 97d016fa8..8e2a3fee5 100644 --- a/src/integration/scala/mrtjp/projectred/integration/gatepartrs.scala +++ b/src/integration/scala/mrtjp/projectred/integration/gatepartrs.scala @@ -119,6 +119,10 @@ abstract class RedstoneGatePart(gateType:GateType) extends GatePart(gateType) wi else calcMaxSignal(ar, true, false) } + def getAnalogRedstoneInput(r:Int):Int = { + (getRedstoneInput(r) + 16) / 17 + } + override def resolveSignal(part:Any, r:Int) = part match { case re:IRedwireEmitter => re.getRedwireSignal(r) diff --git a/src/integration/scala/mrtjp/projectred/integration/gatepartseq.scala b/src/integration/scala/mrtjp/projectred/integration/gatepartseq.scala index cafed2d77..22bd0557c 100644 --- a/src/integration/scala/mrtjp/projectred/integration/gatepartseq.scala +++ b/src/integration/scala/mrtjp/projectred/integration/gatepartseq.scala @@ -696,8 +696,6 @@ class Comparator extends RedstoneGatePart(GateType.COMPARATOR) with INeighborTil if (r == 0) state2&0xF else 0 - def getAnalogInput(r:Int):Int = (getRedstoneInput(r)+16)/17 - def calcInputA:Int = { //TODO comparator calculations may not be accurate anymore @@ -708,7 +706,7 @@ class Comparator extends RedstoneGatePart(GateType.COMPARATOR) with INeighborTil if (state.hasAnalogOutputSignal) return state.getAnalogOutputSignal(world, pos) - var i = getAnalogInput(2) + var i = getAnalogRedstoneInput(2) if (i < 15 && state.isRedstoneConductor(world, pos)) { pos = pos.relative(absDir) @@ -736,7 +734,7 @@ class Comparator extends RedstoneGatePart(GateType.COMPARATOR) with INeighborTil if (list.size == 1) list.get(0) else null } - def calcInput:Int = getAnalogInput(1)<<4|calcInputA<<8|getAnalogInput(3)<<12 + def calcInput:Int = getAnalogRedstoneInput(1)<<4|calcInputA<<8|getAnalogRedstoneInput(3)<<12 def digitize(analog:Int):Int = { var digital = 0