Split by warp tile in Hopper matmul scheduler

[jacobhinkle]

Our current Hopper matmul scheduler ignores the warp_tile option and only splits the CTA tile by the instruction tile. This means that currently we fail to execute a kernel compiled with this valid config:

MMA macro: Hopper_64_8_16
CircularBufferOptions:
  circular_buffer_smem_write: true
  circular_buffer_smem_read: true
  smem_circular_buffer_stage: 3
  smem_circular_buffer_prefetch_gap: 1
SupportedVectorization:
  a: 8
  b: 8
  epilogue: 8
MatMulTileOptions: warp tile [64, 64, 32], CTA tile [128, 128, 32]
Async global mem load: true
Indexing mode: int32_t
Tile rasterization order: row-major
Grid swizzle factor: 1
Cluster dimensions: 2 1 1
Use shared memory epilogue: 1
Promote re-use of prologue shared memory: 0
Split-K factor: 8

The error we see is

RuntimeError: INTERNAL ASSERT FAILED at "/opt/pytorch/nvfuser/csrc/runtime/executor_params.cpp":30, please report a bug with repro script to NVFuser at https://github.com/NVIDIA/Fuser/issues. Selected invalid number of threads for cuda: 4224

We should change our scheduling to instead first split by warp tile and to parallelize TIDy on the cta/warp split instead of cta/instr split. In this way, we can still use large tiles along with smaller instructions without using far too many warps.