From 8e0f479f54e22f05849bfb5f27517a5f50ae9d04 Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Sat, 11 Dec 2021 09:53:18 -0300 Subject: [PATCH] ghdl: added a more concise alternative --- ghdl-yosys/Makefile | 9 ++++++++ ghdl-yosys/vhdl1.sh | 22 ++++++++++++++++++ ghdl-yosys/vlog1.sh | 22 ++++++++++++++++++ ghdl/vhdl.sh | 37 ++++++++++++++++++++++++++----- openflow/Makefile | 11 --------- openflow/mix.sh | 54 --------------------------------------------- 6 files changed, 85 insertions(+), 70 deletions(-) create mode 100644 ghdl-yosys/Makefile create mode 100644 ghdl-yosys/vhdl1.sh create mode 100644 ghdl-yosys/vlog1.sh delete mode 100644 openflow/Makefile delete mode 100644 openflow/mix.sh diff --git a/ghdl-yosys/Makefile b/ghdl-yosys/Makefile new file mode 100644 index 0000000..0e208ff --- /dev/null +++ b/ghdl-yosys/Makefile @@ -0,0 +1,9 @@ +#!/usr/bin/make + +COMMAND=bash + +vlog1 vlog2 vhdl1 vhdl2: + $(COMMAND) $@.sh + +clean: + rm -fr *.asc *.bit *.cf *.edif *.json *.pcf diff --git a/ghdl-yosys/vhdl1.sh b/ghdl-yosys/vhdl1.sh new file mode 100644 index 0000000..3671517 --- /dev/null +++ b/ghdl-yosys/vhdl1.sh @@ -0,0 +1,22 @@ +#!/bin/bash + +set -e + +DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" +HDL=../resources/mix +CONSTRAINT=../../resources/constraints/icestick + +rm -fr *.cf *.json + +VHDL_FILES=$HDL/top.vhdl +VLOG_FILES=$HDL/blink.v + +$DOCKER hdlc/ghdl:yosys yosys -Q -m ghdl -p " +ghdl $VHDL_FILES -e; +read_verilog $VLOG_FILES; +synth_ice40 -top Top -json blink.json +" + +cat $CONSTRAINT/clk.pcf $CONSTRAINT/led.pcf > icestick.pcf +$DOCKER hdlc/nextpnr:ice40 nextpnr-ice40 --json blink.json --hx8k --package tq144:4k --pcf icestick.pcf --asc blink.asc +$DOCKER hdlc/icestorm icepack blink.asc blink.bit diff --git a/ghdl-yosys/vlog1.sh b/ghdl-yosys/vlog1.sh new file mode 100644 index 0000000..5bb7fa3 --- /dev/null +++ b/ghdl-yosys/vlog1.sh @@ -0,0 +1,22 @@ +#!/bin/bash + +set -e + +DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" +HDL=../resources/mix +CONSTRAINT=../../resources/constraints/icestick + +rm -fr *.cf *.json + +VHDL_FILES=$HDL/blink.vhdl +VLOG_FILES=$HDL/top.v + +$DOCKER hdlc/ghdl:yosys yosys -Q -m ghdl -p " +ghdl $VHDL_FILES -e; +read_verilog $VLOG_FILES; +synth_ice40 -top Top -json blink.json +" + +cat $CONSTRAINT/clk.pcf $CONSTRAINT/led.pcf > icestick.pcf +$DOCKER hdlc/nextpnr:ice40 nextpnr-ice40 --json blink.json --hx8k --package tq144:4k --pcf icestick.pcf --asc blink.asc +$DOCKER hdlc/icestorm icepack blink.asc blink.bit diff --git a/ghdl/vhdl.sh b/ghdl/vhdl.sh index 99ea6b6..215d6d5 100644 --- a/ghdl/vhdl.sh +++ b/ghdl/vhdl.sh @@ -2,11 +2,38 @@ set -e -FLAGS="--std=08 -fsynopsys -fexplicit -frelaxed" +DIR=../resources/vhdl -ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink.vhdl -ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink_pkg.vhdl -ghdl -a $FLAGS ../resources/vhdl/top.vhdl +FLAGS="--std=08 -fsynopsys -fexplicit -frelaxed" GENERICS="-gBOO=true -gINT=255 -gLOG='1' -gVEC="11111111" -gCHR='Z' -gSTR="WXYZ" -gSKIP_REA=1" -ghdl --synth $FLAGS $GENERICS Top ARCH_SEL + +############################################################################### +# Alternative 1 +############################################################################### + +# This alternative is better to specify particular options per file + +ghdl -a $FLAGS --work=blink_lib $DIR/blink.vhdl +ghdl -a $FLAGS --work=blink_lib $DIR/blink_pkg.vhdl +ghdl -a $FLAGS $DIR/top.vhdl + +# --out=raw-vhdl generate a VHDL 93 netlist + +ghdl synth $FLAGS --out=raw-vhdl $GENERICS Top ARCH_SEL + +# This alternative creates .cf files due the ghdl -a +rm -fr *.cf + +############################################################################### +# Alternative 2 +############################################################################### + +# This alternative is more concise + +# --work= applies to the following files +# --out=verilog generate a Verilog netlist + +ghdl synth $FLAGS --out=verilog $GENERICS \ + --work=blink_lib $DIR/blink.vhdl $DIR/blink_pkg.vhdl \ + --work=work $DIR/top.vhdl -e Top ARCH_SEL diff --git a/openflow/Makefile b/openflow/Makefile deleted file mode 100644 index 363b782..0000000 --- a/openflow/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -#!/usr/bin/make - -DOCKER_CMD=docker run --rm -it -v $$HOME:$$HOME -w $$PWD ghdl/synth:beta - -COMMAND=bash - -mix: - $(COMMAND) $@.sh - -clean: - rm -fr *.cf *.edif diff --git a/openflow/mix.sh b/openflow/mix.sh deleted file mode 100644 index 2ecf68e..0000000 --- a/openflow/mix.sh +++ /dev/null @@ -1,54 +0,0 @@ -#!/bin/bash - -set -e - -DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" - -FLAGS="--std=08 -fsynopsys -fexplicit -frelaxed" - -function msg () { tput setaf 6; echo "$1"; tput sgr0; } - -function synth () { -$DOCKER hdlc/ghdl:yosys /bin/bash -c " -yosys -Q -m ghdl -p ' -ghdl $FLAGS $1 -e; -read_verilog $2; -synth_ice40 -top $3 -json blink.json -'" > /dev/null -} - -############################################################################### - -msg "* Verilog Top" -synth "../resources/mix/blink.vhdl" "../resources/mix/top.v" "Top" - -msg "* VHDL Top" -synth "../resources/mix/top.vhdl" "../resources/mix/blink.v" "Top" - -############################################################################### - -msg "* Verilog Top (alternative)" - -$DOCKER hdlc/ghdl:yosys /bin/bash -c " -ghdl -a ../resources/mix/blink.vhdl -yosys -Q -m ghdl -p ' -ghdl Blink; -read_verilog ../resources/mix/top.v; -synth_ice40 -top Top -json blink.json -'" > /dev/null - -rm -fr *.cf *.edif *.json - -msg "* VHDL Top (alternative)" - -$DOCKER hdlc/ghdl:yosys /bin/bash -c " -ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink.vhdl -ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink_pkg.vhdl -ghdl -a $FLAGS ../resources/vhdl/top.vhdl -yosys -Q -m ghdl -p ' -ghdl $FLAGS Top; -synth_xilinx -family xc7; -write_edif -pvector bra yosys.edif -'" > /dev/null - -rm -fr *.cf *.edif *.json