From 5295f81624960d4b1d8bf67f7b1433763fda916d Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Fri, 26 Nov 2021 08:04:12 -0300 Subject: [PATCH 01/23] Added the hdl directory with VHDL files --- hdl/blink.vhdl | 39 +++++++++++++++++++++++++++++++++++++++ hdl/blink_pkg.vhdl | 17 +++++++++++++++++ hdl/top.vhdl | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+) create mode 100644 hdl/blink.vhdl create mode 100644 hdl/blink_pkg.vhdl create mode 100644 hdl/top.vhdl diff --git a/hdl/blink.vhdl b/hdl/blink.vhdl new file mode 100644 index 0000000..1b57f1f --- /dev/null +++ b/hdl/blink.vhdl @@ -0,0 +1,39 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity Blink is + generic ( + FREQ : positive:=25e6; + SECS : positive:=1 + ); + port ( + clk_i : in std_logic; + led_o : out std_logic + ); +end entity Blink; + +architecture RTL of Blink is + + constant DIV : positive:=FREQ*SECS; + + signal led : std_logic; + signal cnt : natural range 0 to DIV-1:=0; + +begin + + blink_p: + process (clk_i) + begin + if rising_edge(clk_i) then + if cnt=DIV-1 then + cnt <= 0; + led <= not(led); + else + cnt <= cnt+1; + end if; + end if; + end process blink_p; + + led_o <= led; + +end architecture RTL; diff --git a/hdl/blink_pkg.vhdl b/hdl/blink_pkg.vhdl new file mode 100644 index 0000000..7956fc3 --- /dev/null +++ b/hdl/blink_pkg.vhdl @@ -0,0 +1,17 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +package blink_pkg is + + component Blink is + generic ( + FREQ : positive:=25e6; + SECS : positive:=1 + ); + port ( + clk_i : in std_logic; + led_o : out std_logic + ); + end component Blink; + +end package blink_pkg; diff --git a/hdl/top.vhdl b/hdl/top.vhdl new file mode 100644 index 0000000..e8a87b5 --- /dev/null +++ b/hdl/top.vhdl @@ -0,0 +1,38 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library blink_lib; +use blink_lib.blink_pkg.all; + +entity Top is + generic ( + BOO : boolean:=FALSE; + INT : integer:=0; + LOG : std_logic:='0'; + VEC : std_logic_vector(7 downto 0):="00000000"; + STR : string:="ABCD"; + REA : real:=0.0 + ); + port ( + clk_i : in std_logic; + led_o : out std_logic + ); +end entity Top; + +architecture EMPTY of Top is +begin + + led_o <= '1'; + +end architecture EMPTY; + +architecture VIVADO of Top is +begin + + inst: if BOO=TRUE and INT=255 and LOG='1' and VEC="11111111" and STR="WXYZ" and REA=1.1 generate + blink_i: Blink + generic map (FREQ => 125e6, SECS => 1) + port map (clk_i => clk_i, led_o => led_o); + end generate inst; + +end architecture VIVADO; From d31ec038fd1d528cc8cc6daa4d5d50955518c36e Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Fri, 26 Nov 2021 08:05:00 -0300 Subject: [PATCH 02/23] vivado: rewritten (vlog.tcl is WIP) --- vivado/Makefile | 4 +++- vivado/params.tcl | 30 ------------------------------ vivado/prog.tcl | 6 ++++++ vivado/vhdl.tcl | 32 ++++++++++++++++++++++++++++++++ vivado/{flow.tcl => vlog.tcl} | 12 ++++++++---- 5 files changed, 49 insertions(+), 35 deletions(-) delete mode 100644 vivado/params.tcl create mode 100644 vivado/prog.tcl create mode 100644 vivado/vhdl.tcl rename vivado/{flow.tcl => vlog.tcl} (51%) diff --git a/vivado/Makefile b/vivado/Makefile index 075452b..3b8e4ba 100644 --- a/vivado/Makefile +++ b/vivado/Makefile @@ -2,7 +2,9 @@ COMMAND=vivado -mode batch -notrace -quiet -source -flow params: +all: vhdl vlog + +vhdl vlog prog: $(COMMAND) $@.tcl version: diff --git a/vivado/params.tcl b/vivado/params.tcl deleted file mode 100644 index 16eb079..0000000 --- a/vivado/params.tcl +++ /dev/null @@ -1,30 +0,0 @@ -create_project -force example - -set_property "part" xc7z010-1-clg400 [current_project] - -# When specifying binary values for boolean or std_logic VHDL generic types, -# you must specify the value using the Verilog bit format, rather than -# standard VHDL format. - -add_files ../resources/verilog/parameters.v -set_property top Params [current_fileset] -set_property "generic" "BOO=1 INT=255 LOG=1'b1 VEC=8'b11111111 STR=WXYZ REA=1.1" -objects [get_filesets sources_1] - -reset_run synth_1 -launch_runs synth_1 -wait_on_run synth_1 - -# To avoid re-synthesis of the Verilog version -remove_files [get_files] - -add_files ../resources/vhdl/generics.vhdl -set_property top Params [current_fileset] -# NOTE: support to specify a REAL generic (VHDL) was added into the Vivado 2020.2 version -# https://forums.xilinx.com/t5/Vivado-TCL-Community/How-to-specify-a-REAL-generic-in-Vivado/m-p/1209088#M9581 -set_property "generic" "BOO=true INT=255 LOG=1'b1 VEC=8'b11111111 STR=WXYZ REA=1.1" -objects [get_filesets sources_1] - -reset_run synth_1 -launch_runs synth_1 -wait_on_run synth_1 - -close_project diff --git a/vivado/prog.tcl b/vivado/prog.tcl new file mode 100644 index 0000000..46bcc58 --- /dev/null +++ b/vivado/prog.tcl @@ -0,0 +1,6 @@ +if { [ catch { open_hw_manager } ] } { open_hw } +connect_hw_server +open_hw_target +set obj [lindex [get_hw_devices [current_hw_device]] 0] +set_property PROGRAM.FILE project.bit $obj +program_hw_devices $obj diff --git a/vivado/vhdl.tcl b/vivado/vhdl.tcl new file mode 100644 index 0000000..d895056 --- /dev/null +++ b/vivado/vhdl.tcl @@ -0,0 +1,32 @@ +create_project -force vhdl-project + +set_property "part" xc7z010-1-clg400 [current_project] + +add_files ../hdl/blink.vhdl +set_property library blink_lib [get_files ../hdl/blink.vhdl] + +add_files ../hdl/blink_pkg.vhdl +set_property library blink_lib [get_files ../hdl/blink_pkg.vhdl] + +add_files ../hdl/top.vhdl +add_files ../resources/constraints/zybo/clk.xdc +add_files ../resources/constraints/zybo/led.xdc + +set_property top Top [current_fileset] +set_property top_arch VIVADO [current_fileset] + +# NOTE: support to specify a REAL generic was added into the Vivado 2020.2 version +# https://forums.xilinx.com/t5/Vivado-TCL-Community/How-to-specify-a-REAL-generic-in-Vivado/m-p/1209088#M9581 +set_property "generic" "BOO=true INT=255 LOG=1'b1 VEC=8'b11111111 STR=WXYZ REA=1.1" -objects [get_filesets sources_1] + +reset_run synth_1 +launch_runs synth_1 +wait_on_run synth_1 + +launch_runs impl_1 +wait_on_run impl_1 + +open_run impl_1 +write_bitstream -force project + +close_project diff --git a/vivado/flow.tcl b/vivado/vlog.tcl similarity index 51% rename from vivado/flow.tcl rename to vivado/vlog.tcl index 35fee20..aeac675 100644 --- a/vivado/flow.tcl +++ b/vivado/vlog.tcl @@ -1,12 +1,16 @@ -create_project -force example +create_project -force vlog-project set_property "part" xc7z010-1-clg400 [current_project] -add_files ../resources/vhdl/blink.vhdl +add_files ../hdl/blink.v + +add_files ../hdl/top.v add_files ../resources/constraints/zybo/clk.xdc add_files ../resources/constraints/zybo/led.xdc -set_property top Blink [current_fileset] +set_property top Top [current_fileset] + +set_property "generic" "BOO=1 INT=255 LOG=1'b1 VEC=8'b11111111 STR=WXYZ REA=1.1" -objects [get_filesets sources_1] reset_run synth_1 launch_runs synth_1 @@ -16,6 +20,6 @@ launch_runs impl_1 wait_on_run impl_1 open_run impl_1 -write_bitstream -force example +write_bitstream -force project close_project From b0a7c0b7bb307540a974cc43120074fd82ff9fa4 Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Fri, 26 Nov 2021 08:05:26 -0300 Subject: [PATCH 03/23] hdl: added Verilog files (WIP) --- hdl/blink.v | 25 +++++++++++++++++++++++++ hdl/top.v | 20 ++++++++++++++++++++ 2 files changed, 45 insertions(+) create mode 100644 hdl/blink.v create mode 100644 hdl/top.v diff --git a/hdl/blink.v b/hdl/blink.v new file mode 100644 index 0000000..ba44745 --- /dev/null +++ b/hdl/blink.v @@ -0,0 +1,25 @@ +module Blink #( + parameter FREQ = 25000000, + parameter SECS = 1 +)( + input wire clk_i, + output wire led_o +); + + localparam DIV = FREQ*SECS; + + reg led; + reg [$clog2(DIV)-1:0] cnt = 0; + + always @(posedge clk_i) begin + if (cnt == DIV-1) begin + cnt = 0; + led <= ~led; + end else begin + cnt = cnt + 1; + end + end + + assign led_o = led; + +endmodule diff --git a/hdl/top.v b/hdl/top.v new file mode 100644 index 0000000..7f761f4 --- /dev/null +++ b/hdl/top.v @@ -0,0 +1,20 @@ +`define ARCH "EMPTY" + +module Top #( + parameter BOO = 0, + parameter INT = 0, + parameter LOG = 1'b0, + parameter VEC = 8'd0, + parameter STR = "ABCD", + parameter REA = 0.0 +)( + input wire clk_i, + output wire led_o +); + +localparam FREQ = 50000000; + +Blink #(.FREQ (FREQ), .SECS (1)) + dut (.clk_i (clk_i), .led_o (led_o)); + +endmodule From 340f4f624b946e39352bf31777897e481e266e14 Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Fri, 26 Nov 2021 19:13:38 -0300 Subject: [PATCH 04/23] vivado: finished vlog.tcl --- hdl/top.v | 34 +++++++++++++++++++++++----------- vivado/Makefile | 2 +- vivado/prog.tcl | 8 ++++++++ vivado/vhdl.tcl | 1 + vivado/vlog.tcl | 4 ++++ 5 files changed, 37 insertions(+), 12 deletions(-) diff --git a/hdl/top.v b/hdl/top.v index 7f761f4..057afb2 100644 --- a/hdl/top.v +++ b/hdl/top.v @@ -1,20 +1,32 @@ -`define ARCH "EMPTY" +`include "header1.vh" +`include "header2.vh" + +`define FREQ `DEFAULT_FREQ +`define SECS `DEFAULT_SECS module Top #( - parameter BOO = 0, - parameter INT = 0, - parameter LOG = 1'b0, - parameter VEC = 8'd0, - parameter STR = "ABCD", - parameter REA = 0.0 + parameter BOO = 0, + parameter INT = 0, + parameter LOG = 1'b0, + parameter VEC = 8'd0, + parameter STR = "ABCD", + parameter REA = 0.0 )( - input wire clk_i, - output wire led_o + input wire clk_i, + output wire led_o ); -localparam FREQ = 50000000; +`ifdef VIVADO -Blink #(.FREQ (FREQ), .SECS (1)) + generate if (BOO==1 & INT==255 & LOG==1'b1 & VEC==8'b11111111 & STR=="WXYZ" & REA==1.1) + Blink #(.FREQ (`FREQ), .SECS (`SECS)) dut (.clk_i (clk_i), .led_o (led_o)); + endgenerate + +`else + + assign led_o = 1'b1; + +`endif endmodule diff --git a/vivado/Makefile b/vivado/Makefile index 3b8e4ba..2745953 100644 --- a/vivado/Makefile +++ b/vivado/Makefile @@ -4,7 +4,7 @@ COMMAND=vivado -mode batch -notrace -quiet -source all: vhdl vlog -vhdl vlog prog: +vhdl vlog prog detect: $(COMMAND) $@.tcl version: diff --git a/vivado/prog.tcl b/vivado/prog.tcl index 46bcc58..fa9c537 100644 --- a/vivado/prog.tcl +++ b/vivado/prog.tcl @@ -1,6 +1,14 @@ if { [ catch { open_hw_manager } ] } { open_hw } connect_hw_server open_hw_target + +puts "* Devices detected in the JTAG chain" +puts [get_hw_devices] + +puts "* Programming the FPGA" + set obj [lindex [get_hw_devices [current_hw_device]] 0] set_property PROGRAM.FILE project.bit $obj program_hw_devices $obj + +puts "* Done" diff --git a/vivado/vhdl.tcl b/vivado/vhdl.tcl index d895056..7603861 100644 --- a/vivado/vhdl.tcl +++ b/vivado/vhdl.tcl @@ -13,6 +13,7 @@ add_files ../resources/constraints/zybo/clk.xdc add_files ../resources/constraints/zybo/led.xdc set_property top Top [current_fileset] + set_property top_arch VIVADO [current_fileset] # NOTE: support to specify a REAL generic was added into the Vivado 2020.2 version diff --git a/vivado/vlog.tcl b/vivado/vlog.tcl index aeac675..49f7291 100644 --- a/vivado/vlog.tcl +++ b/vivado/vlog.tcl @@ -10,6 +10,10 @@ add_files ../resources/constraints/zybo/led.xdc set_property top Top [current_fileset] +set_property verilog_define {VIVADO=1 FREQ=125000000} [current_fileset] + +set_property "include_dirs" "../resources/verilog/path1 ../resources/verilog/path2" [current_fileset] + set_property "generic" "BOO=1 INT=255 LOG=1'b1 VEC=8'b11111111 STR=WXYZ REA=1.1" -objects [get_filesets sources_1] reset_run synth_1 From 24c0f56e8229d4f90d06bc041cc046869f7a5686 Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Fri, 26 Nov 2021 20:06:16 -0300 Subject: [PATCH 05/23] resources: submodule updated --- .gitmodules | 2 +- resources | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 362bc8a..1072404 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,3 @@ [submodule "resources"] path = resources - url = https://github.com/PyFPGA/resources + url = https://github.com/PyFPGA/resources.git diff --git a/resources b/resources index c6b2a78..303ecb7 160000 --- a/resources +++ b/resources @@ -1 +1 @@ -Subproject commit c6b2a782e78e4ca3628ef81d3665a780628600d9 +Subproject commit 303ecb7a850a3d706de3aa8f861437fd6f851d51 From 45500a49235a37b64e33f910f3d079652216d7a1 Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Fri, 26 Nov 2021 20:12:15 -0300 Subject: [PATCH 06/23] hdl: removed (content already in the 'resources' submodule) --- hdl/blink.v | 25 ------------------------- hdl/blink.vhdl | 39 --------------------------------------- hdl/blink_pkg.vhdl | 17 ----------------- hdl/top.v | 32 -------------------------------- hdl/top.vhdl | 38 -------------------------------------- vivado/vhdl.tcl | 10 +++++----- vivado/vlog.tcl | 4 ++-- 7 files changed, 7 insertions(+), 158 deletions(-) delete mode 100644 hdl/blink.v delete mode 100644 hdl/blink.vhdl delete mode 100644 hdl/blink_pkg.vhdl delete mode 100644 hdl/top.v delete mode 100644 hdl/top.vhdl diff --git a/hdl/blink.v b/hdl/blink.v deleted file mode 100644 index ba44745..0000000 --- a/hdl/blink.v +++ /dev/null @@ -1,25 +0,0 @@ -module Blink #( - parameter FREQ = 25000000, - parameter SECS = 1 -)( - input wire clk_i, - output wire led_o -); - - localparam DIV = FREQ*SECS; - - reg led; - reg [$clog2(DIV)-1:0] cnt = 0; - - always @(posedge clk_i) begin - if (cnt == DIV-1) begin - cnt = 0; - led <= ~led; - end else begin - cnt = cnt + 1; - end - end - - assign led_o = led; - -endmodule diff --git a/hdl/blink.vhdl b/hdl/blink.vhdl deleted file mode 100644 index 1b57f1f..0000000 --- a/hdl/blink.vhdl +++ /dev/null @@ -1,39 +0,0 @@ -library IEEE; -use IEEE.std_logic_1164.all; - -entity Blink is - generic ( - FREQ : positive:=25e6; - SECS : positive:=1 - ); - port ( - clk_i : in std_logic; - led_o : out std_logic - ); -end entity Blink; - -architecture RTL of Blink is - - constant DIV : positive:=FREQ*SECS; - - signal led : std_logic; - signal cnt : natural range 0 to DIV-1:=0; - -begin - - blink_p: - process (clk_i) - begin - if rising_edge(clk_i) then - if cnt=DIV-1 then - cnt <= 0; - led <= not(led); - else - cnt <= cnt+1; - end if; - end if; - end process blink_p; - - led_o <= led; - -end architecture RTL; diff --git a/hdl/blink_pkg.vhdl b/hdl/blink_pkg.vhdl deleted file mode 100644 index 7956fc3..0000000 --- a/hdl/blink_pkg.vhdl +++ /dev/null @@ -1,17 +0,0 @@ -library IEEE; -use IEEE.std_logic_1164.all; - -package blink_pkg is - - component Blink is - generic ( - FREQ : positive:=25e6; - SECS : positive:=1 - ); - port ( - clk_i : in std_logic; - led_o : out std_logic - ); - end component Blink; - -end package blink_pkg; diff --git a/hdl/top.v b/hdl/top.v deleted file mode 100644 index 057afb2..0000000 --- a/hdl/top.v +++ /dev/null @@ -1,32 +0,0 @@ -`include "header1.vh" -`include "header2.vh" - -`define FREQ `DEFAULT_FREQ -`define SECS `DEFAULT_SECS - -module Top #( - parameter BOO = 0, - parameter INT = 0, - parameter LOG = 1'b0, - parameter VEC = 8'd0, - parameter STR = "ABCD", - parameter REA = 0.0 -)( - input wire clk_i, - output wire led_o -); - -`ifdef VIVADO - - generate if (BOO==1 & INT==255 & LOG==1'b1 & VEC==8'b11111111 & STR=="WXYZ" & REA==1.1) - Blink #(.FREQ (`FREQ), .SECS (`SECS)) - dut (.clk_i (clk_i), .led_o (led_o)); - endgenerate - -`else - - assign led_o = 1'b1; - -`endif - -endmodule diff --git a/hdl/top.vhdl b/hdl/top.vhdl deleted file mode 100644 index e8a87b5..0000000 --- a/hdl/top.vhdl +++ /dev/null @@ -1,38 +0,0 @@ -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -library blink_lib; -use blink_lib.blink_pkg.all; - -entity Top is - generic ( - BOO : boolean:=FALSE; - INT : integer:=0; - LOG : std_logic:='0'; - VEC : std_logic_vector(7 downto 0):="00000000"; - STR : string:="ABCD"; - REA : real:=0.0 - ); - port ( - clk_i : in std_logic; - led_o : out std_logic - ); -end entity Top; - -architecture EMPTY of Top is -begin - - led_o <= '1'; - -end architecture EMPTY; - -architecture VIVADO of Top is -begin - - inst: if BOO=TRUE and INT=255 and LOG='1' and VEC="11111111" and STR="WXYZ" and REA=1.1 generate - blink_i: Blink - generic map (FREQ => 125e6, SECS => 1) - port map (clk_i => clk_i, led_o => led_o); - end generate inst; - -end architecture VIVADO; diff --git a/vivado/vhdl.tcl b/vivado/vhdl.tcl index 7603861..6085da7 100644 --- a/vivado/vhdl.tcl +++ b/vivado/vhdl.tcl @@ -2,13 +2,13 @@ create_project -force vhdl-project set_property "part" xc7z010-1-clg400 [current_project] -add_files ../hdl/blink.vhdl -set_property library blink_lib [get_files ../hdl/blink.vhdl] +add_files ../resources/vhdl/blink.vhdl +set_property library blink_lib [get_files ../resources/vhdl/blink.vhdl] -add_files ../hdl/blink_pkg.vhdl -set_property library blink_lib [get_files ../hdl/blink_pkg.vhdl] +add_files ../resources/vhdl/blink_pkg.vhdl +set_property library blink_lib [get_files ../resources/vhdl/blink_pkg.vhdl] -add_files ../hdl/top.vhdl +add_files ../resources/vhdl/top.vhdl add_files ../resources/constraints/zybo/clk.xdc add_files ../resources/constraints/zybo/led.xdc diff --git a/vivado/vlog.tcl b/vivado/vlog.tcl index 49f7291..6c4ea87 100644 --- a/vivado/vlog.tcl +++ b/vivado/vlog.tcl @@ -2,9 +2,9 @@ create_project -force vlog-project set_property "part" xc7z010-1-clg400 [current_project] -add_files ../hdl/blink.v +add_files ../resources/verilog/blink.v -add_files ../hdl/top.v +add_files ../resources/verilog/top.v add_files ../resources/constraints/zybo/clk.xdc add_files ../resources/constraints/zybo/led.xdc From 9c3bd9801e217c5a4a51035b2ddb54ae1604257b Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Fri, 26 Nov 2021 20:42:00 -0300 Subject: [PATCH 07/23] ghdl: added a VHDL example --- ghdl/Makefile | 11 +++++++++++ ghdl/vhdl.sh | 14 ++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 ghdl/Makefile create mode 100644 ghdl/vhdl.sh diff --git a/ghdl/Makefile b/ghdl/Makefile new file mode 100644 index 0000000..643169c --- /dev/null +++ b/ghdl/Makefile @@ -0,0 +1,11 @@ +#!/usr/bin/make + +DOCKER_CMD=docker run --rm -it -v $$HOME:$$HOME -w $$PWD ghdl/synth:beta + +COMMAND=bash + +vhdl: + $(DOCKER_CMD) $(COMMAND) $@.sh + +clean: + rm -fr *.cf diff --git a/ghdl/vhdl.sh b/ghdl/vhdl.sh new file mode 100644 index 0000000..4928655 --- /dev/null +++ b/ghdl/vhdl.sh @@ -0,0 +1,14 @@ +#!/bin/bash + +set -e + +FLAGS="--std=08 -fsynopsys -fexplicit -frelaxed" + +ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink.vhdl +ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink_pkg.vhdl +ghdl -a $FLAGS ../resources/vhdl/top.vhdl +ghdl --synth $FLAGS -gBOO=true -gINT=255 -gLOG=\'1\' -gSTR="WXYZ" -gVEC="11111111" Top GHDL + +## -gREA=1.1 -> unhandled override for generic "rea" + + From 12d3c33dc264e70dd8f2f1120f4e738fb4bb7842 Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Sun, 28 Nov 2021 14:01:57 -0300 Subject: [PATCH 08/23] resources: submodule updated --- resources | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/resources b/resources index 303ecb7..fe72398 160000 --- a/resources +++ b/resources @@ -1 +1 @@ -Subproject commit 303ecb7a850a3d706de3aa8f861437fd6f851d51 +Subproject commit fe723989b2a3ca2c4c8bdd5f57c460e1dba1281a From 82a7744bedbbd30b7f59f7e5d04c21438f218961 Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Sun, 28 Nov 2021 14:03:24 -0300 Subject: [PATCH 09/23] ghdl: added the check of a CHARACTER generic and a README.md file with notes --- ghdl/README.md | 7 +++++++ ghdl/vhdl.sh | 6 ++---- 2 files changed, 9 insertions(+), 4 deletions(-) create mode 100644 ghdl/README.md diff --git a/ghdl/README.md b/ghdl/README.md new file mode 100644 index 0000000..8f6da20 --- /dev/null +++ b/ghdl/README.md @@ -0,0 +1,7 @@ +# Notes about GHDL + +> Last update: Nov 2021 + +* Support to specify a REAL generic is not working + * unhandled override for generic "rea" + * As a workaround, I set SKIP_REA diff --git a/ghdl/vhdl.sh b/ghdl/vhdl.sh index 4928655..99ea6b6 100644 --- a/ghdl/vhdl.sh +++ b/ghdl/vhdl.sh @@ -7,8 +7,6 @@ FLAGS="--std=08 -fsynopsys -fexplicit -frelaxed" ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink.vhdl ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink_pkg.vhdl ghdl -a $FLAGS ../resources/vhdl/top.vhdl -ghdl --synth $FLAGS -gBOO=true -gINT=255 -gLOG=\'1\' -gSTR="WXYZ" -gVEC="11111111" Top GHDL - -## -gREA=1.1 -> unhandled override for generic "rea" - +GENERICS="-gBOO=true -gINT=255 -gLOG='1' -gVEC="11111111" -gCHR='Z' -gSTR="WXYZ" -gSKIP_REA=1" +ghdl --synth $FLAGS $GENERICS Top ARCH_SEL From ca96bbc5060014b9d90696860ee3277779a5cf7b Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Sun, 28 Nov 2021 14:04:26 -0300 Subject: [PATCH 10/23] vivado: added the check of a CHARACTER generic and a README.md file with notes --- vivado/README.md | 14 ++++++++++++++ vivado/vhdl.tcl | 8 ++++---- 2 files changed, 18 insertions(+), 4 deletions(-) create mode 100644 vivado/README.md diff --git a/vivado/README.md b/vivado/README.md new file mode 100644 index 0000000..056392d --- /dev/null +++ b/vivado/README.md @@ -0,0 +1,14 @@ +# Notes about Vivado + +> Last update: Vivado 2021.2 + +* FREQ=125MHz to match the employed clock of the ZYBO. + +VHDL: +* Support to specify a REAL generic was added/fixed in the Vivado 2020.2 version + * https://forums.xilinx.com/t5/Vivado-TCL-Community/How-to-specify-a-REAL-generic-in-Vivado/m-p/1209088#M9581 +* Specify an architecture is supported, but not working + * https://support.xilinx.com/s/question/0D52E00006r9kHiSAI/specify-a-vhdl-architecture-seems-not-working + * As a workaround, I set SKIP_ARCH +* Values are specified following Verilog notation. + * In case of character, is needed to specify the ASCII value diff --git a/vivado/vhdl.tcl b/vivado/vhdl.tcl index 6085da7..29d6840 100644 --- a/vivado/vhdl.tcl +++ b/vivado/vhdl.tcl @@ -13,12 +13,12 @@ add_files ../resources/constraints/zybo/clk.xdc add_files ../resources/constraints/zybo/led.xdc set_property top Top [current_fileset] +set_property top_arch ARCH_SEL [current_fileset] -set_property top_arch VIVADO [current_fileset] +set GENERICS "FREQ=125000000 BOO=true INT=255 LOG=1'b1 VEC=8'b11111111 CHR=8'd90 STR=WXYZ REA=1.1 SKIP_ARCH=1" +set_property "generic" $GENERICS -objects [get_filesets sources_1] -# NOTE: support to specify a REAL generic was added into the Vivado 2020.2 version -# https://forums.xilinx.com/t5/Vivado-TCL-Community/How-to-specify-a-REAL-generic-in-Vivado/m-p/1209088#M9581 -set_property "generic" "BOO=true INT=255 LOG=1'b1 VEC=8'b11111111 STR=WXYZ REA=1.1" -objects [get_filesets sources_1] +set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1] reset_run synth_1 launch_runs synth_1 From 39b6fbe0a8e7a993ecb0916435b11655aeb67d78 Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Sun, 28 Nov 2021 16:47:05 -0300 Subject: [PATCH 11/23] resources: submodule updated --- resources | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/resources b/resources index fe72398..f69243b 160000 --- a/resources +++ b/resources @@ -1 +1 @@ -Subproject commit fe723989b2a3ca2c4c8bdd5f57c460e1dba1281a +Subproject commit f69243b28ddd07f9c8d4ffb1eabe4c3c257d4b39 From c4e9629bfda2a49cfb2a7fb5191db1826e4e01cc Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Sun, 28 Nov 2021 16:48:08 -0300 Subject: [PATCH 12/23] yosys: added a Verilog example --- yosys/Makefile | 11 +++++++++++ yosys/README.md | 6 ++++++ yosys/vlog.sh | 13 +++++++++++++ 3 files changed, 30 insertions(+) create mode 100644 yosys/Makefile create mode 100644 yosys/README.md create mode 100644 yosys/vlog.sh diff --git a/yosys/Makefile b/yosys/Makefile new file mode 100644 index 0000000..6b84458 --- /dev/null +++ b/yosys/Makefile @@ -0,0 +1,11 @@ +#!/usr/bin/make + +DOCKER_CMD=docker run --rm -it -v $$HOME:$$HOME -w $$PWD ghdl/synth:beta + +COMMAND=bash + +vlog vhdl: + $(DOCKER_CMD) $(COMMAND) $@.sh + +clean: + rm -fr *.cf diff --git a/yosys/README.md b/yosys/README.md new file mode 100644 index 0000000..cf1b90d --- /dev/null +++ b/yosys/README.md @@ -0,0 +1,6 @@ +# Notes about Yosys + +> Last update: Nov 2021 + +* Specify a REAL parameter is not supported (`ERROR: Can't decode value '1.1'!`) + * As a workaround, I set SKIP_REA diff --git a/yosys/vlog.sh b/yosys/vlog.sh new file mode 100644 index 0000000..d561bd6 --- /dev/null +++ b/yosys/vlog.sh @@ -0,0 +1,13 @@ +#!/bin/bash + +set -e + +yosys -Q -p ' +verilog_defaults -add -I../resources/vlog/path1; +verilog_defaults -add -I../resources/vlog/path2; +verilog_defines -DARCH_SEL=1; +read_verilog -defer ../resources/vlog/blink.v; +read_verilog -defer ../resources/vlog/top.v; +chparam -set BOO 1 -set INT 255 -set LOG 1 -set VEC 255 -set CHR "Z" -set STR "WXYZ" -set SKIP_REA 1 Top; +synth -top Top +' From a599946dca3a7a8ca25d49787406aa1230b7a13c Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Sun, 28 Nov 2021 16:49:33 -0300 Subject: [PATCH 13/23] vivado: fixed Verilog example after changes into resources --- vivado/Makefile | 2 +- vivado/README.md | 3 +++ vivado/vlog.tcl | 12 +++++++----- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/vivado/Makefile b/vivado/Makefile index 2745953..24673e5 100644 --- a/vivado/Makefile +++ b/vivado/Makefile @@ -12,4 +12,4 @@ version: clean: rm -fr *.bit *.cache *.hw *.runs *.xpr *.jou *.ip_user_files - rm -fr *.html *.log *.txt *.xml .Xil + rm -fr *.html *.log *.txt *.xml .Xil *.zip diff --git a/vivado/README.md b/vivado/README.md index 056392d..e342dcf 100644 --- a/vivado/README.md +++ b/vivado/README.md @@ -12,3 +12,6 @@ VHDL: * As a workaround, I set SKIP_ARCH * Values are specified following Verilog notation. * In case of character, is needed to specify the ASCII value + +Verilog: +* `$finish` is ignored, but fortunatly `$error("some text")` produces the desired result. diff --git a/vivado/vlog.tcl b/vivado/vlog.tcl index 6c4ea87..9467322 100644 --- a/vivado/vlog.tcl +++ b/vivado/vlog.tcl @@ -2,19 +2,21 @@ create_project -force vlog-project set_property "part" xc7z010-1-clg400 [current_project] -add_files ../resources/verilog/blink.v +add_files ../resources/vlog/blink.v -add_files ../resources/verilog/top.v +add_files ../resources/vlog/top.v add_files ../resources/constraints/zybo/clk.xdc add_files ../resources/constraints/zybo/led.xdc set_property top Top [current_fileset] -set_property verilog_define {VIVADO=1 FREQ=125000000} [current_fileset] +set_property verilog_define {ARCH_SEL=1 FREQ=125000000} [current_fileset] -set_property "include_dirs" "../resources/verilog/path1 ../resources/verilog/path2" [current_fileset] +set_property "include_dirs" "../resources/vlog/path1 ../resources/vlog/path2" [current_fileset] -set_property "generic" "BOO=1 INT=255 LOG=1'b1 VEC=8'b11111111 STR=WXYZ REA=1.1" -objects [get_filesets sources_1] +set_property "generic" "BOO=1 INT=255 LOG=1'b1 VEC=8'b11111111 CHR=Z STR=WXYZ REA=1.1" -objects [get_filesets sources_1] + +set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1] reset_run synth_1 launch_runs synth_1 From d3cacb707ebb8c148945ab735f9670420cfcca62 Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Sun, 28 Nov 2021 16:50:19 -0300 Subject: [PATCH 14/23] ghdl: updated README.md --- ghdl/README.md | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/ghdl/README.md b/ghdl/README.md index 8f6da20..a328644 100644 --- a/ghdl/README.md +++ b/ghdl/README.md @@ -2,6 +2,5 @@ > Last update: Nov 2021 -* Support to specify a REAL generic is not working - * unhandled override for generic "rea" +* Specify a REAL generic is not supported (`unhandled override for generic "rea"`) * As a workaround, I set SKIP_REA From ef5e009ae6f5c3573b2c9b2b62a9c6afcd000fac Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Sun, 28 Nov 2021 16:50:31 -0300 Subject: [PATCH 15/23] Added clean.sh --- clean.sh | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 clean.sh diff --git a/clean.sh b/clean.sh new file mode 100644 index 0000000..f96b779 --- /dev/null +++ b/clean.sh @@ -0,0 +1,9 @@ +#!/bin/bash + +set -e + +for DIR in */ ; do + if test -f "$DIR/Makefile"; then + make -C $DIR clean + fi +done From bca0b5a264b67a4bb15ca40e92a27f7abbb56d8d Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Sun, 28 Nov 2021 22:44:17 -0300 Subject: [PATCH 16/23] openflow: removed ghdl.sh and yosys.sh Similar examples are now at ghdl and yosys directories. --- openflow/Makefile | 2 +- openflow/ghdl.sh | 33 --------------------------------- openflow/yosys.sh | 30 ------------------------------ 3 files changed, 1 insertion(+), 64 deletions(-) delete mode 100644 openflow/ghdl.sh delete mode 100644 openflow/yosys.sh diff --git a/openflow/Makefile b/openflow/Makefile index 18774a5..0c0c536 100644 --- a/openflow/Makefile +++ b/openflow/Makefile @@ -4,7 +4,7 @@ DOCKER_CMD=docker run --rm -it -v $$HOME:$$HOME -w $$PWD ghdl/synth:beta COMMAND=bash -flow ghdl mix params yosys: +flow mix: $(COMMAND) $@.sh clean: diff --git a/openflow/ghdl.sh b/openflow/ghdl.sh deleted file mode 100644 index c2c6ada..0000000 --- a/openflow/ghdl.sh +++ /dev/null @@ -1,33 +0,0 @@ -#!/bin/bash - -set -e - -DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" - -FLAGS="--std=08 -fsynopsys -fexplicit -frelaxed" - -function msg () { tput setaf 6; echo "$1"; tput sgr0; } - -############################################################################### - -msg "* GHDL Flow" - -$DOCKER hdlc/ghdl:yosys /bin/bash -c " -ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink.vhdl -ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink_pkg.vhdl -ghdl -a $FLAGS ../resources/vhdl/top.vhdl -ghdl --synth $FLAGS Top -" - -rm -fr *.cf - -############################################################################### - -msg "* Parameters in GHDL" - -$DOCKER hdlc/ghdl:yosys ghdl -a $FLAGS ../resources/vhdl/generics.vhdl -#$DOCKER hdlc/ghdl:yosys ghdl --synth $FLAGS -gBOO=true -gINT=255 -gLOG=\'1\' -gSTR="WXYZ" Params -#$DOCKER hdlc/ghdl:yosys ghdl --synth $FLAGS -gBOO=true -gINT=255 -gLOG=\'1\' -gSTR="WXYZ" -gVEC="11111111" Params -#$DOCKER hdlc/ghdl:yosys ghdl --synth $FLAGS -gBOO=true -gINT=255 -gLOG=\'1\' -gSTR="WXYZ" -gREA=1.1 Params - -rm -fr *.cf diff --git a/openflow/yosys.sh b/openflow/yosys.sh deleted file mode 100644 index 6c3eb08..0000000 --- a/openflow/yosys.sh +++ /dev/null @@ -1,30 +0,0 @@ -#!/bin/bash - -set -e - -DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" - -function msg () { tput setaf 6; echo "$1"; tput sgr0; } - -################################################################################# - -msg "* Yosys Flow" - -$DOCKER hdlc/ghdl:yosys yosys -Q -p ' -verilog_defaults -add -I../resources/verilog/path1; -verilog_defaults -add -I../resources/verilog/path2; -read_verilog -defer ../resources/verilog/paths.v; -synth_xilinx -top Paths -family xc7; -write_edif -pvector bra yosys.edif -' - -rm -fr *.edif - -############################################################################### - -msg "* Parameters in Yosys" - -$DOCKER hdlc/ghdl:yosys yosys -Q -p " -read_verilog -defer ../resources/verilog/parameters.v; -chparam -set BOO 1 -set INT 255 -set LOG 1 -set VEC 8'b11111111 -set STR \"WXYZ\" -set REA \"1.1\" Params -" From 1aa13e0fe12f453dc208572a509e0fad213cc8de Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Sun, 28 Nov 2021 22:51:38 -0300 Subject: [PATCH 17/23] yosys: added vhdl.sh --- yosys/Makefile | 6 +++--- yosys/vhdl.sh | 17 +++++++++++++++++ 2 files changed, 20 insertions(+), 3 deletions(-) create mode 100644 yosys/vhdl.sh diff --git a/yosys/Makefile b/yosys/Makefile index 6b84458..535d65d 100644 --- a/yosys/Makefile +++ b/yosys/Makefile @@ -1,11 +1,11 @@ #!/usr/bin/make -DOCKER_CMD=docker run --rm -it -v $$HOME:$$HOME -w $$PWD ghdl/synth:beta +COMMAND=docker run --rm -it -v $$HOME:$$HOME -w $$PWD ghdl/synth:beta bash -COMMAND=bash +all: vhdl vlog vlog vhdl: - $(DOCKER_CMD) $(COMMAND) $@.sh + $(COMMAND) $@.sh clean: rm -fr *.cf diff --git a/yosys/vhdl.sh b/yosys/vhdl.sh new file mode 100644 index 0000000..4ff4298 --- /dev/null +++ b/yosys/vhdl.sh @@ -0,0 +1,17 @@ +#!/bin/bash + +set -e + +FLAGS="--std=08 -fsynopsys -fexplicit -frelaxed" + +ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink.vhdl +ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink_pkg.vhdl +ghdl -a $FLAGS ../resources/vhdl/top.vhdl + +GENERICS="-gBOO=true -gINT=255 -gLOG='1' -gVEC="11111111" -gCHR='Z' -gSTR="WXYZ" -gSKIP_REA=1" + +yosys -Q -m ghdl -p " +ghdl $FLAGS $GENERICS Top ARCH_SEL; +synth -top Top +" + From c3da5210fadf462848f37ca681221250dd4790aa Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Sun, 28 Nov 2021 23:19:18 -0300 Subject: [PATCH 18/23] openflow: flow.sh was split into yosys/icestorm and yosys/trellis --- openflow/Makefile | 2 +- openflow/flow.sh | 57 ----------------------------------------- yosys/Makefile | 2 ++ yosys/icestorm/Makefile | 9 +++++++ yosys/icestorm/prog.sh | 7 +++++ yosys/icestorm/vlog.sh | 22 ++++++++++++++++ yosys/trellis/Makefile | 9 +++++++ yosys/trellis/prog.sh | 8 ++++++ yosys/trellis/vlog.sh | 19 ++++++++++++++ 9 files changed, 77 insertions(+), 58 deletions(-) delete mode 100644 openflow/flow.sh create mode 100644 yosys/icestorm/Makefile create mode 100644 yosys/icestorm/prog.sh create mode 100644 yosys/icestorm/vlog.sh create mode 100644 yosys/trellis/Makefile create mode 100644 yosys/trellis/prog.sh create mode 100644 yosys/trellis/vlog.sh diff --git a/openflow/Makefile b/openflow/Makefile index 0c0c536..363b782 100644 --- a/openflow/Makefile +++ b/openflow/Makefile @@ -4,7 +4,7 @@ DOCKER_CMD=docker run --rm -it -v $$HOME:$$HOME -w $$PWD ghdl/synth:beta COMMAND=bash -flow mix: +mix: $(COMMAND) $@.sh clean: diff --git a/openflow/flow.sh b/openflow/flow.sh deleted file mode 100644 index 2782ef6..0000000 --- a/openflow/flow.sh +++ /dev/null @@ -1,57 +0,0 @@ -#!/bin/bash - -set -e - -DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" - -function msg () { tput setaf 6; echo "$1"; tput sgr0; } - -############################################################################### - -msg "* Yosys + nextpnr + IceStorm" - -cat ../resources/constraints/edu-ciaa-fpga/clk.pcf ../resources/constraints/edu-ciaa-fpga/led.pcf > edu-ciaa-fpga.pcf - -$DOCKER hdlc/ghdl:yosys /bin/bash -c " -yosys -Q -p ' -read_verilog -defer ../resources/verilog/blink.v; -synth_ice40 -top Blink -json blink.json -'" - -$DOCKER hdlc/nextpnr:ice40 /bin/bash -c " -nextpnr-ice40 --json blink.json --hx8k --package tq144:4k --pcf edu-ciaa-fpga.pcf --asc blink.asc -" - -rm -f edu-ciaa-fpga.pcf - -$DOCKER hdlc/icestorm /bin/bash -c " -icepack blink.asc blink.bit -icetime -d hx8k -mtr blink.rpt blink.asc -" - -# $DOCKER --device /dev/bus/usb hdlc/prog iceprog blink.bit - -rm -fr *.asc *.bit *.json *.rpt - -################################################################################## - -msg "* Yosys + nextpnr + Trellis" - -$DOCKER hdlc/ghdl:yosys /bin/bash -c " -yosys -Q -p ' -read_verilog -defer ../resources/verilog/blink.v; -synth_ecp5 -top Blink -json blink.json -'" - -$DOCKER hdlc/nextpnr:ecp5 /bin/bash -c " -nextpnr-ecp5 --json blink.json --25k --package CSFBGA285 --lpf ../resources/constraints/orangecrab/clk.lpf --lpf ../resources/constraints/orangecrab/led.lpf --textcfg blink.config -" - -$DOCKER hdlc/prjtrellis /bin/bash -c " -ecppack --svf blink.svf blink.config blink.bit -" - -# $DOCKER --device /dev/bus/usb hdlc/prog openocd -f ${TRELLIS}/misc/openocd/ecp5-evn.cfg -c "transport select jtag; init; svf blink.svf; exit" -# tinyprog -p aux.bit - -rm -fr *.bit *.config *.json *.svf diff --git a/yosys/Makefile b/yosys/Makefile index 535d65d..73a9364 100644 --- a/yosys/Makefile +++ b/yosys/Makefile @@ -9,3 +9,5 @@ vlog vhdl: clean: rm -fr *.cf + make -C icestorm clean + make -C trellis clean diff --git a/yosys/icestorm/Makefile b/yosys/icestorm/Makefile new file mode 100644 index 0000000..01b1fbf --- /dev/null +++ b/yosys/icestorm/Makefile @@ -0,0 +1,9 @@ +#!/usr/bin/make + +all: vlog + +vlog prog: + bash $@.sh + +clean: + rm -fr *.asc *.bit *.json *.rpt *.pcf diff --git a/yosys/icestorm/prog.sh b/yosys/icestorm/prog.sh new file mode 100644 index 0000000..539e9b8 --- /dev/null +++ b/yosys/icestorm/prog.sh @@ -0,0 +1,7 @@ +#!/bin/bash + +set -e + +DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" + +$DOCKER --device /dev/bus/usb hdlc/prog iceprog blink.bit diff --git a/yosys/icestorm/vlog.sh b/yosys/icestorm/vlog.sh new file mode 100644 index 0000000..d463228 --- /dev/null +++ b/yosys/icestorm/vlog.sh @@ -0,0 +1,22 @@ +#!/bin/bash + +set -e + +DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" + +cat ../../resources/constraints/icestick/clk.pcf ../../resources/constraints/icestick/led.pcf > icestick.pcf + +$DOCKER hdlc/ghdl:yosys /bin/bash -c " +yosys -Q -p ' +read_verilog -defer ../../resources/vlog/blink.v; +synth_ice40 -top Blink -json blink.json +'" + +$DOCKER hdlc/nextpnr:ice40 /bin/bash -c " +nextpnr-ice40 --json blink.json --hx8k --package tq144:4k --pcf icestick.pcf --asc blink.asc +" + +$DOCKER hdlc/icestorm /bin/bash -c " +icepack blink.asc blink.bit +icetime -d hx8k -mtr blink.rpt blink.asc +" diff --git a/yosys/trellis/Makefile b/yosys/trellis/Makefile new file mode 100644 index 0000000..53756b8 --- /dev/null +++ b/yosys/trellis/Makefile @@ -0,0 +1,9 @@ +#!/usr/bin/make + +all: vlog + +vlog prog: + bash $@.sh + +clean: + rm -fr *.bit *.config *.json *.svf diff --git a/yosys/trellis/prog.sh b/yosys/trellis/prog.sh new file mode 100644 index 0000000..7035499 --- /dev/null +++ b/yosys/trellis/prog.sh @@ -0,0 +1,8 @@ +#!/bin/bash + +set -e + +DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" + +$DOCKER --device /dev/bus/usb hdlc/prog openocd -f ${TRELLIS}/misc/openocd/ecp5-evn.cfg -c "transport select jtag; init; svf blink.svf; exit" +# tinyprog -p aux.bit diff --git a/yosys/trellis/vlog.sh b/yosys/trellis/vlog.sh new file mode 100644 index 0000000..eaf8030 --- /dev/null +++ b/yosys/trellis/vlog.sh @@ -0,0 +1,19 @@ +#!/bin/bash + +set -e + +DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" + +$DOCKER hdlc/ghdl:yosys /bin/bash -c " +yosys -Q -p ' +read_verilog -defer ../../resources/vlog/blink.v; +synth_ecp5 -top Blink -json blink.json +'" + +$DOCKER hdlc/nextpnr:ecp5 /bin/bash -c " +nextpnr-ecp5 --json blink.json --25k --package CSFBGA285 --lpf ../../resources/constraints/orangecrab/clk.lpf --lpf ../../resources/constraints/orangecrab/led.lpf --textcfg blink.config +" + +$DOCKER hdlc/prjtrellis /bin/bash -c " +ecppack --svf blink.svf blink.config blink.bit +" From 42e0da824ba42810ba8a9d8ce106e847db47c194 Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Tue, 30 Nov 2021 10:19:59 -0300 Subject: [PATCH 19/23] ghdl: updated the employed Docker container --- ghdl/Makefile | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/ghdl/Makefile b/ghdl/Makefile index 643169c..6c6fbfc 100644 --- a/ghdl/Makefile +++ b/ghdl/Makefile @@ -1,11 +1,9 @@ #!/usr/bin/make -DOCKER_CMD=docker run --rm -it -v $$HOME:$$HOME -w $$PWD ghdl/synth:beta - -COMMAND=bash +COMMAND=docker run --rm -it -v $$HOME:$$HOME -w $$PWD hdlc/ghdl:yosys bash vhdl: - $(DOCKER_CMD) $(COMMAND) $@.sh + $(COMMAND) $@.sh clean: rm -fr *.cf From 6c08653833e1b007bab9b1a44fca7df7ae523cfb Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Tue, 30 Nov 2021 10:30:02 -0300 Subject: [PATCH 20/23] yosys: updated the employed Docker container --- yosys/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys/Makefile b/yosys/Makefile index 73a9364..f0116a4 100644 --- a/yosys/Makefile +++ b/yosys/Makefile @@ -1,6 +1,6 @@ #!/usr/bin/make -COMMAND=docker run --rm -it -v $$HOME:$$HOME -w $$PWD ghdl/synth:beta bash +COMMAND=docker run --rm -it -v $$HOME:$$HOME -w $$PWD hdlc/ghdl:yosys bash all: vhdl vlog From 98aa5cc270f93e4572f721e878ce6ec494bfafbe Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Sat, 11 Dec 2021 21:06:23 -0300 Subject: [PATCH 21/23] ghdl: added a more concise alternative --- ghdl/vhdl.sh | 38 +++++++++++++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/ghdl/vhdl.sh b/ghdl/vhdl.sh index 99ea6b6..7273ae4 100644 --- a/ghdl/vhdl.sh +++ b/ghdl/vhdl.sh @@ -2,11 +2,39 @@ set -e -FLAGS="--std=08 -fsynopsys -fexplicit -frelaxed" +DIR=../resources/vhdl -ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink.vhdl -ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink_pkg.vhdl -ghdl -a $FLAGS ../resources/vhdl/top.vhdl +FLAGS="--std=08 -fsynopsys -fexplicit -frelaxed" GENERICS="-gBOO=true -gINT=255 -gLOG='1' -gVEC="11111111" -gCHR='Z' -gSTR="WXYZ" -gSKIP_REA=1" -ghdl --synth $FLAGS $GENERICS Top ARCH_SEL + +############################################################################### +# Alternative 1 +############################################################################### + +# This alternative is better to specify particular options per file + +ghdl -a $FLAGS --work=blink_lib $DIR/blink.vhdl +ghdl -a $FLAGS --work=blink_lib $DIR/blink_pkg.vhdl +ghdl -a $FLAGS $DIR/top.vhdl + +# --out=raw-vhdl generate a VHDL 93 netlist + +ghdl synth $FLAGS --out=raw-vhdl $GENERICS Top ARCH_SEL + +# This alternative creates .cf files + +rm -fr *.cf + +############################################################################### +# Alternative 2 +############################################################################### + +# This alternative is more concise + +# --work= applies to the following files +# --out=verilog generate a Verilog netlist + +ghdl synth $FLAGS --out=verilog $GENERICS \ + --work=blink_lib $DIR/blink.vhdl $DIR/blink_pkg.vhdl \ + --work=work $DIR/top.vhdl -e Top ARCH_SEL From 263b9c869d154ed9ac89f20b5e677c1e1085fa1e Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Sat, 11 Dec 2021 21:56:02 -0300 Subject: [PATCH 22/23] ghdl-yosys: added * Moved yosys/vhdl.sh to ghdl-yosys/vhdl.sh * Moved openflow content to ghdl-yosys --- ghdl-yosys/Makefile | 11 +++++++ ghdl-yosys/vhdl-top.sh | 11 +++++++ {yosys => ghdl-yosys}/vhdl.sh | 11 +++---- ghdl-yosys/vlog-top.sh | 11 +++++++ openflow/Makefile | 11 ------- openflow/mix.sh | 54 ----------------------------------- yosys/Makefile | 4 +-- 7 files changed, 41 insertions(+), 72 deletions(-) create mode 100644 ghdl-yosys/Makefile create mode 100644 ghdl-yosys/vhdl-top.sh rename {yosys => ghdl-yosys}/vhdl.sh (59%) create mode 100644 ghdl-yosys/vlog-top.sh delete mode 100644 openflow/Makefile delete mode 100644 openflow/mix.sh diff --git a/ghdl-yosys/Makefile b/ghdl-yosys/Makefile new file mode 100644 index 0000000..836c4a5 --- /dev/null +++ b/ghdl-yosys/Makefile @@ -0,0 +1,11 @@ +#!/usr/bin/make + +COMMAND=docker run --rm -it -v $$HOME:$$HOME -w $$PWD hdlc/ghdl:yosys bash + +all: vhdl vhdl-top vlog-top + +vhdl vhdl-top vlog-top: + $(COMMAND) $@.sh + +clean: + rm -fr *.cf diff --git a/ghdl-yosys/vhdl-top.sh b/ghdl-yosys/vhdl-top.sh new file mode 100644 index 0000000..571f2ad --- /dev/null +++ b/ghdl-yosys/vhdl-top.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +set -e + +DIR=../resources/mix + +yosys -Q -m ghdl -p " +ghdl $DIR/top.vhdl -e; +read_verilog $DIR/blink.v; +synth -top Top +" diff --git a/yosys/vhdl.sh b/ghdl-yosys/vhdl.sh similarity index 59% rename from yosys/vhdl.sh rename to ghdl-yosys/vhdl.sh index 4ff4298..9fe4057 100644 --- a/yosys/vhdl.sh +++ b/ghdl-yosys/vhdl.sh @@ -2,16 +2,17 @@ set -e -FLAGS="--std=08 -fsynopsys -fexplicit -frelaxed" +DIR=../resources/vhdl -ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink.vhdl -ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink_pkg.vhdl -ghdl -a $FLAGS ../resources/vhdl/top.vhdl +FLAGS="--std=08 -fsynopsys -fexplicit -frelaxed" GENERICS="-gBOO=true -gINT=255 -gLOG='1' -gVEC="11111111" -gCHR='Z' -gSTR="WXYZ" -gSKIP_REA=1" +ghdl -a $FLAGS --work=blink_lib $DIR/blink.vhdl +ghdl -a $FLAGS --work=blink_lib $DIR/blink_pkg.vhdl +ghdl -a $FLAGS $DIR/top.vhdl + yosys -Q -m ghdl -p " ghdl $FLAGS $GENERICS Top ARCH_SEL; synth -top Top " - diff --git a/ghdl-yosys/vlog-top.sh b/ghdl-yosys/vlog-top.sh new file mode 100644 index 0000000..5463d46 --- /dev/null +++ b/ghdl-yosys/vlog-top.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +set -e + +DIR=../resources/mix + +yosys -Q -m ghdl -p " +ghdl $DIR/blink.vhdl -e; +read_verilog $DIR/top.v; +synth -top Top +" diff --git a/openflow/Makefile b/openflow/Makefile deleted file mode 100644 index 363b782..0000000 --- a/openflow/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -#!/usr/bin/make - -DOCKER_CMD=docker run --rm -it -v $$HOME:$$HOME -w $$PWD ghdl/synth:beta - -COMMAND=bash - -mix: - $(COMMAND) $@.sh - -clean: - rm -fr *.cf *.edif diff --git a/openflow/mix.sh b/openflow/mix.sh deleted file mode 100644 index 2ecf68e..0000000 --- a/openflow/mix.sh +++ /dev/null @@ -1,54 +0,0 @@ -#!/bin/bash - -set -e - -DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" - -FLAGS="--std=08 -fsynopsys -fexplicit -frelaxed" - -function msg () { tput setaf 6; echo "$1"; tput sgr0; } - -function synth () { -$DOCKER hdlc/ghdl:yosys /bin/bash -c " -yosys -Q -m ghdl -p ' -ghdl $FLAGS $1 -e; -read_verilog $2; -synth_ice40 -top $3 -json blink.json -'" > /dev/null -} - -############################################################################### - -msg "* Verilog Top" -synth "../resources/mix/blink.vhdl" "../resources/mix/top.v" "Top" - -msg "* VHDL Top" -synth "../resources/mix/top.vhdl" "../resources/mix/blink.v" "Top" - -############################################################################### - -msg "* Verilog Top (alternative)" - -$DOCKER hdlc/ghdl:yosys /bin/bash -c " -ghdl -a ../resources/mix/blink.vhdl -yosys -Q -m ghdl -p ' -ghdl Blink; -read_verilog ../resources/mix/top.v; -synth_ice40 -top Top -json blink.json -'" > /dev/null - -rm -fr *.cf *.edif *.json - -msg "* VHDL Top (alternative)" - -$DOCKER hdlc/ghdl:yosys /bin/bash -c " -ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink.vhdl -ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink_pkg.vhdl -ghdl -a $FLAGS ../resources/vhdl/top.vhdl -yosys -Q -m ghdl -p ' -ghdl $FLAGS Top; -synth_xilinx -family xc7; -write_edif -pvector bra yosys.edif -'" > /dev/null - -rm -fr *.cf *.edif *.json diff --git a/yosys/Makefile b/yosys/Makefile index f0116a4..4f532c6 100644 --- a/yosys/Makefile +++ b/yosys/Makefile @@ -2,9 +2,9 @@ COMMAND=docker run --rm -it -v $$HOME:$$HOME -w $$PWD hdlc/ghdl:yosys bash -all: vhdl vlog +all: vlog -vlog vhdl: +vlog: $(COMMAND) $@.sh clean: From abb22a7e1d7f2a46dbf04c7d2fd2aef21a2f0334 Mon Sep 17 00:00:00 2001 From: "Rodrigo A. Melo" Date: Sun, 15 May 2022 15:39:30 -0300 Subject: [PATCH 23/23] resources: submodule updated --- resources | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/resources b/resources index f69243b..6a58bba 160000 --- a/resources +++ b/resources @@ -1 +1 @@ -Subproject commit f69243b28ddd07f9c8d4ffb1eabe4c3c257d4b39 +Subproject commit 6a58bba3b1c36d238d1111e910db02f0b284aef7