From 75f63395a03765fe83c14570e23a2f2deb5b7f2e Mon Sep 17 00:00:00 2001 From: Krzysztof Drewniak Date: Fri, 3 May 2024 21:21:28 +0000 Subject: [PATCH] Remove uses of .isa<> on values to silence warnings --- .../Dialect/Rock/Transforms/AlignTiling.cpp | 4 +- .../Dialect/Rock/Transforms/Regularize.cpp | 2 +- .../Rock/utility/transformMapUtils.cpp | 8 ++-- mlir/tools/rocmlir-gen/rocmlir-gen.cpp | 38 +++++++++---------- 4 files changed, 26 insertions(+), 26 deletions(-) diff --git a/mlir/lib/Dialect/Rock/Transforms/AlignTiling.cpp b/mlir/lib/Dialect/Rock/Transforms/AlignTiling.cpp index 21723a8e19df..78a21d955c9a 100644 --- a/mlir/lib/Dialect/Rock/Transforms/AlignTiling.cpp +++ b/mlir/lib/Dialect/Rock/Transforms/AlignTiling.cpp @@ -457,7 +457,7 @@ static LogicalResult checkUniqueReader(Operation *op, Operation *reader, for (Value result : op->getResults()) { // if its block arg, it can have uses beyond the unit of compilation // in scope here. - if (result.isa()) { + if (isa(result)) { isUnique = false; } for (auto &use : result.getUses()) { @@ -541,7 +541,7 @@ traceToWriter(Value startVal, static Value makeRegs(LinalgAlignRewriter &b, MemRefType::Builder &mrb, Location loc, Type srcType) { - auto srcMemType = srcType.cast(); + auto srcMemType = cast(srcType); // 1. create a second allocation of the same type to hold loaded elements return b.create(loc, static_cast(mrb.setElementType( srcMemType.getElementType()))); diff --git a/mlir/lib/Dialect/Rock/Transforms/Regularize.cpp b/mlir/lib/Dialect/Rock/Transforms/Regularize.cpp index e8941eece8d7..cb0bc9d3cded 100644 --- a/mlir/lib/Dialect/Rock/Transforms/Regularize.cpp +++ b/mlir/lib/Dialect/Rock/Transforms/Regularize.cpp @@ -163,7 +163,7 @@ void AnnotateGenericOp(Operation *op, MLIRContext *ctx) { dyn_cast_or_null(inp.getDefiningOp())) inp = viewOp.getViewSource(); - if (inp.isa()) { + if (isa(inp)) { auto arg = dyn_cast(inp); auto shape = inp.getType().cast(); int64_t argSize = shape.getNumElements(); diff --git a/mlir/lib/Dialect/Rock/utility/transformMapUtils.cpp b/mlir/lib/Dialect/Rock/utility/transformMapUtils.cpp index d8d5a939c71c..edc3b7a09601 100644 --- a/mlir/lib/Dialect/Rock/utility/transformMapUtils.cpp +++ b/mlir/lib/Dialect/Rock/utility/transformMapUtils.cpp @@ -1144,7 +1144,7 @@ static void createPermutationForMinorIdentityWithBroadcast( for (const auto &idxAndValue : llvm::enumerate(originalMap.getResults())) { auto idx = idxAndValue.index(); AffineExpr resultExpr = idxAndValue.value(); - if (resultExpr.isa()) { + if (isa(resultExpr)) { foundInputDims.insert(originalMap.getDimPosition(idx)); } } @@ -1152,7 +1152,7 @@ static void createPermutationForMinorIdentityWithBroadcast( for (const auto &idxAndValue : llvm::enumerate(originalMap.getResults())) { auto idx = idxAndValue.index(); AffineExpr resultExpr = idxAndValue.value(); - if (resultExpr.isa()) { + if (isa(resultExpr)) { auto swap1 = originalMap.getDimPosition(idx); auto swap2 = originalMap.getNumInputs() - originalMap.getNumResults() + idx; @@ -1201,7 +1201,7 @@ Value mlir::rock::insertTransposeAndBroadcastTransforms( newInpDimSize *= inpShape[idx]; AffineExpr resultExpr = idxAndValue.value(); mergeDims.push_back(idx); - if (diff != 0 && resultExpr.isa() && + if (diff != 0 && isa(resultExpr) && inpShape[idx] == 1) { diff++; } else { @@ -1639,7 +1639,7 @@ ArrayAttr mlir::rock::invertTransforms(OpBuilder &b, Location loc, ArrayAttr transforms) { SmallVector invertedTrs; for (Attribute tr : llvm::reverse(transforms)) { - TransformMapAttr trMap = tr.cast(); + auto trMap = cast(tr); TransformMapAttr invertedTrMap = invertTransformMap(b, trMap, loc); if (!invertedTrMap) return {}; diff --git a/mlir/tools/rocmlir-gen/rocmlir-gen.cpp b/mlir/tools/rocmlir-gen/rocmlir-gen.cpp index 554c72b0a7b9..6ce0ae34b910 100644 --- a/mlir/tools/rocmlir-gen/rocmlir-gen.cpp +++ b/mlir/tools/rocmlir-gen/rocmlir-gen.cpp @@ -1488,12 +1488,12 @@ static func::FuncOp getMemcpyFuncDecl(ModuleOp module, const MemRefType srcType, newLoadOp = opBuilder.create(loc, dstElemType, loadOp); } else { - assert(dstElemType.isa()); + assert(isa(dstElemType)); newLoadOp = opBuilder.create(loc, dstElemType, loadOp); } } else { - assert(srcElemType.isa()); + assert(isa(srcElemType)); if (dstElemType.isIntOrIndex()) { newLoadOp = opBuilder.create(loc, dstElemType, loadOp); @@ -1555,7 +1555,7 @@ static void emitMemcpy(OpBuilder &b, Value src, Value dst) { Value ensureFloatIsF32(OpBuilder &b, Location loc, Value ref, Type floatType) { auto refType = ref.getType().template dyn_cast(); Type refElemType = refType.getElementType(); - if (!refElemType.isa() || refElemType.isF32()) + if (!isa(refElemType) || refElemType.isF32()) return ref; Value refFlat = makeNDMemRef(b, ref, 1); auto f32NewType = MemRefType::get(refType.getShape(), floatType); @@ -1871,11 +1871,11 @@ createCPUConvWithMLIR(ModuleOp module, func::FuncOp &func, affine::buildAffineLoopNest(b, loc, lowerBounds, upperBounds, steps, createConv2dLoopNest); - if (!opd1.isa()) + if (!isa(opd1)) b.create(loc, opd1); - if (!opd2.isa()) + if (!isa(opd2)) b.create(loc, opd2); - if (!result.isa()) { + if (!isa(result)) { BlockArgument resultBlockArg; switch (genConfig.operation.value()) { case rock::ConvOpType::Fwd: @@ -2096,11 +2096,11 @@ static void createCPUConvWithCPP(ModuleOp module, func::FuncOp &func, paddingWidthRightConstantOp, dilationHeightConstantOp, dilationWidthConstantOp, accelConstantOp}); - if (!filter.isa()) + if (!isa(filter)) b.create(loc, filter); - if (!input.isa()) + if (!isa(input)) b.create(loc, input); - if (!output.isa()) { + if (!isa(output)) { BlockArgument resultBlockArg = block->getArgument(2); Value resultFlat = makeNDMemRef(b, output, 1); emitMemcpy(b, resultFlat, resultBlockArg); @@ -2514,7 +2514,7 @@ static func::FuncOp createCpuGemmKernelWithMlir(ModuleOp module, [](OpBuilder &builder, Location loc, ValueRange elems) { Value a = elems[0], b = elems[1], c = elems[2]; Type cType = c.getType(); - if (cType.isa()) { + if (isa(cType)) { Value aExt = rock::createTypeConversionOp(builder, loc, a, cType); Value bExt = rock::createTypeConversionOp(builder, loc, b, cType); Value mul = builder.create(loc, aExt, bExt); @@ -2527,11 +2527,11 @@ static func::FuncOp createCpuGemmKernelWithMlir(ModuleOp module, } }); - if (!aVal.isa()) + if (!isa(aVal)) b.create(loc, aVal); - if (!bVal.isa()) + if (!isa(bVal)) b.create(loc, bVal); - if (!cVal.isa()) { + if (!isa(cVal)) { BlockArgument resultBlockArg = block->getArgument(2); Value resultFlat = makeNDMemRef(b, cVal, 1); emitMemcpy(b, resultFlat, resultBlockArg); @@ -2800,7 +2800,7 @@ static func::FuncOp createVerifierFunc(ModuleOp module, const KernelIF &kernel, // obtain function name of the verifier wrapper std::string verifyFuncName = "mcpuVerify"; - if (valElemType.isa()) { + if (isa(valElemType)) { // f16, bf16, fp8, bf8 will be converted to f32 by wrapper. verifyFuncName += "Float"; } else if (valElemType.isInteger(8) || valElemType.isInteger(32) || @@ -2916,7 +2916,7 @@ static func::FuncOp createVerifierFunc(ModuleOp module, const KernelIF &kernel, // Declare and call the wrapper verify function func::FuncOp verifyFuncDecl; - if (testElemType.isa()) { + if (isa(testElemType)) { constexpr float defaultRMSThreshold(0.00003f); constexpr float defaultRMSThresholdFP16(0.001f); float RMSThresholdValue = @@ -3260,16 +3260,16 @@ static LogicalResult populateHostHarnessLogic( SmallVector localVars; SmallVector valVars; for (auto [idx, paramType] : llvm::enumerate(root0.params)) { - auto paramMRType = paramType.dyn_cast(); + auto paramMRType = dyn_cast(paramType); assert(paramMRType && "currently only supports memref types"); Type elemType = paramMRType.getElementType(); bool isSmallFloat = - elemType.isa() && elemType.getIntOrFloatBitWidth() < 32; + isa(elemType) && elemType.getIntOrFloatBitWidth() < 32; if (isCPUKernel) { // -prc if (genParams.operation.has_value()) { if (idx < genParams.types.size()) elemType = genParams.types[idx]; - if (elemType.isa() && llvm::is_contained(outIndices, idx)) + if (isa(elemType) && llvm::is_contained(outIndices, idx)) elemType = b.getIntegerType(64); paramMRType = MemRefType::get(paramMRType.getShape(), elemType); } @@ -3289,7 +3289,7 @@ static LogicalResult populateHostHarnessLogic( if (hasValidation || (isCPUKernel && isSmallFloat)) { // Emit validation var Type valElemType = floatType; - if (genParams.operation.has_value() && elemType.isa()) { + if (genParams.operation.has_value() && isa(elemType)) { valElemType = elemType; if (!gpuValidation && idx == 2) //-pv_with_mlir, -pv_with_cpp, or -pv_with_gpu && non-accel