From 1390073fe047f366cc557296026dc651300e7672 Mon Sep 17 00:00:00 2001 From: Thomas Roehl Date: Tue, 31 Oct 2023 19:12:40 +0100 Subject: [PATCH] Fixes for ICX & SPR CHA, especially umask_ext and filter registers --- src/includes/perfmon_icelake.h | 2 +- src/includes/perfmon_icelakeX_counters.h | 80 ++++++++++++------------ src/includes/perfmon_perfevent.h | 22 ++++++- src/includes/perfmon_sapphirerapids.h | 17 +++++ 4 files changed, 77 insertions(+), 44 deletions(-) diff --git a/src/includes/perfmon_icelake.h b/src/includes/perfmon_icelake.h index b57e9b230..702d6366d 100644 --- a/src/includes/perfmon_icelake.h +++ b/src/includes/perfmon_icelake.h @@ -402,7 +402,7 @@ int icx_cbox_setup(int cpu_id, RegisterIndex index, PerfmonEvent *event) { case 0x36: case 0x35: - umask_ext_mask = 0x1FFFFF; + umask_ext_mask = 0xFFFFFF; break; case 0x34: umask_ext_mask = 0x1FFF; diff --git a/src/includes/perfmon_icelakeX_counters.h b/src/includes/perfmon_icelakeX_counters.h index 3ecdc36a3..78c9afde1 100644 --- a/src/includes/perfmon_icelakeX_counters.h +++ b/src/includes/perfmon_icelakeX_counters.h @@ -628,46 +628,46 @@ static char* icelakeX_translate_types[NUM_UNITS] = { [MBOX5FIX] = "/sys/bus/event_source/devices/uncore_imc_5", [MBOX6FIX] = "/sys/bus/event_source/devices/uncore_imc_6", [MBOX7FIX] = "/sys/bus/event_source/devices/uncore_imc_7", - [CBOX0] = "/sys/bus/event_source/devices/uncore_cbox_0", - [CBOX1] = "/sys/bus/event_source/devices/uncore_cbox_1", - [CBOX2] = "/sys/bus/event_source/devices/uncore_cbox_2", - [CBOX3] = "/sys/bus/event_source/devices/uncore_cbox_3", - [CBOX4] = "/sys/bus/event_source/devices/uncore_cbox_4", - [CBOX5] = "/sys/bus/event_source/devices/uncore_cbox_5", - [CBOX6] = "/sys/bus/event_source/devices/uncore_cbox_6", - [CBOX7] = "/sys/bus/event_source/devices/uncore_cbox_7", - [CBOX8] = "/sys/bus/event_source/devices/uncore_cbox_8", - [CBOX9] = "/sys/bus/event_source/devices/uncore_cbox_9", - [CBOX10] = "/sys/bus/event_source/devices/uncore_cbox_10", - [CBOX11] = "/sys/bus/event_source/devices/uncore_cbox_11", - [CBOX12] = "/sys/bus/event_source/devices/uncore_cbox_12", - [CBOX13] = "/sys/bus/event_source/devices/uncore_cbox_13", - [CBOX14] = "/sys/bus/event_source/devices/uncore_cbox_14", - [CBOX15] = "/sys/bus/event_source/devices/uncore_cbox_15", - [CBOX16] = "/sys/bus/event_source/devices/uncore_cbox_16", - [CBOX17] = "/sys/bus/event_source/devices/uncore_cbox_17", - [CBOX18] = "/sys/bus/event_source/devices/uncore_cbox_18", - [CBOX19] = "/sys/bus/event_source/devices/uncore_cbox_19", - [CBOX20] = "/sys/bus/event_source/devices/uncore_cbox_20", - [CBOX21] = "/sys/bus/event_source/devices/uncore_cbox_21", - [CBOX22] = "/sys/bus/event_source/devices/uncore_cbox_22", - [CBOX23] = "/sys/bus/event_source/devices/uncore_cbox_23", - [CBOX24] = "/sys/bus/event_source/devices/uncore_cbox_24", - [CBOX25] = "/sys/bus/event_source/devices/uncore_cbox_25", - [CBOX26] = "/sys/bus/event_source/devices/uncore_cbox_26", - [CBOX27] = "/sys/bus/event_source/devices/uncore_cbox_27", - [CBOX28] = "/sys/bus/event_source/devices/uncore_cbox_27", - [CBOX29] = "/sys/bus/event_source/devices/uncore_cbox_27", - [CBOX30] = "/sys/bus/event_source/devices/uncore_cbox_27", - [CBOX31] = "/sys/bus/event_source/devices/uncore_cbox_27", - [CBOX32] = "/sys/bus/event_source/devices/uncore_cbox_27", - [CBOX33] = "/sys/bus/event_source/devices/uncore_cbox_27", - [CBOX34] = "/sys/bus/event_source/devices/uncore_cbox_27", - [CBOX35] = "/sys/bus/event_source/devices/uncore_cbox_27", - [CBOX36] = "/sys/bus/event_source/devices/uncore_cbox_27", - [CBOX37] = "/sys/bus/event_source/devices/uncore_cbox_27", - [CBOX38] = "/sys/bus/event_source/devices/uncore_cbox_27", - [CBOX39] = "/sys/bus/event_source/devices/uncore_cbox_27", + [CBOX0] = "/sys/bus/event_source/devices/uncore_cha_0", + [CBOX1] = "/sys/bus/event_source/devices/uncore_cha_1", + [CBOX2] = "/sys/bus/event_source/devices/uncore_cha_2", + [CBOX3] = "/sys/bus/event_source/devices/uncore_cha_3", + [CBOX4] = "/sys/bus/event_source/devices/uncore_cha_4", + [CBOX5] = "/sys/bus/event_source/devices/uncore_cha_5", + [CBOX6] = "/sys/bus/event_source/devices/uncore_cha_6", + [CBOX7] = "/sys/bus/event_source/devices/uncore_cha_7", + [CBOX8] = "/sys/bus/event_source/devices/uncore_cha_8", + [CBOX9] = "/sys/bus/event_source/devices/uncore_cha_9", + [CBOX10] = "/sys/bus/event_source/devices/uncore_cha_10", + [CBOX11] = "/sys/bus/event_source/devices/uncore_cha_11", + [CBOX12] = "/sys/bus/event_source/devices/uncore_cha_12", + [CBOX13] = "/sys/bus/event_source/devices/uncore_cha_13", + [CBOX14] = "/sys/bus/event_source/devices/uncore_cha_14", + [CBOX15] = "/sys/bus/event_source/devices/uncore_cha_15", + [CBOX16] = "/sys/bus/event_source/devices/uncore_cha_16", + [CBOX17] = "/sys/bus/event_source/devices/uncore_cha_17", + [CBOX18] = "/sys/bus/event_source/devices/uncore_cha_18", + [CBOX19] = "/sys/bus/event_source/devices/uncore_cha_19", + [CBOX20] = "/sys/bus/event_source/devices/uncore_cha_20", + [CBOX21] = "/sys/bus/event_source/devices/uncore_cha_21", + [CBOX22] = "/sys/bus/event_source/devices/uncore_cha_22", + [CBOX23] = "/sys/bus/event_source/devices/uncore_cha_23", + [CBOX24] = "/sys/bus/event_source/devices/uncore_cha_24", + [CBOX25] = "/sys/bus/event_source/devices/uncore_cha_25", + [CBOX26] = "/sys/bus/event_source/devices/uncore_cha_26", + [CBOX27] = "/sys/bus/event_source/devices/uncore_cha_27", + [CBOX28] = "/sys/bus/event_source/devices/uncore_cha_28", + [CBOX29] = "/sys/bus/event_source/devices/uncore_cha_29", + [CBOX30] = "/sys/bus/event_source/devices/uncore_cha_30", + [CBOX31] = "/sys/bus/event_source/devices/uncore_cha_31", + [CBOX32] = "/sys/bus/event_source/devices/uncore_cha_32", + [CBOX33] = "/sys/bus/event_source/devices/uncore_cha_33", + [CBOX34] = "/sys/bus/event_source/devices/uncore_cha_34", + [CBOX35] = "/sys/bus/event_source/devices/uncore_cha_35", + [CBOX36] = "/sys/bus/event_source/devices/uncore_cha_36", + [CBOX37] = "/sys/bus/event_source/devices/uncore_cha_37", + [CBOX38] = "/sys/bus/event_source/devices/uncore_cha_38", + [CBOX39] = "/sys/bus/event_source/devices/uncore_cha_39", [BBOX0] = "/sys/bus/event_source/devices/uncore_m2m_0", [BBOX1] = "/sys/bus/event_source/devices/uncore_m2m_1", [BBOX2] = "/sys/bus/event_source/devices/uncore_m2m_2", diff --git a/src/includes/perfmon_perfevent.h b/src/includes/perfmon_perfevent.h index df65af961..098d77781 100644 --- a/src/includes/perfmon_perfevent.h +++ b/src/includes/perfmon_perfevent.h @@ -172,7 +172,6 @@ struct perf_event_config_format { }; - int parse_event_config(char* base, char* option, int* num_formats, struct perf_event_config_format **formats) { int err = 0; @@ -289,6 +288,7 @@ int read_perf_event_type(char* folder) return type; } + int apply_event_config(struct perf_event_attr *attr, uint64_t optval, int num_formats, struct perf_event_config_format *formats) { if (!attr || num_formats <= 0 || !formats) @@ -759,11 +759,27 @@ int perf_uncore_setup(struct perf_event_attr *attr, RegisterType type, PerfmonEv if (ret == 0) { uint64_t umask = event->umask; + if (type >= CBOX0 && type <= CBOX59 && cpuid_info.isIntel && num_formats > 1 + && (cpuid_info.model == ICELAKEX1 || cpuid_info.model == ICELAKEX2 || cpuid_info.model == SAPPHIRERAPIDS)) + { + DEBUG_PRINT(DEBUGLEV_DEVELOP, Applying special umask handling for CBOXes of Intel ICX and SPR chips); + for(int j = 0; j < event->numberOfOptions; j++) + { + if (event->options[j].type == EVENT_OPTION_MATCH0) + { + DEBUG_PRINT(DEBUGLEV_DEVELOP, 0x%lX (0x%lX | (0x%lX << (%d - %d))), umask | (event->options[j].value << (formats[0].end - formats[0].start)), umask, event->options[j].value, formats[0].end, formats[0].start); + umask |= (event->options[j].value << (formats[0].end - formats[0].start + 1)); + break; + } + } + } for (int i = 0; i < num_formats && umask != 0x0; i++) { + DEBUG_PRINT(DEBUGLEV_DEVELOP, Format %s from %d-%d with value 0x%lX, perfEventOptionNames[EVENT_OPTION_GENERIC_UMASK], formats[i].start, formats[i].end, umask); switch(formats[i].reg) { case CONFIG: + DEBUG_PRINT(DEBUGLEV_DEVELOP, Adding 0x%lX to 0x%X, create_mask(umask, formats[i].start, formats[i].end), attr->config); attr->config |= create_mask(umask, formats[i].start, formats[i].end); break; case CONFIG1: @@ -824,14 +840,14 @@ int perf_uncore_setup(struct perf_event_attr *attr, RegisterType type, PerfmonEv } free(formats); } - if (cpuid_info.family == P6_FAMILY && cpuid_info.model == SAPPHIRERAPIDS && event->options[j].type == EVENT_OPTION_MATCH0) + /*if (cpuid_info.family == P6_FAMILY && cpuid_info.model == SAPPHIRERAPIDS && event->options[j].type == EVENT_OPTION_MATCH0) { attr->config |= (((uint64_t)event->options[j].value) & 0x3ffffff) << 32; } if (cpuid_info.family == P6_FAMILY && ((cpuid_info.model == ICELAKEX1 || cpuid_info.model == ICELAKEX2)) && event->options[j].type == EVENT_OPTION_MATCH0) { attr->config |= create_mask(event->options[j].value, 32, 57); - } + }*/ break; default: break; diff --git a/src/includes/perfmon_sapphirerapids.h b/src/includes/perfmon_sapphirerapids.h index a7d7262d7..b43d6a106 100644 --- a/src/includes/perfmon_sapphirerapids.h +++ b/src/includes/perfmon_sapphirerapids.h @@ -258,6 +258,18 @@ int spr_setup_uncore(int thread_id, RegisterIndex index, PerfmonEvent *event) case EVENT_OPTION_INVERT: flags |= (1ULL<<23); break; + case EVENT_OPTION_TID: + if (counter_map[index].type >= CBOX0 && counter_map[index].index <= CBOX55) + { + uint64_t reg = box_map[counter_map[index].type].filterRegister1; + uint64_t val = event->options[j].value & 0x3FF; + CHECK_PCI_WRITE_ERROR(HPMwrite(cpu_id, dev, reg, val)); + VERBOSEPRINTREG(cpu_id, counter_map[index].configRegister, flags, SETUP_CBOX_FILTER); + flags |= (1ULL << 16); + } + case EVENT_OPTION_MATCH0: + flags |= (event->options[j].value & 0xFFFFFF) << 32; + break; case EVENT_OPTION_THRESHOLD: flags |= (event->options[j].value & 0xFFULL) << 24; break; @@ -2218,6 +2230,11 @@ int perfmon_finalizeCountersThread_sapphirerapids(int thread_id, PerfmonEventSet } VERBOSEPRINTPCIREG(cpu_id, dev, counter_map[index].counterRegister, 0x0ULL, CLEAR_CTR); CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, dev, counter_map[index].counterRegister, 0x0ULL)); + if (box_map[type].filterRegister1 != 0x0) + { + VERBOSEPRINTPCIREG(cpu_id, dev, box_map[type].filterRegister1, 0x0ULL, CLEAR_FILTER); + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, dev, box_map[type].filterRegister1, 0x0ULL)); + } } eventSet->events[i].threadCounter[thread_id].init = FALSE; }