v0.3.78b

• salt problems. this time named siepic_tools2

v0.3.78

• bug fix
• name change to siepic-tools

v0.3.77

• KLayout 0.27.1 compatible
• Waveguide GUI improvements
• Verification:
  • remove Missing compact model check; this causes a lot of questions, particularly since the CML can be installed directly within INTERCONNECT.
  • added new verification: mulitple DevRec objects, suggests that it is a flattened cell

v0.3.76

• netlist & verification fix, with fixed GSiP example
• warning message that it doesn't work with KLayout 0.27

v0.3.75

• fix for GSiP PDK

v0.3.74

• fixes, including for CentOS7

v0.3.73

Improvements:

• integration with OPICS circuit simulator
• new scripting function: layout cell_character_replacement

Fixes

• support for multiple PDKs/technologies
• sbend
• scripting function: connect_pins_with_waveguide
• scripting function: connect_cell
• measure waveguide length difference

Multi-PDK support:

• find Waveguides.XML by finding folders that contain tech_name.lyt

v0.3.71

• fix in connect_pins_with_waveguide

v0.3.70

• GSiP Python2 backwards compatibility
• SiEPIC.scripts.connect_cell - added mirror option, fixes, better error checking
• added new INTERCONNECT path for Windows

v0.3.69

• performance improvements, for scripted layout using functions:
  • connect_pins_with_waveguide
  • find_components
• GSiP updates
  • split PCells into individual files
• added yaml package so KLayout can read YAML files, for PCells to read DRC parameters