DRC Error - M2/Si Device Overlap

[FaresBadrCA]

This may be more of a question than an issue: If my routing metal layer and my silicon waveguide layer overlap, I get a DRC error (shown below). Why is it not allowed to overlap the two? Aren't they on different layers?

[lukasc-ubc]

Hello,

It is acceptable to have Si and M2 overlapping, as they are far enough apart.

The error you are seeing is because we used a DevRec layer for optical structures, to avoid overlapping optical structures.

But I tried to reproduce your error, and I don't see it. Could you perhaps upload an example of this error, so I can reproduce it?

[FaresBadrCA]

The gds file in my latest pull request submissions/EBeam_faresb_heater.gds has this error. I suspect it is because I am running the 'Path to Wireguide' script on the routing layer. Is it a mistake to use that function on the routing metal layer?

In that same file, there is also a "Shapes outside component" functional layer error that doesn't seem to point to any shape that exists, but that may be a separate issue.

[lukasc-ubc]

Let me investigate. I also used the 'Path to Wireguide' in my example above. In any case, we can check it manually and waive the error if necessary.

[lukasc-ubc]

The overlap check was in both "V" Functional verification and "D" DRC. I removed it from the DRC check since it wasn't working correctly, whereas "V" works.