chipScope.cdc

#ChipScope Core Inserter Project File Version 3.0
#Sun Jan 21 14:00:13 CET 2018
Project.device.designInputFile=/home/yrid/Programing/fpga/sigasiWorkspace/sata-fpga/out/top_cs.ngc
Project.device.designOutputFile=/home/yrid/Programing/fpga/sigasiWorkspace/sata-fpga/out/top_cs.ngc
Project.device.deviceFamily=14
Project.device.enableRPMs=true
Project.device.outputDirectory=/home/yrid/Programing/fpga/sigasiWorkspace/sata-fpga/out/_ngo
Project.device.useSRL16=true
Project.filter.dimension=19
Project.filter<0>=*dcm*
Project.filter<10>=*LED*
Project.filter<11>=*LED**
Project.filter<12>=*GPIO*
Project.filter<13>=*rst_s*
Project.filter<14>=rst_s
Project.filter<15>=*ready*
Project.filter<16>=*sata_ready*
Project.filter<17>=*phy_ready*
Project.filter<18>=phy_ready
Project.filter<1>=dcm*
Project.filter<2>=dcm
Project.filter<3>=
Project.filter<4>=*150*
Project.filter<5>=*75*
Project.filter<6>=75*
Project.filter<7>=75
Project.filter<8>=*dcm_locked_s*
Project.filter<9>=*clk_75mhz_s*
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=Inst_platform/tx_rx_clk_150mhz_bufg_s
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=platform_ready_s
Project.unit<0>.dataChannel<1>=Inst_platform/comm_init_detect_s
Project.unit<0>.dataChannel<2>=Inst_platform/comm_wake_detect_s
Project.unit<0>.dataChannel<3>=GPIO_LED_1_OBUF
Project.unit<0>.dataChannel<4>=Inst_platform/dcm_locked_s
Project.unit<0>.dataDepth=32768
Project.unit<0>.dataEqualsTrigger=false
Project.unit<0>.dataPortWidth=5
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=Inst_platform/dcm_locked_s
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchType<0><0>=5
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=1
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro