From 625facb350c52a1c5e3d9625044f2b2388bf49e8 Mon Sep 17 00:00:00 2001
From: zhoujing <jing.zhou@terapines.com>
Date: Fri, 14 Jun 2024 09:46:00 +0800
Subject: [PATCH] [VENTUS][fix] Add memory access flags in tablegen In this
 way, it is better to judge what memory scope is accessed by load/store
 instructions

---
 .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 16 +++++++
 llvm/lib/Target/RISCV/RISCVInstrFormats.td    |  6 +++
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp      | 46 +++----------------
 llvm/lib/Target/RISCV/VentusInstrInfoV.td     | 11 ++++-
 4 files changed, 38 insertions(+), 41 deletions(-)

diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index f80853d82f57..583f5e5d5e3b 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -102,6 +102,10 @@ enum {
 
   IsVOPIMM11Shift = IsVVALUInstrShift + 1,
   IsVOPIMM11Mask = 1 << IsVOPIMM11Shift,
+
+  MemScopeShift = IsVOPIMM11Shift + 1,
+  MemScopeMask = 0b11 << MemScopeShift
+
 };
 
 // Match with the definitions in RISCVInstrFormats.td
@@ -112,6 +116,12 @@ enum VConstraintType {
   VMConstraint = 0b100,
 };
 
+enum MemScope {
+  DefaultMemScope = 0b00,
+  LocalMemScope = 0b01,
+  PrivateMemScope = 0b10
+};
+
 enum VLMUL : uint8_t {
   LMUL_1 = 0,
   LMUL_2,
@@ -135,6 +145,12 @@ static inline VConstraintType getConstraint(uint64_t TSFlags) {
                                       ConstraintShift);
 }
 
+/// \returns the memory access scope for the instruction.
+static inline MemScope getMemScope(uint64_t TSFlags) {
+  return static_cast<MemScope>((TSFlags & MemScopeMask) >>
+                                      MemScopeShift);
+}
+
 /// \returns true if there is a dummy mask operand for the instruction.
 static inline bool hasDummyMaskOp(uint64_t TSFlags) {
   return TSFlags & HasDummyMaskOpMask;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index b352b8d379ee..468fd781d394 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -211,6 +211,12 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
 
   bit IsVOPIMM11 = 0;
   let TSFlags{20} = IsVOPIMM11;
+
+  // 0: global and constant
+  // 1: shared/local
+  // 2: private
+  bits<2> MemScope = 0;
+  let TSFlags{22-21} = MemScope;
 }
 
 // Pseudo instructions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 3dfbf2e5dcd1..1ce7c91f3593 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -96,51 +96,18 @@ unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
 }
 
 bool RISCVInstrInfo::isPrivateMemoryAccess(const MachineInstr &MI) const {
-  switch (MI.getOpcode()) {
-    default:
-      return false;
-    case RISCV::VLW:
-    case RISCV::VLB:
-    case RISCV::VLBU:
-    case RISCV::VLH:
-    case RISCV::VLHU:
-    case RISCV::VSW:
-    case RISCV::VSH:
-    case RISCV::VSB:
-      return true;
-  }
+ return RISCVII::getMemScope(MI.getDesc().TSFlags) ==
+         RISCVII::MemScope::PrivateMemScope;
 }
 
 bool RISCVInstrInfo::isUniformMemoryAccess(const MachineInstr &MI) const {
-  switch (MI.getOpcode()) {
-    default:
-      return false;
-    case RISCV::LW:
-    case RISCV::LB:
-    case RISCV::LBU:
-    case RISCV::LH:
-    case RISCV::LHU:
-    case RISCV::SW:
-    case RISCV::SH:
-    case RISCV::SB:
-      return true;
-  }
+  return RISCVII::getMemScope(MI.getDesc().TSFlags) ==
+         RISCVII::MemScope::DefaultMemScope;
 }
 
 bool RISCVInstrInfo::isLocalMemoryAccess(const MachineInstr &MI) const {
-  switch (MI.getOpcode()) {
-    default:
-      return false;
-    case RISCV::VLWI12:
-    case RISCV::VLBI12:
-    case RISCV::VLBUI12:
-    case RISCV::VLHI12:
-    case RISCV::VLHUI12:
-    case RISCV::VSWI12:
-    case RISCV::VSHI12:
-    case RISCV::VSBI12:
-      return true;
-  }
+ return RISCVII::getMemScope(MI.getDesc().TSFlags) ==
+         RISCVII::MemScope::LocalMemScope;
 }
 
 
@@ -214,6 +181,7 @@ unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
   case RISCV::SD:
   case RISCV::VSW:
   case RISCV::VSH:
+  case RISCV::VSB:
     break;
   }
 
diff --git a/llvm/lib/Target/RISCV/VentusInstrInfoV.td b/llvm/lib/Target/RISCV/VentusInstrInfoV.td
index 2f9e2ff43c95..19d13e4a06b6 100644
--- a/llvm/lib/Target/RISCV/VentusInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/VentusInstrInfoV.td
@@ -711,6 +711,7 @@ class VENTUS_VL<bits<3> funct3, string opcodestr>
               opcodestr # ".v", "$rd, ${imm12}(${rs1})"> {
   let Inst{31} = 0;
   let Inst{30-20} = imm12{10-0};
+  let MemScope = 0b10;
 }
 class VENTUS_VS<bits<3> funct3, string opcodestr>
     : RVInstS<funct3, OPC_CUSTOM_1, (outs),
@@ -719,17 +720,23 @@ class VENTUS_VS<bits<3> funct3, string opcodestr>
   let Inst{31} = 1;
   let Inst{30-25} = imm12{10-5};
   let Inst{11-7} = imm12{4-0};
+  let MemScope = 0b10;
 }
 
 // Local/Global memory load/store instructions
 class VENTUS_VLI12<bits<3> funct3, string opcodestr> :
               RVInstI<funct3, OPC_CUSTOM_3, (outs VGPR:$rd),
               (ins VGPRMem:$rs1, simm12:$imm12),
-              opcodestr # ".v" , "$rd, ${imm12}(${rs1})">, Sched<[]>;
+              opcodestr # ".v" , "$rd, ${imm12}(${rs1})">, Sched<[]> {
+  let MemScope = 0b01;
+}
+
 class VENTUS_VSI12<bits<3> funct3, string opcodestr> :
               RVInstS<funct3, OPC_CUSTOM_3, (outs),
               (ins VGPR:$rs2, VGPRMem:$rs1, simm12:$imm12),
-              opcodestr # ".v", "$rs2, ${imm12}(${rs1})">, Sched<[]>;
+              opcodestr # ".v", "$rs2, ${imm12}(${rs1})">, Sched<[]> {
+  let MemScope = 0b01;
+}
 
 //===----------------------------------------------------------------------===//
 // Instructions