ERROR: Re-definition of module `\para_ser_01'!

[yslim2002]

env: PDK=sky130A
OpenLane 2023.07.25_2_g01e67230-conda
All rights reserved. (c) 2020-2022 Efabless Corporation and contributors.
Available under the Apache License, version 2.0. See the LICENSE file for more details.

[INFO]: Using configuration in 'config.json'...
[INFO]: PDK Root: /home/yslim/Seacas_Improve/conda-env/share/pdk
[INFO]: Process Design Kit: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Optimization Standard Cell Library: sky130_fd_sc_hd
[INFO]: Run Directory: /home/yslim/Seacas_Improve/runs/RUN_2023.09.19_02.19.39
[INFO]: Saving runtime environment...
[INFO]: Preparing LEF files for the nom corner...
[INFO]: Preparing LEF files for the min corner...
[INFO]: Preparing LEF files for the max corner...
[INFO]: Running linter (Verilator) (log: runs/RUN_2023.09.19_02.19.39/logs/synthesis/linter.log)...
[INFO]: 0 errors found by linter
[INFO]: 0 warnings found by linter
[STEP 1]
[INFO]: Running Synthesis (log: runs/RUN_2023.09.19_02.19.39/logs/synthesis/1-synthesis.log)...
[ERROR]: during executing yosys script /home/yslim/Seacas_Improve/conda-env/share/openlane/scripts/yosys/synth.tcl
[ERROR]: Log: runs/RUN_2023.09.19_02.19.39/logs/synthesis/1-synthesis.log
[ERROR]: Last 10 lines:
Generating RTLIL representation for module \multip_016'. Note: Assuming pure combinatorial block at multip_016.v:56.3-68.6 in compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending use of @* instead of @(...) for better match of synthesis and simulation. Generating RTLIL representation for module \fft'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /home/yslim/Seacas_Improve/para_ser_01.v
   /home/yslim/Seacas_Improve/para_ser_01.v:51: ERROR: Re-definition of module `\para_ser_01'!
   child process exited abnormally

[ERROR]: Creating issue reproducible...
[INFO]: Saving runtime environment...
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Parsing config file(s)…
Setting up /home/yslim/Seacas_Improve/runs/RUN_2023.09.19_02.19.39/issue_reproducible…
Done.
[INFO]: Reproducible packaged: Please tarball and upload 'runs/RUN_2023.09.19_02.19.39/issue_reproducible' if you're going to submit an issue.
[ERROR]: Step 1 (synthesis) failed with error:
-code 1 -level 0 -errorstack {INNER {invokeStk1 throw_error} CALL {run_tcl_script -tool yosys -no_consume /home/yslim/Seacas_Improve/conda-env/share/openlane/scripts/yosys/synth.tcl -indexed_log /home/yslim/Seacas_Improve/runs/RUN_2023.09.19_02.19.39/logs/synthesis/1-synthesis.log} CALL {run_yosys_script /home/yslim/Seacas_Improve/conda-env/share/openlane/scripts/yosys/synth.tcl -indexed_log /home/yslim/Seacas_Improve/runs/RUN_2023.09.19_02.19.39/logs/synthesis/1-synthesis.log} CALL {run_yosys -indexed_log /home/yslim/Seacas_Improve/runs/RUN_2023.09.19_02.19.39/logs/synthesis/1-synthesis.log} CALL run_synthesis CALL {run_non_interactive_mode -design .}} -errorcode NONE -errorinfo {
while executing
"throw_error"
(procedure "run_tcl_script" line 219)
invoked from within
"run_tcl_script -tool yosys -no_consume {*}$args"
(procedure "run_yosys_script" line 2)
invoked from within
"run_yosys_script $::env(SYNTH_SCRIPT) -indexed_log $arg_values(-indexed_log)"
(procedure "run_yosys" line 44)
invoked from within
"run_yosys -indexed_log $log"
(procedure "run_synthesis" line 13)
invoked from within
"run_synthesis"} -errorline 1
[INFO]: Saving current set of views in 'runs/RUN_2023.09.19_02.19.39/results/final'...
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at 'runs/RUN_2023.09.19_02.19.39/reports/manufacturability.rpt'.
[INFO]: Created metrics report at 'runs/RUN_2023.09.19_02.19.39/reports/metrics.csv'.
[INFO]: Saving runtime environment...
[ERROR]: Flow failed.

[yslim2002]

Anyone can help me with this issue? I am getting this error even I changed the module names for many times. The project that I used is in this github repository: https://github.com/VenciFreeman/FFT_ChipDesign.git

[yslim2002]

/----------------------------------------------------------------------------
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Xenia Wolf [email protected] |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
----------------------------------------------------------------------------/

Yosys 0.33+6 (git sha1 31ee566ec, x86_64-conda-linux-gnu-cc 11.2.0 -fvisibility-inlines-hidden -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -fdebug-prefix-map=/root/conda-eda/conda-eda/workdir/conda-env/conda-bld/yosys_1694474244328/work=/usr/local/src/conda/yosys-0.33_11_g31ee566ec -fdebug-prefix-map=/home/yslim/Seacas_Improve/conda-env=/usr/local/src/conda-prefix -fPIC -Os -fno-merge-constants)

[TCL: yosys -import] Command name collision: found pre-existing command cd' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command exec' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Verilog-2005 frontend: /home/yslim/Seacas_Improve/fft_chip.v
   Parsing SystemVerilog input from /home/yslim/Seacas_Improve/fft_chip.v' to AST representation. Generating RTLIL representation for module \fft_chip'.
   Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /home/yslim/Seacas_Improve/fft.v
   Parsing SystemVerilog input from /home/yslim/Seacas_Improve/fft.v' to AST representation. Generating RTLIL representation for module \ctrr_01'.
   Generating RTLIL representation for module \s_p'. Generating RTLIL representation for module \mux'.
   Note: Assuming pure combinatorial block at mux.v:38.3-45.6 in
   compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
   use of @* instead of @(...) for better match of synthesis and simulation.
   Note: Assuming pure combinatorial block at mux.v:54.3-58.18 in
   compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
   use of @* instead of @(...) for better match of synthesis and simulation.
   Note: Assuming pure combinatorial block at mux.v:60.4-64.18 in
   compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
   use of @* instead of @(...) for better match of synthesis and simulation.
   Note: Assuming pure combinatorial block at mux.v:66.4-70.18 in
   compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
   use of @* instead of @(...) for better match of synthesis and simulation.
   Note: Assuming pure combinatorial block at mux.v:72.4-76.18 in
   compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
   use of @* instead of @(...) for better match of synthesis and simulation.
   Generating RTLIL representation for module \butterfly'. Note: Assuming pure combinatorial block at butterfly.v:100.3-111.6 in compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending use of @* instead of @(...) for better match of synthesis and simulation. Note: Assuming pure combinatorial block at butterfly.v:114.3-125.6 in compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending use of @* instead of @(...) for better match of synthesis and simulation. Note: Assuming pure combinatorial block at butterfly.v:128.3-139.6 in compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending use of @* instead of @(...) for better match of synthesis and simulation. Note: Assuming pure combinatorial block at butterfly.v:142.3-153.6 in compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending use of @* instead of @(...) for better match of synthesis and simulation. Note: Assuming pure combinatorial block at butterfly.v:156.3-167.6 in compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending use of @* instead of @(...) for better match of synthesis and simulation. Note: Assuming pure combinatorial block at butterfly.v:170.3-181.6 in compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending use of @* instead of @(...) for better match of synthesis and simulation. Generating RTLIL representation for module \reg_01'.
   Generating RTLIL representation for module \para_ser_01'. Generating RTLIL representation for module \multip_016'.
   Note: Assuming pure combinatorial block at multip_016.v:56.3-68.6 in
   compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
   use of @* instead of @(...) for better match of synthesis and simulation.
   Generating RTLIL representation for module `\fft'.
   Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /home/yslim/Seacas_Improve/para_ser_01.v
   /home/yslim/Seacas_Improve/para_ser_01.v:51: ERROR: Re-definition of module `\para_ser_01'!

[vijayank88]

It is simple way to fix is check the line number 51 in /home/yslim/Seacas_Improve/para_ser_01.v and remove module para_ser_01.
Check whether it is part of include list