write_verilog Exclude physical only cells in final verilog file

[gkamendje]

I would like to use the final verilog file in a gate level simulation and I was wondering if there is a simple way to prevent physical only cells (such as filler cells) to be written out by write_verilog. For now I am just post processing the file to remove those cells. Thanks for any hint.

[maliberty]

There is no direct option for that today. write_verilog does have a -remove_cells option that could be used to exclude cells.

I do think this would make a good enhancement request if you want to file one.

[vijayank88]

@gkamendje

write_verilog <output_name>.v -remove_cells *_fill_*

The above command will write verilog without filler cells.

[gkamendje]

@vijayank88 thanks for the hint