Replies: 6 comments 29 replies
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You can mark your reset signals as multi cycle paths in the sdc. That often has a huge impact on buffering. |
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What do you mean by "a global reset signal being one cycle feels like overkill to me."? MegaBoom uses a synchronous reset and the "standard way" to fan out a synchronous reset is to add pipeline stages so that a synchronous reset tree can be built easily. It is "a pipeline that should be cleared" by holding the synchronous reset high for as many cycles as it takes. Reset recommendations from an FPGA, but the same applies to ASIC: https://www.intel.com/content/www/us/en/docs/programmable/683521/22-4/reset-recommendations.html The number of cycles to pipeline a synchronous reset is really a placement and routing consideration, so it would be neat if this could be left to post synthesis. |
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Instead of requiring your reset to complete in one cycle you can assert the reset for multiple cycles. It's a question of how timing critical the signal is, and whether boom relies on a single cycle reset |
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https://www.01signal.com/constraints/timing/timing-exceptions-advanced/ |
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"Instead of requiring your reset to complete in one cycle you can assert the reset for multiple cycles. It's a question of how timing critical the signal is, and whether boom relies on a single cycle reset" => Yes. This is the correct solution. I believe that MegaBoom is doing this, however I can't find out where it does so, so I have no proof. Note that I have, for now, built the BoomTile module as a macro, this is not the top level. I could try to build the top level module, but for now I wanted to stick to something smaller than the whole MegaBoom design... |
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@QuantamHD I'll try building from higher up in the design and see if yosys will complete in a reasonable amount of time when I flatten the design. Perhaps I'll "find" the reset pipeline stages. The-OpenROAD-Project/megaboom#2 |
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I'm looking at the fanout of the reset signal. As I understand it, this is the fanout is at each level. If that was for a perfectly balanced tree, then the fanout of reset would be the product of all those fanouts, which is on the order of 10^33, whereas I know from Quartus that the fanout of the reset signal is ca. 11000. Therefore, and unsurprisingly, the worst reset path is in a part of the tree that is highly unbalanced. |
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FPGA "fanouts" can be quite a bit different than ASIC fanouts because of differences in structure and how registers are allocated. That being said, I'm sure the resizer algorithm could be improved for high fanout nets. Register cloning (mentioned in the other comment) would be an orthogonal solution to this problem. |
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Not the fairest of comparisons - ASIC toolchains require much more computation than FPGA toolchains.
That is strange indeed. If DRT is finishing without violations, it may be worth reducing some of the layer adjustments so that GRT doesn't have to work as hard.
This is actually not retiming, this is register cloning. Retiming means that logic in one pipeline stage is moved to another pipeline stage. For example, a multiply is moved from before a register to after: What you are describing is register cloning (more generally, gate cloning). This process splits the fanout of a register by creating a duplicate and increasing the fanout of the previous stage. There has been work on gate cloning, but unfortunately that person left the project and wasn't able to finish. |
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Yes. |
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Honestly, if we know about high fan-out nets we should just turn them into trees automatically. Resizer is not that smart, and is meant more for smaller run of the mill nets. |
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You mean high fanout nets that have pipeline stages, like a synchronous reset with pipeline stages? |
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@rovinski I'm confused as to why you think it isn't retiming. "In BOOM, the floating point units and the pipelined integer multiply unit are described combinationally and then padded to the requested latency with registers." sounds like retiming |
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@maliberty yes, that is retiming but the registered reset is not retiming. |
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Some thoughts:
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I opened it and it looks quite different from your image above: |
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The skew is totally different and much better: |
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When in the flow is your skew picture from? |
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Feature request, speed up global route: The-OpenROAD-Project/OpenROAD#4407 |
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I switched to building DigitalTop in MegaBoom. ChipTop won't build, there's some more work needed on the Chipyard side of things. At DigitalTop, the synchronous reset is still the critical path. Note that synthesis is still hierarchical, it may need to be flattened to for synthesis to "find" the register pipeline registers. Interestingly, the clock skew seems to be highest in that neck of the woods(frontend/bpd/banked_predictors_*)... |
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Hello, I'm currently using Chipyard to synthesize SmallBoom. The tech I used is ASAP7 and the tool is Yosys. But a problem occurs like the issue I mentioned in ucb-bar/chipyard#1936. Have you met this before? Or could you figure out what the matter is and how to solve it? |
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I have not used hammer, only ORFS. Sorry. |
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The error mentioned in that issue is between yosys & abc and has nothing to do with OR. You might ask at https://github.com/YosysHQ/yosys |
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yosys and abc are tricky w.r.t. verboseness: ORFS adds -v 3 in YOSYS_FLAGS, which is a reasonable logging level, but it silences important errors like missing modules. You may try to adjust the verbosity flags in hammer..... |
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@maliberty @tspyrou @louiic @yupferris @vvbandeira @precisionmoon @hovind @jouthus
Just sharing some observations on running time for MegaBoom.
The https://github.com/The-OpenROAD-Project/megaboom project is using a wafer thin Bazel layer on top of ORFS to explore a practical workflow for exploring designs that have to run overnight.
Floorplan:
On running times:
CTS:
Timing after detailed routing:
On the longest timing path:
The longest path is on reset. This is expected, because Yosys does not do retiming. That BOOM relies on retiming in the way it is written is explicitly documented: https://docs.boom-core.org/en/latest/sections/physical-realization.html
The top level synchronous reset has many pipeline stages. However, BOOM is relying on global synthesis to distribute these pipeline stages in retiming. This is understandable: it is not an interesting aspect to study academically as it is a "solved problem". Either it is done manually with lots of effort, or it is done automatically by tools. There is something to be said for either approach for and against...
Here we see hold cells inserted due to clock skew:
I recall trying to use OpenROAD for larger designs in January 2023 without much luck.
Today, with a very limited effort to set up constraints & floorplan, I can quickly learn a lot about quite a large design in OpenROAD.
I'm looking forward to see the progress of OpenROAD in 2024!
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