Retiming during the flow

[chidori430]

Is it possible to use register retiming during synthesis for the OpenRoad flow? I noticed that there seem to be options for it in the yosys documentation but I'm unsure how to make it work in the OpenRoad flow.

[maliberty]

We have tried to use it so there are no current options for it. If you try it and find it helpful that would be interesting. You should also consider your verification methodology as it can be tricky.

[chidori430]

I have another question. I'm trying to verify my design and I can't seem to find the Verilog file with the gate level definitions for nangate45. I have the lib file but I thought there would be a Verilog file with the definitions located somewhere also.

[maliberty]

Not to my knowledge.

[oharboe]

We have tried to use it so there are no current options for it.

@maliberty I'm a bit confused by the above sentence. It seems like there is a "not" missing.

Should it have been: "We have not tried to use it so there are no current options for it"?

[vijayank88]

@maliberty
Where/When RESYNTH_TIMING_RECOVER this variable used. Description says Enable re-synthesis for timing optimization.. Is that different from user request?

OpenROAD-flow-scripts/flow/scripts/floorplan.tcl

Line 72 in 7db5d2c

##### Restructure for timing #########

[maliberty]

RESYNTH_TIMING_RECOVER is not retiming and is an unfinished experiment that should not be used.

[vijayank88]

It is part of flow variable list. Can you please provide description where/when it will be used?
Maybe I will add a note Not to be used, still under development, is that OK?