diff --git a/include/ord/Design.h b/include/ord/Design.h index a28459ab12b..d10ff0c921d 100644 --- a/include/ord/Design.h +++ b/include/ord/Design.h @@ -36,6 +36,8 @@ #pragma once #include +#include +#include #include #include @@ -61,6 +63,10 @@ namespace ant { class AntennaChecker; } +namespace dft { +class Dft; +} + namespace grt { class GlobalRouter; } @@ -77,6 +83,10 @@ namespace mpl { class MacroPlacer; } +namespace mpl2 { +class MacroPlacer2; +} + namespace ppl { class IOPlacer; } @@ -113,6 +123,10 @@ namespace rmp { class Restructure; } +namespace rsz { +class Resizer; +} + namespace stt { class SteinerTreeBuilder; } @@ -136,12 +150,14 @@ class LibertyCell; namespace ord { +class OpenRoad; class Tech; class Design { public: explicit Design(Tech* tech); + void readVerilog(const std::string& file_name); void readDef(const std::string& file_name, bool continue_on_errors = false, @@ -176,25 +192,32 @@ class Design std::uint64_t getNetRoutedLength(odb::dbNet* net); // Services - ifp::InitFloorplan* getFloorplan(); ant::AntennaChecker* getAntennaChecker(); - grt::GlobalRouter* getGlobalRouter(); - gpl::Replace* getReplace(); - dpl::Opendp* getOpendp(); - mpl::MacroPlacer* getMacroPlacer(); - ppl::IOPlacer* getIOPlacer(); - tap::Tapcell* getTapcell(); cts::TritonCTS* getTritonCts(); - drt::TritonRoute* getTritonRoute(); + dft::Dft* getDft(); + dpl::Opendp* getOpendp(); dpo::Optdp* getOptdp(); + drt::TritonRoute* getTritonRoute(); fin::Finale* getFinale(); + gpl::Replace* getReplace(); + grt::GlobalRouter* getGlobalRouter(); + ifp::InitFloorplan getFloorplan(); + mpl::MacroPlacer* getMacroPlacer(); + mpl2::MacroPlacer2* getMacroPlacer2(); + odb::dbDatabase* getDb(); + pad::ICeWall* getICeWall(); par::PartitionMgr* getPartitionMgr(); + pdn::PdnGen* getPdnGen(); + ppl::IOPlacer* getIOPlacer(); + psm::PDNSim* getPDNSim(); rcx::Ext* getOpenRCX(); rmp::Restructure* getRestructure(); + rsz::Resizer* getResizer(); stt::SteinerTreeBuilder* getSteinerTreeBuilder(); - psm::PDNSim* getPDNSim(); - pdn::PdnGen* getPdnGen(); - pad::ICeWall* getICeWall(); + tap::Tapcell* getTapcell(); + + // Needed by standalone startup, not for general use. + ord::OpenRoad* getOpenRoad(); // This returns a database that is not the one associated with // the rest of the application. It is usable as a standalone @@ -209,6 +232,9 @@ class Design sta::LibertyCell* getLibertyCell(odb::dbMaster* master); Tech* tech_; + + // Single-thread access to the interpreter in evalTclString + static std::mutex interp_mutex; }; } // namespace ord diff --git a/include/ord/OpenRoad.hh b/include/ord/OpenRoad.hh index bd36283bef9..8c707d23703 100644 --- a/include/ord/OpenRoad.hh +++ b/include/ord/OpenRoad.hh @@ -165,6 +165,7 @@ class OpenRoad // Tools should use their initialization functions to get the // OpenRoad object and/or any other tools they need to reference. static OpenRoad* openRoad(); + static void setOpenRoad(OpenRoad* app, bool reinit_ok = false); void init(Tcl_Interp* tcl_interp); Tcl_Interp* tclInterp() { return tcl_interp_; } @@ -293,6 +294,10 @@ class OpenRoad std::set observers_; int threads_ = 1; + + static OpenRoad* app_; + + friend class Tech; }; int tclAppInit(Tcl_Interp* interp); diff --git a/include/ord/Tech.h b/include/ord/Tech.h index 5422c4671eb..ebb255689db 100644 --- a/include/ord/Tech.h +++ b/include/ord/Tech.h @@ -35,35 +35,38 @@ #pragma once +#include #include namespace odb { class dbDatabase; -} - -namespace utl { -class Logger; -} +class dbTech; +} // namespace odb namespace sta { class dbSta; -class dbNetwork; -class LibertyCell; } // namespace sta namespace ord { +class OpenRoad; + class Tech { public: Tech(); + ~Tech(); + void readLef(const std::string& file_name); void readLiberty(const std::string& file_name); odb::dbDatabase* getDB(); + odb::dbTech* getTech(); sta::dbSta* getSta(); private: - odb::dbDatabase* db_; + OpenRoad* app_; + + friend class Design; }; } // namespace ord diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index f1ecea31ce1..ab7f828106b 100755 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -422,6 +422,7 @@ if (Python3_FOUND AND BUILD_PYTHON) dbSta odb OpenSTA + ifp ) target_link_libraries(openroad openroad_swig_py diff --git a/src/Design.cc b/src/Design.cc index e60e466da24..b1d766eda22 100644 --- a/src/Design.cc +++ b/src/Design.cc @@ -49,10 +49,17 @@ namespace ord { +std::mutex Design::interp_mutex; + Design::Design(Tech* tech) : tech_(tech) { } +ord::OpenRoad* Design::getOpenRoad() +{ + return tech_->app_; +} + odb::dbBlock* Design::getBlock() { auto chip = tech_->getDB()->getChip(); @@ -66,8 +73,7 @@ void Design::readVerilog(const std::string& file_name) getLogger()->error(utl::ORD, 36, "A block already exists in the db"); } - auto app = OpenRoad::openRoad(); - app->readVerilog(file_name.c_str()); + getOpenRoad()->readVerilog(file_name.c_str()); } void Design::readDef(const std::string& file_name, @@ -77,7 +83,6 @@ void Design::readDef(const std::string& file_name, bool child // = false ) { - auto app = OpenRoad::openRoad(); if (floorplan_init && incremental) { getLogger()->error(utl::ORD, 101, @@ -87,81 +92,75 @@ void Design::readDef(const std::string& file_name, if (tech_->getDB()->getTech() == nullptr) { getLogger()->error(utl::ORD, 102, "No technology has been read."); } - app->readDef(file_name.c_str(), - tech_->getDB()->getTech(), - continue_on_errors, - floorplan_init, - incremental, - child); + getOpenRoad()->readDef(file_name.c_str(), + tech_->getDB()->getTech(), + continue_on_errors, + floorplan_init, + incremental, + child); } void Design::link(const std::string& design_name) { - auto app = OpenRoad::openRoad(); - app->linkDesign(design_name.c_str(), false); + getOpenRoad()->linkDesign(design_name.c_str(), false); } void Design::readDb(std::istream& stream) { - auto app = OpenRoad::openRoad(); - app->readDb(stream); + getOpenRoad()->readDb(stream); } void Design::readDb(const std::string& file_name) { - auto app = OpenRoad::openRoad(); - app->readDb(file_name.c_str()); + getOpenRoad()->readDb(file_name.c_str()); } void Design::writeDb(std::ostream& stream) { - auto app = OpenRoad::openRoad(); - app->writeDb(stream); + getOpenRoad()->writeDb(stream); } void Design::writeDb(const std::string& file_name) { - auto app = OpenRoad::openRoad(); - app->writeDb(file_name.c_str()); + getOpenRoad()->writeDb(file_name.c_str()); } void Design::writeDef(const std::string& file_name) { - auto app = OpenRoad::openRoad(); - app->writeDef(file_name.c_str(), "5.8"); + getOpenRoad()->writeDef(file_name.c_str(), "5.8"); } -ifp::InitFloorplan* Design::getFloorplan() +ifp::InitFloorplan Design::getFloorplan() { - auto app = OpenRoad::openRoad(); auto block = getBlock(); if (!block) { getLogger()->error(utl::ORD, 37, "No block loaded."); } - return new ifp::InitFloorplan(block, app->getLogger(), app->getDbNetwork()); + return ifp::InitFloorplan(block, getLogger(), getSta()->getDbNetwork()); } utl::Logger* Design::getLogger() { - auto app = OpenRoad::openRoad(); - return app->getLogger(); + return getOpenRoad()->getLogger(); } int Design::micronToDBU(double coord) { - int dbuPerMicron = getBlock()->getDbUnitsPerMicron(); + const int dbuPerMicron = getBlock()->getDbUnitsPerMicron(); return round(coord * dbuPerMicron); } ant::AntennaChecker* Design::getAntennaChecker() { - auto app = OpenRoad::openRoad(); - return app->getAntennaChecker(); + return getOpenRoad()->getAntennaChecker(); } const std::string Design::evalTclString(const std::string& cmd) { - Tcl_Interp* tcl_interp = OpenRoad::openRoad()->tclInterp(); + const std::lock_guard lock(interp_mutex); + auto openroad = getOpenRoad(); + ord::OpenRoad::setOpenRoad(openroad, /* reinit_ok */ true); + Tcl_Interp* tcl_interp = openroad->tclInterp(); Tcl_Eval(tcl_interp, cmd.c_str()); return std::string(Tcl_GetStringResult(tcl_interp)); } @@ -173,14 +172,12 @@ Tech* Design::getTech() sta::dbSta* Design::getSta() { - auto app = OpenRoad::openRoad(); - return app->getSta(); + return tech_->getSta(); } sta::LibertyCell* Design::getLibertyCell(odb::dbMaster* master) { - sta::dbSta* sta = getSta(); - sta::dbNetwork* network = sta->getDbNetwork(); + sta::dbNetwork* network = getSta()->getDbNetwork(); sta::Cell* cell = network->dbToSta(master); if (!cell) { @@ -268,104 +265,107 @@ std::uint64_t Design::getNetRoutedLength(odb::dbNet* net) grt::GlobalRouter* Design::getGlobalRouter() { - auto app = OpenRoad::openRoad(); - return app->getGlobalRouter(); + return getOpenRoad()->getGlobalRouter(); } gpl::Replace* Design::getReplace() { - auto app = OpenRoad::openRoad(); - return app->getReplace(); + return getOpenRoad()->getReplace(); } dpl::Opendp* Design::getOpendp() { - auto app = OpenRoad::openRoad(); - return app->getOpendp(); + return getOpenRoad()->getOpendp(); +} + +mpl2::MacroPlacer2* Design::getMacroPlacer2() +{ + return getOpenRoad()->getMacroPlacer2(); } mpl::MacroPlacer* Design::getMacroPlacer() { - auto app = OpenRoad::openRoad(); - return app->getMacroPlacer(); + return getOpenRoad()->getMacroPlacer(); } ppl::IOPlacer* Design::getIOPlacer() { - auto app = OpenRoad::openRoad(); - return app->getIOPlacer(); + return getOpenRoad()->getIOPlacer(); } tap::Tapcell* Design::getTapcell() { - auto app = OpenRoad::openRoad(); - return app->getTapcell(); + return getOpenRoad()->getTapcell(); } cts::TritonCTS* Design::getTritonCts() { - auto app = OpenRoad::openRoad(); - return app->getTritonCts(); + return getOpenRoad()->getTritonCts(); } drt::TritonRoute* Design::getTritonRoute() { - auto app = OpenRoad::openRoad(); - return app->getTritonRoute(); + return getOpenRoad()->getTritonRoute(); } dpo::Optdp* Design::getOptdp() { - auto app = OpenRoad::openRoad(); - return app->getOptdp(); + return getOpenRoad()->getOptdp(); } fin::Finale* Design::getFinale() { - auto app = OpenRoad::openRoad(); - return app->getFinale(); + return getOpenRoad()->getFinale(); } par::PartitionMgr* Design::getPartitionMgr() { - auto app = OpenRoad::openRoad(); - return app->getPartitionMgr(); + return getOpenRoad()->getPartitionMgr(); } rcx::Ext* Design::getOpenRCX() { - auto app = OpenRoad::openRoad(); - return app->getOpenRCX(); + return getOpenRoad()->getOpenRCX(); } rmp::Restructure* Design::getRestructure() { - auto app = OpenRoad::openRoad(); - return app->getRestructure(); + return getOpenRoad()->getRestructure(); } stt::SteinerTreeBuilder* Design::getSteinerTreeBuilder() { - auto app = OpenRoad::openRoad(); - return app->getSteinerTreeBuilder(); + return getOpenRoad()->getSteinerTreeBuilder(); } psm::PDNSim* Design::getPDNSim() { - auto app = OpenRoad::openRoad(); - return app->getPDNSim(); + return getOpenRoad()->getPDNSim(); } pdn::PdnGen* Design::getPdnGen() { - auto app = OpenRoad::openRoad(); - return app->getPdnGen(); + return getOpenRoad()->getPdnGen(); } pad::ICeWall* Design::getICeWall() { - auto app = OpenRoad::openRoad(); - return app->getICeWall(); + return getOpenRoad()->getICeWall(); +} + +dft::Dft* Design::getDft() +{ + return getOpenRoad()->getDft(); +} + +odb::dbDatabase* Design::getDb() +{ + return getOpenRoad()->getDb(); +} + +rsz::Resizer* Design::getResizer() +{ + return getOpenRoad()->getResizer(); } /* static */ diff --git a/src/Design.i b/src/Design.i new file mode 100644 index 00000000000..c9791f3d900 --- /dev/null +++ b/src/Design.i @@ -0,0 +1,36 @@ +/////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2024, Precision Innovations Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +/////////////////////////////////////////////////////////////////////////////// + +%typemap(in,numinputs=0) ord::Design* design { + $1 = static_cast(Tcl_GetAssocData(interp, "design", nullptr)); +} diff --git a/src/Main.cc b/src/Main.cc index a887ba0fc4c..c629d2b333c 100644 --- a/src/Main.cc +++ b/src/Main.cc @@ -65,8 +65,10 @@ #endif #include "gui/gui.h" +#include "ord/Design.h" #include "ord/InitOpenRoad.hh" #include "ord/OpenRoad.hh" +#include "ord/Tech.h" #include "sta/StaMain.hh" #include "sta/StringUtil.hh" #include "utl/Logger.h" @@ -202,6 +204,12 @@ static void initPython() static volatile sig_atomic_t fatal_error_in_progress = 0; +// When we enter through main() we have a single tech and design. +// Custom applications using OR as a library might define multiple. +// Such applications won't allocate or use these objects. +static std::unique_ptr the_tech; +static std::unique_ptr the_design; + static void handler(int sig) { if (fatal_error_in_progress) { @@ -262,6 +270,10 @@ int main(int argc, char* argv[]) cmd_argc = argc; cmd_argv = argv; + + the_tech = std::make_unique(); + the_design = std::make_unique(the_tech.get()); + ord::OpenRoad::setOpenRoad(the_design->getOpenRoad()); #ifdef ENABLE_PYTHON3 if (findCmdLineFlag(cmd_argc, cmd_argv, "-python")) { // Setup the app with tcl @@ -389,6 +401,11 @@ static int tclAppInit(int& argc, const char* init_filename, Tcl_Interp* interp) { + // This is to enable Design.i where a design arg can be + // retrieved from the interpreter. This is necessary for + // cases with more than one interpreter (ie more than one Design). + // This should replace the use of the singleton OpenRoad::openRoad(). + Tcl_SetAssocData(interp, "design", nullptr, the_design.get()); bool exit_after_cmd_file = false; // first check if gui was requested and launch. // gui will call this function again as part of setup diff --git a/src/OpenRoad-py.i b/src/OpenRoad-py.i index be7179c3c99..a541a9ffafd 100644 --- a/src/OpenRoad-py.i +++ b/src/OpenRoad-py.i @@ -43,6 +43,7 @@ #include "ord/Tech.h" #include "ord/Design.h" #include "ord/Timing.h" +#include "ifp/InitFloorplan.hh" using odb::dbDatabase; using odb::dbBlock; diff --git a/src/OpenRoad.cc b/src/OpenRoad.cc index 62ad942134e..fc46d46587f 100644 --- a/src/OpenRoad.cc +++ b/src/OpenRoad.cc @@ -115,6 +115,8 @@ using sta::evalTclInit; using utl::ORD; +OpenRoad* OpenRoad::app_ = nullptr; + OpenRoad::OpenRoad() { db_ = dbDatabase::create(); @@ -159,9 +161,17 @@ sta::dbNetwork* OpenRoad::getDbNetwork() /* static */ OpenRoad* OpenRoad::openRoad() { - // This will be destroyed at application exit - static OpenRoad o; - return &o; + return app_; +} + +/* static */ +void OpenRoad::setOpenRoad(OpenRoad* app, bool reinit_ok) +{ + if (!reinit_ok && app_) { + std::cerr << "Attempt to reinitialize the application." << std::endl; + exit(1); + } + app_ = app; } //////////////////////////////////////////////////////////////// diff --git a/src/Tech.cc b/src/Tech.cc index e15588b95ef..52024cc2a85 100644 --- a/src/Tech.cc +++ b/src/Tech.cc @@ -35,6 +35,8 @@ #include "ord/Tech.h" +#include + #include "db_sta/dbSta.hh" #include "odb/db.h" #include "odb/lefin.h" @@ -42,21 +44,36 @@ namespace ord { -Tech::Tech() +Tech::Tech() : app_(new OpenRoad()) +{ + auto* interp = Tcl_CreateInterp(); + Tcl_Init(interp); + app_->init(interp); +} + +Tech::~Tech() { - auto app = OpenRoad::openRoad(); - db_ = app->getDb(); + delete app_; } odb::dbDatabase* Tech::getDB() { - return db_; + return app_->getDb(); +} + +odb::dbTech* Tech::getTech() +{ + return getDB()->getTech(); +} + +sta::dbSta* Tech::getSta() +{ + return app_->getSta(); } void Tech::readLef(const std::string& file_name) { - auto app = OpenRoad::openRoad(); - const bool make_tech = db_->getTech() == nullptr; + const bool make_tech = getDB()->getTech() == nullptr; const bool make_library = true; std::string lib_name = file_name; @@ -70,24 +87,17 @@ void Tech::readLef(const std::string& file_name) lib_name.erase(lib_name.begin() + dot_pos, lib_name.end()); } - app->readLef( + app_->readLef( file_name.c_str(), lib_name.c_str(), "", make_tech, make_library); } void Tech::readLiberty(const std::string& file_name) { - auto sta = OpenRoad::openRoad()->getSta(); // TODO: take corner & min/max args - sta->readLiberty(file_name.c_str(), - sta->cmdCorner(), - sta::MinMaxAll::all(), - true /* infer_latches */); -} - -sta::dbSta* Tech::getSta() -{ - auto sta = OpenRoad::openRoad()->getSta(); - return sta; + getSta()->readLiberty(file_name.c_str(), + getSta()->cmdCorner(), + sta::MinMaxAll::all(), + true /* infer_latches */); } } // namespace ord diff --git a/src/Timing.cc b/src/Timing.cc index c9cfb2d2a11..2b9a31ae351 100644 --- a/src/Timing.cc +++ b/src/Timing.cc @@ -40,13 +40,13 @@ #include "db_sta/dbNetwork.hh" #include "db_sta/dbSta.hh" #include "odb/db.h" -#include "ord/OpenRoad.hh" -#include "sta/Search.hh" -// #include "ord/Tech.h" #include "ord/Design.h" +#include "ord/OpenRoad.hh" +#include "ord/Tech.h" #include "rsz/Resizer.hh" #include "sta/Corner.hh" #include "sta/Liberty.hh" +#include "sta/Search.hh" #include "sta/TimingArc.hh" #include "sta/TimingRole.hh" #include "utl/Logger.h" @@ -59,8 +59,7 @@ Timing::Timing(Design* design) : design_(design) sta::dbSta* Timing::getSta() { - auto app = OpenRoad::openRoad(); - return app->getSta(); + return design_->getTech()->getSta(); } std::pair Timing::staToDBPin(const sta::Pin* pin) diff --git a/src/ant/test/ant_check.ok b/src/ant/test/ant_check.ok index 9f0342af872..48109e94830 100644 --- a/src/ant/test/ant_check.ok +++ b/src/ant/test/ant_check.ok @@ -1,9 +1,7 @@ [INFO ODB-0227] LEF file: ant_check.lef, created 14 layers, 30 vias, 3 library cells -[INFO ODB-0127] Reading DEF file: ant_check.def [INFO ODB-0128] Design: gcd [INFO ODB-0131] Created 3 components and 24 component-terminals. [INFO ODB-0133] Created 1 nets and 3 connections. -[INFO ODB-0134] Finished DEF file: ant_check.def Net: net50 Pin: output50/A (sky130_fd_sc_ms__buf_1) Layer: mcon diff --git a/src/ant/test/ant_check.py b/src/ant/test/ant_check.py index c5250fd1a09..4367edc1b54 100644 --- a/src/ant/test/ant_check.py +++ b/src/ant/test/ant_check.py @@ -2,11 +2,12 @@ # antenna values for testing from openroad import Design, Tech import ant +import helpers tech = Tech() tech.readLef("ant_check.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("ant_check.def") ack = design.getAntennaChecker() diff --git a/src/ant/test/ant_check.tcl b/src/ant/test/ant_check.tcl index d5e5580528c..946b369434c 100644 --- a/src/ant/test/ant_check.tcl +++ b/src/ant/test/ant_check.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # A minimal LEF file that has been modified to include particular antenna values for testing read_lef ant_check.lef read_def ant_check.def @@ -7,4 +8,4 @@ puts "violation count = [ant::antenna_violation_count]" # check if net50 has a violation set net "net50" -puts "Net $net violations: [ant::check_net_violation $net]" \ No newline at end of file +puts "Net $net violations: [ant::check_net_violation $net]" diff --git a/src/ant/test/ant_report.py b/src/ant/test/ant_report.py index ddd4cfe1ce5..546ba09ff7f 100644 --- a/src/ant/test/ant_report.py +++ b/src/ant/test/ant_report.py @@ -8,7 +8,7 @@ tech = Tech() tech.readLef("ant_check.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("ant_check.def") ack = design.getAntennaChecker() diff --git a/src/ant/test/check_api1.py b/src/ant/test/check_api1.py index 0a146798c82..fce36cd38c9 100644 --- a/src/ant/test/check_api1.py +++ b/src/ant/test/check_api1.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("merged_spacing.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("sw130_random.def") ack = design.getAntennaChecker() diff --git a/src/ant/test/check_drt1.py b/src/ant/test/check_drt1.py index 9147b420453..521d8d1d522 100644 --- a/src/ant/test/check_drt1.py +++ b/src/ant/test/check_drt1.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("merged_spacing.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("sw130_random.def") ack = design.getAntennaChecker() diff --git a/src/ant/test/no-check_grt1.py b/src/ant/test/no-check_grt1.py index bdf59e9b384..fd352288575 100644 --- a/src/ant/test/no-check_grt1.py +++ b/src/ant/test/no-check_grt1.py @@ -6,7 +6,7 @@ tech.readLef("sky130hs/sky130hs.tlef") tech.readLef("sky130hs/sky130hs_std_cell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd_sky130.def") # TODO: grt not yet wrapped and we need that here diff --git a/src/cmake/swig_lib.cmake b/src/cmake/swig_lib.cmake index 316cd285a40..fa93b3fa217 100644 --- a/src/cmake/swig_lib.cmake +++ b/src/cmake/swig_lib.cmake @@ -58,9 +58,9 @@ function(swig_lib) # Setup swig of I_FILE. set_property(SOURCE ${ARG_I_FILE} - PROPERTY COMPILE_OPTIONS ${LANGUAGE_OPTIONS} - -Werror - -w317,325,378,401,402,467,472,503,509) + PROPERTY COMPILE_OPTIONS ${LANGUAGE_OPTIONS} + -Werror + -w317,325,378,401,402,451,467,472,503,509) set_property(SOURCE ${ARG_I_FILE} PROPERTY SWIG_MODULE_NAME ${ARG_NAME}) diff --git a/src/cts/test/balance_levels.py b/src/cts/test/balance_levels.py index cd6426d8754..e07a04da922 100644 --- a/src/cts/test/balance_levels.py +++ b/src/cts/test/balance_levels.py @@ -7,7 +7,7 @@ tech.readLiberty("Nangate45/Nangate45_typ.lib") tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.evalTclString(cts_helpers.make_array) design.evalTclString("set block [make_array 300 200000 200000 150]") design.evalTclString("sta::db_network_defined") diff --git a/src/cts/test/check_buffers.py b/src/cts/test/check_buffers.py index af03e152214..84f51be045e 100644 --- a/src/cts/test/check_buffers.py +++ b/src/cts/test/check_buffers.py @@ -7,7 +7,7 @@ tech.readLiberty("Nangate45/Nangate45_typ.lib") tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("check_buffers.def") design.evalTclString("create_clock -period 5 clk") diff --git a/src/cts/test/check_charBuf.py b/src/cts/test/check_charBuf.py index 30a91b126e4..0b6ff358fb5 100644 --- a/src/cts/test/check_charBuf.py +++ b/src/cts/test/check_charBuf.py @@ -6,7 +6,7 @@ tech.readLiberty("Nangate45/Nangate45_typ.lib") tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("16sinks.def") design.evalTclString("create_clock -period 5 clk") diff --git a/src/cts/test/check_wire_rc_cts.py b/src/cts/test/check_wire_rc_cts.py index e14acffe84e..d44ea6a4f71 100644 --- a/src/cts/test/check_wire_rc_cts.py +++ b/src/cts/test/check_wire_rc_cts.py @@ -7,7 +7,7 @@ tech.readLiberty("Nangate45/Nangate45_typ.lib") tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("check_buffers.def") design.evalTclString("create_clock -period 5 clk") diff --git a/src/cts/test/find_clock.py b/src/cts/test/find_clock.py index e983b169867..6983aa975b3 100644 --- a/src/cts/test/find_clock.py +++ b/src/cts/test/find_clock.py @@ -6,7 +6,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("16sinks.def") design.evalTclString("create_clock -period 5 clk") diff --git a/src/cts/test/find_clock_pad.py b/src/cts/test/find_clock_pad.py index 8a0f8e23531..4accf4ad48d 100644 --- a/src/cts/test/find_clock_pad.py +++ b/src/cts/test/find_clock_pad.py @@ -8,7 +8,7 @@ tech.readLiberty("Nangate45/Nangate45_typ.lib") tech.readLiberty("pad.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("find_clock_pad.def") design.evalTclString("create_clock -name clk -period 10 clk1") diff --git a/src/cts/test/max_cap.py b/src/cts/test/max_cap.py index 56010761778..8da16f23bd0 100644 --- a/src/cts/test/max_cap.py +++ b/src/cts/test/max_cap.py @@ -8,7 +8,7 @@ tech.readLef("sky130hs/sky130hs_std_cell.lef") tech.readLiberty("sky130hs/sky130hs_tt.lib") -design = Design(tech) +design = helpers.make_design(tech) # avoid potential name clash with tcl test def_file = "max_cap-py.def" diff --git a/src/cts/test/no_clocks.py b/src/cts/test/no_clocks.py index 701e7da3ffd..c933bc4b73a 100644 --- a/src/cts/test/no_clocks.py +++ b/src/cts/test/no_clocks.py @@ -6,7 +6,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("no_clock.def") design.evalTclString("set_wire_rc -clock -layer metal5") diff --git a/src/cts/test/no_sinks.py b/src/cts/test/no_sinks.py index cbd2c1508ec..22dc0cdd384 100644 --- a/src/cts/test/no_sinks.py +++ b/src/cts/test/no_sinks.py @@ -6,7 +6,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("no_sinks.def") design.evalTclString("create_clock -period 5 clk") diff --git a/src/cts/test/simple_test.py b/src/cts/test/simple_test.py index d40432bbad2..bbfc84c2808 100644 --- a/src/cts/test/simple_test.py +++ b/src/cts/test/simple_test.py @@ -6,7 +6,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("16sinks.def") design.evalTclString("create_clock -period 5 clk") diff --git a/src/cts/test/simple_test_clustered.py b/src/cts/test/simple_test_clustered.py index 06117b0e0f1..a5c4f0a7c85 100644 --- a/src/cts/test/simple_test_clustered.py +++ b/src/cts/test/simple_test_clustered.py @@ -7,7 +7,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.evalTclString(cts_helpers.make_array) design.evalTclString("make_array 300") design.evalTclString("sta::db_network_defined") diff --git a/src/cts/test/simple_test_clustered_max_cap.py b/src/cts/test/simple_test_clustered_max_cap.py index bf11da54b06..4b867242b6e 100644 --- a/src/cts/test/simple_test_clustered_max_cap.py +++ b/src/cts/test/simple_test_clustered_max_cap.py @@ -7,7 +7,7 @@ tech.readLiberty("Nangate45/Nangate45_typ.lib") tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.evalTclString(cts_helpers.make_array) design.evalTclString("make_array 300") design.evalTclString("sta::db_network_defined") diff --git a/src/dpl/test/aes.py b/src/dpl/test/aes.py index 57eddb837a7..d094e219aa0 100644 --- a/src/dpl/test/aes.py +++ b/src/dpl/test/aes.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("aes_cipher_top_replace.def") dpl_aux.detailed_placement(design) diff --git a/src/dpl/test/blockage01.py b/src/dpl/test/blockage01.py index 7518aa70136..445dcd19404 100644 --- a/src/dpl/test/blockage01.py +++ b/src/dpl/test/blockage01.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("blockage01.def") dpl_aux.detailed_placement(design) diff --git a/src/dpl/test/cell_on_block1.py b/src/dpl/test/cell_on_block1.py index a5e2d5dac33..28fef537f20 100644 --- a/src/dpl/test/cell_on_block1.py +++ b/src/dpl/test/cell_on_block1.py @@ -6,7 +6,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") tech.readLef("block2.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("cell_on_block1.def") dpl_aux.detailed_placement(design) diff --git a/src/dpl/test/cell_on_block2.py b/src/dpl/test/cell_on_block2.py index 5bea691aa05..e72e65855af 100644 --- a/src/dpl/test/cell_on_block2.py +++ b/src/dpl/test/cell_on_block2.py @@ -6,7 +6,7 @@ tech.readLef("sky130hd/sky130hd.tlef") tech.readLef("sky130hd/sky130hd_std_cell.lef") tech.readLef("cell_on_block2.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("cell_on_block2.def") dpl_aux.set_placement_padding(design, globl=True, right=4) diff --git a/src/dpl/test/check1.py b/src/dpl/test/check1.py index 0764327c38e..e38cf3b5331 100644 --- a/src/dpl/test/check1.py +++ b/src/dpl/test/check1.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("simple01.def") gpl = design.getOpendp() diff --git a/src/dpl/test/fence01.py b/src/dpl/test/fence01.py index 222f9fbd8ca..531d476f51b 100644 --- a/src/dpl/test/fence01.py +++ b/src/dpl/test/fence01.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("fence01.def") dpl_aux.detailed_placement(design) diff --git a/src/dpl/test/fence02.py b/src/dpl/test/fence02.py index 8b3a7fcf53a..bee4989754b 100644 --- a/src/dpl/test/fence02.py +++ b/src/dpl/test/fence02.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("fence02.def") dpl_aux.detailed_placement(design) diff --git a/src/dpl/test/fence03.py b/src/dpl/test/fence03.py index 24c491a5fdd..213f5031925 100644 --- a/src/dpl/test/fence03.py +++ b/src/dpl/test/fence03.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("fence03.def") dpl_aux.detailed_placement(design) diff --git a/src/dpl/test/fillers1.py b/src/dpl/test/fillers1.py index 2998ffef020..ee1bf5811ea 100644 --- a/src/dpl/test/fillers1.py +++ b/src/dpl/test/fillers1.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("simple01.def") dpl_aux.detailed_placement(design) diff --git a/src/dpl/test/fillers2.py b/src/dpl/test/fillers2.py index 121f11002ed..27ba4e642ba 100644 --- a/src/dpl/test/fillers2.py +++ b/src/dpl/test/fillers2.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("simple01.def") dpl_aux.set_placement_padding(design, globl=True, left=2, right=2) diff --git a/src/dpl/test/fillers3.py b/src/dpl/test/fillers3.py index b6d7483876e..203efacb8d9 100644 --- a/src/dpl/test/fillers3.py +++ b/src/dpl/test/fillers3.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("simple01.def") dpl_aux.detailed_placement(design) diff --git a/src/dpl/test/fillers4.py b/src/dpl/test/fillers4.py index 8051b197118..d742cda4600 100644 --- a/src/dpl/test/fillers4.py +++ b/src/dpl/test/fillers4.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") tech.readLef("fill3.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("fillers4.def") dpl_aux.detailed_placement(design, disallow_one_site_gaps=True) diff --git a/src/dpl/test/fragmented_row01.py b/src/dpl/test/fragmented_row01.py index 37e46d52559..fc5f3da40f9 100644 --- a/src/dpl/test/fragmented_row01.py +++ b/src/dpl/test/fragmented_row01.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("fragmented_row01.def") dpl_aux.detailed_placement(design) diff --git a/src/dpl/test/fragmented_row02.py b/src/dpl/test/fragmented_row02.py index 8594dd79e9d..c4f0123b743 100644 --- a/src/dpl/test/fragmented_row02.py +++ b/src/dpl/test/fragmented_row02.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("fragmented_row02.def") dpl_aux.detailed_placement(design) diff --git a/src/dpl/test/gcd.py b/src/dpl/test/gcd.py index bdffbd40e3a..5784da02011 100644 --- a/src/dpl/test/gcd.py +++ b/src/dpl/test/gcd.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd_replace.def") dpl_aux.detailed_placement(design) diff --git a/src/dpl/test/ibex.py b/src/dpl/test/ibex.py index b666a307fbd..0ad811a05af 100644 --- a/src/dpl/test/ibex.py +++ b/src/dpl/test/ibex.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("ibex_core_replace.def") dpl_aux.detailed_placement(design) diff --git a/src/dpl/test/mirror1.py b/src/dpl/test/mirror1.py index 4837c41ccc0..a720e49434f 100644 --- a/src/dpl/test/mirror1.py +++ b/src/dpl/test/mirror1.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd_replace.def") dpl_aux.set_placement_padding(design, globl=True, left=1, right=1) diff --git a/src/dpl/test/mirror2.py b/src/dpl/test/mirror2.py index 0a427addb5f..73b799d568c 100644 --- a/src/dpl/test/mirror2.py +++ b/src/dpl/test/mirror2.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") tech.readLef("extra.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("mirror2.def") dpl_aux.set_placement_padding(design, globl=True, left=1, right=1) diff --git a/src/dpl/test/mirror3.py b/src/dpl/test/mirror3.py index 8eb7e3e709d..6f7165ba288 100644 --- a/src/dpl/test/mirror3.py +++ b/src/dpl/test/mirror3.py @@ -5,6 +5,6 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd_replace.def") design.getOpendp().optimizeMirroring() diff --git a/src/dpl/test/obstruction1.py b/src/dpl/test/obstruction1.py index 1270269ab33..0ec417d8488 100644 --- a/src/dpl/test/obstruction1.py +++ b/src/dpl/test/obstruction1.py @@ -7,7 +7,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") tech.readLef("obstruction1.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("obstruction1.def") dpl_aux.detailed_placement(design) diff --git a/src/dpl/test/obstruction2.py b/src/dpl/test/obstruction2.py index e9f2f187234..e1523d26a54 100644 --- a/src/dpl/test/obstruction2.py +++ b/src/dpl/test/obstruction2.py @@ -8,7 +8,7 @@ tech.readLiberty("Nangate45/fakeram45_64x7.lib") tech.readLef("Nangate45/Nangate45.lef") tech.readLef("Nangate45/fakeram45_64x7.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("obstruction2.def") dpl_aux.detailed_placement(design) diff --git a/src/dpl/test/one_site_gap_disallow.py b/src/dpl/test/one_site_gap_disallow.py index 5880aa81403..868ba896d90 100644 --- a/src/dpl/test/one_site_gap_disallow.py +++ b/src/dpl/test/one_site_gap_disallow.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("one_site_gap_disallow.def") dpl_aux.detailed_placement(design, disallow_one_site_gaps=True) diff --git a/src/dpl/test/pad01.py b/src/dpl/test/pad01.py index 90bf1c2bec0..7a28d6037d4 100644 --- a/src/dpl/test/pad01.py +++ b/src/dpl/test/pad01.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("simple01.def") dpl_aux.set_placement_padding(design, globl=True, left=5) diff --git a/src/dpl/test/pad03.py b/src/dpl/test/pad03.py index efde2e46ce3..1d793eef668 100644 --- a/src/dpl/test/pad03.py +++ b/src/dpl/test/pad03.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("simple03.def") dpl_aux.set_placement_padding(design, globl=True, right=5) diff --git a/src/dpl/test/simple01.py b/src/dpl/test/simple01.py index 1a3ca5a60bf..e5e4d714695 100644 --- a/src/dpl/test/simple01.py +++ b/src/dpl/test/simple01.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("simple01.def") dpl_aux.detailed_placement(design) diff --git a/src/dpl/test/simple02.py b/src/dpl/test/simple02.py index bdc141f184c..5a70cbd8625 100644 --- a/src/dpl/test/simple02.py +++ b/src/dpl/test/simple02.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("simple02.def") dpl_aux.detailed_placement(design) diff --git a/src/dpo/test/aes.py b/src/dpo/test/aes.py index ca610be4b40..8af5ccf5e76 100644 --- a/src/dpo/test/aes.py +++ b/src/dpo/test/aes.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("aes.def") design.getOptdp().improvePlacement(1, 0, 0) diff --git a/src/dpo/test/gcd.py b/src/dpo/test/gcd.py index 72212fb3575..e8bc0e5fd7e 100644 --- a/src/dpo/test/gcd.py +++ b/src/dpo/test/gcd.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") design.getOptdp().improvePlacement(1, 0, 0) diff --git a/src/dpo/test/ibex.py b/src/dpo/test/ibex.py index c5a164a63ff..f96b5132fc0 100644 --- a/src/dpo/test/ibex.py +++ b/src/dpo/test/ibex.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("ibex.def") design.getOptdp().improvePlacement(1, 0, 0) diff --git a/src/drt/test/aes_nangate45.py b/src/drt/test/aes_nangate45.py index 1664b2eb9d6..20eca850f71 100644 --- a/src/drt/test/aes_nangate45.py +++ b/src/drt/test/aes_nangate45.py @@ -13,7 +13,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45_tech.lef") tech.readLef("Nangate45/Nangate45_stdcell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("aes_nangate45_preroute.def") gr = design.getGlobalRouter() diff --git a/src/drt/test/ispd18_sample.py b/src/drt/test/ispd18_sample.py index 8295327f776..16e51735d37 100644 --- a/src/drt/test/ispd18_sample.py +++ b/src/drt/test/ispd18_sample.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("testcase/ispd18_sample/ispd18_sample.input.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("testcase/ispd18_sample/ispd18_sample.input.def") gr = design.getGlobalRouter() diff --git a/src/drt/test/single_step.py b/src/drt/test/single_step.py index bdb62f1fd66..06c4c866b18 100644 --- a/src/drt/test/single_step.py +++ b/src/drt/test/single_step.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("testcase/ispd18_sample/ispd18_sample.input.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("testcase/ispd18_sample/ispd18_sample.input.def") gr = design.getGlobalRouter() diff --git a/src/drt/test/top_level_term.py b/src/drt/test/top_level_term.py index 7bf5336a177..4b474e00797 100644 --- a/src/drt/test/top_level_term.py +++ b/src/drt/test/top_level_term.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("sky130hs/sky130hs.tlef") tech.readLef("sky130hs/sky130hs_std_cell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("top_level_term.def") gr = design.getGlobalRouter() diff --git a/src/drt/test/top_level_term2.py b/src/drt/test/top_level_term2.py index 3a59192b2a3..ed1f65dbaeb 100644 --- a/src/drt/test/top_level_term2.py +++ b/src/drt/test/top_level_term2.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("sky130hs/sky130hs.tlef") tech.readLef("sky130hs/sky130hs_std_cell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("top_level_term2.def") gr = design.getGlobalRouter() diff --git a/src/fin/test/gcd_fill.py b/src/fin/test/gcd_fill.py index ed08c83a078..99dc91fae2e 100644 --- a/src/fin/test/gcd_fill.py +++ b/src/fin/test/gcd_fill.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("sky130hd/sky130hd.tlef") tech.readLef("sky130hd/sky130_fd_sc_hd_merged.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd_prefill.def") dfl = design.getFinale() diff --git a/src/gpl/test/CMakeLists.txt b/src/gpl/test/CMakeLists.txt index ddd56e52dec..523a01cddf4 100644 --- a/src/gpl/test/CMakeLists.txt +++ b/src/gpl/test/CMakeLists.txt @@ -10,6 +10,8 @@ set(TEST_NAMES simple01-skip-io simple01-rd simple02-rd + simple03-rd + simple04-rd simple02 simple03 simple04 @@ -18,6 +20,7 @@ set(TEST_NAMES simple07 simple08 simple09 + simple10 core01 ar01 ar02 diff --git a/src/gpl/test/ar01.py b/src/gpl/test/ar01.py index 92ce18155fa..fa27600157b 100644 --- a/src/gpl/test/ar01.py +++ b/src/gpl/test/ar01.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./ar01.def") gpl_aux.global_placement( diff --git a/src/gpl/test/ar02.py b/src/gpl/test/ar02.py index 6251d999713..44774c81957 100644 --- a/src/gpl/test/ar02.py +++ b/src/gpl/test/ar02.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./ar02.def") gpl_aux.global_placement( diff --git a/src/gpl/test/convergence01.py b/src/gpl/test/convergence01.py index 00f8401c9a8..5d8c3f8d002 100644 --- a/src/gpl/test/convergence01.py +++ b/src/gpl/test/convergence01.py @@ -16,7 +16,7 @@ tech.readLef("./asap7/asap7_tech_1x_201209.lef") tech.readLef("./asap7/asap7sc7p5t_28_R_1x_220121a.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("convergence01.def") design.evalTclString("read_sdc convergence01.sdc") diff --git a/src/gpl/test/core01.py b/src/gpl/test/core01.py index 39989ab8d09..f43ea10464f 100644 --- a/src/gpl/test/core01.py +++ b/src/gpl/test/core01.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./core01.def") gpl_aux.global_placement( diff --git a/src/gpl/test/error01.py b/src/gpl/test/error01.py index 841fe7b2389..fdfcfa95686 100644 --- a/src/gpl/test/error01.py +++ b/src/gpl/test/error01.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./error01.def") try: diff --git a/src/gpl/test/incremental01.py b/src/gpl/test/incremental01.py index d47abdae754..65873b6e9ac 100644 --- a/src/gpl/test/incremental01.py +++ b/src/gpl/test/incremental01.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./incremental01.def") gpl_aux.global_placement(design, init_density_penalty=0.1, incremental=True) diff --git a/src/gpl/test/incremental02.py b/src/gpl/test/incremental02.py index accce2d31bf..53126ede8b0 100644 --- a/src/gpl/test/incremental02.py +++ b/src/gpl/test/incremental02.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./incremental02.def") gpl_aux.global_placement(design, incremental=True, density=0.3, pad_left=2, pad_right=2) diff --git a/src/gpl/test/nograd01.py b/src/gpl/test/nograd01.py index 0f68585af61..243c1374f5c 100644 --- a/src/gpl/test/nograd01.py +++ b/src/gpl/test/nograd01.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("asap7/asap7_tech_1x_201209.lef") tech.readLef("asap7/asap7sc7p5t_28_R_1x_220121a.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./nograd01.def") gpl_aux.global_placement(design, skip_io=True) diff --git a/src/gpl/test/simple01-obs.py b/src/gpl/test/simple01-obs.py index 7abb67b010a..46ccb37a920 100644 --- a/src/gpl/test/simple01-obs.py +++ b/src/gpl/test/simple01-obs.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./simple01-obs.def") # design.evalTclString("global_placement -init_density_penalty 0.01 -skip_initial_place -density 0.8") diff --git a/src/gpl/test/simple01-ref.py b/src/gpl/test/simple01-ref.py index 6b4bddeb6b4..d561edb1c08 100644 --- a/src/gpl/test/simple01-ref.py +++ b/src/gpl/test/simple01-ref.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./simple01-ref.def") gpl_aux.global_placement( diff --git a/src/gpl/test/simple01-skip-io.py b/src/gpl/test/simple01-skip-io.py index 10e68980348..668a33c259f 100644 --- a/src/gpl/test/simple01-skip-io.py +++ b/src/gpl/test/simple01-skip-io.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./simple01-skip-io.def") gpl_aux.global_placement(design, skip_io=True) diff --git a/src/gpl/test/simple01-td-tune.py b/src/gpl/test/simple01-td-tune.py index cb662dbd10a..b79fcdfff98 100644 --- a/src/gpl/test/simple01-td-tune.py +++ b/src/gpl/test/simple01-td-tune.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLiberty("./library/nangate45/NangateOpenCellLibrary_typical.lib") tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("simple01-td-tune.def") design.evalTclString("create_clock -name core_clock -period 2 clk") diff --git a/src/gpl/test/simple01-td.py b/src/gpl/test/simple01-td.py index c59111ba903..59a7833c8d9 100644 --- a/src/gpl/test/simple01-td.py +++ b/src/gpl/test/simple01-td.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLiberty("./library/nangate45/NangateOpenCellLibrary_typical.lib") tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./simple01-td.def") design.evalTclString("create_clock -name core_clock -period 2 clk") diff --git a/src/gpl/test/simple01-uniform.py b/src/gpl/test/simple01-uniform.py index 83264ee46d2..45f7944c471 100644 --- a/src/gpl/test/simple01-uniform.py +++ b/src/gpl/test/simple01-uniform.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./simple01.def") gpl_aux.global_placement( diff --git a/src/gpl/test/simple01.py b/src/gpl/test/simple01.py index 2ec71c7faff..36f6623b25f 100644 --- a/src/gpl/test/simple01.py +++ b/src/gpl/test/simple01.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./simple01.def") gpl_aux.global_placement(design, init_density_penalty=0.01, skip_initial_place=True) diff --git a/src/gpl/test/simple02.py b/src/gpl/test/simple02.py index 85faefd0a91..30fe4eabfbd 100644 --- a/src/gpl/test/simple02.py +++ b/src/gpl/test/simple02.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./simple02.def") gpl_aux.global_placement( diff --git a/src/gpl/test/simple03.py b/src/gpl/test/simple03.py index 73ee42bc7b8..5bb6842ffa0 100644 --- a/src/gpl/test/simple03.py +++ b/src/gpl/test/simple03.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./simple03.def") gpl_aux.global_placement(design) diff --git a/src/gpl/test/simple04.py b/src/gpl/test/simple04.py index cb3412d7e9b..f2353b18ed4 100644 --- a/src/gpl/test/simple04.py +++ b/src/gpl/test/simple04.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./simple04.def") gpl_aux.global_placement(design) diff --git a/src/gpl/test/simple05.py b/src/gpl/test/simple05.py index 5241ded3849..1b0c20f35cf 100644 --- a/src/gpl/test/simple05.py +++ b/src/gpl/test/simple05.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./simple05.def") gpl_aux.global_placement(design, skip_initial_place=True) diff --git a/src/gpl/test/simple06.py b/src/gpl/test/simple06.py index 2883f939d10..22fd16eef95 100644 --- a/src/gpl/test/simple06.py +++ b/src/gpl/test/simple06.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./simple06.def") gpl_aux.global_placement(design, skip_nesterov_place=True) diff --git a/src/gpl/test/simple07.py b/src/gpl/test/simple07.py index 0eb02093ad1..9a92398bd63 100644 --- a/src/gpl/test/simple07.py +++ b/src/gpl/test/simple07.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./sky130hd.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./simple07.def") gpl_aux.global_placement(design, density=0.75) diff --git a/src/gpl/test/simple08.py b/src/gpl/test/simple08.py index 75fca1d7dc2..dbe8b867c3d 100644 --- a/src/gpl/test/simple08.py +++ b/src/gpl/test/simple08.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./sky130hd.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./simple08.def") gpl_aux.global_placement(design, density=0.75, bin_grid_count=64, overflow=0.2) diff --git a/src/gpl/test/simple09.py b/src/gpl/test/simple09.py index 892967b518f..0d9f261ae62 100644 --- a/src/gpl/test/simple09.py +++ b/src/gpl/test/simple09.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./simple09.def") gpl_aux.global_placement(design, init_density_penalty=1.0, skip_initial_place=True) diff --git a/src/gpl/test/simple10.py b/src/gpl/test/simple10.py index f66b322db3b..52f2564f86a 100644 --- a/src/gpl/test/simple10.py +++ b/src/gpl/test/simple10.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("./sky130hd.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./simple10.def") gpl_aux.global_placement(design, density=0.75) diff --git a/src/grt/test/clock_route.py b/src/grt/test/clock_route.py index 58327d80117..dd25cc5ae5e 100644 --- a/src/grt/test/clock_route.py +++ b/src/grt/test/clock_route.py @@ -7,7 +7,7 @@ tech.readLef("sky130hs/sky130hs.tlef") tech.readLef("sky130hs/sky130hs_std_cell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("clock_route.def") gr = design.getGlobalRouter() diff --git a/src/grt/test/clock_route_error1.py b/src/grt/test/clock_route_error1.py index 54d10f0d530..6397c153d92 100644 --- a/src/grt/test/clock_route_error1.py +++ b/src/grt/test/clock_route_error1.py @@ -7,7 +7,7 @@ tech.readLef("sky130hs/sky130hs.tlef") tech.readLef("sky130hs/sky130hs_std_cell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("clock_route.def") # FIXME: When stt has been Python wrapped, use the Python version of set_routing_alpha diff --git a/src/grt/test/congestion1.py b/src/grt/test/congestion1.py index 572d3ff86c2..570c83d71fd 100644 --- a/src/grt/test/congestion1.py +++ b/src/grt/test/congestion1.py @@ -7,7 +7,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) gcddef = os.path.join(test_path, "gcd.def") design.readDef(gcddef) gr = design.getGlobalRouter() diff --git a/src/grt/test/congestion2.py b/src/grt/test/congestion2.py index b8ea1099950..e9068452a8f 100644 --- a/src/grt/test/congestion2.py +++ b/src/grt/test/congestion2.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") gr = design.getGlobalRouter() diff --git a/src/grt/test/critical_nets_percentage.py b/src/grt/test/critical_nets_percentage.py index 65bea1aa495..076aafd3788 100644 --- a/src/grt/test/critical_nets_percentage.py +++ b/src/grt/test/critical_nets_percentage.py @@ -7,7 +7,7 @@ tech.readLef("sky130hs/sky130hs.tlef") tech.readLef("sky130hs/sky130hs_std_cell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("critical_nets_percentage.def") gr = design.getGlobalRouter() diff --git a/src/grt/test/est_rc1.py b/src/grt/test/est_rc1.py index 1f55a3e7180..39341693e28 100644 --- a/src/grt/test/est_rc1.py +++ b/src/grt/test/est_rc1.py @@ -8,7 +8,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) gcddef = os.path.join(test_path, "gcd.def") design.readDef(gcddef) gr = design.getGlobalRouter() diff --git a/src/grt/test/gcd_flute.py b/src/grt/test/gcd_flute.py index 1e8e38ed4dd..f3d362206b7 100644 --- a/src/grt/test/gcd_flute.py +++ b/src/grt/test/gcd_flute.py @@ -7,7 +7,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) gcddef = os.path.join(test_path, "gcd.def") design.readDef(gcddef) gr = design.getGlobalRouter() diff --git a/src/grt/test/macro_obs_not_aligned.py b/src/grt/test/macro_obs_not_aligned.py index 0a5cda8f794..1d638717790 100644 --- a/src/grt/test/macro_obs_not_aligned.py +++ b/src/grt/test/macro_obs_not_aligned.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("macro_obs_not_aligned.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("macro_obs_not_aligned.def") gr = design.getGlobalRouter() diff --git a/src/grt/test/multiple_calls.py b/src/grt/test/multiple_calls.py index d463492a0aa..2fe04955143 100644 --- a/src/grt/test/multiple_calls.py +++ b/src/grt/test/multiple_calls.py @@ -4,7 +4,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("multiple_calls.def") guide_file1 = helpers.make_result_file("mc1_route.guide") diff --git a/src/grt/test/ndr_1w_3s.py b/src/grt/test/ndr_1w_3s.py index 0879e73d041..425f91e9931 100644 --- a/src/grt/test/ndr_1w_3s.py +++ b/src/grt/test/ndr_1w_3s.py @@ -7,7 +7,7 @@ tech.readLef("sky130hs/sky130hs.tlef") tech.readLef("sky130hs/sky130hs_std_cell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("clock_route.def") gr = design.getGlobalRouter() diff --git a/src/grt/test/obs_out_of_die.py b/src/grt/test/obs_out_of_die.py index 2c9a5c52f72..b0e581b1920 100644 --- a/src/grt/test/obs_out_of_die.py +++ b/src/grt/test/obs_out_of_die.py @@ -7,7 +7,7 @@ tech.readLef("sky130hs/sky130hs.tlef") tech.readLef("sky130hs/sky130hs_std_cell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("obs_out_of_die.def") gr = design.getGlobalRouter() diff --git a/src/grt/test/pd1.py b/src/grt/test/pd1.py index e6774671745..aeffe37395a 100644 --- a/src/grt/test/pd1.py +++ b/src/grt/test/pd1.py @@ -8,7 +8,7 @@ tech.readLef("sky130hs/sky130hs.tlef") tech.readLef("sky130hs/sky130hs_std_cell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("clock_route.def") design.evalTclString( diff --git a/src/grt/test/pin_access1.py b/src/grt/test/pin_access1.py index 209f9972371..c31445b900e 100644 --- a/src/grt/test/pin_access1.py +++ b/src/grt/test/pin_access1.py @@ -8,7 +8,7 @@ tech.readLef("sky130hs/sky130hs.tlef") tech.readLef("sky130hs/sky130hs_std_cell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("clock_route.def") gr = design.getGlobalRouter() diff --git a/src/grt/test/pre_routed1.py b/src/grt/test/pre_routed1.py index f3d4eb13c76..9c0e9057b62 100644 --- a/src/grt/test/pre_routed1.py +++ b/src/grt/test/pre_routed1.py @@ -8,7 +8,7 @@ tech.readLef("sky130hs/sky130hs.tlef") tech.readLef("sky130hs/sky130hs_std_cell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("pre_routed1.def") gr = design.getGlobalRouter() diff --git a/src/grt/test/region_adjustment.py b/src/grt/test/region_adjustment.py index 8028abdb984..96262de4996 100644 --- a/src/grt/test/region_adjustment.py +++ b/src/grt/test/region_adjustment.py @@ -6,7 +6,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("region_adjustment.def") gr = design.getGlobalRouter() diff --git a/src/grt/test/repair_antennas1.py b/src/grt/test/repair_antennas1.py index b3c552853d5..7b51ac393cf 100644 --- a/src/grt/test/repair_antennas1.py +++ b/src/grt/test/repair_antennas1.py @@ -7,7 +7,7 @@ tech.readLef("sky130hs/sky130hs.tlef") tech.readLef("sky130hs/sky130hs_std_cell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd_sky130.def") gr = design.getGlobalRouter() diff --git a/src/grt/test/tracks1.py b/src/grt/test/tracks1.py index c3db3a99e15..051dbbb281b 100644 --- a/src/grt/test/tracks1.py +++ b/src/grt/test/tracks1.py @@ -8,7 +8,7 @@ tech.readLef("sky130hs/sky130hs.tlef") tech.readLef("sky130hs/sky130hs_std_cell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("tracks1.def") gr = design.getGlobalRouter() diff --git a/src/ifp/include/ifp/InitFloorplan.hh b/src/ifp/include/ifp/InitFloorplan.hh index 05369bfce2d..15c80e801e9 100644 --- a/src/ifp/include/ifp/InitFloorplan.hh +++ b/src/ifp/include/ifp/InitFloorplan.hh @@ -65,6 +65,7 @@ enum class RowParity class InitFloorplan { public: + InitFloorplan() = default; // only for swig InitFloorplan(odb::dbBlock* block, Logger* logger, sta::dbNetwork* network); // utilization is in [0, 100]% @@ -131,9 +132,9 @@ class InitFloorplan void updateVoltageDomain(int core_lx, int core_ly, int core_ux, int core_uy); void addUsedSites(std::map& sites_by_name) const; - odb::dbBlock* block_; - Logger* logger_; - sta::dbNetwork* network_; + odb::dbBlock* block_{nullptr}; + Logger* logger_{nullptr}; + sta::dbNetwork* network_{nullptr}; // this is a set of sets of all constructed site ids. std::set> constructed_patterns_; diff --git a/src/ifp/src/InitFloorplan.i b/src/ifp/src/InitFloorplan.i index 2006a5f20fd..31408fffe54 100644 --- a/src/ifp/src/InitFloorplan.i +++ b/src/ifp/src/InitFloorplan.i @@ -38,6 +38,7 @@ #include "db_sta/dbSta.hh" #include "ifp/InitFloorplan.hh" #include "ord/OpenRoad.hh" +#include "ord/Design.h" #include "utl/Logger.h" // Defined by OpenRoad.i @@ -57,19 +58,6 @@ static utl::Logger* getLogger() { return ord::OpenRoad::openRoad()->getLogger(); } -static ifp::InitFloorplan get_floorplan() -{ - auto app = ord::getOpenRoad(); - auto chip = app->getDb()->getChip(); - auto logger = app->getLogger(); - if (!chip || !chip->getBlock()) { - logger->error(utl::IFP, 38, "No design is loaded."); - } - auto block = chip->getBlock(); - auto network = app->getDbNetwork(); - return ifp::InitFloorplan(block, logger, network); -} - %} //////////////////////////////////////////////////////////////// @@ -82,6 +70,7 @@ static ifp::InitFloorplan get_floorplan() %import %import "dbtypes.i" %include "../../Exception.i" +%include "../../Design.i" %typemap(in) ifp::RowParity { char *str = Tcl_GetStringFromObj($input, 0); @@ -101,7 +90,8 @@ static ifp::InitFloorplan get_floorplan() namespace ifp { void -init_floorplan_core(int die_lx, +init_floorplan_core(ord::Design* design, + int die_lx, int die_ly, int die_ux, int die_uy, @@ -116,13 +106,14 @@ init_floorplan_core(int die_lx, { std::set flipped_sites_set(flipped_sites.begin(), flipped_sites.end()); - get_floorplan().initFloorplan({die_lx, die_ly, die_ux, die_uy}, + design->getFloorplan().initFloorplan({die_lx, die_ly, die_ux, die_uy}, {core_lx, core_ly, core_ux, core_uy}, site, additional_sites, row_parity, flipped_sites_set); } void -init_floorplan_util(double util, +init_floorplan_util(ord::Design* design, + double util, double aspect_ratio, int core_space_bottom, int core_space_top, @@ -135,7 +126,7 @@ init_floorplan_util(double util, { std::set flipped_sites_set(flipped_sites.begin(), flipped_sites.end()); - get_floorplan().initFloorplan(util, aspect_ratio, + design->getFloorplan().initFloorplan(util, aspect_ratio, core_space_bottom, core_space_top, core_space_left, core_space_right, site, additional_sites, row_parity, @@ -143,30 +134,34 @@ init_floorplan_util(double util, } void -insert_tiecells_cmd(odb::dbMTerm* tie_term, const char* prefix) +insert_tiecells_cmd(ord::Design* design, + odb::dbMTerm* tie_term, const char* prefix) { - get_floorplan().insertTiecells(tie_term, prefix); + design->getFloorplan().insertTiecells(tie_term, prefix); } void -make_layer_tracks() +make_layer_tracks(ord::Design* design) { - get_floorplan().makeTracks(); + design->getFloorplan().makeTracks(); } void -make_layer_tracks(odb::dbTechLayer* layer, +make_layer_tracks(ord::Design* design, + odb::dbTechLayer* layer, int x_offset, int x_pitch, int y_offset, int y_pitch) { - get_floorplan().makeTracks(layer, x_offset, x_pitch, y_offset, y_pitch); + design->getFloorplan().makeTracks(layer, x_offset, x_pitch, + y_offset, y_pitch); } -odb::dbSite* find_site(const char* site_name) +odb::dbSite* find_site(ord::Design* design, + const char* site_name) { - auto site = get_floorplan().findSite(site_name); + auto site = design->getFloorplan().findSite(site_name); if (!site) { getLogger()->error(utl::IFP, 18, "Unable to find site: {}", site_name); } diff --git a/src/ifp/test/ifp_helpers.py b/src/ifp/test/ifp_helpers.py index 00670f77cc1..b0e0d0f7bf8 100644 --- a/src/ifp/test/ifp_helpers.py +++ b/src/ifp/test/ifp_helpers.py @@ -42,20 +42,18 @@ def __init__(self, msg): # To be removed once we have UPF support -def create_voltage_domain(domain_name, area): +def create_voltage_domain(design, domain_name, area): # which flavor of error reporting should be used here? if len(area) != 4: raise IFPError("utl::error ODB 315 '-area is a list of 4 coordinates'") - db = ord.get_db() - chip = db.getChip() + block = design.getBlock() - if chip == None: + if block == None: raise IFPError( "utl::error ODB 317 'please load the design before trying to use this command'" ) - block = chip.getBlock() region = odb.dbRegion_create(block, domain_name) if region == None: @@ -71,13 +69,13 @@ def create_voltage_domain(domain_name, area): group.setType("VOLTAGE_DOMAIN") -def insert_tiecells(floorplan, args, prefix=None): +def insert_tiecells(tech, floorplan, args, prefix=None): tie_pin_split = args.split("/") port = tie_pin_split[-1] tie_cell = "/".join(tie_pin_split[0:-1]) master = None - db = ord.get_db() + db = tech.getDB() for lib in db.getLibs(): master = lib.findMaster(tie_cell) diff --git a/src/ifp/test/init_floorplan8.py b/src/ifp/test/init_floorplan8.py index 6cd5cb11d25..16cb7a19b01 100644 --- a/src/ifp/test/init_floorplan8.py +++ b/src/ifp/test/init_floorplan8.py @@ -17,7 +17,7 @@ l = design.micronToDBU(27) u = design.micronToDBU(60) -ifph.create_voltage_domain("TEMP_ANALOG", (l, l, u, u)) +ifph.create_voltage_domain(design, "TEMP_ANALOG", (l, l, u, u)) floorplan = design.getFloorplan() site = floorplan.findSite("FreePDK45_38x28_10R_NP_162NW_34O") diff --git a/src/ifp/test/init_floorplan9.py b/src/ifp/test/init_floorplan9.py index 687c97363d1..c4f6c8e5e5f 100644 --- a/src/ifp/test/init_floorplan9.py +++ b/src/ifp/test/init_floorplan9.py @@ -21,7 +21,7 @@ ux = design.micronToDBU(64.86) uy = design.micronToDBU(62.56) -ifph.create_voltage_domain("TEMP_ANALOG", (lx, ly, ux, uy)) +ifph.create_voltage_domain(design, "TEMP_ANALOG", (lx, ly, ux, uy)) floorplan.initFloorplan(die, core, floorplan.findSite("unithd")) diff --git a/src/ifp/test/make_tracks2.py b/src/ifp/test/make_tracks2.py index 19ee66dc221..7906693c5cb 100644 --- a/src/ifp/test/make_tracks2.py +++ b/src/ifp/test/make_tracks2.py @@ -18,7 +18,7 @@ floorplan.findSite("FreePDK45_38x28_10R_NP_162NW_34O"), ) -db_tech = ord.get_db_tech() +db_tech = tech.getTech() m1 = db_tech.findLayer("metal1") m2 = db_tech.findLayer("metal2") diff --git a/src/ifp/test/make_tracks3.py b/src/ifp/test/make_tracks3.py index a95002bdf50..27700eb97f5 100644 --- a/src/ifp/test/make_tracks3.py +++ b/src/ifp/test/make_tracks3.py @@ -18,7 +18,7 @@ floorplan.findSite("FreePDK45_38x28_10R_NP_162NW_34O"), ) -db_tech = ord.get_db_tech() +db_tech = tech.getTech() m1 = db_tech.findLayer("metal1") m2 = db_tech.findLayer("metal2") diff --git a/src/ifp/test/make_tracks4.py b/src/ifp/test/make_tracks4.py index e70bb4e93f3..d1bb62d494d 100644 --- a/src/ifp/test/make_tracks4.py +++ b/src/ifp/test/make_tracks4.py @@ -18,7 +18,7 @@ floorplan.findSite("FreePDK45_38x28_10R_NP_162NW_34O"), ) -db_tech = ord.get_db_tech() +db_tech = tech.getTech() m2 = db_tech.findLayer("metal2") x_offset = design.micronToDBU(300) diff --git a/src/ifp/test/make_tracks5.py b/src/ifp/test/make_tracks5.py index 153cf2dbfc0..135e63f807e 100644 --- a/src/ifp/test/make_tracks5.py +++ b/src/ifp/test/make_tracks5.py @@ -18,7 +18,7 @@ floorplan.findSite("FreePDK45_38x28_10R_NP_162NW_34O"), ) -db_tech = ord.get_db_tech() +db_tech = tech.getTech() m1 = db_tech.findLayer("metal1") x_offset = design.micronToDBU(0.1) diff --git a/src/ifp/test/placement_blockage1.py b/src/ifp/test/placement_blockage1.py index 93ce12723be..18db3e982ab 100644 --- a/src/ifp/test/placement_blockage1.py +++ b/src/ifp/test/placement_blockage1.py @@ -11,8 +11,8 @@ design.readVerilog("reg1.v") design.link("top") -odb.dbBlockage_create(ord.get_db_block(), 0, 0, 1000000, 208400) -odb.dbBlockage_create(ord.get_db_block(), 0, 508400, 1000000, 708400) +odb.dbBlockage_create(design.getBlock(), 0, 0, 1000000, 208400) +odb.dbBlockage_create(design.getBlock(), 0, 508400, 1000000, 708400) floorplan = design.getFloorplan() floorplan.initFloorplan( diff --git a/src/ifp/test/placement_blockage2.py b/src/ifp/test/placement_blockage2.py index 2c4a4ef9dda..e733ae6a1ee 100644 --- a/src/ifp/test/placement_blockage2.py +++ b/src/ifp/test/placement_blockage2.py @@ -11,7 +11,7 @@ design.readVerilog("reg1.v") design.link("top") -odb.dbBlockage_create(ord.get_db_block(), 0, 0, 2000000, 208400) +odb.dbBlockage_create(design.getBlock(), 0, 0, 2000000, 208400) floorplan = design.getFloorplan() floorplan.initFloorplan( diff --git a/src/ifp/test/tiecells.py b/src/ifp/test/tiecells.py index c33c580723d..6f3828b9e4b 100644 --- a/src/ifp/test/tiecells.py +++ b/src/ifp/test/tiecells.py @@ -19,8 +19,8 @@ ) -ifp_helpers.insert_tiecells(floorplan, "LOGIC0_X1/Z", "TIE_ZERO_") -ifp_helpers.insert_tiecells(floorplan, "LOGIC1_X1/Z") +ifp_helpers.insert_tiecells(tech, floorplan, "LOGIC0_X1/Z", "TIE_ZERO_") +ifp_helpers.insert_tiecells(tech, floorplan, "LOGIC1_X1/Z") def_file = helpers.make_result_file("tiecells.def") design.writeDef(def_file) diff --git a/src/mpl/test/east_west1.py b/src/mpl/test/east_west1.py index 4382071d582..32fba61a3f9 100644 --- a/src/mpl/test/east_west1.py +++ b/src/mpl/test/east_west1.py @@ -9,7 +9,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLef("Nangate45/fakeram45_64x7.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("east_west1.def") design.evalTclString('read_sdc "gcd.sdc"') diff --git a/src/mpl/test/east_west2.py b/src/mpl/test/east_west2.py index 0ccbce8f4dc..7b95ef877ef 100644 --- a/src/mpl/test/east_west2.py +++ b/src/mpl/test/east_west2.py @@ -9,7 +9,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLef("Nangate45/fakeram45_64x7.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("east_west1.def") # This appears to be the only difference from east_west1, ie, we do not diff --git a/src/mpl/test/level3_01.py b/src/mpl/test/level3_01.py index f9fdbe45de9..3815362a3a2 100644 --- a/src/mpl/test/level3_01.py +++ b/src/mpl/test/level3_01.py @@ -9,7 +9,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLef("Nangate45/fakeram45_64x7.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("level3.def") design.evalTclString('read_sdc "gcd.sdc"') diff --git a/src/mpl/test/level3_02.py b/src/mpl/test/level3_02.py index edbed2e8bd9..3d209257d6c 100644 --- a/src/mpl/test/level3_02.py +++ b/src/mpl/test/level3_02.py @@ -10,7 +10,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLef("Nangate45/fakeram45_64x7.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("level3.def") design.evalTclString('read_sdc "gcd.sdc"') diff --git a/src/mpl/test/snap_layer1.py b/src/mpl/test/snap_layer1.py index 1e7cd3773dc..3ba41f237f7 100644 --- a/src/mpl/test/snap_layer1.py +++ b/src/mpl/test/snap_layer1.py @@ -9,7 +9,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLef("Nangate45/fakeram45_64x7.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("east_west1.def") mpl_aux.macro_placement(design, snap_layer=3, halo=[1.0, 1.0]) diff --git a/src/par/test/partition_gcd.py b/src/par/test/partition_gcd.py index 70a8abd5930..f7e02b9ad3e 100644 --- a/src/par/test/partition_gcd.py +++ b/src/par/test/partition_gcd.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLiberty("Nangate45/Nangate45_typ.lib") tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("gcd.v") design.link("gcd") diff --git a/src/pdn/test/asap7_taper.py b/src/pdn/test/asap7_taper.py index e14502dedf5..57066843f52 100644 --- a/src/pdn/test/asap7_taper.py +++ b/src/pdn/test/asap7_taper.py @@ -7,7 +7,7 @@ tech.readLef("asap7_vias/asap7_tech_1x.lef") tech.readLef("asap7_vias/asap7sc7p5t_27_R_1x.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("asap7_vias/floorplan.def") pdn_aux.add_global_connection(design, net_name="VDD", pin_pattern="^VDD$", power=True) diff --git a/src/pdn/test/core_grid.py b/src/pdn/test/core_grid.py index 8a402f62927..e3872d93b05 100644 --- a/src/pdn/test/core_grid.py +++ b/src/pdn/test/core_grid.py @@ -7,7 +7,7 @@ tech.readLef("Nangate45/Nangate45_tech.lef") tech.readLef("Nangate45/Nangate45_stdcell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("nangate_gcd/floorplan.def") pdngen = design.getPdnGen() diff --git a/src/pdn/test/core_grid_with_rings.py b/src/pdn/test/core_grid_with_rings.py index 20202a232de..7938179106e 100644 --- a/src/pdn/test/core_grid_with_rings.py +++ b/src/pdn/test/core_grid_with_rings.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("nangate_gcd/floorplan.def") pdn_aux.add_global_connection(design, net_name="VDD", pin_pattern="VDD", power=True) diff --git a/src/pdn/test/core_grid_with_routing_obstructions.py b/src/pdn/test/core_grid_with_routing_obstructions.py index ab83e15088b..7362d130a84 100644 --- a/src/pdn/test/core_grid_with_routing_obstructions.py +++ b/src/pdn/test/core_grid_with_routing_obstructions.py @@ -6,7 +6,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("nangate_gcd/floorplan.def") pdngen = design.getPdnGen() diff --git a/src/pdn/test/existing.py b/src/pdn/test/existing.py index 637f6fecceb..989c17d31db 100644 --- a/src/pdn/test/existing.py +++ b/src/pdn/test/existing.py @@ -6,7 +6,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLef("nangate_macros/fakeram45_64x32.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("nangate_existing/floorplan.def") diff --git a/src/pdn/test/macros.py b/src/pdn/test/macros.py index 7dbd25d81b5..07b693b8a00 100644 --- a/src/pdn/test/macros.py +++ b/src/pdn/test/macros.py @@ -7,7 +7,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLef("nangate_macros/fakeram45_64x32.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("nangate_macros/floorplan.def") pdn_aux.add_global_connection(design, net_name="VDD", pin_pattern="^VDD$", power=True) diff --git a/src/pdn/test/max_width.py b/src/pdn/test/max_width.py index 1d00928ee5e..ca6ad659b69 100644 --- a/src/pdn/test/max_width.py +++ b/src/pdn/test/max_width.py @@ -7,7 +7,7 @@ tech.readLef("asap7_vias/asap7_tech_1x.lef") tech.readLef("asap7_vias/asap7sc7p5t_27_R_1x.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("asap7_vias/floorplan.def") pdngen = design.getPdnGen() diff --git a/src/pdn/test/min_width.py b/src/pdn/test/min_width.py index 7485088be02..6a3516e781b 100644 --- a/src/pdn/test/min_width.py +++ b/src/pdn/test/min_width.py @@ -6,7 +6,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("nangate_gcd/floorplan.def") pdngen = design.getPdnGen() diff --git a/src/pdn/test/offgrid.py b/src/pdn/test/offgrid.py index df507f0027d..d455b38cba8 100644 --- a/src/pdn/test/offgrid.py +++ b/src/pdn/test/offgrid.py @@ -6,7 +6,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("nangate_gcd/floorplan.def") pdn_aux.add_global_connection(design, net_name="VDD", pin_pattern="VDD", power=True) diff --git a/src/pdn/test/power_switch.py b/src/pdn/test/power_switch.py index 36dd877ddba..cfd6b996623 100644 --- a/src/pdn/test/power_switch.py +++ b/src/pdn/test/power_switch.py @@ -8,7 +8,7 @@ tech.readLef("sky130hd/sky130_fd_sc_hd_merged.lef") tech.readLef("sky130_power_switch/power_switch.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("sky130_power_switch/floorplan.def") pdn_aux.add_global_connection(design, net_name="VDD", power=True, pin_pattern="^VDDG$") diff --git a/src/pdn/test/repair_vias.py b/src/pdn/test/repair_vias.py index 62c111fb512..27f18c3ad12 100644 --- a/src/pdn/test/repair_vias.py +++ b/src/pdn/test/repair_vias.py @@ -6,7 +6,7 @@ tech = Tech() tech.readLef("asap7_vias/asap7_tech_1x_noviarules.lef") tech.readLef("asap7_vias/asap7sc7p5t_27_R_1x.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("asap7_vias/floorplan_repair.def") pdn_aux.repair_pdn_vias(design, all=True) diff --git a/src/pdn/test/report.py b/src/pdn/test/report.py index eb9e1b90360..2c495191ae7 100644 --- a/src/pdn/test/report.py +++ b/src/pdn/test/report.py @@ -6,7 +6,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLef("nangate_bsg_black_parrot/dummy_pads.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("nangate_bsg_black_parrot/floorplan.def") pdngen = design.getPdnGen() diff --git a/src/pdn/test/reset.py b/src/pdn/test/reset.py index 17a11eeaecb..f9ecec19a36 100644 --- a/src/pdn/test/reset.py +++ b/src/pdn/test/reset.py @@ -7,7 +7,7 @@ tech.readLef("Nangate45/Nangate45_tech.lef") tech.readLef("Nangate45/Nangate45_stdcell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("nangate_gcd/floorplan.def") pdngen = design.getPdnGen() diff --git a/src/pdn/test/ripup.py b/src/pdn/test/ripup.py index 0c0ce86a8d9..daa0f26f0c8 100644 --- a/src/pdn/test/ripup.py +++ b/src/pdn/test/ripup.py @@ -6,7 +6,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("nangate_gcd/floorplan_with_grid.def") pdngen = design.getPdnGen() diff --git a/src/pdn/test/widthtable.py b/src/pdn/test/widthtable.py index 4b1ad3ece39..2244215c4a8 100644 --- a/src/pdn/test/widthtable.py +++ b/src/pdn/test/widthtable.py @@ -6,7 +6,7 @@ tech.readLef("asap7_vias/asap7_tech_1x_noviarules.lef") tech.readLef("asap7_vias/asap7sc7p5t_27_R_1x.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("asap7_vias/floorplan.def") pdn_aux.add_global_connection(design, net_name="VDD", pin_pattern="^VDD$", power=True) diff --git a/src/ppl/test/add_constraint1.py b/src/ppl/test/add_constraint1.py index 37c5c59c589..2caea7b930c 100644 --- a/src/ppl/test/add_constraint1.py +++ b/src/ppl/test/add_constraint1.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.set_io_pin_constraint(design, direction="INPUT", region="top:*") diff --git a/src/ppl/test/add_constraint10.py b/src/ppl/test/add_constraint10.py index db260339556..d708ec26acb 100644 --- a/src/ppl/test/add_constraint10.py +++ b/src/ppl/test/add_constraint10.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") design.evalTclString( diff --git a/src/ppl/test/add_constraint2.py b/src/ppl/test/add_constraint2.py index cf03a354b80..9c74d44a764 100644 --- a/src/ppl/test/add_constraint2.py +++ b/src/ppl/test/add_constraint2.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.set_io_pin_constraint(design, direction="INPUT", region="bottom:*") diff --git a/src/ppl/test/add_constraint3.py b/src/ppl/test/add_constraint3.py index 07419997579..8b73ff6bee0 100644 --- a/src/ppl/test/add_constraint3.py +++ b/src/ppl/test/add_constraint3.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.set_io_pin_constraint(design, direction="INPUT", region="left:*") diff --git a/src/ppl/test/add_constraint4.py b/src/ppl/test/add_constraint4.py index 70c33e2a73f..d322fa3e637 100644 --- a/src/ppl/test/add_constraint4.py +++ b/src/ppl/test/add_constraint4.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.set_io_pin_constraint(design, direction="INPUT", region="right:*") diff --git a/src/ppl/test/add_constraint7.py b/src/ppl/test/add_constraint7.py index 04282c92be4..79cfa32972b 100644 --- a/src/ppl/test/add_constraint7.py +++ b/src/ppl/test/add_constraint7.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.set_io_pin_constraint( diff --git a/src/ppl/test/add_constraint8.py b/src/ppl/test/add_constraint8.py index af3e62da0d6..a8c1f370ad1 100644 --- a/src/ppl/test/add_constraint8.py +++ b/src/ppl/test/add_constraint8.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") design.evalTclString("set_io_pin_constraint -pin_names {req_msg*} -region bottom:0-18") diff --git a/src/ppl/test/add_constraint9.py b/src/ppl/test/add_constraint9.py index 9fbdee76a7d..bc966cfc167 100644 --- a/src/ppl/test/add_constraint9.py +++ b/src/ppl/test/add_constraint9.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") design.evalTclString( diff --git a/src/ppl/test/blocked_region.py b/src/ppl/test/blocked_region.py index 8d42f17dc21..2abaccff128 100644 --- a/src/ppl/test/blocked_region.py +++ b/src/ppl/test/blocked_region.py @@ -8,7 +8,7 @@ tech.readLef("sky130hd/sky130_fd_sc_hd_merged.lef") tech.readLef("blocked_region.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("blocked_region.def") ppl_aux.place_pins(design, hor_layers="met3", ver_layers="met2", random=True) diff --git a/src/ppl/test/exclude1.py b/src/ppl/test/exclude1.py index 1bf3264830d..d659f3a6be5 100644 --- a/src/ppl/test/exclude1.py +++ b/src/ppl/test/exclude1.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") diff --git a/src/ppl/test/exclude2.py b/src/ppl/test/exclude2.py index 7eb948cbafa..8a6ed9a7d7d 100644 --- a/src/ppl/test/exclude2.py +++ b/src/ppl/test/exclude2.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") diff --git a/src/ppl/test/exclude3.py b/src/ppl/test/exclude3.py index e12bab8338f..1150728a8f4 100644 --- a/src/ppl/test/exclude3.py +++ b/src/ppl/test/exclude3.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") diff --git a/src/ppl/test/gcd.py b/src/ppl/test/gcd.py index f727378d261..ef311b8342a 100644 --- a/src/ppl/test/gcd.py +++ b/src/ppl/test/gcd.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.place_pins( diff --git a/src/ppl/test/group_pins1.py b/src/ppl/test/group_pins1.py index 8fa1328c110..dbe60baa119 100644 --- a/src/ppl/test/group_pins1.py +++ b/src/ppl/test/group_pins1.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.place_pins( diff --git a/src/ppl/test/group_pins2.py b/src/ppl/test/group_pins2.py index 994801c7036..f5550d9f7e3 100644 --- a/src/ppl/test/group_pins2.py +++ b/src/ppl/test/group_pins2.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.place_pins( diff --git a/src/ppl/test/group_pins3.py b/src/ppl/test/group_pins3.py index e7d46aad13a..a8e1c232c97 100644 --- a/src/ppl/test/group_pins3.py +++ b/src/ppl/test/group_pins3.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("group_pins3.def") ppl_aux.place_pins( diff --git a/src/ppl/test/group_pins7.py b/src/ppl/test/group_pins7.py index 87e3cd12c27..7b872e3084c 100644 --- a/src/ppl/test/group_pins7.py +++ b/src/ppl/test/group_pins7.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("group_pins3.def") diff --git a/src/ppl/test/group_pins8.py b/src/ppl/test/group_pins8.py index 228b8a4c95c..49474ed7f30 100644 --- a/src/ppl/test/group_pins8.py +++ b/src/ppl/test/group_pins8.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.set_io_pin_constraint(design, pin_names="resp_val resp_rdy req_rdy", group=True) diff --git a/src/ppl/test/group_pins9.py b/src/ppl/test/group_pins9.py index fb671369d19..04e33f29e4b 100644 --- a/src/ppl/test/group_pins9.py +++ b/src/ppl/test/group_pins9.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.set_io_pin_constraint( diff --git a/src/ppl/test/min_dist_in_tracks1.py b/src/ppl/test/min_dist_in_tracks1.py index 1a9e72d7c11..df99a6514cb 100644 --- a/src/ppl/test/min_dist_in_tracks1.py +++ b/src/ppl/test/min_dist_in_tracks1.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.place_pins( diff --git a/src/ppl/test/multi_layers.py b/src/ppl/test/multi_layers.py index a6e91055940..72d66b427f5 100644 --- a/src/ppl/test/multi_layers.py +++ b/src/ppl/test/multi_layers.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.place_pins( diff --git a/src/ppl/test/multiple_calls.py b/src/ppl/test/multiple_calls.py index ca2f2409364..4a0789f778c 100644 --- a/src/ppl/test/multiple_calls.py +++ b/src/ppl/test/multiple_calls.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.place_pins( diff --git a/src/ppl/test/place_pin1.py b/src/ppl/test/place_pin1.py index 9e707498f44..21a677cfb0e 100644 --- a/src/ppl/test/place_pin1.py +++ b/src/ppl/test/place_pin1.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.place_pin( diff --git a/src/ppl/test/place_pin2.py b/src/ppl/test/place_pin2.py index 180dd93dc53..333690705ea 100644 --- a/src/ppl/test/place_pin2.py +++ b/src/ppl/test/place_pin2.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.place_pin( diff --git a/src/ppl/test/random1.py b/src/ppl/test/random1.py index a59bc27e10a..d93f1e480a8 100644 --- a/src/ppl/test/random1.py +++ b/src/ppl/test/random1.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.place_pins(design, hor_layers="metal3", ver_layers="metal2", random=True) diff --git a/src/ppl/test/random2.py b/src/ppl/test/random2.py index 815b5f9d563..0d48074589d 100644 --- a/src/ppl/test/random2.py +++ b/src/ppl/test/random2.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.place_pins( diff --git a/src/ppl/test/random3.py b/src/ppl/test/random3.py index 80483a8706d..64d8af78fb5 100644 --- a/src/ppl/test/random3.py +++ b/src/ppl/test/random3.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.set_io_pin_constraint(design, direction="INPUT", region="top:*") diff --git a/src/ppl/test/random4.py b/src/ppl/test/random4.py index d42c1815fdf..c607aa5d9c5 100644 --- a/src/ppl/test/random4.py +++ b/src/ppl/test/random4.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.set_io_pin_constraint( diff --git a/src/ppl/test/random7.py b/src/ppl/test/random7.py index dad0b94c77d..2886c638d4d 100644 --- a/src/ppl/test/random7.py +++ b/src/ppl/test/random7.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.place_pins( diff --git a/src/ppl/test/top_layer1.py b/src/ppl/test/top_layer1.py index 9694784f777..10b8a423647 100644 --- a/src/ppl/test/top_layer1.py +++ b/src/ppl/test/top_layer1.py @@ -8,7 +8,7 @@ tech.readLef("sky130hd/sky130_fd_sc_hd_merged.lef") tech.readLef("blocked_region.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("blocked_region.def") ppl_aux.define_pin_shape_pattern( diff --git a/src/ppl/test/top_layer2.py b/src/ppl/test/top_layer2.py index 46d4a469927..09949731bfe 100644 --- a/src/ppl/test/top_layer2.py +++ b/src/ppl/test/top_layer2.py @@ -8,7 +8,7 @@ tech.readLef("sky130hd/sky130_fd_sc_hd_merged.lef") tech.readLef("blocked_region.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("blocked_region.def") ppl_aux.define_pin_shape_pattern( diff --git a/src/ppl/test/top_layer3.py b/src/ppl/test/top_layer3.py index 0aed7c328eb..529c85fb235 100644 --- a/src/ppl/test/top_layer3.py +++ b/src/ppl/test/top_layer3.py @@ -6,7 +6,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") ppl_aux.define_pin_shape_pattern( diff --git a/src/psm/test/aes_asap7_vdd.py b/src/psm/test/aes_asap7_vdd.py index 464de80f440..9e8bcb7c47b 100644 --- a/src/psm/test/aes_asap7_vdd.py +++ b/src/psm/test/aes_asap7_vdd.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("asap7/asap7_tech_1x_201209.lef") tech.readLef("asap7/asap7sc7p5t_28_R_1x_220121a.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("asap7_data/aes_place.def") tech.readLiberty("asap7_data/asap7.lib") diff --git a/src/psm/test/aes_test_vdd.py b/src/psm/test/aes_test_vdd.py index e51f31be197..c8c5131bb33 100644 --- a/src/psm/test/aes_test_vdd.py +++ b/src/psm/test/aes_test_vdd.py @@ -6,7 +6,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("Nangate45_data/aes.def") design.evalTclString("read_sdc Nangate45_data/aes.sdc") diff --git a/src/psm/test/aes_test_vss.py b/src/psm/test/aes_test_vss.py index c9f360b2b5a..eb1a696b00f 100644 --- a/src/psm/test/aes_test_vss.py +++ b/src/psm/test/aes_test_vss.py @@ -6,7 +6,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("Nangate45_data/aes.def") design.evalTclString("read_sdc Nangate45_data/aes.sdc") diff --git a/src/psm/test/gcd_em_test_vdd.py b/src/psm/test/gcd_em_test_vdd.py index f61ae097b70..12860241355 100644 --- a/src/psm/test/gcd_em_test_vdd.py +++ b/src/psm/test/gcd_em_test_vdd.py @@ -6,7 +6,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("Nangate45_data/gcd.def") design.evalTclString("read_sdc Nangate45_data/gcd.sdc") diff --git a/src/psm/test/gcd_no_vsrc.py b/src/psm/test/gcd_no_vsrc.py index f3d985c0ead..cbb291732ef 100644 --- a/src/psm/test/gcd_no_vsrc.py +++ b/src/psm/test/gcd_no_vsrc.py @@ -6,7 +6,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("Nangate45_data/gcd.def") design.evalTclString("read_sdc Nangate45_data/gcd.sdc") diff --git a/src/psm/test/gcd_sky130_vdd.py b/src/psm/test/gcd_sky130_vdd.py index df1793f8f02..71ae82c8b8e 100644 --- a/src/psm/test/gcd_sky130_vdd.py +++ b/src/psm/test/gcd_sky130_vdd.py @@ -7,7 +7,7 @@ tech.readLef("sky130hd/sky130hd_std_cell.lef") tech.readLiberty("sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("sky130hd_data/gcd_sky130hd_floorplan.def") design.evalTclString("read_sdc sky130hd_data/gcd_sky130hd_floorplan.sdc") diff --git a/src/psm/test/gcd_test_vdd.py b/src/psm/test/gcd_test_vdd.py index 1c0375948ae..ca970677902 100644 --- a/src/psm/test/gcd_test_vdd.py +++ b/src/psm/test/gcd_test_vdd.py @@ -6,7 +6,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("Nangate45_data/gcd.def") design.evalTclString("read_sdc Nangate45_data/gcd.sdc") diff --git a/src/psm/test/gcd_vss_no_vsrc.py b/src/psm/test/gcd_vss_no_vsrc.py index ec7f8165438..79c59492511 100644 --- a/src/psm/test/gcd_vss_no_vsrc.py +++ b/src/psm/test/gcd_vss_no_vsrc.py @@ -6,7 +6,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("Nangate45_data/gcd.def") design.evalTclString("read_sdc Nangate45_data/gcd.sdc") diff --git a/src/psm/test/gcd_write_sp_test_vdd.py b/src/psm/test/gcd_write_sp_test_vdd.py index f2a7d891740..612778a63f8 100644 --- a/src/psm/test/gcd_write_sp_test_vdd.py +++ b/src/psm/test/gcd_write_sp_test_vdd.py @@ -6,7 +6,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("Nangate45_data/gcd.def") design.evalTclString("read_sdc Nangate45_data/gcd.sdc") diff --git a/src/rcx/include/rcx/ext.h b/src/rcx/include/rcx/ext.h index b3d4798092a..addc967e411 100644 --- a/src/rcx/include/rcx/ext.h +++ b/src/rcx/include/rcx/ext.h @@ -51,11 +51,10 @@ class Ext Ext(); ~Ext() = default; - void init( - odb::dbDatabase* db, - Logger* logger, - const char* spef_version, - const std::function& rcx_init = []() {}); + void init(odb::dbDatabase* db, + Logger* logger, + const char* spef_version, + const std::function& rcx_init); void setLogger(Logger* logger); void write_rules(const std::string& name, @@ -109,8 +108,8 @@ class Ext { const char* debug_net = nullptr; const char* ext_model_file = nullptr; - const char* const net = nullptr; - const int cc_up = 2; + const char* net = nullptr; + static constexpr int cc_up = 2; int corner_cnt = 1; double max_res = 50.0; bool no_merge_via_res = false; diff --git a/src/rcx/src/ext-py.i b/src/rcx/src/ext-py.i index b2f013f4477..586c4d435f0 100644 --- a/src/rcx/src/ext-py.i +++ b/src/rcx/src/ext-py.i @@ -40,7 +40,13 @@ using namespace odb; using rcx::Ext; %} +%include %include "../../Exception-py.i" +%import "odb/odb.h" +// Python doesn't supported nested classes so this is +// required to make them available. +%feature ("flatnested"); +%include "rcx/ext.h" // Just reuse the api defined in ext.i %inline %{ diff --git a/src/rcx/src/ext.i b/src/rcx/src/ext.i index 21b12466fd1..390177375fa 100644 --- a/src/rcx/src/ext.i +++ b/src/rcx/src/ext.i @@ -51,6 +51,7 @@ using rcx::Ext; %} %include "../../Exception.i" +%include "../../Design.i" %inline %{ diff --git a/src/rcx/test/45_gcd.py b/src/rcx/test/45_gcd.py index 30f60c50932..81dfa55c95c 100644 --- a/src/rcx/test/45_gcd.py +++ b/src/rcx/test/45_gcd.py @@ -9,19 +9,19 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("45_gcd.def") # Load via resistance info via_45.set_resistance(tech) -rcx_aux.define_process_corner(ext_model_index=0, filename="X") +rcx_aux.define_process_corner(design, ext_model_index=0, filename="X") rcx_aux.extract_parasitics( - ext_model_file="45_patterns.rules", max_res=0, coupling_threshold=0.1 + design, ext_model_file="45_patterns.rules", max_res=0, coupling_threshold=0.1 ) spef_file = helpers.make_result_file("45_gcd.spef") -rcx_aux.write_spef(filename=spef_file, nets=test_nets) +rcx_aux.write_spef(design, filename=spef_file, nets=test_nets) helpers.diff_files("45_gcd.spefok", spef_file, "^\\*(DATE|VERSION)") diff --git a/src/rcx/test/ext_pattern.py b/src/rcx/test/ext_pattern.py index c99b7a657d4..9a44ee979be 100644 --- a/src/rcx/test/ext_pattern.py +++ b/src/rcx/test/ext_pattern.py @@ -6,12 +6,13 @@ tech = Tech() tech.readLef("sky130hs/sky130hs.tlef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("generate_pattern.defok") -rcx_aux.define_process_corner(ext_model_index=0, filename="X") +rcx_aux.define_process_corner(design, ext_model_index=0, filename="X") rcx_aux.extract_parasitics( + design, ext_model_file="ext_pattern.rules", cc_model=12, max_res=0, @@ -20,5 +21,5 @@ ) spef_file = helpers.make_result_file("ext_pattern.spef") -rcx_aux.write_spef(filename=spef_file, nets=test_nets) +rcx_aux.write_spef(design, filename=spef_file, nets=test_nets) helpers.diff_files("ext_pattern.spefok", spef_file, "^\\*(DATE|VERSION)") diff --git a/src/rcx/test/gcd.py b/src/rcx/test/gcd.py index 613a42ee28b..971644f1a07 100644 --- a/src/rcx/test/gcd.py +++ b/src/rcx/test/gcd.py @@ -9,19 +9,19 @@ test_nets = "" -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd.def") # This uses 'set_layer_rc' which is in rsz which has not yet been # Python wrapped. Remove when rsz has been wrapped design.evalTclString("source sky130hs/sky130hs.rc") -rcx_aux.define_process_corner(ext_model_index=0, filename="X") +rcx_aux.define_process_corner(design, ext_model_index=0, filename="X") rcx_aux.extract_parasitics( - ext_model_file="ext_pattern.rules", max_res=0, coupling_threshold=0.1 + design, ext_model_file="ext_pattern.rules", max_res=0, coupling_threshold=0.1 ) spef_file = helpers.make_result_file("gcd.spef") -rcx_aux.write_spef(filename=spef_file, nets=test_nets) +rcx_aux.write_spef(design, filename=spef_file, nets=test_nets) helpers.diff_files("gcd.spefok", spef_file, "^\\*(DATE|VERSION)") diff --git a/src/rcx/test/generate_pattern.py b/src/rcx/test/generate_pattern.py index c545e104a01..243481be2e4 100644 --- a/src/rcx/test/generate_pattern.py +++ b/src/rcx/test/generate_pattern.py @@ -4,15 +4,15 @@ tech = Tech() tech.readLef("sky130hs/sky130hs.tlef") -design = Design(tech) +design = helpers.make_design(tech) -rcx_aux.bench_wires(len=100, all=True) +rcx_aux.bench_wires(design, len=100, all=True) def_file = helpers.make_result_file("generate_pattern.def") verilog_file = helpers.make_result_file("generate_pattern.v") -rcx_aux.bench_verilog(filename=verilog_file) +rcx_aux.bench_verilog(design, filename=verilog_file) design.writeDef(def_file) diff --git a/src/rcx/test/rcx_aux.py b/src/rcx/test/rcx_aux.py index e80ec49a828..444171842dd 100644 --- a/src/rcx/test/rcx_aux.py +++ b/src/rcx/test/rcx_aux.py @@ -5,11 +5,12 @@ # Ensure keywords only and provide defaults when appropriate -def define_process_corner(*, ext_model_index=0, filename=""): - rcx.define_process_corner(ext_model_index, filename) +def define_process_corner(design, *, ext_model_index=0, filename=""): + design.getOpenRCX().define_process_corner(ext_model_index, filename) def extract_parasitics( + design, *, ext_model_file=None, corner_cnt=1, @@ -21,29 +22,39 @@ def extract_parasitics( context_depth=5, no_merge_via_res=False ): - # NOTE: This is position dependent - rcx.extract( - ext_model_file, - corner_cnt, - max_res, - coupling_threshold, - cc_model, - context_depth, - debug_net_id, - lef_res, - no_merge_via_res, - ) + opts = rcx.ExtractOptions() -def write_spef(*, filename="", nets="", net_id=0, coordinates=False): - rcx.write_spef(filename, nets, net_id, coordinates) + opts.ext_model_file = ext_model_file + opts.corner_cnt = corner_cnt + opts.max_res = max_res + opts.coupling_threshold = coupling_threshold + opts.cc_model = cc_model + opts.context_depth = context_depth + opts.lef_res = lef_res + opts.debug_net = debug_net_id + opts.no_merge_via_res = no_merge_via_res + design.getOpenRCX().extract(opts) -def bench_verilog(*, filename=""): - rcx.bench_verilog(filename) + +def write_spef(design, *, filename="", nets="", net_id=0, coordinates=False): + opts = rcx.SpefOptions() + opts.file = filename + opts.nets = nets + opts.net_id = net_id + if coordinates: + opts.N = "Y" + + design.getOpenRCX().write_spef(opts) + + +def bench_verilog(design, *, filename=""): + design.getOpenRCX().bench_verilog(filename) def bench_wires( + design, *, met_cnt=1000, cnt=5, @@ -58,33 +69,43 @@ def bench_wires( over_dist=100, under_dist=100 ): - rcx.bench_wires( - db_only, - over, - diag, - all, - met_cnt, - cnt, - len, - under_met, - w_list, - s_list, - over_dist, - under_dist, - ) - - -def adjust_rc(*, res_factor=1.0, cc_factor=1.0, gndc_factor=1.0): - rcx.adjust_rc(res_factor, cc_factor, gndc_factor) - - -def diff_spef(*, filename="", r_conn=False, r_res=False, r_cap=False, r_cc_cap=False): - rcx.diff_spef(filename, r_conn, r_res, r_cap, r_cc_cap) + opts = rcx.BenchWiresOptions() + opts.w_list = w_list + opts.s_list = s_list + opts.Over = over + opts.diag = diag + opts.gen_def_patterns = all + opts.cnt = cnt + opts.len = len + opts.under_met = under_met + opts.met_cnt = met_cnt + opts.db_only = db_only + opts.over_dist = over_dist + opts.under_dist = under_dist + design.getOpenRCX().bench_wires(opts) + + +def adjust_rc(design, *, res_factor=1.0, cc_factor=1.0, gndc_factor=1.0): + design.getOpenRCX().adjust_rc(res_factor, cc_factor, gndc_factor) + + +def diff_spef( + design, *, filename="", r_conn=False, r_res=False, r_cap=False, r_cc_cap=False +): + opts = rcx.DiffOptions() + opts.file = file + opts.r_res = r_res + opts.r_cap = r_cap + opts.r_cc_cap = r_cc_cap + opts.r_conn = r_conn + design.getOpenRCX().diff_spef(opts) -def write_rules(*, filename="extRules", dir="./", name="TYP", pattern=0): - rcx.write_rules(filename, dir, name, pattern) +def write_rules(design, *, filename="extRules", dir="./", name="TYP", pattern=0): + design.getOpenRCX().write_rules(filename, dir, name, pattern) -def read_spef(*, filename): - rcx.read_spef(filename) +def read_spef(design, *, filename): + opts = rcx.DiffOptions() + opts.file = filename + design.getOpenRCX().read_spef(opts) diff --git a/src/rmp/test/blif_reader.py b/src/rmp/test/blif_reader.py index 4195f76c25b..252af24375b 100644 --- a/src/rmp/test/blif_reader.py +++ b/src/rmp/test/blif_reader.py @@ -4,7 +4,7 @@ import rmp tech = Tech() -design = Design(tech) +design = helpers.make_design(tech) blif = rmp_aux.create_blif( design, hicell="LOGIC1_X1", hiport="Z", locell="LOGIC0_X1", loport="Z" diff --git a/src/rmp/test/blif_writer.py b/src/rmp/test/blif_writer.py index 0e56e911c55..45e460b2f1e 100644 --- a/src/rmp/test/blif_writer.py +++ b/src/rmp/test/blif_writer.py @@ -6,7 +6,7 @@ tech = Tech() tech.readLef("./Nangate45/Nangate45.lef") tech.readLiberty("./Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("./design.def") blif = rmp_aux.create_blif(design) diff --git a/src/rmp/test/const_cell_removal.py b/src/rmp/test/const_cell_removal.py index d9643ac2055..49184c2b638 100644 --- a/src/rmp/test/const_cell_removal.py +++ b/src/rmp/test/const_cell_removal.py @@ -6,7 +6,7 @@ tech.readLiberty("Nangate45/Nangate45_typ.lib") tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("rcon.def") design.evalTclString("read_sdc rcon.sdc") design.evalTclString("report_design_area") diff --git a/src/rmp/test/gcd_restructure.py b/src/rmp/test/gcd_restructure.py index 4262b17eece..aecdb3395a4 100644 --- a/src/rmp/test/gcd_restructure.py +++ b/src/rmp/test/gcd_restructure.py @@ -6,7 +6,7 @@ tech.readLiberty("Nangate45/Nangate45_typ.lib") tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd_placed.def") # read_sdc is defined in sta/tcl/Sdc.tcl (not yet wrapped) diff --git a/src/stt/src/flt/flute.cpp b/src/stt/src/flt/flute.cpp index 700dd7b7209..840897219c5 100644 --- a/src/stt/src/flt/flute.cpp +++ b/src/stt/src/flt/flute.cpp @@ -267,6 +267,7 @@ static void deleteLUT(LUT_TYPE& LUT, NUMSOLN_TYPE& numsoln) } delete[] numsoln; delete[] LUT; + LUT = nullptr; } } diff --git a/src/stt/test/flute1.py b/src/stt/test/flute1.py index 638cc6b47ef..57f529834fb 100644 --- a/src/stt/test/flute1.py +++ b/src/stt/test/flute1.py @@ -4,7 +4,7 @@ import stt_aux tech = Tech() -design = Design(tech) +design = helpers.make_design(tech) net = [ ["net250", 0], diff --git a/src/tap/src/tapcell.i b/src/tap/src/tapcell.i index eaa066a5545..f3bf55081be 100644 --- a/src/tap/src/tapcell.i +++ b/src/tap/src/tapcell.i @@ -40,15 +40,10 @@ #include "tap/tapcell.h" namespace ord { - tap::Tapcell* getTapcell(); - } using ord::getTapcell; - using std::set; - using std::string; - using std::vector; static odb::dbMaster* findMaster(const char* name) { diff --git a/src/tap/test/avoid_overlap.py b/src/tap/test/avoid_overlap.py index 5ade931362a..ff9c269e4bb 100644 --- a/src/tap/test/avoid_overlap.py +++ b/src/tap/test/avoid_overlap.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("sky130hs/sky130hs.tlef") tech.readLef("sky130hs/sky130hs_std_cell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd_sky130hs_floorplan.def") diff --git a/src/tap/test/boundary_macros.py b/src/tap/test/boundary_macros.py index 71d54d0e730..9f911017d09 100644 --- a/src/tap/test/boundary_macros.py +++ b/src/tap/test/boundary_macros.py @@ -7,7 +7,7 @@ tech.readLef("Nangate45/Nangate45_tech.lef") tech.readLef("Nangate45/Nangate45_stdcell.lef") tech.readLef("Nangate45/fakeram45_64x7.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("boundary_macros.def") options = tap.Options() diff --git a/src/tap/test/cut_rows.py b/src/tap/test/cut_rows.py index e9527bfb741..7a3f74aa9b3 100644 --- a/src/tap/test/cut_rows.py +++ b/src/tap/test/cut_rows.py @@ -6,7 +6,7 @@ tech.readLef("Nangate45/Nangate45_tech.lef") tech.readLef("Nangate45/Nangate45_stdcell.lef") tech.readLef("Nangate45/fakeram45_64x7.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("boundary_macros.def") options = tap.Options() diff --git a/src/tap/test/cut_rows_with_endcaps.py b/src/tap/test/cut_rows_with_endcaps.py index 38d59705169..513f4979ad5 100644 --- a/src/tap/test/cut_rows_with_endcaps.py +++ b/src/tap/test/cut_rows_with_endcaps.py @@ -6,7 +6,7 @@ tech.readLef("Nangate45/Nangate45_tech.lef") tech.readLef("Nangate45/Nangate45_stdcell.lef") tech.readLef("Nangate45/fakeram45_64x7.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("boundary_macros_tapsplaced.def") options = tap.Options() diff --git a/src/tap/test/gcd_fakeram.py b/src/tap/test/gcd_fakeram.py index b7c590e900b..66b75e4e88f 100644 --- a/src/tap/test/gcd_fakeram.py +++ b/src/tap/test/gcd_fakeram.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") tech.readLef("Nangate45/fakeram45_64x7.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd_fakeram.def") options = tap.Options() diff --git a/src/tap/test/gcd_nangate45.py b/src/tap/test/gcd_nangate45.py index c3ead5e6ddc..0f75aed0372 100644 --- a/src/tap/test/gcd_nangate45.py +++ b/src/tap/test/gcd_nangate45.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45_tech.lef") tech.readLef("Nangate45/Nangate45_stdcell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd_nangate45.def") options = tap.Options() diff --git a/src/tap/test/gcd_prefix.py b/src/tap/test/gcd_prefix.py index 357ff0e7674..f08c66620b0 100644 --- a/src/tap/test/gcd_prefix.py +++ b/src/tap/test/gcd_prefix.py @@ -6,7 +6,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45_tech.lef") tech.readLef("Nangate45/Nangate45_stdcell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd_prefix.def") options = tap.Options() diff --git a/src/tap/test/gcd_ripup.py b/src/tap/test/gcd_ripup.py index eb9469277d4..d9e4785628a 100644 --- a/src/tap/test/gcd_ripup.py +++ b/src/tap/test/gcd_ripup.py @@ -6,7 +6,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") tech.readLef("Nangate45/fakeram45_64x7.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd_ripup.def") options = tap.Options() diff --git a/src/tap/test/gcd_sky130.py b/src/tap/test/gcd_sky130.py index 4727c4dd1b4..c7dfe980f55 100644 --- a/src/tap/test/gcd_sky130.py +++ b/src/tap/test/gcd_sky130.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("sky130hs/sky130hs.tlef") tech.readLef("sky130hs/sky130hs_std_cell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd_sky130hs_floorplan.def") options = tap.Options() diff --git a/src/tap/test/multiple_calls.py b/src/tap/test/multiple_calls.py index f55a530ea67..92d5a2f91e2 100644 --- a/src/tap/test/multiple_calls.py +++ b/src/tap/test/multiple_calls.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") tech.readLef("Nangate45/fakeram45_64x7.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd_ripup.def") options = tap.Options() diff --git a/src/tap/test/no_endcap.py b/src/tap/test/no_endcap.py index e9f58996d67..672decd312c 100644 --- a/src/tap/test/no_endcap.py +++ b/src/tap/test/no_endcap.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("sky130hs/sky130hs.tlef") tech.readLef("sky130hs/sky130hs_std_cell.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("gcd_sky130hs_floorplan.def") options = tap.Options() diff --git a/src/tap/test/symmetry.py b/src/tap/test/symmetry.py index 7bea3012af6..427a74a83ea 100644 --- a/src/tap/test/symmetry.py +++ b/src/tap/test/symmetry.py @@ -5,7 +5,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45_tech.lef") tech.readLef("symmetry.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readDef("symmetry.def") options = tap.Options() diff --git a/test/helpers.py b/test/helpers.py index 8cf60a5f2f5..23063249e1f 100644 --- a/test/helpers.py +++ b/test/helpers.py @@ -2,6 +2,7 @@ import os import utl import re +from openroad import Design def make_rect(design, xl, yl, xh, yh): @@ -51,28 +52,24 @@ def diff_files(file1, file2, ignore=None): return 0 -# Output voltage file is specified as ... -utl.suppress_message(utl.PSM, 2) -# Output current file specified ... -utl.suppress_message(utl.PSM, 3) -# Error file is specified as ... -utl.suppress_message(utl.PSM, 83) -# Output spice file is specified as -utl.suppress_message(utl.PSM, 5) -# SPICE file is written at -utl.suppress_message(utl.PSM, 6) -# Reading DEF file -utl.suppress_message(utl.ODB, 127) -# Finished DEF file -utl.suppress_message(utl.ODB, 134) - -# suppress tap info messages -utl.suppress_message(utl.TAP, 100) -utl.suppress_message(utl.TAP, 101) - -# suppress par messages with filenames -utl.suppress_message(utl.PAR, 6) -utl.suppress_message(utl.PAR, 38) - -# suppress ord message with number of threads -utl.suppress_message(utl.ORD, 30) +def make_design(tech): + design = Design(tech) + logger = design.getLogger() + + # Reading DEF file + logger.suppressMessage(utl.ODB, 127) + # Finished DEF file + logger.suppressMessage(utl.ODB, 134) + + # suppress tap info messages + logger.suppressMessage(utl.TAP, 100) + logger.suppressMessage(utl.TAP, 101) + + # suppress par messages with files' names + logger.suppressMessage(utl.PAR, 6) + logger.suppressMessage(utl.PAR, 38) + + # suppress ord message with number of threads + logger.suppressMessage(utl.ORD, 30) + + return design diff --git a/test/helpers.tcl b/test/helpers.tcl index 9dca284176d..a0787225501 100644 --- a/test/helpers.tcl +++ b/test/helpers.tcl @@ -188,16 +188,6 @@ proc exit_summary {} { exit $::failing_checks } -# Output voltage file is specified as ... -suppress_message PSM 2 -# Output current file specified ... -suppress_message PSM 3 -# Error file is specified as ... -suppress_message PSM 83 -# Output spice file is specified as -suppress_message PSM 5 -# SPICE file is written at -suppress_message PSM 6 # Reading DEF file suppress_message ODB 127 # Finished DEF file