Can I see which nets in TritonRoute that are causing violations?

[oharboe]

When I have violations in TritonRoute that can't be resolved, it would be helpful to have some tricks on how to debug this and find the root cause in the RTL.

In my case, I eventually found a problem by wandering around in the OpenROAD GUI: I had to tweak my RTL to allow setting some pin constraints.

In FPGA tools, knowing the failing timing path start and end register can often, but not always be useful. Sometimes the problem is somewhere completely else in the design and the actual failing timing paths are just a symptom.

Even so, is there a similar list available somewhere for TritonRoute? A list of start/end registers for problematic routes?

[maliberty]

TR generates markers in "-output_drc $::env(REPORTS_DIR)/5_route_drc.rpt". They can be loaded in the GUI using the 'drc viewer'. There is also a timing path viewer in the GUI.

[oharboe]

Perfect!