Meandering wires in a void

[oharboe]

I'm doing some exploration of floorplanning, which means that I sometimes have a LOT of free space after detailed routing.

I saw this net, which I thought was curious: a meandering wire in the void...

Wouldn't a single vertical + horizontal wire be faster?

I'm curious as to why the detailed router meanders in this way.

[maliberty]

what does the route guide look like for this wire?

[oharboe]

I know what is going on. That wire has a lot of flip-flops on it.

This is a holdover from FPGA design. In the FPGA design, we used global synthesis and we had a synchronous reset with a LARGE fan-out. That large fan-out was handled by adding a number of flip-flops to it so that the tools would be able to create a synchronous reset tree to deal with the fanout and reset congestion. This is congruent with the recommendation in Quartus to use the HyperFlex architecture where there are bypassable registers in the routing. To use those, you basically add a bunch of pipeline stages to your synchronous reset. Basically the more modern Intel FPGAs now recommend synchronous reset over asynchronous reset for this reason.

https://www.intel.com/content/www/us/en/docs/programmable/683353/21-3/fpga-architecture-introduction.html

The above with the caveat that I'm not an FPGA expert when it comes to detail, I just write RTL, follow some high level guidelines, and the tools handle the rest...