Synthesis support

[Blebowski]

Hello, Is there any idea whether eventually OpenRoad would like to support also synthesis as part of the tool (instead of using Yosys externally) ?

[maliberty]

There is no plan for that. At most we would integrate yosys. What motivates your question?

[Blebowski]

Hi, @maliberty , several points:

• Yosys does not support full System Verilog (AFAIK, only with proprietary parser). Nor it supports VHDL (only via GHDL yosys plugin, and getting this to work is tricky)
• Synthesis is mentioned several times in: Meta: Top 3 Pain Points of the Toolchain #1759

1. Hard to get netlist that passes the timing
2. Possible QoR gains

• Generally, placement / routing aware synthesis reaches better results in lower geometries
• Industry high-end goes this direction
• Easier user interface (single database, simpler to pass information from synthesis to PnR)

[Blebowski]

However,
I need to note that I am not actively using nor developing OpenRoad. As for the usage, in company where I work, we use Synopsys for Synthesis and PnR tools due to stability, documentation, good performance and vast features available. We are looking forward for the day when we will be able to use open source.
As for the development, I would really like to join, but I already have little time for the open-source work due to my daily job.

[maliberty]

SV support is unrelated to OR and is being addressed in https://github.com/chipsalliance/Surelog. The pain is mostly related to missing ASIC oriented features in yosys/abc (eg operator mapping).

In general its a large effort and would need dedicated resources to work on it. There isn't enough bandwidth to make it a priority. If you want to start addressing some of these concerns I'd be happy to discuss further.

[Blebowski]

I would really like to, however I don't think I have capacity to do it in my free time, nor in my daily job. I think it will take me long time just to dive a little bit into the code-base of OR

[Iyury1]

I am planning to learn this code base and eventually contribute. This sounds like a really interesting idea for a long-term improvement. @Blebowski it seems you have a clear understanding of the functionality you want. If some actionable items came from this discussion I would love to help.

[QuantamHD]

@lyury1 Google is also interested in this functionality. I've Sketched basic solutions on integrating Yosys and OpenROAD.

[Iyury1]

@QuantamHD Sounds good. Feel free to contact me though the email listed on my github profile if you need any assistance.

[maliberty]

OR has already integrated abc which handles the technology dependent operations. Its less clear that there is a big advantage to the technology independent operations in yosys itself. There is some work slowly progressing on remapping in OR using abc.

[Iyury1]

In #1759 @antonblanchard mentioned "We don't pass FFs, manually instantiated standard cells or other black boxed things to ABC, so are missing a lot of optimizations including the ability to do register retiming. I've looked into this but tripped up on what looks like ABC issues."
Can you clarify is this the work that needs to be done on remapping in OR using ABC?

[maliberty]

Retiming is a separate idea that requires substantial verification and testing methodology to accompany it.

Remapping is more about improving the tech mapping when you have a better idea of the timing based on physical implementation.