How can I go from timing reports to Verilog?

[oharboe]

I have a timing path in the OpenROAD GUI that I want to understand.

How can I go from the timing report in the GUI to the Verilog?

[maliberty]

The-OpenROAD-Project/OpenROAD-flow-scripts#1129 should help with naming once merged.

There is no direct link today so you'll have to work back from the names. @QuantamHD has some work to store line numbers that is hopefully going to land but has been tied up in OSS licensing issues.

[oharboe]

I tried The-OpenROAD-Project/OpenROAD-flow-scripts#1129 and I was not able to find my way back to the Verilog code... I didnt see a change in the names in the timing path in my case.

[maliberty]

Does your path have any registers in it? How are they named?

[oharboe]

Does your path have any registers in it? How are they named?

No, this is for an unregistered signal going through a macro.

I will try to study this using mock-array-big so I can share details.

[oharboe]

I tried to reproduce this with mock-array-big, but got an example of how the timing report very clearly shows, with highlighting of macros, where the timing problem is and it's not hard at all to figure out what Verilog to look at:

[oharboe]

@maliberty Here is an example of how it is hard to get from the static timing report to the Verilog:

Build the design with make DESIGN_CONFIG=designs/asap7/mock-array-big/config.mk, then look at the Element make DESIGN_CONFIG=designs/asap7/mock-array-big/Element/config.mk gui_final.

How, in general, do I find my way to the Verilog code?

[vijayank88]

Just check this whether helps you to trace from timing report to verilog.

1. Open 6_final.v and Element.v in parallel
2. Check Start to End it is DFF to ouput port connection.
3. grep for _081_ instance D pin to find its source input
4. Trace DFF output Q to trace its end point as shown in the Data path details
   

[oharboe]

I can see how I can find my way in 6_final.v, but how do I go from 6_final.v to Element.v?

[maliberty]

If you use the rename PR I mentioned then the register should have a name matching the Element.v to some degree. Does that work here?

[oharboe]

It's significantly better, as, yes, there's a chance of finding the register now.

reg [7:0] REG; is a line in Element.v

[oharboe]

What I've heard is that tracking from timing reports back to RTL is an "unsolved problem in EDA tools", so The-OpenROAD-Project/OpenROAD-flow-scripts#1129 is probably as good as it gets for now.

To go beyond this, I suppose Yosys has to grow some sophistication w.r.t. tracking back to the original Verilog.

One of the goals of https://circt.llvm.org/ is to provide an improved infrastructure for RTL as it goes through a number of tools in a flow. Perhaps, one day, yosys will support https://circt.llvm.org/. Ideally this would give Yosys more input languages and better "debug information" through synthesis and technology mapping...