flipflop + inverter + rebuffer + output buffer

[oharboe]

Is the "rebuffer" buffer superfluous here?

The "rebuffer" buffer does not exist in placement, only after CTS.

make DESIGN_CONFIG=designs/asap7/mock-array/Element/config.mk gui_final:

make DESIGN_CONFIG=designs/asap7/mock-array/Element/config.mk gui_place:

[maliberty]

It is there for timing optimization as the path has negative slack which is addressed post-CTS. Is there a reason to think it superfluous?

[maliberty]

You could mark the net don't touch before CTS and compare

[oharboe]

How do I stop "don't touch" from removing the output buffer so I get the comparison I'm after?

$ git diff
diff --git a/flow/designs/asap7/mock-array/Element/constraints.sdc b/flow/designs/asap7/mock-array/Element/constraints.sdc
index f103fd3ae..62af2c3f4 100644
--- a/flow/designs/asap7/mock-array/Element/constraints.sdc
+++ b/flow/designs/asap7/mock-array/Element/constraints.sdc
@@ -67,3 +67,5 @@ set_driving_cell [all_inputs] -lib_cell BUFx4_ASAP7_75t_R
 #  See platforms/asap7/lib/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz, line 1223.
 #set_load -pin_load 2.731126 [all_outputs]
 set_load -pin_load 10 [all_outputs]
+
+set_dont_touch io_lsbOuts_7

[oharboe]

If I disable repair timing, I get slightly better (10ps) timing and the extra buffer is gone:

$ git diff
diff --git a/flow/scripts/cts.tcl b/flow/scripts/cts.tcl
index e75daa577..b1c23caa1 100644
--- a/flow/scripts/cts.tcl
+++ b/flow/scripts/cts.tcl
@@ -104,7 +104,7 @@ if { [info exists ::env(EQUIVALENCE_CHECK)] } {
     write_eqy_verilog 4_before_rsz.v
 }
 
-repair_timing {*}$additional_args
+#repair_timing {*}$additional_args

[oharboe]

If I delete set_load -pin_load 10 [all_outputs], the extra buffer goes away.

I'm wondering if the constraints.sdc for the Element is too clever. Isn't the timing checked at the mock-array level? The constraints.sdc file for the Element is only there to drive optimizations, as I understand it.

diff --git a/flow/designs/asap7/mock-array/Element/constraints.sdc b/flow/designs/asap7/mock-array/Element/constraints.sdc
index f103fd3ae..f8ea05f72 100644
--- a/flow/designs/asap7/mock-array/Element/constraints.sdc
+++ b/flow/designs/asap7/mock-array/Element/constraints.sdc
@@ -62,8 +62,3 @@ set_max_delay $max_delay -from [get_ports {io_lsbIns_*}] -to [get_ports {io_lsbO
 # Set driving cell and load capacitance explicitly to ensure timing results are sufficiently pessimistic
 #set_driving_cell [all_inputs] -lib_cell BUFx2_ASAP7_75t_R
 set_driving_cell [all_inputs] -lib_cell BUFx4_ASAP7_75t_R
-# Assuming the load on each output is a BUFx2_ASAP7_75t_R, we pessimistically use 3 times the highest input
-#  pin capacitance for this cell, which is 0.577042.
-#  See platforms/asap7/lib/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz, line 1223.
-#set_load -pin_load 2.731126 [all_outputs]
-set_load -pin_load 10 [all_outputs]

[oharboe]

Strange... If I delete set_driving_cell [all_inputs] -lib_cell BUFx4_ASAP7_75t_R, then the buffer on the output comes back. Why does a constraint on inputs cause buffers to be added to the output?

[oharboe]

No extra buffers after removing set_load -pin_load 10 [all_outputs]:

Untar cts-nobuffer.tar.gz

$ ./run-me-mock-array_Element-asap7-base.sh
OpenROAD v2.0-12488-g85f541bb6
openroad> report_checks -to io_lsbOuts_7
Startpoint: _755_ (rising edge-triggered flip-flop clocked by clock)
Endpoint: io_lsbOuts_7 (output port clocked by clock_vir)
Path Group: clock_vir
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
  74.98   74.98   clock network delay (propagated)
   0.00   74.98 ^ _755_/CLK (DFFHQNx2_ASAP7_75t_R)
  45.97  120.95 v _755_/QN (DFFHQNx2_ASAP7_75t_R)
  13.06  134.01 ^ _435_/Y (INVx4_ASAP7_75t_R)
  18.04  152.05 ^ output265/Y (BUFx2_ASAP7_75t_R)
   0.01  152.06 ^ io_lsbOuts_7 (out)
         152.06   data arrival time

 300.00  300.00   clock clock_vir (rise edge)
  70.00  370.00   clock network delay (ideal)
 -20.00  350.00   clock uncertainty
   0.00  350.00   clock reconvergence pessimism
-240.00  110.00   output external delay
         110.00   data required time
---------------------------------------------------------
         110.00   data required time
        -152.06   data arrival time
---------------------------------------------------------
         -42.06   slack (VIOLATED)

[oharboe]

If I remove set_driving_cell [all_inputs] -lib_cell BUFx4_ASAP7_75t_R, then the buffer is back.

Untar cts-buffer.tar.gz

./run-me-mock-array_Element-asap7-base.sh
OpenROAD v2.0-12488-g85f541bb6
[deleted]
openroad> report_checks -to io_lsbOuts_7
Startpoint: _755_ (rising edge-triggered flip-flop clocked by clock)
Endpoint: io_lsbOuts_7 (output port clocked by clock_vir)
Path Group: clock_vir
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
  66.89   66.89   clock network delay (propagated)
   0.00   66.89 ^ _755_/CLK (DFFHQNx2_ASAP7_75t_R)
  43.95  110.84 v _755_/QN (DFFHQNx2_ASAP7_75t_R)
  11.41  122.24 ^ _435_/Y (INVx3_ASAP7_75t_R)
  15.29  137.53 ^ rebuffer1/Y (BUFx6f_ASAP7_75t_R)
  12.78  150.31 ^ output265/Y (BUFx3_ASAP7_75t_R)
   0.01  150.32 ^ io_lsbOuts_7 (out)
         150.32   data arrival time

 300.00  300.00   clock clock_vir (rise edge)
  70.00  370.00   clock network delay (ideal)
 -20.00  350.00   clock uncertainty
   0.00  350.00   clock reconvergence pessimism
-240.00  110.00   output external delay
         110.00   data required time
---------------------------------------------------------
         110.00   data required time
        -150.32   data arrival time
---------------------------------------------------------
         -40.32   slack (VIOLATED)


openroad> 

[maliberty]

How do I stop "don't touch" from removing the output buffer so I get the comparison I'm after?

Set don't touch after the output buffer is created.

If I delete set_load -pin_load 10 [all_outputs], the extra buffer goes away.

Probably the timing improves and the net no longer needs repair. Similarly with the set_driving_cell changing the timing.