.gitignore

/compile
/qucs-core/build-aux/ar-lib
/qucs-core/build-aux/compile
/qucs-core/build-aux/test-driver
/qucs-core/build-aux/ylwrap
/qucs-core/src/components/verilog/DLS_1ton.cpp
/qucs-core/src/components/verilog/DLS_nto1.cpp
/qucs-core/src/components/verilog/EKV26MOS.cpp
/qucs-core/src/components/verilog/MESFET.cpp
/qucs-core/src/components/verilog/andor4x2.cpp
/qucs-core/src/components/verilog/andor4x3.cpp
/qucs-core/src/components/verilog/andor4x4.cpp
/qucs-core/src/components/verilog/binarytogrey4bit.cpp
/qucs-core/src/components/verilog/comp_1bit.cpp
/qucs-core/src/components/verilog/comp_2bit.cpp
/qucs-core/src/components/verilog/comp_4bit.cpp
/qucs-core/src/components/verilog/dff_SR.cpp
/qucs-core/src/components/verilog/dmux2to4.cpp
/qucs-core/src/components/verilog/dmux3to8.cpp
/qucs-core/src/components/verilog/dmux4to16.cpp
/qucs-core/src/components/verilog/fa1b.cpp
/qucs-core/src/components/verilog/fa2b.cpp
/qucs-core/src/components/verilog/gatedDlatch.cpp
/qucs-core/src/components/verilog/greytobinary4bit.cpp
/qucs-core/src/components/verilog/ha1b.cpp
/qucs-core/src/components/verilog/hpribin4bit.cpp
/qucs-core/src/components/verilog/jkff_SR.cpp
/qucs-core/src/components/verilog/log_amp.cpp
/qucs-core/src/components/verilog/logic_0.cpp
/qucs-core/src/components/verilog/logic_1.cpp
/qucs-core/src/components/verilog/mod_amp.cpp
/qucs-core/src/components/verilog/mux2to1.cpp
/qucs-core/src/components/verilog/mux4to1.cpp
/qucs-core/src/components/verilog/mux8to1.cpp
/qucs-core/src/components/verilog/nigbt.cpp
/qucs-core/src/components/verilog/pad2bit.cpp
/qucs-core/src/components/verilog/pad3bit.cpp
/qucs-core/src/components/verilog/pad4bit.cpp
/qucs-core/src/components/verilog/photodiode.cpp
/qucs-core/src/components/verilog/phototransistor.cpp
/qucs-core/src/components/verilog/potentiometer.cpp
/qucs-core/src/components/verilog/tff_SR.cpp
/qucs-core/src/components/verilog/vcresistor.cpp
/qucs-core/src/converter/parse_spice.hpp
/qucs-core/src/converter/parse_vcd.hpp
/qucs-core/src/parse_citi.hpp
/qucs-core/src/parse_csv.hpp
/qucs-core/src/parse_dataset.hpp
/qucs-core/src/parse_mdl.hpp
/qucs-core/src/parse_netlist.hpp
/qucs-core/src/parse_touchstone.hpp
/qucs-core/src/parse_zvr.hpp
/qucs/ar-lib
# Qucs Specific #
#################
*/src/qucsator
*/src/converter/qucsconv
*/src/gperfappgen
qucs_typedefs.h
*/src/components/verilog/discipline.vams

# Verilog-A generated files
qucs-core/src/components/verilog/*.cpp

# Following files generated by lex and yacc

# qucsator generated files (in qucs-core/src)
scan_netlist.cpp
parse_netlist.cpp
scan_dataset.cpp
parse_dataset.cpp
tokens_dataset.h
tokens_netlist.h
parse_touchstone.cpp
tokens_touchstone.h
scan_touchstone.cpp
parse_citi.cpp
tokens_citi.h
scan_citi.cpp
parse_zvr.cpp
scan_zvr.cpp
tokens_zvr.h
parse_mdl.cpp
scan_mdl.cpp
tokens_mdl.h
parse_csv.cpp
tokens_csv.h
scan_csv.cpp
qucsdefs.h
gperfapphash.cpp
gperfapphash.gph
gperfappgen.h

# spice converter generated files (in qucs-core/src/converter)
parse_spice.cpp
scan_spice.cpp
tokens_spice.h
parse_vcd.cpp
scan_vcd.cpp
tokens_vcd.h

# ADMS Specific #
##################
*.adms
*.implicit.xml
*.interface.xml
*.vams.c
*.va.c
*.xml.c
*/adms/admsXml/preprocessorLex.c
*/adms/admsXml/preprocessorYacc.c
*/adms/admsXml/preprocessorYacc.h
*/adms/admsXml/verilogaLex.c
*/adms/admsXml/verilogaYacc.c
*/adms/admsXml/verilogaYacc.h
*/adms/admsXml/verilogaYacc.y
*/adms/admsXml/admstpathYacc.c
*/adms/admsXml/admstpathYacc.h
*/adms/admsXml/admstpathYacc.y
*/adms/admsXml/.libs/
*/adms/admsXml/adms.c
*/adms/admsXml/adms.h
*/adms/admsXml/adms.implicit.xml.c
*/adms/admsXml/admsCheck
*/adms/admsXml/admsXml
*.analogfunction.cpp
*.analogfunction.h
*.core.cpp
*.core.h
*.defs.h

# Temp Files #
##############
*~

# Autotools Generated #
#######################
*.la
*.lo
configure
Makefile.in
Makefile
stamp-h1
missing
config.guess
config.h
config.sub
config.h.in
config.log
config.status
build-stamp
aclocal.m4
INSTALL
depcomp
install-sh
libtool
autom4te.cache/
auxconf/
libltdl/
libtool.m4
ltoptions.m4
ltsugar.m4
ltversion.m4
lt~obsolete.m4
ltmain.sh

# Unknown #
###########
*.output

# Compiled source #
###################
*.com
*.class
*.dll
*.exe
*.o
*.so
*.mex*
*.pyc
moc_*.cpp
moc_*.cxx
qrc_*.cpp
qrc_*.cxx
.libs

# Packages #
############
# it's better to unpack these files and commit the raw source
# git has its own built in compression methods
*.7z
*.dmg
*.gz
*.iso
*.jar
*.rar
*.tar
*.zip

# Logs and databases #
######################
*.log
*.sql
*.sqlite

# OS generated files #
######################
.DS_Store
.DS_Store?
._*
.Spotlight-V100
.Trashes
Icon?
ehthumbs.db
Thumbs.db

# Code::Blocks generated files #
################################
*.layout
*.depend

# Doxygen html output #
#######################
qucs/contrib/doxygen/html/

# CMake #
#########
# created by Qt Creator
CMakeLists.txt.user

# emacs #
#########
# dot hash files (write locks)
.\#*

# Qucs user files #
###################
# ignore schematics, data display and data
*.sch
*.dpl
*.dat
# except in the examples/ directory
!examples/*.sch
!examples/*.dpl
!qucs-doc/tutorial/sparameteramp/*/*.sch
!qucs-doc/tutorial/sparameteramp/*/*.dpl

# Xcode #
#########
DerivedData
*.build
Debug
*.xcodeproj

# Others #
##########
CMakeScripts
*.cxx_parameters
shadow

########
qucsactivefilter
*.pro.user

CMakeFiles
CMakeCache.txt
*.cmake
*.depends
/qucs-core/src/components/verilog/constants.vams
/qucs-core/src/components/verilog/disciplines.vams
/qucs-doc/technical/octave-workspace