diff --git a/configs/a64fx_SME.yaml b/configs/a64fx_SME.yaml index 859fe2283a..0fef3e053e 100644 --- a/configs/a64fx_SME.yaml +++ b/configs/a64fx_SME.yaml @@ -95,24 +95,11 @@ Ports: Portname: BR Instruction-Group-Support: - BRANCH -# Define example SME / SVE Streaming Mode units +# Define example SME unit 8: Portname: SME Instruction-Group-Support: - SME - 9: - Portname: PR_S - Instruction-Group-Support: - - STREAMING_PREDICATE - 10: - Portname: FLA_S - Instruction-Group-Support: - - STREAMING_SVE - 11: - Portname: FLB_S - Instruction-Group-Support: - - STREAMING_SVE_SIMPLE - - STREAMING_SVE_MUL Reservation-Stations: 0: Size: 20 @@ -147,13 +134,6 @@ Reservation-Stations: Dispatch-Rate: 1 Ports: - SME - 6: - Size: 40 - Dispatch-Rate: 3 - Ports: - - FLA_S - - FLB_S - - PR_S Execution-Units: 0: Pipelined: True @@ -209,24 +189,6 @@ Execution-Units: - INT_DIV_OR_SQRT - FP_DIV_OR_SQRT - SVE_DIV_OR_SQRT - 9: - Pipelined: True - Blocking-Groups: - - INT_DIV_OR_SQRT - - FP_DIV_OR_SQRT - - SVE_DIV_OR_SQRT - 10: - Pipelined: True - Blocking-Groups: - - INT_DIV_OR_SQRT - - FP_DIV_OR_SQRT - - SVE_DIV_OR_SQRT - 11: - Pipelined: True - Blocking-Groups: - - INT_DIV_OR_SQRT - - FP_DIV_OR_SQRT - - SVE_DIV_OR_SQRT Latencies: 0: Instruction-Groups: @@ -255,11 +217,9 @@ Latencies: - SCALAR_SIMPLE - VECTOR_SIMPLE_LOGICAL - SVE_SIMPLE_LOGICAL - - STREAMING_SVE_SIMPLE_LOGICAL - SME_SIMPLE_LOGICAL - VECTOR_SIMPLE_CMP - SVE_SIMPLE_CMP - - STREAMING_SVE_SIMPLE_CMP - SME_SIMPLE_CMP Execution-Latency: 4 Execution-Throughput: 1 @@ -273,25 +233,21 @@ Latencies: - SCALAR_SIMPLE_CVT - VECTOR_SIMPLE - SVE_SIMPLE - - STREAMING_SVE_SIMPLE - SME_SIMPLE - FP_MUL - SVE_MUL - - STREAMING_SVE_MUL - SME_MUL Execution-Latency: 9 Execution-Throughput: 1 7: Instruction-Groups: - SVE_DIV_OR_SQRT - - STREAMING_SVE_DIV_OR_SQRT - SME_DIV_OR_SQRT Execution-Latency: 98 Execution-Throughput: 98 8: Instruction-Groups: - PREDICATE - - STREAMING_PREDICATE Execution-Latency: 3 Execution-Throughput: 1 9: @@ -305,10 +261,8 @@ Latencies: 10: Instruction-Groups: - LOAD_SVE - - LOAD_STREAMING_SVE - LOAD_SME - STORE_ADDRESS_SVE - - STORE_ADDRESS_STREAMING_SVE - STORE_ADDRESS_SME Execution-Latency: 6 Execution-Throughput: 1 diff --git a/src/include/simeng/arch/aarch64/Instruction.hh b/src/include/simeng/arch/aarch64/Instruction.hh index 44263432a1..76e74d7eb7 100644 --- a/src/include/simeng/arch/aarch64/Instruction.hh +++ b/src/include/simeng/arch/aarch64/Instruction.hh @@ -370,12 +370,6 @@ class Instruction : public simeng::Instruction { * processing this instruction. */ InstructionException getException() const; - /** Checks whether the current SVE Streaming Mode status is different to when - * this instruction was first decoded, and updates the instruction group - * accordingly if required. - * Returns TRUE if the group was updated, FALSE otherwise. */ - bool checkStreamingGroupAndUpdate(); - private: /** Process the instruction's metadata to determine source/destination * registers. */ @@ -457,9 +451,6 @@ class Instruction : public simeng::Instruction { * the `InsnType` namespace allowing each bit to represent a unique * identifier such as `isLoad` or `isMultiply` etc. */ uint32_t instructionIdentifier_ = 0; - - /** The instruction group this instruction belongs to. */ - uint16_t instructionGroup_ = InstructionGroups::NONE; }; } // namespace aarch64 diff --git a/src/include/simeng/arch/aarch64/InstructionGroups.hh b/src/include/simeng/arch/aarch64/InstructionGroups.hh index 6c58ff4976..fc15e95230 100644 --- a/src/include/simeng/arch/aarch64/InstructionGroups.hh +++ b/src/include/simeng/arch/aarch64/InstructionGroups.hh @@ -98,53 +98,37 @@ const uint16_t LOAD_SVE = 62; const uint16_t STORE_ADDRESS_SVE = 63; const uint16_t STORE_DATA_SVE = 64; const uint16_t STORE_SVE = 65; -const uint16_t STREAMING_SVE = 66; -const uint16_t STREAMING_SVE_SIMPLE = 67; -const uint16_t STREAMING_SVE_SIMPLE_ARTH = 68; -const uint16_t STREAMING_SVE_SIMPLE_ARTH_NOSHIFT = 69; -const uint16_t STREAMING_SVE_SIMPLE_LOGICAL = 70; -const uint16_t STREAMING_SVE_SIMPLE_LOGICAL_NOSHIFT = 71; -const uint16_t STREAMING_SVE_SIMPLE_CMP = 72; -const uint16_t STREAMING_SVE_SIMPLE_CVT = 73; -const uint16_t STREAMING_SVE_MUL = 74; -const uint16_t STREAMING_SVE_DIV_OR_SQRT = 75; -const uint16_t LOAD_STREAMING_SVE = 76; -const uint16_t STORE_ADDRESS_STREAMING_SVE = 77; -const uint16_t STORE_DATA_STREAMING_SVE = 78; -const uint16_t STORE_STREAMING_SVE = 79; -const uint16_t SME = 80; -const uint16_t SME_SIMPLE = 81; -const uint16_t SME_SIMPLE_ARTH = 82; -const uint16_t SME_SIMPLE_ARTH_NOSHIFT = 83; -const uint16_t SME_SIMPLE_LOGICAL = 84; -const uint16_t SME_SIMPLE_LOGICAL_NOSHIFT = 85; -const uint16_t SME_SIMPLE_CMP = 86; -const uint16_t SME_SIMPLE_CVT = 87; -const uint16_t SME_MUL = 88; -const uint16_t SME_DIV_OR_SQRT = 89; -const uint16_t LOAD_SME = 90; -const uint16_t STORE_ADDRESS_SME = 91; -const uint16_t STORE_DATA_SME = 92; -const uint16_t STORE_SME = 93; -const uint16_t PREDICATE = 94; -const uint16_t STREAMING_PREDICATE = 95; -const uint16_t LOAD = 96; -const uint16_t STORE_ADDRESS = 97; -const uint16_t STORE_DATA = 98; -const uint16_t STORE = 99; -const uint16_t BRANCH = 100; -const uint16_t ALL = 101; -const uint16_t NONE = 102; +const uint16_t PREDICATE = 66; +const uint16_t LOAD = 67; +const uint16_t STORE_ADDRESS = 68; +const uint16_t STORE_DATA = 69; +const uint16_t STORE = 70; +const uint16_t BRANCH = 71; +const uint16_t SME = 72; +const uint16_t SME_SIMPLE = 73; +const uint16_t SME_SIMPLE_ARTH = 74; +const uint16_t SME_SIMPLE_ARTH_NOSHIFT = 75; +const uint16_t SME_SIMPLE_LOGICAL = 76; +const uint16_t SME_SIMPLE_LOGICAL_NOSHIFT = 77; +const uint16_t SME_SIMPLE_CMP = 78; +const uint16_t SME_SIMPLE_CVT = 79; +const uint16_t SME_MUL = 80; +const uint16_t SME_DIV_OR_SQRT = 81; +const uint16_t LOAD_SME = 82; +const uint16_t STORE_ADDRESS_SME = 83; +const uint16_t STORE_DATA_SME = 84; +const uint16_t STORE_SME = 85; +const uint16_t ALL = 86; +const uint16_t NONE = 87; } // namespace InstructionGroups /** The number of aarch64 instruction groups. */ -static constexpr uint8_t NUM_GROUPS = 103; +static constexpr uint8_t NUM_GROUPS = 88; const std::unordered_map> groupInheritance_ = { {InstructionGroups::ALL, {InstructionGroups::INT, InstructionGroups::FP, InstructionGroups::SVE, - InstructionGroups::STREAMING_SVE, InstructionGroups::SME, - InstructionGroups::PREDICATE, InstructionGroups::STREAMING_PREDICATE, + InstructionGroups::SME, InstructionGroups::PREDICATE, InstructionGroups::LOAD, InstructionGroups::STORE, InstructionGroups::BRANCH}}, {InstructionGroups::INT, @@ -218,19 +202,6 @@ const std::unordered_map> groupInheritance_ = { {InstructionGroups::SVE_SIMPLE_ARTH_NOSHIFT}}, {InstructionGroups::SVE_SIMPLE_LOGICAL, {InstructionGroups::SVE_SIMPLE_LOGICAL_NOSHIFT}}, - {InstructionGroups::STREAMING_SVE, - {InstructionGroups::STREAMING_SVE_SIMPLE, - InstructionGroups::STREAMING_SVE_DIV_OR_SQRT, - InstructionGroups::STREAMING_SVE_MUL}}, - {InstructionGroups::STREAMING_SVE_SIMPLE, - {InstructionGroups::STREAMING_SVE_SIMPLE_ARTH, - InstructionGroups::STREAMING_SVE_SIMPLE_LOGICAL, - InstructionGroups::STREAMING_SVE_SIMPLE_CMP, - InstructionGroups::STREAMING_SVE_SIMPLE_CVT}}, - {InstructionGroups::STREAMING_SVE_SIMPLE_ARTH, - {InstructionGroups::STREAMING_SVE_SIMPLE_ARTH_NOSHIFT}}, - {InstructionGroups::STREAMING_SVE_SIMPLE_LOGICAL, - {InstructionGroups::STREAMING_SVE_SIMPLE_LOGICAL_NOSHIFT}}, {InstructionGroups::SME, {InstructionGroups::SME_SIMPLE, InstructionGroups::SME_DIV_OR_SQRT, InstructionGroups::SME_MUL}}, @@ -244,11 +215,11 @@ const std::unordered_map> groupInheritance_ = { {InstructionGroups::LOAD, {InstructionGroups::LOAD_INT, InstructionGroups::LOAD_SCALAR, InstructionGroups::LOAD_VECTOR, InstructionGroups::LOAD_SVE, - InstructionGroups::LOAD_STREAMING_SVE, InstructionGroups::LOAD_SME}}, + InstructionGroups::LOAD_SME}}, {InstructionGroups::STORE, {InstructionGroups::STORE_INT, InstructionGroups::STORE_SCALAR, InstructionGroups::STORE_VECTOR, InstructionGroups::STORE_SVE, - InstructionGroups::STORE_STREAMING_SVE, InstructionGroups::STORE_SME}}, + InstructionGroups::STORE_SME}}, {InstructionGroups::STORE_INT, {InstructionGroups::STORE_ADDRESS_INT, InstructionGroups::STORE_DATA_INT}}, {InstructionGroups::STORE_SCALAR, @@ -259,9 +230,6 @@ const std::unordered_map> groupInheritance_ = { InstructionGroups::STORE_DATA_VECTOR}}, {InstructionGroups::STORE_SVE, {InstructionGroups::STORE_ADDRESS_SVE, InstructionGroups::STORE_DATA_SVE}}, - {InstructionGroups::STORE_STREAMING_SVE, - {InstructionGroups::STORE_ADDRESS_STREAMING_SVE, - InstructionGroups::STORE_DATA_STREAMING_SVE}}, {InstructionGroups::STORE_SME, {InstructionGroups::STORE_ADDRESS_SME, InstructionGroups::STORE_DATA_SME}}, {InstructionGroups::STORE_ADDRESS, @@ -269,12 +237,10 @@ const std::unordered_map> groupInheritance_ = { InstructionGroups::STORE_ADDRESS_SCALAR, InstructionGroups::STORE_ADDRESS_VECTOR, InstructionGroups::STORE_ADDRESS_SVE, - InstructionGroups::STORE_ADDRESS_STREAMING_SVE, InstructionGroups::STORE_ADDRESS_SME}}, {InstructionGroups::STORE_DATA, {InstructionGroups::STORE_DATA_INT, InstructionGroups::STORE_DATA_SCALAR, InstructionGroups::STORE_DATA_VECTOR, InstructionGroups::STORE_DATA_SVE, - InstructionGroups::STORE_DATA_STREAMING_SVE, InstructionGroups::STORE_DATA_SME}}}; } // namespace aarch64 diff --git a/src/include/simeng/arch/riscv/Instruction.hh b/src/include/simeng/arch/riscv/Instruction.hh index bff382df04..9e707449c6 100644 --- a/src/include/simeng/arch/riscv/Instruction.hh +++ b/src/include/simeng/arch/riscv/Instruction.hh @@ -252,9 +252,6 @@ class Instruction : public simeng::Instruction { * the `InsnType` namespace allowing each bit to represent a unique * identifier such as `isLoad` or `isMultiply` etc. */ uint16_t instructionIdentifier_ = 0; - - /** The instruction group this instruction belongs to. */ - uint16_t instructionGroup_ = InstructionGroups::NONE; }; } // namespace riscv diff --git a/src/lib/arch/aarch64/Architecture.cc b/src/lib/arch/aarch64/Architecture.cc index fea53d7767..9ee13de3b6 100644 --- a/src/lib/arch/aarch64/Architecture.cc +++ b/src/lib/arch/aarch64/Architecture.cc @@ -188,20 +188,6 @@ uint8_t Architecture::predecode(const uint8_t* ptr, uint16_t bytesAvailable, newInsn.setExecutionInfo(getExecutionInfo(newInsn)); // Cache the instruction iter = decodeCache_.insert({insn, newInsn}).first; - } else { - Instruction& cachedInsn = decodeCache_.at(insn); - // Check if SVE or Predicate instructions need their group updating due to - // SVE Streaming Mode activeness being different from when the instruction - // was first decoded. - if (cachedInsn.checkStreamingGroupAndUpdate()) { - // If the instruction's group has changed then update its execution info. - // The newly set group is most likely to be the most accurate, as an - // incorrect group allocation is only achieved when an exception/flush is - // triggered by changing the SVE Streaming Mode state. - cachedInsn.setExecutionInfo(getExecutionInfo(cachedInsn)); - } - // Need to re-set iterator after updating the decodeCache_ structure - iter = decodeCache_.find(insn); } // Split instruction into 1 or more defined micro-ops diff --git a/src/lib/arch/aarch64/Instruction.cc b/src/lib/arch/aarch64/Instruction.cc index 2811c72625..e3b697433e 100644 --- a/src/lib/arch/aarch64/Instruction.cc +++ b/src/lib/arch/aarch64/Instruction.cc @@ -131,7 +131,35 @@ bool Instruction::isLoad() const { return isInstruction(InsnType::isLoad); } bool Instruction::isBranch() const { return isInstruction(InsnType::isBranch); } -uint16_t Instruction::getGroup() const { return instructionGroup_; } +uint16_t Instruction::getGroup() const { + // Use identifiers to decide instruction group + // Set base + uint16_t base = InstructionGroups::INT; + if (isInstruction(InsnType::isScalarData)) + base = InstructionGroups::SCALAR; + else if (isInstruction(InsnType::isVectorData)) + base = InstructionGroups::VECTOR; + else if (isInstruction(InsnType::isSVEData)) + base = InstructionGroups::SVE; + else if (isInstruction(InsnType::isSMEData)) + base = InstructionGroups::SME; + + if (isInstruction(InsnType::isLoad)) return base + 10; + if (isInstruction(InsnType::isStoreAddress)) return base + 11; + if (isInstruction(InsnType::isStoreData)) return base + 12; + if (isInstruction(InsnType::isBranch)) return InstructionGroups::BRANCH; + if (isInstruction(InsnType::isPredicate)) return InstructionGroups::PREDICATE; + if (isInstruction(InsnType::isDivideOrSqrt)) return base + 9; + if (isInstruction(InsnType::isMultiply)) return base + 8; + if (isInstruction(InsnType::isConvert)) return base + 7; + if (isInstruction(InsnType::isCompare)) return base + 6; + if (isInstruction(InsnType::isLogical)) { + if (isInstruction(InsnType::isShift)) return base + 4; + return base + 5; + } + if (isInstruction(InsnType::isShift)) return base + 2; + return base + 3; // Default return is {Data type}_SIMPLE_ARTH +} bool Instruction::canExecute() const { return (sourceOperandsPending_ == 0); } @@ -164,33 +192,6 @@ const Architecture& Instruction::getArchitecture() const { InstructionException Instruction::getException() const { return exception_; } -bool Instruction::checkStreamingGroupAndUpdate() { - // Only instruction groups that depend on SVE Streaming Mode are SVE and - // PREDICATE - const uint16_t currentGroup = instructionGroup_; - const bool smEnabled = architecture_.isStreamingModeEnabled(); - if (isInstruction(InsnType::isPredicate)) { - // Decide on predicate group based on whether SVE Streaming Mode is enabled. - instructionGroup_ = smEnabled ? InstructionGroups::STREAMING_PREDICATE - : InstructionGroups::PREDICATE; - } else if (isInstruction(InsnType::isSVEData)) { - assert(((instructionGroup_ >= InstructionGroups::SVE && - instructionGroup_ <= InstructionGroups::STORE_SVE) || - (instructionGroup_ >= InstructionGroups::STREAMING_SVE && - instructionGroup_ <= InstructionGroups::STORE_STREAMING_SVE)) && - "Invalid instruction group for SVE instruction."); - // Get instruction group offset. - instructionGroup_ -= (instructionGroup_ >= InstructionGroups::STREAMING_SVE) - ? InstructionGroups::STREAMING_SVE - : InstructionGroups::SVE; - // Add instruction group base depending on whether SVE Streaming Mode is - // enabled. - instructionGroup_ += - smEnabled ? InstructionGroups::STREAMING_SVE : InstructionGroups::SVE; - } - return (currentGroup != instructionGroup_); -} - } // namespace aarch64 } // namespace arch } // namespace simeng diff --git a/src/lib/arch/aarch64/Instruction_decode.cc b/src/lib/arch/aarch64/Instruction_decode.cc index 38915d3186..3b884e73ab 100644 --- a/src/lib/arch/aarch64/Instruction_decode.cc +++ b/src/lib/arch/aarch64/Instruction_decode.cc @@ -691,50 +691,6 @@ void Instruction::decode() { sourceValues_.resize(sourceRegisterCount_); results_.resize(destinationRegisterCount_); } - - // Calculate the instruction's group based on identifiers - bool smEnabled = architecture_.isStreamingModeEnabled(); - // Set base group - uint16_t group = InstructionGroups::INT; - if (isInstruction(InsnType::isScalarData)) - group = InstructionGroups::SCALAR; - else if (isInstruction(InsnType::isVectorData)) - group = InstructionGroups::VECTOR; - else if (isInstruction(InsnType::isSVEData)) - group = - smEnabled ? InstructionGroups::STREAMING_SVE : InstructionGroups::SVE; - else if (isInstruction(InsnType::isSMEData)) - group = InstructionGroups::SME; - // Identify subgroup type - if (isInstruction(InsnType::isLoad)) - group += 10; - else if (isInstruction(InsnType::isStoreAddress)) - group += 11; - else if (isInstruction(InsnType::isStoreData)) - group += 12; - else if (isInstruction(InsnType::isBranch)) - group = InstructionGroups::BRANCH; - else if (isInstruction(InsnType::isPredicate)) - group = smEnabled ? InstructionGroups::STREAMING_PREDICATE - : InstructionGroups::PREDICATE; - else if (isInstruction(InsnType::isDivideOrSqrt)) - group += 9; - else if (isInstruction(InsnType::isMultiply)) - group += 8; - else if (isInstruction(InsnType::isConvert)) - group += 7; - else if (isInstruction(InsnType::isCompare)) - group += 6; - else if (isInstruction(InsnType::isLogical)) { - if (isInstruction(InsnType::isShift)) - group += 4; - else - group += 5; - } else if (isInstruction(InsnType::isShift)) - group += 2; - else - group += 3; // Default is {Data type}_SIMPLE_ARTH_NOSHIFT - instructionGroup_ = group; } } // namespace aarch64 diff --git a/src/lib/arch/aarch64/MicroDecoder.cc b/src/lib/arch/aarch64/MicroDecoder.cc index 3376f34d61..edb4a9a1c2 100644 --- a/src/lib/arch/aarch64/MicroDecoder.cc +++ b/src/lib/arch/aarch64/MicroDecoder.cc @@ -610,29 +610,6 @@ uint8_t MicroDecoder::decode(const Architecture& architecture, uint32_t word, } } } - // TODO: When SVE instructions have micro-op support, include the - // following code to ensure instruction groups are correct in SVE - // Streaming Mode - // - /* else { - std::vector& cachedUops = microDecodeCache_.at(word); - for (size_t uop = 0; uop < iter->second.size(); uop++) { - // Check if SVE or Predicate instructions need their group updating due - // to SVE Streaming Mode activeness being different from when the - // instruction was first decoded. - if (cachedUops[uop].checkStreamingGroupAndUpdate()) { - // If the instruction's group has changed then update its execution - // info. The newly set group is most likely to be the most accurate, - // as an incorrect group allocation is only achieved when an - // exception/flush is triggered by changing the SVE Streaming Mode - // state. - cachedUops[uop].setExecutionInfo( - architecture.getExecutionInfo(cachedUops[uop])); - } - } - // Need to re-set iterator after updating the microDecodeCache_ - structure iter = microDecodeCache_.find(word); - } */ // Get the number of micro-operations split into and transfer into passed // output vector num_ops = iter->second.size(); diff --git a/src/lib/arch/riscv/Instruction.cc b/src/lib/arch/riscv/Instruction.cc index 472e7f7ad7..c71b581a60 100644 --- a/src/lib/arch/riscv/Instruction.cc +++ b/src/lib/arch/riscv/Instruction.cc @@ -126,7 +126,24 @@ bool Instruction::isLoad() const { return isInstruction(InsnType::isLoad); } bool Instruction::isBranch() const { return isInstruction(InsnType::isBranch); } -uint16_t Instruction::getGroup() const { return instructionGroup_; } +uint16_t Instruction::getGroup() const { + uint16_t base = InstructionGroups::INT; + + if (isInstruction(InsnType::isFloat)) { + base = InstructionGroups::FLOAT; + } + + if (isInstruction(InsnType::isBranch)) return InstructionGroups::BRANCH; + if (isInstruction(InsnType::isLoad)) return base + 8; + if (isInstruction(InsnType::isStore)) return base + 9; + if (isInstruction(InsnType::isDivide)) return base + 7; + if (isInstruction(InsnType::isMultiply)) return base + 6; + if (isInstruction(InsnType::isShift) || isInstruction(InsnType::isConvert)) + return base + 5; + if (isInstruction(InsnType::isLogical)) return base + 4; + if (isInstruction(InsnType::isCompare)) return base + 3; + return base + 2; // Default return is {Data type}_SIMPLE_ARTH +} bool Instruction::canExecute() const { return (sourceOperandsPending_ == 0); } diff --git a/src/lib/arch/riscv/Instruction_decode.cc b/src/lib/arch/riscv/Instruction_decode.cc index 5337cc095e..e8145d4c11 100644 --- a/src/lib/arch/riscv/Instruction_decode.cc +++ b/src/lib/arch/riscv/Instruction_decode.cc @@ -310,33 +310,6 @@ void Instruction::decode() { knownOffset_ = sourceImm_; break; } - - // Calculate the instruction's group based on identifiers - // Set base group - uint16_t group = InstructionGroups::INT; - if (isInstruction(InsnType::isFloat)) group = InstructionGroups::FLOAT; - // Identify subgroup type - if (isInstruction(InsnType::isBranch)) - group = InstructionGroups::BRANCH; - else if (isInstruction(InsnType::isLoad)) - group += 8; - else if (isInstruction(InsnType::isStore)) - group += 9; - else if (isInstruction(InsnType::isDivide)) - group += 7; - else if (isInstruction(InsnType::isMultiply)) - group += 6; - else if (isInstruction(InsnType::isShift) || - isInstruction(InsnType::isConvert)) - group += 5; - else if (isInstruction(InsnType::isLogical)) - group += 4; - else if (isInstruction(InsnType::isCompare)) - group += 3; - else - group += 2; // Default return is {Data type}_SIMPLE_ARTH - - instructionGroup_ = group; } } // namespace riscv diff --git a/src/lib/config/ModelConfig.cc b/src/lib/config/ModelConfig.cc index 051865d9cd..6d6152ced4 100644 --- a/src/lib/config/ModelConfig.cc +++ b/src/lib/config/ModelConfig.cc @@ -1172,20 +1172,12 @@ void ModelConfig::createGroupMapping() { "STORE_ADDRESS_SVE", "STORE_DATA_SVE", "STORE_SVE", - "STREAMING_SVE", - "STREAMING_SVE_SIMPLE", - "STREAMING_SVE_SIMPLE_ARTH", - "STREAMING_SVE_SIMPLE_ARTH_NOSHIFT", - "STREAMING_SVE_SIMPLE_LOGICAL", - "STREAMING_SVE_SIMPLE_LOGICAL_NOSHIFT", - "STREAMING_SVE_SIMPLE_CMP", - "STREAMING_SVE_SIMPLE_CVT", - "STREAMING_SVE_MUL", - "STREAMING_SVE_DIV_OR_SQRT", - "LOAD_STREAMING_SVE", - "STORE_ADDRESS_STREAMING_SVE", - "STORE_DATA_STREAMING_SVE", - "STORE_STREAMING_SVE", + "PREDICATE", + "LOAD", + "STORE_ADDRESS", + "STORE_DATA", + "STORE", + "BRANCH", "SME", "SME_SIMPLE", "SME_SIMPLE_ARTH", @@ -1200,13 +1192,6 @@ void ModelConfig::createGroupMapping() { "STORE_ADDRESS_SME", "STORE_DATA_SME", "STORE_SME", - "PREDICATE", - "STREAMING_PREDICATE", - "LOAD", - "STORE_ADDRESS", - "STORE_DATA", - "STORE", - "BRANCH", "ALL", "NONE"}; } else if (isa_ == ISA::RV64) { diff --git a/test/integration/ConfigTest.cc b/test/integration/ConfigTest.cc index 41ac868fd5..12c295d2d4 100644 --- a/test/integration/ConfigTest.cc +++ b/test/integration/ConfigTest.cc @@ -59,16 +59,15 @@ TEST(ConfigTest, Default) { "'Permitted-Stores-Per-Cycle': 1\nPorts:\n 0:\n Portname: 0\n " "'Instruction-Group-Support':\n - ALL\n " "'Instruction-Opcode-Support':\n - 6343\n " - "'Instruction-Group-Support-Nums':\n - 101\n" - "'Reservation-Stations':\n 0:\n Size: 32\n 'Dispatch-Rate': " - "4\n Ports:\n - 0\n 'Port-Nums':\n - 0\n" - "'Execution-Units':\n 0:\n Pipelined: 1\n 'Blocking-Groups':\n " - " - NONE\n 'Blocking-Group-Nums':\n - 102\nLatencies:\n " - "0:\n 'Instruction-Groups':\n - NONE\n " - "'Instruction-Opcodes':\n - 6343\n 'Execution-Latency': 1\n " - "'Execution-Throughput': 1\n 'Instruction-Group-Nums':\n - 102\n" - "'CPU-Info':\n 'Generate-Special-Dir': 1\n " - "'Special-File-Dir-Path': " SIMENG_BUILD_DIR + "'Instruction-Group-Support-Nums':\n - " + "86\n'Reservation-Stations':\n 0:\n Size: 32\n 'Dispatch-Rate': " + "4\n Ports:\n - 0\n 'Port-Nums':\n - " + "0\n'Execution-Units':\n 0:\n Pipelined: 1\n 'Blocking-Groups':\n " + " - NONE\n 'Blocking-Group-Nums':\n - 87\nLatencies:\n 0:\n " + " 'Instruction-Groups':\n - NONE\n 'Instruction-Opcodes':\n " + " - 6343\n 'Execution-Latency': 1\n 'Execution-Throughput': 1\n " + " 'Instruction-Group-Nums':\n - 87\n'CPU-Info':\n " + "'Generate-Special-Dir': 1\n 'Special-File-Dir-Path': " SIMENG_BUILD_DIR "/specialFiles/\n 'Core-Count': 1\n 'Socket-Count': 1\n SMT: 1\n " "BogoMIPS: 0\n Features: ''\n 'CPU-Implementer': 0x0\n " "'CPU-Architecture': 0\n 'CPU-Variant': 0x0\n 'CPU-Part': 0x0\n " diff --git a/test/regression/aarch64/AArch64RegressionTest.hh b/test/regression/aarch64/AArch64RegressionTest.hh index 6f295f1d80..eebbd4f3d8 100644 --- a/test/regression/aarch64/AArch64RegressionTest.hh +++ b/test/regression/aarch64/AArch64RegressionTest.hh @@ -28,7 +28,7 @@ }, Ports: { - '0': { Portname: 0, Instruction-Group-Support: [INT, FP, SVE, PREDICATE, LOAD, STORE, BRANCH, SME, STREAMING_SVE, STREAMING_PREDICATE] }, + '0': { Portname: 0, Instruction-Group-Support: [INT, FP, SVE, PREDICATE, LOAD, STORE, BRANCH, SME] }, }, } )YAML"; diff --git a/test/regression/aarch64/Exception.cc b/test/regression/aarch64/Exception.cc index b8440742c6..1c90371ddc 100644 --- a/test/regression/aarch64/Exception.cc +++ b/test/regression/aarch64/Exception.cc @@ -387,8 +387,7 @@ INSTANTIATE_TEST_SUITE_P( "{Core: {Vector-Length: 512, Streaming-Vector-Length: 1024}, " "LSQ-L1-Interface: {Load-Bandwidth: 256, Store-Bandwidth: 256}, " "Ports: {'0': {Portname: 0, Instruction-Group-Support: [INT, SVE, " - "STREAMING_SVE, PREDICATE, STREAMING_PREDICATE, LOAD, STORE, " - "BRANCH, SME]}}}")), + "PREDICATE, LOAD, STORE, BRANCH, SME]}}}")), paramToString); } // namespace diff --git a/test/unit/aarch64/ArchitectureTest.cc b/test/unit/aarch64/ArchitectureTest.cc index 8c6d06f52c..8671d18707 100644 --- a/test/unit/aarch64/ArchitectureTest.cc +++ b/test/unit/aarch64/ArchitectureTest.cc @@ -118,50 +118,6 @@ TEST_F(AArch64ArchitectureTest, predecode) { EXPECT_EQ(output[0]->getInstructionAddress(), 0x4); EXPECT_EQ(output[0]->exceptionEncountered(), false); EXPECT_EQ(output[0]->getGroup(), InstructionGroups::SVE_DIV_OR_SQRT); - - // Test that a cached (when SVE Streaming Mode was disabled) SVE instruction - // has its group changed to a STREAMING group when SVE Streaming Mode is - // enabled - output = MacroOp(); - EXPECT_FALSE(arch->isStreamingModeEnabled()); - arch->setSVCRval(3); // SVCR.SMZA = 1 - EXPECT_TRUE(arch->isStreamingModeEnabled()); - result = arch->predecode(validInstrBytes.data(), validInstrBytes.size(), 0x4, - output); - EXPECT_EQ(result, 4); - EXPECT_EQ(output[0]->getInstructionAddress(), 0x4); - EXPECT_EQ(output[0]->exceptionEncountered(), false); - EXPECT_EQ(output[0]->getGroup(), - InstructionGroups::STREAMING_SVE_DIV_OR_SQRT); - - // Test that the same cached SVE instruction has its group reverted to - // non-STREAMING when SVE Streaming Mode is disabled again - output = MacroOp(); - EXPECT_TRUE(arch->isStreamingModeEnabled()); - arch->setSVCRval(2); // SVCR.ZA = 1, SVCR.SM = 0 - EXPECT_FALSE(arch->isStreamingModeEnabled()); - result = arch->predecode(validInstrBytes.data(), validInstrBytes.size(), 0x4, - output); - EXPECT_EQ(result, 4); - EXPECT_EQ(output[0]->getInstructionAddress(), 0x4); - EXPECT_EQ(output[0]->exceptionEncountered(), false); - EXPECT_EQ(output[0]->getGroup(), InstructionGroups::SVE_DIV_OR_SQRT); -} - -TEST_F(AArch64ArchitectureTest, predecode_streamingMode) { - // Test that an un-cached SVE instruction is put into a STREAMING group when - // SVE Streaming Mode is enabled - MacroOp output; - EXPECT_FALSE(arch->isStreamingModeEnabled()); - arch->setSVCRval(3); - EXPECT_TRUE(arch->isStreamingModeEnabled()); - uint8_t result = arch->predecode(validInstrBytes.data(), - validInstrBytes.size(), 0x4, output); - EXPECT_EQ(result, 4); - EXPECT_EQ(output[0]->getInstructionAddress(), 0x4); - EXPECT_EQ(output[0]->exceptionEncountered(), false); - EXPECT_EQ(output[0]->getGroup(), - InstructionGroups::STREAMING_SVE_DIV_OR_SQRT); } TEST_F(AArch64ArchitectureTest, getSystemRegisterTag) { diff --git a/test/unit/aarch64/InstructionTest.cc b/test/unit/aarch64/InstructionTest.cc index 95366d96e7..6143893f6b 100644 --- a/test/unit/aarch64/InstructionTest.cc +++ b/test/unit/aarch64/InstructionTest.cc @@ -198,7 +198,7 @@ TEST_F(AArch64InstructionTest, invalidInsn_1) { EXPECT_EQ(insn.getException(), InstructionException::EncodingUnallocated); EXPECT_EQ(insn.getGeneratedAddresses().size(), 0); // Default Group for instruction that is not decoded - EXPECT_EQ(insn.getGroup(), InstructionGroups::NONE); + EXPECT_EQ(insn.getGroup(), InstructionGroups::INT_SIMPLE_ARTH_NOSHIFT); EXPECT_EQ(insn.getInstructionAddress(), 0x44); EXPECT_EQ(insn.getInstructionId(), 13); EXPECT_EQ(insn.getKnownOffset(), 0); @@ -264,7 +264,7 @@ TEST_F(AArch64InstructionTest, invalidInsn_2) { EXPECT_EQ(insn.getException(), InstructionException::HypervisorCall); EXPECT_EQ(insn.getGeneratedAddresses().size(), 0); // Default Group for instruction that is not decoded - EXPECT_EQ(insn.getGroup(), InstructionGroups::NONE); + EXPECT_EQ(insn.getGroup(), InstructionGroups::INT_SIMPLE_ARTH_NOSHIFT); EXPECT_EQ(insn.getInstructionAddress(), 0x43); EXPECT_EQ(insn.getInstructionId(), 15); EXPECT_EQ(insn.getKnownOffset(), 0); @@ -642,74 +642,6 @@ TEST_F(AArch64InstructionTest, setters) { EXPECT_TRUE(insn.isWaitingCommit()); } -TEST_F(AArch64InstructionTest, checkStreamingGroupAndUpdate) { - EXPECT_FALSE(arch.isStreamingModeEnabled()); - // Insn is `fdivr z1.s, p0/m, z1.s, z0.s` - Instruction SVE_insn = Instruction(arch, *fdivMetadata.get(), MicroOpInfo()); - EXPECT_EQ(SVE_insn.getGroup(), InstructionGroups::SVE_DIV_OR_SQRT); - // insn is `cbz x2, #0x28` - Instruction nonSVE_insn = - Instruction(arch, *cbzMetadata.get(), MicroOpInfo()); - EXPECT_EQ(nonSVE_insn.getGroup(), InstructionGroups::BRANCH); - // insn is `psel p4, p0, p2.s[w13, 0]` - Instruction PRED_insn = Instruction(arch, *pselMetadata.get(), MicroOpInfo()); - EXPECT_EQ(PRED_insn.getGroup(), InstructionGroups::PREDICATE); - - // Without changing SVE Streaming Mode, calling checkStreamingGroupAndUpdate - // should have no effect - EXPECT_FALSE(arch.isStreamingModeEnabled()); - EXPECT_EQ(SVE_insn.getGroup(), InstructionGroups::SVE_DIV_OR_SQRT); - EXPECT_EQ(nonSVE_insn.getGroup(), InstructionGroups::BRANCH); - EXPECT_EQ(PRED_insn.getGroup(), InstructionGroups::PREDICATE); - EXPECT_FALSE(SVE_insn.checkStreamingGroupAndUpdate()); - EXPECT_FALSE(nonSVE_insn.checkStreamingGroupAndUpdate()); - EXPECT_FALSE(PRED_insn.checkStreamingGroupAndUpdate()); - EXPECT_EQ(SVE_insn.getGroup(), InstructionGroups::SVE_DIV_OR_SQRT); - EXPECT_EQ(nonSVE_insn.getGroup(), InstructionGroups::BRANCH); - EXPECT_EQ(PRED_insn.getGroup(), InstructionGroups::PREDICATE); - - // Updating SVE Streaming Mode should mean calling - // checkStreamingGroupAndUpdate changes SVE and PRED groups - arch.setSVCRval(3); - EXPECT_TRUE(arch.isStreamingModeEnabled()); - EXPECT_EQ(SVE_insn.getGroup(), InstructionGroups::SVE_DIV_OR_SQRT); - EXPECT_EQ(nonSVE_insn.getGroup(), InstructionGroups::BRANCH); - EXPECT_EQ(PRED_insn.getGroup(), InstructionGroups::PREDICATE); - EXPECT_TRUE(SVE_insn.checkStreamingGroupAndUpdate()); - EXPECT_FALSE(nonSVE_insn.checkStreamingGroupAndUpdate()); - EXPECT_TRUE(PRED_insn.checkStreamingGroupAndUpdate()); - EXPECT_EQ(SVE_insn.getGroup(), InstructionGroups::STREAMING_SVE_DIV_OR_SQRT); - EXPECT_EQ(nonSVE_insn.getGroup(), InstructionGroups::BRANCH); - EXPECT_EQ(PRED_insn.getGroup(), InstructionGroups::STREAMING_PREDICATE); - - // Calling checkStreamingGroupAndUpdate again should have no effect on SVE and - // PRED groups, and should return false as a result - EXPECT_TRUE(arch.isStreamingModeEnabled()); - EXPECT_EQ(SVE_insn.getGroup(), InstructionGroups::STREAMING_SVE_DIV_OR_SQRT); - EXPECT_EQ(nonSVE_insn.getGroup(), InstructionGroups::BRANCH); - EXPECT_EQ(PRED_insn.getGroup(), InstructionGroups::STREAMING_PREDICATE); - EXPECT_FALSE(SVE_insn.checkStreamingGroupAndUpdate()); - EXPECT_FALSE(nonSVE_insn.checkStreamingGroupAndUpdate()); - EXPECT_FALSE(PRED_insn.checkStreamingGroupAndUpdate()); - EXPECT_EQ(SVE_insn.getGroup(), InstructionGroups::STREAMING_SVE_DIV_OR_SQRT); - EXPECT_EQ(nonSVE_insn.getGroup(), InstructionGroups::BRANCH); - EXPECT_EQ(PRED_insn.getGroup(), InstructionGroups::STREAMING_PREDICATE); - - // Disabling SVE Streaming Mode should cause SVE and PRED groups to be updated - // again to non-STREAMING, and true returned as a result - arch.setSVCRval(0); - EXPECT_FALSE(arch.isStreamingModeEnabled()); - EXPECT_EQ(SVE_insn.getGroup(), InstructionGroups::STREAMING_SVE_DIV_OR_SQRT); - EXPECT_EQ(nonSVE_insn.getGroup(), InstructionGroups::BRANCH); - EXPECT_EQ(PRED_insn.getGroup(), InstructionGroups::STREAMING_PREDICATE); - EXPECT_TRUE(SVE_insn.checkStreamingGroupAndUpdate()); - EXPECT_FALSE(nonSVE_insn.checkStreamingGroupAndUpdate()); - EXPECT_TRUE(PRED_insn.checkStreamingGroupAndUpdate()); - EXPECT_EQ(SVE_insn.getGroup(), InstructionGroups::SVE_DIV_OR_SQRT); - EXPECT_EQ(nonSVE_insn.getGroup(), InstructionGroups::BRANCH); - EXPECT_EQ(PRED_insn.getGroup(), InstructionGroups::PREDICATE); -} - } // namespace aarch64 } // namespace arch } // namespace simeng \ No newline at end of file diff --git a/test/unit/riscv/InstructionTest.cc b/test/unit/riscv/InstructionTest.cc index 43e0daf745..64eff7071c 100644 --- a/test/unit/riscv/InstructionTest.cc +++ b/test/unit/riscv/InstructionTest.cc @@ -179,7 +179,7 @@ TEST_F(RiscVInstructionTest, invalidInsn_1) { EXPECT_EQ(insn.getException(), InstructionException::EncodingUnallocated); EXPECT_EQ(insn.getGeneratedAddresses().size(), 0); // Default Group for instruction that is not decoded - EXPECT_EQ(insn.getGroup(), InstructionGroups::NONE); + EXPECT_EQ(insn.getGroup(), InstructionGroups::INT_SIMPLE_ARTH); EXPECT_EQ(insn.getInstructionAddress(), 0x44); EXPECT_EQ(insn.getInstructionId(), 13); EXPECT_EQ(insn.getKnownOffset(), 0); @@ -243,7 +243,7 @@ TEST_F(RiscVInstructionTest, invalidInsn_2) { EXPECT_EQ(insn.getException(), InstructionException::HypervisorCall); EXPECT_EQ(insn.getGeneratedAddresses().size(), 0); // Default Group for instruction that is not decoded - EXPECT_EQ(insn.getGroup(), InstructionGroups::NONE); + EXPECT_EQ(insn.getGroup(), InstructionGroups::INT_SIMPLE_ARTH); EXPECT_EQ(insn.getInstructionAddress(), 0x43); EXPECT_EQ(insn.getInstructionId(), 15); EXPECT_EQ(insn.getKnownOffset(), 0);