diff --git a/src/include/simeng/arch/aarch64/helpers/sve.hh b/src/include/simeng/arch/aarch64/helpers/sve.hh
index 492a82d08..a2a5a404d 100644
--- a/src/include/simeng/arch/aarch64/helpers/sve.hh
+++ b/src/include/simeng/arch/aarch64/helpers/sve.hh
@@ -1086,12 +1086,12 @@ RegisterValue sveIndex(
   return {out, 256};
 }
 
-/** Helper function for SVE instructions with the format `lastb rd, pg, zn`.
+/** Helper function for SVE instructions with the format `lastb zd, pg, zn`.
  * T represents the vector register type (e.g. zd.d would be uint64_t).
  * Returns correctly formatted RegisterValue. */
 template <typename T>
-RegisterValue sveLastBScalar(srcValContainer& sourceValues,
-                             const uint16_t VL_bits) {
+RegisterValue sveLastBSimdScalar(srcValContainer& sourceValues,
+                                 const uint16_t VL_bits) {
   const uint64_t* p = sourceValues[0].getAsVector<uint64_t>();
   const T* n = sourceValues[1].getAsVector<T>();
 
diff --git a/src/lib/arch/aarch64/Instruction_execute.cc b/src/lib/arch/aarch64/Instruction_execute.cc
index cfd3be6f6..9b025398e 100644
--- a/src/lib/arch/aarch64/Instruction_execute.cc
+++ b/src/lib/arch/aarch64/Instruction_execute.cc
@@ -2649,19 +2649,19 @@ void Instruction::execute() {
         break;
       }
       case Opcode::AArch64_LASTB_VPZ_D: {  // lastb dd, pg, zn.d
-        results_[0] = sveLastBScalar<uint64_t>(sourceValues_, VL_bits);
+        results_[0] = sveLastBSimdScalar<uint64_t>(sourceValues_, VL_bits);
         break;
       }
       case Opcode::AArch64_LASTB_VPZ_S: {  // lastb sd, pg, zn.s
-        results_[0] = sveLastBScalar<uint32_t>(sourceValues_, VL_bits);
+        results_[0] = sveLastBSimdScalar<uint32_t>(sourceValues_, VL_bits);
         break;
       }
       case Opcode::AArch64_LASTB_VPZ_H: {  // lastb hd, pg, zn.h
-        results_[0] = sveLastBScalar<uint16_t>(sourceValues_, VL_bits);
+        results_[0] = sveLastBSimdScalar<uint16_t>(sourceValues_, VL_bits);
         break;
       }
       case Opcode::AArch64_LASTB_VPZ_B: {  // lastb bd, pg, zn.b
-        results_[0] = sveLastBScalar<uint8_t>(sourceValues_, VL_bits);
+        results_[0] = sveLastBSimdScalar<uint8_t>(sourceValues_, VL_bits);
         break;
       }
       case Opcode::AArch64_CLASTB_VPZ_D: {  // clastb dd, pg, dn, zn.d