| counter | LUv1w1 | LUv1w128 | LUv2w128 | LUv3w1 | LUv3w128 | LUv3w256 |
|---|---|---|---|---|---|---|
| duration | 18804.0000 | 12966.0000 | 12928.0000 | 28484.0000 | 13496.0000 | 10230.0000 |
| task-clock | 18758.1700 | 12920.4800 | 12879.9600 | 28436.7200 | 13448.1400 | 10176.6500 |
| cycles | 65.5432 | 45.1430 | 45.0400 | 99.4207 | 47.0158 | 35.5842 |
| stalled-cycles-backend | 0.0296 | 0.0000 | 0.0311 | 0.0000 | 0.0000 | 0.0249 |
| stalled-cycles-frontend | 0.0328 | 0.0252 | 0.0245 | 0.0477 | 0.0297 | 0.0360 |
| iTLB-load-misses | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| iTLB-loads | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| instructions | 366.2419 | 184.0925 | 184.0537 | 275.4774 | 138.7212 | 71.2203 |
| branch-instructions | 45.8251 | 23.1162 | 23.1071 | 45.8991 | 23.1298 | 11.8955 |
| branch-misses | 0.0667 | 0.0649 | 0.0649 | 0.0673 | 0.0649 | 0.0529 |
| ex_ret_ops | 320.8363 | 161.3172 | 161.2397 | 229.9458 | 115.8476 | 59.7142 |
| ex_div_busy | 0.0024 | 0.0017 | 0.0017 | 0.0037 | 0.0017 | 0.0013 |
| ex_ret_mmx_fp_instr.sse_instr | 228.4481 | 114.3669 | 114.3212 | 137.3419 | 68.8432 | 34.7657 |
| fp_ret_sse_avx_ops.all | 91.1590 | 90.9073 | 90.9670 | 91.2838 | 90.9883 | 90.7231 |
| fp_num_mov_elim_scal_op.sse_mov_ops | 0.0672 | 0.0680 | 0.0003 | 0.0000 | 0.0000 | 0.0000 |
| fp_num_mov_elim_scal_op.sse_mov_ops_elim | 0.0671 | 0.0680 | 0.0003 | 0.0000 | 0.0000 | 0.0000 |
| fp_ret_sse_avx_ops.add_sub_flops | 45.5895 | 45.5061 | 45.4147 | 0.0000 | 0.0000 | 0.0000 |
| fp_ret_sse_avx_ops.mult_flops | 45.6662 | 45.5972 | 45.5227 | 0.0667 | 0.0668 | 0.0664 |
| fp_ret_sse_avx_ops.mac_flops | 0.0000 | 0.0000 | 0.0000 | 91.2993 | 90.9491 | 90.6957 |
| fp_ret_sse_avx_ops.div_flops | 0.0001 | 0.0001 | 0.0001 | 0.0001 | 0.0001 | 0.0001 |
| de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch | 230.7012 | 116.4050 | 116.3664 | 138.0797 | 69.9852 | 35.8751 |
| de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch | 93.1612 | 47.7233 | 47.6548 | 92.9763 | 47.6622 | 25.5646 |
| cache-misses | 1.0660 | 1.0481 | 1.0557 | 1.6720 | 1.2380 | 1.8161 |
| cache-references | 16.2917 | 15.9480 | 15.9108 | 17.8252 | 16.2297 | 15.8417 |
| all_data_cache_accesses | 138.5783 | 70.1912 | 70.0429 | 138.0911 | 70.0091 | 36.2074 |
| L1-dcache-load-misses | 6.8684 | 6.8753 | 6.8684 | 6.9340 | 6.8648 | 6.8311 |
| L1-dcache-loads | 137.4327 | 77.9212 | 77.8904 | 137.5856 | 77.8968 | 48.6690 |
| L1-dcache-prefetches | 1.6385 | 0.9124 | 0.9277 | 6.1072 | 0.8397 | 0.6533 |
| L1-icache-load-misses | 0.0003 | 0.0005 | 0.0005 | 0.0008 | 0.0007 | 0.0011 |
| L1-icache-loads | 0.0775 | 0.0953 | 0.0653 | 0.1088 | 0.0759 | 0.1182 |
| l2_cache_accesses_from_dc_misses | 6.8663 | 6.8731 | 6.8671 | 6.9429 | 6.8785 | 6.8316 |
| l2_cache_hits_from_dc_misses | 6.0876 | 5.8205 | 5.8091 | 6.2108 | 5.8101 | 5.1146 |
| l2_cache_misses_from_dc_misses | 0.5293 | 0.7258 | 0.7263 | 0.4963 | 0.7320 | 1.1943 |
| dTLB-load-misses | 0.0001 | 0.0001 | 0.0001 | 0.0001 | 0.0001 | 0.0001 |
| dTLB-loads | 0.0752 | 0.0765 | 0.0765 | 0.0769 | 0.0754 | 0.0784 |
| ls_dispatch.ld_dispatch | 92.4154 | 46.8405 | 46.8986 | 92.1294 | 46.8981 | 24.3692 |
| ls_dispatch.ld_st_dispatch | 0.0020 | 0.0020 | 0.0018 | 0.0033 | 0.0018 | 0.0014 |
| ls_dispatch.store_dispatch | 46.0608 | 23.2053 | 23.2136 | 45.9509 | 23.2327 | 11.8387 |