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Confusing text when writing a cache value #165

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Yazwh0 opened this issue Mar 11, 2024 · 0 comments
Open

Confusing text when writing a cache value #165

Yazwh0 opened this issue Mar 11, 2024 · 0 comments

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@Yazwh0
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Yazwh0 commented Mar 11, 2024

Control over which parts are written are chosen by the value written to DATA0 or DATA1. The value written is treated as a nibble mask where a 0-bit writes the data and a 1-bit masks the data from being written.In other words, writing a 0 will flush the entire 32-bit cache. Writing #%00001111 will write the second and third byte in the cache to VRAM in the second and third memory locations in the 4-byte-aligned region.

In the paragraph above some of the language implies something that isn't happening.

writing a 0 will flush the entire 32-bit cache

The word 'flush' implies that the cache will be empty, or reset after writing it.

Writing #%00001111 will write the second and third byte

Is 'second' and 'third' bytes the right language? Byte 0, 1, 2 or 3 would make sense, but the second byte isnt byte 2. Maybe using the same language as the table (so L, M, H, and U) would be easier to understand?

https://github.com/X16Community/x16-docs/blob/master/X16%20Reference%20-%2010%20-%20VERA%20FX%20Reference.md#writing-the-cache-to-vram

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