From 59edc15775541e306a8c935da4251f89ec06574b Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 12 Sep 2023 16:40:04 +0800 Subject: [PATCH 01/27] review and fix UIMM field for all pulp instructions Signed-off-by: Vaibhav Jain --- .../corev-dv/custom/isa/custom/rv32x_instr.sv | 98 +++++++++---------- 1 file changed, 49 insertions(+), 49 deletions(-) diff --git a/cv32e40p/env/corev-dv/custom/isa/custom/rv32x_instr.sv b/cv32e40p/env/corev-dv/custom/isa/custom/rv32x_instr.sv index d6807e96d9..4a60f7833e 100644 --- a/cv32e40p/env/corev-dv/custom/isa/custom/rv32x_instr.sv +++ b/cv32e40p/env/corev-dv/custom/isa/custom/rv32x_instr.sv @@ -18,11 +18,11 @@ `DEFINE_CV32E40P_INSTR(CV_BNEIMM , B_FORMAT, BRANCH_IMM, RV32X) // HW LOOPS -`DEFINE_CV32E40P_INSTR(CV_START , I_FORMAT, HWLOOP, RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_START , I_FORMAT, HWLOOP, RV32X) `DEFINE_CV32E40P_INSTR(CV_STARTI, I_FORMAT, HWLOOP, RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_END , I_FORMAT, HWLOOP, RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_END , I_FORMAT, HWLOOP, RV32X) `DEFINE_CV32E40P_INSTR(CV_ENDI , I_FORMAT, HWLOOP, RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_COUNT , I_FORMAT, HWLOOP, RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_COUNT , I_FORMAT, HWLOOP, RV32X) `DEFINE_CV32E40P_INSTR(CV_COUNTI, I_FORMAT, HWLOOP, RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_SETUP , I_FORMAT, HWLOOP, RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_SETUPI, I_FORMAT, HWLOOP, RV32X, UIMM) @@ -121,18 +121,18 @@ `DEFINE_CV32E40P_INSTR(CV_AVGU_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_AVGU_SC_H , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_AVGU_SC_B , R_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_AVGU_SCI_H , I_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_AVGU_SCI_B , I_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_AVGU_SCI_H , I_FORMAT , SIMD , RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_AVGU_SCI_B , I_FORMAT , SIMD , RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_MIN_H , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_MIN_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_MIN_SC_H , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_MIN_SC_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_MIN_SCI_H , I_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_MIN_SCI_B , I_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_MINU_H , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_MINU_B , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_MINU_SC_H , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_MINU_SC_B , R_FORMAT , SIMD , RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_MINU_H , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_MINU_B , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_MINU_SC_H , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_MINU_SC_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_MINU_SCI_H , I_FORMAT , SIMD , RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_MINU_SCI_B , I_FORMAT , SIMD , RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_MAX_H , R_FORMAT , SIMD , RV32X) @@ -141,30 +141,30 @@ `DEFINE_CV32E40P_INSTR(CV_MAX_SC_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_MAX_SCI_H , I_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_MAX_SCI_B , I_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_MAXU_H , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_MAXU_B , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_MAXU_SC_H , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_MAXU_SC_B , R_FORMAT , SIMD , RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_MAXU_H , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_MAXU_B , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_MAXU_SC_H , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_MAXU_SC_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_MAXU_SCI_H , I_FORMAT , SIMD , RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_MAXU_SCI_B , I_FORMAT , SIMD , RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_SRL_H , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_SRL_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_SRL_SC_H , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_SRL_SC_B , R_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_SRL_SCI_H , I_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_SRL_SCI_B , I_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_SRL_SCI_H , I_FORMAT , SIMD , RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_SRL_SCI_B , I_FORMAT , SIMD , RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_SRA_H , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_SRA_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_SRA_SC_H , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_SRA_SC_B , R_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_SRA_SCI_H , I_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_SRA_SCI_B , I_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_SRA_SCI_H , I_FORMAT , SIMD , RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_SRA_SCI_B , I_FORMAT , SIMD , RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_SLL_H , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_SLL_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_SLL_SC_H , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_SLL_SC_B , R_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_SLL_SCI_H , I_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_SLL_SCI_B , I_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_SLL_SCI_H , I_FORMAT , SIMD , RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_SLL_SCI_B , I_FORMAT , SIMD , RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_OR_H , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_OR_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_OR_SC_H , R_FORMAT , SIMD , RV32X) @@ -185,10 +185,10 @@ `DEFINE_CV32E40P_INSTR(CV_AND_SCI_B , I_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_ABS_H , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_ABS_B , R_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_DOTUP_H , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_DOTUP_B , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_DOTUP_SC_H , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_DOTUP_SC_B , R_FORMAT , SIMD , RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_DOTUP_H , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_DOTUP_B , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_DOTUP_SC_H , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_DOTUP_SC_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_DOTUP_SCI_H , I_FORMAT , SIMD , RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_DOTUP_SCI_B , I_FORMAT , SIMD , RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_DOTUSP_H , R_FORMAT , SIMD , RV32X) @@ -203,10 +203,10 @@ `DEFINE_CV32E40P_INSTR(CV_DOTSP_SC_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_DOTSP_SCI_H , I_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_DOTSP_SCI_B , I_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_SDOTUP_H , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_SDOTUP_B , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_SDOTUP_SC_H , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_SDOTUP_SC_B , R_FORMAT , SIMD , RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_SDOTUP_H , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_SDOTUP_B , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_SDOTUP_SC_H , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_SDOTUP_SC_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_SDOTUP_SCI_H , I_FORMAT , SIMD , RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_SDOTUP_SCI_B , I_FORMAT , SIMD , RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_SDOTUSP_H , R_FORMAT , SIMD , RV32X) @@ -221,12 +221,12 @@ `DEFINE_CV32E40P_INSTR(CV_SDOTSP_SC_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_SDOTSP_SCI_H , I_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_SDOTSP_SCI_B , I_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_EXTRACT_H , I_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_EXTRACT_B , I_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_EXTRACTU_H , I_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_EXTRACTU_B , I_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_INSERT_H , I_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_INSERT_B , I_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_EXTRACT_H , I_FORMAT , SIMD , RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_EXTRACT_B , I_FORMAT , SIMD , RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_EXTRACTU_H , I_FORMAT , SIMD , RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_EXTRACTU_B , I_FORMAT , SIMD , RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_INSERT_H , I_FORMAT , SIMD , RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_INSERT_B , I_FORMAT , SIMD , RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_SHUFFLE_H , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_SHUFFLE_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_SHUFFLE_SCI_H , I_FORMAT , SIMD , RV32X, UIMM) @@ -276,28 +276,28 @@ `DEFINE_CV32E40P_INSTR(CV_CMPLE_SC_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_CMPLE_SCI_H , I_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_CMPLE_SCI_B , I_FORMAT , SIMD , RV32X) -`DEFINE_CV32E40P_INSTR(CV_CMPGTU_H , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_CMPGTU_B , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_CMPGTU_SC_H , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_CMPGTU_SC_B , R_FORMAT , SIMD , RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_CMPGTU_H , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_CMPGTU_B , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_CMPGTU_SC_H , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_CMPGTU_SC_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_CMPGTU_SCI_H , I_FORMAT , SIMD , RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_CMPGTU_SCI_B , I_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_CMPGEU_H , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_CMPGEU_B , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_CMPGEU_SC_H , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_CMPGEU_SC_B , R_FORMAT , SIMD , RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_CMPGEU_H , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_CMPGEU_B , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_CMPGEU_SC_H , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_CMPGEU_SC_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_CMPGEU_SCI_H , I_FORMAT , SIMD , RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_CMPGEU_SCI_B , I_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_CMPLTU_H , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_CMPLTU_B , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_CMPLTU_SC_H , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_CMPLTU_SC_B , R_FORMAT , SIMD , RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_CMPLTU_H , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_CMPLTU_B , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_CMPLTU_SC_H , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_CMPLTU_SC_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_CMPLTU_SCI_H , I_FORMAT , SIMD , RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_CMPLTU_SCI_B , I_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_CMPLEU_H , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_CMPLEU_B , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_CMPLEU_SC_H , R_FORMAT , SIMD , RV32X, UIMM) -`DEFINE_CV32E40P_INSTR(CV_CMPLEU_SC_B , R_FORMAT , SIMD , RV32X, UIMM) +`DEFINE_CV32E40P_INSTR(CV_CMPLEU_H , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_CMPLEU_B , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_CMPLEU_SC_H , R_FORMAT , SIMD , RV32X) +`DEFINE_CV32E40P_INSTR(CV_CMPLEU_SC_B , R_FORMAT , SIMD , RV32X) `DEFINE_CV32E40P_INSTR(CV_CMPLEU_SCI_H , I_FORMAT , SIMD , RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_CMPLEU_SCI_B , I_FORMAT , SIMD , RV32X, UIMM) `DEFINE_CV32E40P_INSTR(CV_CPLXMUL_R , R_FORMAT , SIMD , RV32X) From 4c441e860373e3e26aecb6a243816a59ec20901d Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 12 Sep 2023 16:42:50 +0800 Subject: [PATCH 02/27] update post-inc pulp load-store instr asm format aligning cv32e40p user manual v1.4.0 Signed-off-by: Vaibhav Jain --- .../custom/isa/custom/riscv_custom_instr.sv | 28 +++++++++++-------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv b/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv index 076abfc6c8..6055d03b43 100644 --- a/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv +++ b/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv @@ -322,8 +322,10 @@ class cv32e40p_instr extends riscv_instr; if(category != SYSTEM) begin case(format) I_FORMAT: begin // instr rd,rs1,imm more or less - if(category inside {POST_INC_LOAD, EVENT_LOAD}) - asm_str_final = $sformatf("%0s %0s, %0s(%0s%0s)", asm_str, rd.name(), get_imm(), rs1.name(), get_post_incr_str()); + if(category == POST_INC_LOAD) + asm_str_final = $sformatf("%0s %0s, (%0s), %0s", asm_str, rd.name(), rs1.name(), get_imm()); + else if (category == EVENT_LOAD) + asm_str_final = $sformatf("%0s %0s, %0s(%0s)", asm_str, rd.name(), get_imm(), rs1.name()); else if (category == BITMANIP) asm_str_final = $sformatf("%0s %0s, %0s, %0s", asm_str, rd.name(), rs1.name(), get_imm()); else if (category == HWLOOP) begin @@ -337,12 +339,20 @@ class cv32e40p_instr extends riscv_instr; asm_str_final = $sformatf("%0s %0s, %0s, %0s", asm_str, rd.name(), rs1.name(), get_imm()); end R_FORMAT: begin - if (category == POST_INC_LOAD) - asm_str_final = $sformatf("%0s %0s, %0s(%0s%0s)", asm_str, rd.name(), rs2.name(), rs1.name(), get_post_incr_str()); + if (category == POST_INC_LOAD) begin + if(is_post_incr) + asm_str_final = $sformatf("%0s %0s, (%0s), %0s", asm_str, rd.name(), rs1.name(), rs2.name()); + else + asm_str_final = $sformatf("%0s %0s, %0s(%0s)", asm_str, rd.name(), rs2.name(), rs1.name()); + end - else if (category == POST_INC_STORE) + else if (category == POST_INC_STORE) begin // rd is used as offset (rs3 in mnemonic, no use to add another register in the sv class just for this) - asm_str_final = $sformatf("%0s %0s, %0s(%0s%0s)", asm_str, rs2.name(), rd.name(), rs1.name(), get_post_incr_str()); + if(is_post_incr) + asm_str_final = $sformatf("%0s %0s, (%0s), %0s", asm_str, rs2.name(), rs1.name(), rd.name()); + else + asm_str_final = $sformatf("%0s %0s, %0s(%0s)", asm_str, rs2.name(), rd.name(), rs1.name()); + end else if (category == BITMANIP && instr_name inside {CV_FF1, CV_FL1, CV_CLB, CV_CNT}) asm_str_final = $sformatf("%0s %0s, %0s", asm_str, rd.name(), rs1.name()); @@ -363,7 +373,7 @@ class cv32e40p_instr extends riscv_instr; end S_FORMAT: begin // instr rs1,rs2,imm if(category == POST_INC_STORE) - asm_str_final = $sformatf("%0s %0s, %0s(%0s!)", asm_str, rs2.name(), get_imm(), rs1.name()); + asm_str_final = $sformatf("%0s %0s, (%0s), %0s", asm_str, rs2.name(), rs1.name(), get_imm()); else if (category inside {ALU, MAC} ) asm_str_final = $sformatf("%0s %0s, %0s, %0s, %0s", asm_str, rd.name(), rs1.name(), rs2.name(), get_imm()); else @@ -691,10 +701,6 @@ class cv32e40p_instr extends riscv_instr; super.update_imm_str(); endfunction - virtual function string get_post_incr_str(); - return (is_post_incr) ? "!" : ""; - endfunction : get_post_incr_str - // `include "isa/riscv_instr_cov.svh" endclass From 8ce22f7db41587e8f9b6d207aee7b1c4b758d382 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 12 Sep 2023 16:44:41 +0800 Subject: [PATCH 03/27] change cv_slet,cv_sletu instr asm to cv_sle,cv_sleu to align with cv32e40p user manual v1.4.0 Signed-off-by: Vaibhav Jain --- cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv | 4 ++-- .../env/corev-dv/custom/isa/custom/riscv_custom_instr_enum.sv | 4 ++-- cv32e40p/env/corev-dv/custom/isa/custom/rv32x_instr.sv | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv b/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv index 6055d03b43..aa66013e7e 100644 --- a/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv +++ b/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv @@ -419,7 +419,7 @@ class cv32e40p_instr extends riscv_instr; CV_EXTRACT, CV_EXTRACTU, CV_INSERT, CV_BCLR, CV_BSET, CV_BITREV : get_opcode = 7'b1011011; // General ALU - CV_ABS, CV_SLET, CV_SLETU, CV_MIN, CV_MINU, + CV_ABS, CV_SLE, CV_SLEU, CV_MIN, CV_MINU, CV_MAX, CV_MAXU, CV_EXTHS, CV_EXTHZ, CV_EXTBS, CV_EXTBZ, CV_CLIP, CV_CLIPU, CV_CLIPR, CV_CLIPUR, CV_ADDNR, CV_ADDUNR, CV_ADDRNR, CV_ADDURNR, @@ -581,7 +581,7 @@ class cv32e40p_instr extends riscv_instr; CV_EXTRACT, CV_EXTRACTU, CV_INSERT : get_func3 = 3'b000; CV_BCLR, CV_BSET, CV_BITREV : get_func3 = 3'b001; // General ALU - CV_ABS, CV_SLET, CV_SLETU, CV_MIN, CV_MINU, + CV_ABS, CV_SLE, CV_SLEU, CV_MIN, CV_MINU, CV_MAX, CV_MAXU, CV_EXTHS, CV_EXTHZ, CV_EXTBS, CV_EXTBZ, CV_CLIP, CV_CLIPU, CV_CLIPR, CV_CLIPUR, CV_ADDNR, CV_ADDUNR, CV_ADDRNR, CV_ADDURNR, diff --git a/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr_enum.sv b/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr_enum.sv index fc2a7b508a..cd44a53576 100644 --- a/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr_enum.sv +++ b/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr_enum.sv @@ -35,8 +35,8 @@ CV_CLB, CV_CNT, CV_ABS, - CV_SLET, - CV_SLETU, + CV_SLE, + CV_SLEU, CV_MIN, CV_MINU, CV_MAX, diff --git a/cv32e40p/env/corev-dv/custom/isa/custom/rv32x_instr.sv b/cv32e40p/env/corev-dv/custom/isa/custom/rv32x_instr.sv index 4a60f7833e..ee4135b9c1 100644 --- a/cv32e40p/env/corev-dv/custom/isa/custom/rv32x_instr.sv +++ b/cv32e40p/env/corev-dv/custom/isa/custom/rv32x_instr.sv @@ -47,8 +47,8 @@ // ALU `DEFINE_CV32E40P_INSTR(CV_ABS , R_FORMAT , ALU , RV32X) -`DEFINE_CV32E40P_INSTR(CV_SLET , R_FORMAT , ALU , RV32X) -`DEFINE_CV32E40P_INSTR(CV_SLETU , R_FORMAT , ALU , RV32X) +`DEFINE_CV32E40P_INSTR(CV_SLE , R_FORMAT , ALU , RV32X) +`DEFINE_CV32E40P_INSTR(CV_SLEU , R_FORMAT , ALU , RV32X) `DEFINE_CV32E40P_INSTR(CV_MIN , R_FORMAT , ALU , RV32X) `DEFINE_CV32E40P_INSTR(CV_MINU , R_FORMAT , ALU , RV32X) `DEFINE_CV32E40P_INSTR(CV_MAX , R_FORMAT , ALU , RV32X) From 11a2694b83a0a5c6b52684d5aea28159d158cc9e Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Tue, 12 Sep 2023 11:07:44 +0200 Subject: [PATCH 04/27] fix when no cfg_file is available for the test --- bin/templates/regress_rmdb.j2 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/templates/regress_rmdb.j2 b/bin/templates/regress_rmdb.j2 index c2ab88850e..ab342040dc 100644 --- a/bin/templates/regress_rmdb.j2 +++ b/bin/templates/regress_rmdb.j2 @@ -119,7 +119,7 @@ [getParameterByPriority "{{config}}" "{{t.cfg}}" "(%build_config:%)"] [getParameterByPriority "" "{{t.test_cfg}}" "(%build_test_cfg:%)"] - [getTestCfgName (%t_test_cfg:%)] + [getTestCfgName "(%t_test_cfg:%)"] [getParameterByPriorityYesOrNo "{{iss}}" "{{t.iss}}" "(%build_iss:%)"] [getParameterByPriorityYesOrNo "{{coverage}}" "{{t.cov}}" "(%build_cov:%)"] [GetRandomValues {{t.num}}] From a43abb0729e69f0b722e64e43ea5a797dd0d5e53 Mon Sep 17 00:00:00 2001 From: bsm Date: Wed, 13 Sep 2023 09:21:00 +0800 Subject: [PATCH 05/27] Resolve fixme Signed-off-by: bsm --- .../isa/cv32e40p_riscv_compressed_instr.sv | 276 +++++++++++++----- 1 file changed, 204 insertions(+), 72 deletions(-) diff --git a/cv32e40p/env/corev-dv/custom/isa/cv32e40p_riscv_compressed_instr.sv b/cv32e40p/env/corev-dv/custom/isa/cv32e40p_riscv_compressed_instr.sv index 94da416622..106b242e48 100644 --- a/cv32e40p/env/corev-dv/custom/isa/cv32e40p_riscv_compressed_instr.sv +++ b/cv32e40p/env/corev-dv/custom/isa/cv32e40p_riscv_compressed_instr.sv @@ -1,5 +1,8 @@ /* * Copyright 2020 Google LLC + * Copyright 2023 OpenHW Group + * Copyright 2023 Dolphin Design + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -12,46 +15,33 @@ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - * - * - * Copyright 2023 OpenHW Group - * Copyright 2023 Dolphin Design - * - * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 */ class cv32e40p_riscv_compressed_instr extends riscv_compressed_instr; - rand riscv_fpr_t fs1; rand riscv_fpr_t fs2; rand riscv_fpr_t fd; - rand bit[4:0] reg_idx_fs2; //FIXME : dd-vaibhavjain - rand bit[4:0] reg_idx_fd; //FIXME : dd-vaibhavjain - //FIXME: dd-vaibhavjain. Remove after toolchain fix - constraint rv32fc_reg_idx_temp_c { - if (instr_name == C_FLW) { - reg_idx_fd inside {[8:15]}; - } - if (instr_name == C_FSW) { - reg_idx_fs2 inside {[8:15]}; - } - } + bit has_fs2 = 1'b0; + bit has_fd = 1'b0; constraint rvc_csr_c { // Registers specified by the three-bit rs1’, rs2’, and rd’ if (format inside {CIW_FORMAT, CL_FORMAT, CS_FORMAT, CB_FORMAT, CA_FORMAT}) { if (has_rs1) { rs1 inside {[S0:A5]}; - fs1 inside {[S0:A5]}; } if (has_rs2) { rs2 inside {[S0:A5]}; - fs2 inside {[S0:A5]}; } if (has_rd) { rd inside {[S0:A5]}; - fd inside {[S0:A5]}; + } + if (has_fs2) { + fs2 inside {[FS0:FA5]}; + } + if (has_fd) { + fd inside {[FS0:FA5]}; } } // C_ADDI16SP is only valid when rd == SP @@ -68,55 +58,83 @@ class cv32e40p_riscv_compressed_instr extends riscv_compressed_instr; function new(string name = ""); super.new(name); - fs1 = FS0; fs2 = FS0; fd = FS0; endfunction : new virtual function void set_imm_len(); - if (format inside {CI_FORMAT, CSS_FORMAT}) begin - imm_len = 6; - end else if (format inside {CL_FORMAT, CS_FORMAT}) begin - imm_len = 5; - end else if (format inside {CJ_FORMAT}) begin - imm_len = 11; - end else if (format inside {CB_FORMAT}) begin - if (instr_name == C_ANDI) begin - imm_len = 6; - end else begin - imm_len = 7; - end - end else if (format inside {CB_FORMAT, CIW_FORMAT}) begin - imm_len = 8; - end - if (instr_name inside {C_SQ, C_LQ, C_LQSP, C_SQSP, C_ADDI16SP}) begin - imm_align = 4; - end else if (instr_name inside {C_SD, C_LD, C_LDSP, C_SDSP}) begin - imm_align = 3; - end else if (instr_name inside {C_SW, C_LW, C_LWSP, C_SWSP, C_ADDI4SPN, C_FSW, C_FLW, C_FLWSP, C_FSWSP}) begin + super.set_imm_len(); + if (instr_name inside {C_FSW, C_FLW, C_FLWSP, C_FSWSP}) begin imm_align = 2; - end else if (instr_name inside {C_LUI}) begin - imm_align = 12; - end else if (instr_name inside {C_J, C_JAL, C_BNEZ, C_BEQZ}) begin - imm_align = 1; end endfunction : set_imm_len + virtual function void do_copy(uvm_object rhs); + cv32e40p_riscv_compressed_instr rhs_; + super.copy(rhs); + assert($cast(rhs_, rhs)); + this.fs2 = rhs_.fs2; + this.fd = rhs_.fd; + this.has_fs2 = rhs_.has_fs2; + this.has_fd = rhs_.has_fd; + endfunction : do_copy + + virtual function void set_rand_mode(); + case (format) inside + CR_FORMAT : begin + if (category == JUMP) begin + has_rd = 1'b0; + end else begin + has_rs1 = 1'b0; + end + has_imm = 1'b0; + end + CSS_FORMAT : begin + has_rs1 = 1'b0; + has_rd = 1'b0; + if (instr_name == C_FSWSP) has_fs2 = 1'b1; + end + CL_FORMAT: begin + has_rs2 = 1'b0; + if (instr_name == C_FLW) has_fd = 1'b1; + end + CS_FORMAT : begin + has_rd = 1'b0; + if (instr_name == C_FSW) has_fs2 = 1'b1; + end + CA_FORMAT: begin + has_rs1 = 1'b0; + has_imm = 1'b0; + end + CI_FORMAT, CIW_FORMAT: begin + has_rs1 = 1'b0; + has_rs2 = 1'b0; + if (instr_name == C_FLWSP) has_fd = 1'b1; + end + CJ_FORMAT: begin + has_rs1 = 1'b0; + has_rs2 = 1'b0; + has_rd = 1'b0; + end + CB_FORMAT: begin + if (instr_name != C_ANDI) has_rd = 1'b0; + has_rs2 = 1'b0; + end + endcase + endfunction + // Convert the instruction to assembly code virtual function string convert2asm(string prefix = ""); string asm_str; asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN); - std::randomize(reg_idx_fs2) with { if (instr_name == C_FSW) { - reg_idx_fs2 inside {[8:15]}; - } - }; //FIXME : dd-vaibhavjain - - std::randomize(reg_idx_fd) with { if (instr_name == C_FLW) { - reg_idx_fd inside {[8:15]}; - } - }; //FIXME : dd-vaibhavjain - + // workaround: ensure all floating compressed have random fd and fs within a stream + if (instr_name inside {C_FSW, C_FLW}) begin + std::randomize(fs2) with { fs2 inside {[FS0:FA5]}; }; + end + if (instr_name inside {C_FSW, C_FLW, C_FSWSP, C_FLWSP}) begin + std::randomize(fd) with { fd inside {[FS0:FA5]}; }; + end if (category != SYSTEM) begin case(format) @@ -129,24 +147,22 @@ class cv32e40p_riscv_compressed_instr extends riscv_compressed_instr; asm_str = $sformatf("%0s%0s, sp, %0s", asm_str, rd.name(), get_imm()); else if (instr_name inside {C_LDSP, C_LWSP, C_LQSP}) asm_str = $sformatf("%0s%0s, %0s(sp)", asm_str, rd.name(), get_imm()); - else if (instr_name inside {C_FLWSP}) - //asm_str = $sformatf("%0s%0s, %0s(sp)", asm_str, fd.name(), get_imm()); - asm_str = $sformatf("%0s f%0d, %0s(sp)", asm_str, reg_idx_fd, get_imm()); //FIXME : dd-vaibhavjain. revert temp wrd after toolchain fix + else if (instr_name == C_FLWSP) + asm_str = $sformatf("%0s%0s, %0s(sp)", asm_str, fd.name(), get_imm()); else asm_str = $sformatf("%0s%0s, %0s", asm_str, rd.name(), get_imm()); CL_FORMAT: - if (instr_name == C_FLW) - //asm_str = $sformatf("%0s%0s, %0s(%0s)", asm_str, fd.name(), get_imm(), rs1.name()); - asm_str = $sformatf("%0s f%0d, %0s(%0s)", asm_str, reg_idx_fd, get_imm(), rs1.name()); //FIXME : dd-vaibhavjain. revert temp wrd after toolchain fix - else - asm_str = $sformatf("%0s%0s, %0s(%0s)", asm_str, rd.name(), get_imm(), rs1.name()); + if (instr_name == C_FLW) + asm_str = $sformatf("%0s%0s, %0s(%0s)", asm_str, fd.name(), get_imm(), rs1.name()); + else + asm_str = $sformatf("%0s%0s, %0s(%0s)", asm_str, rd.name(), get_imm(), rs1.name()); CS_FORMAT: - if (category == STORE) + if (category == STORE) begin if (instr_name == C_FSW) - //asm_str = $sformatf("%0s%0s, %0s(%0s)", asm_str, fs2.name(), get_imm(), rs1.name()); - asm_str = $sformatf("%0s f%0d, %0s(%0s)", asm_str, reg_idx_fs2, get_imm(), rs1.name()); //FIXME : dd-vaibhavjain. revert temp wrd after toolchain fix - else + asm_str = $sformatf("%0s%0s, %0s(%0s)", asm_str, fs2.name(), get_imm(), rs1.name()); + else asm_str = $sformatf("%0s%0s, %0s(%0s)", asm_str, rs2.name(), get_imm(), rs1.name()); + end else asm_str = $sformatf("%0s%0s, %0s", asm_str, rs1.name(), rs2.name()); CA_FORMAT: @@ -154,12 +170,12 @@ class cv32e40p_riscv_compressed_instr extends riscv_compressed_instr; CB_FORMAT: asm_str = $sformatf("%0s%0s, %0s", asm_str, rs1.name(), get_imm()); CSS_FORMAT: - if (category == STORE) + if (category == STORE) begin if (instr_name == C_FSWSP) - //asm_str = $sformatf("%0s%0s, %0s(sp)", asm_str, fs2.name(), get_imm()); - asm_str = $sformatf("%0s f%0d, %0s(sp)", asm_str, reg_idx_fs2, get_imm()); //FIXME : dd-vaibhavjain. revert temp wrd after toolchain fix + asm_str = $sformatf("%0s%0s, %0s(sp)", asm_str, fs2.name(), get_imm()); else asm_str = $sformatf("%0s%0s, %0s(sp)", asm_str, rs2.name(), get_imm()); + end else asm_str = $sformatf("%0s%0s, %0s", asm_str, rs2.name(), get_imm()); CR_FORMAT: @@ -183,5 +199,121 @@ class cv32e40p_riscv_compressed_instr extends riscv_compressed_instr; asm_str = {asm_str, " #",comment}; return asm_str.tolower(); endfunction : convert2asm - + + // Convert the instruction to assembly code + virtual function string convert2bin(string prefix = ""); + string binary; + case (instr_name) inside + C_ADDI4SPN: + binary = $sformatf("%4h", {get_func3(), imm[5:4], imm[9:6], + imm[2], imm[3], get_c_gpr(rd), get_c_opcode()}); + C_LQ: + binary = $sformatf("%4h", {get_func3(), imm[5:4], imm[8], + get_c_gpr(rs1), imm[7:6], get_c_gpr(rd), get_c_opcode()}); + C_FLD, C_LD: + binary = $sformatf("%4h", {get_func3(), imm[5:3], get_c_gpr(rs1), + imm[7:6], get_c_gpr(rd), get_c_opcode()}); + C_LW: + binary = $sformatf("%4h", {get_func3(), imm[5:3], get_c_gpr(rs1), + imm[2], imm[6], get_c_gpr(rd), get_c_opcode()}); + C_FLW: + binary = $sformatf("%4h", {get_func3(), imm[5:3], get_c_gpr(rs1), + imm[2], imm[6], get_c_fpr(fd), get_c_opcode()}); + C_SQ: + binary = $sformatf("%4h", {get_func3(), imm[5:4], imm[8], + get_c_gpr(rs1), imm[7:6], get_c_gpr(rs2), get_c_opcode()}); + C_FSD, C_SD: + binary = $sformatf("%4h", {get_func3(), imm[5:3], get_c_gpr(rs1), + imm[7:6], get_c_gpr(rs2), get_c_opcode()}); + C_SW: + binary = $sformatf("%4h", {get_func3(), imm[5:3], get_c_gpr(rs1), + imm[2], imm[6], get_c_gpr(rs2), get_c_opcode()}); + C_FSW: + binary = $sformatf("%4h", {get_func3(), imm[5:3], get_c_gpr(rs1), + imm[2], imm[6], get_c_fpr(fs2), get_c_opcode()}); + C_NOP, C_ADDI, C_LI, C_ADDIW: + binary = $sformatf("%4h", {get_func3(), imm[5], rd, imm[4:0], get_c_opcode()}); + C_JAL, C_J: + binary = $sformatf("%4h", {get_func3(), imm[11], imm[4], imm[9:8], + imm[10], imm[6], imm[7], imm[3:1], imm[5], get_c_opcode()}); + C_ADDI16SP: + binary = $sformatf("%4h", {get_func3(), imm[9], 5'b00010, + imm[4], imm[6], imm[8:7], imm[5], get_c_opcode()}); + C_LUI: + binary = $sformatf("%4h", {get_func3(), imm[5], rd, imm[4:0], get_c_opcode()}); + C_SRLI: + binary = $sformatf("%4h", {get_func3(), imm[5], + 2'b0, get_c_gpr(rd), imm[4:0], get_c_opcode()}); + C_SRLI64: + binary = $sformatf("%4h", {get_func3(), 3'b0, get_c_gpr(rd), 5'b0, get_c_opcode()}); + C_SRAI: + binary = $sformatf("%4h", {get_func3(), imm[5], + 2'b01, get_c_gpr(rd), imm[4:0], get_c_opcode()}); + C_SRAI64: + binary = $sformatf("%4h", {get_func3(), 3'b001, + get_c_gpr(rd), 5'b0, get_c_opcode()}); + C_ANDI: + binary = $sformatf("%4h", {get_func3(), imm[5], + 2'b10, get_c_gpr(rd), imm[4:0], get_c_opcode()}); + C_SUB: + binary = $sformatf("%4h", {get_func3(), 3'b011, get_c_gpr(rd), + 2'b00, get_c_gpr(rs2), get_c_opcode()}); + C_XOR: + binary = $sformatf("%4h", {get_func3(), 3'b011, get_c_gpr(rd), + 2'b01, get_c_gpr(rs2), get_c_opcode()}); + C_OR: + binary = $sformatf("%4h", {get_func3(), 3'b011, get_c_gpr(rd), + 2'b10, get_c_gpr(rs2), get_c_opcode()}); + C_AND: + binary = $sformatf("%4h", {get_func3(), 3'b011, get_c_gpr(rd), + 2'b11, get_c_gpr(rs2), get_c_opcode()}); + C_SUBW: + binary = $sformatf("%4h", {get_func3(), 3'b111, get_c_gpr(rd), + 2'b00, get_c_gpr(rs2), get_c_opcode()}); + C_ADDW: + binary = $sformatf("%4h", {get_func3(), 3'b111, get_c_gpr(rd), + 2'b01, get_c_gpr(rs2), get_c_opcode()}); + C_BEQZ, C_BNEZ: + binary = $sformatf("%4h", {get_func3(), imm[8], imm[4:3], + get_c_gpr(rs1), imm[7:6], imm[2:1], imm[5], get_c_opcode()}); + C_SLLI: + binary = $sformatf("%4h", {get_func3(), imm[5], rd, imm[4:0], get_c_opcode()}); + C_SLLI64: + binary = $sformatf("%4h", {get_func3(), 1'b0, rd, 5'b0, get_c_opcode()}); + C_FLDSP, C_LDSP: + binary = $sformatf("%4h", {get_func3(), imm[5], rd, imm[4:3], imm[8:6], get_c_opcode()}); + C_LQSP: + binary = $sformatf("%4h", {get_func3(), imm[5], rd, imm[4], imm[9:6], get_c_opcode()}); + C_LWSP: + binary = $sformatf("%4h", {get_func3(), imm[5], rd, imm[4:2], imm[7:6], get_c_opcode()}); + C_FLWSP: + binary = $sformatf("%4h", {get_func3(), imm[5], fd, imm[4:2], imm[7:6], get_c_opcode()}); + C_JR: + binary = $sformatf("%4h", {get_func3(), 1'b0, rs1, 5'b0, get_c_opcode()}); + C_MV: + binary = $sformatf("%4h", {get_func3(), 1'b0, rd, rs2, get_c_opcode()}); + C_EBREAK: + binary = $sformatf("%4h", {get_func3(), 1'b1, 10'b0, get_c_opcode()}); + C_JALR: + binary = $sformatf("%4h", {get_func3(), 1'b1, 10'b0, get_c_opcode()}); + C_ADD: + binary = $sformatf("%4h", {get_func3(), 1'b1, rd, rs2, get_c_opcode()}); + C_FSDSP, C_SDSP: + binary = $sformatf("%4h", {get_func3(), imm[5:3], imm[8:6], rs2, get_c_opcode()}); + C_SQSP: + binary = $sformatf("%4h", {get_func3(), imm[5:4], imm[9:6], rs2, get_c_opcode()}); + C_SWSP: + binary = $sformatf("%4h", {get_func3(), imm[5:2], imm[7:6], rs2, get_c_opcode()}); + C_FSWSP: + binary = $sformatf("%4h", {get_func3(), imm[5:2], imm[7:6], fs2, get_c_opcode()}); + default : `uvm_fatal(`gfn, $sformatf("Unsupported instruction %0s", instr_name.name())) + endcase + return {prefix, binary}; + endfunction : convert2bin + + // Get RVFC register name for CL, CS format + function bit [2:0] get_c_fpr(riscv_fpr_t fpr); + return fpr[2:0]; + endfunction + endclass : cv32e40p_riscv_compressed_instr From 7d1eeea5c0293403c7f9c9ae6c730cbe16091f77 Mon Sep 17 00:00:00 2001 From: bsm Date: Wed, 13 Sep 2023 09:22:01 +0800 Subject: [PATCH 06/27] Update existing stream to include compress floating instructions Signed-off-by: bsm --- .../instr_lib/cv32e40p_float_instr_lib.sv | 300 +++++++++++------- .../cv32e40p_float_instr_lib_defines.sv | 38 +-- 2 files changed, 206 insertions(+), 132 deletions(-) diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv index 4ec4bfb025..64e2109bd2 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv @@ -27,6 +27,7 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; localparam TOTAL_INSTR_F_TYPE = 26; + localparam TOTAL_INSTR_FC_TYPE = 4; localparam TOTAL_INSTR_ZFINX_TYPE = 22; localparam MAX_D_REG = 1; // rd/fd localparam MAX_S_REG = 3; // rs/fs @@ -68,6 +69,7 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; riscv_instr_category_t exclude_category[]; riscv_instr_group_t include_group[]; riscv_instr_group_t exclude_group[]; + bit use_special_operand_patterns; // use special pattern opeands on directed instrs bit use_fp_only_for_directed_instr; // use fp instr only as directed instrs in stream bit use_no_repetitive_instr_per_stream; // directed instr is not allow to repeat in a stream bit use_same_instr_per_stream; // same directed is use within a stream @@ -76,6 +78,7 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; bit init_gpr = (is_zfinx) ? 1 : 0; // initialize gpr registers in stream with rand value bit init_fpr = (is_zfinx) ? 0 : 1; // initialize fpr registers in stream with rand value bit en_clr_fflags_af_instr; // clear fflag to prevent residual fflags status of current f_instr + bit include_load_store_base_sp; // include store instr that uses sp // for use_prev_rd_on_next_operands implementation usage - start riscv_reg_t prev_rd; @@ -86,14 +89,15 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; // for use_prev_rd_on_next_operands implementation usage - end rand int unsigned num_of_instr_per_stream; - rand riscv_reg_t avail_gp_regs[][]; // regs for extension zfinx and f - rand riscv_fpr_t avail_fp_regs[][]; // regs for extension f only - rand riscv_reg_t gp_scratch_reg; // allocation for scratch reg + rand riscv_reg_t avail_gp_regs[][]; // regs for extension zfinx and f + rand riscv_fpr_t avail_fp_regs[][]; // regs for extension f only + rand riscv_reg_t gp_reg_scratch; // allocation for scratch reg + rand riscv_reg_t gp_reg_sp; // allocation for store instr that uses sp rand bit [31:0] imm; rand f_rounding_mode_t rm; rand bit use_rounding_mode_from_instr; - rand bit enable_special_operand_patterns; + // rand bit use_special_operand_patterns; rand operand_pattens_t operand_a_pattern[]; rand operand_pattens_t operand_b_pattern[]; rand operand_pattens_t operand_c_pattern[]; @@ -109,13 +113,12 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; constraint c_others { if (use_no_repetitive_instr_per_stream) { if (is_zfinx) {soft num_of_instr_per_stream inside {[TOTAL_INSTR_ZFINX_TYPE/2 : TOTAL_INSTR_ZFINX_TYPE]};} - else {soft num_of_instr_per_stream inside {[TOTAL_INSTR_F_TYPE/2 : TOTAL_INSTR_F_TYPE]};} + else {soft num_of_instr_per_stream inside {[(TOTAL_INSTR_F_TYPE+TOTAL_INSTR_FC_TYPE)/2 : (TOTAL_INSTR_F_TYPE+TOTAL_INSTR_FC_TYPE)]};} } else { if (en_clr_fflags_af_instr) {soft num_of_instr_per_stream == 50;} else {soft num_of_instr_per_stream == 100;} } num_of_instr_per_stream > 0; - solve num_of_instr_per_stream before enable_special_operand_patterns; } constraint c_avail_gp_regs { @@ -123,17 +126,27 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; foreach (avail_gp_regs[i]) { soft avail_gp_regs[i].size() == 10; // more buffer as some dedicated gpr should not been used unique{avail_gp_regs[i]}; - soft avail_gp_regs[i][0] inside {[S0:A5]}; // MUST: RV32C only uses 8 most common regs + soft avail_gp_regs[i][0] inside {[S0:A5]}; // MUST: RV32C only uses 8 most common xregs soft avail_gp_regs[i][1] inside {SP}; // MUST: some random instr uses SP as rd foreach (avail_gp_regs[i][j]) { - !(avail_gp_regs[i][j] inside {cfg.reserved_regs, reserved_rd, gp_scratch_reg}); + !(avail_gp_regs[i][j] inside {cfg.reserved_regs, reserved_rd, gp_reg_scratch, gp_reg_sp}); } } } - constraint c_gp_scratch_reg { - !(gp_scratch_reg inside {cfg.reserved_regs, reserved_rd, ZERO, SP}); - solve gp_scratch_reg before avail_gp_regs; + constraint c_gp_reg_scratch { + !(gp_reg_scratch inside {cfg.reserved_regs, reserved_rd, ZERO, SP}); + solve gp_reg_scratch before avail_gp_regs; + } + + constraint c_gp_reg_sp { + soft gp_reg_sp == gp_reg_scratch; + if (include_load_store_base_sp) { + if (cv32e40p_cfg.sp != SP) { + gp_reg_sp == SP; // reserve this for load-store-sp + } + } + solve gp_reg_sp before avail_gp_regs; } constraint c_avail_fp_regs { @@ -142,13 +155,11 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; soft avail_fp_regs[i].size() > FLEN/2; // widen the range of selections soft avail_fp_regs[i].size() < FLEN + 1; // total of available fpr unique{avail_fp_regs[i]}; + soft avail_fp_regs[i][0] inside {[FS0:FA5]}; // MUST: RV32CF only uses 8 most common fregs - fs + soft avail_fp_regs[i][1] inside {[FS0:FA5]}; // MUST: RV32CF only uses 8 most common fregs - fd } } - constraint c_enable_special_operand_patterns { - soft enable_special_operand_patterns == 0; - } - `C_OPERAND_PATTERN(a) `C_OPERAND_PATTERN(b) `C_OPERAND_PATTERN(c) @@ -167,10 +178,12 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; function void pre_randomize(); super.pre_randomize(); + use_special_operand_patterns = 0; use_fp_only_for_directed_instr = 1; // directed instr is fp only use_prev_rd_on_next_operands = 0; use_no_repetitive_instr_per_stream = 0; en_clr_fflags_af_instr = 1; + include_load_store_base_sp = $urandom_range(1); endfunction: pre_randomize function void post_randomize(); @@ -181,7 +194,7 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; print_stream_setting(); initialize_regs(); - if (enable_special_operand_patterns) begin + if (use_special_operand_patterns) begin foreach (operand_a[i]) begin `uvm_info(_header, $sformatf(">> Specific operand patterns \ \n>> instr[%0d] operand_a is %0d [%s]\ @@ -191,9 +204,9 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; i, operand_a[i][31:12], operand_a_pattern[i], i, operand_b[i][31:12], operand_b_pattern[i], i, operand_c[i][31:12], operand_c_pattern[i]), UVM_DEBUG); - // i, operand_c[i][31:12], operand_c_pattern[i]), (enable_special_operand_patterns) ? UVM_NONE : UVM_DEBUG); + // i, operand_c[i][31:12], operand_c_pattern[i]), (use_special_operand_patterns) ? UVM_NONE : UVM_DEBUG); end - end // enable_special_operand_patterns + end for (int i = 0; i < num_of_instr_per_stream; i++) begin : GEN_N_MANIPULATE_INSTR @@ -215,19 +228,20 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; // directed instr randomization based on extension if (!is_fp_instr) begin : OTHER_NON_FP_SUPPORTED_EXTENSIONS randomize_gpr(instr); - if (!(instr.group == RV32C)) f_use_prev_rd_on_next_operands(.p_instr((use_prev_rd_on_next_operands) ? instr : null), .idx(i)); - if (instr.instr_name inside {SB, SH, SW, C_SW, C_SWSP}) begin: SPECIAL_HANDLING_FOR_STORE - wa_prevent_store_on_code_space(instr); + if (!(instr.group == RV32C || instr.group == RV32FC)) + f_use_prev_rd_on_next_operands(.p_instr((use_prev_rd_on_next_operands) ? instr : null), .idx(i)); + if (instr.instr_name inside {`STORE_INSTR_LIST, `FP_STORE_INSTR_LIST}) begin + // wa_prevent_store_on_code_space(instr); + store_instr_gpr_handling(instr); end instr_list.push_back(instr); end else if (is_zfinx) begin : EXTENSION_ZFINX - `DV_CHECK_FATAL($cast(instr_zfinx, instr), "Cast to instr_zfinx failed!"); + `DV_CHECK_FATAL($cast(instr_zfinx, instr), $sformatf("Cast to instr_zfinx failed for %s!", instr.instr_name.name()) ); randomize_gpr_zfinx(instr_zfinx, i); f_use_prev_rd_on_next_operands(.p_instr_zfinx((use_prev_rd_on_next_operands) ? instr_zfinx : null), .idx(i)); - if (enable_special_operand_patterns) begin : OVERRIDE_OPERANDS_W_SPECIAL_PATTERNS + if (use_special_operand_patterns) rand_fp_special_operands_zfinx(instr_zfinx, i); - end instr_list.push_back(instr_zfinx); `uvm_info(_header, $sformatf("\n>>>> instr_zfinx[%s] >>>> \ \n>> has_rs1 | has_rs2 | has_rs3 | has_rd | has_imm -> %0b , %0b , %0b , %0b , %0b \ @@ -238,15 +252,15 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; instr_zfinx.rs1.name(), instr_zfinx.rs2.name(), instr_zfinx.rs3.name(), instr_zfinx.rd.name(), instr_zfinx.imm), UVM_DEBUG); end else begin : EXTENSION_F - `DV_CHECK_FATAL($cast(instr_f, instr), "Cast to instr_f failed!"); + `DV_CHECK_FATAL($cast(instr_f, instr), $sformatf("Cast to instr_f failed for %s!", instr.instr_name.name()) ); randomize_fpr(instr_f, i); f_use_prev_rd_on_next_operands(.p_instr_f((use_prev_rd_on_next_operands) ? instr_f : null), .idx(i)); - if (instr_f.instr_name == FSW) begin: SPECIAL_HANDLING_FOR_STORE - wa_prevent_store_on_code_space(instr_f); + if (instr_f.instr_name inside {`FP_STORE_INSTR_LIST}) begin + // wa_prevent_store_on_code_space(instr_f); + store_instr_gpr_handling(instr); end - if (enable_special_operand_patterns) begin : OVERRIDE_OPERANDS_W_SPECIAL_PATTERNS + if (use_special_operand_patterns) rand_fp_special_operands(instr_f, i); - end instr_list.push_back(instr_f); `uvm_info(_header, $sformatf("\n>>>> instr_f[%s] >>>> \ \n>> has_rs1 | has_rs2 | has_rd | has_imm -> %0b , %0b , %0b , %0b \ @@ -277,26 +291,34 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; virtual function void print_stream_setting(); `uvm_info(_header, $sformatf(">>%s with base constraints \ \n>> num_of_instr_per_stream [%0d] \ - \n>> enable_special_operand_patterns [%0b] \ + \n>> use_special_operand_patterns [%0b] \ \n>> use_fp_only_for_directed_instr [%0b] \ \n>> use_no_repetitive_instr_per_stream [%0b] \ \n>> use_same_instr_per_stream [%0b] \ \n>> use_prev_rd_on_next_operands [%0b] \ \n>> more_weight_for_fdiv_fsqrt_gen [%0b] \ + \n>> include_load_store_base_sp [%0b] \ ", - get_name(), num_of_instr_per_stream, enable_special_operand_patterns, use_fp_only_for_directed_instr, + get_name(), num_of_instr_per_stream, use_special_operand_patterns, use_fp_only_for_directed_instr, use_no_repetitive_instr_per_stream, use_same_instr_per_stream, use_prev_rd_on_next_operands, - // more_weight_for_fdiv_fsqrt_gen, en_clr_fflags_af_instr - more_weight_for_fdiv_fsqrt_gen + more_weight_for_fdiv_fsqrt_gen, include_load_store_base_sp ), UVM_NONE); endfunction : print_stream_setting + // set reserved sp to have fix addr for store instrs + virtual function void set_reserved_sp_addr(); + if (include_load_store_base_sp) begin + `SET_GPR_VALUE(SP,32'h8000_0000); + end + endfunction: set_reserved_sp_addr + // clear csr fflags (by through fflags or fcsr) // condition: reg rs1 must be keep for csr clr purpose only throughout this stream bit clr_csr_option = $urandom_range(1); bit clr_csr_init_done = 0; // reduce overhead riscv_instr_name_t csr_name = INVALID_INSTR; logic [31:0] csr_rm = $urandom_range(0,4); + virtual function void clr_crs_fflags(riscv_reg_t rs1); riscv_reg_t i_rs1 = rs1; logic [31:0] csrrw_val = 0; @@ -309,8 +331,8 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; end if ($urandom_range(1)) directed_csr_access(.instr_name(csr_name), .rs1(i_rs1), .csr(12'h001)); // fflags else directed_csr_access(.instr_name(csr_name), .rs1(i_rs1), .csr(12'h003)); // fcsr - endfunction : clr_crs_fflags + // set dyamic fm // condition: this must execute before clr_crs_fflags virtual function void set_csr_fm(riscv_reg_t rs1); @@ -322,12 +344,13 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; // init all the gpr/fpr based on F/zfinx respectly prior directed stream // reset fpu fflag prior directed stream virtual function void rand_fp_val(output logic [31:0] val); - int option = $urandom_range(0,3); + int option = $urandom_range(0,4); void'(std::randomize(val) with { if (option == 0) {val[22:18] == 0; val[17:13] == 0; val[12:8] == 0; val[7:0] != 0;} if (option == 1) {val[22:18] == 0; val[17:13] == 0; val[12:8] != 0; val[7:0] == 0;} if (option == 2) {val[22:18] == 0; val[17:13] != 0; val[12:8] == 0; val[7:0] == 0;} if (option == 3) {val[22:18] != 0; val[17:13] == 0; val[12:8] == 0; val[7:0] == 0;} + // option == 4 is full rand }); endfunction : rand_fp_val virtual function void initialize_regs(); @@ -349,53 +372,71 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; `SET_FPR_VALUE(i_fpr,i_imm); end end - set_csr_fm(gp_scratch_reg); - clr_crs_fflags(gp_scratch_reg); // note: this must be the last in order + set_reserved_sp_addr(); + set_csr_fm(gp_reg_scratch); + clr_crs_fflags(gp_reg_scratch); // note: this must be the last in order endfunction : initialize_regs // for updating the arguments that use in get_rand_instr virtual function void update_current_instr_arg_list(int idx=0); + bit select_fp_instr, include_fpc, rand_status; + + rand_status = std::randomize(select_fp_instr) with {select_fp_instr dist {0:=1, 1:=1};}; + assert(rand_status); + rand_status = std::randomize(include_fpc) with {include_fpc dist {0:=3, 1:=1};}; // less weight on fpc + assert(rand_status); + + if (!use_same_instr_per_stream) include_instr.delete(); include_group.delete(); - include_group = new[1] ((is_zfinx) ? {RV32ZFINX} : {RV32F}); - if (!use_fp_only_for_directed_instr) begin : USE_MIXED_FP_N_OTHERS_INSTR - bit select_fp_instr, rand_status; - - exclude_instr = new[33] (`EXCLUDE_INSTR_LIST); - if (more_weight_for_fdiv_fsqrt_gen) begin - if ($urandom_range(1)) include_group = new[4] ({include_group, RV32I, RV32M, RV32C}); - else include_group = new[4] ({include_group, RV32I, RV32M, RV32X}); - end - else begin - // put more weight in generating fp instr in directed streams - rand_status = std::randomize(select_fp_instr) with {select_fp_instr dist {1:=2, 0:=1};}; - assert(rand_status); - if (!select_fp_instr) begin - if ($urandom_range(1)) include_group = new[3] ({RV32I, RV32M, RV32C}); - else include_group = new[3] ({RV32I, RV32M, RV32X}); - end + + if (is_zfinx) begin + include_group = new[1] ({RV32ZFINX}); + end else begin + if (include_fpc) include_group = new[2] ({RV32F, RV32FC}); + else include_group = new[1] ({RV32F}); + end + + if (use_fp_only_for_directed_instr) begin + select_fp_instr = 1; + end else begin : INSERT_MIXED_INSTR + exclude_instr = new[33] ({`EXCLUDE_INSTR_LIST}); + if (!select_fp_instr) begin : USE_OTHERS + include_group.delete(); + if ($urandom_range(1)) include_group = new[3] ({RV32I, RV32M, RV32C}); + else include_group = new[3] ({RV32I, RV32M, RV32X}); end + end + + if (more_weight_for_fdiv_fsqrt_gen) begin + if (select_fp_instr) // is fp + if ($urandom_range(1)) // 50% rate of getting fdiv/fsqrt + include_instr = new[1] ($urandom_range(1) ? {FDIV_S} : {FSQRT_S}); + end + if (!include_load_store_base_sp) begin + if (!(C_SWSP inside {exclude_instr})) exclude_instr = new[exclude_instr.size()+1] ({exclude_instr, C_SWSP}); + if (!(C_FSWSP inside {exclude_instr})) exclude_instr = new[exclude_instr.size()+1] ({exclude_instr, C_FSWSP}); + end + else begin : SP_RESERVED_FOR_LOAD_STORE_INSTRS_ONLY + if (!(C_ADDI4SPN inside {exclude_instr})) exclude_instr = new[exclude_instr.size()+1] ({exclude_instr, C_ADDI4SPN}); + if (!(C_ADDI16SP inside {exclude_instr})) exclude_instr = new[exclude_instr.size()+1] ({exclude_instr, C_ADDI16SP}); end + endfunction: update_current_instr_arg_list - // insert additonal instr if there is any prior directed instr + // placeholder to insert additonal instr if there is any prior directed instr virtual function void add_instr_prior_directed_instr(riscv_instr instr, int idx=0); endfunction : add_instr_prior_directed_instr virtual function void update_next_instr_arg_list(riscv_instr prev_instr=null, int idx=0); if (use_no_repetitive_instr_per_stream && prev_instr != null) begin - int size = exclude_instr.size(); - exclude_instr = new[size+1] (exclude_instr); - exclude_instr[size] = prev_instr.instr_name; + if (!(prev_instr.instr_name inside {exclude_instr})) + exclude_instr = new[exclude_instr.size()+1] ({exclude_instr, prev_instr.instr_name}); end if (use_same_instr_per_stream && prev_instr != null) begin + assert (use_fp_only_for_directed_instr && use_same_instr_per_stream); include_instr = new[1] ({prev_instr.instr_name}); end - if (more_weight_for_fdiv_fsqrt_gen) begin - // at least 50% of the total directed_instr should be either fdiv/fsqrt - if (idx%2 && !(prev_instr.instr_name inside {FDIV_S, FSQRT_S})) include_instr = new[1] ($urandom_range(1) ? {FDIV_S} : {FSQRT_S}); - else include_instr.delete(); - end endfunction: update_next_instr_arg_list function void randomize_gpr(riscv_instr instr, int idx=0); @@ -434,13 +475,15 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; rs1 != cfg.reserved_regs[i]; } } + if (has_imm) { + soft imm == local::imm; + } rm == local::rm; use_rounding_mode_from_instr == local::use_rounding_mode_from_instr; ) endfunction: randomize_gpr - // for randomizing gpr to be used in this instr function void randomize_gpr_zfinx(riscv_fp_in_x_regs_instr instr, int idx=0); instr.set_rand_mode(); `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, @@ -474,12 +517,14 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; rs1 != cfg.reserved_regs[i]; } } + if (has_imm) { + soft imm == local::imm; + } rm == local::rm; use_rounding_mode_from_instr == local::use_rounding_mode_from_instr; ) endfunction: randomize_gpr_zfinx - // for randomizing fpr to be used in this instr virtual function void randomize_fpr(riscv_floating_point_instr instr, int idx=0); instr.set_rand_mode(); `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, @@ -510,8 +555,8 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; !(rd inside {reserved_rd, cfg.reserved_regs, ZERO}); } } - if (instr_name inside {FLW, FSW}) { - imm == local::imm; + if (has_imm) { + soft imm == local::imm; } rm == local::rm; use_rounding_mode_from_instr == local::use_rounding_mode_from_instr; @@ -636,7 +681,7 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; operand_pattens_t m_operand_a_pattern, m_operand_b_pattern, m_operand_c_pattern; riscv_reg_t imm_rd; - void'(std::randomize(imm_rd) with {!(imm_rd inside {cfg.reserved_regs, reserved_rd, instr.rs1, instr.rs2, instr.rd, gp_scratch_reg, ZERO}); }); // for MANIPULATE_FPR_OPERANDS + void'(std::randomize(imm_rd) with {!(imm_rd inside {cfg.reserved_regs, reserved_rd, instr.rs1, instr.rs2, instr.rd, gp_reg_scratch, gp_reg_sp, ZERO}); }); // for MANIPULATE_FPR_OPERANDS m_operand_a = operand_a[idx]; m_operand_a_pattern = operand_a_pattern[idx]; m_operand_b = operand_b[idx]; m_operand_b_pattern = operand_b_pattern[idx]; @@ -676,7 +721,7 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; int idx=0); if (is_fp_instr) begin if (en_clr_fflags_af_instr) - clr_crs_fflags(gp_scratch_reg); + clr_crs_fflags(gp_reg_scratch); end endfunction: act_post_directed_instr @@ -710,8 +755,8 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; if ( (p_instr_zfinx != null && p_instr_f != null) || - (p_instr_zfinx != null && p_instr != null) || - (p_instr_f != null && p_instr != null) + (p_instr_zfinx != null && p_instr != null) || + (p_instr_f != null && p_instr != null) ) begin `uvm_fatal(_header, $sformatf("[f_use_prev_rd_on_next_operands] Invalid args combination")); end @@ -739,7 +784,7 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; end if ( (curr_has_r_flags[rand_idx] && p_instr_f != null) || - (curr_has_r_flags[rand_idx] && p_instr != null) + (curr_has_r_flags[rand_idx] && p_instr != null) ) begin unique case(rand_idx) 1: if (p_instr_f != null) p_instr_f.rs1 = prev_rd; else p_instr.rs1 = prev_rd; @@ -776,7 +821,7 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; end // PREV_HAS_FD if (curr_has_r_flags[0]) prev_rd = (p_instr_zfinx != null) ? p_instr_zfinx.rd : - ((p_instr_f != null) ? p_instr_f.rd : p_instr.rd); + ((p_instr_f != null) ? p_instr_f.rd : p_instr.rd); if (curr_has_f_flags[0]) prev_fd = p_instr_f.fd; prev_has_r_flags = curr_has_r_flags; @@ -788,7 +833,7 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; endfunction: f_use_prev_rd_on_next_operands - // workaround to prevent FSW from overriding onto the code space + // workaround to prevent store instruction to corrupt the code space (OBSOLETED BUT KEEP THE FUNCTION) virtual function void wa_prevent_store_on_code_space(riscv_instr instr, int idx=0); bit [7:0] wa_rand_imm = $urandom_range(1,255); @@ -799,15 +844,17 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; if (is_fp_instr) begin `DV_CHECK_FATAL($cast(_instr, instr), "Cast to _instr failed!"); end - if (instr.instr_name == C_SWSP) rd = SP; - else rd = (is_fp_instr) ? _instr.rs1 : instr.rs1; + if (instr.instr_name == C_SWSP || instr.instr_name == C_FSWSP) + rd = SP; + else + rd = (is_fp_instr) ? _instr.rs1 : instr.rs1; wa_instr = new riscv_instr::get_rand_instr(.include_instr({LUI})); override_instr( .instr (wa_instr), .rd (rd), .imm ({12'h0, wa_rand_imm, 12'h0}) // yyy_ww_xxx - ); + ); // +1 overhead instrucion prior store instr_list.push_back(wa_instr); instr_list[$].comment = {instr_list[$].comment, $sformatf(" [wa_prevent_store_on_code_space] ")}; @@ -863,7 +910,7 @@ class cv32e40p_fp_n_mixed_instr_more_fdiv_fsqrt_stream extends cv32e40p_fp_n_mix function void pre_randomize(); super.pre_randomize(); - more_weight_for_fdiv_fsqrt_gen = 1; + more_weight_for_fdiv_fsqrt_gen = 1; endfunction: pre_randomize endclass: cv32e40p_fp_n_mixed_instr_more_fdiv_fsqrt_stream @@ -876,20 +923,18 @@ class cv32e40p_fp_w_special_operands_instr_stream extends cv32e40p_float_zfinx_b `uvm_object_utils(cv32e40p_fp_w_special_operands_instr_stream) `uvm_object_new - constraint ovr_c_enable_special_operand_patterns { - enable_special_operand_patterns == 1; - } - function void pre_randomize(); super.pre_randomize(); - use_fp_only_for_directed_instr = 1; - // exclude FLW, FSW and FMV_W_X: no fp regs as operand and by refering to verif plan - exclude_instr = new[exclude_instr.size() + 2] ({exclude_instr, FLW, FSW}); + use_special_operand_patterns = 1; + use_fp_only_for_directed_instr = 1; + include_load_store_base_sp = 0; // exclude store instrs for this stream endfunction: pre_randomize // to define exclude list for this stream class virtual function void update_current_instr_arg_list(int idx=0); super.update_current_instr_arg_list(idx); + // exclude store instrs for this stream + exclude_instr = new[33+3] ({`EXCLUDE_INSTR_LIST, `FP_STORE_INSTR_LIST}); // note: it should test all rather just focus on specific instrs as per verifplan. ease for Imperas coverage analysis // if (!use_no_repetitive_instr_per_stream && !use_same_instr_per_stream) begin // exclude_instr = new[exclude_instr.size() + 12] ( @@ -917,13 +962,14 @@ class cv32e40p_fp_w_prev_rd_as_operand_instr_stream extends cv32e40p_float_zfinx use_prev_rd_on_next_operands = 1; use_fp_only_for_directed_instr = 0; en_clr_fflags_af_instr = 0; + include_load_store_base_sp = 0; // exclude store instrs for this stream endfunction: pre_randomize // to define exclude list for this stream class virtual function void update_current_instr_arg_list(int idx=0); super.update_current_instr_arg_list(idx); - // exclude FSW: rs1/offset need to prevent from overriding the code space; rs1 should not overriden by prev rd - exclude_instr = new[exclude_instr.size() + 1] ({exclude_instr, FSW}); + // exclude store instrs for this stream + exclude_instr = new[33+10+3] ({`EXCLUDE_INSTR_LIST, `STORE_INSTR_LIST, `FP_STORE_INSTR_LIST}); endfunction: update_current_instr_arg_list endclass: cv32e40p_fp_w_prev_rd_as_operand_instr_stream @@ -953,7 +999,7 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i constraint ovr_c_others { if (is_zfinx) {num_of_instr_per_stream == TOTAL_INSTR_ZFINX_TYPE;} - else {num_of_instr_per_stream == TOTAL_INSTR_F_TYPE;} + else {num_of_instr_per_stream == TOTAL_INSTR_F_TYPE+TOTAL_INSTR_FC_TYPE;} } function void pre_randomize(); @@ -961,7 +1007,6 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i // cycle through all possible mc instrs for selected directed fp instr per stream use_fp_only_for_directed_instr = 1; use_same_instr_per_stream = 1; - assert (use_fp_only_for_directed_instr && use_same_instr_per_stream); endfunction: pre_randomize virtual function void act_post_directed_instr( @@ -974,6 +1019,12 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i insert_nop_instr($urandom_range(1,2)); endfunction: act_post_directed_instr + virtual function void update_current_instr_arg_list(int idx=0); + super.update_current_instr_arg_list(idx); + if (is_zfinx) include_group = new[1] ({RV32ZFINX}); + else include_group = new[1] ({RV32F}); + endfunction: update_current_instr_arg_list + // stream implementation to insert mc fp instr virtual function void add_instr_prior_directed_instr(riscv_instr instr, int idx=0); @@ -981,11 +1032,11 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i riscv_fp_in_x_regs_instr mc_instr_zfinx; riscv_floating_point_instr mc_instr_f; - if (instr.group inside {RV32F, RV32ZFINX}) begin : BODY - + if (instr.group inside {RV32F, RV32FC, RV32ZFINX}) begin : BODY + mc_instr = new riscv_instr::get_rand_instr( .exclude_instr(mc_exclude_instr), - .include_group((is_zfinx) ? {RV32ZFINX} : {RV32F}) + .include_group((is_zfinx) ? {RV32ZFINX} : {RV32F, RV32FC}) ); update_next_mc_instr(mc_instr); @@ -995,18 +1046,30 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i update_mc_instr_latency(mc_instr_zfinx); instr_list.push_back(mc_instr_zfinx); end + else if (mc_instr.group == RV32FC) begin + randomize_gpr(mc_instr); + if (mc_instr.instr_name inside {`FP_STORE_INSTR_LIST}) begin + // wa_prevent_store_on_code_space(mc_instr); + store_instr_gpr_handling(mc_instr); + end + update_mc_instr_latency(mc_instr); + instr_list.push_back(mc_instr); + end else begin `DV_CHECK_FATAL($cast(mc_instr_f, mc_instr), "Cast to instr_f failed!"); randomize_fpr(mc_instr_f, idx); - if (mc_instr_f.instr_name inside {FSW, SB, SH, SW}) begin: SPECIAL_HANDLING_FOR_STORE - wa_prevent_store_on_code_space(mc_instr_f); + if (mc_instr_f.instr_name inside {`FP_STORE_INSTR_LIST}) begin: SPECIAL_HANDLING_FOR_STORE + // wa_prevent_store_on_code_space(mc_instr_f); + store_instr_gpr_handling(mc_instr_f); end update_mc_instr_latency(mc_instr_f); instr_list.push_back(mc_instr_f); end instr_list[$].comment = {instr_list[$].comment, $sformatf(" [add_instr_prior_directed_instr] ")}; - rand_fill_mc_latency_w_instrs( .instr_zfinx(mc_instr_zfinx), .instr_f(mc_instr_f) ); + rand_fill_mc_latency_w_instrs( + .instr(mc_instr), .instr_zfinx(mc_instr_zfinx), .instr_f(mc_instr_f) + ); end // BODY @@ -1015,7 +1078,7 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i // for cycle through all posible mc instr virtual function void update_next_mc_instr(riscv_instr prev_instr=null); int size = mc_exclude_instr.size(); - if (prev_instr != null) begin + if (prev_instr != null && !(prev_instr.instr_name inside {mc_exclude_instr})) begin mc_exclude_instr = new[size+1] (mc_exclude_instr); mc_exclude_instr[size] = prev_instr.instr_name; end @@ -1025,19 +1088,21 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i virtual function void update_mc_instr_latency(riscv_instr mc_instr=null); unique case(mc_instr.instr_name) - FLW, FSW: begin mc_instr_latency = 2; end - FMV_W_X, FMV_X_W: begin mc_instr_latency = 2; end - FMADD_S, FMSUB_S: begin mc_instr_latency = 1 + fpu_addmul_lat; end + FLW, FSW: begin mc_instr_latency = 1; end // table 12.1 + C_FLW, C_FSW: begin mc_instr_latency = 1; end + C_FLWSP, C_FSWSP: begin mc_instr_latency = 1; end + FMADD_S, FMSUB_S: begin mc_instr_latency = 1 + fpu_addmul_lat; end // table 12.1 FNMSUB_S, FNMADD_S: begin mc_instr_latency = 1 + fpu_addmul_lat; end FADD_S, FSUB_S: begin mc_instr_latency = 1 + fpu_addmul_lat; end FMUL_S: begin mc_instr_latency = 1 + fpu_addmul_lat; end FMIN_S, FMAX_S: begin mc_instr_latency = 1 + fpu_addmul_lat; end - FDIV_S, FSQRT_S: begin mc_instr_latency = $urandom_range(1,12); end - FSGNJ_S,FSGNJN_S, FSGNJX_S: begin mc_instr_latency = 1 + fpu_others_lat; end + FDIV_S, FSQRT_S: begin mc_instr_latency = $urandom_range(1,12); end // table 12.1 + FSGNJ_S,FSGNJN_S, FSGNJX_S: begin mc_instr_latency = 1 + fpu_others_lat; end // table 12.1 FCVT_W_S, FCVT_WU_S: begin mc_instr_latency = 1 + fpu_others_lat; end FEQ_S, FLT_S, FLE_S: begin mc_instr_latency = 1 + fpu_others_lat; end FCLASS_S: begin mc_instr_latency = 1 + fpu_others_lat; end FCVT_S_W,FCVT_S_WU: begin mc_instr_latency = 1 + fpu_others_lat; end + FMV_W_X, FMV_X_W: begin mc_instr_latency = 1 + fpu_others_lat; end endcase endfunction: update_mc_instr_latency @@ -1045,6 +1110,7 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i // to fill up mc latency period with random instr // to delay the directed_instr insertion with deterministic delay virtual function void rand_fill_mc_latency_w_instrs( + riscv_instr instr=null, riscv_fp_in_x_regs_instr instr_zfinx=null, riscv_floating_point_instr instr_f=null ); @@ -1054,6 +1120,7 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i int rand_mc_latency = $urandom_range(0,mc_instr_latency); int loop_cnt = 0; + assert(!(instr == null && instr_zfinx == null && instr_f == null)); assert(rand_mc_latency >= 0); while (!(loop_cnt == 100) && rand_mc_latency > 0) begin @@ -1081,12 +1148,18 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i if (!skip) begin // fillng_instr need to have no rd/rs dependency on fp instr so that pipeline can go through reserved_rd.delete(); - if (is_zfinx) begin + if (instr_zfinx != null) begin if (instr_zfinx.has_rs1) begin reserved_rd = new[reserved_rd.size() + 1] ({reserved_rd, instr_zfinx.rs1}); end if (instr_zfinx.has_rs2) begin reserved_rd = new[reserved_rd.size() + 1] ({reserved_rd, instr_zfinx.rs2}); end if (instr_zfinx.has_rs3) begin reserved_rd = new[reserved_rd.size() + 1] ({reserved_rd, instr_zfinx.rs3}); end if (instr_zfinx.has_rd) begin reserved_rd = new[reserved_rd.size() + 1] ({reserved_rd, instr_zfinx.rd}); end - end else begin + end + else if (instr != null) begin + if (instr.has_rs1) begin reserved_rd = new[reserved_rd.size() + 1] ({reserved_rd, instr.rs1}); end + if (instr.has_rs2) begin reserved_rd = new[reserved_rd.size() + 1] ({reserved_rd, instr.rs2}); end + if (instr.has_rd) begin reserved_rd = new[reserved_rd.size() + 1] ({reserved_rd, instr.rd}); end + end + else begin if (instr_f.has_rs1) begin reserved_rd = new[reserved_rd.size() + 1] ({reserved_rd, instr_f.rs1}); end if (instr_f.has_rs2) begin reserved_rd = new[reserved_rd.size() + 1] ({reserved_rd, instr_f.rs2}); end if (instr_f.has_rd) begin reserved_rd = new[reserved_rd.size() + 1] ({reserved_rd, instr_f.rd}); end @@ -1148,16 +1221,15 @@ class cv32e40p_fp_operand_forwarding_instr_stream extends cv32e40p_float_zfinx_b fp_cnt_percent_per_block != 0; fp_cnt_percent_per_block % 10 == 0; soft fp_first_instr_per_block dist {1 := 4, 0 := 1}; - // soft fp_cnt_percent_per_block dist {30 := 5, 50 := 3, 70 :=2}; - soft fp_cnt_percent_per_block dist {20 := 5, 30 := 3, 40 :=3}; + soft fp_cnt_percent_per_block dist {20 := 2, 30 := 5, 40 :=3, 50:=2}; soft shuffle_instr_per_block == 0; } constraint ovr_c_avail_gp_regs { foreach (avail_gp_regs[i]) { - avail_gp_regs[i].size() == XLEN - cfg.reserved_regs.size() - reserved_rd.size() - 2; // 2 for ZERO and gp_scratch_reg + avail_gp_regs[i].size() == XLEN - cfg.reserved_regs.size() - reserved_rd.size() - 3; // 3 are ZERO, gp_reg_scratch, gp_reg_sp foreach (avail_gp_regs[i][j]) { - !(avail_gp_regs[i][j] inside {ZERO, gp_scratch_reg}); + !(avail_gp_regs[i][j] inside {ZERO, gp_reg_scratch, gp_reg_sp}); } } } @@ -1166,7 +1238,8 @@ class cv32e40p_fp_operand_forwarding_instr_stream extends cv32e40p_float_zfinx_b super.pre_randomize(); use_fp_only_for_directed_instr = 0; num_of_instr_per_block = 10; - assert (num_of_instr_per_block != 0 && num_of_instr_per_block%10 == 0); + include_load_store_base_sp = 0; // exclude store instrs for this stream + assert (num_of_instr_per_block != 0 && num_of_instr_per_block%10 == 0); endfunction: pre_randomize virtual function void print_stream_setting(); @@ -1183,11 +1256,10 @@ class cv32e40p_fp_operand_forwarding_instr_stream extends cv32e40p_float_zfinx_b // to define exclude list for this stream class virtual function void update_current_instr_arg_list(int idx=0); - exclude_instr = new[33] (`EXCLUDE_INSTR_LIST); - // always exclude all store instr to prevent from overriding the code space; - exclude_instr = new[exclude_instr.size() + 4] ({exclude_instr, FSW, SB, SH, SW}); - // always exclude RV32C because it only uses 8 common gpr. We cover > 8 gpr here - exclude_group = new[1] ({RV32C}); + // exclude store instrs for this stream + exclude_instr = new[33+8+3] ({`EXCLUDE_INSTR_LIST, `STORE_INSTR_LIST, `FP_STORE_INSTR_LIST}); // fixme: need to have a specific to stress on all types of store operations with data forwarding + // always exclude RV32C because it only uses 8 common gpr/fpr. We cover more than 8 registers here + exclude_group = new[2] ({RV32C, RV32FC}); // if (instr_order_per_block[idx] == IS_FP) begin include_group = new[1] ((is_zfinx) ? {RV32ZFINX} : {RV32F}); @@ -1363,7 +1435,7 @@ class cv32e40p_fp_operand_forwarding_instr_stream extends cv32e40p_float_zfinx_b instr_list.push_back(i_instr_list[j]); instr_list[$].comment = {instr_list[$].comment, $sformatf(" Inserted %0s - blk_idx[%0d]", get_name(), j)}; end - clr_crs_fflags(gp_scratch_reg); + clr_crs_fflags(gp_reg_scratch); end // POST_PROCESS_BLOCK end // for GEN_N_MANIPULATE_INSTR diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib_defines.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib_defines.sv index ff44b9c34b..335a496058 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib_defines.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib_defines.sv @@ -23,19 +23,15 @@ constraint c_operand_``IDX``_pattern {\ soft operand_``IDX``_pattern.size() == num_of_instr_per_stream;\ foreach (operand_``IDX``_pattern[i]) {\ - if (enable_special_operand_patterns) {\ - soft operand_``IDX``_pattern[i] dist { IS_RAND := 6, \ - IS_Q_NAN := 4, IS_S_NAN := 4, \ - IS_POSITIVE_ZERO := 4, IS_NEGATIVE_ZERO := 4, \ - IS_POSITIVE_INFINITY := 4, IS_NEGATIVE_INFINITY := 4, \ - IS_POSITIVE_MAX := 4, IS_NEGATIVE_MAX := 4, \ - IS_POSITIVE_MIN := 4, IS_NEGATIVE_MIN := 4, \ - IS_POSITIVE_MIN_DIV2 := 4, IS_NEGATIVE_MIN_DIV2 := 4, \ - IS_POSITIVE_SUBNORMAL_MAX := 4, IS_NEGATIVE_SUBNORMAL_MAX := 4, \ - IS_POSITIVE_SUBNORMAL_MIN := 4, IS_NEGATIVE_SUBNORMAL_MIN := 4 };\ - } else {\ - soft operand_``IDX``_pattern[i] == IS_RAND;\ - }\ + soft operand_``IDX``_pattern[i] dist { IS_RAND := 6, \ + IS_Q_NAN := 4, IS_S_NAN := 4, \ + IS_POSITIVE_ZERO := 4, IS_NEGATIVE_ZERO := 4, \ + IS_POSITIVE_INFINITY := 4, IS_NEGATIVE_INFINITY := 4, \ + IS_POSITIVE_MAX := 4, IS_NEGATIVE_MAX := 4, \ + IS_POSITIVE_MIN := 4, IS_NEGATIVE_MIN := 4, \ + IS_POSITIVE_MIN_DIV2 := 4, IS_NEGATIVE_MIN_DIV2 := 4, \ + IS_POSITIVE_SUBNORMAL_MAX := 4, IS_NEGATIVE_SUBNORMAL_MAX := 4, \ + IS_POSITIVE_SUBNORMAL_MIN := 4, IS_NEGATIVE_SUBNORMAL_MIN := 4 };\ }\ } @@ -183,14 +179,20 @@ instr_list[$].comment = {instr_list[$].comment, $sformatf(`" [``OPERAND`` - %s - 32'h%8h] `", ``OPERAND``_pattern.name(), ``OPERAND``)};\ end - // 22 always exclude list within fp stream; 11 are related to hw-loop (total 33) - `define EXCLUDE_INSTR_LIST {JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, ECALL, EBREAK, \ - DRET, MRET, URET, SRET, WFI, C_EBREAK, C_BEQZ, C_BNEZ, C_J, C_JAL, \ - C_JR, C_JALR, \ - CV_START, CV_STARTI, CV_END, CV_ENDI, CV_COUNT, CV_COUNTI, CV_SETUP, CV_SETUPI, CV_ELW, CV_BEQIMM, CV_BNEIMM} + // 22 always exclude list within fp stream + 11 are related to hw-loop (total 33) + `define EXCLUDE_INSTR_LIST JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, ECALL, EBREAK, \ + DRET, MRET, URET, SRET, WFI, C_EBREAK, C_BEQZ, C_BNEZ, C_J, C_JAL, \ + C_JR, C_JALR, \ + CV_START, CV_STARTI, CV_END, CV_ENDI, CV_COUNT, CV_COUNTI, CV_SETUP, CV_SETUPI, CV_ELW, CV_BEQIMM, CV_BNEIMM + + // store instruction list + `define STORE_INSTR_LIST SB, SH, SW, C_SW, C_SWSP, CV_SB, CV_SH, CV_SW, C_FSW, C_FSWSP + `define FP_STORE_INSTR_LIST FSW, C_FSW, C_FSWSP + `define STORE_INSTR_W_SP_LIST C_SWSP, C_FSWSP // refer Table 6-1 user manual `define RV32I_INT_COMP_INSTR_LIST {ADD, ADDI, SUB, LUI, AUIPC, SLL, SLLI, SRL, SRLI, SRA, SRAI, \ XOR, XORI, OR, ORI, AND, ANDI} /* with deterministic 1 cycle defined */ `define RV32M_MULH_INSTR_LIST {MULH, MULHSU, MULHU} /* with deterministic 5 cycles defined */ + From 823dbed1b0f5a65fa4936e07c00a3771bea24732 Mon Sep 17 00:00:00 2001 From: bsm Date: Thu, 14 Sep 2023 15:55:10 +0800 Subject: [PATCH 07/27] Add fp operand forward streams that stress on load store instructions Signed-off-by: bsm --- .../instr_lib/cv32e40p_float_instr_lib.sv | 323 +++++++++++++++--- .../cv32e40p_float_instr_lib_defines.sv | 63 +++- .../corev-dv.yaml | 5 +- .../corev-dv.yaml | 3 +- 4 files changed, 341 insertions(+), 53 deletions(-) diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv index 64e2109bd2..998ea374f4 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv @@ -33,30 +33,6 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; localparam MAX_S_REG = 3; // rs/fs localparam TOTAL_D_AND_S_REG = MAX_D_REG + MAX_S_REG; - // typedef - start - typedef enum bit [4:0] { - IS_RAND = 0, - IS_POSITIVE_ZERO, - IS_NEGATIVE_ZERO, - IS_POSITIVE_INFINITY, - IS_NEGATIVE_INFINITY, - IS_POSITIVE_MAX, - IS_NEGATIVE_MAX, - IS_POSITIVE_MIN, - IS_NEGATIVE_MIN, - IS_POSITIVE_MIN_DIV2, - IS_NEGATIVE_MIN_DIV2, - IS_POSITIVE_SUBNORMAL_MAX, - IS_NEGATIVE_SUBNORMAL_MAX, - IS_POSITIVE_SUBNORMAL_MIN, - IS_NEGATIVE_SUBNORMAL_MIN, - IS_Q_NAN, - IS_S_NAN, - IS_FMV_RAND_RS1, - IS_FCVT_RAND_RS1 - } operand_pattens_t; - // typedef - end - `include "instr_lib/cv32e40p_float_instr_lib_defines.sv" // properties - start @@ -222,7 +198,7 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; ); is_fp_instr = (instr.group inside {RV32F, RV32ZFINX}); update_next_instr_arg_list(instr, i); - rand_var_for_inline_constraint(); + // rand_var_for_inline_constraint(); // fixme add_instr_prior_directed_instr(instr, i); // directed instr randomization based on extension @@ -440,6 +416,7 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; endfunction: update_next_instr_arg_list function void randomize_gpr(riscv_instr instr, int idx=0); + rand_var_for_inline_constraint(); instr.set_rand_mode(); `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, if (local::avail_gp_regs[local::idx].size() > 0) { @@ -485,6 +462,7 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; endfunction: randomize_gpr function void randomize_gpr_zfinx(riscv_fp_in_x_regs_instr instr, int idx=0); + rand_var_for_inline_constraint(); instr.set_rand_mode(); `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, if (local::avail_gp_regs[local::idx].size() > 0) { @@ -526,6 +504,7 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; endfunction: randomize_gpr_zfinx virtual function void randomize_fpr(riscv_floating_point_instr instr, int idx=0); + rand_var_for_inline_constraint(); instr.set_rand_mode(); `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, if (local::avail_fp_regs[local::idx].size() >0 ) { @@ -975,7 +954,8 @@ class cv32e40p_fp_w_prev_rd_as_operand_instr_stream extends cv32e40p_float_zfinx endclass: cv32e40p_fp_w_prev_rd_as_operand_instr_stream - // [optional] extended class that preceeded mc instr prior directed fp instr + // + // extended class that preceeded mc instr prior directed fp instr // note: this is additional class that use to improve the coverage defined in verif plan // use if cv32e40p_fp_n_mixed_instr_stream is not able to achive certain % of coverage class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_instr_stream; @@ -1181,28 +1161,17 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i endclass: cv32e40p_constraint_mc_fp_instr_stream -// [optional] extended class to stress test on operand forwarding scenario -// info: https://en.wikipedia.org/wiki/Operand_forwarding -// note: Similar to cv32e40p_fp_w_prev_rd_as_operand_instr_stream but is more focus compare to it. -// Forwarding paths and write-back logic are shared for the integer and floating point operations -// and are not replicated. -class cv32e40p_fp_operand_forwarding_instr_stream extends cv32e40p_float_zfinx_base_instr_stream; - - `uvm_object_utils(cv32e40p_fp_operand_forwarding_instr_stream) + // + // extended class to stress on operands forwarding + // info: https://en.wikipedia.org/wiki/Operand_forwarding + // note: Similar to cv32e40p_fp_w_prev_rd_as_operand_instr_stream but is more focus compare to it. + // Forwarding paths and write-back logic are shared for the integer and floating point operations + // and are not replicated. +class cv32e40p_fp_op_fwd_instr_stream extends cv32e40p_float_zfinx_base_instr_stream; + + `uvm_object_utils(cv32e40p_fp_op_fwd_instr_stream) `uvm_object_new - typedef enum bit [1:0] { - PREV_RD_IS_CURR_RD = 0, - PREV_RD_IS_CURR_RS, - PREV_RS_IS_CURR_RD, - PREV_RS_IS_CURR_RS /* this is not cover here */ - } forward_pattern_t; - - typedef enum bit { - IS_NON_FP = 0, - IS_FP - } instr_type_t; - int unsigned num_of_instr_per_block; int unsigned num_of_fp_instr_per_block; riscv_instr i_instr_list[$]; @@ -1348,7 +1317,7 @@ class cv32e40p_fp_operand_forwarding_instr_stream extends cv32e40p_float_zfinx_b prev_instr_has_gpr = instr_has_gpr; endfunction: act_post_directed_instr - // override becase this testcase need overall special handling + // override because this testcase need special handling function void post_randomize(); print_stream_setting(); @@ -1442,6 +1411,264 @@ class cv32e40p_fp_operand_forwarding_instr_stream extends cv32e40p_float_zfinx_b endfunction: post_randomize -endclass: cv32e40p_fp_operand_forwarding_instr_stream +endclass: cv32e40p_fp_op_fwd_instr_stream + + + // + // extended class to stress on operands forwarding mixed with various load store instrs +class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_base_instr_stream; + + load_store_opt_t load_store_option=NULL; + bit use_load_store_w_sp_only; + bit use_compress_load_store_only; + int unsigned num_of_load_store_instr; + + rand int unsigned stream_loops; + + `uvm_object_utils(cv32e40p_fp_op_fwd_instr_w_loadstore_stream) + `uvm_object_new + + constraint c_stream_loops { + soft stream_loops inside {[6:10]}; + num_of_instr_per_stream == stream_loops; + solve stream_loops before num_of_instr_per_stream; + } + + function void pre_randomize(); + super.pre_randomize(); + use_fp_only_for_directed_instr = 0; + en_clr_fflags_af_instr = 1; + include_load_store_base_sp = 0; // do not reserved SP + endfunction: pre_randomize + + virtual function void reset_rand_instr_entry(); + include_instr.delete(); exclude_instr.delete(); + include_category.delete(); exclude_category.delete(); + include_group.delete(); exclude_group.delete(); + endfunction : reset_rand_instr_entry + + virtual function void update_current_instr_arg_list(int idx=0); + endfunction: update_current_instr_arg_list + + virtual function void manipulate_preceeded_fp( + riscv_fp_in_x_regs_instr p_instr_zfinx=null, + riscv_floating_point_instr p_instr_f=null + ); + riscv_reg_t i_rd = (is_zfinx) ? p_instr_zfinx.rd : p_instr_f.rd ; + riscv_reg_t i_rs1 = (is_zfinx) ? p_instr_zfinx.rs1 : p_instr_f.rs1 ; + riscv_reg_t i_rs2 = (is_zfinx) ? p_instr_zfinx.rs2 : ZERO ; + riscv_reg_t i_rs3 = (is_zfinx) ? p_instr_zfinx.rs3 : ZERO ; + logic [31:0] v_rd = $urandom_range(0, 32'hFFFF_FFFF); + + riscv_fpr_t i_fs1 = (is_zfinx) ? FT0 : p_instr_f.fs1; + + assert(!(p_instr_zfinx == null && p_instr_f == null)); + `SET_GPR_VALUE(i_rd, v_rd); + + if (p_instr_zfinx != null) begin + unique case (p_instr_zfinx.instr_name) + FADD_S, FSUB_S : begin `SET_GPR_VALUE(i_rs1, F_NEG_ZERO); `SET_GPR_VALUE(i_rs2, ALL_ZERO); end // rd = rs1 +/- rs2 + FMADD_S, FMSUB_S : begin `SET_GPR_VALUE(i_rs1, F_POS_ONE); `SET_GPR_VALUE(i_rs2, F_NEG_ZERO); `SET_GPR_VALUE(i_rs3, ALL_ZERO); end // rd = rs1*rs2 +/- rs3 + FNMADD_S, FNMSUB_S : begin `SET_GPR_VALUE(i_rs1, F_NEG_ONE); `SET_GPR_VALUE(i_rs2, F_NEG_ZERO); `SET_GPR_VALUE(i_rs3, ALL_ZERO); end // rd = -rs1*rs2 -/+ rs3 + FMUL_S, FDIV_S : begin `SET_GPR_VALUE(i_rs1, F_NEG_ZERO_DIV2); `SET_GPR_VALUE(i_rs2, F_POS_ONE); end // rd = rs1 *// rs2 + FSQRT_S : begin `SET_GPR_VALUE(i_rs1, F_POS_FOUR); end // rd = sqrt(rs1) + FMAX_S : begin `SET_GPR_VALUE(i_rs1, F_POS_FOUR); `SET_GPR_VALUE(i_rs2, ALL_ZERO); end // rd = (rs1 > rs2) ? rs1 : rs2; + FMIN_S : begin `SET_GPR_VALUE(i_rs1, F_NEG_ZERO_DIV2); `SET_GPR_VALUE(i_rs2, F_NEG_ZERO); end // rd = (rs1 < rs2) ? rs1 : rs2; + FSGNJ_S, FSGNJX_S : begin `SET_GPR_VALUE(i_rs1, ALL_ZERO); `SET_GPR_VALUE(i_rs2, F_NEG_ZERO); end // rd = sign(rs2),rs1[30:0] / rd = sign(rs1 xor rs2), rs1[30:0] + FSGNJN_S : begin `SET_GPR_VALUE(i_rs1, ALL_ZERO); `SET_GPR_VALUE(i_rs2, F_POS_FOUR); end // rd = sign(!rs2),rs1[30:0] + FCVT_S_W, FCVT_S_WU : begin `SET_GPR_VALUE(i_rs1, D_POS_TWO); end // rd(float) = rs1(int) + FCVT_W_S, FCVT_WU_S : begin `SET_GPR_VALUE(i_rs1, F_POS_VAL1); end // rd(int) = rs1(floating) + endcase + end + else begin + unique case (p_instr_f.instr_name) + FCVT_W_S, FCVT_WU_S : begin `SET_FPR_VALUE(i_fs1, F_POS_VAL1); end // rd(int) = fs1 + FMV_X_W : begin `SET_FPR_VALUE(i_fs1, F_NEG_ZERO); end // rd(int) <- fs1 + endcase + end + + endfunction : manipulate_preceeded_fp + + // override because this testcase need special handling + function void post_randomize(); + + print_stream_setting(); + initialize_regs(); + + for (int i = 0; i < stream_loops; i++) begin + riscv_instr instr, instr2, instr3; + riscv_fp_in_x_regs_instr instr_zfinx, instr_zfinx2, instr_zfinx3; + riscv_floating_point_instr instr_f, instr_f2, instr_f3; + cv32e40p_riscv_compressed_instr instr_fc; + int unsigned cnt, cnt_limit=100; + riscv_reg_t last_store_rs1=ZERO; + + // rand available options + use_compress_load_store_only = $urandom_range(1); + use_load_store_w_sp_only = (use_compress_load_store_only) ? $urandom_range(1) : 0; + load_store_option = load_store_opt_t'($urandom_range(2)); + num_of_load_store_instr = $urandom_range(4,8); + + if (use_compress_load_store_only) begin + void'(std::randomize(avail_gp_regs[i]) with { + avail_gp_regs[i].size() == 8; + unique{avail_gp_regs[i]}; + foreach (avail_gp_regs[i][j]) { + avail_gp_regs[i][j] inside {[S0:A5]}; + } + }); + void'(std::randomize(avail_fp_regs[i]) with { + avail_fp_regs[i].size() == 8; + unique{avail_fp_regs[i]}; + foreach (avail_fp_regs[i][j]) { + avail_fp_regs[i][j] inside {[FS0:FA5]}; + } + }); + end + + + // generate preceeded fp - start + reset_rand_instr_entry(); + exclude_instr = new[4] ({FEQ_S, FLT_S, FLE_S, FCLASS_S}); + exclude_category = new[2] ({LOAD, STORE}); + if (is_zfinx) include_group = new[1] ({RV32ZFINX}); + else include_group = new[1] ({RV32F}); + cnt = 0; + do begin + if (cnt == cnt_limit) begin + `uvm_fatal(_header, $sformatf("[generate preceeded fp] cnt_limit reached")); + end + instr = new riscv_instr::get_rand_instr( + .exclude_instr(exclude_instr), + .exclude_category(exclude_category), + .include_group(include_group) + ); + cnt++; + end + while (!instr.has_rd); + if (is_zfinx) begin + `DV_CHECK_FATAL($cast(instr_zfinx, instr), $sformatf("Cast to instr_zfinx failed for %s!", instr.instr_name.name()) ); + randomize_gpr_zfinx(instr_zfinx, i); + if (use_load_store_w_sp_only) instr_zfinx.rd = SP; + manipulate_preceeded_fp(.p_instr_zfinx(instr_zfinx)); + instr_list.push_back(instr_zfinx); + end + else begin + `DV_CHECK_FATAL($cast(instr_f, instr), $sformatf("Cast to instr_f failed for %s!", instr.instr_name.name()) ); + randomize_fpr(instr_f, i); + if (use_load_store_w_sp_only) instr_f.rd = SP; + manipulate_preceeded_fp(.p_instr_f(instr_f)); + instr_list.push_back(instr_f); + end + instr_list[$].comment = {instr_list[$].comment, $sformatf("Inserted %s - [generate preceeded fp]", get_name())}; + // generate preceeded fp - end + + + // generate load-store instrs - start + for (int j=0; j +num_of_sub_program=0 +test_override_riscv_instr_stream=1 +no_branch_jump=1 - +directed_instr_0=cv32e40p_fp_w_prev_rd_as_operand_instr_stream,5 - +directed_instr_1=cv32e40p_fp_operand_forwarding_instr_stream,3 + +directed_instr_0=cv32e40p_fp_w_prev_rd_as_operand_instr_stream,2 + +directed_instr_1=cv32e40p_fp_op_fwd_instr_stream,4 + +directed_instr_2=cv32e40p_fp_op_fwd_instr_w_loadstore_stream,4 diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_sanity_test/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_sanity_test/corev-dv.yaml index 68d47a3b93..9ad6bd81c7 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_sanity_test/corev-dv.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_sanity_test/corev-dv.yaml @@ -31,7 +31,8 @@ plusargs: > +directed_instr_3=cv32e40p_fp_w_special_operands_instr_stream,1 +directed_instr_4=cv32e40p_fp_w_prev_rd_as_operand_instr_stream,1 +directed_instr_5=cv32e40p_constraint_mc_fp_instr_stream,1 - +directed_instr_6=cv32e40p_fp_operand_forwarding_instr_stream,1 + +directed_instr_6=cv32e40p_fp_op_fwd_instr_stream,1 + +directed_instr_7=cv32e40p_fp_op_fwd_instr_w_loadstore_stream,1 # note: # 1) example yaml template for fp test with f_extension From 151d8bb83bc228b0fc12af5ea3573fd0467ca218 Mon Sep 17 00:00:00 2001 From: bsm Date: Thu, 14 Sep 2023 16:00:01 +0800 Subject: [PATCH 08/27] Resolve fixme Signed-off-by: bsm --- cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv index 998ea374f4..e03c3d1ba6 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv @@ -198,7 +198,6 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; ); is_fp_instr = (instr.group inside {RV32F, RV32ZFINX}); update_next_instr_arg_list(instr, i); - // rand_var_for_inline_constraint(); // fixme add_instr_prior_directed_instr(instr, i); // directed instr randomization based on extension @@ -1226,7 +1225,7 @@ class cv32e40p_fp_op_fwd_instr_stream extends cv32e40p_float_zfinx_base_instr_st // to define exclude list for this stream class virtual function void update_current_instr_arg_list(int idx=0); // exclude store instrs for this stream - exclude_instr = new[33+8+3] ({`EXCLUDE_INSTR_LIST, `STORE_INSTR_LIST, `FP_STORE_INSTR_LIST}); // fixme: need to have a specific to stress on all types of store operations with data forwarding + exclude_instr = new[33+8+3] ({`EXCLUDE_INSTR_LIST, `STORE_INSTR_LIST, `FP_STORE_INSTR_LIST}); // always exclude RV32C because it only uses 8 common gpr/fpr. We cover more than 8 registers here exclude_group = new[2] ({RV32C, RV32FC}); // From ac9e5b4c5192413f55acc055d4981e920236a2b8 Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Thu, 14 Sep 2023 15:29:39 +0200 Subject: [PATCH 09/27] test updated to match latest cv32e40p specification --- .../pulp_post_increment_load_store.S | 241 +++++++++--------- 1 file changed, 120 insertions(+), 121 deletions(-) diff --git a/cv32e40p/tests/programs/custom/pulp_post_increment_load_store/pulp_post_increment_load_store.S b/cv32e40p/tests/programs/custom/pulp_post_increment_load_store/pulp_post_increment_load_store.S index 697d779dd6..5d3092bcce 100644 --- a/cv32e40p/tests/programs/custom/pulp_post_increment_load_store/pulp_post_increment_load_store.S +++ b/cv32e40p/tests/programs/custom/pulp_post_increment_load_store/pulp_post_increment_load_store.S @@ -44,14 +44,14 @@ main: li x31, 0x5912efde li x4, 0x40001104 #tests1-6 test the cv.lb instruction (immediate offset). values loaded in and compared to are expected output values -#cv.lb instruction is of format "cv.lb rD, Imm(rs1!)". rD is loaded with the sign extended value at Mem8(rs1), then +#cv.lb instruction is of format "cv.lb rD, (rs1), Imm". rD is loaded with the sign extended value at Mem8(rs1), then #rs1 is incremented by the value of Imm. Imm has a max size of 12 bits li x20, 0x00120000 li x21, 0x00120000 test1: li x17, 0x7c64e787 sw x17, 0(x20) - cv.lb x18, 0x8(x20!) + cv.lb x18, (x20), 0x8 li x19, 0xffffff87 beq x18, x19, check1 c.addi x15, 0x1 @@ -62,7 +62,7 @@ check1: test2: li x17, 0xe4ea7b58 sw x17, 0(x20) - cv.lb x18, 0x5(x20!) + cv.lb x18, (x20), 0x5 li x19, 0x00000058 beq x18, x19, check2 c.addi x15, 0x1 @@ -73,7 +73,7 @@ check2: test3: li x17, 0x366ff377 sw x17, 0(x20) - cv.lb x18, 0xd(x20!) + cv.lb x18, (x20), 0xd li x19, 0x00000077 beq x18, x19, check3 c.addi x15, 0x1 @@ -84,7 +84,7 @@ check3: test4: li x17, 0x17c7fa9d sw x17, 0(x20) - cv.lb x18, 0xbc(x20!) + cv.lb x18, (x20), 0xbc li x19, 0xffffff9d beq x18, x19, check4 c.addi x15, 0x1 @@ -95,7 +95,7 @@ check4: test5: li x17, 0x1b450b7b sw x17, 0(x20) - cv.lb x18, 0x642(x20!) + cv.lb x18, (x20), 0x642 li x19, 0x0000007b beq x18, x19, check5 c.addi x15, 0x1 @@ -106,7 +106,7 @@ check5: test6: li x17, 0x1b2f8686 sw x17, 0(x20) - cv.lb x18, 0x4c(x20!) + cv.lb x18, (x20), 0x4c li x19, 0xffffff86 beq x18, x19, check6 c.addi x15, 0x1 @@ -115,7 +115,7 @@ check6: beq x20, x21, test7 c.addi x16, 0x1 #tests7-12 test the cv.lbu instruction (immediate offset). values loaded in and compared to are expected output values -#cv.lbu instruction is of format "cv.lbu rD, Imm(rs1!)". rD is loaded with the Z extended value at Mem8(rs1), then +#cv.lbu instruction is of format "cv.lbu rD, (rs1), Imm". rD is loaded with the Z extended value at Mem8(rs1), then #rs1 is incremented by the value of Imm. Imm has a max size of 12 bits test7: li x20, 0x00120000 @@ -123,7 +123,7 @@ test7: li x17, 0x284def7c sw x17, 0(x20) nop - cv.lbu x18, 0xa8(x20!) + cv.lbu x18, (x20), 0xa8 li x19, 0x00007c beq x18, x19, check7 c.addi x15, 0x1 @@ -134,7 +134,7 @@ check7: test8: li x17, 0x1c133aa7 sw x17, 0(x20) - cv.lbu x18, 0x776(x20!) + cv.lbu x18, (x20), 0x776 li x19, 0x000000a7 beq x18, x19, check8 c.addi x15, 0x1 @@ -145,7 +145,7 @@ check8: test9: li x17, 0xc30dc4ae sw x17, 0(x20) - cv.lbu x18, 0xb4(x20!) + cv.lbu x18, (x20), 0xb4 li x19, 0x000000ae beq x18, x19, check9 c.addi x15, 0x1 @@ -156,7 +156,7 @@ check9: test10: li x17, 0xd58dcbf8 sw x17, 0(x20) - cv.lbu x18, 0x12(x20!) + cv.lbu x18, (x20), 0x12 li x19, 0x000000f8 beq x18, x19, check10 c.addi x15, 0x1 @@ -167,7 +167,7 @@ check10: test11: li x17, 0x0a326929 sw x17, 0(x20) - cv.lbu x18, 0x40(x20!) + cv.lbu x18, (x20), 0x40 li x19, 0x00000029 beq x18, x19, check11 c.addi x15, 0x1 @@ -178,7 +178,7 @@ check11: test12: li x17, 0xaa36097f sw x17, 0(x20) - cv.lbu x18, 0x52(x20!) + cv.lbu x18, (x20), 0x52 li x19, 0x0000007f beq x18, x19, check12 c.addi x15, 0x1 @@ -187,14 +187,14 @@ check12: beq x20, x21, test13 c.addi x16, 0x1 #tests13-18 test the cv.lh instruction (immediate offset). values loaded in and compared to are expected output values -#cv.lh instruction is of format "cv.lh rD, Imm(rs1!)". rD is loaded with the sign extended value at Mem16(rs1), then +#cv.lh instruction is of format "cv.lh rD, (rs1), Imm". rD is loaded with the sign extended value at Mem16(rs1), then #rs1 is incremented by the value of Imm. Imm has a max size of 12 bits test13: li x20, 0x00120000 li x21, 0x00120000 li x17, 0x0eb518be sw x17, 0(x20) - cv.lh x18, 0xc8(x20!) + cv.lh x18, (x20), 0xc8 li x19, 0x000018be beq x18, x19, check13 c.addi x15, 0x1 @@ -205,7 +205,7 @@ check13: test14: li x17, 0xae82beec sw x17, 0(x20) - cv.lh x18, 0x224(x20!) + cv.lh x18, (x20), 0x224 li x19, 0xffffbeec beq x18, x19, check14 c.addi x15, 0x1 @@ -216,7 +216,7 @@ check14: test15: li x17, 0x872ff921 sw x17, 0(x20) - cv.lh x18, 0xe0(x20!) + cv.lh x18, (x20), 0xe0 li x19, 0xfffff921 beq x18, x19, check15 c.addi x15, 0x1 @@ -227,7 +227,7 @@ check15: test16: li x17, 0x6af22644 sw x17, 0(x20) - cv.lh x18, 0x424(x20!) + cv.lh x18, (x20), 0x424 li x19, 0x00002644 beq x18, x19, check16 c.addi x15, 0x1 @@ -238,7 +238,7 @@ check16: test17: li x17, 0xaab13adb sw x17, 0(x20) - cv.lh x18, 0x86(x20!) + cv.lh x18, (x20), 0x86 li x19, 0x00003adb beq x18, x19, check17 c.addi x15, 0x1 @@ -249,7 +249,7 @@ check17: test18: li x17, 0x5a5a1ece sw x17, 0(x20) - cv.lh x18, 0x6fc(x20!) + cv.lh x18, (x20), 0x6fc li x19, 0x00001ece beq x18, x19, check18 c.addi x15, 0x1 @@ -258,7 +258,7 @@ check18: beq x20, x21, test19 c.addi x16, 0x1 #tests19-24 test the cv.lhu instruction (immediate offset). values loaded in and compared to are expected output values -#cv.lhu instruction is of format "cv.lhu rD, Imm(rs1!)". rD is loaded with the Z extended value at Mem16(rs1), then +#cv.lhu instruction is of format "cv.lhu rD, (rs1), Imm". rD is loaded with the Z extended value at Mem16(rs1), then #rs1 is incremented by the value of Imm. Imm has a max size of 12 bits test19: li x20, 0x00120000 @@ -266,7 +266,7 @@ test19: li x17, 0x1e9afd85 sw x17, 0(x20) nop - cv.lhu x18, 0x482(x20!) + cv.lhu x18, (x20), 0x482 li x19, 0x0000fd85 beq x18, x19, check19 c.addi x15, 0x1 @@ -277,7 +277,7 @@ check19: test20: li x17, 0xc78ece79 sw x17, 0(x20) - cv.lhu x18, 0xbd(x20!) + cv.lhu x18, (x20), 0xbd li x19, 0x0000ce79 beq x18, x19, check20 c.addi x15, 0x1 @@ -288,7 +288,7 @@ check20: test21: li x17, 0xeef54369 sw x17, 0(x20) - cv.lhu x18, 0x2d2(x20!) + cv.lhu x18, (x20), 0x2d2 li x19, 0x00004369 beq x18, x19, check21 c.addi x15, 0x1 @@ -299,7 +299,7 @@ check21: test22: li x17, 0xa9f93ae3 sw x17, 0(x20) - cv.lhu x18, 0xb(x20!) + cv.lhu x18, (x20), 0xb li x19, 0x00003ae3 beq x18, x19, check22 c.addi x15, 0x1 @@ -310,7 +310,7 @@ check22: test23: li x17, 0xee24c6e4 sw x17, 0(x20) - cv.lhu x18, 0xee(x20!) + cv.lhu x18, (x20), 0xee li x19, 0x0000c6e4 beq x18, x19, check23 c.addi x15, 0x1 @@ -321,7 +321,7 @@ check23: test24: li x17, 0xdd8f738b sw x17, 0(x20) - cv.lhu x18, 0x3(x20!) + cv.lhu x18, (x20), 0x3 li x19, 0x0000738b beq x18, x19, check24 c.addi x15, 0x1 @@ -330,7 +330,7 @@ check24: beq x20, x21, test25 c.addi x16, 0x1 #tests25-30 test the cv.lw instruction (immediate offset). values loaded in and compared to are expected output values -#cv.lw instruction is of format "cv.lw rD, Imm(rs1!)". rD is loaded with the value at Mem(rs1), then +#cv.lw instruction is of format "cv.lw rD, (rs1), Imm". rD is loaded with the value at Mem(rs1), then #rs1 is incremented by the value of Imm. Imm has a max size of 12 bits test25: li x20, 0x00120000 @@ -338,7 +338,7 @@ test25: li x17, 0xbe54b277 sw x17, 0(x20) nop - cv.lw x18, 0x5(x20!) + cv.lw x18, (x20), 0x5 li x19, 0xbe54b277 beq x18, x19, check25 c.addi x15, 0x1 @@ -349,7 +349,7 @@ check25: test26: li x17, 0xdef7980c sw x17, 0(x20) - cv.lw x18, 0x5cf(x20!) + cv.lw x18, (x20), 0x5cf li x19, 0xdef7980c beq x18, x19, check26 c.addi x15, 0x1 @@ -360,7 +360,7 @@ check26: test27: li x17, 0x1021f6d2 sw x17, 0(x20) - cv.lw x18, 0x133(x20!) + cv.lw x18, (x20), 0x133 li x19, 0x1021f6d2 beq x18, x19, check27 c.addi x15, 0x1 @@ -371,7 +371,7 @@ check27: test28: li x17, 0x683e7019 sw x17, 0(x20) - cv.lw x18, 0xf8(x20!) + cv.lw x18, (x20), 0xf8 li x19, 0x683e7019 beq x18, x19, check28 c.addi x15, 0x1 @@ -382,7 +382,7 @@ check28: test29: li x17, 0xe4f76ef9 sw x17, 0(x20) - cv.lw x18, 0x6(x20!) + cv.lw x18, (x20), 0x6 li x19, 0xe4f76ef9 beq x18, x19, check29 c.addi x15, 0x1 @@ -393,7 +393,7 @@ check29: test30: li x17, 0xd1337559 sw x17, 0(x20) - cv.lw x18, 0xd5(x20!) + cv.lw x18, (x20), 0xd5 li x19, 0xd1337559 beq x18, x19, check30 c.addi x15, 0x1 @@ -402,7 +402,7 @@ check30: beq x20, x21, test31 c.addi x16, 0x1 #tests31-36 test the cv.lb instruction (register offset). values loaded in and compared to are expected output values -#cv.lb instruction is of format "cv.lb rD, rs2(rs1!)". rD is loaded with the sign extended value at Mem8(rs1), then +#cv.lb instruction is of format "cv.lb rD, (rs1), rs2". rD is loaded with the sign extended value at Mem8(rs1), then #rs1 is incremented by the value of rs2 test31: li x20, 0x00120000 @@ -410,7 +410,7 @@ test31: li x17, 0x7c64e787 li x22, 0x8 sw x17, 0(x20) - cv.lb x18, x22(x20!) + cv.lb x18, (x20), x22 li x19, 0xffffff87 beq x18, x19, check31 c.addi x15, 0x1 @@ -422,7 +422,7 @@ test32: li x17, 0xe4ea7b58 li x22, 0x5 sw x17, 0(x20) - cv.lb x18, x22(x20!) + cv.lb x18, (x20), x22 li x19, 0x00000058 beq x18, x19, check32 c.addi x15, 0x1 @@ -434,7 +434,7 @@ test33: li x17, 0x366ff377 li x22, 0xd sw x17, 0(x20) - cv.lb x18, x22(x20!) + cv.lb x18, (x20), x22 li x19, 0x00000077 beq x18, x19, check33 c.addi x15, 0x1 @@ -446,7 +446,7 @@ test34: li x17, 0x17c7fa9d li x22, 0xbc sw x17, 0(x20) - cv.lb x18, x22(x20!) + cv.lb x18, (x20), x22 li x19, 0xffffff9d beq x18, x19, check34 c.addi x15, 0x1 @@ -458,7 +458,7 @@ test35: li x17, 0x1b450b7b li x22, 0x642 sw x17, 0(x20) - cv.lb x18, x22(x20!) + cv.lb x18, (x20), x22 li x19, 0x0000007b beq x18, x19, check35 c.addi x15, 0x1 @@ -470,7 +470,7 @@ test36: li x17, 0x1b2f8686 li x22, 0x4c sw x17, 0(x20) - cv.lb x18, x22(x20!) + cv.lb x18, (x20), x22 li x19, 0xffffff86 beq x18, x19, check36 c.addi x15, 0x1 @@ -479,7 +479,7 @@ check36: beq x20, x21, test37 c.addi x16, 0x1 #tests37-42 test the cv.lbu instruction (register offset). values loaded in and compared to are expected output values -#cv.lbu instruction is of format "cv.lbu rD, rs2(rs1!)". rD is loaded with the Z extended value at Mem8(rs1), then +#cv.lbu instruction is of format "cv.lbu rD, (rs1), rs2". rD is loaded with the Z extended value at Mem8(rs1), then #rs1 is incremented by the value of rs2. test37: li x20, 0x00120000 @@ -488,7 +488,7 @@ test37: li x22, 0xa8 sw x17, 0(x20) nop - cv.lbu x18, x22(x20!) + cv.lbu x18, (x20), x22 li x19, 0x00007c beq x18, x19, check37 c.addi x15, 0x1 @@ -500,7 +500,7 @@ test38: li x17, 0x1c133aa7 li x22, 0x776 sw x17, 0(x20) - cv.lbu x18, x22(x20!) + cv.lbu x18, (x20), x22 li x19, 0x000000a7 beq x18, x19, check38 c.addi x15, 0x1 @@ -512,7 +512,7 @@ test39: li x17, 0xc30dc4ae li x22, 0xb4 sw x17, 0(x20) - cv.lbu x18,x22(x20!) + cv.lbu x18,(x20), x22 li x19, 0x000000ae beq x18, x19, check39 c.addi x15, 0x1 @@ -524,7 +524,7 @@ test40: li x17, 0xd58dcbf8 li x22, 0x12 sw x17, 0(x20) - cv.lbu x18, x22(x20!) + cv.lbu x18, (x20), x22 li x19, 0x000000f8 beq x18, x19, check40 c.addi x15, 0x1 @@ -536,7 +536,7 @@ test41: li x17, 0x0a326929 li x22, 0x40 sw x17, 0(x20) - cv.lbu x18, x22(x20!) + cv.lbu x18, (x20), x22 li x19, 0x00000029 beq x18, x19, check41 c.addi x15, 0x1 @@ -548,7 +548,7 @@ test42: li x17, 0xaa36097f li x22, 0x52 sw x17, 0(x20) - cv.lbu x18, x22(x20!) + cv.lbu x18, (x20), x22 li x19, 0x0000007f beq x18, x19, check42 c.addi x15, 0x1 @@ -557,7 +557,7 @@ check42: beq x20, x21, test43 c.addi x16, 0x1 #tests43-48 test the cv.lh instruction (register offset). values loaded in and compared to are expected output values -#cv.lh instruction is of format "cv.lh rD, rs2(rs1!)". rD is loaded with the sign extended value at Mem16(rs1), then +#cv.lh instruction is of format "cv.lh rD, (rs1), rs2". rD is loaded with the sign extended value at Mem16(rs1), then #rs1 is incremented by the value of rs2. test43: li x20, 0x00120000 @@ -565,7 +565,7 @@ test43: li x17, 0x0eb518be li x22, 0xc8 sw x17, 0(x20) - cv.lh x18, x22(x20!) + cv.lh x18, (x20), x22 li x19, 0x000018be beq x18, x19, check43 c.addi x15, 0x1 @@ -577,7 +577,7 @@ test44: li x17, 0xae82beec li x22, 0x224 sw x17, 0(x20) - cv.lh x18, x22(x20!) + cv.lh x18, (x20), x22 li x19, 0xffffbeec beq x18, x19, check44 c.addi x15, 0x1 @@ -589,7 +589,7 @@ test45: li x17, 0x872ff921 li x22, 0xe0 sw x17, 0(x20) - cv.lh x18, x22(x20!) + cv.lh x18, (x20), x22 li x19, 0xfffff921 beq x18, x19, check45 c.addi x15, 0x1 @@ -601,7 +601,7 @@ test46: li x17, 0x6af22644 li x22, 0x424 sw x17, 0(x20) - cv.lh x18, x22(x20!) + cv.lh x18, (x20), x22 li x19, 0x00002644 beq x18, x19, check46 c.addi x15, 0x1 @@ -613,7 +613,7 @@ test47: li x17, 0xaab13adb li x22, 0x86 sw x17, 0(x20) - cv.lh x18, x22(x20!) + cv.lh x18, (x20), x22 li x19, 0x00003adb beq x18, x19, check47 c.addi x15, 0x1 @@ -625,7 +625,7 @@ test48: li x17, 0x5a5a1ece li x22, 0x6fc sw x17, 0(x20) - cv.lh x18, x22(x20!) + cv.lh x18, (x20), x22 li x19, 0x00001ece beq x18, x19, check48 c.addi x15, 0x1 @@ -634,7 +634,7 @@ check48: beq x20, x21, test49 c.addi x16, 0x1 #tests49-54 test the cv.lhu instruction (register offset). values loaded in and compared to are expected output values -#cv.lhu instruction is of format "cv.lhu rD, rs2(rs1!)". rD is loaded with the Z extended value at Mem16(rs1), then +#cv.lhu instruction is of format "cv.lhu rD, (rs1), rs2". rD is loaded with the Z extended value at Mem16(rs1), then #rs1 is incremented by the value of rs2. test49: li x20, 0x00120000 @@ -643,7 +643,7 @@ test49: li x22, 0x482 sw x17, 0(x20) nop - cv.lhu x18, x22(x20!) + cv.lhu x18, (x20), x22 li x19, 0x0000fd85 beq x18, x19, check49 c.addi x15, 0x1 @@ -655,7 +655,7 @@ test50: li x17, 0xc78ece79 li x22, 0xbd sw x17, 0(x20) - cv.lhu x18, x22(x20!) + cv.lhu x18, (x20), x22 li x19, 0x0000ce79 beq x18, x19, check50 c.addi x15, 0x1 @@ -667,7 +667,7 @@ test51: li x17, 0xeef54369 li x22, 0x2d2 sw x17, 0(x20) - cv.lhu x18, x22(x20!) + cv.lhu x18, (x20), x22 li x19, 0x00004369 beq x18, x19, check51 c.addi x15, 0x1 @@ -679,7 +679,7 @@ test52: li x17, 0xa9f93ae3 li x22, 0xb sw x17, 0(x20) - cv.lhu x18, x22(x20!) + cv.lhu x18, (x20), x22 li x19, 0x00003ae3 beq x18, x19, check52 c.addi x15, 0x1 @@ -691,7 +691,7 @@ test53: li x17, 0xee24c6e4 li x22, 0xee sw x17, 0(x20) - cv.lhu x18, x22(x20!) + cv.lhu x18, (x20), x22 li x19, 0x0000c6e4 beq x18, x19, check53 c.addi x15, 0x1 @@ -703,7 +703,7 @@ test54: li x17, 0xdd8f738b li x22, 0x3 sw x17, 0(x20) - cv.lhu x18, x22(x20!) + cv.lhu x18, (x20), x22 li x19, 0x0000738b beq x18, x19, check54 c.addi x15, 0x1 @@ -712,7 +712,7 @@ check54: beq x20, x21, test55 c.addi x16, 0x1 #tests55-60 test the cv.lw instruction (register offset). values loaded in and compared to are expected output values -#cv.lw instruction is of format "cv.lw rD, rs2(rs1!)". rD is loaded with the value at Mem(rs1), then +#cv.lw instruction is of format "cv.lw rD, (rs1), rs2". rD is loaded with the value at Mem(rs1), then #rs1 is incremented by the value of rs2. test55: li x20, 0x00120000 @@ -721,7 +721,7 @@ test55: li x22, 0x5 sw x17, 0(x20) nop - cv.lw x18, x22(x20!) + cv.lw x18, (x20), x22 li x19, 0xbe54b277 beq x18, x19, check55 c.addi x15, 0x1 @@ -733,7 +733,7 @@ test56: li x17, 0xdef7980c li x22, 0x5cf sw x17, 0(x20) - cv.lw x18, x22(x20!) + cv.lw x18, (x20), x22 li x19, 0xdef7980c beq x18, x19, check56 c.addi x15, 0x1 @@ -745,7 +745,7 @@ test57: li x17, 0x1021f6d2 li x22, 0x133 sw x17, 0(x20) - cv.lw x18, x22(x20!) + cv.lw x18, (x20), x22 li x19, 0x1021f6d2 beq x18, x19, check57 c.addi x15, 0x1 @@ -757,7 +757,7 @@ test58: li x17, 0x683e7019 li x22, 0xf8 sw x17, 0(x20) - cv.lw x18, x22(x20!) + cv.lw x18, (x20), x22 li x19, 0x683e7019 beq x18, x19, check58 c.addi x15, 0x1 @@ -769,7 +769,7 @@ test59: li x17, 0xe4f76ef9 li x22, 0x6 sw x17, 0(x20) - cv.lw x18, x22(x20!) + cv.lw x18, (x20), x22 li x19, 0xe4f76ef9 beq x18, x19, check59 c.addi x15, 0x1 @@ -781,7 +781,7 @@ test60: li x17, 0xd1337559 li x22, 0xd5 sw x17, 0(x20) - cv.lw x18, x22(x20!) + cv.lw x18, (x20), x22 li x19, 0xd1337559 beq x18, x19, check60 c.addi x15, 0x1 @@ -1075,14 +1075,14 @@ test90: beq x18, x19, test91 c.addi x15, 0x1 #tests91-96 test the cv.sb (immediate offset). values loaded in and compared to are expected output values -#cv.sb instruction is of format "cv.sb rs2, Imm(rs1!)". The memory location specified by rs1 is loaded with +#cv.sb instruction is of format "cv.sb rs2, (rs1), Imm". The memory location specified by rs1 is loaded with #the lowest 8 bits of rs2, and then rs1 is post-incremented by the Imm value. Imm has a max size of 12 bits. test91: li x20, 0x00120000 li x21, 0x00120000 li x17, 0x45da99a1 sw x23, 0(x20) - cv.sb x17, 0x169(x20!) + cv.sb x17, (x20), 0x169 lw x18, 0(x21) li x19, 0x000000a1 beq x18, x19, check91 @@ -1094,7 +1094,7 @@ check91: test92: li x17, 0x54cf5e63 sw x23, 0(x20) - cv.sb x17, 0xc(x20!) + cv.sb x17, (x20), 0xc lw x18, 0(x21) li x19, 0x00000063 beq x18, x19, check92 @@ -1102,11 +1102,11 @@ test92: check92: addi x21, x21, 0xc beq x20, x21, test93 - c.addi x16, 0x1 + c.addi x16, 0x1 test93: li x17, 0x96ea27cf sw x23, 0(x20) - cv.sb x17, 0x76b(x20!) + cv.sb x17, (x20), 0x76b lw x18, 0(x21) li x19, 0x000000cf beq x18, x19, check93 @@ -1118,7 +1118,7 @@ check93: test94: li x17, 0xcf8223dc sw x23, 0(x20) - cv.sb x17, 0x43(x20!) + cv.sb x17, (x20), 0x43 lw x18, 0(x21) li x19, 0x000000dc beq x18, x19, check94 @@ -1130,7 +1130,7 @@ check94: test95: li x17, 0x4523e08c sw x23, 0(x20) - cv.sb x17, 0x4e7(x20!) + cv.sb x17, (x20), 0x4e7 lw x18, 0(x21) li x19, 0x0000008c beq x18, x19, check95 @@ -1142,7 +1142,7 @@ check95: test96: li x17, 0x2b853d75 sw x23, 0(x20) - cv.sb x17, 0x182(x20!) + cv.sb x17, (x20), 0x182 lw x18, 0(x21) li x19, 0x00000075 beq x18, x19, check96 @@ -1152,14 +1152,14 @@ check96: beq x20, x21, test97 c.addi x16, 0x1 #tests97-102 test the cv.sh (immediate offset). values loaded in and compared to are expected output values -#cv.sh instruction is of format "cv.sh rs2, Imm(rs1!)". The memory location specified by rs1 is loaded with +#cv.sh instruction is of format "cv.sh rs2, (rs1), Imm". The memory location specified by rs1 is loaded with #the lower 16 bits of rs2, and then rs1 is post-incremented by the Imm value. Imm has a max size of 12 bits. test97: li x20, 0x00120000 li x21, 0x00120000 li x17, 0x941cf440 sw x23, 0(x20) - cv.sh x17, 0xf0(x20!) + cv.sh x17, (x20), 0xf0 lw x18, 0(x21) li x19, 0x0000f440 beq x18, x19, check97 @@ -1171,7 +1171,7 @@ check97: test98: li x17, 0xc6deecbe sw x23, 0(x20) - cv.sh x17, 0x2ce(x20!) + cv.sh x17, (x20), 0x2ce lw x18, 0(x21) li x19, 0x0000ecbe beq x18, x19, check98 @@ -1179,11 +1179,11 @@ test98: check98: addi x21, x21, 0x2ce beq x20, x21, test99 - c.addi x16, 0x1 + c.addi x16, 0x1 test99: li x17, 0x2ba34fea sw x23, 0(x20) - cv.sh x17, 0x5c8(x20!) + cv.sh x17, (x20), 0x5c8 lw x18, 0(x21) li x19, 0x00004fea beq x18, x19, check99 @@ -1195,7 +1195,7 @@ check99: test100: li x17, 0x6938a875 sw x23, 0(x20) - cv.sh x17, 0x1f2(x20!) + cv.sh x17, (x20), 0x1f2 lw x18, 0(x21) li x19, 0x0000a875 beq x18, x19, check100 @@ -1207,7 +1207,7 @@ check100: test101: li x17, 0x7b72a298 sw x23, 0(x20) - cv.sh x17, 0x19(x20!) + cv.sh x17, (x20), 0x19 lw x18, 0(x21) li x19, 0x0000a298 beq x18, x19, check101 @@ -1219,7 +1219,7 @@ check101: test102: li x17, 0x6c02d5f9 sw x23, 0(x20) - cv.sh x17, 0xe(x20!) + cv.sh x17, (x20), 0xe lw x18, 0(x21) li x19, 0x0000d5f9 beq x18, x19, check102 @@ -1229,13 +1229,13 @@ check102: beq x20, x21, test103 c.addi x16, 0x1 #tests103-108 test the cv.sw (immediate offset). values loaded in and compared to are expected output values -#cv.sw instruction is of format "cv.sw rs2, Imm(rs1!)". The memory location specified by rs1 is loaded with +#cv.sw instruction is of format "cv.sw rs2, (rs1), Imm". The memory location specified by rs1 is loaded with #the value of rs2, and then rs1 is post-incremented by the Imm value. Imm has a max size of 12 bits. test103: li x20, 0x00120000 li x21, 0x00120000 li x17, 0xc0020ade - cv.sw x17, 0x2d4(x20!) + cv.sw x17, (x20), 0x2d4 lw x18, 0(x21) li x19, 0xc0020ade beq x18, x19, check103 @@ -1246,7 +1246,7 @@ check103: c.addi x16, 0x1 test104: li x17, 0x7a47d390 - cv.sw x17, 0x4aa(x20!) + cv.sw x17, (x20), 0x4aa lw x18, 0(x21) li x19, 0x7a47d390 beq x18, x19, check104 @@ -1254,10 +1254,10 @@ test104: check104: addi x21, x21, 0x4aa beq x20, x21, test105 - c.addi x16, 0x1 + c.addi x16, 0x1 test105: li x17, 0x998655c1 - cv.sw x17, 0x54e(x20!) + cv.sw x17, (x20), 0x54e lw x18, 0(x21) li x19, 0x998655c1 beq x18, x19, check105 @@ -1268,7 +1268,7 @@ check105: c.addi x16, 0x1 test106: li x17, 0x4b6fe0c0 - cv.sw x17, 0xa(x20!) + cv.sw x17, (x20), 0xa lw x18, 0(x21) li x19, 0x4b6fe0c0 beq x18, x19, check106 @@ -1279,7 +1279,7 @@ check106: c.addi x16, 0x1 test107: li x17, 0xd24cd259 - cv.sw x17, 0x40(x20!) + cv.sw x17, (x20), 0x40 lw x18, 0(x21) li x19, 0xd24cd259 beq x18, x19, check107 @@ -1290,7 +1290,7 @@ check107: c.addi x16, 0x1 test108: li x17, 0xb13bdb56 - cv.sw x17, 0x13f(x20!) + cv.sw x17, (x20), 0x13f lw x18, 0(x21) li x19, 0xb13bdb56 beq x18, x19, check108 @@ -1300,7 +1300,7 @@ check108: beq x20, x21, test109 c.addi x16, 0x1 #tests109-114 test the cv.sb (register offset). values loaded in and compared to are expected output values -#cv.sb instruction is of format "cv.sb rs2, rs3(rs1!)". The memory location specified by rs1 is loaded with +#cv.sb instruction is of format "cv.sb rs2, (rs1), rs3". The memory location specified by rs1 is loaded with #the lowest 8 bits of rs2, and then rs1 is post-incremented by the value of rs3 test109: li x20, 0x00120000 @@ -1308,7 +1308,7 @@ test109: li x22, 0x000081ef li x17, 0x19726d93 sw x23, 0(x20) - cv.sb x17, x22(x20!) + cv.sb x17, (x20), x22 lw x18, 0(x21) li x19, 0x00000093 beq x18, x19, check109 @@ -1321,7 +1321,7 @@ test110: li x17, 0x6b186ac0 li x22, 0x0005807 sw x23, 0(x20) - cv.sb x17, x22(x20!) + cv.sb x17, (x20), x22 lw x18, 0(x21) li x19, 0x000000c0 beq x18, x19, check110 @@ -1334,7 +1334,7 @@ test111: li x17, 0xdf0bcaf4 li x22, 0x0004516d sw x23, 0(x20) - cv.sb x17, x22(x20!) + cv.sb x17, (x20), x22 lw x18, 0(x21) li x19, 0x000000f4 beq x18, x19, check111 @@ -1347,7 +1347,7 @@ test112: li x17, 0x6f5f2d04 li x22, 0x00007119 sw x23, 0(x20) - cv.sb x17, x22(x20!) + cv.sb x17, (x20), x22 lw x18, 0(x21) li x19, 0x00000004 beq x18, x19, check112 @@ -1360,7 +1360,7 @@ test113: li x17, 0xaa522c5c li x22, 0x000000d7 sw x23, 0(x20) - cv.sb x17, x22(x20!) + cv.sb x17, (x20), x22 lw x18, 0(x21) li x19, 0x0000005c beq x18, x19, check113 @@ -1373,7 +1373,7 @@ test114: li x17, 0x115bc669 li x22, 0x00000ea9 sw x23, 0(x20) - cv.sb x17, x22(x20!) + cv.sb x17, (x20), x22 lw x18, 0(x21) li x19, 0x00000069 beq x18, x19, check114 @@ -1383,7 +1383,7 @@ check114: beq x20, x21, test115 c.addi x16, 0x1 #tests115-120 test the cv.sh (register offset). values loaded in and compared to are expected output values -#cv.sh instruction is of format "cv.sh rs2, rs3(rs1!)". The memory location specified by rs1 is loaded with +#cv.sh instruction is of format "cv.sh rs2, (rs1), rs3". The memory location specified by rs1 is loaded with #the lower 16 bits of rs2, and then rs1 is post-incremented by the value of rs3 test115: li x20, 0x00120000 @@ -1391,7 +1391,7 @@ test115: li x17, 0xcd7f46b8 li x22, 0x000001ce sw x23, 0(x20) - cv.sh x17, x22(x20!) + cv.sh x17, (x20), x22 lw x18, 0(x21) li x19, 0x000046b8 beq x18, x19, check115 @@ -1404,7 +1404,7 @@ test116: li x17, 0x3469027c li x22, 0x00004dfe sw x23, 0(x20) - cv.sh x17, x22(x20!) + cv.sh x17, (x20), x22 lw x18, 0(x21) li x19, 0x0000027c beq x18, x19, check116 @@ -1412,12 +1412,12 @@ test116: check116: add x21, x21, x22 beq x20, x21, test117 - c.addi x16, 0x1 + c.addi x16, 0x1 test117: li x17, 0xf6e88dea li x22, 0x00000007 sw x23, 0(x20) - cv.sh x17, x22(x20!) + cv.sh x17, (x20), x22 lw x18, 0(x21) li x19, 0x00008dea beq x18, x19, check117 @@ -1430,7 +1430,7 @@ test118: li x17, 0xbe78c33e li x22, 0x00000369 sw x23, 0(x20) - cv.sh x17, x22(x20!) + cv.sh x17, (x20), x22 lw x18, 0(x21) li x19, 0x0000c33e beq x18, x19, check118 @@ -1443,7 +1443,7 @@ test119: li x17, 0x49ffa7b1 li x22, 0x000072de sw x23, 0(x20) - cv.sh x17, x22(x20!) + cv.sh x17, (x20), x22 lw x18, 0(x21) li x19, 0x0000a7b1 beq x18, x19, check119 @@ -1456,7 +1456,7 @@ test120: li x17, 0x98978835 li x22, 0x00004376 sw x23, 0(x20) - cv.sh x17, x22(x20!) + cv.sh x17, (x20), x22 lw x18, 0(x21) li x19, 0x00008835 beq x18, x19, check120 @@ -1466,14 +1466,14 @@ check120: beq x20, x21, test121 c.addi x16, 0x1 #tests121-126 test the cv.sw (register offset). values loaded in and compared to are expected output values -#cv.sw instruction is of format "cv.sw rs2, rs3(rs1!)". The memory location specified by rs1 is loaded with +#cv.sw instruction is of format "cv.sw rs2, (rs1), rs3". The memory location specified by rs1 is loaded with #the value of rs2, and then rs1 is post-incremented by the value of rs3 test121: li x20, 0x00120000 li x21, 0x00120000 li x17, 0x0e38cb05 li x22, 0x0006616a - cv.sw x17, x22(x20!) + cv.sw x17, (x20), x22 lw x18, 0(x21) li x19, 0x0e38cb05 beq x18, x19, check121 @@ -1485,7 +1485,7 @@ check121: test122: li x17, 0x09e4f2b8 li x22, 0x00000e6b - cv.sw x17, x22(x20!) + cv.sw x17, (x20), x22 lw x18, 0(x21) li x19, 0x09e4f2b8 beq x18, x19, check122 @@ -1493,11 +1493,11 @@ test122: check122: add x21, x21, x22 beq x20, x21, test123 - c.addi x16, 0x1 + c.addi x16, 0x1 test123: li x17, 0x316538b6 li x22, 0x0000f3d6 - cv.sw x17, x22(x20!) + cv.sw x17, (x20), x22 lw x18, 0(x21) li x19, 0x316538b6 beq x18, x19, check123 @@ -1509,7 +1509,7 @@ check123: test124: li x17, 0xd6954e61 li x22, 0x0000031c - cv.sw x17, x22(x20!) + cv.sw x17, (x20), x22 lw x18, 0(x21) li x19, 0xd6954e61 beq x18, x19, check124 @@ -1521,7 +1521,7 @@ check124: test125: li x17, 0x3528cd0f li x22, 0x0000008f - cv.sw x17, x22(x20!) + cv.sw x17, (x20), x22 lw x18, 0(x21) li x19, 0x3528cd0f beq x18, x19, check125 @@ -1533,7 +1533,7 @@ check125: test126: li x17, 0x248eb80a li x22, 0x00000006 - cv.sw x17, x22(x20!) + cv.sw x17, (x20), x22 lw x18, 0(x21) li x19, 0x248eb80a beq x18, x19, check126 @@ -1543,7 +1543,7 @@ check126: beq x20, x21, test127 c.addi x16, 0x1 #tests127-132 test the cv.sb (register-register). values loaded in and compared to are expected output values -#cv.sb instruction is of format "cv.sb rs2, rs3(rs1!)". The memory location specified by (rs1+rs3) is loaded with +#cv.sb instruction is of format "cv.sb rs2, (rs1), rs3". The memory location specified by (rs1+rs3) is loaded with #the lowest 8 bits of rs2. test127: li x20, 0x00120000 @@ -1629,7 +1629,7 @@ test134: lhu x18, 0(x22) li x19, 0x00006b82 beq x18, x19, test135 - c.addi x15, 0x1 + c.addi x15, 0x1 test135: li x17, 0xf99d2198 li x21, 0x0000fc55 @@ -1691,7 +1691,7 @@ test140: lw x18, 0(x22) li x19, 0x6bcc2112 beq x18, x19, test141 - c.addi x15, 0x1 + c.addi x15, 0x1 test141: li x17, 0xe9d5ca99 li x21, 0x0000b608 @@ -1736,4 +1736,3 @@ exit: li x17, 0x20000000 sw x18,0(x17) wfi - From 98823e5c4427993218171161ec88e19db9dd6d5c Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Thu, 14 Sep 2023 16:48:07 +0200 Subject: [PATCH 10/27] updated timeout on all tests --- cv32e40p/regress/cv32e40pv2_ci_check.yaml | 10 ++--- cv32e40p/regress/cv32e40pv2_fpu_instr.yaml | 2 +- .../regress/cv32e40pv2_interrupt_debug.yaml | 20 ++++----- cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml | 42 +++++++++---------- 4 files changed, 37 insertions(+), 37 deletions(-) diff --git a/cv32e40p/regress/cv32e40pv2_ci_check.yaml b/cv32e40p/regress/cv32e40pv2_ci_check.yaml index 6aec162695..04227a5d4c 100644 --- a/cv32e40p/regress/cv32e40pv2_ci_check.yaml +++ b/cv32e40p/regress/cv32e40pv2_ci_check.yaml @@ -104,20 +104,20 @@ tests: - uvmt_cv32e40p_pulp_cluster_fpu_zfinx_2cyclat description: UVM Hello World Test dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=hello-world + cmd: make test COREV=YES TEST=hello-world CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 interrupt_test: build: uvmt_cv32e40p_pulp_fpu description: Interrupt directed on PULP+FPU HW dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=interrupt_test + cmd: make test COREV=YES TEST=interrupt_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 debug_test: build: uvmt_cv32e40p_pulp_fpu dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test + cmd: make test COREV=YES TEST=debug_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 corev_rand_fp_instr_sanity_test: @@ -142,9 +142,9 @@ tests: corev_rand_pulp_instr_test: build: uvmt_cv32e40p_pulp dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_instr_test + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" corev_rand_pulp_hwloop_test: build: uvmt_cv32e40p_pulp dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_hwloop_test + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" diff --git a/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml b/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml index 5dadadcc9f..c12e93b366 100644 --- a/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml +++ b/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml @@ -53,5 +53,5 @@ tests: fpu_bugs_test: build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make test TEST=fpu_bugs_test + cmd: make test TEST=fpu_bugs_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml index 3e4c26aada..1004a81874 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml @@ -38,7 +38,7 @@ tests: build: uvmt_cv32e40p description: corev_rand_debug_ebreak_xpulp dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_ebreak_xpulp + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_ebreak_xpulp CFG_PLUSARGS="+UVM_TIMEOUT=20000000" test_cfg: debug_ebreak corev_rand_debug_single_step: @@ -95,60 +95,60 @@ tests: build: uvmt_cv32e40p description: corev_rand_pulp_hwloop_debug dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_hwloop_debug + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=20000000" debug_test: build: uvmt_cv32e40p description: debug_test (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test + cmd: make test COREV=YES TEST=debug_test CFG_PLUSARGS="+UVM_TIMEOUT=20000000" num: 1 debug_test_boot_set: build: uvmt_cv32e40p description: debug_test_boot_set (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test_boot_set + cmd: make test COREV=YES TEST=debug_test_boot_set CFG_PLUSARGS="+UVM_TIMEOUT=20000000" num: 1 debug_test_known_miscompares: build: uvmt_cv32e40p description: debug_test_known_miscompares (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test_known_miscompares + cmd: make test COREV=YES TEST=debug_test_known_miscompares CFG_PLUSARGS="+UVM_TIMEOUT=20000000" num: 1 debug_test_reset: build: uvmt_cv32e40p description: debug_test_reset (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test_reset + cmd: make test COREV=YES TEST=debug_test_reset CFG_PLUSARGS="+UVM_TIMEOUT=20000000" num: 1 debug_test_reset: build: uvmt_cv32e40p description: debug_test_reset (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test_reset + cmd: make test COREV=YES TEST=debug_test_reset CFG_PLUSARGS="+UVM_TIMEOUT=20000000" num: 1 interrupt_test: build: uvmt_cv32e40p description: interrupt_test (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=interrupt_test + cmd: make test COREV=YES TEST=interrupt_test CFG_PLUSARGS="+UVM_TIMEOUT=20000000" num: 1 interrupt_bootstrap: build: uvmt_cv32e40p description: interrupt_bootstrap (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=interrupt_bootstrap + cmd: make test COREV=YES TEST=interrupt_bootstrap CFG_PLUSARGS="+UVM_TIMEOUT=20000000" num: 1 riscv_ebreak_test_0: build: uvmt_cv32e40p description: riscv_ebreak_test_0 (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=riscv_ebreak_test_0 + cmd: make test COREV=YES TEST=riscv_ebreak_test_0 CFG_PLUSARGS="+UVM_TIMEOUT=20000000" num: 1 diff --git a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml index 44a6c61285..554f9a9b3c 100644 --- a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml +++ b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml @@ -52,14 +52,14 @@ tests: build: uvmt_cv32e40p description: pulp_hardware_loop directed test dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_hardware_loop + cmd: make test COREV=YES TEST=pulp_hardware_loop CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_hardware_loop_interrupt_test: build: uvmt_cv32e40p description: pulp_hardware_loop directed test dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_hardware_loop_interrupt_test + cmd: make test COREV=YES TEST=pulp_hardware_loop_interrupt_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 # pulp_hardware_loop_debug_test: @@ -77,131 +77,131 @@ tests: build: uvmt_cv32e40p description: pulp_bit_manipulation legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_bit_manipulation + cmd: make test COREV=YES TEST=pulp_bit_manipulation CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_general_alu: build: uvmt_cv32e40p description: pulp_general_alu legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_general_alu + cmd: make test COREV=YES TEST=pulp_general_alu CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_immediate_branching: build: uvmt_cv32e40p description: pulp_immediate_branching legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_immediate_branching + cmd: make test COREV=YES TEST=pulp_immediate_branching CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_multiply_accumulate: build: uvmt_cv32e40p description: pulp_multiply_accumulate legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_multiply_accumulate + cmd: make test COREV=YES TEST=pulp_multiply_accumulate CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_post_increment_load_store: build: uvmt_cv32e40p description: pulp_post_increment_load_store legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_post_increment_load_store + cmd: make test COREV=YES TEST=pulp_post_increment_load_store CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_vectorial_add_sub: build: uvmt_cv32e40p description: pulp_vectorial_add_sub legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_vectorial_add_sub + cmd: make test COREV=YES TEST=pulp_vectorial_add_sub CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_vectorial_avg: build: uvmt_cv32e40p description: pulp_vectorial_avg legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_vectorial_avg + cmd: make test COREV=YES TEST=pulp_vectorial_avg CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_vectorial_bit_manip: build: uvmt_cv32e40p description: pulp_vectorial_bit_manip legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_vectorial_bit_manip + cmd: make test COREV=YES TEST=pulp_vectorial_bit_manip CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_vectorial_bitwise: build: uvmt_cv32e40p description: pulp_vectorial_bitwise legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_vectorial_bitwise + cmd: make test COREV=YES TEST=pulp_vectorial_bitwise CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_vectorial_comparison_1: build: uvmt_cv32e40p description: pulp_vectorial_comparison_1 legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_vectorial_comparison_1 + cmd: make test COREV=YES TEST=pulp_vectorial_comparison_1 CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_vectorial_comparison_2: build: uvmt_cv32e40p description: pulp_vectorial_comparison_2 legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_vectorial_comparison_2 + cmd: make test COREV=YES TEST=pulp_vectorial_comparison_2 CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_vectorial_comparison_3: build: uvmt_cv32e40p description: pulp_vectorial_comparison_3 legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_vectorial_comparison_3 + cmd: make test COREV=YES TEST=pulp_vectorial_comparison_3 CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_vectorial_complex: build: uvmt_cv32e40p description: pulp_vectorial_complex legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_vectorial_complex + cmd: make test COREV=YES TEST=pulp_vectorial_complex CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_vectorial_dot_product_1: build: uvmt_cv32e40p description: pulp_vectorial_dot_product_1 legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_vectorial_dot_product_1 + cmd: make test COREV=YES TEST=pulp_vectorial_dot_product_1 CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_vectorial_dot_product_2: build: uvmt_cv32e40p description: pulp_vectorial_dot_product_2 legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_vectorial_dot_product_2 + cmd: make test COREV=YES TEST=pulp_vectorial_dot_product_2 CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_vectorial_max: build: uvmt_cv32e40p description: pulp_vectorial_max legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_vectorial_max + cmd: make test COREV=YES TEST=pulp_vectorial_max CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_vectorial_min: build: uvmt_cv32e40p description: pulp_vectorial_min legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_vectorial_min + cmd: make test COREV=YES TEST=pulp_vectorial_min CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_vectorial_shift: build: uvmt_cv32e40p description: pulp_vectorial_shift legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_vectorial_shift + cmd: make test COREV=YES TEST=pulp_vectorial_shift CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 pulp_vectorial_shuffle_pack: build: uvmt_cv32e40p description: pulp_vectorial_shuffle_pack legacy v1, kept as it stresses corner cases dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=pulp_vectorial_shuffle_pack + cmd: make test COREV=YES TEST=pulp_vectorial_shuffle_pack CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 From 19d7733e0aa446d47ebf7d1091e120fab1049a8b Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Thu, 14 Sep 2023 18:21:35 +0200 Subject: [PATCH 11/27] generalized the usage of skip_sim to a list of options that prevents the test to be added to the regression && added skip_sim for matmul float in benchmark to prevent its addition if cfg has no FPU --- bin/cv_regress | 15 ++++++--- cv32e40p/regress/cv32e40pv2_benchmarks.yaml | 36 +++++++++++++++++---- 2 files changed, 40 insertions(+), 11 deletions(-) diff --git a/bin/cv_regress b/bin/cv_regress index 12ca026d5a..48494c3401 100755 --- a/bin/cv_regress +++ b/bin/cv_regress @@ -137,11 +137,6 @@ def read_file(args, file): for k in testlist['tests']: t = testlist['tests'][k] - try: - if args.simulator in t['skip_sim']: - continue - except KeyError: - pass test = cv_regression.Test(name=k, simulator=args.simulator, **t) if args.cov: test.set_cov() @@ -173,6 +168,16 @@ def read_file(args, file): elif test.num != 1: test.num = int(args.num or test.num) + try: + if test.simulator in t['skip_sim']: + logger.info('Skipping test {} due to selected simulator {}'.format(test.name, test.simulator)) + continue + if test.cfg in t['skip_sim']: + logger.info('Skipping test {} due to selected cfg {}'.format(test.name, test.cfg)) + continue + except KeyError: + pass + regression.add_test(test) return regression diff --git a/cv32e40p/regress/cv32e40pv2_benchmarks.yaml b/cv32e40p/regress/cv32e40pv2_benchmarks.yaml index 2017d6c0cb..c13503d804 100644 --- a/cv32e40p/regress/cv32e40pv2_benchmarks.yaml +++ b/cv32e40p/regress/cv32e40pv2_benchmarks.yaml @@ -16,21 +16,45 @@ builds: uvmt_cv32e40p: cmd: make comp comp_corev-dv dir: cv32e40p/sim/uvmt - cfg: pulp + cfg: pulp_fpu +# ==================================================================================== # List of tests tests: + dhrystone: + build: uvmt_cv32e40p + description: dhrystone + dir: cv32e40p/sim/uvmt + cmd: make test TEST=dhrystone CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + num: 1 + + fibonacci: + build: uvmt_cv32e40p + description: fibonacci + dir: cv32e40p/sim/uvmt + cmd: make test TEST=fibonacci CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + num: 1 + coremark: build: uvmt_cv32e40p + description: coremark dir: cv32e40p/sim/uvmt - cmd: make test TEST=coremark + cmd: make test TEST=coremark CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + num: 1 - dhrystone: + matmul_32b_float: build: uvmt_cv32e40p + description: matmul_32b_float dir: cv32e40p/sim/uvmt - cmd: make test TEST=dhrystone + cmd: make test TEST=matmul_32b_float CFG_PLUSARGS="+UVM_TIMEOUT=2000000" + num: 1 + skip_sim: + - pulp + - pulp_cluster - fibonacci: + matmul_32b_int: build: uvmt_cv32e40p + description: matmul_32b_int dir: cv32e40p/sim/uvmt - cmd: make test TEST=fibonacci + cmd: make test TEST=matmul_32b_int CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + num: 1 From 3bdb05d89a6bbce17e4a8bc5f33e684a520febdf Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 15 Sep 2023 15:05:05 +0800 Subject: [PATCH 12/27] gpr constraint gpr_c overriden to include new reserved reg list Signed-off-by: Vaibhav Jain --- cv32e40p/env/corev-dv/cv32e40p_instr_gen_config.sv | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/cv32e40p/env/corev-dv/cv32e40p_instr_gen_config.sv b/cv32e40p/env/corev-dv/cv32e40p_instr_gen_config.sv index c034f45ab5..3bf17af480 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_instr_gen_config.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_instr_gen_config.sv @@ -80,12 +80,17 @@ class cv32e40p_instr_gen_config extends riscv_instr_gen_config; dp == ZERO; } else { !(dp inside {sp, tp, ra, scratch_reg, GP, RA, ZERO}); - foreach (gpr[i]) { - !(gpr[i] inside {dp}); - } } } + constraint gpr_c { + solve sp, tp, scratch_reg, dp, str_rs1, str_rs3 before gpr; + foreach (gpr[i]) { + !(gpr[i] inside {sp, tp, scratch_reg, pmp_reg, dp, str_rs1, str_rs3, ZERO, RA, GP}); + } + unique {gpr}; + } + // CV32E40P requires the MTVEC table to be aligned to 256KB boundaries constraint mtvec_c { tvec_alignment == 8; @@ -164,6 +169,7 @@ class cv32e40p_instr_gen_config extends riscv_instr_gen_config; `uvm_field_int(knob_zero_fast_intr_handlers, UVM_DEFAULT) `uvm_field_enum(riscv_reg_t, dp, UVM_DEFAULT) `uvm_field_enum(riscv_reg_t, scratch_reg, UVM_DEFAULT) + `uvm_field_sarray_enum(riscv_reg_t, gpr, UVM_DEFAULT) `uvm_field_int(enable_fast_interrupt_handler, UVM_DEFAULT) `uvm_field_int(use_fast_intr_handler, UVM_DEFAULT) `uvm_field_int(insert_rand_directed_instr_stream, UVM_DEFAULT) From 7bde730be00b55375d81c8b4799b40b033e0f4f1 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 15 Sep 2023 15:05:43 +0800 Subject: [PATCH 13/27] add plusarg test_override_riscv_instr_sequence=1 Signed-off-by: Vaibhav Jain --- .../corev-dv/corev_rand_debug_ebreak_xpulp/corev-dv.yaml | 1 + .../corev-dv/corev_rand_debug_single_step_xpulp/corev-dv.yaml | 1 + 2 files changed, 2 insertions(+) diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_debug_ebreak_xpulp/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_debug_ebreak_xpulp/corev-dv.yaml index 681bf7fee2..fef88275c5 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_rand_debug_ebreak_xpulp/corev-dv.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_debug_ebreak_xpulp/corev-dv.yaml @@ -22,3 +22,4 @@ plusargs: > +enable_debug_single_step=0 +gen_debug_section=1 +test_override_riscv_instr_stream=1 + +test_override_riscv_instr_sequence=1 diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_debug_single_step_xpulp/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_debug_single_step_xpulp/corev-dv.yaml index 74ed51aaac..ce030d4581 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_rand_debug_single_step_xpulp/corev-dv.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_debug_single_step_xpulp/corev-dv.yaml @@ -22,3 +22,4 @@ plusargs: > +enable_debug_single_step=1 +gen_debug_section=1 +test_override_riscv_instr_stream=1 + +test_override_riscv_instr_sequence=1 From ea18f453db8df5614d0c9c7bb1611b1948cad8e2 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 15 Sep 2023 15:09:35 +0800 Subject: [PATCH 14/27] add fix_sp=1 to ensure x2 reg is used as sp in these tests to avoid conflict with compress load stores with sp which are included Signed-off-by: Vaibhav Jain --- .../programs/corev-dv/corev_rand_pulp_instr_test/corev-dv.yaml | 1 + .../corev-dv/corev_rand_pulp_mac_instr_test/corev-dv.yaml | 1 + .../corev-dv/corev_rand_pulp_simd_instr_test/corev-dv.yaml | 1 + 3 files changed, 3 insertions(+) diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_instr_test/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_instr_test/corev-dv.yaml index 3a58cd66f9..254e4e4f49 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_instr_test/corev-dv.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_instr_test/corev-dv.yaml @@ -33,6 +33,7 @@ plusargs: > +no_csr_instr=0 +no_wfi=1 +no_dret=1 + +fix_sp=1 +enable_misaligned_instr=1 +test_override_riscv_instr_stream=1 +test_override_riscv_instr_sequence=1 diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_mac_instr_test/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_mac_instr_test/corev-dv.yaml index 37225b445e..09bbf092ab 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_mac_instr_test/corev-dv.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_mac_instr_test/corev-dv.yaml @@ -30,6 +30,7 @@ plusargs: > +no_wfi=1 +no_ebreak=1 +no_dret=1 + +fix_sp=1 +enable_misaligned_instr=1 +set_dcsr_ebreak=0 +test_override_riscv_instr_stream=1 diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_simd_instr_test/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_simd_instr_test/corev-dv.yaml index 45ade40084..18b5395a3a 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_simd_instr_test/corev-dv.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_simd_instr_test/corev-dv.yaml @@ -30,6 +30,7 @@ plusargs: > +no_wfi=1 +no_ebreak=1 +no_dret=1 + +fix_sp=1 +enable_misaligned_instr=1 +set_dcsr_ebreak=0 +test_override_riscv_instr_stream=1 From cc4c94850b6dde08ae7dbd3638db772227124fba Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 15 Sep 2023 15:10:20 +0800 Subject: [PATCH 15/27] add obi_zero_latency test_cfg yaml Signed-off-by: Vaibhav Jain --- cv32e40p/tests/test_cfg/obi_zero_latency.yaml | 5 +++++ 1 file changed, 5 insertions(+) create mode 100644 cv32e40p/tests/test_cfg/obi_zero_latency.yaml diff --git a/cv32e40p/tests/test_cfg/obi_zero_latency.yaml b/cv32e40p/tests/test_cfg/obi_zero_latency.yaml new file mode 100644 index 0000000000..ea3ae8205a --- /dev/null +++ b/cv32e40p/tests/test_cfg/obi_zero_latency.yaml @@ -0,0 +1,5 @@ +name: Fixed zero latency for both obi buses +description: > + Obi bus latency config - Zero delay +plusargs: > + +rand_stall_obi_disable From b2303ce3b75d43ed872deb785177e507fe40ee1a Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 15 Sep 2023 15:21:41 +0800 Subject: [PATCH 16/27] update v2 regress lists for interrupt_debug and xpulp Signed-off-by: Vaibhav Jain --- .../regress/cv32e40pv2_interrupt_debug.yaml | 103 ++++++++++++++---- cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml | 26 ++++- 2 files changed, 106 insertions(+), 23 deletions(-) diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml index 1004a81874..97a81a4d2d 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml @@ -25,77 +25,67 @@ tests: build: uvmt_cv32e40p description: corev_rand_debug dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" corev_rand_debug_ebreak: build: uvmt_cv32e40p description: corev_rand_debug_ebreak dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_ebreak CFG_PLUSARGS="+UVM_TIMEOUT=20000000" - test_cfg: debug_ebreak + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_ebreak CFG_PLUSARGS="+UVM_TIMEOUT=10000000" corev_rand_debug_ebreak_xpulp: build: uvmt_cv32e40p description: corev_rand_debug_ebreak_xpulp dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_ebreak_xpulp CFG_PLUSARGS="+UVM_TIMEOUT=20000000" - test_cfg: debug_ebreak + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_ebreak_xpulp CFG_PLUSARGS="+UVM_TIMEOUT=10000000" corev_rand_debug_single_step: build: uvmt_cv32e40p description: corev_rand_debug_single_step dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_single_step CFG_PLUSARGS="+UVM_TIMEOUT=20000000" - test_cfg: debug_single_step_en + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_single_step CFG_PLUSARGS="+UVM_TIMEOUT=10000000" corev_rand_debug_single_step_xpulp: build: uvmt_cv32e40p description: corev_rand_debug_single_step_xpulp dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_single_step_xpulp CFG_PLUSARGS="+UVM_TIMEOUT=20000000" - test_cfg: debug_single_step_en + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_single_step_xpulp CFG_PLUSARGS="+UVM_TIMEOUT=10000000" corev_rand_interrupt: build: uvmt_cv32e40p description: corev_rand_interrupt dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt CFG_PLUSARGS="+UVM_TIMEOUT=10000000" corev_rand_interrupt_debug: build: uvmt_cv32e40p description: corev_rand_interrupt_debug dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_debug CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" corev_rand_interrupt_exception: build: uvmt_cv32e40p description: corev_rand_interrupt_exception dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_exception CFG_PLUSARGS="+UVM_TIMEOUT=10000000" corev_rand_interrupt_nested: build: uvmt_cv32e40p description: corev_rand_interrupt_nested dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_nested CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_nested CFG_PLUSARGS="+UVM_TIMEOUT=10000000" corev_rand_interrupt_wfi: build: uvmt_cv32e40p description: corev_rand_interrupt_wfi dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi CFG_PLUSARGS="+UVM_TIMEOUT=10000000" corev_rand_interrupt_wfi_mem_stress: build: uvmt_cv32e40p description: corev_rand_interrupt_wfi_mem_stress dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=20000000" - - corev_rand_pulp_hwloop_debug: - build: uvmt_cv32e40p - description: corev_rand_pulp_hwloop_debug - dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=10000000" debug_test: build: uvmt_cv32e40p @@ -152,3 +142,74 @@ tests: dir: cv32e40p/sim/uvmt cmd: make test COREV=YES TEST=riscv_ebreak_test_0 CFG_PLUSARGS="+UVM_TIMEOUT=20000000" num: 1 + + corev_rand_pulp_instr_ebreak_debug_test: + testname: corev_rand_pulp_instr_test + description: pulp rand test with ebreak debug + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" + test_cfg: debug_ebreak + + corev_rand_pulp_instr_single_step_debug_test: + testname: corev_rand_pulp_instr_test + description: pulp rand test with single-step debug + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" + test_cfg: debug_single_step_en + + corev_rand_pulp_instr_interrupt_test: + testname: corev_rand_pulp_instr_test + description: pulp instr test with random interrupts + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" + test_cfg: gen_rand_int + + corev_rand_pulp_hwloop_debug: + build: uvmt_cv32e40p + description: hwloop debug random test + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + + corev_rand_pulp_hwloop_debug_ebreak: + testname: corev_rand_pulp_hwloop_debug + description: hwloop ebreak debug random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_ebreak + + corev_rand_pulp_hwloop_debug_single_step: + testname: corev_rand_pulp_hwloop_debug + description: hwloop single-step debug random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_single_step_en + + corev_rand_pulp_hwloop_debug_with_interrupt: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug with interrupt random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int + + corev_rand_pulp_hwloop_interrupt_test: + testname: corev_rand_pulp_hwloop_test + description: hwloop test with random interrupts + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int + + corev_rand_pulp_hwloop_exception_single_step_debug: + testname: corev_rand_pulp_hwloop_exception + description: hwloop exception test with single step debug + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_single_step_en + diff --git a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml index 554f9a9b3c..80c5f0312a 100644 --- a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml +++ b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml @@ -28,13 +28,13 @@ tests: build: uvmt_cv32e40p description: corev_rand_pulp_hwloop_test dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" corev_rand_pulp_instr_test: build: uvmt_cv32e40p description: corev_rand_pulp_instr_test dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" corev_rand_pulp_simd_instr_test: build: uvmt_cv32e40p @@ -48,6 +48,28 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_mac_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + corev_rand_pulp_hwloop_exception: + build: uvmt_cv32e40p + description: hwloop exception test + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + + corev_rand_pulp_illegal_instr_test: + testname: corev_rand_pulp_instr_test + description: pulp instr test with illegal instructions + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" + test_cfg: insert_illegal_instr + + corev_rand_pulp_hwloop_illegal_instr_test: + testname: corev_rand_pulp_hwloop_test + description: hwloop test with illegal instructions + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: insert_illegal_instr + pulp_hardware_loop: build: uvmt_cv32e40p description: pulp_hardware_loop directed test From 029bac447efc0c98d3241144b60259d953171847 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 15 Sep 2023 15:42:35 +0800 Subject: [PATCH 17/27] update cv32e40p core hash Signed-off-by: Vaibhav Jain --- cv32e40p/sim/ExternalRepos.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cv32e40p/sim/ExternalRepos.mk b/cv32e40p/sim/ExternalRepos.mk index 999d600691..fb5da82f2c 100644 --- a/cv32e40p/sim/ExternalRepos.mk +++ b/cv32e40p/sim/ExternalRepos.mk @@ -15,7 +15,7 @@ export SHELL = /bin/bash CV_CORE_REPO ?= https://github.com/openhwgroup/cv32e40p CV_CORE_BRANCH ?= dev -CV_CORE_HASH ?= 7e131050c88bd57b2866887eea7de07735f60706 +CV_CORE_HASH ?= d0f3305c82492f63e7eaad3f6781453de9c4573d CV_CORE_TAG ?= none # The CV_CORE_HASH above points to version of the RTL that is newer. From 615959272e80b3e1d3d9c85ad496933836d0de32 Mon Sep 17 00:00:00 2001 From: bsm Date: Wed, 20 Sep 2023 12:57:43 +0800 Subject: [PATCH 18/27] Update core hash Signed-off-by: bsm --- cv32e40p/sim/ExternalRepos.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cv32e40p/sim/ExternalRepos.mk b/cv32e40p/sim/ExternalRepos.mk index fb5da82f2c..747473e2ed 100644 --- a/cv32e40p/sim/ExternalRepos.mk +++ b/cv32e40p/sim/ExternalRepos.mk @@ -15,7 +15,7 @@ export SHELL = /bin/bash CV_CORE_REPO ?= https://github.com/openhwgroup/cv32e40p CV_CORE_BRANCH ?= dev -CV_CORE_HASH ?= d0f3305c82492f63e7eaad3f6781453de9c4573d +CV_CORE_HASH ?= c520546c0cc3f64ef064d52dfdc91abbba63f181 CV_CORE_TAG ?= none # The CV_CORE_HASH above points to version of the RTL that is newer. From 0cab4174996aa329bc127da612c3567a4e38b4cb Mon Sep 17 00:00:00 2001 From: bsm Date: Wed, 20 Sep 2023 12:59:59 +0800 Subject: [PATCH 19/27] Fix directed stream placement when limit reached Signed-off-by: bsm --- .../corev-dv/cv32e40p_rand_instr_stream.sv | 28 +++++++++++-------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv b/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv index 8127ea318c..7baeb00a26 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv @@ -109,7 +109,18 @@ class cv32e40p_rand_instr_stream extends riscv_rand_instr_stream; rand_cnt++; if (rand_cnt >= 200) begin - `uvm_fatal(`gfn, $sformatf("rand_cnt hit limit %0d and not able to find space for instr placement. Please revise the stream", rand_cnt)) + int idx_placement[$]; + `uvm_info(`gfn, $sformatf("placement limit %0d reached. Place the stream at begining of instr_list", rand_cnt), UVM_NONE) + idx = 0; + idx_e = (idx + new_instr_cnt-1); + idx_start.push_front(idx); + idx_end.push_front(idx_e); + idx_placement = idx_start.find_first_index(x) with (x == idx); + for (int i=idx_placement[0]+1; i Date: Wed, 20 Sep 2023 13:01:54 +0800 Subject: [PATCH 20/27] Fix test issues; Add xpulp load store in operand forward test; Optimize fflag clear in test Signed-off-by: bsm --- .../instr_lib/cv32e40p_float_instr_lib.sv | 271 ++++++++++++++---- .../cv32e40p_float_instr_lib_defines.sv | 2 +- 2 files changed, 219 insertions(+), 54 deletions(-) diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv index e03c3d1ba6..e54f5d3ebd 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv @@ -38,7 +38,7 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; // properties - start string _header; bit is_zfinx = riscv_instr_pkg::RV32ZFINX inside {riscv_instr_pkg::supported_isa}; - bit is_fp_instr; + bit is_fp_instr, is_fpc_instr; riscv_instr_name_t include_instr[]; riscv_instr_name_t exclude_instr[]; riscv_instr_category_t include_category[]; @@ -50,6 +50,7 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; bit use_no_repetitive_instr_per_stream; // directed instr is not allow to repeat in a stream bit use_same_instr_per_stream; // same directed is use within a stream bit use_prev_rd_on_next_operands; // previous instr rd is used for directed instr operands + bit use_diff_regs_for_operands = 0; // to control rand instr uses different registers for instr oeprands bit more_weight_for_fdiv_fsqrt_gen; // more weight on generating fdiv and fsqrt directed_instr bit init_gpr = (is_zfinx) ? 1 : 0; // initialize gpr registers in stream with rand value bit init_fpr = (is_zfinx) ? 0 : 1; // initialize fpr registers in stream with rand value @@ -72,6 +73,7 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; rand bit [31:0] imm; rand f_rounding_mode_t rm; rand bit use_rounding_mode_from_instr; + rand bit use_xpulp_as_others_instr; // rand bit use_special_operand_patterns; rand operand_pattens_t operand_a_pattern[]; @@ -136,6 +138,10 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; } } + constraint c_use_xpulp_as_others_instr { + use_xpulp_as_others_instr dist {0:=3, 1:=1}; + } + `C_OPERAND_PATTERN(a) `C_OPERAND_PATTERN(b) `C_OPERAND_PATTERN(c) @@ -349,7 +355,6 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; end set_reserved_sp_addr(); set_csr_fm(gp_reg_scratch); - clr_crs_fflags(gp_reg_scratch); // note: this must be the last in order endfunction : initialize_regs // for updating the arguments that use in get_rand_instr @@ -377,8 +382,9 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; exclude_instr = new[33] ({`EXCLUDE_INSTR_LIST}); if (!select_fp_instr) begin : USE_OTHERS include_group.delete(); - if ($urandom_range(1)) include_group = new[3] ({RV32I, RV32M, RV32C}); - else include_group = new[3] ({RV32I, RV32M, RV32X}); + if (use_xpulp_as_others_instr) include_group = new[1] ({RV32X}); + else if ($urandom_range(1)) include_group = new[3] ({RV32I, RV32M, RV32C}); + else include_group = new[3] ({RV32I, RV32M, RV32X}); end end @@ -401,6 +407,10 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; // placeholder to insert additonal instr if there is any prior directed instr virtual function void add_instr_prior_directed_instr(riscv_instr instr, int idx=0); + if (is_fp_instr) begin + if (en_clr_fflags_af_instr) + clr_crs_fflags(gp_reg_scratch); + end endfunction : add_instr_prior_directed_instr virtual function void update_next_instr_arg_list(riscv_instr prev_instr=null, int idx=0); @@ -435,6 +445,9 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; } if (has_rs2) { rs2 != reserved_rd[i]; + if (local::use_diff_regs_for_operands) { + rs2 != rs1; + } } if (has_rd) { rd != reserved_rd[i]; @@ -460,6 +473,63 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; endfunction: randomize_gpr + function void randomize_gpr_compress(cv32e40p_riscv_compressed_instr instr, int idx=0); + rand_var_for_inline_constraint(); + instr.set_rand_mode(); + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, + if (local::avail_gp_regs[local::idx].size() > 0) { + if (has_rs1) { + rs1 inside {avail_gp_regs[local::idx]}; + } + if (has_rs2) { + rs2 inside {avail_gp_regs[local::idx]}; + } + if (has_rd) { + rd inside {avail_gp_regs[local::idx]}; + } + } + foreach (reserved_rd[i]) { + if (has_rs1) { + rs1 != reserved_rd[i]; + } + if (has_rs2) { + rs2 != reserved_rd[i]; + if (local::use_diff_regs_for_operands) { + rs2 != rs1; + } + } + if (has_rd) { + rd != reserved_rd[i]; + } + if (format == CB_FORMAT) { + rs1 != reserved_rd[i]; + } + } + foreach (cfg.reserved_regs[i]) { + if (has_rd) { + rd != cfg.reserved_regs[i]; + } + if (format == CB_FORMAT) { + rs1 != cfg.reserved_regs[i]; + } + } + if (local::avail_fp_regs[local::idx].size() >0 ) { + if (has_fs2) { + fs2 inside {avail_fp_regs[local::idx]}; + } + if (has_fd) { + fd inside {avail_fp_regs[local::idx]}; + } + } + if (has_imm) { + soft imm == local::imm; + } + rm == local::rm; + use_rounding_mode_from_instr == local::use_rounding_mode_from_instr; + ) + + endfunction: randomize_gpr_compress + function void randomize_gpr_zfinx(riscv_fp_in_x_regs_instr instr, int idx=0); rand_var_for_inline_constraint(); instr.set_rand_mode(); @@ -470,9 +540,16 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; } if (has_rs2) { rs2 inside {avail_gp_regs[local::idx]}; + if (local::use_diff_regs_for_operands) { + rs2 != rs1; + } } if (has_rs3) { rs3 inside {avail_gp_regs[local::idx]}; + if (local::use_diff_regs_for_operands) { + rs3 != rs2; + rs3 != rs1; + } } if (has_rd) { rd inside {avail_gp_regs[local::idx]}; @@ -512,9 +589,16 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; } if (has_fs2) { fs2 inside {avail_fp_regs[local::idx]}; + if (local::use_diff_regs_for_operands) { + fs2 != fs1; + } } if (has_fs3) { fs3 inside {avail_fp_regs[local::idx]}; + if (local::use_diff_regs_for_operands) { + fs3 != fs2; + fs3 != fs1; + } } if (has_fd) { fd inside {avail_fp_regs[local::idx]}; @@ -697,10 +781,6 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; riscv_fp_in_x_regs_instr p_instr_zfinx=null, riscv_floating_point_instr p_instr_f=null, int idx=0); - if (is_fp_instr) begin - if (en_clr_fflags_af_instr) - clr_crs_fflags(gp_reg_scratch); - end endfunction: act_post_directed_instr // add b2b nop instr (eq to ADDI x0, x0, 0) @@ -943,6 +1023,11 @@ class cv32e40p_fp_w_prev_rd_as_operand_instr_stream extends cv32e40p_float_zfinx include_load_store_base_sp = 0; // exclude store instrs for this stream endfunction: pre_randomize + function void post_randomize(); + super.post_randomize(); + clr_crs_fflags(gp_reg_scratch); + endfunction : post_randomize + // to define exclude list for this stream class virtual function void update_current_instr_arg_list(int idx=0); super.update_current_instr_arg_list(idx); @@ -985,6 +1070,7 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i super.pre_randomize(); // cycle through all possible mc instrs for selected directed fp instr per stream use_fp_only_for_directed_instr = 1; + en_clr_fflags_af_instr = 0; use_same_instr_per_stream = 1; endfunction: pre_randomize @@ -993,9 +1079,8 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i riscv_fp_in_x_regs_instr p_instr_zfinx=null, riscv_floating_point_instr p_instr_f=null, int idx=0); - super.act_post_directed_instr(); - // put some random NOP before next mc fp iteration - insert_nop_instr($urandom_range(1,2)); + clr_crs_fflags(gp_reg_scratch); + insert_nop_instr($urandom_range(1,2)); // put some random NOP before next mc fp iteration endfunction: act_post_directed_instr virtual function void update_current_instr_arg_list(int idx=0); @@ -1012,7 +1097,7 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i riscv_floating_point_instr mc_instr_f; if (instr.group inside {RV32F, RV32FC, RV32ZFINX}) begin : BODY - + mc_instr = new riscv_instr::get_rand_instr( .exclude_instr(mc_exclude_instr), .include_group((is_zfinx) ? {RV32ZFINX} : {RV32F, RV32FC}) @@ -1205,6 +1290,7 @@ class cv32e40p_fp_op_fwd_instr_stream extends cv32e40p_float_zfinx_base_instr_st function void pre_randomize(); super.pre_randomize(); use_fp_only_for_directed_instr = 0; + en_clr_fflags_af_instr = 0; num_of_instr_per_block = 10; include_load_store_base_sp = 0; // exclude store instrs for this stream assert (num_of_instr_per_block != 0 && num_of_instr_per_block%10 == 0); @@ -1236,8 +1322,9 @@ class cv32e40p_fp_op_fwd_instr_stream extends cv32e40p_float_zfinx_base_instr_st else include_instr.delete(); end else begin - if ($urandom_range(1)) include_group = new[3] ({RV32I, RV32M, RV32C}); - else include_group = new[3] ({RV32I, RV32M, RV32X}); + if (use_xpulp_as_others_instr) include_group = new[1] ({RV32X}); + else if ($urandom_range(1)) include_group = new[3] ({RV32I, RV32M, RV32C}); + else include_group = new[3] ({RV32I, RV32M, RV32X}); include_instr.delete(); end endfunction: update_current_instr_arg_list @@ -1421,6 +1508,8 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b bit use_load_store_w_sp_only; bit use_compress_load_store_only; int unsigned num_of_load_store_instr; + bit post_fp_src_is_load_dest; + int unsigned cnt, cnt_limit=100; rand int unsigned stream_loops; @@ -1436,8 +1525,9 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b function void pre_randomize(); super.pre_randomize(); use_fp_only_for_directed_instr = 0; - en_clr_fflags_af_instr = 1; + en_clr_fflags_af_instr = 0; include_load_store_base_sp = 0; // do not reserved SP + reserved_rd = new[reserved_rd.size()+1] ({reserved_rd, ZERO}); endfunction: pre_randomize virtual function void reset_rand_instr_entry(); @@ -1466,15 +1556,15 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b if (p_instr_zfinx != null) begin unique case (p_instr_zfinx.instr_name) - FADD_S, FSUB_S : begin `SET_GPR_VALUE(i_rs1, F_NEG_ZERO); `SET_GPR_VALUE(i_rs2, ALL_ZERO); end // rd = rs1 +/- rs2 - FMADD_S, FMSUB_S : begin `SET_GPR_VALUE(i_rs1, F_POS_ONE); `SET_GPR_VALUE(i_rs2, F_NEG_ZERO); `SET_GPR_VALUE(i_rs3, ALL_ZERO); end // rd = rs1*rs2 +/- rs3 - FNMADD_S, FNMSUB_S : begin `SET_GPR_VALUE(i_rs1, F_NEG_ONE); `SET_GPR_VALUE(i_rs2, F_NEG_ZERO); `SET_GPR_VALUE(i_rs3, ALL_ZERO); end // rd = -rs1*rs2 -/+ rs3 + FADD_S, FSUB_S : begin `SET_GPR_VALUE(i_rs1, F_NEG_ZERO_DIV2); `SET_GPR_VALUE(i_rs2, ALL_ZERO); end // rd = rs1 +/- rs2 + FMADD_S, FMSUB_S : begin `SET_GPR_VALUE(i_rs1, F_POS_ONE); `SET_GPR_VALUE(i_rs2, F_NEG_ZERO_DIV2); `SET_GPR_VALUE(i_rs3, ALL_ZERO); end // rd = rs1*rs2 +/- rs3 + FNMADD_S, FNMSUB_S : begin `SET_GPR_VALUE(i_rs1, F_NEG_ONE); `SET_GPR_VALUE(i_rs2, F_NEG_ZERO_DIV2); `SET_GPR_VALUE(i_rs3, ALL_ZERO); end // rd = -rs1*rs2 -/+ rs3 FMUL_S, FDIV_S : begin `SET_GPR_VALUE(i_rs1, F_NEG_ZERO_DIV2); `SET_GPR_VALUE(i_rs2, F_POS_ONE); end // rd = rs1 *// rs2 FSQRT_S : begin `SET_GPR_VALUE(i_rs1, F_POS_FOUR); end // rd = sqrt(rs1) FMAX_S : begin `SET_GPR_VALUE(i_rs1, F_POS_FOUR); `SET_GPR_VALUE(i_rs2, ALL_ZERO); end // rd = (rs1 > rs2) ? rs1 : rs2; - FMIN_S : begin `SET_GPR_VALUE(i_rs1, F_NEG_ZERO_DIV2); `SET_GPR_VALUE(i_rs2, F_NEG_ZERO); end // rd = (rs1 < rs2) ? rs1 : rs2; - FSGNJ_S, FSGNJX_S : begin `SET_GPR_VALUE(i_rs1, ALL_ZERO); `SET_GPR_VALUE(i_rs2, F_NEG_ZERO); end // rd = sign(rs2),rs1[30:0] / rd = sign(rs1 xor rs2), rs1[30:0] - FSGNJN_S : begin `SET_GPR_VALUE(i_rs1, ALL_ZERO); `SET_GPR_VALUE(i_rs2, F_POS_FOUR); end // rd = sign(!rs2),rs1[30:0] + FMIN_S : begin `SET_GPR_VALUE(i_rs1, F_NEG_ZERO_DIV2); `SET_GPR_VALUE(i_rs2, F_NEG_ZERO_DIV2); end // rd = (rs1 < rs2) ? rs1 : rs2; + FSGNJ_S, FSGNJX_S : begin `SET_GPR_VALUE(i_rs1, F_NEG_ZERO_DIV2); `SET_GPR_VALUE(i_rs2, ALL_ZERO); end // rd = sign(rs2),rs1[30:0] / rd = sign(rs1 xor rs2), rs1[30:0] + FSGNJN_S : begin `SET_GPR_VALUE(i_rs1, F_NEG_ZERO_DIV2); `SET_GPR_VALUE(i_rs2, F_NEG_ZERO); end // rd = sign(!rs2),rs1[30:0] FCVT_S_W, FCVT_S_WU : begin `SET_GPR_VALUE(i_rs1, D_POS_TWO); end // rd(float) = rs1(int) FCVT_W_S, FCVT_WU_S : begin `SET_GPR_VALUE(i_rs1, F_POS_VAL1); end // rd(int) = rs1(floating) endcase @@ -1482,13 +1572,22 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b else begin unique case (p_instr_f.instr_name) FCVT_W_S, FCVT_WU_S : begin `SET_FPR_VALUE(i_fs1, F_POS_VAL1); end // rd(int) = fs1 - FMV_X_W : begin `SET_FPR_VALUE(i_fs1, F_NEG_ZERO); end // rd(int) <- fs1 + FMV_X_W : begin `SET_FPR_VALUE(i_fs1, F_NEG_ZERO_DIV2); end // rd(int) <- fs1 endcase end endfunction : manipulate_preceeded_fp + virtual function void cnt_limit_chk(string str="NULL"); + cnt++; + if (cnt >= cnt_limit) begin + `uvm_fatal(_header, $sformatf("[%s] cnt_%0d vs cnt_limit_%0d reached", str, cnt, cnt_limit)); + end + endfunction : cnt_limit_chk + // override because this testcase need special handling + // note: + // limitation_1 (commented out): on RV32FC due to current workaround at convert2asm in cv32e40p_riscv_compressed_instr function void post_randomize(); print_stream_setting(); @@ -1498,15 +1597,17 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b riscv_instr instr, instr2, instr3; riscv_fp_in_x_regs_instr instr_zfinx, instr_zfinx2, instr_zfinx3; riscv_floating_point_instr instr_f, instr_f2, instr_f3; - cv32e40p_riscv_compressed_instr instr_fc; - int unsigned cnt, cnt_limit=100; - riscv_reg_t last_store_rs1=ZERO; + cv32e40p_riscv_compressed_instr instr_fc, instr_fc2; + riscv_reg_t last_load_rd, last_store_rs1, q_load_rd[$]; + riscv_fpr_t last_load_fd; + bit has_store, has_load_rd, has_load_fd; // rand available options use_compress_load_store_only = $urandom_range(1); use_load_store_w_sp_only = (use_compress_load_store_only) ? $urandom_range(1) : 0; load_store_option = load_store_opt_t'($urandom_range(2)); num_of_load_store_instr = $urandom_range(4,8); + post_fp_src_is_load_dest = (load_store_option inside {LOAD_ONLY, LOAD_STORE}) ? $urandom_range(1) : 0; if (use_compress_load_store_only) begin void'(std::randomize(avail_gp_regs[i]) with { @@ -1518,6 +1619,7 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b }); void'(std::randomize(avail_fp_regs[i]) with { avail_fp_regs[i].size() == 8; + // avail_fp_regs[i].size() == 4; // limitation_1 unique{avail_fp_regs[i]}; foreach (avail_fp_regs[i][j]) { avail_fp_regs[i][j] inside {[FS0:FA5]}; @@ -1527,6 +1629,7 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b // generate preceeded fp - start + use_diff_regs_for_operands = 1; reset_rand_instr_entry(); exclude_instr = new[4] ({FEQ_S, FLT_S, FLE_S, FCLASS_S}); exclude_category = new[2] ({LOAD, STORE}); @@ -1534,15 +1637,12 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b else include_group = new[1] ({RV32F}); cnt = 0; do begin - if (cnt == cnt_limit) begin - `uvm_fatal(_header, $sformatf("[generate preceeded fp] cnt_limit reached")); - end + cnt_limit_chk("generate_preceeded_fp"); instr = new riscv_instr::get_rand_instr( .exclude_instr(exclude_instr), .exclude_category(exclude_category), .include_group(include_group) ); - cnt++; end while (!instr.has_rd); if (is_zfinx) begin @@ -1564,6 +1664,7 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b // generate load-store instrs - start + use_diff_regs_for_operands = 1; for (int j=0; j Date: Wed, 20 Sep 2023 14:25:33 +0800 Subject: [PATCH 21/27] Fix build errors in xrun and vcs Signed-off-by: bsm --- .../instr_lib/cv32e40p_float_instr_lib.sv | 30 +++++++++++-------- 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv index e54f5d3ebd..c635dada5e 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv @@ -1610,21 +1610,25 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b post_fp_src_is_load_dest = (load_store_option inside {LOAD_ONLY, LOAD_STORE}) ? $urandom_range(1) : 0; if (use_compress_load_store_only) begin - void'(std::randomize(avail_gp_regs[i]) with { - avail_gp_regs[i].size() == 8; - unique{avail_gp_regs[i]}; - foreach (avail_gp_regs[i][j]) { - avail_gp_regs[i][j] inside {[S0:A5]}; + riscv_reg_t rand_avail_gp_regs[]; + riscv_fpr_t rand_avail_fp_regs[]; + void'(std::randomize(rand_avail_gp_regs) with { + rand_avail_gp_regs.size() == 8; + unique{rand_avail_gp_regs}; + foreach (rand_avail_gp_regs[j]) { + rand_avail_gp_regs[j] inside {[S0:A5]}; } }); - void'(std::randomize(avail_fp_regs[i]) with { - avail_fp_regs[i].size() == 8; - // avail_fp_regs[i].size() == 4; // limitation_1 - unique{avail_fp_regs[i]}; - foreach (avail_fp_regs[i][j]) { - avail_fp_regs[i][j] inside {[FS0:FA5]}; + void'(std::randomize(rand_avail_fp_regs) with { + rand_avail_fp_regs.size() == 8; + // rand_avail_fp_regs.size() == 4; // limitation_1 + unique{rand_avail_fp_regs}; + foreach (rand_avail_fp_regs[j]) { + rand_avail_fp_regs[j] inside {[FS0:FA5]}; } }); + avail_gp_regs[i] = rand_avail_gp_regs; + avail_fp_regs[i] = rand_avail_fp_regs; end @@ -1819,10 +1823,12 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b if (q_load_rd.size() != 0) begin : OVERRIDE_USED_LOAD_RD_TO_STORE_SAFEZONE_ADDR q_load_rd.sort(); foreach (q_load_rd[idx]) begin + riscv_reg_t temp_q_load_rd; if (idx != 0) begin if (q_load_rd[idx] == q_load_rd[idx-1]) continue; end - `SET_GPR_VALUE(q_load_rd[idx], F_NEG_ZERO_DIV2); + temp_q_load_rd = q_load_rd[idx]; + `SET_GPR_VALUE(temp_q_load_rd, F_NEG_ZERO_DIV2); end q_load_rd.delete(); end From 2a64dbacb81b31aae9bed3253c16b61a06895ffa Mon Sep 17 00:00:00 2001 From: bsm Date: Fri, 22 Sep 2023 08:43:27 +0800 Subject: [PATCH 22/27] Fix constraint random conflict issue for compress instruction Signed-off-by: bsm --- cv32e40p/env/corev-dv/cv32e40p_instr_gen_config.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cv32e40p/env/corev-dv/cv32e40p_instr_gen_config.sv b/cv32e40p/env/corev-dv/cv32e40p_instr_gen_config.sv index 3bf17af480..20e76ae460 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_instr_gen_config.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_instr_gen_config.sv @@ -123,7 +123,7 @@ class cv32e40p_instr_gen_config extends riscv_instr_gen_config; constraint num_zfinx_reserved_reg_c { if (RV32ZFINX inside {riscv_instr_pkg::supported_isa}) { - num_zfinx_reserved_reg inside {[5:10]}; + num_zfinx_reserved_reg inside {[5:8]}; } else { num_zfinx_reserved_reg == 0; } @@ -135,7 +135,7 @@ class cv32e40p_instr_gen_config extends riscv_instr_gen_config; zfinx_reserved_gpr.size() == num_zfinx_reserved_reg; unique {zfinx_reserved_gpr}; foreach(zfinx_reserved_gpr[i]) { - !(zfinx_reserved_gpr[i] inside {ZERO, RA, SP, GP, TP}); + !(zfinx_reserved_gpr[i] inside {ZERO, RA, SP, GP, TP, S0, S1, A0, A1, A2, A3, A4, A5}); (zfinx_reserved_gpr[i] != dp); (zfinx_reserved_gpr[i] != str_rs1); (zfinx_reserved_gpr[i] != str_rs3); From 8dabb73562856e903989ef190294e0fb5f110778 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 22 Sep 2023 13:27:30 +0800 Subject: [PATCH 23/27] fix hwloop_exception stream removing hwloop illegal instr Signed-off-by: Vaibhav Jain --- .../corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv index dced7e6b06..96f34c45d7 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv @@ -1513,7 +1513,10 @@ class cv32e40p_xpulp_hwloop_exception extends cv32e40p_xpulp_hwloop_base_stream; //Exclude list for all random instruction generation part riscv_exclude_common_instr = {CV_START, CV_STARTI, CV_END, CV_ENDI, CV_COUNT, CV_COUNTI, CV_SETUP, CV_SETUPI, CV_ELW, - JAL, C_J, C_JAL}; + C_ADDI16SP, + WFI, + URET, SRET, MRET, DRET, + JALR, JAL, C_JR, C_JALR, C_J, C_JAL }; super.post_randomize(); this.print(); endfunction : post_randomize @@ -1603,6 +1606,9 @@ class cv32e40p_xpulp_hwloop_exception extends cv32e40p_xpulp_hwloop_base_stream; if(no_compressed) riscv_exclude_group = {riscv_exclude_group, RV32C, RV32FC}; + if(no_branch) + riscv_exclude_instr = {riscv_exclude_instr, BEQ, BNE, BLT, BGE, BLTU, BGEU, C_BEQZ, C_BNEZ, CV_BEQIMM, CV_BNEIMM}; + `uvm_info("cv32e40p_xpulp_hwloop_base_stream", $sformatf("insert_rand_instr- Number of Random instr to generate= %0d",num_rand_instr), UVM_HIGH) From db5baf4ffb928b7e9997bea34ab7323dcaefff2e Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 22 Sep 2023 13:34:42 +0800 Subject: [PATCH 24/27] reduce random hwloop_exception test timeout Signed-off-by: Vaibhav Jain --- cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml | 2 +- cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml index 97a81a4d2d..e85183a593 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml @@ -210,6 +210,6 @@ tests: description: hwloop exception test with single step debug build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=3000000" test_cfg: debug_single_step_en diff --git a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml index 80c5f0312a..289d2032b3 100644 --- a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml +++ b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml @@ -52,7 +52,7 @@ tests: build: uvmt_cv32e40p description: hwloop exception test dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=1000000" corev_rand_pulp_illegal_instr_test: testname: corev_rand_pulp_instr_test From a3eb6da12ab66ad172e65bb6a128aaa5104774c3 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 29 Sep 2023 16:56:43 +0800 Subject: [PATCH 25/27] increase IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS to 14 Signed-off-by: Vaibhav Jain --- cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv index 0fe28e938b..7c9716e8a2 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv @@ -455,8 +455,8 @@ module uvmt_cv32e40p_imperas_dv_wrap // Select processor name void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "CV32E40P")); - // Worst case propagation of events 4 retirements (actually 3 observed) - void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 4)); + // Worst case propagation of events 14 retirements (14 due to long fpu multicycle instr) + void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 14)); // Redirect stdout to parent systemverilog simulator void'(rvviRefConfigSetInt(IDV_CONFIG_REDIRECT_STDOUT, RVVI_TRUE)); From 36e30a1e21413eb00f0bc29eb6c07cd9e0729711 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 29 Sep 2023 16:57:48 +0800 Subject: [PATCH 26/27] reduce loop count range max to 100 and remove branch and fence instr from exception stream Signed-off-by: Vaibhav Jain --- .../instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv index 96f34c45d7..00c70b9d73 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv @@ -154,10 +154,10 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; num_loops_active inside {1,2,3}; foreach(hwloop_counti[i]) - hwloop_counti[i] inside {[0:200]};//TODO: check 0 is valid + hwloop_counti[i] inside {[0:100]};//TODO: check 0 is valid foreach(hwloop_count[i]) - hwloop_count[i] inside {[0:200]};//TODO: check 0 is valid + hwloop_count[i] inside {[0:100]};//TODO: check 0 is valid } constraint num_hwloop_instr_c { @@ -1541,6 +1541,12 @@ class cv32e40p_xpulp_hwloop_exception extends cv32e40p_xpulp_hwloop_base_stream; if(no_compressed) riscv_exclude_group = {riscv_exclude_group, RV32C, RV32FC}; + if(no_branch) + riscv_exclude_instr = {riscv_exclude_instr, BEQ, BNE, BLT, BGE, BLTU, BGEU, C_BEQZ, C_BNEZ, CV_BEQIMM, CV_BNEIMM}; + + if(no_fence) + riscv_exclude_instr = {riscv_exclude_instr, FENCE, FENCE_I}; + riscv_exclude_xpulp = {riscv_exclude_group, RV32X}; //Create and Randomize array for avail_regs each time to ensure randomization @@ -1609,6 +1615,9 @@ class cv32e40p_xpulp_hwloop_exception extends cv32e40p_xpulp_hwloop_base_stream; if(no_branch) riscv_exclude_instr = {riscv_exclude_instr, BEQ, BNE, BLT, BGE, BLTU, BGEU, C_BEQZ, C_BNEZ, CV_BEQIMM, CV_BNEIMM}; + if(no_fence) + riscv_exclude_instr = {riscv_exclude_instr, FENCE, FENCE_I}; + `uvm_info("cv32e40p_xpulp_hwloop_base_stream", $sformatf("insert_rand_instr- Number of Random instr to generate= %0d",num_rand_instr), UVM_HIGH) From b5cb182d83aa91512602039c88fe422ec5ab1a6e Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 29 Sep 2023 16:58:41 +0800 Subject: [PATCH 27/27] set num to 1 for long running corev-dv tests to be moved to a seprate regress list and reduce long timeout Signed-off-by: Vaibhav Jain --- .../regress/cv32e40pv2_interrupt_debug.yaml | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml index e85183a593..0b23a62fcb 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml @@ -25,67 +25,72 @@ tests: build: uvmt_cv32e40p description: corev_rand_debug dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug CFG_PLUSARGS="+UVM_TIMEOUT=2000000" corev_rand_debug_ebreak: build: uvmt_cv32e40p description: corev_rand_debug_ebreak dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_ebreak CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_ebreak CFG_PLUSARGS="+UVM_TIMEOUT=2000000" corev_rand_debug_ebreak_xpulp: build: uvmt_cv32e40p description: corev_rand_debug_ebreak_xpulp dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_ebreak_xpulp CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + num: 1 corev_rand_debug_single_step: build: uvmt_cv32e40p description: corev_rand_debug_single_step dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_single_step CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + num: 1 corev_rand_debug_single_step_xpulp: build: uvmt_cv32e40p description: corev_rand_debug_single_step_xpulp dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_single_step_xpulp CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + num: 1 corev_rand_interrupt: build: uvmt_cv32e40p description: corev_rand_interrupt dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + num: 1 corev_rand_interrupt_debug: build: uvmt_cv32e40p description: corev_rand_interrupt_debug dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_debug CFG_PLUSARGS="+UVM_TIMEOUT=2000000" corev_rand_interrupt_exception: build: uvmt_cv32e40p description: corev_rand_interrupt_exception dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_exception CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_exception CFG_PLUSARGS="+UVM_TIMEOUT=2000000" corev_rand_interrupt_nested: build: uvmt_cv32e40p description: corev_rand_interrupt_nested dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_nested CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + num: 1 corev_rand_interrupt_wfi: build: uvmt_cv32e40p description: corev_rand_interrupt_wfi dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi CFG_PLUSARGS="+UVM_TIMEOUT=2000000" corev_rand_interrupt_wfi_mem_stress: build: uvmt_cv32e40p description: corev_rand_interrupt_wfi_mem_stress dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=2000000" debug_test: build: uvmt_cv32e40p