diff --git a/bin/README.md b/bin/README.md
index 683c616008..3dc8fc3164 100644
--- a/bin/README.md
+++ b/bin/README.md
@@ -89,7 +89,14 @@ Please refer to the help utility of *cv_regress* for more details on the utility
 
 Once regression script is generated, it can be run using the correct tool, either by sourcing the shell script, or as an example using Questa Verification Run Manager:
 
-> vrun -rmdb vsim_ci_check.rmdb -run cv32e40p
+> % vrun -rmdb vsim_ci_check.rmdb -run cv32e40p
+
+
+### CV32E40Pv2 Regression Generator
+
+For cv32e40pv2 project, regressions have been split into 5 files across 7 configurations. An interactive utiliy can be run to customize regression parameters (ISS, coverage collection, simulator...) and generate all files needed, by following the instructions of the script.
+
+> % sh cv32e40pv2_nr_generator.sh
 
 ### Regression YAML Format
 
@@ -115,7 +122,7 @@ tests:<br>
 &nbsp;&nbsp;<*Required*: test label. If using the test only once in the same yaml file, the label can match the *actual* test name><br>
 &nbsp;&nbsp;**test_name0**:<br>
 &nbsp;&nbsp;&nbsp;&nbsp;<*Required*: build dependencies, can be a single build_name, or a list of build_name if **builds** is specified (plural) ><br>
-&nbsp;&nbsp;&nbsp;&nbsp;**build(s)**: \<string> (list of \<string>) <br>
+&nbsp;&nbsp;&nbsp;&nbsp;**build(s)**: \<string> (if plural, a list of \<string>) <br>
 &nbsp;&nbsp;&nbsp;&nbsp;<*Required*: human-readable test description><br>
 &nbsp;&nbsp;&nbsp;&nbsp;**description**: \<string><br>
 &nbsp;&nbsp;&nbsp;&nbsp;<*Required*: make directory for the test><br>
@@ -125,9 +132,9 @@ tests:<br>
 &nbsp;&nbsp;&nbsp;&nbsp;**testname**: \<string><br>
 &nbsp;&nbsp;&nbsp;&nbsp;<*Optional*: A make command to run before running the test(s).  This could be used for gen_* makes for corev-dv<br>
 &nbsp;&nbsp;&nbsp;&nbsp;**precmd**: \<string><br>
-&nbsp;&nbsp;&nbsp;&nbsp;<*Optional*: A specific configuration of the riscv-dv generator to use for this test><br>
-&nbsp;&nbsp;&nbsp;&nbsp;**riscvdv_cfg**: \<string><br>
 &nbsp;&nbsp;&nbsp;&nbsp;<*Required*: make directory for the test><br>
 &nbsp;&nbsp;&nbsp;&nbsp;**cmd**: \<string><br>
 &nbsp;&nbsp;&nbsp;&nbsp;<*Optional*: The number of test iterations to run.  Note that all runs will receive a random seed><br>
-&nbsp;&nbsp;&nbsp;&nbsp;**num**: \<number>
+&nbsp;&nbsp;&nbsp;&nbsp;**num**: \<number><br>
+&nbsp;&nbsp;&nbsp;&nbsp;<*Optional*: a list of configurations or simulators to be skipped for this specific test><br>
+&nbsp;&nbsp;&nbsp;&nbsp;**skip_sim**: \<number><br>
diff --git a/bin/cv32e40pv2_nr_generator.sh b/bin/cv32e40pv2_nr_generator.sh
new file mode 100644
index 0000000000..3ccbf9c694
--- /dev/null
+++ b/bin/cv32e40pv2_nr_generator.sh
@@ -0,0 +1,434 @@
+#!/bin/bash
+
+###############################################################################
+#
+# Copyright 2024 Dolphin Design
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://solderpad.org/licenses/
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+#
+###############################################################################
+# CV32E40Pv2_nr_generator: Execute all the cmds run for CV32E40Pv2 regressions.
+# Auto-customisation to change number of rand jobs, simulator, iss use etc.
+#
+# Usage:
+#       CV32E40Pv2_nr_generator.sh
+#
+###############################################################################
+
+add_sh_cmd_and_check () {
+    basename=$1
+    output_file=$2
+
+
+    echo "
+sh ${basename}.sh > ${regr}.log 2>&1
+fail_count=$(grep -o "Failing tests: [0-9]*" ${regr}.log | grep -o "[0-9]*")
+pass_count=$(grep -o "Passing tests: [0-9]*" ${regr}.log | grep -o "[0-9]*")
+total=$((fail_count + pass_count))
+((tot_fail_count+=fail_count))
+((tot_pass_count+=pass_count))
+" >> $output_file
+
+}
+
+add_rmdb_cmd_and_check () {
+    basename=$1
+    output_file=$2
+    parallel_jobs=$3
+    coverage=$4
+
+    echo "regr=${basename}" >> $output_file
+    echo "nb_jobs=${parallel_jobs}" >> $output_file
+
+
+    echo 'vrun -rmdb ${regr}.rmdb -run cv32e40p -j ${nb_jobs} -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND > ${regr}.log 2>&1' >> $output_file
+
+    if [[ $coverage -eq 1 ]]; then
+        echo "status_section=\$(sed -n '/Test (valid UCDB) status:/,/RegressionCompleted:/p' \${regr}.log | head -n -1)
+ok_count=\$(echo \"\$status_section\" | grep \"Ok \" | sed 's/[^0-9]*//g')
+warning_count=\$(echo \"\$status_section\" | grep \"Warning \" | sed 's/[^0-9]*//g')
+pass_count=\$((ok_count + warning_count))" >> $output_file
+    else
+        echo "status_section=\$(sed -n '/Action script pass\/fail status:/,/RegressionCompleted:/p' \${regr}.log | head -n -1)
+tmp_pass_count=\$(echo \"\$status_section\" | grep \"Passed \" | sed 's/[^0-9]*//g')
+pass_count=\$((tmp_pass_count-3)) " >> $output_file
+    fi
+
+echo "
+fail_count=\$(echo \"\$status_section\" | grep \"Failed \" | sed 's/[^0-9]*//g')
+((tot_fail_count+=fail_count))
+((tot_pass_count+=pass_count))
+total=\$((fail_count + pass_count))
+" >> $output_file
+
+}
+
+
+if [[ -n "${SIMULATOR+x}" ]]; then
+    default_nr_simulator=$SIMULATOR
+else
+    default_nr_simulator=vsim
+fi
+
+default_nr_type=sh
+default_nr_vrun_jobs=10
+default_nr_vrun_lsf_cmd="bsub -K -q long"
+default_nr_vrun_lsf_switch="--lsf \"$default_nr_vrun_lsf_cmd\""
+default_nr_cfgs=(pulp pulp_fpu pulp_fpu_1cyclat pulp_fpu_2cyclat pulp_fpu_zfinx pulp_fpu_zfinx_1cyclat pulp_fpu_zfinx_2cyclat)
+default_nr_use_iss=yes
+default_nr_en_cov=1
+default_nr_xpulp_jobs=200
+default_nr_fpu_jobs=300
+default_nr_dbg_short_jobs=60
+default_nr_dbg_long_jobs=6
+default_nr_legacy_jobs=1
+
+nr_regr=(xpulp_instr fpu_instr interrupt_debug_short interrupt_debug_long legacy_v1)
+
+echo ""
+echo "=================================================================="
+echo "| Here are the default parameters for CV32E40Pv2 full regression "
+echo -e "| SIMULATOR\t\t  = $default_nr_simulator"
+echo -e "| NR_TYPE\t\t  = $default_nr_type"
+echo -e "| CFGs\t\t\t  = ${default_nr_cfgs[*]}"
+echo -e "| USE_ISS\t\t  = $default_nr_use_iss"
+echo -e "| EN_COV\t\t  = $(if [[ $default_nr_en_cov -eq 1 ]]; then echo "yes"; else echo "no"; fi)"
+echo -e "| NB_RAND_DBG_SHORT_TESTS = $default_nr_dbg_short_jobs"
+echo -e "| NB_RAND_DBG_LONG_TESTS  = $default_nr_dbg_long_jobs"
+echo -e "| NB_RAND_PULP_TESTS\t  = $default_nr_xpulp_jobs"
+echo -e "| NB_RAND_FPU_TESTS\t  = $default_nr_fpu_jobs"
+echo -e "| NB_RAND_LEGACY_V1_TESTS = $default_nr_legacy_jobs"
+echo "| "
+echo -n "| Do you want to keep default parameters for CV32E40Pv2 regression ? [Y]/N : "
+read -r default_or_no
+
+default_or_no=${default_or_no,,}
+
+
+
+if [[ -z "$default_or_no" || "$default_or_no" == y* ]]; then
+    nr_simulator=$default_nr_simulator
+    nr_type=$default_nr_type
+    nr_vrun_jobs=$default_nr_vrun_jobs
+    nr_vrun_lsf_cmd=$default_nr_vrun_lsf_cmd
+    nr_vrun_lsf_switch=$default_nr_vrun_lsf_switch
+    nr_cfgs=("${default_nr_cfgs[@]}")
+    nr_use_iss=$default_nr_use_iss
+    nr_en_cov=$default_nr_en_cov
+    nr_xpulp_jobs=$default_nr_xpulp_jobs
+    nr_fpu_jobs=$default_nr_fpu_jobs
+    nr_dbg_short_jobs=$default_nr_dbg_short_jobs
+    nr_dbg_long_jobs=$default_nr_dbg_long_jobs
+    nr_legacy_jobs=$default_nr_legacy_jobs
+else
+    while true; do
+        echo "|"
+
+        #############################
+        ## GET NR_SIMULATOR
+        while true; do
+            echo -n "| Which supported simulator do you want to use ? [Default: $default_nr_simulator] vsim / xrun / vcs : "
+            read -r choice_simulator
+            choice_simulator=${choice_simulator,,}
+            if [[ -z "$choice_simulator" || "$choice_simulator" == vsim ]]; then
+                nr_simulator=$default_nr_simulator
+                break
+            elif [[ "$choice_simulator" == xrun || "$choice_simulator" == vcs ]]; then
+                nr_simulator=$choice_simulator
+                break
+            else
+                echo "| Unknown simulator $choice_simulator, try again"
+            fi
+        done
+
+        #############################
+        ## GET NR_TYPE
+        while true; do
+            echo -n "| Which regression type do you want to use ? [Default: $default_nr_type] sh / rmdb (Questa Vrun) : "
+            read -r choice_type
+            choice_type=${choice_type,,}
+            if [[ -z "$choice_type" || "$choice_type" == sh ]]; then
+                nr_type=$default_nr_type
+                break
+            elif [[ "$choice_type" == rmdb ]]; then
+                nr_type=rmdb
+
+                #############################
+                ## GET NR_VRUN_JOBS
+                while true; do
+                    echo -n "| RMDB (Questa Vrun) Selected. How many // jobs do you want to run ? [Default: $default_nr_vrun_jobs] / NB : "
+                    read -r choice_vrun_jobs
+                    if [[ -z "$choice_vrun_jobs" ]]; then
+                        nr_vrun_jobs=$default_nr_vrun_jobs
+                        break
+                    elif [[ "$choice_vrun_jobs" =~ ^[0-9]+$ ]]; then
+                        nr_vrun_jobs=$choice_vrun_jobs
+                        break
+                    else
+                        echo "Error : invalid entry, enter a number"
+                    fi
+                done
+
+                #############################
+                ## GET NR_VRUN_LSF_CMD
+                while true; do
+                    echo -n "| Do you want to use a LSF grid system ? [Default: Yes with $default_nr_vrun_lsf_cmd] / <Yes, just give any LSF CMD> / No : "
+                    read -r choice_vrun_lsf_cmd
+                    if [[ -z "$choice_vrun_lsf_cmd" ]]; then
+                        nr_vrun_lsf_cmd=$default_nr_vrun_lsf_cmd
+                        break
+                    elif [[ "$choice_vrun_lsf_cmd" =~ bsub ]]; then
+                        nr_vrun_lsf_cmd=$choice_vrun_lsf_cmd
+                        break
+                    fi
+                    choice_vrun_lsf_cmd=${choice_vrun_lsf_cmd,,}
+                    if [[ "$choice_vrun_lsf_cmd" == n* ]]; then
+                        nr_vrun_lsf_cmd=""
+                        break
+                    else
+                        echo "| Answer no if LSF not needed, LSF command expected to start with bsub, try again"
+                    fi
+                done
+
+                break
+
+            else
+                echo "| Unknown regrssion type $choice_type, try again"
+            fi
+        done
+
+        while true; do
+            echo -n "| Pick ONE specific configuration to run or left all ? [A]ll / (see_list_above) : "
+            read -r choice_cfg
+            choice_cfg=${choice_cfg,,}
+            if [[ -z "$choice_cfg" || "$choice_cfg" == a* ]]; then
+                nr_cfgs=("${default_nr_cfgs[@]}")
+                break
+            elif [[ ${default_nr_cfgs[@]} =~ $choice_cfg ]]; then
+                nr_cfgs=( "$choice_cfg" )
+                break
+            else
+                echo "| Unknown cfg $choice_cfg, try again"
+            fi
+        done
+
+        echo -n "| Do you want to use Imperas ISS ? [Y]/N : "
+        read -r choice_use_iss
+        choice_use_iss=${choice_use_iss,,}
+        if [[ -z "$choice_use_iss" || "$choice_use_iss" == y* ]]; then
+            nr_use_iss=yes
+        else
+            nr_use_iss=no
+        fi
+
+        echo -n "| Do you want to Enable Coverage collection ? [Y]/N : "
+        read -r choice_en_cov
+        choice_en_cov=${choice_en_cov,,}
+        if [[ -z "$choice_en_cov" || "$choice_en_cov" == y* ]]; then
+            nr_en_cov=1
+        else
+            nr_en_cov=0
+        fi
+
+        while true; do
+            printf "| %-36s %-25s %-39s |  [%3d] / NB : " "How many random tests should run for" "interrupt & debug (short)" "(cv32e40pv2_interrupt_debug_short.yaml)" $default_nr_dbg_short_jobs
+            read -r choice_dbg_short_jobs
+            if [[ -z "$choice_dbg_short_jobs" ]]; then
+                nr_dbg_short_jobs=$default_nr_dbg_short_jobs
+                break
+            elif [[ "$choice_dbg_short_jobs" =~ ^[0-9]+$ ]]; then
+                nr_dbg_short_jobs=$choice_dbg_short_jobs
+                break
+            else
+                echo "Error : invalid entry, enter a number"
+            fi
+        done
+
+        while true; do
+            printf "| %-36s %-25s %-39s |  [%3d] / NB : " " " "interrupt & debug (long)" "(cv32e40pv2_interrupt_debug_long.yaml)" $default_nr_dbg_long_jobs
+            read -r choice_dbg_long_jobs
+            if [[ -z "$choice_dbg_long_jobs" ]]; then
+                nr_dbg_long_jobs=$default_nr_dbg_long_jobs
+                break
+            elif [[ "$choice_dbg_long_jobs" =~ ^[0-9]+$ ]]; then
+                nr_dbg_long_jobs=$choice_dbg_long_jobs
+                break
+            else
+                echo "Error : invalid entry, enter a number"
+            fi
+        done
+
+        while true; do
+            printf "| %-36s %-25s %-39s |  [%3d] / NB : " " " "XPULP instructions" "(cv32e40pv2_xpulp_instr.yaml)" $default_nr_xpulp_jobs
+            read -r choice_xpulp_jobs
+            if [[ -z "$choice_xpulp_jobs" ]]; then
+                nr_xpulp_jobs=$default_nr_xpulp_jobs
+                break
+            elif [[ "$choice_xpulp_jobs" =~ ^[0-9]+$ ]]; then
+                nr_xpulp_jobs=$choice_xpulp_jobs
+                break
+            else
+                echo "Error : invalid entry, enter a number"
+            fi
+        done
+
+        while true; do
+            printf "| %-36s %-25s %-39s |  [%3d] / NB : " " " "FP instructions" "(cv32e40pv2_fpu_instr.yaml)" $default_nr_fpu_jobs
+            read -r choice_fpu_jobs
+            if [[ -z "$choice_fpu_jobs" ]]; then
+                nr_fpu_jobs=$default_nr_fpu_jobs
+                break
+            elif [[ "$choice_fpu_jobs" =~ ^[0-9]+$ ]]; then
+                nr_fpu_jobs=$choice_fpu_jobs
+                break
+            else
+                echo "Error : invalid entry, enter a number"
+            fi
+        done
+
+        while true; do
+            printf "| %-36s %-25s %-39s |  [%3d] / NB : " " " "legacy v1 tests" "(cv32e40pv2_legacy_v1.yaml)" $default_nr_legacy_jobs
+            read -r choice_legacy
+            if [[ -z "$choice_legacy" ]]; then
+                nr_legacy_jobs=$default_nr_legacy_jobs
+                break
+            elif [[ "$choice_legacy" =~ ^[0-9]+$ ]]; then
+                nr_legacy_jobs=$choice_legacy
+                break
+            else
+                echo "Error : invalid entry, enter a number"
+            fi
+        done
+
+        echo "|"
+        echo "|"
+        echo "| Here are your selected parameters for CV32E40Pv2 regression "
+        echo -e "| SIMULATOR\t\t  = $nr_simulator"
+        echo -e "| NR_TYPE\t\t  = $nr_type $(if [[ $nr_type -eq vrun ]]; then echo "$nr_vrun_jobs // jobs | LSF command : $nr_vrun_lsf_cmd"; fi)"
+        echo -e "| CFGs\t\t\t  = ${nr_cfgs[*]}"
+        echo -e "| USE_ISS\t\t  = $nr_use_iss"
+        echo -e "| EN_COV\t\t  = $(if [[ $nr_en_cov -eq 1 ]]; then echo "yes"; else echo "no"; fi)"
+        echo -e "| NB_RAND_DBG_SHORT_TESTS = $nr_dbg_short_jobs"
+        echo -e "| NB_RAND_DBG_LONG_TESTS  = $nr_dbg_long_jobs"
+        echo -e "| NB_RAND_PULP_TESTS\t  = $nr_xpulp_jobs"
+        echo -e "| NB_RAND_FPU_TESTS\t  = $nr_fpu_jobs"
+        echo -e "| NB_RAND_LEGACY_V1_TESTS = $nr_legacy_jobs"
+        echo "| "
+        echo -n "| Would you like to generate regressions with these parameters ? [Y]/N/Default : "
+        read -r yes_or_no
+
+        yes_or_no=${yes_or_no,,}
+        if [[ -z "$yes_or_no" || "$yes_or_no" == y* ]]; then
+            break
+        fi
+        if [[ "$yes_or_no" == d* ]]; then
+            nr_simulator=$default_nr_simulator
+            nr_type=$default_nr_type
+            nr_cfgs=("${default_nr_cfgs[@]}")
+            nr_use_iss=$default_nr_use_iss
+            nr_en_cov=$default_nr_en_cov
+            nr_xpulp_jobs=$default_nr_xpulp_jobs
+            nr_fpu_jobs=$default_nr_fpu_jobs
+            nr_dbg_short_jobs=$default_nr_dbg_short_jobs
+            nr_dbg_long_jobs=$default_nr_dbg_long_jobs
+            nr_legacy_jobs=$default_nr_legacy_jobs
+            echo "|"
+            echo "| Resetting all parameters to default"
+            echo "|"
+            break
+        fi
+        echo "|"
+    done
+fi
+
+echo "|"
+
+nr_jobs=( $nr_xpulp_jobs $nr_fpu_jobs $nr_dbg_short_jobs $nr_dbg_long_jobs $nr_legacy_jobs )
+
+nr_tst_cfgs=(
+    "disable_all_trn_logs"
+    "disable_all_trn_logs,floating_pt_instr_en"
+    "disable_all_trn_logs,floating_pt_instr_en"
+    "disable_all_trn_logs,floating_pt_instr_en"
+    "disable_all_trn_logs,floating_pt_zfinx_instr_en"
+    "disable_all_trn_logs,floating_pt_zfinx_instr_en"
+    "disable_all_trn_logs,floating_pt_zfinx_instr_en"
+)
+
+mkdir -p all_nrs
+
+echo "#!/bin/bash" > start_all_nr.sh
+echo "tot_fail_count=0" >> start_all_nr.sh
+echo "tot_pass_count=0" >> start_all_nr.sh
+echo "cd all_nrs" >> start_all_nr.sh
+
+for idx in "${!default_nr_cfgs[@]}"; do
+    if [[ ${nr_cfgs[@]} =~ "${default_nr_cfgs[idx]}" ]]; then
+        cfg="${default_nr_cfgs[idx]}"
+        echo "| Generating configuration $cfg "
+        echo -e "\n" >> start_all_nr.sh
+        echo "echo -e \"\n----> Starting configuration $cfg at \$(date \"+%Y-%m-%d %H:%M:%S\")\"" >> start_all_nr.sh
+        mkdir -p all_nrs/$cfg
+        echo "cd $cfg" >> start_all_nr.sh
+        for jdx in "${!nr_regr[@]}"; do
+            jobs="${nr_jobs[jdx]}"
+            regr="${nr_regr[jdx]}"
+            tst_cfg="${nr_tst_cfgs[idx]}"
+            if [[ $cfg == pulp && $regr == fpu_instr ]]; then
+                continue
+            fi
+            ./cv_regress --${nr_type} --file=cv32e40pv2_${regr}.yaml --simulator=$nr_simulator --outfile=${regr}.${nr_type} --num=$jobs --iss $nr_use_iss $(if [[ $nr_en_cov -eq 1 ]]; then echo "--cov"; else echo ""; fi) --cfg $cfg --add_test_cfg $tst_cfg $(if [[ -n $nr_vrun_lsf_cmd && $nr_type -eq rmdb ]]; then echo "--lsf $nr_vrun_lsf_cmd"; else echo ""; fi) 1> /dev/null
+            mv -f ${regr}.${nr_type} all_nrs/${cfg}/.
+            printf "| \t Generated %-21s into : all_nrs/${cfg}/${regr}.${nr_type} \n" "$regr"
+            echo "" >> start_all_nr.sh
+            echo "echo -e \"--> Starting ${regr} at \$(date \"+%Y-%m-%d %H:%M:%S\")\"" >> start_all_nr.sh
+
+            add_${nr_type}_cmd_and_check ${regr} start_all_nr.sh $nr_vrun_jobs $nr_en_cov
+
+            echo "echo -n \"--> Finished ${regr} at \$(date \"+%Y-%m-%d %H:%M:%S\")\"" >> start_all_nr.sh
+            echo 'echo " : [ $pass_count | $total ]  ( $fail_count Failed, see ${regr}.log ) "' >> start_all_nr.sh
+            # echo -e "| \t sh ${cfg}_${regr}.sh >2 /dev/null"
+        done
+        echo "echo -e \"--> Finished ${cfg} at \$(date \"+%Y-%m-%d %H:%M:%S\")\"" >> start_all_nr.sh
+
+        echo "cd .." >> start_all_nr.sh
+    fi
+done
+
+echo "echo \"\"" >> start_all_nr.sh
+echo "echo \"=======================================================\"" >> start_all_nr.sh
+echo "echo \"Total Passing tests: \${tot_pass_count}\"" >> start_all_nr.sh
+echo "echo \"Total Failing tests: \${tot_fail_count}\"" >> start_all_nr.sh
+echo "echo \"=======================================================\"" >> start_all_nr.sh
+echo "echo \"\"" >> start_all_nr.sh
+
+echo "|"
+echo "| Generation done."
+echo "|"
+
+echo -n "| Do you want to start the whole regression now ? Y/[N] : "
+read -r choice_nr
+choice_nr=${choice_nr,,}
+if [[ -z "$choice_nr" || "$choice_nr" == n* ]]; then
+    echo "| You can run the script using this command to execute the whole regression later: sh start_all_nr.sh "
+    echo "| Bye !"
+    exit 0
+else
+
+    echo "|"
+    time sh start_all_nr.sh
+    echo ""
+    echo "|"
+fi
diff --git a/bin/cv_regress b/bin/cv_regress
index 684b54155f..e5d9001e52 100755
--- a/bin/cv_regress
+++ b/bin/cv_regress
@@ -228,8 +228,18 @@ except KeyError:
 DEFAULT_CFG = 'default'
 DEFAULT_PARALLEL = '30'
 
-logging.basicConfig(level=logging.INFO)
 logger = logging.getLogger(__name__)
+logger.setLevel(logging.INFO)
+
+stdout_handler = cv_regression.InfoDebugStreamHandler(sys.stdout)
+stderr_handler = cv_regression.WarningErrorStreamHandler(sys.stderr)
+
+formatter = logging.Formatter(logging.BASIC_FORMAT)
+stdout_handler.setFormatter(formatter)
+stderr_handler.setFormatter(formatter)
+
+logger.addHandler(stdout_handler)
+logger.addHandler(stderr_handler)
 
 parser = argparse.ArgumentParser(formatter_class=argparse.ArgumentDefaultsHelpFormatter)
 parser.add_argument('-f', '--file', action='append', help='One or more input regression YAML lists to read')
@@ -258,6 +268,7 @@ args = parser.parse_args()
 
 if args.debug:
     logger.setLevel(logging.DEBUG)
+    stdout_handler.setLevel(logging.DEBUG)
 
 # Validate arguments
 if not args.file:
diff --git a/bin/lib/cv_regression.py b/bin/lib/cv_regression.py
index 4dea5aeaf9..487059a575 100644
--- a/bin/lib/cv_regression.py
+++ b/bin/lib/cv_regression.py
@@ -23,6 +23,7 @@
 import sys
 import logging
 from collections import OrderedDict
+from logging import StreamHandler
 
 logger = logging.getLogger(__name__)
 
@@ -173,3 +174,20 @@ def get_tests_of_build(self, build):
 
         tests = [t for t in self.tests.values() if build in t.builds]
         return tests
+
+
+class InfoDebugStreamHandler(StreamHandler):
+    def __init__(self, stream=None):
+        StreamHandler.__init__(self, stream)
+
+    def emit(self, record):
+        if record.levelno <= logging.INFO:
+            StreamHandler.emit(self, record)
+
+class WarningErrorStreamHandler(StreamHandler):
+    def __init__(self, stream=None):
+        StreamHandler.__init__(self, stream)
+
+    def emit(self, record):
+        if record.levelno > logging.INFO:
+            StreamHandler.emit(self, record)
diff --git a/cv32e40p/docs/CV32E40Pv2_full_nr.sh b/cv32e40p/docs/CV32E40Pv2_full_nr.sh
new file mode 100755
index 0000000000..5877b47501
--- /dev/null
+++ b/cv32e40p/docs/CV32E40Pv2_full_nr.sh
@@ -0,0 +1,187 @@
+#!/bin/bash
+
+###############################################################################
+#
+# Copyright 2024 Dolphin Design
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://solderpad.org/licenses/
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+#
+###############################################################################
+#
+# CV32E40Pv2_full_nr: lists the needed commands to reproduce the NR as performed
+# by dolphin design team suring CV32E40Pv2 verification, using shell script only
+# For the closest reproduction, consider using CV32E40Pv2_full_nr_questa_vrun.sh
+#
+# Usage:
+#       To reproduce the full NR, simply execute:
+#           sh CV32E40Pv2_full_nr.sh
+#
+#       OR
+#
+#       pick one "./cv_regress ..." line to run it in a terminal inside the
+#       bin folder to generate your own sub-regress file if only one
+#       config/regress file combo is desired
+#
+# - CV_VERIF_PATH (core-v-verif root path) should be defined before running this script
+# - All needed tools should be sourced before running the script
+# (simulator, imperas ISS, etc.)
+#
+###############################################################################
+
+if [[ -z "${CV_VERIF_PATH-}" ]]; then
+    echo "CV_VERIF_PATH does not exist. Set CV_VERIF_PATH environment variable to your core-v-verif root directory and re-run again. Abort."
+    exit 1
+fi
+
+pushd ${CV_VERIF_PATH}/bin > /dev/null
+
+# CFG pulp | NR File xpulp_instr
+./cv_regress --sh --file=cv32e40pv2_xpulp_instr.yaml --simulator=vsim --outfile=pulp_xpulp_instr.sh --num=200 --iss yes --cov --cfg pulp --add_test_cfg disable_all_trn_logs
+sh pulp_xpulp_instr.sh
+
+# CFG pulp | NR File interrupt_debug_short
+./cv_regress --sh --file=cv32e40pv2_interrupt_debug_short.yaml --simulator=vsim --outfile=pulp_interrupt_debug_short.sh --num=60 --iss yes --cov --cfg pulp --add_test_cfg disable_all_trn_logs
+sh pulp_interrupt_debug_short.sh
+
+# CFG pulp | NR File interrupt_debug_long
+./cv_regress --sh --file=cv32e40pv2_interrupt_debug_long.yaml --simulator=vsim --outfile=pulp_interrupt_debug_long.sh --num=6 --iss yes --cov --cfg pulp --add_test_cfg disable_all_trn_logs
+sh pulp_interrupt_debug_long.sh
+
+# CFG pulp | NR File legacy_v1
+./cv_regress --sh --file=cv32e40pv2_legacy_v1.yaml --simulator=vsim --outfile=pulp_legacy_v1.sh --num=1 --iss yes --cov --cfg pulp --add_test_cfg disable_all_trn_logs
+sh pulp_legacy_v1.sh
+
+# CFG pulp_fpu | NR File xpulp_instr
+./cv_regress --sh --file=cv32e40pv2_xpulp_instr.yaml --simulator=vsim --outfile=pulp_fpu_xpulp_instr.sh --num=200 --iss yes --cov --cfg pulp_fpu --add_test_cfg disable_all_trn_logs,floating_pt_instr_en
+sh pulp_fpu_xpulp_instr.sh
+
+# CFG pulp_fpu | NR File fpu_instr
+./cv_regress --sh --file=cv32e40pv2_fpu_instr.yaml --simulator=vsim --outfile=pulp_fpu_fpu_instr.sh --num=300 --iss yes --cov --cfg pulp_fpu --add_test_cfg disable_all_trn_logs,floating_pt_instr_en
+sh pulp_fpu_fpu_instr.sh
+
+# CFG pulp_fpu | NR File interrupt_debug_short
+./cv_regress --sh --file=cv32e40pv2_interrupt_debug_short.yaml --simulator=vsim --outfile=pulp_fpu_interrupt_debug_short.sh --num=60 --iss yes --cov --cfg pulp_fpu --add_test_cfg disable_all_trn_logs,floating_pt_instr_en
+sh pulp_fpu_interrupt_debug_short.sh
+
+# CFG pulp_fpu | NR File interrupt_debug_long
+./cv_regress --sh --file=cv32e40pv2_interrupt_debug_long.yaml --simulator=vsim --outfile=pulp_fpu_interrupt_debug_long.sh --num=6 --iss yes --cov --cfg pulp_fpu --add_test_cfg disable_all_trn_logs,floating_pt_instr_en
+sh pulp_fpu_interrupt_debug_long.sh
+
+# CFG pulp_fpu | NR File legacy_v1
+./cv_regress --sh --file=cv32e40pv2_legacy_v1.yaml --simulator=vsim --outfile=pulp_fpu_legacy_v1.sh --num=1 --iss yes --cov --cfg pulp_fpu --add_test_cfg disable_all_trn_logs,floating_pt_instr_en
+sh pulp_fpu_legacy_v1.sh
+
+# CFG pulp_fpu_1cyclat | NR File xpulp_instr
+./cv_regress --sh --file=cv32e40pv2_xpulp_instr.yaml --simulator=vsim --outfile=pulp_fpu_1cyclat_xpulp_instr.sh --num=200 --iss yes --cov --cfg pulp_fpu_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en
+sh pulp_fpu_1cyclat_xpulp_instr.sh
+
+# CFG pulp_fpu_1cyclat | NR File fpu_instr
+./cv_regress --sh --file=cv32e40pv2_fpu_instr.yaml --simulator=vsim --outfile=pulp_fpu_1cyclat_fpu_instr.sh --num=300 --iss yes --cov --cfg pulp_fpu_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en
+sh pulp_fpu_1cyclat_fpu_instr.sh
+
+# CFG pulp_fpu_1cyclat | NR File interrupt_debug_short
+./cv_regress --sh --file=cv32e40pv2_interrupt_debug_short.yaml --simulator=vsim --outfile=pulp_fpu_1cyclat_interrupt_debug_short.sh --num=60 --iss yes --cov --cfg pulp_fpu_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en
+sh pulp_fpu_1cyclat_interrupt_debug_short.sh
+
+# CFG pulp_fpu_1cyclat | NR File interrupt_debug_long
+./cv_regress --sh --file=cv32e40pv2_interrupt_debug_long.yaml --simulator=vsim --outfile=pulp_fpu_1cyclat_interrupt_debug_long.sh --num=6 --iss yes --cov --cfg pulp_fpu_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en
+sh pulp_fpu_1cyclat_interrupt_debug_long.sh
+
+# CFG pulp_fpu_1cyclat | NR File legacy_v1
+./cv_regress --sh --file=cv32e40pv2_legacy_v1.yaml --simulator=vsim --outfile=pulp_fpu_1cyclat_legacy_v1.sh --num=1 --iss yes --cov --cfg pulp_fpu_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en
+sh pulp_fpu_1cyclat_legacy_v1.sh
+
+# CFG pulp_fpu_2cyclat | NR File xpulp_instr
+./cv_regress --sh --file=cv32e40pv2_xpulp_instr.yaml --simulator=vsim --outfile=pulp_fpu_2cyclat_xpulp_instr.sh --num=200 --iss yes --cov --cfg pulp_fpu_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en
+sh pulp_fpu_2cyclat_xpulp_instr.sh
+
+# CFG pulp_fpu_2cyclat | NR File fpu_instr
+./cv_regress --sh --file=cv32e40pv2_fpu_instr.yaml --simulator=vsim --outfile=pulp_fpu_2cyclat_fpu_instr.sh --num=300 --iss yes --cov --cfg pulp_fpu_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en
+sh pulp_fpu_2cyclat_fpu_instr.sh
+
+# CFG pulp_fpu_2cyclat | NR File interrupt_debug_short
+./cv_regress --sh --file=cv32e40pv2_interrupt_debug_short.yaml --simulator=vsim --outfile=pulp_fpu_2cyclat_interrupt_debug_short.sh --num=60 --iss yes --cov --cfg pulp_fpu_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en
+sh pulp_fpu_2cyclat_interrupt_debug_short.sh
+
+# CFG pulp_fpu_2cyclat | NR File interrupt_debug_long
+./cv_regress --sh --file=cv32e40pv2_interrupt_debug_long.yaml --simulator=vsim --outfile=pulp_fpu_2cyclat_interrupt_debug_long.sh --num=6 --iss yes --cov --cfg pulp_fpu_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en
+sh pulp_fpu_2cyclat_interrupt_debug_long.sh
+
+# CFG pulp_fpu_2cyclat | NR File legacy_v1
+./cv_regress --sh --file=cv32e40pv2_legacy_v1.yaml --simulator=vsim --outfile=pulp_fpu_2cyclat_legacy_v1.sh --num=1 --iss yes --cov --cfg pulp_fpu_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en
+sh pulp_fpu_2cyclat_legacy_v1.sh
+
+# CFG pulp_fpu_zfinx | NR File xpulp_instr
+./cv_regress --sh --file=cv32e40pv2_xpulp_instr.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_xpulp_instr.sh --num=200 --iss yes --cov --cfg pulp_fpu_zfinx --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en
+sh pulp_fpu_zfinx_xpulp_instr.sh
+
+# CFG pulp_fpu_zfinx | NR File fpu_instr
+./cv_regress --sh --file=cv32e40pv2_fpu_instr.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_fpu_instr.sh --num=300 --iss yes --cov --cfg pulp_fpu_zfinx --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en
+sh pulp_fpu_zfinx_fpu_instr.sh
+
+# CFG pulp_fpu_zfinx | NR File interrupt_debug_short
+./cv_regress --sh --file=cv32e40pv2_interrupt_debug_short.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_interrupt_debug_short.sh --num=60 --iss yes --cov --cfg pulp_fpu_zfinx --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en
+sh pulp_fpu_zfinx_interrupt_debug_short.sh
+
+# CFG pulp_fpu_zfinx | NR File interrupt_debug_long
+./cv_regress --sh --file=cv32e40pv2_interrupt_debug_long.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_interrupt_debug_long.sh --num=6 --iss yes --cov --cfg pulp_fpu_zfinx --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en
+sh pulp_fpu_zfinx_interrupt_debug_long.sh
+
+# CFG pulp_fpu_zfinx | NR File legacy_v1
+./cv_regress --sh --file=cv32e40pv2_legacy_v1.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_legacy_v1.sh --num=1 --iss yes --cov --cfg pulp_fpu_zfinx --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en
+sh pulp_fpu_zfinx_legacy_v1.sh
+
+# CFG pulp_fpu_zfinx_1cyclat | NR File xpulp_instr
+./cv_regress --sh --file=cv32e40pv2_xpulp_instr.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_1cyclat_xpulp_instr.sh --num=200 --iss yes --cov --cfg pulp_fpu_zfinx_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en
+sh pulp_fpu_zfinx_1cyclat_xpulp_instr.sh
+
+# CFG pulp_fpu_zfinx_1cyclat | NR File fpu_instr
+./cv_regress --sh --file=cv32e40pv2_fpu_instr.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_1cyclat_fpu_instr.sh --num=300 --iss yes --cov --cfg pulp_fpu_zfinx_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en
+sh pulp_fpu_zfinx_1cyclat_fpu_instr.sh
+
+# CFG pulp_fpu_zfinx_1cyclat | NR File interrupt_debug_short
+./cv_regress --sh --file=cv32e40pv2_interrupt_debug_short.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_1cyclat_interrupt_debug_short.sh --num=60 --iss yes --cov --cfg pulp_fpu_zfinx_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en
+sh pulp_fpu_zfinx_1cyclat_interrupt_debug_short.sh
+
+# CFG pulp_fpu_zfinx_1cyclat | NR File interrupt_debug_long
+./cv_regress --sh --file=cv32e40pv2_interrupt_debug_long.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_1cyclat_interrupt_debug_long.sh --num=6 --iss yes --cov --cfg pulp_fpu_zfinx_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en
+sh pulp_fpu_zfinx_1cyclat_interrupt_debug_long.sh
+
+# CFG pulp_fpu_zfinx_1cyclat | NR File legacy_v1
+./cv_regress --sh --file=cv32e40pv2_legacy_v1.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_1cyclat_legacy_v1.sh --num=1 --iss yes --cov --cfg pulp_fpu_zfinx_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en
+sh pulp_fpu_zfinx_1cyclat_legacy_v1.sh
+
+# CFG pulp_fpu_zfinx_2cyclat | NR File xpulp_instr
+./cv_regress --sh --file=cv32e40pv2_xpulp_instr.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_2cyclat_xpulp_instr.sh --num=200 --iss yes --cov --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en
+sh pulp_fpu_zfinx_2cyclat_xpulp_instr.sh
+
+# CFG pulp_fpu_zfinx_2cyclat | NR File fpu_instr
+./cv_regress --sh --file=cv32e40pv2_fpu_instr.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_2cyclat_fpu_instr.sh --num=300 --iss yes --cov --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en
+sh pulp_fpu_zfinx_2cyclat_fpu_instr.sh
+
+# CFG pulp_fpu_zfinx_2cyclat | NR File interrupt_debug_short
+./cv_regress --sh --file=cv32e40pv2_interrupt_debug_short.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_2cyclat_interrupt_debug_short.sh --num=60 --iss yes --cov --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en
+sh pulp_fpu_zfinx_2cyclat_interrupt_debug_short.sh
+
+# CFG pulp_fpu_zfinx_2cyclat | NR File interrupt_debug_long
+./cv_regress --sh --file=cv32e40pv2_interrupt_debug_long.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_2cyclat_interrupt_debug_long.sh --num=6 --iss yes --cov --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en
+sh pulp_fpu_zfinx_2cyclat_interrupt_debug_long.sh
+
+# CFG pulp_fpu_zfinx_2cyclat | NR File legacy_v1
+./cv_regress --sh --file=cv32e40pv2_legacy_v1.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_2cyclat_legacy_v1.sh --num=1 --iss yes --cov --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en
+sh pulp_fpu_zfinx_2cyclat_legacy_v1.sh
+
+
+popd > /dev/null
diff --git a/cv32e40p/docs/CV32E40Pv2_full_nr_questa_vrun.sh b/cv32e40p/docs/CV32E40Pv2_full_nr_questa_vrun.sh
new file mode 100755
index 0000000000..f870930d1d
--- /dev/null
+++ b/cv32e40p/docs/CV32E40Pv2_full_nr_questa_vrun.sh
@@ -0,0 +1,194 @@
+#!/bin/bash
+
+###############################################################################
+#
+# Copyright 2024 Dolphin Design
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://solderpad.org/licenses/
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+#
+###############################################################################
+#
+# CV32E40Pv2_full_nr_questa_vrun: lists the needed commands to reproduce the NR
+# as performed by dolphin design team during CV32E40Pv2 verification, by using
+# Questa VRUN
+#
+# Usage:
+#       To reproduce the full NR, simply execute:
+#           sh CV32E40Pv2_full_nr_questa_vrun.sh
+#
+#       OR
+#
+#       pick one "./cv_regress ..." line to run it in a terminal inside the
+#       bin folder to generate your own sub-regress file if only one
+#       config/regress file combo is desired
+#
+# Required:
+# - CV_VERIF_PATH (core-v-verif root path) should be defined before running this script
+# - All needed tools should be sourced before running the script
+# (simulator, imperas ISS, etc.)
+# - A LSF grid system available, with a queue named "long" (change LSF_QUEUE value if not)
+# - You can change the number of parallel jobs to run in questa by updating the value of
+#   NB_JOBS below
+#
+###############################################################################
+
+if [[ -z "${CV_VERIF_PATH-}" ]]; then
+    echo "CV_VERIF_PATH does not exist. Set CV_VERIF_PATH environment variable to your core-v-verif root directory and re-run again. Abort."
+    exit 1
+fi
+
+pushd ${CV_VERIF_PATH}/bin > /dev/null
+
+LSF_QUEUE=long
+NB_JOBS=10
+
+# CFG pulp | NR File xpulp_instr
+./cv_regress --rmdb --file=cv32e40pv2_xpulp_instr.yaml --simulator=vsim --outfile=pulp_xpulp_instr.rmdb --num=200 --iss yes --cov --cfg pulp --add_test_cfg disable_all_trn_logs --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_xpulp_instr.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp | NR File interrupt_debug_short
+./cv_regress --rmdb --file=cv32e40pv2_interrupt_debug_short.yaml --simulator=vsim --outfile=pulp_interrupt_debug_short.rmdb --num=60 --iss yes --cov --cfg pulp --add_test_cfg disable_all_trn_logs --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_interrupt_debug_short.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp | NR File interrupt_debug_long
+./cv_regress --rmdb --file=cv32e40pv2_interrupt_debug_long.yaml --simulator=vsim --outfile=pulp_interrupt_debug_long.rmdb --num=6 --iss yes --cov --cfg pulp --add_test_cfg disable_all_trn_logs --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_interrupt_debug_long.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp | NR File legacy_v1
+./cv_regress --rmdb --file=cv32e40pv2_legacy_v1.yaml --simulator=vsim --outfile=pulp_legacy_v1.rmdb --num=1 --iss yes --cov --cfg pulp --add_test_cfg disable_all_trn_logs --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_legacy_v1.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu | NR File xpulp_instr
+./cv_regress --rmdb --file=cv32e40pv2_xpulp_instr.yaml --simulator=vsim --outfile=pulp_fpu_xpulp_instr.rmdb --num=200 --iss yes --cov --cfg pulp_fpu --add_test_cfg disable_all_trn_logs,floating_pt_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_xpulp_instr.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu | NR File fpu_instr
+./cv_regress --rmdb --file=cv32e40pv2_fpu_instr.yaml --simulator=vsim --outfile=pulp_fpu_fpu_instr.rmdb --num=300 --iss yes --cov --cfg pulp_fpu --add_test_cfg disable_all_trn_logs,floating_pt_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_fpu_instr.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu | NR File interrupt_debug_short
+./cv_regress --rmdb --file=cv32e40pv2_interrupt_debug_short.yaml --simulator=vsim --outfile=pulp_fpu_interrupt_debug_short.rmdb --num=60 --iss yes --cov --cfg pulp_fpu --add_test_cfg disable_all_trn_logs,floating_pt_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_interrupt_debug_short.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu | NR File interrupt_debug_long
+./cv_regress --rmdb --file=cv32e40pv2_interrupt_debug_long.yaml --simulator=vsim --outfile=pulp_fpu_interrupt_debug_long.rmdb --num=6 --iss yes --cov --cfg pulp_fpu --add_test_cfg disable_all_trn_logs,floating_pt_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_interrupt_debug_long.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu | NR File legacy_v1
+./cv_regress --rmdb --file=cv32e40pv2_legacy_v1.yaml --simulator=vsim --outfile=pulp_fpu_legacy_v1.rmdb --num=1 --iss yes --cov --cfg pulp_fpu --add_test_cfg disable_all_trn_logs,floating_pt_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_legacy_v1.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_1cyclat | NR File xpulp_instr
+./cv_regress --rmdb --file=cv32e40pv2_xpulp_instr.yaml --simulator=vsim --outfile=pulp_fpu_1cyclat_xpulp_instr.rmdb --num=200 --iss yes --cov --cfg pulp_fpu_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_1cyclat_xpulp_instr.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_1cyclat | NR File fpu_instr
+./cv_regress --rmdb --file=cv32e40pv2_fpu_instr.yaml --simulator=vsim --outfile=pulp_fpu_1cyclat_fpu_instr.rmdb --num=300 --iss yes --cov --cfg pulp_fpu_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_1cyclat_fpu_instr.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_1cyclat | NR File interrupt_debug_short
+./cv_regress --rmdb --file=cv32e40pv2_interrupt_debug_short.yaml --simulator=vsim --outfile=pulp_fpu_1cyclat_interrupt_debug_short.rmdb --num=60 --iss yes --cov --cfg pulp_fpu_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_1cyclat_interrupt_debug_short.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_1cyclat | NR File interrupt_debug_long
+./cv_regress --rmdb --file=cv32e40pv2_interrupt_debug_long.yaml --simulator=vsim --outfile=pulp_fpu_1cyclat_interrupt_debug_long.rmdb --num=6 --iss yes --cov --cfg pulp_fpu_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_1cyclat_interrupt_debug_long.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_1cyclat | NR File legacy_v1
+./cv_regress --rmdb --file=cv32e40pv2_legacy_v1.yaml --simulator=vsim --outfile=pulp_fpu_1cyclat_legacy_v1.rmdb --num=1 --iss yes --cov --cfg pulp_fpu_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_1cyclat_legacy_v1.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_2cyclat | NR File xpulp_instr
+./cv_regress --rmdb --file=cv32e40pv2_xpulp_instr.yaml --simulator=vsim --outfile=pulp_fpu_2cyclat_xpulp_instr.rmdb --num=200 --iss yes --cov --cfg pulp_fpu_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_2cyclat_xpulp_instr.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_2cyclat | NR File fpu_instr
+./cv_regress --rmdb --file=cv32e40pv2_fpu_instr.yaml --simulator=vsim --outfile=pulp_fpu_2cyclat_fpu_instr.rmdb --num=300 --iss yes --cov --cfg pulp_fpu_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_2cyclat_fpu_instr.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_2cyclat | NR File interrupt_debug_short
+./cv_regress --rmdb --file=cv32e40pv2_interrupt_debug_short.yaml --simulator=vsim --outfile=pulp_fpu_2cyclat_interrupt_debug_short.rmdb --num=60 --iss yes --cov --cfg pulp_fpu_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_2cyclat_interrupt_debug_short.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_2cyclat | NR File interrupt_debug_long
+./cv_regress --rmdb --file=cv32e40pv2_interrupt_debug_long.yaml --simulator=vsim --outfile=pulp_fpu_2cyclat_interrupt_debug_long.rmdb --num=6 --iss yes --cov --cfg pulp_fpu_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_2cyclat_interrupt_debug_long.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_2cyclat | NR File legacy_v1
+./cv_regress --rmdb --file=cv32e40pv2_legacy_v1.yaml --simulator=vsim --outfile=pulp_fpu_2cyclat_legacy_v1.rmdb --num=1 --iss yes --cov --cfg pulp_fpu_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_2cyclat_legacy_v1.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_zfinx | NR File xpulp_instr
+./cv_regress --rmdb --file=cv32e40pv2_xpulp_instr.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_xpulp_instr.rmdb --num=200 --iss yes --cov --cfg pulp_fpu_zfinx --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_zfinx_xpulp_instr.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_zfinx | NR File fpu_instr
+./cv_regress --rmdb --file=cv32e40pv2_fpu_instr.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_fpu_instr.rmdb --num=300 --iss yes --cov --cfg pulp_fpu_zfinx --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_zfinx_fpu_instr.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_zfinx | NR File interrupt_debug_short
+./cv_regress --rmdb --file=cv32e40pv2_interrupt_debug_short.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_interrupt_debug_short.rmdb --num=60 --iss yes --cov --cfg pulp_fpu_zfinx --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_zfinx_interrupt_debug_short.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_zfinx | NR File interrupt_debug_long
+./cv_regress --rmdb --file=cv32e40pv2_interrupt_debug_long.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_interrupt_debug_long.rmdb --num=6 --iss yes --cov --cfg pulp_fpu_zfinx --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_zfinx_interrupt_debug_long.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_zfinx | NR File legacy_v1
+./cv_regress --rmdb --file=cv32e40pv2_legacy_v1.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_legacy_v1.rmdb --num=1 --iss yes --cov --cfg pulp_fpu_zfinx --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_zfinx_legacy_v1.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_zfinx_1cyclat | NR File xpulp_instr
+./cv_regress --rmdb --file=cv32e40pv2_xpulp_instr.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_1cyclat_xpulp_instr.rmdb --num=200 --iss yes --cov --cfg pulp_fpu_zfinx_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_zfinx_1cyclat_xpulp_instr.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_zfinx_1cyclat | NR File fpu_instr
+./cv_regress --rmdb --file=cv32e40pv2_fpu_instr.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_1cyclat_fpu_instr.rmdb --num=300 --iss yes --cov --cfg pulp_fpu_zfinx_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_zfinx_1cyclat_fpu_instr.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_zfinx_1cyclat | NR File interrupt_debug_short
+./cv_regress --rmdb --file=cv32e40pv2_interrupt_debug_short.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_1cyclat_interrupt_debug_short.rmdb --num=60 --iss yes --cov --cfg pulp_fpu_zfinx_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_zfinx_1cyclat_interrupt_debug_short.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_zfinx_1cyclat | NR File interrupt_debug_long
+./cv_regress --rmdb --file=cv32e40pv2_interrupt_debug_long.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_1cyclat_interrupt_debug_long.rmdb --num=6 --iss yes --cov --cfg pulp_fpu_zfinx_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_zfinx_1cyclat_interrupt_debug_long.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_zfinx_1cyclat | NR File legacy_v1
+./cv_regress --rmdb --file=cv32e40pv2_legacy_v1.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_1cyclat_legacy_v1.rmdb --num=1 --iss yes --cov --cfg pulp_fpu_zfinx_1cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_zfinx_1cyclat_legacy_v1.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_zfinx_2cyclat | NR File xpulp_instr
+./cv_regress --rmdb --file=cv32e40pv2_xpulp_instr.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_2cyclat_xpulp_instr.rmdb --num=200 --iss yes --cov --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_zfinx_2cyclat_xpulp_instr.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_zfinx_2cyclat | NR File fpu_instr
+./cv_regress --rmdb --file=cv32e40pv2_fpu_instr.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_2cyclat_fpu_instr.rmdb --num=300 --iss yes --cov --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_zfinx_2cyclat_fpu_instr.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_zfinx_2cyclat | NR File interrupt_debug_short
+./cv_regress --rmdb --file=cv32e40pv2_interrupt_debug_short.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_2cyclat_interrupt_debug_short.rmdb --num=60 --iss yes --cov --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_zfinx_2cyclat_interrupt_debug_short.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_zfinx_2cyclat | NR File interrupt_debug_long
+./cv_regress --rmdb --file=cv32e40pv2_interrupt_debug_long.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_2cyclat_interrupt_debug_long.rmdb --num=6 --iss yes --cov --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_zfinx_2cyclat_interrupt_debug_long.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+# CFG pulp_fpu_zfinx_2cyclat | NR File legacy_v1
+./cv_regress --rmdb --file=cv32e40pv2_legacy_v1.yaml --simulator=vsim --outfile=pulp_fpu_zfinx_2cyclat_legacy_v1.rmdb --num=1 --iss yes --cov --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg disable_all_trn_logs,floating_pt_zfinx_instr_en --lsf "bsub -K -q ${LSF_QUEUE}"
+vrun -rmdb pulp_fpu_zfinx_2cyclat_legacy_v1.rmdb -run cv32e40p -j $NB_JOBS -notimeout -nogridmsg -noautotriage -noautomerge -GUSE_POST_COMPRESSION=yes -GSEED_MODE=RAND
+
+
+popd > /dev/null
diff --git a/cv32e40p/docs/VerifPlans/README.md b/cv32e40p/docs/VerifPlans/README.md
index 755f264440..e8709b7b64 100644
--- a/cv32e40p/docs/VerifPlans/README.md
+++ b/cv32e40p/docs/VerifPlans/README.md
@@ -32,27 +32,27 @@ Under the heading `Link`, the name shown corresponds to the filename of the vpla
 
 | Category            | Feature        | VPlan Status | Review Status | Comment | Link |
 |---------------------|----------------|--------------|---------------|---------|------|
-| **Base Instruction Set** | RV32IMC + F + Zfinx + Zifencei | v2-formal-new | Reviewed |      | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) |
-| **Interrupts**      | CLINT | v1-updated   | Reviewed | Addition of missing XPULP / F / Zfinx interrupts | [CV32E40Pv2_interrupts.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/interrupts/CV32E40Pv2_interrupts.xlsx "Interrupts Vplan")|
-| **Debug & Trace**   | Debug          | v1-reused | Reviewed | Missing XPULP-specific debug are in a separate vplan | [CV32E40Pv2_debug.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/debug-trace/CV32E40Pv2_debug.xlsx "Debug Vplan")|
-| **Privileged Spec** | CSRs / Zicsr | v2-formal-new | Reviewed |      | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) |
-| **Micro-architecture** | OBI |  v1-reused  | Reviewed |         | [CV32E40P_OBI_VerifPlan.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_OBI_VerifPlan.xlsx "OBI Vplan") |
-|                        | Pipeline / Sleep Unit | v1-reused | Reviewed |  | [CV32E40P_Pipeline_Sleep.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_Pipeline_Sleep.xlsx "Pipeline Sleep Vplan") |
-|                        | FPU Register File | v2-sim-new | Reviewed |  | [CV32E40Pv2_FPU_register_file.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40Pv2_FPU_register_file.xlsx "FPU Reg. File Vplan") |
-| **Additional ISA** | F / Zfinx | v2-sim-new | Reviewed | Includes uncoverable items from formal verification | [CV32E40Pv2_F-Zfinx-instructions.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/Zfinx_F_instructions/CV32E40Pv2_F-Zfinx-instructions.xlsx "Add. F/Zfinx Vplan") |
-| **XPULP** | Post-Increment Load/Store (Formal) | v2-formal-new | Reviewed |      | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) |
-|  | Post-Increment Load/Store (Simulation) | v2-sim-new | Reviewed | Addition of "pipeline" with simulation (preceeding F multicycle)  | [CV32E40Pv2_xpulp-postinc-loadstore.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-postinc-loadstore.xlsx "Post-Inc Load/Store simu Vplan") |
-|  | Bitmanipulation (Formal) | v2-formal-new | Reviewed |      | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) |
-|  | Bitmanipulation (Simulation) | v2-sim-new | Reviewed | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway  | [CV32E40Pv2_xpulp-bitmanipulation.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-bitmanipulations.xlsx "Bitmanip simu Vplan") |
-|  | General ALU (Formal) | v2-formal-new | Reviewed |      | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) |
-|  | General ALU (Simulation) | v2-simu-new | Reviewed | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway  | [CV32E40Pv2_xpulp-general-alu.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-general-alu.xlsx "General ALU simu Vplan") |
-|  | Immediate Branching (Formal) | v2-formal-new | Reviewed |      | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) |
-|  | Immediate Branching (Simulation) | v2-simu-new | Reviewed | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway  | [CV32E40Pv2_xpulp-immediate-branching.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-immediate-branching.xlsx "Imm Branching simu Vplan") |
-|  | MAC (Formal) | v2-formal-new | Reviewed |      | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) |
-|  | MAC (Simulation) | v2-sim-new | Reviewed | Addition of missing coverage from formal (operands "toggle")   | [CV32E40Pv2_xpulp-multiply-accumulate.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-multiply-accumulate.xlsx "MAC simu Vplan") |
-|  | SIMD (Formal) | v2-formal-new | Reviewed |      | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) |
-|  | SIMD (Simulation) | v2-sim-new | Reviewed | Addition of missing coverage from formal (operands "toggle")   | [CV32E40Pv2_xpulp-packed-simd.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-packed-simd.xlsx "SIMD simu Vplan") |
-|  | HWLoop (Simulation) | v2-sim-new | Reviewed | Feature not test at all in formal verification | [CV32E40Pv2_xpulp-hwloop.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-hwloop.xlsx "HWLoop Vplan") |
+| **Base Instruction Set** | RV32IMC + F + Zfinx + Zifencei | v2-formal-new | Complete |      | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) |
+| **Interrupts**      | CLINT | v1-updated   | Complete | Addition of missing XPULP / F / Zfinx interrupts | [CV32E40Pv2_interrupts.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/interrupts/CV32E40Pv2_interrupts.xlsx "Interrupts Vplan")|
+| **Debug & Trace**   | Debug          | v1-reused | Complete | Missing XPULP-specific debug are in a separate vplan | [CV32E40Pv2_debug.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/debug-trace/CV32E40Pv2_debug.xlsx "Debug Vplan")|
+| **Privileged Spec** | CSRs / Zicsr | v2-formal-new | Complete |      | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) |
+| **Micro-architecture** | OBI |  v1-reused  | Complete |         | [CV32E40P_OBI_VerifPlan.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_OBI_VerifPlan.xlsx "OBI Vplan") |
+|                        | Pipeline / Sleep Unit | v1-reused | Complete |  | [CV32E40P_Pipeline_Sleep.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_Pipeline_Sleep.xlsx "Pipeline Sleep Vplan") |
+|                        | FPU Register File | v2-sim-new | Complete |  | [CV32E40Pv2_FPU_register_file.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40Pv2_FPU_register_file.xlsx "FPU Reg. File Vplan") |
+| **Additional ISA** | F / Zfinx | v2-sim-new | Complete | Includes uncoverable items from formal verification | [CV32E40Pv2_F-Zfinx-instructions.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/Zfinx_F_instructions/CV32E40Pv2_F-Zfinx-instructions.xlsx "Add. F/Zfinx Vplan") |
+| **XPULP** | Post-Increment Load/Store (Formal) | v2-formal-new | Complete |      | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) |
+|  | Post-Increment Load/Store (Simulation) | v2-sim-new | Complete | Addition of "pipeline" with simulation (preceeding F multicycle)  | [CV32E40Pv2_xpulp-postinc-loadstore.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-postinc-loadstore.xlsx "Post-Inc Load/Store simu Vplan") |
+|  | Bitmanipulation (Formal) | v2-formal-new | Complete |      | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) |
+|  | Bitmanipulation (Simulation) | v2-sim-new | Complete | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway  | [CV32E40Pv2_xpulp-bitmanipulation.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-bitmanipulations.xlsx "Bitmanip simu Vplan") |
+|  | General ALU (Formal) | v2-formal-new | Complete |      | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) |
+|  | General ALU (Simulation) | v2-simu-new | Complete | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway  | [CV32E40Pv2_xpulp-general-alu.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-general-alu.xlsx "General ALU simu Vplan") |
+|  | Immediate Branching (Formal) | v2-formal-new | Complete |      | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) |
+|  | Immediate Branching (Simulation) | v2-simu-new | Complete | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway  | [CV32E40Pv2_xpulp-immediate-branching.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-immediate-branching.xlsx "Imm Branching simu Vplan") |
+|  | MAC (Formal) | v2-formal-new | Complete |      | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) |
+|  | MAC (Simulation) | v2-sim-new | Complete | Addition of missing coverage from formal (operands "toggle")   | [CV32E40Pv2_xpulp-multiply-accumulate.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-multiply-accumulate.xlsx "MAC simu Vplan") |
+|  | SIMD (Formal) | v2-formal-new | Complete |      | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) |
+|  | SIMD (Simulation) | v2-sim-new | Complete | Addition of missing coverage from formal (operands "toggle")   | [CV32E40Pv2_xpulp-packed-simd.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-packed-simd.xlsx "SIMD simu Vplan") |
+|  | HWLoop (Simulation) | v2-sim-new | Complete | Feature not test at all in formal verification | [CV32E40Pv2_xpulp-hwloop.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-hwloop.xlsx "HWLoop Vplan") |
 
 
 </br>