diff --git a/bin/templates/regress_rmdb.j2 b/bin/templates/regress_rmdb.j2 index a0411f811a..4aba954d56 100644 --- a/bin/templates/regress_rmdb.j2 +++ b/bin/templates/regress_rmdb.j2 @@ -208,8 +208,11 @@ echo " TEST RUNCMD: (%t_cmd%) CHECK_SIM_RESULT={{regress_macros.yesorno(check_sim_results)}} COMP=0 CV_CORE={{project}} {{toolchain|upper}}=1 CFG=(%t_cfg%) TEST_CFG_FILE=(%t_test_cfg:%) SIMULATOR=(%t_simulator%) USE_ISS=(%t_iss:%) COV=(%t_cov:%) RUN_INDEX=(%t_iteration%) GEN_START_INDEX=(%t_iteration%) SEED=(%t_iteration%) {{regress_macros.cv_results(results_path)}} {{makeargs}} (%t_makearg%)" echo " logfile: (%log_file%)" - echo " Here is the commend to reproduce the test locally: - echo " (%t_cmd%) CHECK_SIM_RESULT={{regress_macros.yesorno(check_sim_results)}} CV_CORE={{project}} {{toolchain|upper}}=1 CFG=(%t_cfg%) TEST_CFG_FILE=(%t_test_cfg:%) SIMULATOR=(%t_simulator%) USE_ISS=(%t_iss:%) COV=(%t_cov:%) SEED=(%t_iteration%) {{makeargs}} (%t_makearg%) + echo " RTL repo: CV_CORE_REPO : ${CV_CORE_REPO}" + echo " CV_CORE_BRANCH: ${CV_CORE_BRANCH}" + echo " CV_CORE_HASH : ${CV_CORE_HASH}" + echo " Here is the command to reproduce the test, using above RTL repo: " + echo " (%t_cmd%) CHECK_SIM_RESULT={{regress_macros.yesorno(check_sim_results)}} CV_CORE={{project}} {{toolchain|upper}}=1 CFG=(%t_cfg%) TEST_CFG_FILE=(%t_test_cfg:%) SIMULATOR=(%t_simulator%) USE_ISS=(%t_iss:%) COV=(%t_cov:%) SEED=(%t_iteration%) {{makeargs}} (%t_makearg%) " cd (%t_abs_dir%) && (%t_cmd%) CHECK_SIM_RESULT={{regress_macros.yesorno(check_sim_results)}} CHECK_SIM_LOG=(%log_file%) COMP=0 CV_CORE={{project}} {{toolchain|upper}}=1 CFG=(%t_cfg%) TEST_CFG_FILE=(%t_test_cfg:%) SIMULATOR=(%t_simulator%) USE_ISS=(%t_iss:%) COV=(%t_cov:%) RUN_INDEX=(%t_iteration%) GEN_START_INDEX=(%t_iteration%) SEED=(%t_iteration%) {{regress_macros.cv_results(results_path)}} {{makeargs}} (%t_makearg%) diff --git a/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv b/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv index ed095c67a0..299874fbaa 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv @@ -365,9 +365,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // Restore user mode GPR value from kernel stack before return // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack - //pop_gpr_from_kernel_stack(status, scratch, cfg.mstatus_mprv, - // cfg.sp, cfg.tp, interrupt_handler_instr); - pop_regfile_from_kernel_stack(status, scratch, cfg.mstatus_mprv, cfg.sp, cfg.tp, interrupt_handler_instr, corev_cfg); // Emit fast interrupt handler since cv32e40p has hardware interrupt ack @@ -526,8 +523,40 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; instr_stream.push_back(str); endfunction + // Override ECALL trap handler - gen_ecall_handler of corev-dv + // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack + // With RV32X enabled, check for ecall instr on the last instr of hwloop + // If true, then + // (a) Set MEPC to first instr of hwloop body + // (b) Add logic to decrement the LPCOUNT + virtual function void gen_ecall_handler(int hart); + string instr[$]; + cv32e40p_instr_gen_config corev_cfg; + + `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") + + if (riscv_instr_pkg::RV32X inside {riscv_instr_pkg::supported_isa}) begin + instr = {instr, + `COMMON_HWLOOP_EXC_HANDLING_CODE + }; + end else begin + instr = {instr, + $sformatf("csrr x%0d, mepc", cfg.gpr[0]), + $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), + $sformatf("csrw mepc, x%0d", cfg.gpr[0]) + }; + end + pop_regfile_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr, corev_cfg); + instr.push_back("mret"); + gen_section(get_label("ecall_handler", hart), instr); + endfunction : gen_ecall_handler + // Override Ebreak trap handler - gen_ebreak_handler // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack + // With RV32X enabled, check for ebreak instr on the last instr of hwloop + // If true, then + // (a) Set MEPC to first instr of hwloop body + // (b) Add logic to decrement the LPCOUNT virtual function void gen_ebreak_handler(int hart); string instr[$]; cv32e40p_instr_gen_config corev_cfg; @@ -536,13 +565,18 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; gen_signature_handshake(instr, CORE_STATUS, EBREAK_EXCEPTION); gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); - instr = {instr, - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), - $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), - $sformatf("csrw 0x%0x, x%0d", MEPC, cfg.gpr[0]) - }; + if (riscv_instr_pkg::RV32X inside {riscv_instr_pkg::supported_isa}) begin + instr = {instr, + `COMMON_HWLOOP_EXC_HANDLING_CODE + }; + end else begin + instr = {instr, + $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), + $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), + $sformatf("csrw 0x%0x, x%0d", MEPC, cfg.gpr[0]) + }; + end // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack - //pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); pop_regfile_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr, corev_cfg); instr.push_back("mret"); gen_section(get_label("ebreak_handler", hart), instr); @@ -551,8 +585,9 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // Override Illegal instruction handler - gen_illegal_instr_handler // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack // With RV32X enabled, check for illegal instr on the last instr of hwloop - // If true, then set MEPC to first instr of hwloop instead of simply - // incrementing by 4. + // If true, then + // (a) Set MEPC to first instr of hwloop body + // (b) Add logic to decrement the LPCOUNT virtual function void gen_illegal_instr_handler(int hart); string instr[$]; cv32e40p_instr_gen_config corev_cfg; @@ -563,28 +598,7 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); if (riscv_instr_pkg::RV32X inside {riscv_instr_pkg::supported_isa}) begin instr = {instr, - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], LPCOUNT1), - $sformatf("li x%0d, 2", cfg.gpr[1]), - $sformatf("bge x%0d, x%0d, 1f", cfg.gpr[0], cfg.gpr[1]), - $sformatf("2: csrr x%0d, 0x%0x", cfg.gpr[0], LPCOUNT0), - $sformatf("li x%0d, 2", cfg.gpr[1]), - $sformatf("bge x%0d, x%0d, 3f", cfg.gpr[0], cfg.gpr[1]), - $sformatf("beqz x0, 4f"), - $sformatf("1: csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPEND1), - $sformatf("addi x%0d, x%0d, -4", cfg.gpr[1], cfg.gpr[1]), - $sformatf("bne x%0d, x%0d, 2b", cfg.gpr[0], cfg.gpr[1]), - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], LPSTART1), - $sformatf("beqz x0, 5f"), - $sformatf("3: csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPEND0), - $sformatf("addi x%0d, x%0d, -4", cfg.gpr[1], cfg.gpr[1]), - $sformatf("bne x%0d, x%0d, 4f", cfg.gpr[0], cfg.gpr[1]), - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], LPSTART0), - $sformatf("beqz x0, 5f"), - $sformatf("4: csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), - $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), - $sformatf("5: csrw 0x%0x, x%0d", MEPC, cfg.gpr[0]) + `COMMON_HWLOOP_EXC_HANDLING_CODE }; end else begin instr = {instr, @@ -594,7 +608,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; }; end // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack - //pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); pop_regfile_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr, corev_cfg); instr.push_back("mret"); gen_section(get_label("illegal_instr_handler", hart), instr); @@ -616,7 +629,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; instr); end // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack - //pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); pop_regfile_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr, corev_cfg); instr.push_back("mret"); gen_section(get_label("instr_fault_handler", hart), instr); @@ -638,7 +650,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; instr); end // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack - //pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); pop_regfile_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr, corev_cfg); instr.push_back("mret"); gen_section(get_label("load_fault_handler", hart), instr); @@ -660,7 +671,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; instr); end // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack - //pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); pop_regfile_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr, corev_cfg); instr.push_back("mret"); gen_section(get_label("store_fault_handler", hart), instr); diff --git a/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv b/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv index ca8f904690..c828b7395b 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv @@ -115,7 +115,7 @@ class cv32e40p_debug_rom_gen extends riscv_debug_rom_gen; format_section(debug_main); gen_sub_program(hart, sub_program[hart], sub_program_name, cfg.num_debug_sub_program, 1'b1, "debug_sub"); - main_program[hart] = riscv_instr_sequence::type_id::create("debug_program"); + main_program[hart] = cv32e40p_instr_sequence::type_id::create("debug_program"); main_program[hart].instr_cnt = cfg.debug_program_instr_cnt; main_program[hart].is_debug_program = 1; main_program[hart].cfg = cfg; diff --git a/cv32e40p/env/corev-dv/cv32e40p_illegal_instr.sv b/cv32e40p/env/corev-dv/cv32e40p_illegal_instr.sv index 4160c8185c..dcad5642e1 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_illegal_instr.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_illegal_instr.sv @@ -43,6 +43,10 @@ class cv32e40p_illegal_instr extends riscv_illegal_instr; function void cv32e40p_init(riscv_instr_gen_config cfg); this.cfg = cfg; + if (riscv_instr_pkg::RV32FC inside {riscv_instr_pkg::supported_isa}) begin + legal_c00_opcode = {legal_c00_opcode, 3'b011, 3'b111}; + legal_c10_opcode = {legal_c10_opcode, 3'b011, 3'b111}; + end if (riscv_instr_pkg::RV32ZFINX inside {riscv_instr_pkg::supported_isa}) begin legal_opcode = {legal_opcode, 7'b1000011, 7'b1000111, 7'b1001011, 7'b1001111, 7'b1010011}; diff --git a/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv b/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv index 3756295b06..a22508508b 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv @@ -175,6 +175,12 @@ class cv32e40p_instr_sequence extends riscv_instr_sequence; instr_stream.instr_list[i].has_label = 1'b0; end end + // Remove all pulp store instructions inside debug_program + if(is_debug_program == 1) begin + if (instr_stream.instr_list[i].instr_name inside {CV_SB, CV_SH, CV_SW} ) begin + instr_stream.instr_list.delete(i); + end + end i++; end // while `uvm_info(get_full_name(), "Finished post-processing instructions", UVM_HIGH) diff --git a/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv b/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv index 1bfb8c8463..eef1415f43 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv @@ -27,6 +27,71 @@ package cv32e40p_instr_test_pkg; import riscv_signature_pkg::*; import corev_instr_test_pkg::*; + + // MACRO for Common HWLOOP handling code for all the exception handlers + // Common handler code to ensure all handlers use same code. + // Description: + // Check for expection (ecall/ebreak/illegal) on the last hwloop body instr + // If true, then + // (a) Set MEPC to first instr of hwloop body + // (b) Add logic to decrement the LPCOUNT + `define COMMON_HWLOOP_EXC_HANDLING_CODE \ + /* Check LPCOUNT1 >= 1 */ \ + $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], LPCOUNT1), \ + $sformatf("li x%0d, 1", cfg.gpr[1]), \ + $sformatf("bge x%0d, x%0d, 1f", cfg.gpr[0], cfg.gpr[1]), \ + /* Check LPCOUNT0 >= 1 */ \ + $sformatf("2: csrr x%0d, 0x%0x", cfg.gpr[0], LPCOUNT0), \ + $sformatf("li x%0d, 1", cfg.gpr[1]), \ + $sformatf("bge x%0d, x%0d, 3f", cfg.gpr[0], cfg.gpr[1]), \ + /* Since both LPCOUNT0 & LPCOUNT1 equals 0 */ \ + /* Nothing needs to be done for HWLOOPs and its CSRs */ \ + $sformatf("beqz x0, 4f"), \ + /* HWLOOP1 Handling */ \ + /* Check for ILLEGAL being the LAST HWLOOP Body instr */ \ + $sformatf("1: csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), \ + $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPEND1), \ + $sformatf("addi x%0d, x%0d, -4", cfg.gpr[1], cfg.gpr[1]), \ + $sformatf("bne x%0d, x%0d, 2b", cfg.gpr[0], cfg.gpr[1]), \ + /* Else, If equal this means the illegal instr was the last */ \ + /* hwloop body instr, thus we handle the HWLOOP manually here */ \ + /* First decrement lpcount CSR manually as CSR not updated in HW */ \ + $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPCOUNT1), \ + $sformatf("addi x%0d, x%0d, -1", cfg.gpr[1], cfg.gpr[1]), \ + $sformatf("cv.count 1, x%0d", cfg.gpr[1]), \ + /* Check if the current LPCOUNT1 value == 0, if so, then MEPC=MEPC+4 */ \ + $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPCOUNT1), \ + $sformatf("beqz x%0d, 4f", cfg.gpr[1]), \ + /* Else LPCOUNT1 still >=1 and thus next, */ \ + /* Set the next MEPC to LPSTART1 for next HWLOOP iteration */ \ + $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], LPSTART1), \ + $sformatf("beqz x0, 5f"), \ + /* HWLOOP0 Handling */ \ + /* Check for ILLEGAL being the LAST HWLOOP Body instr */ \ + $sformatf("3: csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), \ + $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPEND0), \ + $sformatf("addi x%0d, x%0d, -4", cfg.gpr[1], cfg.gpr[1]), \ + $sformatf("bne x%0d, x%0d, 4f", cfg.gpr[0], cfg.gpr[1]), \ + /* Else, If equal this means the illegal instr was the last */ \ + /* hwloop body instr, thus we handle the HWLOOP manually here */ \ + /* First decrement lpcount CSR manually as CSR not updated in HW */ \ + $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPCOUNT0), \ + $sformatf("addi x%0d, x%0d, -1", cfg.gpr[1], cfg.gpr[1]), \ + $sformatf("cv.count 0, x%0d", cfg.gpr[1]), \ + /* Check if the current LPCOUNT0 value == 0, if so, then MEPC=MEPC+4 */ \ + $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPCOUNT0), \ + $sformatf("beqz x%0d, 4f", cfg.gpr[1]), \ + /* Else LPCOUNT0 still >=1 and thus next, */ \ + /* Set the next MEPC to LPSTART0 for next HWLOOP iteration */ \ + $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], LPSTART0), \ + $sformatf("beqz x0, 5f"), \ + /* Default increment for MEPC by 4 */ \ + $sformatf("4: csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), \ + $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), \ + /* Write MEPC */ \ + $sformatf("5: csrw 0x%0x, x%0d", MEPC, cfg.gpr[0]) + + `include "cv32e40p_instr_gen_config.sv" // Instruction streams specific to CV32E40P // `include "instr_lib/cv32e40p_load_store_instr_lib.sv" @@ -407,5 +472,4 @@ package cv32e40p_instr_test_pkg; end endfunction - endpackage : cv32e40p_instr_test_pkg; diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv index 00c70b9d73..96e253e7ad 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv @@ -146,7 +146,12 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; } constraint avail_regs_pulp_instr_c { - num_of_avail_regs inside {[10:19]}; + if ((cfg.enable_fp_in_x_regs == 1) && (RV32ZFINX inside {riscv_instr_pkg::supported_isa})) { + num_of_avail_regs >= 8; + num_of_avail_regs <= (24 - num_zfinx_gpr - num_str_reserved_gpr); + } else { + num_of_avail_regs inside {[10:19]}; + } } constraint gen_hwloop_count_c { @@ -154,10 +159,10 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; num_loops_active inside {1,2,3}; foreach(hwloop_counti[i]) - hwloop_counti[i] inside {[0:100]};//TODO: check 0 is valid + hwloop_counti[i] inside {[0:64]}; foreach(hwloop_count[i]) - hwloop_count[i] inside {[0:100]};//TODO: check 0 is valid + hwloop_count[i] inside {[0:64]}; } constraint num_hwloop_instr_c { @@ -216,10 +221,10 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; } else { if (use_setup_inst[1] && use_loop_setupi_inst[1]) { //with setupi only [4:0] uimmS range avail for end label if(use_setup_inst[0]) { - num_hwloop_instr[0] inside {[3:27]}; //TODO:in nested hwloop0 with setupi instr more than 27 instructions will have issue if setupi used for hwloop1? + num_hwloop_instr[0] inside {[3:27]}; //For nested hwloop0 with setupi instr more than 27 instructions will have issue if setupi used for hwloop1 num_hwloop_instr[1] >= num_hwloop_instr[0] + 1 + 2; // num_hwloop_ctrl_instr[0] == 1 ; 2 for end of loop req } else { - num_hwloop_instr[0] inside {[3:25]}; //TODO:in nested hwloop0 with setupi instr more than 27 instructions will have issue if setupi used for hwloop1? + num_hwloop_instr[0] inside {[3:25]}; //For nested hwloop0 with setupi instr more than 27 instructions will have issue if setupi used for hwloop1 num_hwloop_instr[1] >= num_hwloop_instr[0] + 3 + 2; // num_hwloop_ctrl_instr[0] == 3 ; 2 for end of loop req } //num_hwloop_instr[1] inside {[6:30]}; @@ -265,11 +270,13 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; function void post_randomize(); + cv32e40p_exclude_regs.sort(); + this.print(); + if((cv32e40p_exclude_regs.size() < 2) || (cv32e40p_exclude_regs.size() > 25)) begin `uvm_fatal(this.get_type_name(), "cv32e40p_exclude_regs out of range") end - this.print(); gen_xpulp_hwloop_control_instr(); endfunction : post_randomize @@ -428,7 +435,7 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; insert_rand_instr(.num_rand_instr(num_fill_instr_loop_ctrl_to_loop_start[1]), .no_branch(1), .no_compressed(0), - .no_fence(0)); //TODO: Fence instr allowed here? + .no_fence(0)); //Fence instr allowed here end else begin set_label_at_next_instr = 1; //no rand instr so next instruction must have a label @@ -498,7 +505,7 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; .label_is_pulp_hwloop_body_label(1), .no_branch(1), .no_compressed(0), - .no_fence(0)); //TODO: Fence instr allowed here? + .no_fence(0)); //Fence instr allowed here insert_rand_instr(.num_rand_instr($urandom_range(0,20)), .no_branch(1), @@ -561,7 +568,7 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; //Insert Random instructions till Loop HWLOOP_START0/1 label -> use_setup_inst ? 0 : num_fill_instr_loop_ctrl_to_loop_start[0/1] if(!use_setup_inst[hwloop_L]) - insert_rand_instr((num_fill_instr_loop_ctrl_to_loop_start[hwloop_L]),1,0,0); // allow compressed instructions here ; TODO: Fence instr allowed here? + insert_rand_instr((num_fill_instr_loop_ctrl_to_loop_start[hwloop_L]),1,0,0); // allow compressed instructions here ; Fence instr allowed here //LABEL HWLOOP_START0/1: insert_rand_instr_with_label(start_label_s,1); // no branch, no compressed, no fence instructions inside hwloop @@ -575,7 +582,7 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; .label_is_pulp_hwloop_body_label(1), .no_branch(1), .no_compressed(0), - .no_fence(0)); //TODO: Fence instr allowed here? + .no_fence(0)); //Fence instr allowed here // // allow compressed, fence instructions here @@ -926,7 +933,7 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; while (i < num_rand_instr) begin //Create and Randomize array for avail_regs each time to ensure randomization avail_regs = new[num_of_avail_regs - reserved_rd.size()]; - randomize_avail_regs(); + randomize_avail_regs(); //TODO : randomize to exclude cv32e40p_exclude_regs list instr = riscv_instr::type_id::create($sformatf("instr_%0d", i)); @@ -1079,7 +1086,7 @@ class cv32e40p_xpulp_short_hwloop_stream extends cv32e40p_xpulp_hwloop_base_stre if(gen_nested_loop) { if(loop0_high_count) { hwloop_counti[0] dist {[0:400] := 10, [401:1023] := 300, [1024:2047] := 150, - [2048:4095] := 50, 4095 := 300}; + [2048:4094] := 50, 4095 := 300}; hwloop_count[0] dist {[0:400] := 10, [401:1023] := 300, [1024:2047] := 150, [2048:4094] := 50, 4095 := 300}; @@ -1092,7 +1099,7 @@ class cv32e40p_xpulp_short_hwloop_stream extends cv32e40p_xpulp_hwloop_base_stre hwloop_count[0] inside {[0:5]}; hwloop_counti[1] dist {[0:400] := 10, [401:1023] := 300, [1024:2047] := 150, - [2048:4095] := 50, 4095 := 300}; + [2048:4094] := 50, 4095 := 300}; hwloop_count[1] dist {[0:400] := 10, [401:1023] := 300, [1024:2047] := 150, [2048:4094] := 50, 4095 := 300}; @@ -1102,12 +1109,13 @@ class cv32e40p_xpulp_short_hwloop_stream extends cv32e40p_xpulp_hwloop_base_stre } else { foreach(hwloop_counti[i]) hwloop_counti[i] dist {[0:400] := 10, [401:1023] := 300, [1024:2047] := 150, - [2048:4095] := 50, 4095 := 300}; //TODO: check 0 is valid + [2048:4094] := 50, 4095 := 300}; - //TODO: for rs1 32 bit count ? + //For rs1 32 bit count, not planned to exercise whole range in these streams + //due to long run times foreach(hwloop_count[i]) hwloop_count[i] dist {[0:400] := 10, [401:1023] := 300, [1024:2047] := 150, - [2048:4094] := 50, 4095 := 300};//TODO: check 0 is valid + [2048:4094] := 50, 4095 := 300}; } } @@ -1226,10 +1234,10 @@ class cv32e40p_xpulp_long_hwloop_stream extends cv32e40p_xpulp_hwloop_base_strea constraint gen_hwloop_count_c { num_loops_active inside {1}; foreach(hwloop_counti[i]) - hwloop_counti[i] inside {[0:50]};//TODO: check 0 is valid + hwloop_counti[i] inside {[0:25]}; foreach(hwloop_count[i]) - hwloop_count[i] inside {[0:50]};//TODO: check 0 is valid + hwloop_count[i] inside {[0:25]}; } diff --git a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv index e1f2742d26..c9844c1132 100644 --- a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv @@ -53,10 +53,11 @@ class uvme_rv32x_hwloop_covg # ( } s_csr_hwloop; typedef struct { hwloop_type_t hwloop_type; - hwloop_setup_t hwloop_setup [HWLOOP_NB]; + hwloop_setup_t hwloop_setup [HWLOOP_NB]; s_csr_hwloop hwloop_csr; + bit sample_hwloop_csr_done [HWLOOP_NB]; bit execute_instr_in_hwloop [HWLOOP_NB]; - int track_lp_count [HWLOOP_NB]; + int track_lp_count [HWLOOP_NB]; } s_hwloop_stat; // PROPERTIES - START @@ -68,7 +69,7 @@ class uvme_rv32x_hwloop_covg # ( local s_hwloop_stat hwloop_stat_``TYPE = '{default:0, hwloop_type:NULL_TYPE, hwloop_setup:'{default:NULL_SETUP}}; \ local bit [(ILEN-1):0] insn_list_in_hwloop_``TYPE [HWLOOP_NB][$]; \ local bit [31:0] irq_vect_``TYPE [HWLOOP_NB][$]; \ - local bit debug_req_``TYPE [HWLOOP_NB] = '{default:0}; \ + local bit debug_req_``TYPE [HWLOOP_NB] = '{default:0}; \ local bit dbg_trigger_``TYPE [HWLOOP_NB] = '{default:0}; \ local int unsigned dbg_step_cnt_``TYPE [HWLOOP_NB] = '{default:0}; \ local bit done_insn_list_capture_``TYPE [HWLOOP_NB] = '{default:0}; @@ -608,10 +609,14 @@ class uvme_rv32x_hwloop_covg # ( ccp_hwloop_type_dbg_mode : cross cp_hwloop_type, cp_hwloop_dbg_haltreq; \ ccp_hwloop_type_dbg_trigger : cross cp_hwloop_type, cp_hwloop_dbg_trigger; \ ccp_hwloop_type_dbg_step_cnt : cross cp_hwloop_type, cp_hwloop_dbg_step_cnt { \ - bins ccp_dbg_step_range_1 = binsof (cp_hwloop_dbg_step_cnt) intersect {[1:4]} ; \ - bins ccp_dbg_step_range_2 = binsof (cp_hwloop_dbg_step_cnt) intersect {[5:20]} ; \ - bins ccp_dbg_step_range_3 = binsof (cp_hwloop_dbg_step_cnt) intersect {[20:50]} ; \ - bins ccp_dbg_step_range_4 = binsof (cp_hwloop_dbg_step_cnt) intersect {[51:$]} ; \ + bins ccp_single_dbg_step_range_1 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_1) && binsof (cp_hwloop_type.single_hwloop); \ + bins ccp_single_dbg_step_range_2 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_2) && binsof (cp_hwloop_type.single_hwloop); \ + bins ccp_single_dbg_step_range_3 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_3) && binsof (cp_hwloop_type.single_hwloop); \ + bins ccp_single_dbg_step_range_4 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_4) && binsof (cp_hwloop_type.single_hwloop); \ + bins ccp_nested_dbg_step_range_1 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_1) && binsof (cp_hwloop_type.nested_hwloop); \ + bins ccp_nested_dbg_step_range_2 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_2) && binsof (cp_hwloop_type.nested_hwloop); \ + bins ccp_nested_dbg_step_range_3 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_3) && binsof (cp_hwloop_type.nested_hwloop); \ + bins ccp_nested_dbg_step_range_4 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_4) && binsof (cp_hwloop_type.nested_hwloop); \ } /* todo: x with lpcount */ \ endgroup : cg_features_of_hwloop_``LOOP_IDX`` @@ -660,18 +665,18 @@ class uvme_rv32x_hwloop_covg # ( short_setup_cnt++; \ end \ if (csr_hwloop_``TYPE``.lp_start_wb[i] && csr_hwloop_``TYPE``.lp_end_wb[i] && csr_hwloop_``TYPE``.lp_count_wb[i]) begin : SAMPLE_HWLOP_CSR \ - if (csr_hwloop_``TYPE``.lp_count[i] != 0) begin : SAMPLE_IF_TRUE \ - `uvm_info(_header, $sformatf("DEBUG - cg_csr_hwloop[%0d] - sampling csr_hwloop is %p", i, csr_hwloop_``TYPE``), UVM_NONE); \ - unique case (i) \ - 0: begin \ - `CG_CSR_HWLOOP(0).sample(csr_hwloop_``TYPE``); \ - `uvm_info(_header, $sformatf("DEBUG - cg_csr_hwloop[%0d] - get_inst_coverage = %.2f, get_coverage = %.2f", i, `CG_CSR_HWLOOP(0).get_inst_coverage(), `CG_CSR_HWLOOP(0).get_coverage), UVM_NONE); \ - end \ - 1: begin \ - `CG_CSR_HWLOOP(1).sample(csr_hwloop_``TYPE``); \ - `uvm_info(_header, $sformatf("DEBUG - cg_csr_hwloop[%0d] - get_inst_coverage = %.2f, get_coverage = %.2f", i, `CG_CSR_HWLOOP(1).get_inst_coverage(), `CG_CSR_HWLOOP(1).get_coverage), UVM_NONE); \ - end \ - endcase \ + if (csr_hwloop_``TYPE``.lp_count[i] != 0 && !hwloop_stat_``TYPE``.sample_hwloop_csr_done[i]) begin \ + `uvm_info(_header, $sformatf("DEBUG - cg_csr_hwloop[%0d] - sampling csr_hwloop is %p", i, csr_hwloop_``TYPE``), UVM_DEBUG); \ + unique case (i) \ + 0: begin \ + `CG_CSR_HWLOOP(0).sample(csr_hwloop_``TYPE``); \ + `uvm_info(_header, $sformatf("DEBUG - cg_csr_hwloop[%0d] - get_inst_coverage = %.2f, get_coverage = %.2f", i, `CG_CSR_HWLOOP(0).get_inst_coverage(), `CG_CSR_HWLOOP(0).get_coverage), UVM_DEBUG); \ + end \ + 1: begin \ + `CG_CSR_HWLOOP(1).sample(csr_hwloop_``TYPE``); \ + `uvm_info(_header, $sformatf("DEBUG - cg_csr_hwloop[%0d] - get_inst_coverage = %.2f, get_coverage = %.2f", i, `CG_CSR_HWLOOP(1).get_inst_coverage(), `CG_CSR_HWLOOP(1).get_coverage), UVM_DEBUG); \ + end \ + endcase \ // update hwloop_stat \ hwloop_stat_``TYPE``.hwloop_csr.lp_start[i] = csr_hwloop_``TYPE``.lp_start[i]; \ hwloop_stat_``TYPE``.hwloop_csr.lp_end[i] = csr_hwloop_``TYPE``.lp_end[i]; \ @@ -680,8 +685,13 @@ class uvme_rv32x_hwloop_covg # ( hwloop_stat_``TYPE``.hwloop_setup[i] = SHORT; \ else \ hwloop_stat_``TYPE``.hwloop_setup[i] = LONG; \ - end // SAMPLE_IF_TRUE \ - csr_hwloop_``TYPE`` = csr_hwloop_init; // reset struc \ + hwloop_stat_``TYPE``.sample_hwloop_csr_done[i] = 1'b1; \ + end \ + else if (hwloop_stat_``TYPE``.execute_instr_in_hwloop[i]) begin \ + hwloop_stat_``TYPE``.hwloop_csr.lp_start[i] = csr_hwloop_``TYPE``.lp_start[i]; \ + hwloop_stat_``TYPE``.hwloop_csr.lp_end[i] = csr_hwloop_``TYPE``.lp_end[i]; \ + hwloop_stat_``TYPE``.hwloop_csr.lp_count[i] = csr_hwloop_``TYPE``.lp_count[i]; \ + end \ end // SAMPLE_HWLOP_CSR \ end // for \ endtask : check_n_sample_csr_hwloop_``TYPE`` @@ -690,8 +700,6 @@ class uvme_rv32x_hwloop_covg # ( `DEF_CHECK_N_SAMPLE_CSR_HWLOOP(sub) // task to sample cg_features_of_hwloop - string sub = "sub"; - string main = "main"; `define CHECK_N_SAMPLE_HWLOOP(TYPE) check_n_sample_hwloop_``TYPE``(); `define DEF_CHECK_N_SAMPLE_HWLOOP(TYPE) task check_n_sample_hwloop_``TYPE``(); \ for (int i=0; i= 0); \ end \ - if (hwloop_stat_``TYPE``.track_lp_count[i] != hwloop_stat_``TYPE``.hwloop_csr.lp_count[i]) done_insn_list_capture_``TYPE``[i] = 1; \ end \ 1 : begin // in nested, skip when executing hwloop0 \ if (hwloop_stat_``TYPE``.hwloop_type == NESTED && hwloop_stat_``TYPE``.track_lp_count[0] != 0) begin \ @@ -738,11 +746,11 @@ class uvme_rv32x_hwloop_covg # ( else if (is_ebreakm) begin \ insn_list_in_hwloop_``TYPE``[i].push_back(INSN_EBREAKM); \ end \ - if (is_pc_equal_lpend(hwloop_stat_``TYPE``.hwloop_csr, i)) begin \ + if (is_pc_equal_lpend(hwloop_stat_``TYPE``.hwloop_csr, i) && hwloop_stat_``TYPE``.track_lp_count[i] != 0) begin \ hwloop_stat_``TYPE``.track_lp_count[i]--; \ + done_insn_list_capture_``TYPE``[i] = 1; \ assert(hwloop_stat_``TYPE``.track_lp_count[i] >= 0); \ end \ - if (hwloop_stat_``TYPE``.track_lp_count[i] != hwloop_stat_``TYPE``.hwloop_csr.lp_count[i]) done_insn_list_capture_``TYPE``[i] = 1; \ end \ endcase \ end \ @@ -760,7 +768,7 @@ class uvme_rv32x_hwloop_covg # ( insn_item = insn_list_in_hwloop_``TYPE``[i].pop_front(); \ if (irq_vect_``TYPE``[i].size() != 0) begin \ irq_item = irq_vect_``TYPE``[i].pop_front(); \ - `uvm_info(_header, $sformatf("DEBUG - COLLECT_IRQ - idx:%0d - irq_item is %8h", i, irq_item), UVM_NONE); \ + `uvm_info(_header, $sformatf("DEBUG - COLLECT_IRQ - idx:%0d - irq_item is %8h", i, irq_item), UVM_DEBUG); \ end \ if (debug_req_``TYPE``[i] != 0) begin \ debug_req_item = debug_req_``TYPE``[i]; \ @@ -774,7 +782,7 @@ class uvme_rv32x_hwloop_covg # ( dbg_step_cnt_item = dbg_step_cnt_``TYPE``[i]; \ dbg_step_cnt_``TYPE``[i] = 0; \ end \ - `uvm_info(_header, $sformatf("DEBUG - COLLECT_INSTR - idx:%0d - insn_item is %8h", i, insn_item), UVM_NONE); \ + `uvm_info(_header, $sformatf("DEBUG - COLLECT_INSTR - idx:%0d - insn_item is %8h", i, insn_item), UVM_DEBUG); \ unique case (i) \ 0: begin \ `CG_FEATURES_OF_HWLOOP(0).sample(hwloop_stat_``TYPE``, insn_item, irq_item, debug_req_item, dbg_trigger_item, dbg_step_cnt_item); \ @@ -786,6 +794,7 @@ class uvme_rv32x_hwloop_covg # ( end \ done_insn_list_capture_``TYPE``[i] = 0; \ end \ + csr_hwloop_``TYPE`` = csr_hwloop_init; \ hwloop_stat_``TYPE`` = hwloop_stat_init; \ end // SAMPLE_END_OF_HWLOOPS \ endtask : check_n_sample_hwloop_``TYPE`` @@ -801,14 +810,14 @@ class uvme_rv32x_hwloop_covg # ( wait (cv32e40p_rvvi_vif.clk && cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.trap && exception_code_t'(cv32e40p_rvvi_vif.csr_mcause_ecp_code) inside {CODE_ILLEGAL, CODE_EBREAK, CODE_ECALL}); exception_code = exception_code_t'(cv32e40p_rvvi_vif.csr_mcause_ecp_code); case (cv32e40p_rvvi_vif.insn) - INSTR_EBREAK, INSN_CEBREAK : is_ebreak = 1; + INSTR_EBREAK, INSN_CEBREAK : if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm) begin @(posedge cv32e40p_rvvi_vif.clk); continue; end else is_ebreak = 1; INSTR_ECALL : is_ecall = 1; default : is_illegal = 1; endcase - `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry due to %s", exception_code.name()), UVM_NONE); + `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry due to %s", exception_code.name()), UVM_DEBUG); wait (cv32e40p_rvvi_vif.clk && cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.insn == INSTR_MRET); is_ebreak = 0; is_ecall = 0; is_illegal = 0; - `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Exit"), UVM_NONE); + `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Exit"), UVM_DEBUG); end // EXCEPTION_HANDLING forever begin : IRQ_ENTRY wait (hwloop_stat_main.execute_instr_in_hwloop[0] | hwloop_stat_main.execute_instr_in_hwloop[1] | hwloop_stat_sub.execute_instr_in_hwloop[0] | hwloop_stat_sub.execute_instr_in_hwloop[1]); @@ -817,14 +826,14 @@ class uvme_rv32x_hwloop_covg # ( if (hwloop_stat_main.execute_instr_in_hwloop[1] && hwloop_stat_main.track_lp_count[1] !=0 && !in_nested_loop0) irq_vect_main[1].push_back(cv32e40p_rvvi_vif.irq_onehot_priority); if (hwloop_stat_sub.execute_instr_in_hwloop[0] && hwloop_stat_sub.track_lp_count[0] !=0) irq_vect_sub[0].push_back(cv32e40p_rvvi_vif.irq_onehot_priority); if (hwloop_stat_sub.execute_instr_in_hwloop[1] && hwloop_stat_sub.track_lp_count[1] !=0 && !in_nested_loop0) irq_vect_sub[1].push_back(cv32e40p_rvvi_vif.irq_onehot_priority); - `uvm_info(_header, $sformatf("DEBUG - IRQ Entry"), UVM_NONE); + `uvm_info(_header, $sformatf("DEBUG - IRQ Entry"), UVM_DEBUG); is_irq = 1; end // IRQ_ENTRY forever begin : IRQ_EXIT wait (hwloop_stat_main.execute_instr_in_hwloop[0] | hwloop_stat_main.execute_instr_in_hwloop[1] | hwloop_stat_sub.execute_instr_in_hwloop[0] | hwloop_stat_sub.execute_instr_in_hwloop[1]); @(posedge cv32e40p_rvvi_vif.clk); if (is_irq && cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.insn == INSTR_MRET) begin - `uvm_info(_header, $sformatf("DEBUG - IRQ Exit"), UVM_NONE); + `uvm_info(_header, $sformatf("DEBUG - IRQ Exit"), UVM_DEBUG); is_irq = 0; end end // IRQ_EXIT @@ -854,7 +863,7 @@ class uvme_rv32x_hwloop_covg # ( if (hwloop_stat_sub.execute_instr_in_hwloop[1] && hwloop_stat_sub.track_lp_count[1] !=0 && !in_nested_loop0) dbg_step_cnt_sub[1]++; end endcase - `uvm_info(_header, $sformatf("DEBUG - Debug Mode Entry due to %s", dcsr_cause.name()), UVM_NONE); + `uvm_info(_header, $sformatf("DEBUG - Debug Mode Entry due to %s", dcsr_cause.name()), UVM_DEBUG); is_dbg_mode = 1; end end // DBG_ENTRY @@ -863,8 +872,8 @@ class uvme_rv32x_hwloop_covg # ( wait (is_dbg_mode); wait (cv32e40p_rvvi_vif.clk && cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.insn == INSTR_DRET) begin @(posedge cv32e40p_rvvi_vif.clk) ; @(negedge cv32e40p_rvvi_vif.clk); - `uvm_info(_header, $sformatf("DEBUG - Debug Mode Exit"), UVM_NONE); - is_dbg_mode = 0; + `uvm_info(_header, $sformatf("DEBUG - Debug Mode Exit"), UVM_DEBUG); + is_dbg_mode = 0; is_ebreakm = 0; end end // DBG_EXIT join_none // Background threads - END @@ -878,7 +887,7 @@ class uvme_rv32x_hwloop_covg # ( if (!(is_ebreak || is_ecall || is_illegal)) enter_hwloop_sub = 0; end else begin : MAIN - if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm && cv32e40p_rvvi_vif.insn == INSTR_EBREAK) is_ebreakm = 1; else is_ebreakm = 0; + if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm && cv32e40p_rvvi_vif.insn == INSTR_EBREAK) is_ebreakm = 1; if (is_irq && cv32e40p_rvvi_vif.insn[6:0] == OPCODE_JAL) begin wait (!is_irq); continue; end if (is_dbg_mode) begin wait (!is_dbg_mode); continue; end `CHECK_N_SAMPLE_CSR_HWLOOP(main); @@ -893,7 +902,7 @@ class uvme_rv32x_hwloop_covg # ( function void final_phase(uvm_phase phase); super.final_phase(phase); if (hwloop_stat_main == hwloop_stat_init && hwloop_stat_sub == hwloop_stat_init) begin - `uvm_info(_header, $sformatf("DEBUG - No prematured hwloops when test done"), UVM_NONE); + `uvm_info(_header, $sformatf("DEBUG - No prematured hwloops when test done"), UVM_DEBUG); end else begin `uvm_error(_header, $sformatf("Detected prematured hwloops when test done. Please debug ... ")); diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv b/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv index 541630f723..01cdaafe8d 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv @@ -363,10 +363,19 @@ class uvme_cv32e40p_cfg_c extends uvma_core_cntrl_cfg_c; } if (cov_model_enabled) { - obi_memory_instr_cfg.cov_model_enabled == 1; - obi_memory_data_cfg.cov_model_enabled == 1; + clknrst_cfg.cov_model_enabled == 1; + interrupt_cfg.cov_model_enabled == 1; + debug_cfg.cov_model_enabled == 1; + obi_memory_instr_cfg.cov_model_enabled == 1; + obi_memory_data_cfg.cov_model_enabled == 1; + } + else { + clknrst_cfg.cov_model_enabled == 0; + interrupt_cfg.cov_model_enabled == 0; + debug_cfg.cov_model_enabled == 0; + obi_memory_instr_cfg.cov_model_enabled == 0; + obi_memory_data_cfg.cov_model_enabled == 0; } - } /** diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv b/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv index 9bb5c82771..3e03846598 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv @@ -50,7 +50,7 @@ package uvme_cv32e40p_pkg; // Constants / Structs / Enums `include "uvme_cv32e40p_constants.sv" - `include "uvme_cv32e40p_param_all_insn.sv" + `include "uvme_cv32e40p_param_all_insn.sv" // fixme: remove this and import package from core-v-cores (e.g cv32e40p_tracer_pkg.sv) `include "uvme_cv32e40p_tdefs.sv" // Objects diff --git a/cv32e40p/regress/cv32e40p_xpulp_rand_tests.yaml b/cv32e40p/regress/cv32e40p_xpulp_rand_tests.yaml index e3a7edf50e..1ed0e23568 100644 --- a/cv32e40p/regress/cv32e40p_xpulp_rand_tests.yaml +++ b/cv32e40p/regress/cv32e40p_xpulp_rand_tests.yaml @@ -82,7 +82,7 @@ tests: - uvmt_cv32e40p_pulp_fpu_zfinx_1cyclat - uvmt_cv32e40p_pulp_fpu_zfinx_2cyclat dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=40000000" num: 10 corev_rand_pulp_mac_instr_test: @@ -191,7 +191,7 @@ tests: - uvmt_cv32e40p_pulp_fpu_zfinx_1cyclat - uvmt_cv32e40p_pulp_fpu_zfinx_2cyclat dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" num: 2 corev_rand_pulp_hwloop_debug_ebreak: @@ -206,7 +206,7 @@ tests: - uvmt_cv32e40p_pulp_fpu_zfinx_1cyclat - uvmt_cv32e40p_pulp_fpu_zfinx_2cyclat dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" test_cfg: debug_ebreak num: 2 @@ -222,7 +222,7 @@ tests: - uvmt_cv32e40p_pulp_fpu_zfinx_1cyclat - uvmt_cv32e40p_pulp_fpu_zfinx_2cyclat dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" test_cfg: debug_single_step_en num: 2 @@ -238,7 +238,7 @@ tests: - uvmt_cv32e40p_pulp_fpu_zfinx_1cyclat - uvmt_cv32e40p_pulp_fpu_zfinx_2cyclat dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=40000000" test_cfg: gen_rand_int num: 5 @@ -254,7 +254,7 @@ tests: - uvmt_cv32e40p_pulp_fpu_zfinx_1cyclat - uvmt_cv32e40p_pulp_fpu_zfinx_2cyclat dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=40000000" test_cfg: insert_illegal_instr num: 2 @@ -270,7 +270,7 @@ tests: - uvmt_cv32e40p_pulp_fpu_zfinx_1cyclat - uvmt_cv32e40p_pulp_fpu_zfinx_2cyclat dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=40000000" num: 2 corev_rand_pulp_hwloop_exception_single_step_debug: @@ -285,7 +285,7 @@ tests: - uvmt_cv32e40p_pulp_fpu_zfinx_1cyclat - uvmt_cv32e40p_pulp_fpu_zfinx_2cyclat dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=40000000" test_cfg: debug_single_step_en num: 1 diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml index f1c294d297..4b1eee87a1 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml @@ -68,12 +68,14 @@ tests: description: corev_rand_interrupt_debug dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_debug CFG_PLUSARGS="+UVM_TIMEOUT=2000000" + num: 1 corev_rand_interrupt_exception: build: uvmt_cv32e40p description: corev_rand_interrupt_exception dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_exception CFG_PLUSARGS="+UVM_TIMEOUT=2000000" + num: 1 corev_rand_interrupt_nested: build: uvmt_cv32e40p @@ -86,13 +88,14 @@ tests: build: uvmt_cv32e40p description: corev_rand_interrupt_wfi dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi CFG_PLUSARGS="+UVM_TIMEOUT=2000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi CFG_PLUSARGS="+UVM_TIMEOUT=15000000" + num: 1 corev_rand_interrupt_wfi_mem_stress: build: uvmt_cv32e40p description: corev_rand_interrupt_wfi_mem_stress dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=2000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=15000000" num: 1 debug_test: @@ -187,14 +190,14 @@ tests: build: uvmt_cv32e40p description: hwloop debug random test dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" corev_rand_pulp_hwloop_debug_ebreak: testname: corev_rand_pulp_hwloop_debug description: hwloop ebreak debug random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" test_cfg: debug_ebreak corev_rand_pulp_hwloop_debug_single_step: @@ -202,15 +205,16 @@ tests: description: hwloop single-step debug random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" test_cfg: debug_single_step_en + num: 1 corev_rand_pulp_hwloop_debug_trigger: testname: corev_rand_pulp_hwloop_debug description: hwloop debug random test with debug trigger on instr addr match build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" test_cfg: debug_trigger_basic corev_rand_pulp_hwloop_debug_trigger_with_ebreak: @@ -218,7 +222,7 @@ tests: description: hwloop debug random test with debug trigger and ebreak build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" test_cfg: debug_trigger_basic,debug_ebreak corev_rand_pulp_hwloop_debug_trigger_with_single_step: @@ -226,15 +230,16 @@ tests: description: hwloop debug random test with debug trigger and single step build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" test_cfg: debug_trigger_basic,debug_single_step_en + num: 1 corev_rand_pulp_hwloop_debug_with_interrupt: testname: corev_rand_pulp_hwloop_debug description: hwloop debug with interrupt random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" test_cfg: gen_rand_int corev_rand_pulp_hwloop_debug_with_int_debug_trigger: @@ -242,7 +247,7 @@ tests: description: hwloop debug with interrupt and debug trigger random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" test_cfg: gen_rand_int,debug_trigger_basic corev_rand_pulp_hwloop_debug_with_int_debug_trigger_single_step: @@ -250,15 +255,16 @@ tests: description: hwloop debug with interrupt, debug trigger and single step random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en + num: 1 corev_rand_pulp_hwloop_interrupt_test: testname: corev_rand_pulp_hwloop_test description: hwloop test with random interrupts build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=40000000" test_cfg: gen_rand_int corev_rand_pulp_hwloop_exception_single_step_debug: @@ -266,15 +272,16 @@ tests: description: hwloop exception test with single step debug build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=3000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" test_cfg: debug_single_step_en + num: 1 corev_rand_pulp_hwloop_exception_debug_trigger: testname: corev_rand_pulp_hwloop_exception description: hwloop exception test with debug trigger build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=3000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" test_cfg: debug_trigger_basic corev_rand_pulp_hwloop_exception_with_int_debug_trigger: @@ -282,6 +289,6 @@ tests: description: hwloop exception test with interrupt and debug trigger build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=3000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" test_cfg: gen_rand_int,debug_trigger_basic diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml index 286e2faf1d..e401209091 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml @@ -51,26 +51,71 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug_single_step_xpulp CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + corev_rand_interrupt: + build: uvmt_cv32e40p + description: corev_rand_interrupt + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + + corev_rand_interrupt_debug: + build: uvmt_cv32e40p + description: corev_rand_interrupt_debug + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + + corev_rand_interrupt_exception: + build: uvmt_cv32e40p + description: corev_rand_interrupt_exception + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_exception CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + corev_rand_interrupt_nested: build: uvmt_cv32e40p description: corev_rand_interrupt_nested dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_nested CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + corev_rand_interrupt_wfi: + build: uvmt_cv32e40p + description: corev_rand_interrupt_wfi + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi CFG_PLUSARGS="+UVM_TIMEOUT=15000000" + corev_rand_interrupt_wfi_mem_stress: build: uvmt_cv32e40p description: corev_rand_interrupt_wfi_mem_stress dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=2000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=15000000" - corev_rand_interrupt: + corev_rand_pulp_hwloop_debug_single_step: + testname: corev_rand_pulp_hwloop_debug + description: hwloop single-step debug random test build: uvmt_cv32e40p - description: corev_rand_interrupt dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: debug_single_step_en - corev_rand_interrupt_wfi_mem_stress: + corev_rand_pulp_hwloop_debug_trigger_with_single_step: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug random test with debug trigger and single step build: uvmt_cv32e40p - description: corev_rand_interrupt_wfi_mem_stress dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: debug_trigger_basic,debug_single_step_en + + corev_rand_pulp_hwloop_debug_with_int_debug_trigger_single_step: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug with interrupt, debug trigger and single step random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en + + corev_rand_pulp_hwloop_exception_single_step_debug: + testname: corev_rand_pulp_hwloop_exception + description: hwloop exception test with single step debug + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: debug_single_step_en + diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml index ca3d2efd71..215d5c1d3a 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml @@ -21,30 +21,12 @@ builds: # List of tests tests: - corev_rand_interrupt_debug: - build: uvmt_cv32e40p - description: corev_rand_interrupt_debug - dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_debug CFG_PLUSARGS="+UVM_TIMEOUT=2000000" - - corev_rand_interrupt_exception: - build: uvmt_cv32e40p - description: corev_rand_interrupt_exception - dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_exception CFG_PLUSARGS="+UVM_TIMEOUT=2000000" - - corev_rand_interrupt_wfi: - build: uvmt_cv32e40p - description: corev_rand_interrupt_wfi - dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi CFG_PLUSARGS="+UVM_TIMEOUT=2000000" - corev_rand_pulp_instr_ebreak_debug_test: testname: corev_rand_pulp_instr_test description: pulp rand test with ebreak debug build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: debug_ebreak corev_rand_pulp_instr_single_step_debug_test: @@ -52,7 +34,7 @@ tests: description: pulp rand test with single-step debug build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: debug_single_step_en corev_rand_pulp_instr_debug_trigger_test: @@ -60,7 +42,7 @@ tests: description: pulp rand test with debug trigger build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: debug_trigger_basic corev_rand_pulp_instr_interrupt_test: @@ -68,37 +50,29 @@ tests: description: pulp instr test with random interrupts build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: gen_rand_int corev_rand_pulp_hwloop_debug: build: uvmt_cv32e40p description: hwloop debug random test dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" corev_rand_pulp_hwloop_debug_ebreak: testname: corev_rand_pulp_hwloop_debug description: hwloop ebreak debug random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" test_cfg: debug_ebreak - corev_rand_pulp_hwloop_debug_single_step: - testname: corev_rand_pulp_hwloop_debug - description: hwloop single-step debug random test - build: uvmt_cv32e40p - dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" - test_cfg: debug_single_step_en - corev_rand_pulp_hwloop_debug_trigger: testname: corev_rand_pulp_hwloop_debug description: hwloop debug random test with debug trigger on instr addr match build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" test_cfg: debug_trigger_basic corev_rand_pulp_hwloop_debug_trigger_with_ebreak: @@ -106,23 +80,15 @@ tests: description: hwloop debug random test with debug trigger and ebreak build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" test_cfg: debug_trigger_basic,debug_ebreak - corev_rand_pulp_hwloop_debug_trigger_with_single_step: - testname: corev_rand_pulp_hwloop_debug - description: hwloop debug random test with debug trigger and single step - build: uvmt_cv32e40p - dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" - test_cfg: debug_trigger_basic,debug_single_step_en - corev_rand_pulp_hwloop_debug_with_interrupt: testname: corev_rand_pulp_hwloop_debug description: hwloop debug with interrupt random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" test_cfg: gen_rand_int corev_rand_pulp_hwloop_debug_with_int_debug_trigger: @@ -130,39 +96,23 @@ tests: description: hwloop debug with interrupt and debug trigger random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" test_cfg: gen_rand_int,debug_trigger_basic - corev_rand_pulp_hwloop_debug_with_int_debug_trigger_single_step: - testname: corev_rand_pulp_hwloop_debug - description: hwloop debug with interrupt, debug trigger and single step random test - build: uvmt_cv32e40p - dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" - test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en - corev_rand_pulp_hwloop_interrupt_test: testname: corev_rand_pulp_hwloop_test description: hwloop test with random interrupts build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=25000000" test_cfg: gen_rand_int - corev_rand_pulp_hwloop_exception_single_step_debug: - testname: corev_rand_pulp_hwloop_exception - description: hwloop exception test with single step debug - build: uvmt_cv32e40p - dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=3000000" - test_cfg: debug_single_step_en - corev_rand_pulp_hwloop_exception_debug_trigger: testname: corev_rand_pulp_hwloop_exception description: hwloop exception test with debug trigger build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=3000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" test_cfg: debug_trigger_basic corev_rand_pulp_hwloop_exception_with_int_debug_trigger: @@ -170,7 +120,7 @@ tests: description: hwloop exception test with interrupt and debug trigger build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=3000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" test_cfg: gen_rand_int,debug_trigger_basic debug_test: diff --git a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml index 289d2032b3..9212df1ff1 100644 --- a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml +++ b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml @@ -28,7 +28,7 @@ tests: build: uvmt_cv32e40p description: corev_rand_pulp_hwloop_test dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=20000000" corev_rand_pulp_instr_test: build: uvmt_cv32e40p @@ -52,7 +52,7 @@ tests: build: uvmt_cv32e40p description: hwloop exception test dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=15000000" corev_rand_pulp_illegal_instr_test: testname: corev_rand_pulp_instr_test @@ -67,7 +67,7 @@ tests: description: hwloop test with illegal instructions build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=25000000" test_cfg: insert_illegal_instr pulp_hardware_loop: diff --git a/cv32e40p/sim/ExternalRepos.mk b/cv32e40p/sim/ExternalRepos.mk index 05e6b6d55b..e4f22c4d8b 100644 --- a/cv32e40p/sim/ExternalRepos.mk +++ b/cv32e40p/sim/ExternalRepos.mk @@ -15,7 +15,7 @@ export SHELL = /bin/bash CV_CORE_REPO ?= https://github.com/openhwgroup/cv32e40p CV_CORE_BRANCH ?= dev -CV_CORE_HASH ?= 3023e88a8ce07c6854267031637403ea6a8061bb +CV_CORE_HASH ?= 1d0ec8d83091bda8e65c36c48614a41065f5fc10 CV_CORE_TAG ?= none # The CV_CORE_HASH above points to version of the RTL that is newer. diff --git a/cv32e40p/tb/uvmt/imperas_dv.flist b/cv32e40p/tb/uvmt/imperas_dv.flist index d404461e73..735e764513 100644 --- a/cv32e40p/tb/uvmt/imperas_dv.flist +++ b/cv32e40p/tb/uvmt/imperas_dv.flist @@ -23,9 +23,9 @@ +incdir+${IMPERAS_HOME} +incdir+${IMPERAS_HOME}/ImpProprietary/include/host -+incdir+${IMPERAS_HOME}/ImpProprietary/source/host/riscvISACOV/source ++incdir+${IMPERAS_HOME}/ImpProprietary/source/host/CV32E40Pv2_riscvISACOV/source -${TBSRC_HOME}/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh +//${TBSRC_HOME}/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh -f ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/rvvi.f -f ${IMPERAS_HOME}/ImpProprietary/source/host/idv/idv.f diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_debug_assert.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_debug_assert.sv index c62704a6fa..3ffab6661a 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_debug_assert.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_debug_assert.sv @@ -169,7 +169,7 @@ module uvmt_cv32e40p_debug_assert // Trigger match results in debug mode property p_trigger_match; - cov_assert_if.trigger_match_i ##0 cov_assert_if.tdata1[2] ##0 !cov_assert_if.debug_mode_q ##0 cov_assert_if.id_stage_instr_valid_i ##0 cov_assert_if.is_decoding + cov_assert_if.trigger_match_i ##0 cov_assert_if.tdata1[2] ##0 !cov_assert_if.debug_mode_q ##0 cov_assert_if.id_stage_instr_valid_i |-> decode_valid [->2] ##0 (cov_assert_if.debug_mode_q && (cov_assert_if.dcsr_q[8:6]=== cv32e40p_pkg::DBG_CAUSE_TRIGGER) && (cov_assert_if.depc_q == tdata2_at_entry)) && (cov_assert_if.id_stage_pc == halt_addr_at_entry); @@ -460,18 +460,17 @@ module uvmt_cv32e40p_debug_assert debug_cause_pri <= 3'b000; end else begin // Debug evaluated in decode state with valid instructions only - //if(cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE & !cov_assert_if.debug_mode_q) begin - if((cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE) || (cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE_HWLOOP)) begin - if(cov_assert_if.is_decoding & cov_assert_if.id_stage_instr_valid_i) begin + if((cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE || cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE_HWLOOP) & !cov_assert_if.debug_mode_q) begin + if(cov_assert_if.id_stage_instr_valid_i) begin if(cov_assert_if.trigger_match_i) debug_cause_pri <= 3'b010; - else if((cov_assert_if.dcsr_q[15]) & (cov_assert_if.is_ebreak | cov_assert_if.is_cebreak)) + else if(cov_assert_if.is_decoding & (cov_assert_if.dcsr_q[15]) & (cov_assert_if.is_ebreak | cov_assert_if.is_cebreak)) debug_cause_pri <= 3'b001; else if(cov_assert_if.debug_req_i) debug_cause_pri <= 3'b011; - else if(cov_assert_if.dcsr_q[2]) + else if(cov_assert_if.is_decoding & cov_assert_if.dcsr_q[2]) debug_cause_pri <= 3'b100; - else + else if(cov_assert_if.is_decoding) debug_cause_pri <= 3'b000; end diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_dut_wrap.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_dut_wrap.sv index 212676dcbd..fc232c489a 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_dut_wrap.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_dut_wrap.sv @@ -131,7 +131,9 @@ module uvmt_cv32e40p_dut_wrap //always @(irq_agt) $display("%m: @%0t; irq_agt = %8x", $time, irq_agt); assign irq = interrupt_if.irq_drv; - always @(irq) $display("%m: @%0t; irq = %8x", $time, irq); + always @(irq) begin + `uvm_info("uvmt_cv32e40p_dut_wrap", $sformatf("irq = %8x", irq), UVM_HIGH); + end // ------------------------------------------------------------- // Instantiate the Core and optional FPU plus logger and tracers diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv index 7c9716e8a2..8db6c816f2 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv @@ -452,11 +452,12 @@ module uvmt_cv32e40p_imperas_dv_wrap task ref_init; string test_program_elf; reg [31:0] hart_id; + bit [64:0] mtvec_addr_i; // Select processor name void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "CV32E40P")); - // Worst case propagation of events 14 retirements (14 due to long fpu multicycle instr) - void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 14)); + // Worst case propagation of events 19+2 retirements. (19 due to long fpu multicycle instr that observed meantime. +2 is buffer) + void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 21)); // Redirect stdout to parent systemverilog simulator void'(rvviRefConfigSetInt(IDV_CONFIG_REDIRECT_STDOUT, RVVI_TRUE)); @@ -525,6 +526,11 @@ module uvmt_cv32e40p_imperas_dv_wrap // Debug rvviRefNetGroupSet(rvviRefNetIndexGet("haltreq"), 4); + // MTVEC CSR initialization based on TB configuration + if ($value$plusargs("mtvec_addr=%0x", mtvec_addr_i)) begin + rvviRefCsrSet(hart_id, `CSR_MTVEC_ADDR, mtvec_addr_i); + end + void'(rvviRefMemorySetVolatile('h15001000, 'h15001007)); //TODO: deal with int return value endtask // ref_init endmodule : uvmt_cv32e40p_imperas_dv_wrap diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh index 84ae410b71..b82a2c2ddd 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh @@ -17,6 +17,9 @@ `define COVER_RVVI_METRICS `ifdef FPU + `define COVER_CSR_FCSR + `define COVER_CSR_FFLAGS + `define COVER_CSR_FRM `ifndef ZFINX `define COVER_RV32F `define COVER_RV32ZCF diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_hwloop_debug/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_hwloop_debug/corev-dv.yaml index 91b5f89447..e5dceef78a 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_hwloop_debug/corev-dv.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_hwloop_debug/corev-dv.yaml @@ -15,7 +15,7 @@ plusargs: > +rand_directed_instr_0=cv32e40p_xpulp_hwloop_base_stream,1 +rand_directed_instr_1=cv32e40p_xpulp_hwloop_base_stream,1 +rand_directed_instr_2=cv32e40p_xpulp_short_hwloop_stream,1 - +rand_directed_instr_3=cv32e40p_xpulp_long_hwloop_stream,1 + +rand_directed_instr_3=cv32e40p_xpulp_short_hwloop_stream,1 +rand_directed_instr_4=cv32e40p_xpulp_hwloop_isa_stress_stream,1 +rand_directed_instr_5=cv32e40p_xpulp_hwloop_exception,1 +no_fence=1 diff --git a/cv32e40p/tests/test_cfg/disable_all_trn_logs.yaml b/cv32e40p/tests/test_cfg/disable_all_trn_logs.yaml new file mode 100644 index 0000000000..3a3febb1e4 --- /dev/null +++ b/cv32e40p/tests/test_cfg/disable_all_trn_logs.yaml @@ -0,0 +1,5 @@ +name: disable_all_trn_logs +description: > + Disable All Transaction Logs +plusargs: > + +disable_all_trn_logs diff --git a/cv32e40p/tests/uvmt/base-tests/uvmt_cv32e40p_base_test.sv b/cv32e40p/tests/uvmt/base-tests/uvmt_cv32e40p_base_test.sv index e70d5201dd..6e696826c2 100644 --- a/cv32e40p/tests/uvmt/base-tests/uvmt_cv32e40p_base_test.sv +++ b/cv32e40p/tests/uvmt/base-tests/uvmt_cv32e40p_base_test.sv @@ -48,12 +48,15 @@ class uvmt_cv32e40p_base_test_c extends uvm_test; // Default sequences rand uvme_cv32e40p_reset_vseq_c reset_vseq; + // knob to enable features + bit cov_model_enabled; // enable functional coverage `uvm_component_utils_begin(uvmt_cv32e40p_base_test_c) - `uvm_field_object(test_cfg , UVM_DEFAULT) - `uvm_field_object(test_randvars , UVM_DEFAULT) - `uvm_field_object(env_cfg , UVM_DEFAULT) - `uvm_field_object(env_cntxt , UVM_DEFAULT) + `uvm_field_object(test_cfg , UVM_DEFAULT) + `uvm_field_object(test_randvars , UVM_DEFAULT) + `uvm_field_object(env_cfg , UVM_DEFAULT) + `uvm_field_object(env_cntxt , UVM_DEFAULT) + `uvm_field_int (cov_model_enabled , UVM_DEFAULT) `uvm_component_utils_end @@ -63,6 +66,10 @@ class uvmt_cv32e40p_base_test_c extends uvm_test; env_cfg.trn_log_enabled == 1; } + constraint c_cov_model_enabled { + env_cfg.cov_model_enabled == cov_model_enabled; + } + constraint test_type_default_cons { soft test_cfg.tpt == NO_TEST_PROGRAM; } diff --git a/cv32e40p/tests/uvmt/compliance-tests/uvmt_cv32e40p_firmware_test.sv b/cv32e40p/tests/uvmt/compliance-tests/uvmt_cv32e40p_firmware_test.sv index 00a1fc4838..8876d1c1c6 100644 --- a/cv32e40p/tests/uvmt/compliance-tests/uvmt_cv32e40p_firmware_test.sv +++ b/cv32e40p/tests/uvmt/compliance-tests/uvmt_cv32e40p_firmware_test.sv @@ -35,10 +35,22 @@ */ class uvmt_cv32e40p_firmware_test_c extends uvmt_cv32e40p_base_test_c; + bit disable_all_trn_logs; + constraint env_cfg_cons { env_cfg.enabled == 1; env_cfg.is_active == UVM_ACTIVE; - env_cfg.trn_log_enabled == 1; + if (disable_all_trn_logs) { + env_cfg.trn_log_enabled == 0; + env_cfg.clknrst_cfg.trn_log_enabled == 0; + env_cfg.interrupt_cfg.trn_log_enabled == 0; + env_cfg.debug_cfg.trn_log_enabled == 0; + env_cfg.obi_memory_instr_cfg.trn_log_enabled == 0; + env_cfg.obi_memory_data_cfg.trn_log_enabled == 0; + env_cfg.rvfi_cfg.trn_log_enabled == 0; + } else { + env_cfg.trn_log_enabled == 1; + } } `uvm_component_utils_begin(uvmt_cv32e40p_firmware_test_c) `uvm_object_utils_end @@ -86,7 +98,11 @@ function uvmt_cv32e40p_firmware_test_c::new(string name="uvmt_cv32e40p_firmware_ super.new(name, parent); if ($test$plusargs("gen_reduced_rand_dbg_req")) begin - uvme_cv32e40p_random_debug_c::type_id::set_type_override(uvme_cv32e40p_reduced_rand_debug_req_c::get_type()); + uvme_cv32e40p_random_debug_c::type_id::set_type_override(uvme_cv32e40p_reduced_rand_debug_req_c::get_type()); + end + disable_all_trn_logs = 0; + if ($test$plusargs("disable_all_trn_logs")) begin + disable_all_trn_logs = 1; end `uvm_info("TEST", "This is the FIRMWARE TEST", UVM_NONE) diff --git a/mk/uvmt/uvmt.mk b/mk/uvmt/uvmt.mk index 6364900ec5..5a29233170 100644 --- a/mk/uvmt/uvmt.mk +++ b/mk/uvmt/uvmt.mk @@ -93,6 +93,9 @@ GEN_START_INDEX ?= 0 GEN_NUM_TESTS ?= 1 export RUN_INDEX ?= 0 +# Generate Core Trace logs +ENABLE_TRACE_LOG ?= YES + # Common test runtime plusargs from external file, used as test-configuration # Test Name with test-configuration TEST_RUN_NAME = $(if $(TEST_CFG_FILE_NAME),$(TEST)_$(TEST_CFG_FILE_NAME),$(TEST)) diff --git a/mk/uvmt/vcs.mk b/mk/uvmt/vcs.mk index 28b42f6654..89b0179312 100644 --- a/mk/uvmt/vcs.mk +++ b/mk/uvmt/vcs.mk @@ -60,7 +60,7 @@ VCS_COMP_FLAGS ?= -lca -sverilog \ +define+CV32E40P_RVFI \ -assert svaext -ignore unique_checks -full64 -licwait 20 VCS_GUI ?= -VCS_RUN_COV = -cm line+cond+tgl+fsm+branch+assert -cm_dir $(MAKECMDGOALS).vdb +VCS_RUN_COV = -cm line+cond+tgl+fsm+branch+assert -cm_dir $(MAKECMDGOALS).vdb +uvm_set_config_int=uvm_test_top,cov_model_enabled,1 # Necessary libraries for the PMA generator class VCS_PMA_INC += +incdir+$(TBSRC_HOME)/uvmt \ @@ -155,7 +155,12 @@ endif ################################################################################ VCS_FILE_LIST ?= -f $(DV_UVMT_PATH)/uvmt_$(CV_CORE_LC).flist -VCS_USER_COMPILE_ARGS += +define+$(CV_CORE_UC)_TRACE_EXECUTION + +ifeq ($(call IS_YES,$(ENABLE_TRACE_LOG)),YES) + VCS_USER_COMPILE_ARGS += +define+$(CV_CORE_UC)_TRACE_EXECUTION + VCS_USER_COMPILE_ARGS += +define+$(CV_CORE_UC)_RVFI_TRACE_EXECUTION +endif + ifeq ($(call IS_YES,$(USE_ISS)),YES) VCS_USER_COMPILE_ARGS += +define+USE_ISS VCS_USER_COMPILE_ARGS += +define+USE_IMPERASDV diff --git a/mk/uvmt/vsim.mk b/mk/uvmt/vsim.mk index b2fb2dce93..d7a6370ddb 100644 --- a/mk/uvmt/vsim.mk +++ b/mk/uvmt/vsim.mk @@ -47,9 +47,9 @@ VOPT_COV ?= +cover=bcsetf+$(RTLSRC_VLOG_CORE_TOP). else VOPT_COV ?= +cover=setf+$(RTLSRC_VLOG_TB_TOP). endif -VSIM_COV ?= -coverage +VSIM_COV ?= -coverage +uvm_set_config_int=uvm_test_top,cov_model_enabled,1 VOPT_WAVES_ADV_DEBUG ?= -designfile design.bin -VSIM_WAVES_ADV_DEBUG ?= -qwavedb=+signal+assertion+ignoretxntime+msgmode=both +VSIM_WAVES_ADV_DEBUG ?= -qwavedb=+signal+class+classmemory+assertion+ignoretxntime+msgmode=both VSIM_WAVES_DO ?= $(VSIM_SCRIPT_DIR)/waves.tcl # Common QUIET flag defaults to -quiet unless VERBOSE is set @@ -133,9 +133,13 @@ VLOG_FILE_LIST = -f $(DV_UVMT_PATH)/uvmt_$(CV_CORE_LC).flist VLOG_FLAGS += $(DPILIB_VLOG_OPT) # Add the ISS to compilation -VLOG_FLAGS += "+define+$(CV_CORE_UC)_TRACE_EXECUTION" VLOG_FLAGS += "+define+$(CV_CORE_UC)_RVFI" -VLOG_FLAGS += "+define+$(CV_CORE_UC)_RVFI_TRACE_EXECUTION" + +ifeq ($(call IS_YES,$(ENABLE_TRACE_LOG)),YES) + VLOG_FLAGS += "+define+$(CV_CORE_UC)_TRACE_EXECUTION" + VLOG_FLAGS += "+define+$(CV_CORE_UC)_RVFI_TRACE_EXECUTION" +endif + VLOG_FLAGS += "+define+$(CV_CORE_UC)_CORE_LOG" VLOG_FLAGS += "+define+UVM" ifeq ($(call IS_YES,$(USE_ISS)),YES) @@ -209,7 +213,7 @@ run: VSIM_FLAGS += -modelsimini modelsim.ini endif ################################################################################ -# Coverage database generation +# code coverage and functional coverage enablement ifeq ($(call IS_YES,$(COV)),YES) VOPT_FLAGS += $(VOPT_COV) VSIM_FLAGS += $(VSIM_COV) diff --git a/mk/uvmt/xrun.mk b/mk/uvmt/xrun.mk index 97e39c2e93..3d58b5be99 100644 --- a/mk/uvmt/xrun.mk +++ b/mk/uvmt/xrun.mk @@ -64,7 +64,8 @@ XRUN_SINGLE_STEP ?= XRUN_ELAB_COV = -covdut uvmt_$(CV_CORE_LC)_tb -coverage b:e:f:u XRUN_ELAB_COVFILE = -covfile $(abspath $(MAKE_PATH)/../tools/xrun/covfile.tcl) XRUN_RUN_COV = -covscope uvmt_$(CV_CORE_LC)_tb \ - -nowarn CGDEFN + -nowarn CGDEFN \ + +uvm_set_config_int=uvm_test_top,cov_model_enabled,1 XRUN_RUN_BASE_FLAGS += -sv_lib $(DPI_DASM_LIB) XRUN_RUN_BASE_FLAGS += -sv_lib $(abspath $(SVLIB_LIB)) @@ -121,9 +122,9 @@ endif ################################################################################ # Waveform (post-process) command line ifeq ($(call IS_YES,$(ADV_DEBUG)),YES) -WAVES_CMD = cd $(SIM_RUN_RESULTS) && $(INDAGO) -db ida.db +WAVES_CMD = cd $(SIM_RUN_RESULTS) && $(INDAGO) -db ida.db & else -WAVES_CMD = cd $(SIM_RUN_RESULTS) && $(SIMVISION) waves.shm +WAVES_CMD = cd $(SIM_RUN_RESULTS) && $(SIMVISION) waves.shm & endif XRUN_USER_COMPILE_ARGS += $(USER_COMPILE_FLAGS) @@ -179,9 +180,13 @@ endif XRUN_UVM_MACROS_INC_FILE = $(DV_UVMT_PATH)/uvmt_$(CV_CORE_LC)_uvm_macros_inc.sv XRUN_FILE_LIST ?= -f $(DV_UVMT_PATH)/uvmt_$(CV_CORE_LC).flist -XRUN_USER_COMPILE_ARGS += +define+$(CV_CORE_UC)_TRACE_EXECUTION XRUN_USER_COMPILE_ARGS += +define+$(CV_CORE_UC)_RVFI -XRUN_USER_COMPILE_ARGS += +define+$(CV_CORE_UC)_RVFI_TRACE_EXECUTION + +ifeq ($(call IS_YES,$(ENABLE_TRACE_LOG)),YES) + XRUN_USER_COMPILE_ARGS += +define+$(CV_CORE_UC)_TRACE_EXECUTION + XRUN_USER_COMPILE_ARGS += +define+$(CV_CORE_UC)_RVFI_TRACE_EXECUTION +endif + XRUN_USER_COMPILE_ARGS += +define+$(CV_CORE_UC)_CORE_LOG XRUN_USER_COMPILE_ARGS += +define+UVM ifeq ($(call IS_YES,$(USE_ISS)),YES)